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Merge branch 'devel'
[deliverable/linux.git] / drivers / scsi / lpfc / lpfc_sli4.h
CommitLineData
da0436e9
JS		 1/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
792581de 4 * Copyright (C) 2009-2011 Emulex. All rights reserved. *
da0436e9
JS		 5 * EMULEX and SLI are trademarks of Emulex. *
6 * www.emulex.com *
7 * *
8 * This program is free software; you can redistribute it and/or *
9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
19 *******************************************************************/
20
21#define LPFC_ACTIVE_MBOX_WAIT_CNT 100
5af5eee7
JS		 22#define LPFC_XRI_EXCH_BUSY_WAIT_TMO 10000
23#define LPFC_XRI_EXCH_BUSY_WAIT_T1 10
24#define LPFC_XRI_EXCH_BUSY_WAIT_T2 30000
da0436e9 25#define LPFC_RELEASE_NOTIFICATION_INTERVAL 32
da0436e9 26#define LPFC_RPI_LOW_WATER_MARK 10
ecfd03c6 27
a93ff37a
JS		 28#define LPFC_UNREG_FCF 1
29#define LPFC_SKIP_UNREG_FCF 0
30
ecfd03c6
JS		 31/* Amount of time in seconds for waiting FCF rediscovery to complete */
32#define LPFC_FCF_REDISCOVER_WAIT_TMO 2000 /* msec */
33
da0436e9
JS		 34/* Number of SGL entries can be posted in a 4KB nonembedded mbox command */
35#define LPFC_NEMBED_MBOX_SGL_CNT 254
36
37/* Multi-queue arrangement for fast-path FCP work queues */
38#define LPFC_FN_EQN_MAX 8
39#define LPFC_SP_EQN_DEF 1
def9c7a9 40#define LPFC_FP_EQN_DEF 4
da0436e9
JS		 41#define LPFC_FP_EQN_MIN 1
42#define LPFC_FP_EQN_MAX (LPFC_FN_EQN_MAX - LPFC_SP_EQN_DEF)
43
44#define LPFC_FN_WQN_MAX 32
45#define LPFC_SP_WQN_DEF 1
46#define LPFC_FP_WQN_DEF 4
47#define LPFC_FP_WQN_MIN 1
48#define LPFC_FP_WQN_MAX (LPFC_FN_WQN_MAX - LPFC_SP_WQN_DEF)
49
50/*
51 * Provide the default FCF Record attributes used by the driver
52 * when nonFIP mode is configured and there is no other default
53 * FCF Record attributes.
54 */
55#define LPFC_FCOE_FCF_DEF_INDEX 0
56#define LPFC_FCOE_FCF_GET_FIRST 0xFFFF
57#define LPFC_FCOE_FCF_NEXT_NONE 0xFFFF
58
dbb6b3ab
JS		 59#define LPFC_FCOE_NULL_VID 0xFFF
60#define LPFC_FCOE_IGNORE_VID 0xFFFF
61
da0436e9
JS		 62/* First 3 bytes of default FCF MAC is specified by FC_MAP */
63#define LPFC_FCOE_FCF_MAC3 0xFF
64#define LPFC_FCOE_FCF_MAC4 0xFF
65#define LPFC_FCOE_FCF_MAC5 0xFE
66#define LPFC_FCOE_FCF_MAP0 0x0E
67#define LPFC_FCOE_FCF_MAP1 0xFC
68#define LPFC_FCOE_FCF_MAP2 0x00
98fc5dd9 69#define LPFC_FCOE_MAX_RCV_SIZE 0x800
da0436e9
JS		 70#define LPFC_FCOE_FKA_ADV_PER 0
71#define LPFC_FCOE_FIP_PRIORITY 0x80
72
6669f9bb
JS		 73#define sli4_sid_from_fc_hdr(fc_hdr) \
74 ((fc_hdr)->fh_s_id[0] << 16 | \
75 (fc_hdr)->fh_s_id[1] << 8 | \
76 (fc_hdr)->fh_s_id[2])
77
939723a4
JS		 78#define sli4_did_from_fc_hdr(fc_hdr) \
79 ((fc_hdr)->fh_d_id[0] << 16 | \
80 (fc_hdr)->fh_d_id[1] << 8 | \
81 (fc_hdr)->fh_d_id[2])
82
5ffc266e
JS		 83#define sli4_fctl_from_fc_hdr(fc_hdr) \
84 ((fc_hdr)->fh_f_ctl[0] << 16 | \
85 (fc_hdr)->fh_f_ctl[1] << 8 | \
86 (fc_hdr)->fh_f_ctl[2])
87
939723a4
JS		 88#define sli4_type_from_fc_hdr(fc_hdr) \
89 ((fc_hdr)->fh_type)
90
88a2cfbb
JS		 91#define LPFC_FW_RESET_MAXIMUM_WAIT_10MS_CNT 12000
92
da0436e9
JS		 93enum lpfc_sli4_queue_type {
94 LPFC_EQ,
95 LPFC_GCQ,
96 LPFC_MCQ,
97 LPFC_WCQ,
98 LPFC_RCQ,
99 LPFC_MQ,
100 LPFC_WQ,
101 LPFC_HRQ,
102 LPFC_DRQ
103};
104
105/* The queue sub-type defines the functional purpose of the queue */
106enum lpfc_sli4_queue_subtype {
107 LPFC_NONE,
108 LPFC_MBOX,
109 LPFC_FCP,
110 LPFC_ELS,
111 LPFC_USOL
112};
113
114union sli4_qe {
115 void *address;
116 struct lpfc_eqe *eqe;
117 struct lpfc_cqe *cqe;
118 struct lpfc_mcqe *mcqe;
119 struct lpfc_wcqe_complete *wcqe_complete;
120 struct lpfc_wcqe_release *wcqe_release;
121 struct sli4_wcqe_xri_aborted *wcqe_xri_aborted;
122 struct lpfc_rcqe_complete *rcqe_complete;
123 struct lpfc_mqe *mqe;
124 union lpfc_wqe *wqe;
125 struct lpfc_rqe *rqe;
126};
127
128struct lpfc_queue {
129 struct list_head list;
130 enum lpfc_sli4_queue_type type;
131 enum lpfc_sli4_queue_subtype subtype;
132 struct lpfc_hba *phba;
133 struct list_head child_list;
134 uint32_t entry_count; /* Number of entries to support on the queue */
135 uint32_t entry_size; /* Size of each queue entry. */
73d91e50
JS		 136 uint32_t entry_repost; /* Count of entries before doorbell is rung */
137#define LPFC_QUEUE_MIN_REPOST 8
da0436e9 138 uint32_t queue_id; /* Queue ID assigned by the hardware */
2a622bfb 139 uint32_t assoc_qid; /* Queue ID associated with, for CQ/WQ/MQ */
da0436e9
JS		 140 struct list_head page_list;
141 uint32_t page_count; /* Number of pages allocated for this queue */
da0436e9
JS		 142 uint32_t host_index; /* The host's index for putting or getting */
143 uint32_t hba_index; /* The last known hba index for get or put */
144 union sli4_qe qe[1]; /* array to index entries (must be last) */
145};
146
da0436e9
JS		 147struct lpfc_sli4_link {
148 uint8_t speed;
149 uint8_t duplex;
150 uint8_t status;
70f3c073
JS		 151 uint8_t type;
152 uint8_t number;
da0436e9 153 uint8_t fault;
65467b6b 154 uint16_t logical_speed;
70f3c073 155 uint16_t topology;
da0436e9
JS		 156};
157
ecfd03c6
JS		 158struct lpfc_fcf_rec {
159 uint8_t fabric_name[8];
160 uint8_t switch_name[8];
da0436e9
JS		 161 uint8_t mac_addr[6];
162 uint16_t fcf_indx;
ecfd03c6
JS		 163 uint32_t priority;
164 uint16_t vlan_id;
165 uint32_t addr_mode;
166 uint32_t flag;
167#define BOOT_ENABLE 0x01
168#define RECORD_VALID 0x02
169};
170
7d791df7
JS		 171struct lpfc_fcf_pri_rec {
172 uint16_t fcf_index;
173#define LPFC_FCF_ON_PRI_LIST 0x0001
174#define LPFC_FCF_FLOGI_FAILED 0x0002
175 uint16_t flag;
176 uint32_t priority;
177};
178
179struct lpfc_fcf_pri {
180 struct list_head list;
181 struct lpfc_fcf_pri_rec fcf_rec;
182};
183
184/*
185 * Maximum FCF table index, it is for driver internal book keeping, it
186 * just needs to be no less than the supported HBA's FCF table size.
187 */
188#define LPFC_SLI4_FCF_TBL_INDX_MAX 32
189
ecfd03c6 190struct lpfc_fcf {
da0436e9
JS		 191 uint16_t fcfi;
192 uint32_t fcf_flag;
193#define FCF_AVAILABLE 0x01 /* FCF available for discovery */
194#define FCF_REGISTERED 0x02 /* FCF registered with FW */
ecfd03c6
JS		 195#define FCF_SCAN_DONE 0x04 /* FCF table scan done */
196#define FCF_IN_USE 0x08 /* Atleast one discovery completed */
0c9ab6f5
JS		 197#define FCF_INIT_DISC 0x10 /* Initial FCF discovery */
198#define FCF_DEAD_DISC 0x20 /* FCF DEAD fast FCF failover discovery */
199#define FCF_ACVL_DISC 0x40 /* All CVL fast FCF failover discovery */
200#define FCF_DISCOVERY (FCF_INIT_DISC | FCF_DEAD_DISC | FCF_ACVL_DISC)
201#define FCF_REDISC_PEND 0x80 /* FCF rediscovery pending */
202#define FCF_REDISC_EVT 0x100 /* FCF rediscovery event to worker thread */
203#define FCF_REDISC_FOV 0x200 /* Post FCF rediscovery fast failover */
a93ff37a 204#define FCF_REDISC_PROG (FCF_REDISC_PEND | FCF_REDISC_EVT)
da0436e9 205 uint32_t addr_mode;
999d813f 206 uint32_t eligible_fcf_cnt;
ecfd03c6
JS		 207 struct lpfc_fcf_rec current_rec;
208 struct lpfc_fcf_rec failover_rec;
7d791df7
JS		 209 struct list_head fcf_pri_list;
210 struct lpfc_fcf_pri fcf_pri[LPFC_SLI4_FCF_TBL_INDX_MAX];
211 uint32_t current_fcf_scan_pri;
ecfd03c6 212 struct timer_list redisc_wait;
0c9ab6f5 213 unsigned long *fcf_rr_bmask; /* Eligible FCF indexes for RR failover */
da0436e9
JS		 214};
215
0c9ab6f5 216
da0436e9
JS		 217#define LPFC_REGION23_SIGNATURE "RG23"
218#define LPFC_REGION23_VERSION 1
219#define LPFC_REGION23_LAST_REC 0xff
a0c87cbd
JS		 220#define DRIVER_SPECIFIC_TYPE 0xA2
221#define LINUX_DRIVER_ID 0x20
222#define PORT_STE_TYPE 0x1
223
da0436e9
JS		 224struct lpfc_fip_param_hdr {
225 uint8_t type;
226#define FCOE_PARAM_TYPE 0xA0
227 uint8_t length;
228#define FCOE_PARAM_LENGTH 2
229 uint8_t parm_version;
230#define FIPP_VERSION 0x01
231 uint8_t parm_flags;
232#define lpfc_fip_param_hdr_fipp_mode_SHIFT 6
233#define lpfc_fip_param_hdr_fipp_mode_MASK 0x3
234#define lpfc_fip_param_hdr_fipp_mode_WORD parm_flags
6a9c52cf 235#define FIPP_MODE_ON 0x1
da0436e9
JS		 236#define FIPP_MODE_OFF 0x0
237#define FIPP_VLAN_VALID 0x1
238};
239
240struct lpfc_fcoe_params {
241 uint8_t fc_map[3];
242 uint8_t reserved1;
243 uint16_t vlan_tag;
244 uint8_t reserved[2];
245};
246
247struct lpfc_fcf_conn_hdr {
248 uint8_t type;
249#define FCOE_CONN_TBL_TYPE 0xA1
250 uint8_t length; /* words */
251 uint8_t reserved[2];
252};
253
254struct lpfc_fcf_conn_rec {
255 uint16_t flags;
256#define FCFCNCT_VALID 0x0001
257#define FCFCNCT_BOOT 0x0002
258#define FCFCNCT_PRIMARY 0x0004 /* if not set, Secondary */
259#define FCFCNCT_FBNM_VALID 0x0008
260#define FCFCNCT_SWNM_VALID 0x0010
261#define FCFCNCT_VLAN_VALID 0x0020
262#define FCFCNCT_AM_VALID 0x0040
263#define FCFCNCT_AM_PREFERRED 0x0080 /* if not set, AM Required */
264#define FCFCNCT_AM_SPMA 0x0100 /* if not set, FPMA */
265
266 uint16_t vlan_tag;
267 uint8_t fabric_name[8];
268 uint8_t switch_name[8];
269};
270
271struct lpfc_fcf_conn_entry {
272 struct list_head list;
273 struct lpfc_fcf_conn_rec conn_rec;
274};
275
276/*
277 * Define the host's bootstrap mailbox. This structure contains
278 * the member attributes needed to create, use, and destroy the
279 * bootstrap mailbox region.
280 *
281 * The macro definitions for the bmbx data structure are defined
282 * in lpfc_hw4.h with the register definition.
283 */
284struct lpfc_bmbx {
285 struct lpfc_dmabuf *dmabuf;
286 struct dma_address dma_address;
287 void *avirt;
288 dma_addr_t aphys;
289 uint32_t bmbx_size;
290};
291
292#define LPFC_EQE_SIZE LPFC_EQE_SIZE_4
293
294#define LPFC_EQE_SIZE_4B 4
295#define LPFC_EQE_SIZE_16B 16
296#define LPFC_CQE_SIZE 16
297#define LPFC_WQE_SIZE 64
298#define LPFC_MQE_SIZE 256
299#define LPFC_RQE_SIZE 8
300
301#define LPFC_EQE_DEF_COUNT 1024
ff78d8f9 302#define LPFC_CQE_DEF_COUNT 1024
f1126688 303#define LPFC_WQE_DEF_COUNT 256
da0436e9
JS		 304#define LPFC_MQE_DEF_COUNT 16
305#define LPFC_RQE_DEF_COUNT 512
306
307#define LPFC_QUEUE_NOARM false
308#define LPFC_QUEUE_REARM true
309
310
311/*
312 * SLI4 CT field defines
313 */
314#define SLI4_CT_RPI 0
315#define SLI4_CT_VPI 1
316#define SLI4_CT_VFI 2
317#define SLI4_CT_FCFI 3
318
28baac74
JS		 319#define LPFC_SLI4_FL1_MAX_SEGMENT_SIZE 0x10000
320#define LPFC_SLI4_FL1_MAX_BUF_SIZE 0X2000
321#define LPFC_SLI4_MIN_BUF_SIZE 0x400
322#define LPFC_SLI4_MAX_BUF_SIZE 0x20000
da0436e9
JS		 323
324/*
325 * SLI4 specific data structures
326 */
327struct lpfc_max_cfg_param {
328 uint16_t max_xri;
329 uint16_t xri_base;
330 uint16_t xri_used;
331 uint16_t max_rpi;
332 uint16_t rpi_base;
333 uint16_t rpi_used;
334 uint16_t max_vpi;
335 uint16_t vpi_base;
336 uint16_t vpi_used;
337 uint16_t max_vfi;
338 uint16_t vfi_base;
339 uint16_t vfi_used;
340 uint16_t max_fcfi;
da0436e9
JS		 341 uint16_t fcfi_used;
342 uint16_t max_eq;
343 uint16_t max_rq;
344 uint16_t max_cq;
345 uint16_t max_wq;
346};
347
348struct lpfc_hba;
349/* SLI4 HBA multi-fcp queue handler struct */
350struct lpfc_fcp_eq_hdl {
351 uint32_t idx;
352 struct lpfc_hba *phba;
353};
354
28baac74
JS		 355/* Port Capabilities for SLI4 Parameters */
356struct lpfc_pc_sli4_params {
357 uint32_t supported;
358 uint32_t if_type;
359 uint32_t sli_rev;
360 uint32_t sli_family;
361 uint32_t featurelevel_1;
362 uint32_t featurelevel_2;
363 uint32_t proto_types;
364#define LPFC_SLI4_PROTO_FCOE 0x0000001
365#define LPFC_SLI4_PROTO_FC 0x0000002
366#define LPFC_SLI4_PROTO_NIC 0x0000004
367#define LPFC_SLI4_PROTO_ISCSI 0x0000008
368#define LPFC_SLI4_PROTO_RDMA 0x0000010
369 uint32_t sge_supp_len;
370 uint32_t if_page_sz;
371 uint32_t rq_db_window;
372 uint32_t loopbk_scope;
373 uint32_t eq_pages_max;
374 uint32_t eqe_size;
375 uint32_t cq_pages_max;
376 uint32_t cqe_size;
377 uint32_t mq_pages_max;
378 uint32_t mqe_size;
379 uint32_t mq_elem_cnt;
380 uint32_t wq_pages_max;
381 uint32_t wqe_size;
382 uint32_t rq_pages_max;
383 uint32_t rqe_size;
384 uint32_t hdr_pages_max;
385 uint32_t hdr_size;
386 uint32_t hdr_pp_align;
387 uint32_t sgl_pages_max;
388 uint32_t sgl_pp_align;
fedd3b7b
JS		 389 uint8_t cqv;
390 uint8_t mqv;
391 uint8_t wqv;
392 uint8_t rqv;
28baac74
JS		 393};
394
912e3acd
JS		 395struct lpfc_iov {
396 uint32_t pf_number;
397 uint32_t vf_number;
398};
399
cd1c8301
JS		 400struct lpfc_sli4_lnk_info {
401 uint8_t lnk_dv;
402#define LPFC_LNK_DAT_INVAL 0
403#define LPFC_LNK_DAT_VAL 1
404 uint8_t lnk_tp;
405#define LPFC_LNK_GE 0x0 /* FCoE */
406#define LPFC_LNK_FC 0x1 /* FC */
407 uint8_t lnk_no;
408};
409
da0436e9
JS		 410/* SLI4 HBA data structure entries */
411struct lpfc_sli4_hba {
412 void __iomem *conf_regs_memmap_p; /* Kernel memory mapped address for
413 PCI BAR0, config space registers */
414 void __iomem *ctrl_regs_memmap_p; /* Kernel memory mapped address for
415 PCI BAR1, control registers */
416 void __iomem *drbl_regs_memmap_p; /* Kernel memory mapped address for
417 PCI BAR2, doorbell registers */
2fcee4bf
JS		 418 union {
419 struct {
420 /* IF Type 0, BAR 0 PCI cfg space reg mem map */
421 void __iomem *UERRLOregaddr;
422 void __iomem *UERRHIregaddr;
423 void __iomem *UEMASKLOregaddr;
424 void __iomem *UEMASKHIregaddr;
425 } if_type0;
426 struct {
427 /* IF Type 2, BAR 0 PCI cfg space reg mem map. */
428 void __iomem *STATUSregaddr;
429 void __iomem *CTRLregaddr;
430 void __iomem *ERR1regaddr;
2e90f4b5
JS		 431#define SLIPORT_ERR1_REG_ERR_CODE_1 0x1
432#define SLIPORT_ERR1_REG_ERR_CODE_2 0x2
2fcee4bf 433 void __iomem *ERR2regaddr;
2e90f4b5
JS		 434#define SLIPORT_ERR2_REG_FW_RESTART 0x0
435#define SLIPORT_ERR2_REG_FUNC_PROVISON 0x1
436#define SLIPORT_ERR2_REG_FORCED_DUMP 0x2
437#define SLIPORT_ERR2_REG_FAILURE_EQ 0x3
438#define SLIPORT_ERR2_REG_FAILURE_CQ 0x4
439#define SLIPORT_ERR2_REG_FAILURE_BUS 0x5
440#define SLIPORT_ERR2_REG_FAILURE_RQ 0x6
2fcee4bf
JS		 441 } if_type2;
442 } u;
443
444 /* IF type 0, BAR1 and if type 2, Bar 0 CSR register memory map */
445 void __iomem *PSMPHRregaddr;
446
447 /* Well-known SLI INTF register memory map. */
448 void __iomem *SLIINTFregaddr;
449
450 /* IF type 0, BAR 1 function CSR register memory map */
451 void __iomem *ISRregaddr; /* HST_ISR register */
452 void __iomem *IMRregaddr; /* HST_IMR register */
453 void __iomem *ISCRregaddr; /* HST_ISCR register */
454 /* IF type 0, BAR 0 and if type 2, BAR 0 doorbell register memory map */
455 void __iomem *RQDBregaddr; /* RQ_DOORBELL register */
456 void __iomem *WQDBregaddr; /* WQ_DOORBELL register */
457 void __iomem *EQCQDBregaddr; /* EQCQ_DOORBELL register */
458 void __iomem *MQDBregaddr; /* MQ_DOORBELL register */
459 void __iomem *BMBXregaddr; /* BootStrap MBX register */
da0436e9 460
a747c9ce
JS		 461 uint32_t ue_mask_lo;
462 uint32_t ue_mask_hi;
28baac74
JS		 463 struct lpfc_register sli_intf;
464 struct lpfc_pc_sli4_params pc_sli4_params;
da0436e9
JS		 465 struct msix_entry *msix_entries;
466 uint32_t cfg_eqn;
75baf696 467 uint32_t msix_vec_nr;
da0436e9
JS		 468 struct lpfc_fcp_eq_hdl *fcp_eq_hdl; /* FCP per-WQ handle */
469 /* Pointers to the constructed SLI4 queues */
470 struct lpfc_queue **fp_eq; /* Fast-path event queue */
471 struct lpfc_queue *sp_eq; /* Slow-path event queue */
472 struct lpfc_queue **fcp_wq;/* Fast-path FCP work queue */
473 struct lpfc_queue *mbx_wq; /* Slow-path MBOX work queue */
474 struct lpfc_queue *els_wq; /* Slow-path ELS work queue */
475 struct lpfc_queue *hdr_rq; /* Slow-path Header Receive queue */
476 struct lpfc_queue *dat_rq; /* Slow-path Data Receive queue */
477 struct lpfc_queue **fcp_cq;/* Fast-path FCP compl queue */
478 struct lpfc_queue *mbx_cq; /* Slow-path mailbox complete queue */
479 struct lpfc_queue *els_cq; /* Slow-path ELS response complete queue */
da0436e9
JS		 480
481 /* Setup information for various queue parameters */
482 int eq_esize;
483 int eq_ecount;
484 int cq_esize;
485 int cq_ecount;
486 int wq_esize;
487 int wq_ecount;
488 int mq_esize;
489 int mq_ecount;
490 int rq_esize;
491 int rq_ecount;
492#define LPFC_SP_EQ_MAX_INTR_SEC 10000
493#define LPFC_FP_EQ_MAX_INTR_SEC 10000
494
495 uint32_t intr_enable;
496 struct lpfc_bmbx bmbx;
497 struct lpfc_max_cfg_param max_cfg_param;
6d368e53
JS		 498 uint16_t extents_in_use; /* must allocate resource extents. */
499 uint16_t rpi_hdrs_in_use; /* must post rpi hdrs if set. */
da0436e9
JS		 500 uint16_t next_xri; /* last_xri - max_cfg_param.xri_base = used */
501 uint16_t next_rpi;
502 uint16_t scsi_xri_max;
503 uint16_t scsi_xri_cnt;
8a9d2e80 504 uint16_t els_xri_cnt;
6d368e53 505 uint16_t scsi_xri_start;
da0436e9
JS		 506 struct list_head lpfc_free_sgl_list;
507 struct list_head lpfc_sgl_list;
da0436e9 508 struct list_head lpfc_abts_els_sgl_list;
da0436e9 509 struct list_head lpfc_abts_scsi_buf_list;
da0436e9
JS		 510 struct lpfc_sglq **lpfc_sglq_active_list;
511 struct list_head lpfc_rpi_hdr_list;
512 unsigned long *rpi_bmask;
6d368e53 513 uint16_t *rpi_ids;
da0436e9 514 uint16_t rpi_count;
6d368e53
JS		 515 struct list_head lpfc_rpi_blk_list;
516 unsigned long *xri_bmask;
517 uint16_t *xri_ids;
6d368e53
JS		 518 struct list_head lpfc_xri_blk_list;
519 unsigned long *vfi_bmask;
520 uint16_t *vfi_ids;
521 uint16_t vfi_count;
522 struct list_head lpfc_vfi_blk_list;
da0436e9 523 struct lpfc_sli4_flags sli4_flags;
45ed1190 524 struct list_head sp_queue_event;
da0436e9
JS		 525 struct list_head sp_cqe_event_pool;
526 struct list_head sp_asynce_work_queue;
527 struct list_head sp_fcp_xri_aborted_work_queue;
528 struct list_head sp_els_xri_aborted_work_queue;
529 struct list_head sp_unsol_work_queue;
530 struct lpfc_sli4_link link_state;
cd1c8301
JS		 531 struct lpfc_sli4_lnk_info lnk_info;
532 uint32_t pport_name_sta;
533#define LPFC_SLI4_PPNAME_NON 0
534#define LPFC_SLI4_PPNAME_GET 1
912e3acd 535 struct lpfc_iov iov;
da0436e9
JS		 536 spinlock_t abts_scsi_buf_list_lock; /* list of aborted SCSI IOs */
537 spinlock_t abts_sgl_list_lock; /* list of aborted els IOs */
538};
539
540enum lpfc_sge_type {
541 GEN_BUFF_TYPE,
542 SCSI_BUFF_TYPE
543};
544
0f65ff68
JS		 545enum lpfc_sgl_state {
546 SGL_FREED,
547 SGL_ALLOCATED,
548 SGL_XRI_ABORTED
549};
550
da0436e9
JS		 551struct lpfc_sglq {
552 /* lpfc_sglqs are used in double linked lists */
553 struct list_head list;
554 struct list_head clist;
555 enum lpfc_sge_type buff_type; /* is this a scsi sgl */
0f65ff68 556 enum lpfc_sgl_state state;
19ca7609 557 struct lpfc_nodelist *ndlp; /* ndlp associated with IO */
da0436e9 558 uint16_t iotag; /* pre-assigned IO tag */
6d368e53 559 uint16_t sli4_lxritag; /* logical pre-assigned xri. */
da0436e9
JS		 560 uint16_t sli4_xritag; /* pre-assigned XRI, (OXID) tag. */
561 struct sli4_sge *sgl; /* pre-assigned SGL */
562 void *virt; /* virtual address. */
563 dma_addr_t phys; /* physical address */
564};
565
566struct lpfc_rpi_hdr {
567 struct list_head list;
568 uint32_t len;
569 struct lpfc_dmabuf *dmabuf;
570 uint32_t page_count;
571 uint32_t start_rpi;
572};
573
6d368e53
JS		 574struct lpfc_rsrc_blks {
575 struct list_head list;
576 uint16_t rsrc_start;
577 uint16_t rsrc_size;
578 uint16_t rsrc_used;
579};
580
da0436e9
JS		 581/*
582 * SLI4 specific function prototypes
583 */
584int lpfc_pci_function_reset(struct lpfc_hba *);
73d91e50 585int lpfc_sli4_pdev_status_reg_wait(struct lpfc_hba *);
da0436e9 586int lpfc_sli4_hba_setup(struct lpfc_hba *);
da0436e9
JS		 587int lpfc_sli4_config(struct lpfc_hba *, struct lpfcMboxq *, uint8_t,
588 uint8_t, uint32_t, bool);
589void lpfc_sli4_mbox_cmd_free(struct lpfc_hba *, struct lpfcMboxq *);
590void lpfc_sli4_mbx_sge_set(struct lpfcMboxq *, uint32_t, dma_addr_t, uint32_t);
591void lpfc_sli4_mbx_sge_get(struct lpfcMboxq *, uint32_t,
592 struct lpfc_mbx_sge *);
0c9ab6f5
JS		 593int lpfc_sli4_mbx_read_fcf_rec(struct lpfc_hba *, struct lpfcMboxq *,
594 uint16_t);
da0436e9
JS		 595
596void lpfc_sli4_hba_reset(struct lpfc_hba *);
597struct lpfc_queue *lpfc_sli4_queue_alloc(struct lpfc_hba *, uint32_t,
598 uint32_t);
599void lpfc_sli4_queue_free(struct lpfc_queue *);
600uint32_t lpfc_eq_create(struct lpfc_hba *, struct lpfc_queue *, uint16_t);
601uint32_t lpfc_cq_create(struct lpfc_hba *, struct lpfc_queue *,
602 struct lpfc_queue *, uint32_t, uint32_t);
b19a061a
JS		 603int32_t lpfc_mq_create(struct lpfc_hba *, struct lpfc_queue *,
604 struct lpfc_queue *, uint32_t);
da0436e9
JS		 605uint32_t lpfc_wq_create(struct lpfc_hba *, struct lpfc_queue *,
606 struct lpfc_queue *, uint32_t);
607uint32_t lpfc_rq_create(struct lpfc_hba *, struct lpfc_queue *,
608 struct lpfc_queue *, struct lpfc_queue *, uint32_t);
73d91e50 609void lpfc_rq_adjust_repost(struct lpfc_hba *, struct lpfc_queue *, int);
da0436e9
JS		 610uint32_t lpfc_eq_destroy(struct lpfc_hba *, struct lpfc_queue *);
611uint32_t lpfc_cq_destroy(struct lpfc_hba *, struct lpfc_queue *);
612uint32_t lpfc_mq_destroy(struct lpfc_hba *, struct lpfc_queue *);
613uint32_t lpfc_wq_destroy(struct lpfc_hba *, struct lpfc_queue *);
614uint32_t lpfc_rq_destroy(struct lpfc_hba *, struct lpfc_queue *,
615 struct lpfc_queue *);
616int lpfc_sli4_queue_setup(struct lpfc_hba *);
617void lpfc_sli4_queue_unset(struct lpfc_hba *);
618int lpfc_sli4_post_sgl(struct lpfc_hba *, dma_addr_t, dma_addr_t, uint16_t);
619int lpfc_sli4_repost_scsi_sgl_list(struct lpfc_hba *);
da0436e9
JS		 620uint16_t lpfc_sli4_next_xritag(struct lpfc_hba *);
621int lpfc_sli4_post_async_mbox(struct lpfc_hba *);
da0436e9
JS		 622int lpfc_sli4_post_scsi_sgl_block(struct lpfc_hba *, struct list_head *, int);
623struct lpfc_cq_event *__lpfc_sli4_cq_event_alloc(struct lpfc_hba *);
624struct lpfc_cq_event *lpfc_sli4_cq_event_alloc(struct lpfc_hba *);
625void __lpfc_sli4_cq_event_release(struct lpfc_hba *, struct lpfc_cq_event *);
626void lpfc_sli4_cq_event_release(struct lpfc_hba *, struct lpfc_cq_event *);
627int lpfc_sli4_init_rpi_hdrs(struct lpfc_hba *);
628int lpfc_sli4_post_rpi_hdr(struct lpfc_hba *, struct lpfc_rpi_hdr *);
629int lpfc_sli4_post_all_rpi_hdrs(struct lpfc_hba *);
630struct lpfc_rpi_hdr *lpfc_sli4_create_rpi_hdr(struct lpfc_hba *);
631void lpfc_sli4_remove_rpi_hdrs(struct lpfc_hba *);
632int lpfc_sli4_alloc_rpi(struct lpfc_hba *);
633void lpfc_sli4_free_rpi(struct lpfc_hba *, int);
634void lpfc_sli4_remove_rpis(struct lpfc_hba *);
635void lpfc_sli4_async_event_proc(struct lpfc_hba *);
ecfd03c6 636void lpfc_sli4_fcf_redisc_event_proc(struct lpfc_hba *);
6b5151fd
JS		 637int lpfc_sli4_resume_rpi(struct lpfc_nodelist *,
638 void (*)(struct lpfc_hba *, LPFC_MBOXQ_t *), void *);
da0436e9
JS		 639void lpfc_sli4_fcp_xri_abort_event_proc(struct lpfc_hba *);
640void lpfc_sli4_els_xri_abort_event_proc(struct lpfc_hba *);
641void lpfc_sli4_fcp_xri_aborted(struct lpfc_hba *,
642 struct sli4_wcqe_xri_aborted *);
643void lpfc_sli4_els_xri_aborted(struct lpfc_hba *,
644 struct sli4_wcqe_xri_aborted *);
1151e3ec
JS		 645void lpfc_sli4_vport_delete_els_xri_aborted(struct lpfc_vport *);
646void lpfc_sli4_vport_delete_fcp_xri_aborted(struct lpfc_vport *);
da0436e9
JS		 647int lpfc_sli4_brdreset(struct lpfc_hba *);
648int lpfc_sli4_add_fcf_record(struct lpfc_hba *, struct fcf_record *);
649void lpfc_sli_remove_dflt_fcf(struct lpfc_hba *);
650int lpfc_sli4_get_els_iocb_cnt(struct lpfc_hba *);
76a95d75 651int lpfc_sli4_init_vpi(struct lpfc_vport *);
da0436e9
JS		 652uint32_t lpfc_sli4_cq_release(struct lpfc_queue *, bool);
653uint32_t lpfc_sli4_eq_release(struct lpfc_queue *, bool);
654void lpfc_sli4_fcfi_unreg(struct lpfc_hba *, uint16_t);
0c9ab6f5
JS		 655int lpfc_sli4_fcf_scan_read_fcf_rec(struct lpfc_hba *, uint16_t);
656int lpfc_sli4_fcf_rr_read_fcf_rec(struct lpfc_hba *, uint16_t);
657int lpfc_sli4_read_fcf_rec(struct lpfc_hba *, uint16_t);
658void lpfc_mbx_cmpl_fcf_scan_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *);
659void lpfc_mbx_cmpl_fcf_rr_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *);
660void lpfc_mbx_cmpl_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *);
661int lpfc_sli4_unregister_fcf(struct lpfc_hba *);
da0436e9 662int lpfc_sli4_post_status_check(struct lpfc_hba *);
a183a15f
JS		 663uint8_t lpfc_sli_config_mbox_subsys_get(struct lpfc_hba *, LPFC_MBOXQ_t *);
664uint8_t lpfc_sli_config_mbox_opcode_get(struct lpfc_hba *, LPFC_MBOXQ_t *);
Linux kernel - Deliverables
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