Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
fa90c54f | 2 | * QLogic Fibre Channel HBA Driver |
01e58d8e | 3 | * Copyright (c) 2003-2008 QLogic Corporation |
1da177e4 | 4 | * |
fa90c54f | 5 | * See LICENSE.qla2xxx for copyright and licensing details. |
1da177e4 LT |
6 | */ |
7 | #include "qla_def.h" | |
8 | ||
9 | #include <linux/delay.h> | |
10 | ||
a7a167bf | 11 | static inline void |
7b867cf7 | 12 | qla2xxx_prep_dump(struct qla_hw_data *ha, struct qla2xxx_fw_dump *fw_dump) |
a7a167bf AV |
13 | { |
14 | fw_dump->fw_major_version = htonl(ha->fw_major_version); | |
15 | fw_dump->fw_minor_version = htonl(ha->fw_minor_version); | |
16 | fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version); | |
17 | fw_dump->fw_attributes = htonl(ha->fw_attributes); | |
18 | ||
19 | fw_dump->vendor = htonl(ha->pdev->vendor); | |
20 | fw_dump->device = htonl(ha->pdev->device); | |
21 | fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor); | |
22 | fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device); | |
23 | } | |
24 | ||
25 | static inline void * | |
73208dfd | 26 | qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr) |
a7a167bf | 27 | { |
73208dfd AC |
28 | struct req_que *req = ha->req_q_map[0]; |
29 | struct rsp_que *rsp = ha->rsp_q_map[0]; | |
a7a167bf | 30 | /* Request queue. */ |
7b867cf7 | 31 | memcpy(ptr, req->ring, req->length * |
a7a167bf AV |
32 | sizeof(request_t)); |
33 | ||
34 | /* Response queue. */ | |
7b867cf7 AC |
35 | ptr += req->length * sizeof(request_t); |
36 | memcpy(ptr, rsp->ring, rsp->length * | |
a7a167bf AV |
37 | sizeof(response_t)); |
38 | ||
7b867cf7 | 39 | return ptr + (rsp->length * sizeof(response_t)); |
a7a167bf | 40 | } |
1da177e4 | 41 | |
c3a2f0df | 42 | static int |
7b867cf7 | 43 | qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram, |
c5722708 | 44 | uint32_t ram_dwords, void **nxt) |
c3a2f0df AV |
45 | { |
46 | int rval; | |
c5722708 AV |
47 | uint32_t cnt, stat, timer, dwords, idx; |
48 | uint16_t mb0; | |
c3a2f0df | 49 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
c5722708 AV |
50 | dma_addr_t dump_dma = ha->gid_list_dma; |
51 | uint32_t *dump = (uint32_t *)ha->gid_list; | |
c3a2f0df AV |
52 | |
53 | rval = QLA_SUCCESS; | |
c5722708 | 54 | mb0 = 0; |
c3a2f0df | 55 | |
c5722708 | 56 | WRT_REG_WORD(®->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED); |
c3a2f0df AV |
57 | clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); |
58 | ||
c5722708 AV |
59 | dwords = GID_LIST_SIZE / 4; |
60 | for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS; | |
61 | cnt += dwords, addr += dwords) { | |
62 | if (cnt + dwords > ram_dwords) | |
63 | dwords = ram_dwords - cnt; | |
c3a2f0df | 64 | |
c5722708 AV |
65 | WRT_REG_WORD(®->mailbox1, LSW(addr)); |
66 | WRT_REG_WORD(®->mailbox8, MSW(addr)); | |
c3a2f0df | 67 | |
c5722708 AV |
68 | WRT_REG_WORD(®->mailbox2, MSW(dump_dma)); |
69 | WRT_REG_WORD(®->mailbox3, LSW(dump_dma)); | |
70 | WRT_REG_WORD(®->mailbox6, MSW(MSD(dump_dma))); | |
71 | WRT_REG_WORD(®->mailbox7, LSW(MSD(dump_dma))); | |
c3a2f0df | 72 | |
c5722708 AV |
73 | WRT_REG_WORD(®->mailbox4, MSW(dwords)); |
74 | WRT_REG_WORD(®->mailbox5, LSW(dwords)); | |
c3a2f0df AV |
75 | WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); |
76 | ||
77 | for (timer = 6000000; timer; timer--) { | |
78 | /* Check for pending interrupts. */ | |
79 | stat = RD_REG_DWORD(®->host_status); | |
80 | if (stat & HSRX_RISC_INT) { | |
81 | stat &= 0xff; | |
82 | ||
83 | if (stat == 0x1 || stat == 0x2 || | |
84 | stat == 0x10 || stat == 0x11) { | |
85 | set_bit(MBX_INTERRUPT, | |
86 | &ha->mbx_cmd_flags); | |
87 | ||
c5722708 | 88 | mb0 = RD_REG_WORD(®->mailbox0); |
c3a2f0df AV |
89 | |
90 | WRT_REG_DWORD(®->hccr, | |
91 | HCCRX_CLR_RISC_INT); | |
92 | RD_REG_DWORD(®->hccr); | |
93 | break; | |
94 | } | |
95 | ||
96 | /* Clear this intr; it wasn't a mailbox intr */ | |
97 | WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); | |
98 | RD_REG_DWORD(®->hccr); | |
99 | } | |
100 | udelay(5); | |
101 | } | |
102 | ||
103 | if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { | |
c5722708 AV |
104 | rval = mb0 & MBS_MASK; |
105 | for (idx = 0; idx < dwords; idx++) | |
106 | ram[cnt + idx] = swab32(dump[idx]); | |
c3a2f0df AV |
107 | } else { |
108 | rval = QLA_FUNCTION_FAILED; | |
109 | } | |
110 | } | |
111 | ||
c5722708 | 112 | *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL; |
c3a2f0df AV |
113 | return rval; |
114 | } | |
115 | ||
c5722708 | 116 | static int |
7b867cf7 | 117 | qla24xx_dump_memory(struct qla_hw_data *ha, uint32_t *code_ram, |
c5722708 AV |
118 | uint32_t cram_size, void **nxt) |
119 | { | |
120 | int rval; | |
121 | ||
122 | /* Code RAM. */ | |
123 | rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt); | |
124 | if (rval != QLA_SUCCESS) | |
125 | return rval; | |
126 | ||
127 | /* External Memory. */ | |
128 | return qla24xx_dump_ram(ha, 0x100000, *nxt, | |
129 | ha->fw_memory_size - 0x100000 + 1, nxt); | |
130 | } | |
131 | ||
c81d04c9 AV |
132 | static uint32_t * |
133 | qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase, | |
134 | uint32_t count, uint32_t *buf) | |
135 | { | |
136 | uint32_t __iomem *dmp_reg; | |
137 | ||
138 | WRT_REG_DWORD(®->iobase_addr, iobase); | |
139 | dmp_reg = ®->iobase_window; | |
140 | while (count--) | |
141 | *buf++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
142 | ||
143 | return buf; | |
144 | } | |
145 | ||
146 | static inline int | |
147 | qla24xx_pause_risc(struct device_reg_24xx __iomem *reg) | |
148 | { | |
149 | int rval = QLA_SUCCESS; | |
150 | uint32_t cnt; | |
151 | ||
c3b058af AV |
152 | if (RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) |
153 | return rval; | |
154 | ||
155 | WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE); | |
156 | for (cnt = 30000; (RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) == 0 && | |
157 | rval == QLA_SUCCESS; cnt--) { | |
158 | if (cnt) | |
159 | udelay(100); | |
160 | else | |
161 | rval = QLA_FUNCTION_TIMEOUT; | |
c81d04c9 AV |
162 | } |
163 | ||
164 | return rval; | |
165 | } | |
166 | ||
167 | static int | |
7b867cf7 | 168 | qla24xx_soft_reset(struct qla_hw_data *ha) |
c81d04c9 AV |
169 | { |
170 | int rval = QLA_SUCCESS; | |
171 | uint32_t cnt; | |
172 | uint16_t mb0, wd; | |
173 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
174 | ||
175 | /* Reset RISC. */ | |
176 | WRT_REG_DWORD(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); | |
177 | for (cnt = 0; cnt < 30000; cnt++) { | |
178 | if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) | |
179 | break; | |
180 | ||
181 | udelay(10); | |
182 | } | |
183 | ||
184 | WRT_REG_DWORD(®->ctrl_status, | |
185 | CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); | |
186 | pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); | |
187 | ||
188 | udelay(100); | |
189 | /* Wait for firmware to complete NVRAM accesses. */ | |
190 | mb0 = (uint32_t) RD_REG_WORD(®->mailbox0); | |
191 | for (cnt = 10000 ; cnt && mb0; cnt--) { | |
192 | udelay(5); | |
193 | mb0 = (uint32_t) RD_REG_WORD(®->mailbox0); | |
194 | barrier(); | |
195 | } | |
196 | ||
197 | /* Wait for soft-reset to complete. */ | |
198 | for (cnt = 0; cnt < 30000; cnt++) { | |
199 | if ((RD_REG_DWORD(®->ctrl_status) & | |
200 | CSRX_ISP_SOFT_RESET) == 0) | |
201 | break; | |
202 | ||
203 | udelay(10); | |
204 | } | |
205 | WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); | |
206 | RD_REG_DWORD(®->hccr); /* PCI Posting. */ | |
207 | ||
208 | for (cnt = 30000; RD_REG_WORD(®->mailbox0) != 0 && | |
209 | rval == QLA_SUCCESS; cnt--) { | |
210 | if (cnt) | |
211 | udelay(100); | |
212 | else | |
213 | rval = QLA_FUNCTION_TIMEOUT; | |
214 | } | |
215 | ||
216 | return rval; | |
217 | } | |
218 | ||
c5722708 | 219 | static int |
7b867cf7 AC |
220 | qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint16_t *ram, |
221 | uint16_t ram_words, void **nxt) | |
c5722708 AV |
222 | { |
223 | int rval; | |
224 | uint32_t cnt, stat, timer, words, idx; | |
225 | uint16_t mb0; | |
226 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
227 | dma_addr_t dump_dma = ha->gid_list_dma; | |
228 | uint16_t *dump = (uint16_t *)ha->gid_list; | |
229 | ||
230 | rval = QLA_SUCCESS; | |
231 | mb0 = 0; | |
232 | ||
233 | WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED); | |
234 | clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | |
235 | ||
236 | words = GID_LIST_SIZE / 2; | |
237 | for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS; | |
238 | cnt += words, addr += words) { | |
239 | if (cnt + words > ram_words) | |
240 | words = ram_words - cnt; | |
241 | ||
242 | WRT_MAILBOX_REG(ha, reg, 1, LSW(addr)); | |
243 | WRT_MAILBOX_REG(ha, reg, 8, MSW(addr)); | |
244 | ||
245 | WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma)); | |
246 | WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma)); | |
247 | WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma))); | |
248 | WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma))); | |
249 | ||
250 | WRT_MAILBOX_REG(ha, reg, 4, words); | |
251 | WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); | |
252 | ||
253 | for (timer = 6000000; timer; timer--) { | |
254 | /* Check for pending interrupts. */ | |
255 | stat = RD_REG_DWORD(®->u.isp2300.host_status); | |
256 | if (stat & HSR_RISC_INT) { | |
257 | stat &= 0xff; | |
258 | ||
259 | if (stat == 0x1 || stat == 0x2) { | |
260 | set_bit(MBX_INTERRUPT, | |
261 | &ha->mbx_cmd_flags); | |
262 | ||
263 | mb0 = RD_MAILBOX_REG(ha, reg, 0); | |
264 | ||
265 | /* Release mailbox registers. */ | |
266 | WRT_REG_WORD(®->semaphore, 0); | |
267 | WRT_REG_WORD(®->hccr, | |
268 | HCCR_CLR_RISC_INT); | |
269 | RD_REG_WORD(®->hccr); | |
270 | break; | |
271 | } else if (stat == 0x10 || stat == 0x11) { | |
272 | set_bit(MBX_INTERRUPT, | |
273 | &ha->mbx_cmd_flags); | |
274 | ||
275 | mb0 = RD_MAILBOX_REG(ha, reg, 0); | |
276 | ||
277 | WRT_REG_WORD(®->hccr, | |
278 | HCCR_CLR_RISC_INT); | |
279 | RD_REG_WORD(®->hccr); | |
280 | break; | |
281 | } | |
282 | ||
283 | /* clear this intr; it wasn't a mailbox intr */ | |
284 | WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); | |
285 | RD_REG_WORD(®->hccr); | |
286 | } | |
287 | udelay(5); | |
288 | } | |
289 | ||
290 | if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { | |
291 | rval = mb0 & MBS_MASK; | |
292 | for (idx = 0; idx < words; idx++) | |
293 | ram[cnt + idx] = swab16(dump[idx]); | |
294 | } else { | |
295 | rval = QLA_FUNCTION_FAILED; | |
296 | } | |
297 | } | |
298 | ||
299 | *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL; | |
300 | return rval; | |
301 | } | |
302 | ||
c81d04c9 AV |
303 | static inline void |
304 | qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count, | |
305 | uint16_t *buf) | |
306 | { | |
307 | uint16_t __iomem *dmp_reg = ®->u.isp2300.fb_cmd; | |
308 | ||
309 | while (count--) | |
310 | *buf++ = htons(RD_REG_WORD(dmp_reg++)); | |
311 | } | |
312 | ||
bb99de67 AV |
313 | static inline void * |
314 | qla24xx_copy_eft(struct qla_hw_data *ha, void *ptr) | |
315 | { | |
316 | if (!ha->eft) | |
317 | return ptr; | |
318 | ||
319 | memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size)); | |
320 | return ptr + ntohl(ha->fw_dump->eft_size); | |
321 | } | |
322 | ||
323 | static inline void * | |
324 | qla25xx_copy_fce(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) | |
325 | { | |
326 | uint32_t cnt; | |
327 | uint32_t *iter_reg; | |
328 | struct qla2xxx_fce_chain *fcec = ptr; | |
329 | ||
330 | if (!ha->fce) | |
331 | return ptr; | |
332 | ||
333 | *last_chain = &fcec->type; | |
334 | fcec->type = __constant_htonl(DUMP_CHAIN_FCE); | |
335 | fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) + | |
336 | fce_calc_size(ha->fce_bufs)); | |
337 | fcec->size = htonl(fce_calc_size(ha->fce_bufs)); | |
338 | fcec->addr_l = htonl(LSD(ha->fce_dma)); | |
339 | fcec->addr_h = htonl(MSD(ha->fce_dma)); | |
340 | ||
341 | iter_reg = fcec->eregs; | |
342 | for (cnt = 0; cnt < 8; cnt++) | |
343 | *iter_reg++ = htonl(ha->fce_mb[cnt]); | |
344 | ||
345 | memcpy(iter_reg, ha->fce, ntohl(fcec->size)); | |
346 | ||
347 | return iter_reg; | |
348 | } | |
349 | ||
d63ab533 AV |
350 | static inline void * |
351 | qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) | |
352 | { | |
353 | uint32_t cnt, que_idx; | |
354 | uint8_t req_cnt, rsp_cnt, que_cnt; | |
355 | struct qla2xxx_mq_chain *mq = ptr; | |
356 | struct device_reg_25xxmq __iomem *reg; | |
357 | ||
358 | if (!ha->mqenable) | |
359 | return ptr; | |
360 | ||
361 | mq = ptr; | |
362 | *last_chain = &mq->type; | |
363 | mq->type = __constant_htonl(DUMP_CHAIN_MQ); | |
364 | mq->chain_size = __constant_htonl(sizeof(struct qla2xxx_mq_chain)); | |
365 | ||
366 | req_cnt = find_first_zero_bit(ha->req_qid_map, ha->max_queues); | |
367 | rsp_cnt = find_first_zero_bit(ha->rsp_qid_map, ha->max_queues); | |
368 | que_cnt = req_cnt > rsp_cnt ? req_cnt : rsp_cnt; | |
369 | mq->count = htonl(que_cnt); | |
370 | for (cnt = 0; cnt < que_cnt; cnt++) { | |
371 | reg = (struct device_reg_25xxmq *) ((void *) | |
372 | ha->mqiobase + cnt * QLA_QUE_PAGE); | |
373 | que_idx = cnt * 4; | |
374 | mq->qregs[que_idx] = htonl(RD_REG_DWORD(®->req_q_in)); | |
375 | mq->qregs[que_idx+1] = htonl(RD_REG_DWORD(®->req_q_out)); | |
376 | mq->qregs[que_idx+2] = htonl(RD_REG_DWORD(®->rsp_q_in)); | |
377 | mq->qregs[que_idx+3] = htonl(RD_REG_DWORD(®->rsp_q_out)); | |
378 | } | |
379 | ||
380 | return ptr + sizeof(struct qla2xxx_mq_chain); | |
381 | } | |
382 | ||
1da177e4 LT |
383 | /** |
384 | * qla2300_fw_dump() - Dumps binary data from the 2300 firmware. | |
385 | * @ha: HA context | |
386 | * @hardware_locked: Called with the hardware_lock | |
387 | */ | |
388 | void | |
7b867cf7 | 389 | qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
1da177e4 LT |
390 | { |
391 | int rval; | |
c5722708 | 392 | uint32_t cnt; |
7b867cf7 | 393 | struct qla_hw_data *ha = vha->hw; |
3d71644c | 394 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 LT |
395 | uint16_t __iomem *dmp_reg; |
396 | unsigned long flags; | |
397 | struct qla2300_fw_dump *fw; | |
c5722708 | 398 | void *nxt; |
73208dfd | 399 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
1da177e4 | 400 | |
1da177e4 LT |
401 | flags = 0; |
402 | ||
403 | if (!hardware_locked) | |
404 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
405 | ||
d4e3e04d | 406 | if (!ha->fw_dump) { |
1da177e4 | 407 | qla_printk(KERN_WARNING, ha, |
d4e3e04d | 408 | "No buffer available for dump!!!\n"); |
1da177e4 LT |
409 | goto qla2300_fw_dump_failed; |
410 | } | |
411 | ||
d4e3e04d | 412 | if (ha->fw_dumped) { |
1da177e4 | 413 | qla_printk(KERN_WARNING, ha, |
d4e3e04d AV |
414 | "Firmware has been previously dumped (%p) -- ignoring " |
415 | "request...\n", ha->fw_dump); | |
1da177e4 LT |
416 | goto qla2300_fw_dump_failed; |
417 | } | |
a7a167bf AV |
418 | fw = &ha->fw_dump->isp.isp23; |
419 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
1da177e4 LT |
420 | |
421 | rval = QLA_SUCCESS; | |
a7a167bf | 422 | fw->hccr = htons(RD_REG_WORD(®->hccr)); |
1da177e4 LT |
423 | |
424 | /* Pause RISC. */ | |
fa2a1ce5 | 425 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); |
1da177e4 LT |
426 | if (IS_QLA2300(ha)) { |
427 | for (cnt = 30000; | |
428 | (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && | |
429 | rval == QLA_SUCCESS; cnt--) { | |
430 | if (cnt) | |
431 | udelay(100); | |
432 | else | |
433 | rval = QLA_FUNCTION_TIMEOUT; | |
434 | } | |
435 | } else { | |
436 | RD_REG_WORD(®->hccr); /* PCI Posting. */ | |
437 | udelay(10); | |
438 | } | |
439 | ||
440 | if (rval == QLA_SUCCESS) { | |
c81d04c9 | 441 | dmp_reg = ®->flash_address; |
fa2a1ce5 | 442 | for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) |
a7a167bf | 443 | fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 444 | |
c81d04c9 | 445 | dmp_reg = ®->u.isp2300.req_q_in; |
fa2a1ce5 | 446 | for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++) |
a7a167bf | 447 | fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 448 | |
c81d04c9 | 449 | dmp_reg = ®->u.isp2300.mailbox0; |
fa2a1ce5 | 450 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) |
a7a167bf | 451 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 LT |
452 | |
453 | WRT_REG_WORD(®->ctrl_status, 0x40); | |
c81d04c9 | 454 | qla2xxx_read_window(reg, 32, fw->resp_dma_reg); |
1da177e4 LT |
455 | |
456 | WRT_REG_WORD(®->ctrl_status, 0x50); | |
c81d04c9 | 457 | qla2xxx_read_window(reg, 48, fw->dma_reg); |
1da177e4 LT |
458 | |
459 | WRT_REG_WORD(®->ctrl_status, 0x00); | |
c81d04c9 | 460 | dmp_reg = ®->risc_hw; |
fa2a1ce5 | 461 | for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) |
a7a167bf | 462 | fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 463 | |
fa2a1ce5 | 464 | WRT_REG_WORD(®->pcr, 0x2000); |
c81d04c9 | 465 | qla2xxx_read_window(reg, 16, fw->risc_gp0_reg); |
1da177e4 | 466 | |
fa2a1ce5 | 467 | WRT_REG_WORD(®->pcr, 0x2200); |
c81d04c9 | 468 | qla2xxx_read_window(reg, 16, fw->risc_gp1_reg); |
1da177e4 | 469 | |
fa2a1ce5 | 470 | WRT_REG_WORD(®->pcr, 0x2400); |
c81d04c9 | 471 | qla2xxx_read_window(reg, 16, fw->risc_gp2_reg); |
1da177e4 | 472 | |
fa2a1ce5 | 473 | WRT_REG_WORD(®->pcr, 0x2600); |
c81d04c9 | 474 | qla2xxx_read_window(reg, 16, fw->risc_gp3_reg); |
1da177e4 | 475 | |
fa2a1ce5 | 476 | WRT_REG_WORD(®->pcr, 0x2800); |
c81d04c9 | 477 | qla2xxx_read_window(reg, 16, fw->risc_gp4_reg); |
1da177e4 | 478 | |
fa2a1ce5 | 479 | WRT_REG_WORD(®->pcr, 0x2A00); |
c81d04c9 | 480 | qla2xxx_read_window(reg, 16, fw->risc_gp5_reg); |
1da177e4 | 481 | |
fa2a1ce5 | 482 | WRT_REG_WORD(®->pcr, 0x2C00); |
c81d04c9 | 483 | qla2xxx_read_window(reg, 16, fw->risc_gp6_reg); |
1da177e4 | 484 | |
fa2a1ce5 | 485 | WRT_REG_WORD(®->pcr, 0x2E00); |
c81d04c9 | 486 | qla2xxx_read_window(reg, 16, fw->risc_gp7_reg); |
1da177e4 | 487 | |
fa2a1ce5 | 488 | WRT_REG_WORD(®->ctrl_status, 0x10); |
c81d04c9 | 489 | qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg); |
1da177e4 | 490 | |
fa2a1ce5 | 491 | WRT_REG_WORD(®->ctrl_status, 0x20); |
c81d04c9 | 492 | qla2xxx_read_window(reg, 64, fw->fpm_b0_reg); |
1da177e4 | 493 | |
fa2a1ce5 | 494 | WRT_REG_WORD(®->ctrl_status, 0x30); |
c81d04c9 | 495 | qla2xxx_read_window(reg, 64, fw->fpm_b1_reg); |
1da177e4 LT |
496 | |
497 | /* Reset RISC. */ | |
498 | WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); | |
499 | for (cnt = 0; cnt < 30000; cnt++) { | |
500 | if ((RD_REG_WORD(®->ctrl_status) & | |
501 | CSR_ISP_SOFT_RESET) == 0) | |
502 | break; | |
503 | ||
504 | udelay(10); | |
505 | } | |
506 | } | |
507 | ||
508 | if (!IS_QLA2300(ha)) { | |
509 | for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && | |
510 | rval == QLA_SUCCESS; cnt--) { | |
511 | if (cnt) | |
512 | udelay(100); | |
513 | else | |
514 | rval = QLA_FUNCTION_TIMEOUT; | |
515 | } | |
516 | } | |
517 | ||
c5722708 AV |
518 | /* Get RISC SRAM. */ |
519 | if (rval == QLA_SUCCESS) | |
520 | rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram, | |
521 | sizeof(fw->risc_ram) / 2, &nxt); | |
1da177e4 | 522 | |
c5722708 AV |
523 | /* Get stack SRAM. */ |
524 | if (rval == QLA_SUCCESS) | |
525 | rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram, | |
526 | sizeof(fw->stack_ram) / 2, &nxt); | |
1da177e4 | 527 | |
c5722708 AV |
528 | /* Get data SRAM. */ |
529 | if (rval == QLA_SUCCESS) | |
530 | rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram, | |
531 | ha->fw_memory_size - 0x11000 + 1, &nxt); | |
1da177e4 | 532 | |
a7a167bf | 533 | if (rval == QLA_SUCCESS) |
73208dfd | 534 | qla2xxx_copy_queues(ha, nxt); |
a7a167bf | 535 | |
1da177e4 LT |
536 | if (rval != QLA_SUCCESS) { |
537 | qla_printk(KERN_WARNING, ha, | |
538 | "Failed to dump firmware (%x)!!!\n", rval); | |
d4e3e04d | 539 | ha->fw_dumped = 0; |
1da177e4 | 540 | |
1da177e4 LT |
541 | } else { |
542 | qla_printk(KERN_INFO, ha, | |
543 | "Firmware dump saved to temp buffer (%ld/%p).\n", | |
73208dfd | 544 | base_vha->host_no, ha->fw_dump); |
d4e3e04d | 545 | ha->fw_dumped = 1; |
1da177e4 LT |
546 | } |
547 | ||
548 | qla2300_fw_dump_failed: | |
549 | if (!hardware_locked) | |
550 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
551 | } | |
552 | ||
1da177e4 LT |
553 | /** |
554 | * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware. | |
555 | * @ha: HA context | |
556 | * @hardware_locked: Called with the hardware_lock | |
557 | */ | |
558 | void | |
7b867cf7 | 559 | qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
1da177e4 LT |
560 | { |
561 | int rval; | |
562 | uint32_t cnt, timer; | |
563 | uint16_t risc_address; | |
564 | uint16_t mb0, mb2; | |
7b867cf7 | 565 | struct qla_hw_data *ha = vha->hw; |
3d71644c | 566 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 LT |
567 | uint16_t __iomem *dmp_reg; |
568 | unsigned long flags; | |
569 | struct qla2100_fw_dump *fw; | |
73208dfd | 570 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
1da177e4 LT |
571 | |
572 | risc_address = 0; | |
573 | mb0 = mb2 = 0; | |
574 | flags = 0; | |
575 | ||
576 | if (!hardware_locked) | |
577 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
578 | ||
d4e3e04d | 579 | if (!ha->fw_dump) { |
1da177e4 | 580 | qla_printk(KERN_WARNING, ha, |
d4e3e04d | 581 | "No buffer available for dump!!!\n"); |
1da177e4 LT |
582 | goto qla2100_fw_dump_failed; |
583 | } | |
584 | ||
d4e3e04d | 585 | if (ha->fw_dumped) { |
1da177e4 | 586 | qla_printk(KERN_WARNING, ha, |
d4e3e04d AV |
587 | "Firmware has been previously dumped (%p) -- ignoring " |
588 | "request...\n", ha->fw_dump); | |
1da177e4 LT |
589 | goto qla2100_fw_dump_failed; |
590 | } | |
a7a167bf AV |
591 | fw = &ha->fw_dump->isp.isp21; |
592 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
1da177e4 LT |
593 | |
594 | rval = QLA_SUCCESS; | |
a7a167bf | 595 | fw->hccr = htons(RD_REG_WORD(®->hccr)); |
1da177e4 LT |
596 | |
597 | /* Pause RISC. */ | |
fa2a1ce5 | 598 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); |
1da177e4 LT |
599 | for (cnt = 30000; (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && |
600 | rval == QLA_SUCCESS; cnt--) { | |
601 | if (cnt) | |
602 | udelay(100); | |
603 | else | |
604 | rval = QLA_FUNCTION_TIMEOUT; | |
605 | } | |
606 | if (rval == QLA_SUCCESS) { | |
c81d04c9 | 607 | dmp_reg = ®->flash_address; |
fa2a1ce5 | 608 | for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) |
a7a167bf | 609 | fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 610 | |
c81d04c9 | 611 | dmp_reg = ®->u.isp2100.mailbox0; |
1da177e4 | 612 | for (cnt = 0; cnt < ha->mbx_count; cnt++) { |
c81d04c9 AV |
613 | if (cnt == 8) |
614 | dmp_reg = ®->u_end.isp2200.mailbox8; | |
615 | ||
a7a167bf | 616 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 LT |
617 | } |
618 | ||
c81d04c9 | 619 | dmp_reg = ®->u.isp2100.unused_2[0]; |
fa2a1ce5 | 620 | for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++) |
a7a167bf | 621 | fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 LT |
622 | |
623 | WRT_REG_WORD(®->ctrl_status, 0x00); | |
c81d04c9 | 624 | dmp_reg = ®->risc_hw; |
fa2a1ce5 | 625 | for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) |
a7a167bf | 626 | fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 627 | |
fa2a1ce5 | 628 | WRT_REG_WORD(®->pcr, 0x2000); |
c81d04c9 | 629 | qla2xxx_read_window(reg, 16, fw->risc_gp0_reg); |
1da177e4 | 630 | |
fa2a1ce5 | 631 | WRT_REG_WORD(®->pcr, 0x2100); |
c81d04c9 | 632 | qla2xxx_read_window(reg, 16, fw->risc_gp1_reg); |
1da177e4 | 633 | |
fa2a1ce5 | 634 | WRT_REG_WORD(®->pcr, 0x2200); |
c81d04c9 | 635 | qla2xxx_read_window(reg, 16, fw->risc_gp2_reg); |
1da177e4 | 636 | |
fa2a1ce5 | 637 | WRT_REG_WORD(®->pcr, 0x2300); |
c81d04c9 | 638 | qla2xxx_read_window(reg, 16, fw->risc_gp3_reg); |
1da177e4 | 639 | |
fa2a1ce5 | 640 | WRT_REG_WORD(®->pcr, 0x2400); |
c81d04c9 | 641 | qla2xxx_read_window(reg, 16, fw->risc_gp4_reg); |
1da177e4 | 642 | |
fa2a1ce5 | 643 | WRT_REG_WORD(®->pcr, 0x2500); |
c81d04c9 | 644 | qla2xxx_read_window(reg, 16, fw->risc_gp5_reg); |
1da177e4 | 645 | |
fa2a1ce5 | 646 | WRT_REG_WORD(®->pcr, 0x2600); |
c81d04c9 | 647 | qla2xxx_read_window(reg, 16, fw->risc_gp6_reg); |
1da177e4 | 648 | |
fa2a1ce5 | 649 | WRT_REG_WORD(®->pcr, 0x2700); |
c81d04c9 | 650 | qla2xxx_read_window(reg, 16, fw->risc_gp7_reg); |
1da177e4 | 651 | |
fa2a1ce5 | 652 | WRT_REG_WORD(®->ctrl_status, 0x10); |
c81d04c9 | 653 | qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg); |
1da177e4 | 654 | |
fa2a1ce5 | 655 | WRT_REG_WORD(®->ctrl_status, 0x20); |
c81d04c9 | 656 | qla2xxx_read_window(reg, 64, fw->fpm_b0_reg); |
1da177e4 | 657 | |
fa2a1ce5 | 658 | WRT_REG_WORD(®->ctrl_status, 0x30); |
c81d04c9 | 659 | qla2xxx_read_window(reg, 64, fw->fpm_b1_reg); |
1da177e4 LT |
660 | |
661 | /* Reset the ISP. */ | |
662 | WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); | |
663 | } | |
664 | ||
665 | for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && | |
666 | rval == QLA_SUCCESS; cnt--) { | |
667 | if (cnt) | |
668 | udelay(100); | |
669 | else | |
670 | rval = QLA_FUNCTION_TIMEOUT; | |
671 | } | |
672 | ||
673 | /* Pause RISC. */ | |
674 | if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) && | |
675 | (RD_REG_WORD(®->mctr) & (BIT_1 | BIT_0)) != 0))) { | |
676 | ||
fa2a1ce5 | 677 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); |
1da177e4 LT |
678 | for (cnt = 30000; |
679 | (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && | |
680 | rval == QLA_SUCCESS; cnt--) { | |
681 | if (cnt) | |
682 | udelay(100); | |
683 | else | |
684 | rval = QLA_FUNCTION_TIMEOUT; | |
685 | } | |
686 | if (rval == QLA_SUCCESS) { | |
687 | /* Set memory configuration and timing. */ | |
688 | if (IS_QLA2100(ha)) | |
689 | WRT_REG_WORD(®->mctr, 0xf1); | |
690 | else | |
691 | WRT_REG_WORD(®->mctr, 0xf2); | |
692 | RD_REG_WORD(®->mctr); /* PCI Posting. */ | |
693 | ||
694 | /* Release RISC. */ | |
695 | WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); | |
696 | } | |
697 | } | |
698 | ||
699 | if (rval == QLA_SUCCESS) { | |
700 | /* Get RISC SRAM. */ | |
701 | risc_address = 0x1000; | |
702 | WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD); | |
703 | clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | |
704 | } | |
705 | for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS; | |
706 | cnt++, risc_address++) { | |
707 | WRT_MAILBOX_REG(ha, reg, 1, risc_address); | |
708 | WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); | |
709 | ||
710 | for (timer = 6000000; timer != 0; timer--) { | |
711 | /* Check for pending interrupts. */ | |
712 | if (RD_REG_WORD(®->istatus) & ISR_RISC_INT) { | |
713 | if (RD_REG_WORD(®->semaphore) & BIT_0) { | |
714 | set_bit(MBX_INTERRUPT, | |
715 | &ha->mbx_cmd_flags); | |
716 | ||
717 | mb0 = RD_MAILBOX_REG(ha, reg, 0); | |
718 | mb2 = RD_MAILBOX_REG(ha, reg, 2); | |
719 | ||
720 | WRT_REG_WORD(®->semaphore, 0); | |
721 | WRT_REG_WORD(®->hccr, | |
722 | HCCR_CLR_RISC_INT); | |
723 | RD_REG_WORD(®->hccr); | |
724 | break; | |
725 | } | |
726 | WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); | |
727 | RD_REG_WORD(®->hccr); | |
728 | } | |
729 | udelay(5); | |
730 | } | |
731 | ||
732 | if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { | |
733 | rval = mb0 & MBS_MASK; | |
a7a167bf | 734 | fw->risc_ram[cnt] = htons(mb2); |
1da177e4 LT |
735 | } else { |
736 | rval = QLA_FUNCTION_FAILED; | |
737 | } | |
738 | } | |
739 | ||
a7a167bf | 740 | if (rval == QLA_SUCCESS) |
73208dfd | 741 | qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]); |
a7a167bf | 742 | |
1da177e4 LT |
743 | if (rval != QLA_SUCCESS) { |
744 | qla_printk(KERN_WARNING, ha, | |
745 | "Failed to dump firmware (%x)!!!\n", rval); | |
d4e3e04d | 746 | ha->fw_dumped = 0; |
1da177e4 | 747 | |
1da177e4 LT |
748 | } else { |
749 | qla_printk(KERN_INFO, ha, | |
750 | "Firmware dump saved to temp buffer (%ld/%p).\n", | |
73208dfd | 751 | base_vha->host_no, ha->fw_dump); |
d4e3e04d | 752 | ha->fw_dumped = 1; |
1da177e4 LT |
753 | } |
754 | ||
755 | qla2100_fw_dump_failed: | |
756 | if (!hardware_locked) | |
757 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
758 | } | |
759 | ||
6d9b61ed | 760 | void |
7b867cf7 | 761 | qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
6d9b61ed AV |
762 | { |
763 | int rval; | |
c3a2f0df | 764 | uint32_t cnt; |
6d9b61ed | 765 | uint32_t risc_address; |
7b867cf7 | 766 | struct qla_hw_data *ha = vha->hw; |
6d9b61ed AV |
767 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
768 | uint32_t __iomem *dmp_reg; | |
769 | uint32_t *iter_reg; | |
770 | uint16_t __iomem *mbx_reg; | |
771 | unsigned long flags; | |
772 | struct qla24xx_fw_dump *fw; | |
773 | uint32_t ext_mem_cnt; | |
c3a2f0df | 774 | void *nxt; |
73208dfd | 775 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
6d9b61ed AV |
776 | |
777 | risc_address = ext_mem_cnt = 0; | |
6d9b61ed AV |
778 | flags = 0; |
779 | ||
780 | if (!hardware_locked) | |
781 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
782 | ||
d4e3e04d | 783 | if (!ha->fw_dump) { |
6d9b61ed AV |
784 | qla_printk(KERN_WARNING, ha, |
785 | "No buffer available for dump!!!\n"); | |
786 | goto qla24xx_fw_dump_failed; | |
787 | } | |
788 | ||
789 | if (ha->fw_dumped) { | |
790 | qla_printk(KERN_WARNING, ha, | |
791 | "Firmware has been previously dumped (%p) -- ignoring " | |
d4e3e04d | 792 | "request...\n", ha->fw_dump); |
6d9b61ed AV |
793 | goto qla24xx_fw_dump_failed; |
794 | } | |
a7a167bf AV |
795 | fw = &ha->fw_dump->isp.isp24; |
796 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
6d9b61ed | 797 | |
a7a167bf | 798 | fw->host_status = htonl(RD_REG_DWORD(®->host_status)); |
6d9b61ed AV |
799 | |
800 | /* Pause RISC. */ | |
c81d04c9 AV |
801 | rval = qla24xx_pause_risc(reg); |
802 | if (rval != QLA_SUCCESS) | |
803 | goto qla24xx_fw_dump_failed_0; | |
804 | ||
805 | /* Host interface registers. */ | |
806 | dmp_reg = ®->flash_addr; | |
807 | for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) | |
808 | fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); | |
809 | ||
810 | /* Disable interrupts. */ | |
811 | WRT_REG_DWORD(®->ictrl, 0); | |
812 | RD_REG_DWORD(®->ictrl); | |
813 | ||
814 | /* Shadow registers. */ | |
815 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); | |
816 | RD_REG_DWORD(®->iobase_addr); | |
817 | WRT_REG_DWORD(®->iobase_select, 0xB0000000); | |
818 | fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
819 | ||
820 | WRT_REG_DWORD(®->iobase_select, 0xB0100000); | |
821 | fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
822 | ||
823 | WRT_REG_DWORD(®->iobase_select, 0xB0200000); | |
824 | fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
825 | ||
826 | WRT_REG_DWORD(®->iobase_select, 0xB0300000); | |
827 | fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
828 | ||
829 | WRT_REG_DWORD(®->iobase_select, 0xB0400000); | |
830 | fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
831 | ||
832 | WRT_REG_DWORD(®->iobase_select, 0xB0500000); | |
833 | fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
834 | ||
835 | WRT_REG_DWORD(®->iobase_select, 0xB0600000); | |
836 | fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
837 | ||
838 | /* Mailbox registers. */ | |
839 | mbx_reg = ®->mailbox0; | |
840 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) | |
841 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); | |
842 | ||
843 | /* Transfer sequence registers. */ | |
844 | iter_reg = fw->xseq_gp_reg; | |
845 | iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); | |
846 | iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); | |
847 | iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); | |
848 | iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); | |
849 | iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); | |
850 | iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); | |
851 | iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); | |
852 | qla24xx_read_window(reg, 0xBF70, 16, iter_reg); | |
853 | ||
854 | qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg); | |
855 | qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); | |
856 | ||
857 | /* Receive sequence registers. */ | |
858 | iter_reg = fw->rseq_gp_reg; | |
859 | iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); | |
860 | iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); | |
861 | iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); | |
862 | iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); | |
863 | iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); | |
864 | iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); | |
865 | iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); | |
866 | qla24xx_read_window(reg, 0xFF70, 16, iter_reg); | |
867 | ||
868 | qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg); | |
869 | qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); | |
870 | qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); | |
871 | ||
872 | /* Command DMA registers. */ | |
873 | qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); | |
874 | ||
875 | /* Queues. */ | |
876 | iter_reg = fw->req0_dma_reg; | |
877 | iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); | |
878 | dmp_reg = ®->iobase_q; | |
879 | for (cnt = 0; cnt < 7; cnt++) | |
880 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
881 | ||
882 | iter_reg = fw->resp0_dma_reg; | |
883 | iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); | |
884 | dmp_reg = ®->iobase_q; | |
885 | for (cnt = 0; cnt < 7; cnt++) | |
886 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
887 | ||
888 | iter_reg = fw->req1_dma_reg; | |
889 | iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); | |
890 | dmp_reg = ®->iobase_q; | |
891 | for (cnt = 0; cnt < 7; cnt++) | |
892 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
893 | ||
894 | /* Transmit DMA registers. */ | |
895 | iter_reg = fw->xmt0_dma_reg; | |
896 | iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); | |
897 | qla24xx_read_window(reg, 0x7610, 16, iter_reg); | |
898 | ||
899 | iter_reg = fw->xmt1_dma_reg; | |
900 | iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); | |
901 | qla24xx_read_window(reg, 0x7630, 16, iter_reg); | |
902 | ||
903 | iter_reg = fw->xmt2_dma_reg; | |
904 | iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); | |
905 | qla24xx_read_window(reg, 0x7650, 16, iter_reg); | |
906 | ||
907 | iter_reg = fw->xmt3_dma_reg; | |
908 | iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); | |
909 | qla24xx_read_window(reg, 0x7670, 16, iter_reg); | |
910 | ||
911 | iter_reg = fw->xmt4_dma_reg; | |
912 | iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); | |
913 | qla24xx_read_window(reg, 0x7690, 16, iter_reg); | |
914 | ||
915 | qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); | |
916 | ||
917 | /* Receive DMA registers. */ | |
918 | iter_reg = fw->rcvt0_data_dma_reg; | |
919 | iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); | |
920 | qla24xx_read_window(reg, 0x7710, 16, iter_reg); | |
921 | ||
922 | iter_reg = fw->rcvt1_data_dma_reg; | |
923 | iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); | |
924 | qla24xx_read_window(reg, 0x7730, 16, iter_reg); | |
925 | ||
926 | /* RISC registers. */ | |
927 | iter_reg = fw->risc_gp_reg; | |
928 | iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); | |
929 | iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); | |
930 | iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); | |
931 | iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); | |
932 | iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); | |
933 | iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); | |
934 | iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); | |
935 | qla24xx_read_window(reg, 0x0F70, 16, iter_reg); | |
936 | ||
937 | /* Local memory controller registers. */ | |
938 | iter_reg = fw->lmc_reg; | |
939 | iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); | |
940 | iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); | |
941 | iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); | |
942 | iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); | |
943 | iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); | |
944 | iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); | |
945 | qla24xx_read_window(reg, 0x3060, 16, iter_reg); | |
946 | ||
947 | /* Fibre Protocol Module registers. */ | |
948 | iter_reg = fw->fpm_hdw_reg; | |
949 | iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); | |
950 | iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); | |
951 | iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); | |
952 | iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); | |
953 | iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); | |
954 | iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); | |
955 | iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); | |
956 | iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); | |
957 | iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); | |
958 | iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); | |
959 | iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); | |
960 | qla24xx_read_window(reg, 0x40B0, 16, iter_reg); | |
961 | ||
962 | /* Frame Buffer registers. */ | |
963 | iter_reg = fw->fb_hdw_reg; | |
964 | iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); | |
965 | iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); | |
966 | iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); | |
967 | iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); | |
968 | iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); | |
969 | iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); | |
970 | iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); | |
971 | iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); | |
972 | iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); | |
973 | iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); | |
974 | qla24xx_read_window(reg, 0x61B0, 16, iter_reg); | |
975 | ||
976 | rval = qla24xx_soft_reset(ha); | |
977 | if (rval != QLA_SUCCESS) | |
978 | goto qla24xx_fw_dump_failed_0; | |
979 | ||
980 | rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), | |
c5722708 | 981 | &nxt); |
c81d04c9 AV |
982 | if (rval != QLA_SUCCESS) |
983 | goto qla24xx_fw_dump_failed_0; | |
984 | ||
73208dfd | 985 | nxt = qla2xxx_copy_queues(ha, nxt); |
bb99de67 AV |
986 | |
987 | qla24xx_copy_eft(ha, nxt); | |
c81d04c9 AV |
988 | |
989 | qla24xx_fw_dump_failed_0: | |
c3a2f0df AV |
990 | if (rval != QLA_SUCCESS) { |
991 | qla_printk(KERN_WARNING, ha, | |
992 | "Failed to dump firmware (%x)!!!\n", rval); | |
993 | ha->fw_dumped = 0; | |
6d9b61ed | 994 | |
c3a2f0df AV |
995 | } else { |
996 | qla_printk(KERN_INFO, ha, | |
997 | "Firmware dump saved to temp buffer (%ld/%p).\n", | |
73208dfd | 998 | base_vha->host_no, ha->fw_dump); |
c3a2f0df AV |
999 | ha->fw_dumped = 1; |
1000 | } | |
6d9b61ed | 1001 | |
c3a2f0df AV |
1002 | qla24xx_fw_dump_failed: |
1003 | if (!hardware_locked) | |
1004 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1005 | } | |
6d9b61ed | 1006 | |
c3a2f0df | 1007 | void |
7b867cf7 | 1008 | qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
c3a2f0df AV |
1009 | { |
1010 | int rval; | |
1011 | uint32_t cnt; | |
1012 | uint32_t risc_address; | |
7b867cf7 | 1013 | struct qla_hw_data *ha = vha->hw; |
c3a2f0df AV |
1014 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
1015 | uint32_t __iomem *dmp_reg; | |
1016 | uint32_t *iter_reg; | |
1017 | uint16_t __iomem *mbx_reg; | |
1018 | unsigned long flags; | |
1019 | struct qla25xx_fw_dump *fw; | |
1020 | uint32_t ext_mem_cnt; | |
d63ab533 | 1021 | void *nxt, *nxt_chain; |
bb99de67 | 1022 | uint32_t *last_chain = NULL; |
73208dfd | 1023 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
6d9b61ed | 1024 | |
c3a2f0df AV |
1025 | risc_address = ext_mem_cnt = 0; |
1026 | flags = 0; | |
6d9b61ed | 1027 | |
c3a2f0df AV |
1028 | if (!hardware_locked) |
1029 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
6d9b61ed | 1030 | |
c3a2f0df AV |
1031 | if (!ha->fw_dump) { |
1032 | qla_printk(KERN_WARNING, ha, | |
1033 | "No buffer available for dump!!!\n"); | |
1034 | goto qla25xx_fw_dump_failed; | |
1035 | } | |
6d9b61ed | 1036 | |
c3a2f0df AV |
1037 | if (ha->fw_dumped) { |
1038 | qla_printk(KERN_WARNING, ha, | |
1039 | "Firmware has been previously dumped (%p) -- ignoring " | |
1040 | "request...\n", ha->fw_dump); | |
1041 | goto qla25xx_fw_dump_failed; | |
1042 | } | |
1043 | fw = &ha->fw_dump->isp.isp25; | |
1044 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
b5836927 | 1045 | ha->fw_dump->version = __constant_htonl(2); |
6d9b61ed | 1046 | |
c3a2f0df | 1047 | fw->host_status = htonl(RD_REG_DWORD(®->host_status)); |
6d9b61ed | 1048 | |
c3a2f0df | 1049 | /* Pause RISC. */ |
c81d04c9 AV |
1050 | rval = qla24xx_pause_risc(reg); |
1051 | if (rval != QLA_SUCCESS) | |
1052 | goto qla25xx_fw_dump_failed_0; | |
1053 | ||
b5836927 AV |
1054 | /* Host/Risc registers. */ |
1055 | iter_reg = fw->host_risc_reg; | |
1056 | iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); | |
1057 | qla24xx_read_window(reg, 0x7010, 16, iter_reg); | |
1058 | ||
1059 | /* PCIe registers. */ | |
1060 | WRT_REG_DWORD(®->iobase_addr, 0x7C00); | |
1061 | RD_REG_DWORD(®->iobase_addr); | |
1062 | WRT_REG_DWORD(®->iobase_window, 0x01); | |
1063 | dmp_reg = ®->iobase_c4; | |
1064 | fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1065 | fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1066 | fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); | |
1067 | fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); | |
73208dfd | 1068 | |
b5836927 AV |
1069 | WRT_REG_DWORD(®->iobase_window, 0x00); |
1070 | RD_REG_DWORD(®->iobase_window); | |
1071 | ||
c81d04c9 AV |
1072 | /* Host interface registers. */ |
1073 | dmp_reg = ®->flash_addr; | |
1074 | for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) | |
1075 | fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1076 | ||
1077 | /* Disable interrupts. */ | |
1078 | WRT_REG_DWORD(®->ictrl, 0); | |
1079 | RD_REG_DWORD(®->ictrl); | |
1080 | ||
1081 | /* Shadow registers. */ | |
1082 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); | |
1083 | RD_REG_DWORD(®->iobase_addr); | |
1084 | WRT_REG_DWORD(®->iobase_select, 0xB0000000); | |
1085 | fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1086 | ||
1087 | WRT_REG_DWORD(®->iobase_select, 0xB0100000); | |
1088 | fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1089 | ||
1090 | WRT_REG_DWORD(®->iobase_select, 0xB0200000); | |
1091 | fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1092 | ||
1093 | WRT_REG_DWORD(®->iobase_select, 0xB0300000); | |
1094 | fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1095 | ||
1096 | WRT_REG_DWORD(®->iobase_select, 0xB0400000); | |
1097 | fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1098 | ||
1099 | WRT_REG_DWORD(®->iobase_select, 0xB0500000); | |
1100 | fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1101 | ||
1102 | WRT_REG_DWORD(®->iobase_select, 0xB0600000); | |
1103 | fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1104 | ||
1105 | WRT_REG_DWORD(®->iobase_select, 0xB0700000); | |
1106 | fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1107 | ||
1108 | WRT_REG_DWORD(®->iobase_select, 0xB0800000); | |
1109 | fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1110 | ||
1111 | WRT_REG_DWORD(®->iobase_select, 0xB0900000); | |
1112 | fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1113 | ||
1114 | WRT_REG_DWORD(®->iobase_select, 0xB0A00000); | |
1115 | fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1116 | ||
1117 | /* RISC I/O register. */ | |
1118 | WRT_REG_DWORD(®->iobase_addr, 0x0010); | |
1119 | fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); | |
1120 | ||
1121 | /* Mailbox registers. */ | |
1122 | mbx_reg = ®->mailbox0; | |
1123 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) | |
1124 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); | |
1125 | ||
1126 | /* Transfer sequence registers. */ | |
1127 | iter_reg = fw->xseq_gp_reg; | |
1128 | iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); | |
1129 | iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); | |
1130 | iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); | |
1131 | iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); | |
1132 | iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); | |
1133 | iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); | |
1134 | iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); | |
1135 | qla24xx_read_window(reg, 0xBF70, 16, iter_reg); | |
1136 | ||
1137 | iter_reg = fw->xseq_0_reg; | |
1138 | iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); | |
1139 | iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); | |
1140 | qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); | |
1141 | ||
1142 | qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); | |
1143 | ||
1144 | /* Receive sequence registers. */ | |
1145 | iter_reg = fw->rseq_gp_reg; | |
1146 | iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); | |
1147 | iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); | |
1148 | iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); | |
1149 | iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); | |
1150 | iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); | |
1151 | iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); | |
1152 | iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); | |
1153 | qla24xx_read_window(reg, 0xFF70, 16, iter_reg); | |
1154 | ||
1155 | iter_reg = fw->rseq_0_reg; | |
1156 | iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); | |
1157 | qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); | |
1158 | ||
1159 | qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); | |
1160 | qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); | |
1161 | ||
1162 | /* Auxiliary sequence registers. */ | |
1163 | iter_reg = fw->aseq_gp_reg; | |
1164 | iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); | |
1165 | iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); | |
1166 | iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); | |
1167 | iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); | |
1168 | iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); | |
1169 | iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); | |
1170 | iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); | |
1171 | qla24xx_read_window(reg, 0xB070, 16, iter_reg); | |
1172 | ||
1173 | iter_reg = fw->aseq_0_reg; | |
1174 | iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); | |
1175 | qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); | |
1176 | ||
1177 | qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); | |
1178 | qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); | |
1179 | ||
1180 | /* Command DMA registers. */ | |
1181 | qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); | |
1182 | ||
1183 | /* Queues. */ | |
1184 | iter_reg = fw->req0_dma_reg; | |
1185 | iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); | |
1186 | dmp_reg = ®->iobase_q; | |
1187 | for (cnt = 0; cnt < 7; cnt++) | |
1188 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1189 | ||
1190 | iter_reg = fw->resp0_dma_reg; | |
1191 | iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); | |
1192 | dmp_reg = ®->iobase_q; | |
1193 | for (cnt = 0; cnt < 7; cnt++) | |
1194 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1195 | ||
1196 | iter_reg = fw->req1_dma_reg; | |
1197 | iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); | |
1198 | dmp_reg = ®->iobase_q; | |
1199 | for (cnt = 0; cnt < 7; cnt++) | |
1200 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1201 | ||
1202 | /* Transmit DMA registers. */ | |
1203 | iter_reg = fw->xmt0_dma_reg; | |
1204 | iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); | |
1205 | qla24xx_read_window(reg, 0x7610, 16, iter_reg); | |
1206 | ||
1207 | iter_reg = fw->xmt1_dma_reg; | |
1208 | iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); | |
1209 | qla24xx_read_window(reg, 0x7630, 16, iter_reg); | |
1210 | ||
1211 | iter_reg = fw->xmt2_dma_reg; | |
1212 | iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); | |
1213 | qla24xx_read_window(reg, 0x7650, 16, iter_reg); | |
1214 | ||
1215 | iter_reg = fw->xmt3_dma_reg; | |
1216 | iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); | |
1217 | qla24xx_read_window(reg, 0x7670, 16, iter_reg); | |
1218 | ||
1219 | iter_reg = fw->xmt4_dma_reg; | |
1220 | iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); | |
1221 | qla24xx_read_window(reg, 0x7690, 16, iter_reg); | |
1222 | ||
1223 | qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); | |
1224 | ||
1225 | /* Receive DMA registers. */ | |
1226 | iter_reg = fw->rcvt0_data_dma_reg; | |
1227 | iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); | |
1228 | qla24xx_read_window(reg, 0x7710, 16, iter_reg); | |
1229 | ||
1230 | iter_reg = fw->rcvt1_data_dma_reg; | |
1231 | iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); | |
1232 | qla24xx_read_window(reg, 0x7730, 16, iter_reg); | |
1233 | ||
1234 | /* RISC registers. */ | |
1235 | iter_reg = fw->risc_gp_reg; | |
1236 | iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); | |
1237 | iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); | |
1238 | iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); | |
1239 | iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); | |
1240 | iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); | |
1241 | iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); | |
1242 | iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); | |
1243 | qla24xx_read_window(reg, 0x0F70, 16, iter_reg); | |
1244 | ||
1245 | /* Local memory controller registers. */ | |
1246 | iter_reg = fw->lmc_reg; | |
1247 | iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); | |
1248 | iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); | |
1249 | iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); | |
1250 | iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); | |
1251 | iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); | |
1252 | iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); | |
1253 | iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); | |
1254 | qla24xx_read_window(reg, 0x3070, 16, iter_reg); | |
1255 | ||
1256 | /* Fibre Protocol Module registers. */ | |
1257 | iter_reg = fw->fpm_hdw_reg; | |
1258 | iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); | |
1259 | iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); | |
1260 | iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); | |
1261 | iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); | |
1262 | iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); | |
1263 | iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); | |
1264 | iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); | |
1265 | iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); | |
1266 | iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); | |
1267 | iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); | |
1268 | iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); | |
1269 | qla24xx_read_window(reg, 0x40B0, 16, iter_reg); | |
1270 | ||
1271 | /* Frame Buffer registers. */ | |
1272 | iter_reg = fw->fb_hdw_reg; | |
1273 | iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); | |
1274 | iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); | |
1275 | iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); | |
1276 | iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); | |
1277 | iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); | |
1278 | iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); | |
1279 | iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); | |
1280 | iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); | |
1281 | iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); | |
1282 | iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); | |
1283 | iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); | |
1284 | qla24xx_read_window(reg, 0x6F00, 16, iter_reg); | |
1285 | ||
d63ab533 AV |
1286 | /* Multi queue registers */ |
1287 | nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, | |
1288 | &last_chain); | |
1289 | ||
c81d04c9 AV |
1290 | rval = qla24xx_soft_reset(ha); |
1291 | if (rval != QLA_SUCCESS) | |
1292 | goto qla25xx_fw_dump_failed_0; | |
1293 | ||
1294 | rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), | |
c5722708 | 1295 | &nxt); |
c81d04c9 AV |
1296 | if (rval != QLA_SUCCESS) |
1297 | goto qla25xx_fw_dump_failed_0; | |
1298 | ||
73208dfd | 1299 | nxt = qla2xxx_copy_queues(ha, nxt); |
c81d04c9 | 1300 | |
bb99de67 | 1301 | nxt = qla24xx_copy_eft(ha, nxt); |
df613b96 | 1302 | |
d63ab533 AV |
1303 | /* Chain entries -- started with MQ. */ |
1304 | qla25xx_copy_fce(ha, nxt_chain, &last_chain); | |
bb99de67 AV |
1305 | if (last_chain) { |
1306 | ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT); | |
1307 | *last_chain |= __constant_htonl(DUMP_CHAIN_LAST); | |
1308 | } | |
df613b96 | 1309 | |
c81d04c9 | 1310 | qla25xx_fw_dump_failed_0: |
c3a2f0df AV |
1311 | if (rval != QLA_SUCCESS) { |
1312 | qla_printk(KERN_WARNING, ha, | |
1313 | "Failed to dump firmware (%x)!!!\n", rval); | |
1314 | ha->fw_dumped = 0; | |
6d9b61ed AV |
1315 | |
1316 | } else { | |
1317 | qla_printk(KERN_INFO, ha, | |
1318 | "Firmware dump saved to temp buffer (%ld/%p).\n", | |
73208dfd | 1319 | base_vha->host_no, ha->fw_dump); |
6d9b61ed AV |
1320 | ha->fw_dumped = 1; |
1321 | } | |
1322 | ||
c3a2f0df | 1323 | qla25xx_fw_dump_failed: |
6d9b61ed AV |
1324 | if (!hardware_locked) |
1325 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1326 | } | |
3a03eb79 AV |
1327 | |
1328 | void | |
1329 | qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) | |
1330 | { | |
1331 | int rval; | |
1332 | uint32_t cnt; | |
1333 | uint32_t risc_address; | |
1334 | struct qla_hw_data *ha = vha->hw; | |
1335 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
1336 | uint32_t __iomem *dmp_reg; | |
1337 | uint32_t *iter_reg; | |
1338 | uint16_t __iomem *mbx_reg; | |
1339 | unsigned long flags; | |
1340 | struct qla81xx_fw_dump *fw; | |
1341 | uint32_t ext_mem_cnt; | |
1342 | void *nxt, *nxt_chain; | |
1343 | uint32_t *last_chain = NULL; | |
1344 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); | |
1345 | ||
1346 | risc_address = ext_mem_cnt = 0; | |
1347 | flags = 0; | |
1348 | ||
1349 | if (!hardware_locked) | |
1350 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1351 | ||
1352 | if (!ha->fw_dump) { | |
1353 | qla_printk(KERN_WARNING, ha, | |
1354 | "No buffer available for dump!!!\n"); | |
1355 | goto qla81xx_fw_dump_failed; | |
1356 | } | |
1357 | ||
1358 | if (ha->fw_dumped) { | |
1359 | qla_printk(KERN_WARNING, ha, | |
1360 | "Firmware has been previously dumped (%p) -- ignoring " | |
1361 | "request...\n", ha->fw_dump); | |
1362 | goto qla81xx_fw_dump_failed; | |
1363 | } | |
1364 | fw = &ha->fw_dump->isp.isp81; | |
1365 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
1366 | ||
1367 | fw->host_status = htonl(RD_REG_DWORD(®->host_status)); | |
1368 | ||
1369 | /* Pause RISC. */ | |
1370 | rval = qla24xx_pause_risc(reg); | |
1371 | if (rval != QLA_SUCCESS) | |
1372 | goto qla81xx_fw_dump_failed_0; | |
1373 | ||
1374 | /* Host/Risc registers. */ | |
1375 | iter_reg = fw->host_risc_reg; | |
1376 | iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); | |
1377 | qla24xx_read_window(reg, 0x7010, 16, iter_reg); | |
1378 | ||
1379 | /* PCIe registers. */ | |
1380 | WRT_REG_DWORD(®->iobase_addr, 0x7C00); | |
1381 | RD_REG_DWORD(®->iobase_addr); | |
1382 | WRT_REG_DWORD(®->iobase_window, 0x01); | |
1383 | dmp_reg = ®->iobase_c4; | |
1384 | fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1385 | fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1386 | fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); | |
1387 | fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); | |
1388 | ||
1389 | WRT_REG_DWORD(®->iobase_window, 0x00); | |
1390 | RD_REG_DWORD(®->iobase_window); | |
1391 | ||
1392 | /* Host interface registers. */ | |
1393 | dmp_reg = ®->flash_addr; | |
1394 | for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) | |
1395 | fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1396 | ||
1397 | /* Disable interrupts. */ | |
1398 | WRT_REG_DWORD(®->ictrl, 0); | |
1399 | RD_REG_DWORD(®->ictrl); | |
1400 | ||
1401 | /* Shadow registers. */ | |
1402 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); | |
1403 | RD_REG_DWORD(®->iobase_addr); | |
1404 | WRT_REG_DWORD(®->iobase_select, 0xB0000000); | |
1405 | fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1406 | ||
1407 | WRT_REG_DWORD(®->iobase_select, 0xB0100000); | |
1408 | fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1409 | ||
1410 | WRT_REG_DWORD(®->iobase_select, 0xB0200000); | |
1411 | fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1412 | ||
1413 | WRT_REG_DWORD(®->iobase_select, 0xB0300000); | |
1414 | fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1415 | ||
1416 | WRT_REG_DWORD(®->iobase_select, 0xB0400000); | |
1417 | fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1418 | ||
1419 | WRT_REG_DWORD(®->iobase_select, 0xB0500000); | |
1420 | fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1421 | ||
1422 | WRT_REG_DWORD(®->iobase_select, 0xB0600000); | |
1423 | fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1424 | ||
1425 | WRT_REG_DWORD(®->iobase_select, 0xB0700000); | |
1426 | fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1427 | ||
1428 | WRT_REG_DWORD(®->iobase_select, 0xB0800000); | |
1429 | fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1430 | ||
1431 | WRT_REG_DWORD(®->iobase_select, 0xB0900000); | |
1432 | fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1433 | ||
1434 | WRT_REG_DWORD(®->iobase_select, 0xB0A00000); | |
1435 | fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1436 | ||
1437 | /* RISC I/O register. */ | |
1438 | WRT_REG_DWORD(®->iobase_addr, 0x0010); | |
1439 | fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); | |
1440 | ||
1441 | /* Mailbox registers. */ | |
1442 | mbx_reg = ®->mailbox0; | |
1443 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) | |
1444 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); | |
1445 | ||
1446 | /* Transfer sequence registers. */ | |
1447 | iter_reg = fw->xseq_gp_reg; | |
1448 | iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); | |
1449 | iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); | |
1450 | iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); | |
1451 | iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); | |
1452 | iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); | |
1453 | iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); | |
1454 | iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); | |
1455 | qla24xx_read_window(reg, 0xBF70, 16, iter_reg); | |
1456 | ||
1457 | iter_reg = fw->xseq_0_reg; | |
1458 | iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); | |
1459 | iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); | |
1460 | qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); | |
1461 | ||
1462 | qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); | |
1463 | ||
1464 | /* Receive sequence registers. */ | |
1465 | iter_reg = fw->rseq_gp_reg; | |
1466 | iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); | |
1467 | iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); | |
1468 | iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); | |
1469 | iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); | |
1470 | iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); | |
1471 | iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); | |
1472 | iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); | |
1473 | qla24xx_read_window(reg, 0xFF70, 16, iter_reg); | |
1474 | ||
1475 | iter_reg = fw->rseq_0_reg; | |
1476 | iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); | |
1477 | qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); | |
1478 | ||
1479 | qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); | |
1480 | qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); | |
1481 | ||
1482 | /* Auxiliary sequence registers. */ | |
1483 | iter_reg = fw->aseq_gp_reg; | |
1484 | iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); | |
1485 | iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); | |
1486 | iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); | |
1487 | iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); | |
1488 | iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); | |
1489 | iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); | |
1490 | iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); | |
1491 | qla24xx_read_window(reg, 0xB070, 16, iter_reg); | |
1492 | ||
1493 | iter_reg = fw->aseq_0_reg; | |
1494 | iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); | |
1495 | qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); | |
1496 | ||
1497 | qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); | |
1498 | qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); | |
1499 | ||
1500 | /* Command DMA registers. */ | |
1501 | qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); | |
1502 | ||
1503 | /* Queues. */ | |
1504 | iter_reg = fw->req0_dma_reg; | |
1505 | iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); | |
1506 | dmp_reg = ®->iobase_q; | |
1507 | for (cnt = 0; cnt < 7; cnt++) | |
1508 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1509 | ||
1510 | iter_reg = fw->resp0_dma_reg; | |
1511 | iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); | |
1512 | dmp_reg = ®->iobase_q; | |
1513 | for (cnt = 0; cnt < 7; cnt++) | |
1514 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1515 | ||
1516 | iter_reg = fw->req1_dma_reg; | |
1517 | iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); | |
1518 | dmp_reg = ®->iobase_q; | |
1519 | for (cnt = 0; cnt < 7; cnt++) | |
1520 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1521 | ||
1522 | /* Transmit DMA registers. */ | |
1523 | iter_reg = fw->xmt0_dma_reg; | |
1524 | iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); | |
1525 | qla24xx_read_window(reg, 0x7610, 16, iter_reg); | |
1526 | ||
1527 | iter_reg = fw->xmt1_dma_reg; | |
1528 | iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); | |
1529 | qla24xx_read_window(reg, 0x7630, 16, iter_reg); | |
1530 | ||
1531 | iter_reg = fw->xmt2_dma_reg; | |
1532 | iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); | |
1533 | qla24xx_read_window(reg, 0x7650, 16, iter_reg); | |
1534 | ||
1535 | iter_reg = fw->xmt3_dma_reg; | |
1536 | iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); | |
1537 | qla24xx_read_window(reg, 0x7670, 16, iter_reg); | |
1538 | ||
1539 | iter_reg = fw->xmt4_dma_reg; | |
1540 | iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); | |
1541 | qla24xx_read_window(reg, 0x7690, 16, iter_reg); | |
1542 | ||
1543 | qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); | |
1544 | ||
1545 | /* Receive DMA registers. */ | |
1546 | iter_reg = fw->rcvt0_data_dma_reg; | |
1547 | iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); | |
1548 | qla24xx_read_window(reg, 0x7710, 16, iter_reg); | |
1549 | ||
1550 | iter_reg = fw->rcvt1_data_dma_reg; | |
1551 | iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); | |
1552 | qla24xx_read_window(reg, 0x7730, 16, iter_reg); | |
1553 | ||
1554 | /* RISC registers. */ | |
1555 | iter_reg = fw->risc_gp_reg; | |
1556 | iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); | |
1557 | iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); | |
1558 | iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); | |
1559 | iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); | |
1560 | iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); | |
1561 | iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); | |
1562 | iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); | |
1563 | qla24xx_read_window(reg, 0x0F70, 16, iter_reg); | |
1564 | ||
1565 | /* Local memory controller registers. */ | |
1566 | iter_reg = fw->lmc_reg; | |
1567 | iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); | |
1568 | iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); | |
1569 | iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); | |
1570 | iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); | |
1571 | iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); | |
1572 | iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); | |
1573 | iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); | |
1574 | qla24xx_read_window(reg, 0x3070, 16, iter_reg); | |
1575 | ||
1576 | /* Fibre Protocol Module registers. */ | |
1577 | iter_reg = fw->fpm_hdw_reg; | |
1578 | iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); | |
1579 | iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); | |
1580 | iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); | |
1581 | iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); | |
1582 | iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); | |
1583 | iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); | |
1584 | iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); | |
1585 | iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); | |
1586 | iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); | |
1587 | iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); | |
1588 | iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); | |
1589 | iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg); | |
1590 | iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg); | |
1591 | qla24xx_read_window(reg, 0x40D0, 16, iter_reg); | |
1592 | ||
1593 | /* Frame Buffer registers. */ | |
1594 | iter_reg = fw->fb_hdw_reg; | |
1595 | iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); | |
1596 | iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); | |
1597 | iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); | |
1598 | iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); | |
1599 | iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); | |
1600 | iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); | |
1601 | iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); | |
1602 | iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); | |
1603 | iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); | |
1604 | iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); | |
1605 | iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); | |
1606 | iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg); | |
1607 | qla24xx_read_window(reg, 0x6F00, 16, iter_reg); | |
1608 | ||
1609 | /* Multi queue registers */ | |
1610 | nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, | |
1611 | &last_chain); | |
1612 | ||
1613 | rval = qla24xx_soft_reset(ha); | |
1614 | if (rval != QLA_SUCCESS) | |
1615 | goto qla81xx_fw_dump_failed_0; | |
1616 | ||
1617 | rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), | |
1618 | &nxt); | |
1619 | if (rval != QLA_SUCCESS) | |
1620 | goto qla81xx_fw_dump_failed_0; | |
1621 | ||
1622 | nxt = qla2xxx_copy_queues(ha, nxt); | |
1623 | ||
1624 | nxt = qla24xx_copy_eft(ha, nxt); | |
1625 | ||
1626 | /* Chain entries -- started with MQ. */ | |
1627 | qla25xx_copy_fce(ha, nxt_chain, &last_chain); | |
1628 | if (last_chain) { | |
1629 | ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT); | |
1630 | *last_chain |= __constant_htonl(DUMP_CHAIN_LAST); | |
1631 | } | |
1632 | ||
1633 | qla81xx_fw_dump_failed_0: | |
1634 | if (rval != QLA_SUCCESS) { | |
1635 | qla_printk(KERN_WARNING, ha, | |
1636 | "Failed to dump firmware (%x)!!!\n", rval); | |
1637 | ha->fw_dumped = 0; | |
1638 | ||
1639 | } else { | |
1640 | qla_printk(KERN_INFO, ha, | |
1641 | "Firmware dump saved to temp buffer (%ld/%p).\n", | |
1642 | base_vha->host_no, ha->fw_dump); | |
1643 | ha->fw_dumped = 1; | |
1644 | } | |
1645 | ||
1646 | qla81xx_fw_dump_failed: | |
1647 | if (!hardware_locked) | |
1648 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1649 | } | |
1650 | ||
1da177e4 LT |
1651 | /****************************************************************************/ |
1652 | /* Driver Debug Functions. */ | |
1653 | /****************************************************************************/ | |
1654 | ||
fa2a1ce5 | 1655 | void |
7b867cf7 | 1656 | qla2x00_dump_regs(scsi_qla_host_t *vha) |
1da177e4 | 1657 | { |
6afd9763 | 1658 | int i; |
7b867cf7 | 1659 | struct qla_hw_data *ha = vha->hw; |
3d71644c | 1660 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
6afd9763 AV |
1661 | struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; |
1662 | uint16_t __iomem *mbx_reg; | |
1663 | ||
1664 | mbx_reg = IS_FWI2_CAPABLE(ha) ? ®24->mailbox0: | |
1665 | MAILBOX_REG(ha, reg, 0); | |
1da177e4 LT |
1666 | |
1667 | printk("Mailbox registers:\n"); | |
6afd9763 | 1668 | for (i = 0; i < 6; i++) |
7b867cf7 | 1669 | printk("scsi(%ld): mbox %d 0x%04x \n", vha->host_no, i, |
6afd9763 | 1670 | RD_REG_WORD(mbx_reg++)); |
1da177e4 LT |
1671 | } |
1672 | ||
1673 | ||
1674 | void | |
fa2a1ce5 | 1675 | qla2x00_dump_buffer(uint8_t * b, uint32_t size) |
1da177e4 LT |
1676 | { |
1677 | uint32_t cnt; | |
1678 | uint8_t c; | |
1679 | ||
1680 | printk(" 0 1 2 3 4 5 6 7 8 9 " | |
1681 | "Ah Bh Ch Dh Eh Fh\n"); | |
1682 | printk("----------------------------------------" | |
1683 | "----------------------\n"); | |
1684 | ||
1685 | for (cnt = 0; cnt < size;) { | |
1686 | c = *b++; | |
1687 | printk("%02x",(uint32_t) c); | |
1688 | cnt++; | |
1689 | if (!(cnt % 16)) | |
1690 | printk("\n"); | |
1691 | else | |
1692 | printk(" "); | |
1693 | } | |
1694 | if (cnt % 16) | |
1695 | printk("\n"); | |
1696 | } | |
73208dfd AC |
1697 | |
1698 |