projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 | 1 | /* |
| fa90c54f | 2 | * QLogic Fibre Channel HBA Driver |
| 07e264b7 | 3 | * Copyright (c) 2003-2011 QLogic Corporation |
| 1da177e4 | 4 | * |
| fa90c54f | 5 | * See LICENSE.qla2xxx for copyright and licensing details. |
| 1da177e4 | 6 | */ |
| 3ce8866c SK |
7 | |
| 8 | /* | |
| 9 | * Table for showing the current message id in use for particular level | |
| 10 | * Change this table for addition of log/debug messages. | |
| e02587d7 AE |
11 | * ---------------------------------------------------------------------- |
| 12 | * | Level | Last Value Used | Holes | | |
| 13 | * ---------------------------------------------------------------------- | |
| 0b91d116 | 14 | * | Module Init and Probe | 0x0120 | 0x4b,0xba,0xfa | |
| af11f64d AV |
15 | * | Mailbox commands | 0x113e | 0x112c-0x112e | |
| 16 | * | | | 0x113a | | |
| 557cf785 | 17 | * | Device Discovery | 0x2086 | 0x2020-0x2022 | |
| 4aee5766 | 18 | * | Queue Command and IO tracing | 0x3030 | 0x3006,0x3008 | |
| 6246b8a1 | 19 | * | | | 0x302d-0x302e | |
| e02587d7 | 20 | * | DPC Thread | 0x401c | | |
| 3256b435 | 21 | * | Async Events | 0x505d | 0x502b-0x502f | |
| 9ba56b95 | 22 | * | | | 0x5047,0x5052 | |
| 6246b8a1 | 23 | * | Timer Routines | 0x6011 | 0x600e-0x600f | |
| 733a95bd JC |
24 | * | User Space Interactions | 0x709f | 0x7018,0x702e, | |
| 25 | * | | | 0x7039,0x7045, | | |
| 26 | * | | | 0x7073-0x7075, | | |
| 27 | * | | | 0x708c | | |
| cfb0919c CD |
28 | * | Task Management | 0x803c | 0x8025-0x8026 | |
| 29 | * | | | 0x800b,0x8039 | | |
| e02587d7 AE |
30 | * | AER/EEH | 0x900f | | |
| 31 | * | Virtual Port | 0xa007 | | | |
| 3256b435 | 32 | * | ISP82XX Specific | 0xb054 | 0xb053 | |
| 6246b8a1 GM |
33 | * | MultiQ | 0xc00c | | |
| 34 | * | Misc | 0xd010 | | | |
| e02587d7 | 35 | * ---------------------------------------------------------------------- |
| 3ce8866c SK |
36 | */ |
| 37 | ||
| 1da177e4 LT |
38 | #include "qla_def.h" |
| 39 | ||
| 40 | #include <linux/delay.h> | |
| 41 | ||
| 3ce8866c SK |
42 | static uint32_t ql_dbg_offset = 0x800; |
| 43 | ||
| a7a167bf | 44 | static inline void |
| 7b867cf7 | 45 | qla2xxx_prep_dump(struct qla_hw_data *ha, struct qla2xxx_fw_dump *fw_dump) |
| a7a167bf AV |
46 | { |
| 47 | fw_dump->fw_major_version = htonl(ha->fw_major_version); | |
| 48 | fw_dump->fw_minor_version = htonl(ha->fw_minor_version); | |
| 49 | fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version); | |
| 50 | fw_dump->fw_attributes = htonl(ha->fw_attributes); | |
| 51 | ||
| 52 | fw_dump->vendor = htonl(ha->pdev->vendor); | |
| 53 | fw_dump->device = htonl(ha->pdev->device); | |
| 54 | fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor); | |
| 55 | fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device); | |
| 56 | } | |
| 57 | ||
| 58 | static inline void * | |
| 73208dfd | 59 | qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr) |
| a7a167bf | 60 | { |
| 73208dfd AC |
61 | struct req_que *req = ha->req_q_map[0]; |
| 62 | struct rsp_que *rsp = ha->rsp_q_map[0]; | |
| a7a167bf | 63 | /* Request queue. */ |
| 7b867cf7 | 64 | memcpy(ptr, req->ring, req->length * |
| a7a167bf AV |
65 | sizeof(request_t)); |
| 66 | ||
| 67 | /* Response queue. */ | |
| 7b867cf7 AC |
68 | ptr += req->length * sizeof(request_t); |
| 69 | memcpy(ptr, rsp->ring, rsp->length * | |
| a7a167bf AV |
70 | sizeof(response_t)); |
| 71 | ||
| 7b867cf7 | 72 | return ptr + (rsp->length * sizeof(response_t)); |
| a7a167bf | 73 | } |
| 1da177e4 | 74 | |
| c3a2f0df | 75 | static int |
| 7b867cf7 | 76 | qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram, |
| c5722708 | 77 | uint32_t ram_dwords, void **nxt) |
| c3a2f0df AV |
78 | { |
| 79 | int rval; | |
| c5722708 AV |
80 | uint32_t cnt, stat, timer, dwords, idx; |
| 81 | uint16_t mb0; | |
| c3a2f0df | 82 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
| c5722708 AV |
83 | dma_addr_t dump_dma = ha->gid_list_dma; |
| 84 | uint32_t *dump = (uint32_t *)ha->gid_list; | |
| c3a2f0df AV |
85 | |
| 86 | rval = QLA_SUCCESS; | |
| c5722708 | 87 | mb0 = 0; |
| c3a2f0df | 88 | |
| c5722708 | 89 | WRT_REG_WORD(®->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED); |
| c3a2f0df AV |
90 | clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); |
| 91 | ||
| 642ef983 | 92 | dwords = qla2x00_gid_list_size(ha) / 4; |
| c5722708 AV |
93 | for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS; |
| 94 | cnt += dwords, addr += dwords) { | |
| 95 | if (cnt + dwords > ram_dwords) | |
| 96 | dwords = ram_dwords - cnt; | |
| c3a2f0df | 97 | |
| c5722708 AV |
98 | WRT_REG_WORD(®->mailbox1, LSW(addr)); |
| 99 | WRT_REG_WORD(®->mailbox8, MSW(addr)); | |
| c3a2f0df | 100 | |
| c5722708 AV |
101 | WRT_REG_WORD(®->mailbox2, MSW(dump_dma)); |
| 102 | WRT_REG_WORD(®->mailbox3, LSW(dump_dma)); | |
| 103 | WRT_REG_WORD(®->mailbox6, MSW(MSD(dump_dma))); | |
| 104 | WRT_REG_WORD(®->mailbox7, LSW(MSD(dump_dma))); | |
| c3a2f0df | 105 | |
| c5722708 AV |
106 | WRT_REG_WORD(®->mailbox4, MSW(dwords)); |
| 107 | WRT_REG_WORD(®->mailbox5, LSW(dwords)); | |
| c3a2f0df AV |
108 | WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); |
| 109 | ||
| 110 | for (timer = 6000000; timer; timer--) { | |
| 111 | /* Check for pending interrupts. */ | |
| 112 | stat = RD_REG_DWORD(®->host_status); | |
| 113 | if (stat & HSRX_RISC_INT) { | |
| 114 | stat &= 0xff; | |
| 115 | ||
| 116 | if (stat == 0x1 || stat == 0x2 || | |
| 117 | stat == 0x10 || stat == 0x11) { | |
| 118 | set_bit(MBX_INTERRUPT, | |
| 119 | &ha->mbx_cmd_flags); | |
| 120 | ||
| c5722708 | 121 | mb0 = RD_REG_WORD(®->mailbox0); |
| c3a2f0df AV |
122 | |
| 123 | WRT_REG_DWORD(®->hccr, | |
| 124 | HCCRX_CLR_RISC_INT); | |
| 125 | RD_REG_DWORD(®->hccr); | |
| 126 | break; | |
| 127 | } | |
| 128 | ||
| 129 | /* Clear this intr; it wasn't a mailbox intr */ | |
| 130 | WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); | |
| 131 | RD_REG_DWORD(®->hccr); | |
| 132 | } | |
| 133 | udelay(5); | |
| 134 | } | |
| 135 | ||
| 136 | if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { | |
| c5722708 AV |
137 | rval = mb0 & MBS_MASK; |
| 138 | for (idx = 0; idx < dwords; idx++) | |
| 139 | ram[cnt + idx] = swab32(dump[idx]); | |
| c3a2f0df AV |
140 | } else { |
| 141 | rval = QLA_FUNCTION_FAILED; | |
| 142 | } | |
| 143 | } | |
| 144 | ||
| c5722708 | 145 | *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL; |
| c3a2f0df AV |
146 | return rval; |
| 147 | } | |
| 148 | ||
| c5722708 | 149 | static int |
| 7b867cf7 | 150 | qla24xx_dump_memory(struct qla_hw_data *ha, uint32_t *code_ram, |
| c5722708 AV |
151 | uint32_t cram_size, void **nxt) |
| 152 | { | |
| 153 | int rval; | |
| 154 | ||
| 155 | /* Code RAM. */ | |
| 156 | rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt); | |
| 157 | if (rval != QLA_SUCCESS) | |
| 158 | return rval; | |
| 159 | ||
| 160 | /* External Memory. */ | |
| 161 | return qla24xx_dump_ram(ha, 0x100000, *nxt, | |
| 162 | ha->fw_memory_size - 0x100000 + 1, nxt); | |
| 163 | } | |
| 164 | ||
| c81d04c9 AV |
165 | static uint32_t * |
| 166 | qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase, | |
| 167 | uint32_t count, uint32_t *buf) | |
| 168 | { | |
| 169 | uint32_t __iomem *dmp_reg; | |
| 170 | ||
| 171 | WRT_REG_DWORD(®->iobase_addr, iobase); | |
| 172 | dmp_reg = ®->iobase_window; | |
| 173 | while (count--) | |
| 174 | *buf++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 175 | ||
| 176 | return buf; | |
| 177 | } | |
| 178 | ||
| 179 | static inline int | |
| 180 | qla24xx_pause_risc(struct device_reg_24xx __iomem *reg) | |
| 181 | { | |
| 182 | int rval = QLA_SUCCESS; | |
| 183 | uint32_t cnt; | |
| 184 | ||
| c3b058af | 185 | WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE); |
| aed10881 AV |
186 | for (cnt = 30000; |
| 187 | ((RD_REG_DWORD(®->host_status) & HSRX_RISC_PAUSED) == 0) && | |
| c3b058af AV |
188 | rval == QLA_SUCCESS; cnt--) { |
| 189 | if (cnt) | |
| 190 | udelay(100); | |
| 191 | else | |
| 192 | rval = QLA_FUNCTION_TIMEOUT; | |
| c81d04c9 AV |
193 | } |
| 194 | ||
| 195 | return rval; | |
| 196 | } | |
| 197 | ||
| 198 | static int | |
| 7b867cf7 | 199 | qla24xx_soft_reset(struct qla_hw_data *ha) |
| c81d04c9 AV |
200 | { |
| 201 | int rval = QLA_SUCCESS; | |
| 202 | uint32_t cnt; | |
| 203 | uint16_t mb0, wd; | |
| 204 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
| 205 | ||
| 206 | /* Reset RISC. */ | |
| 207 | WRT_REG_DWORD(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); | |
| 208 | for (cnt = 0; cnt < 30000; cnt++) { | |
| 209 | if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) | |
| 210 | break; | |
| 211 | ||
| 212 | udelay(10); | |
| 213 | } | |
| 214 | ||
| 215 | WRT_REG_DWORD(®->ctrl_status, | |
| 216 | CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); | |
| 217 | pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); | |
| 218 | ||
| 219 | udelay(100); | |
| 220 | /* Wait for firmware to complete NVRAM accesses. */ | |
| 221 | mb0 = (uint32_t) RD_REG_WORD(®->mailbox0); | |
| 222 | for (cnt = 10000 ; cnt && mb0; cnt--) { | |
| 223 | udelay(5); | |
| 224 | mb0 = (uint32_t) RD_REG_WORD(®->mailbox0); | |
| 225 | barrier(); | |
| 226 | } | |
| 227 | ||
| 228 | /* Wait for soft-reset to complete. */ | |
| 229 | for (cnt = 0; cnt < 30000; cnt++) { | |
| 230 | if ((RD_REG_DWORD(®->ctrl_status) & | |
| 231 | CSRX_ISP_SOFT_RESET) == 0) | |
| 232 | break; | |
| 233 | ||
| 234 | udelay(10); | |
| 235 | } | |
| 236 | WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); | |
| 237 | RD_REG_DWORD(®->hccr); /* PCI Posting. */ | |
| 238 | ||
| 239 | for (cnt = 30000; RD_REG_WORD(®->mailbox0) != 0 && | |
| 240 | rval == QLA_SUCCESS; cnt--) { | |
| 241 | if (cnt) | |
| 242 | udelay(100); | |
| 243 | else | |
| 244 | rval = QLA_FUNCTION_TIMEOUT; | |
| 245 | } | |
| 246 | ||
| 247 | return rval; | |
| 248 | } | |
| 249 | ||
| c5722708 | 250 | static int |
| 7b867cf7 | 251 | qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint16_t *ram, |
| e18e963b | 252 | uint32_t ram_words, void **nxt) |
| c5722708 AV |
253 | { |
| 254 | int rval; | |
| 255 | uint32_t cnt, stat, timer, words, idx; | |
| 256 | uint16_t mb0; | |
| 257 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
| 258 | dma_addr_t dump_dma = ha->gid_list_dma; | |
| 259 | uint16_t *dump = (uint16_t *)ha->gid_list; | |
| 260 | ||
| 261 | rval = QLA_SUCCESS; | |
| 262 | mb0 = 0; | |
| 263 | ||
| 264 | WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED); | |
| 265 | clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | |
| 266 | ||
| 642ef983 | 267 | words = qla2x00_gid_list_size(ha) / 2; |
| c5722708 AV |
268 | for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS; |
| 269 | cnt += words, addr += words) { | |
| 270 | if (cnt + words > ram_words) | |
| 271 | words = ram_words - cnt; | |
| 272 | ||
| 273 | WRT_MAILBOX_REG(ha, reg, 1, LSW(addr)); | |
| 274 | WRT_MAILBOX_REG(ha, reg, 8, MSW(addr)); | |
| 275 | ||
| 276 | WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma)); | |
| 277 | WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma)); | |
| 278 | WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma))); | |
| 279 | WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma))); | |
| 280 | ||
| 281 | WRT_MAILBOX_REG(ha, reg, 4, words); | |
| 282 | WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); | |
| 283 | ||
| 284 | for (timer = 6000000; timer; timer--) { | |
| 285 | /* Check for pending interrupts. */ | |
| 286 | stat = RD_REG_DWORD(®->u.isp2300.host_status); | |
| 287 | if (stat & HSR_RISC_INT) { | |
| 288 | stat &= 0xff; | |
| 289 | ||
| 290 | if (stat == 0x1 || stat == 0x2) { | |
| 291 | set_bit(MBX_INTERRUPT, | |
| 292 | &ha->mbx_cmd_flags); | |
| 293 | ||
| 294 | mb0 = RD_MAILBOX_REG(ha, reg, 0); | |
| 295 | ||
| 296 | /* Release mailbox registers. */ | |
| 297 | WRT_REG_WORD(®->semaphore, 0); | |
| 298 | WRT_REG_WORD(®->hccr, | |
| 299 | HCCR_CLR_RISC_INT); | |
| 300 | RD_REG_WORD(®->hccr); | |
| 301 | break; | |
| 302 | } else if (stat == 0x10 || stat == 0x11) { | |
| 303 | set_bit(MBX_INTERRUPT, | |
| 304 | &ha->mbx_cmd_flags); | |
| 305 | ||
| 306 | mb0 = RD_MAILBOX_REG(ha, reg, 0); | |
| 307 | ||
| 308 | WRT_REG_WORD(®->hccr, | |
| 309 | HCCR_CLR_RISC_INT); | |
| 310 | RD_REG_WORD(®->hccr); | |
| 311 | break; | |
| 312 | } | |
| 313 | ||
| 314 | /* clear this intr; it wasn't a mailbox intr */ | |
| 315 | WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); | |
| 316 | RD_REG_WORD(®->hccr); | |
| 317 | } | |
| 318 | udelay(5); | |
| 319 | } | |
| 320 | ||
| 321 | if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { | |
| 322 | rval = mb0 & MBS_MASK; | |
| 323 | for (idx = 0; idx < words; idx++) | |
| 324 | ram[cnt + idx] = swab16(dump[idx]); | |
| 325 | } else { | |
| 326 | rval = QLA_FUNCTION_FAILED; | |
| 327 | } | |
| 328 | } | |
| 329 | ||
| 330 | *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL; | |
| 331 | return rval; | |
| 332 | } | |
| 333 | ||
| c81d04c9 AV |
334 | static inline void |
| 335 | qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count, | |
| 336 | uint16_t *buf) | |
| 337 | { | |
| 338 | uint16_t __iomem *dmp_reg = ®->u.isp2300.fb_cmd; | |
| 339 | ||
| 340 | while (count--) | |
| 341 | *buf++ = htons(RD_REG_WORD(dmp_reg++)); | |
| 342 | } | |
| 343 | ||
| bb99de67 AV |
344 | static inline void * |
| 345 | qla24xx_copy_eft(struct qla_hw_data *ha, void *ptr) | |
| 346 | { | |
| 347 | if (!ha->eft) | |
| 348 | return ptr; | |
| 349 | ||
| 350 | memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size)); | |
| 351 | return ptr + ntohl(ha->fw_dump->eft_size); | |
| 352 | } | |
| 353 | ||
| 354 | static inline void * | |
| 355 | qla25xx_copy_fce(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) | |
| 356 | { | |
| 357 | uint32_t cnt; | |
| 358 | uint32_t *iter_reg; | |
| 359 | struct qla2xxx_fce_chain *fcec = ptr; | |
| 360 | ||
| 361 | if (!ha->fce) | |
| 362 | return ptr; | |
| 363 | ||
| 364 | *last_chain = &fcec->type; | |
| 365 | fcec->type = __constant_htonl(DUMP_CHAIN_FCE); | |
| 366 | fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) + | |
| 367 | fce_calc_size(ha->fce_bufs)); | |
| 368 | fcec->size = htonl(fce_calc_size(ha->fce_bufs)); | |
| 369 | fcec->addr_l = htonl(LSD(ha->fce_dma)); | |
| 370 | fcec->addr_h = htonl(MSD(ha->fce_dma)); | |
| 371 | ||
| 372 | iter_reg = fcec->eregs; | |
| 373 | for (cnt = 0; cnt < 8; cnt++) | |
| 374 | *iter_reg++ = htonl(ha->fce_mb[cnt]); | |
| 375 | ||
| 376 | memcpy(iter_reg, ha->fce, ntohl(fcec->size)); | |
| 377 | ||
| 3cb0a67d | 378 | return (char *)iter_reg + ntohl(fcec->size); |
| bb99de67 AV |
379 | } |
| 380 | ||
| 050c9bb1 GM |
381 | static inline void * |
| 382 | qla25xx_copy_mqueues(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) | |
| 383 | { | |
| 384 | struct qla2xxx_mqueue_chain *q; | |
| 385 | struct qla2xxx_mqueue_header *qh; | |
| 386 | struct req_que *req; | |
| 387 | struct rsp_que *rsp; | |
| 388 | int que; | |
| 389 | ||
| 390 | if (!ha->mqenable) | |
| 391 | return ptr; | |
| 392 | ||
| 393 | /* Request queues */ | |
| 394 | for (que = 1; que < ha->max_req_queues; que++) { | |
| 395 | req = ha->req_q_map[que]; | |
| 396 | if (!req) | |
| 397 | break; | |
| 398 | ||
| 399 | /* Add chain. */ | |
| 400 | q = ptr; | |
| 401 | *last_chain = &q->type; | |
| 402 | q->type = __constant_htonl(DUMP_CHAIN_QUEUE); | |
| 403 | q->chain_size = htonl( | |
| 404 | sizeof(struct qla2xxx_mqueue_chain) + | |
| 405 | sizeof(struct qla2xxx_mqueue_header) + | |
| 406 | (req->length * sizeof(request_t))); | |
| 407 | ptr += sizeof(struct qla2xxx_mqueue_chain); | |
| 408 | ||
| 409 | /* Add header. */ | |
| 410 | qh = ptr; | |
| 411 | qh->queue = __constant_htonl(TYPE_REQUEST_QUEUE); | |
| 412 | qh->number = htonl(que); | |
| 413 | qh->size = htonl(req->length * sizeof(request_t)); | |
| 414 | ptr += sizeof(struct qla2xxx_mqueue_header); | |
| 415 | ||
| 416 | /* Add data. */ | |
| 417 | memcpy(ptr, req->ring, req->length * sizeof(request_t)); | |
| 418 | ptr += req->length * sizeof(request_t); | |
| 419 | } | |
| 420 | ||
| 421 | /* Response queues */ | |
| 422 | for (que = 1; que < ha->max_rsp_queues; que++) { | |
| 423 | rsp = ha->rsp_q_map[que]; | |
| 424 | if (!rsp) | |
| 425 | break; | |
| 426 | ||
| 427 | /* Add chain. */ | |
| 428 | q = ptr; | |
| 429 | *last_chain = &q->type; | |
| 430 | q->type = __constant_htonl(DUMP_CHAIN_QUEUE); | |
| 431 | q->chain_size = htonl( | |
| 432 | sizeof(struct qla2xxx_mqueue_chain) + | |
| 433 | sizeof(struct qla2xxx_mqueue_header) + | |
| 434 | (rsp->length * sizeof(response_t))); | |
| 435 | ptr += sizeof(struct qla2xxx_mqueue_chain); | |
| 436 | ||
| 437 | /* Add header. */ | |
| 438 | qh = ptr; | |
| 439 | qh->queue = __constant_htonl(TYPE_RESPONSE_QUEUE); | |
| 440 | qh->number = htonl(que); | |
| 441 | qh->size = htonl(rsp->length * sizeof(response_t)); | |
| 442 | ptr += sizeof(struct qla2xxx_mqueue_header); | |
| 443 | ||
| 444 | /* Add data. */ | |
| 445 | memcpy(ptr, rsp->ring, rsp->length * sizeof(response_t)); | |
| 446 | ptr += rsp->length * sizeof(response_t); | |
| 447 | } | |
| 448 | ||
| 449 | return ptr; | |
| 450 | } | |
| 451 | ||
| d63ab533 AV |
452 | static inline void * |
| 453 | qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) | |
| 454 | { | |
| 455 | uint32_t cnt, que_idx; | |
| 2afa19a9 | 456 | uint8_t que_cnt; |
| d63ab533 AV |
457 | struct qla2xxx_mq_chain *mq = ptr; |
| 458 | struct device_reg_25xxmq __iomem *reg; | |
| 459 | ||
| 6246b8a1 | 460 | if (!ha->mqenable || IS_QLA83XX(ha)) |
| d63ab533 AV |
461 | return ptr; |
| 462 | ||
| 463 | mq = ptr; | |
| 464 | *last_chain = &mq->type; | |
| 465 | mq->type = __constant_htonl(DUMP_CHAIN_MQ); | |
| 466 | mq->chain_size = __constant_htonl(sizeof(struct qla2xxx_mq_chain)); | |
| 467 | ||
| 2afa19a9 AC |
468 | que_cnt = ha->max_req_queues > ha->max_rsp_queues ? |
| 469 | ha->max_req_queues : ha->max_rsp_queues; | |
| d63ab533 AV |
470 | mq->count = htonl(que_cnt); |
| 471 | for (cnt = 0; cnt < que_cnt; cnt++) { | |
| 472 | reg = (struct device_reg_25xxmq *) ((void *) | |
| 473 | ha->mqiobase + cnt * QLA_QUE_PAGE); | |
| 474 | que_idx = cnt * 4; | |
| 475 | mq->qregs[que_idx] = htonl(RD_REG_DWORD(®->req_q_in)); | |
| 476 | mq->qregs[que_idx+1] = htonl(RD_REG_DWORD(®->req_q_out)); | |
| 477 | mq->qregs[que_idx+2] = htonl(RD_REG_DWORD(®->rsp_q_in)); | |
| 478 | mq->qregs[que_idx+3] = htonl(RD_REG_DWORD(®->rsp_q_out)); | |
| 479 | } | |
| 480 | ||
| 481 | return ptr + sizeof(struct qla2xxx_mq_chain); | |
| 482 | } | |
| 483 | ||
| 08de2844 | 484 | void |
| 3420d36c AV |
485 | qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval) |
| 486 | { | |
| 487 | struct qla_hw_data *ha = vha->hw; | |
| 488 | ||
| 489 | if (rval != QLA_SUCCESS) { | |
| 7c3df132 SK |
490 | ql_log(ql_log_warn, vha, 0xd000, |
| 491 | "Failed to dump firmware (%x).\n", rval); | |
| 3420d36c AV |
492 | ha->fw_dumped = 0; |
| 493 | } else { | |
| 7c3df132 | 494 | ql_log(ql_log_info, vha, 0xd001, |
| 3420d36c AV |
495 | "Firmware dump saved to temp buffer (%ld/%p).\n", |
| 496 | vha->host_no, ha->fw_dump); | |
| 497 | ha->fw_dumped = 1; | |
| 498 | qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); | |
| 499 | } | |
| 500 | } | |
| 501 | ||
| 1da177e4 LT |
502 | /** |
| 503 | * qla2300_fw_dump() - Dumps binary data from the 2300 firmware. | |
| 504 | * @ha: HA context | |
| 505 | * @hardware_locked: Called with the hardware_lock | |
| 506 | */ | |
| 507 | void | |
| 7b867cf7 | 508 | qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
| 1da177e4 LT |
509 | { |
| 510 | int rval; | |
| c5722708 | 511 | uint32_t cnt; |
| 7b867cf7 | 512 | struct qla_hw_data *ha = vha->hw; |
| 3d71644c | 513 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
| 1da177e4 LT |
514 | uint16_t __iomem *dmp_reg; |
| 515 | unsigned long flags; | |
| 516 | struct qla2300_fw_dump *fw; | |
| c5722708 | 517 | void *nxt; |
| 73208dfd | 518 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
| 1da177e4 | 519 | |
| 1da177e4 LT |
520 | flags = 0; |
| 521 | ||
| 522 | if (!hardware_locked) | |
| 523 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
| 524 | ||
| d4e3e04d | 525 | if (!ha->fw_dump) { |
| 7c3df132 SK |
526 | ql_log(ql_log_warn, vha, 0xd002, |
| 527 | "No buffer available for dump.\n"); | |
| 1da177e4 LT |
528 | goto qla2300_fw_dump_failed; |
| 529 | } | |
| 530 | ||
| d4e3e04d | 531 | if (ha->fw_dumped) { |
| 7c3df132 SK |
532 | ql_log(ql_log_warn, vha, 0xd003, |
| 533 | "Firmware has been previously dumped (%p) " | |
| 534 | "-- ignoring request.\n", | |
| 535 | ha->fw_dump); | |
| 1da177e4 LT |
536 | goto qla2300_fw_dump_failed; |
| 537 | } | |
| a7a167bf AV |
538 | fw = &ha->fw_dump->isp.isp23; |
| 539 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
| 1da177e4 LT |
540 | |
| 541 | rval = QLA_SUCCESS; | |
| a7a167bf | 542 | fw->hccr = htons(RD_REG_WORD(®->hccr)); |
| 1da177e4 LT |
543 | |
| 544 | /* Pause RISC. */ | |
| fa2a1ce5 | 545 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); |
| 1da177e4 LT |
546 | if (IS_QLA2300(ha)) { |
| 547 | for (cnt = 30000; | |
| 548 | (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && | |
| 549 | rval == QLA_SUCCESS; cnt--) { | |
| 550 | if (cnt) | |
| 551 | udelay(100); | |
| 552 | else | |
| 553 | rval = QLA_FUNCTION_TIMEOUT; | |
| 554 | } | |
| 555 | } else { | |
| 556 | RD_REG_WORD(®->hccr); /* PCI Posting. */ | |
| 557 | udelay(10); | |
| 558 | } | |
| 559 | ||
| 560 | if (rval == QLA_SUCCESS) { | |
| c81d04c9 | 561 | dmp_reg = ®->flash_address; |
| fa2a1ce5 | 562 | for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) |
| a7a167bf | 563 | fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
| 1da177e4 | 564 | |
| c81d04c9 | 565 | dmp_reg = ®->u.isp2300.req_q_in; |
| fa2a1ce5 | 566 | for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++) |
| a7a167bf | 567 | fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
| 1da177e4 | 568 | |
| c81d04c9 | 569 | dmp_reg = ®->u.isp2300.mailbox0; |
| fa2a1ce5 | 570 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) |
| a7a167bf | 571 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
| 1da177e4 LT |
572 | |
| 573 | WRT_REG_WORD(®->ctrl_status, 0x40); | |
| c81d04c9 | 574 | qla2xxx_read_window(reg, 32, fw->resp_dma_reg); |
| 1da177e4 LT |
575 | |
| 576 | WRT_REG_WORD(®->ctrl_status, 0x50); | |
| c81d04c9 | 577 | qla2xxx_read_window(reg, 48, fw->dma_reg); |
| 1da177e4 LT |
578 | |
| 579 | WRT_REG_WORD(®->ctrl_status, 0x00); | |
| c81d04c9 | 580 | dmp_reg = ®->risc_hw; |
| fa2a1ce5 | 581 | for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) |
| a7a167bf | 582 | fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
| 1da177e4 | 583 | |
| fa2a1ce5 | 584 | WRT_REG_WORD(®->pcr, 0x2000); |
| c81d04c9 | 585 | qla2xxx_read_window(reg, 16, fw->risc_gp0_reg); |
| 1da177e4 | 586 | |
| fa2a1ce5 | 587 | WRT_REG_WORD(®->pcr, 0x2200); |
| c81d04c9 | 588 | qla2xxx_read_window(reg, 16, fw->risc_gp1_reg); |
| 1da177e4 | 589 | |
| fa2a1ce5 | 590 | WRT_REG_WORD(®->pcr, 0x2400); |
| c81d04c9 | 591 | qla2xxx_read_window(reg, 16, fw->risc_gp2_reg); |
| 1da177e4 | 592 | |
| fa2a1ce5 | 593 | WRT_REG_WORD(®->pcr, 0x2600); |
| c81d04c9 | 594 | qla2xxx_read_window(reg, 16, fw->risc_gp3_reg); |
| 1da177e4 | 595 | |
| fa2a1ce5 | 596 | WRT_REG_WORD(®->pcr, 0x2800); |
| c81d04c9 | 597 | qla2xxx_read_window(reg, 16, fw->risc_gp4_reg); |
| 1da177e4 | 598 | |
| fa2a1ce5 | 599 | WRT_REG_WORD(®->pcr, 0x2A00); |
| c81d04c9 | 600 | qla2xxx_read_window(reg, 16, fw->risc_gp5_reg); |
| 1da177e4 | 601 | |
| fa2a1ce5 | 602 | WRT_REG_WORD(®->pcr, 0x2C00); |
| c81d04c9 | 603 | qla2xxx_read_window(reg, 16, fw->risc_gp6_reg); |
| 1da177e4 | 604 | |
| fa2a1ce5 | 605 | WRT_REG_WORD(®->pcr, 0x2E00); |
| c81d04c9 | 606 | qla2xxx_read_window(reg, 16, fw->risc_gp7_reg); |
| 1da177e4 | 607 | |
| fa2a1ce5 | 608 | WRT_REG_WORD(®->ctrl_status, 0x10); |
| c81d04c9 | 609 | qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg); |
| 1da177e4 | 610 | |
| fa2a1ce5 | 611 | WRT_REG_WORD(®->ctrl_status, 0x20); |
| c81d04c9 | 612 | qla2xxx_read_window(reg, 64, fw->fpm_b0_reg); |
| 1da177e4 | 613 | |
| fa2a1ce5 | 614 | WRT_REG_WORD(®->ctrl_status, 0x30); |
| c81d04c9 | 615 | qla2xxx_read_window(reg, 64, fw->fpm_b1_reg); |
| 1da177e4 LT |
616 | |
| 617 | /* Reset RISC. */ | |
| 618 | WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); | |
| 619 | for (cnt = 0; cnt < 30000; cnt++) { | |
| 620 | if ((RD_REG_WORD(®->ctrl_status) & | |
| 621 | CSR_ISP_SOFT_RESET) == 0) | |
| 622 | break; | |
| 623 | ||
| 624 | udelay(10); | |
| 625 | } | |
| 626 | } | |
| 627 | ||
| 628 | if (!IS_QLA2300(ha)) { | |
| 629 | for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && | |
| 630 | rval == QLA_SUCCESS; cnt--) { | |
| 631 | if (cnt) | |
| 632 | udelay(100); | |
| 633 | else | |
| 634 | rval = QLA_FUNCTION_TIMEOUT; | |
| 635 | } | |
| 636 | } | |
| 637 | ||
| c5722708 AV |
638 | /* Get RISC SRAM. */ |
| 639 | if (rval == QLA_SUCCESS) | |
| 640 | rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram, | |
| 641 | sizeof(fw->risc_ram) / 2, &nxt); | |
| 1da177e4 | 642 | |
| c5722708 AV |
643 | /* Get stack SRAM. */ |
| 644 | if (rval == QLA_SUCCESS) | |
| 645 | rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram, | |
| 646 | sizeof(fw->stack_ram) / 2, &nxt); | |
| 1da177e4 | 647 | |
| c5722708 AV |
648 | /* Get data SRAM. */ |
| 649 | if (rval == QLA_SUCCESS) | |
| 650 | rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram, | |
| 651 | ha->fw_memory_size - 0x11000 + 1, &nxt); | |
| 1da177e4 | 652 | |
| a7a167bf | 653 | if (rval == QLA_SUCCESS) |
| 73208dfd | 654 | qla2xxx_copy_queues(ha, nxt); |
| a7a167bf | 655 | |
| 3420d36c | 656 | qla2xxx_dump_post_process(base_vha, rval); |
| 1da177e4 LT |
657 | |
| 658 | qla2300_fw_dump_failed: | |
| 659 | if (!hardware_locked) | |
| 660 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
| 661 | } | |
| 662 | ||
| 1da177e4 LT |
663 | /** |
| 664 | * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware. | |
| 665 | * @ha: HA context | |
| 666 | * @hardware_locked: Called with the hardware_lock | |
| 667 | */ | |
| 668 | void | |
| 7b867cf7 | 669 | qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
| 1da177e4 LT |
670 | { |
| 671 | int rval; | |
| 672 | uint32_t cnt, timer; | |
| 673 | uint16_t risc_address; | |
| 674 | uint16_t mb0, mb2; | |
| 7b867cf7 | 675 | struct qla_hw_data *ha = vha->hw; |
| 3d71644c | 676 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
| 1da177e4 LT |
677 | uint16_t __iomem *dmp_reg; |
| 678 | unsigned long flags; | |
| 679 | struct qla2100_fw_dump *fw; | |
| 73208dfd | 680 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
| 1da177e4 LT |
681 | |
| 682 | risc_address = 0; | |
| 683 | mb0 = mb2 = 0; | |
| 684 | flags = 0; | |
| 685 | ||
| 686 | if (!hardware_locked) | |
| 687 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
| 688 | ||
| d4e3e04d | 689 | if (!ha->fw_dump) { |
| 7c3df132 SK |
690 | ql_log(ql_log_warn, vha, 0xd004, |
| 691 | "No buffer available for dump.\n"); | |
| 1da177e4 LT |
692 | goto qla2100_fw_dump_failed; |
| 693 | } | |
| 694 | ||
| d4e3e04d | 695 | if (ha->fw_dumped) { |
| 7c3df132 SK |
696 | ql_log(ql_log_warn, vha, 0xd005, |
| 697 | "Firmware has been previously dumped (%p) " | |
| 698 | "-- ignoring request.\n", | |
| 699 | ha->fw_dump); | |
| 1da177e4 LT |
700 | goto qla2100_fw_dump_failed; |
| 701 | } | |
| a7a167bf AV |
702 | fw = &ha->fw_dump->isp.isp21; |
| 703 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
| 1da177e4 LT |
704 | |
| 705 | rval = QLA_SUCCESS; | |
| a7a167bf | 706 | fw->hccr = htons(RD_REG_WORD(®->hccr)); |
| 1da177e4 LT |
707 | |
| 708 | /* Pause RISC. */ | |
| fa2a1ce5 | 709 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); |
| 1da177e4 LT |
710 | for (cnt = 30000; (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && |
| 711 | rval == QLA_SUCCESS; cnt--) { | |
| 712 | if (cnt) | |
| 713 | udelay(100); | |
| 714 | else | |
| 715 | rval = QLA_FUNCTION_TIMEOUT; | |
| 716 | } | |
| 717 | if (rval == QLA_SUCCESS) { | |
| c81d04c9 | 718 | dmp_reg = ®->flash_address; |
| fa2a1ce5 | 719 | for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) |
| a7a167bf | 720 | fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
| 1da177e4 | 721 | |
| c81d04c9 | 722 | dmp_reg = ®->u.isp2100.mailbox0; |
| 1da177e4 | 723 | for (cnt = 0; cnt < ha->mbx_count; cnt++) { |
| c81d04c9 AV |
724 | if (cnt == 8) |
| 725 | dmp_reg = ®->u_end.isp2200.mailbox8; | |
| 726 | ||
| a7a167bf | 727 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
| 1da177e4 LT |
728 | } |
| 729 | ||
| c81d04c9 | 730 | dmp_reg = ®->u.isp2100.unused_2[0]; |
| fa2a1ce5 | 731 | for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++) |
| a7a167bf | 732 | fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
| 1da177e4 LT |
733 | |
| 734 | WRT_REG_WORD(®->ctrl_status, 0x00); | |
| c81d04c9 | 735 | dmp_reg = ®->risc_hw; |
| fa2a1ce5 | 736 | for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) |
| a7a167bf | 737 | fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
| 1da177e4 | 738 | |
| fa2a1ce5 | 739 | WRT_REG_WORD(®->pcr, 0x2000); |
| c81d04c9 | 740 | qla2xxx_read_window(reg, 16, fw->risc_gp0_reg); |
| 1da177e4 | 741 | |
| fa2a1ce5 | 742 | WRT_REG_WORD(®->pcr, 0x2100); |
| c81d04c9 | 743 | qla2xxx_read_window(reg, 16, fw->risc_gp1_reg); |
| 1da177e4 | 744 | |
| fa2a1ce5 | 745 | WRT_REG_WORD(®->pcr, 0x2200); |
| c81d04c9 | 746 | qla2xxx_read_window(reg, 16, fw->risc_gp2_reg); |
| 1da177e4 | 747 | |
| fa2a1ce5 | 748 | WRT_REG_WORD(®->pcr, 0x2300); |
| c81d04c9 | 749 | qla2xxx_read_window(reg, 16, fw->risc_gp3_reg); |
| 1da177e4 | 750 | |
| fa2a1ce5 | 751 | WRT_REG_WORD(®->pcr, 0x2400); |
| c81d04c9 | 752 | qla2xxx_read_window(reg, 16, fw->risc_gp4_reg); |
| 1da177e4 | 753 | |
| fa2a1ce5 | 754 | WRT_REG_WORD(®->pcr, 0x2500); |
| c81d04c9 | 755 | qla2xxx_read_window(reg, 16, fw->risc_gp5_reg); |
| 1da177e4 | 756 | |
| fa2a1ce5 | 757 | WRT_REG_WORD(®->pcr, 0x2600); |
| c81d04c9 | 758 | qla2xxx_read_window(reg, 16, fw->risc_gp6_reg); |
| 1da177e4 | 759 | |
| fa2a1ce5 | 760 | WRT_REG_WORD(®->pcr, 0x2700); |
| c81d04c9 | 761 | qla2xxx_read_window(reg, 16, fw->risc_gp7_reg); |
| 1da177e4 | 762 | |
| fa2a1ce5 | 763 | WRT_REG_WORD(®->ctrl_status, 0x10); |
| c81d04c9 | 764 | qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg); |
| 1da177e4 | 765 | |
| fa2a1ce5 | 766 | WRT_REG_WORD(®->ctrl_status, 0x20); |
| c81d04c9 | 767 | qla2xxx_read_window(reg, 64, fw->fpm_b0_reg); |
| 1da177e4 | 768 | |
| fa2a1ce5 | 769 | WRT_REG_WORD(®->ctrl_status, 0x30); |
| c81d04c9 | 770 | qla2xxx_read_window(reg, 64, fw->fpm_b1_reg); |
| 1da177e4 LT |
771 | |
| 772 | /* Reset the ISP. */ | |
| 773 | WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); | |
| 774 | } | |
| 775 | ||
| 776 | for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && | |
| 777 | rval == QLA_SUCCESS; cnt--) { | |
| 778 | if (cnt) | |
| 779 | udelay(100); | |
| 780 | else | |
| 781 | rval = QLA_FUNCTION_TIMEOUT; | |
| 782 | } | |
| 783 | ||
| 784 | /* Pause RISC. */ | |
| 785 | if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) && | |
| 786 | (RD_REG_WORD(®->mctr) & (BIT_1 | BIT_0)) != 0))) { | |
| 787 | ||
| fa2a1ce5 | 788 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); |
| 1da177e4 LT |
789 | for (cnt = 30000; |
| 790 | (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && | |
| 791 | rval == QLA_SUCCESS; cnt--) { | |
| 792 | if (cnt) | |
| 793 | udelay(100); | |
| 794 | else | |
| 795 | rval = QLA_FUNCTION_TIMEOUT; | |
| 796 | } | |
| 797 | if (rval == QLA_SUCCESS) { | |
| 798 | /* Set memory configuration and timing. */ | |
| 799 | if (IS_QLA2100(ha)) | |
| 800 | WRT_REG_WORD(®->mctr, 0xf1); | |
| 801 | else | |
| 802 | WRT_REG_WORD(®->mctr, 0xf2); | |
| 803 | RD_REG_WORD(®->mctr); /* PCI Posting. */ | |
| 804 | ||
| 805 | /* Release RISC. */ | |
| 806 | WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); | |
| 807 | } | |
| 808 | } | |
| 809 | ||
| 810 | if (rval == QLA_SUCCESS) { | |
| 811 | /* Get RISC SRAM. */ | |
| 812 | risc_address = 0x1000; | |
| 813 | WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD); | |
| 814 | clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | |
| 815 | } | |
| 816 | for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS; | |
| 817 | cnt++, risc_address++) { | |
| 818 | WRT_MAILBOX_REG(ha, reg, 1, risc_address); | |
| 819 | WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); | |
| 820 | ||
| 821 | for (timer = 6000000; timer != 0; timer--) { | |
| 822 | /* Check for pending interrupts. */ | |
| 823 | if (RD_REG_WORD(®->istatus) & ISR_RISC_INT) { | |
| 824 | if (RD_REG_WORD(®->semaphore) & BIT_0) { | |
| 825 | set_bit(MBX_INTERRUPT, | |
| 826 | &ha->mbx_cmd_flags); | |
| 827 | ||
| 828 | mb0 = RD_MAILBOX_REG(ha, reg, 0); | |
| 829 | mb2 = RD_MAILBOX_REG(ha, reg, 2); | |
| 830 | ||
| 831 | WRT_REG_WORD(®->semaphore, 0); | |
| 832 | WRT_REG_WORD(®->hccr, | |
| 833 | HCCR_CLR_RISC_INT); | |
| 834 | RD_REG_WORD(®->hccr); | |
| 835 | break; | |
| 836 | } | |
| 837 | WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); | |
| 838 | RD_REG_WORD(®->hccr); | |
| 839 | } | |
| 840 | udelay(5); | |
| 841 | } | |
| 842 | ||
| 843 | if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { | |
| 844 | rval = mb0 & MBS_MASK; | |
| a7a167bf | 845 | fw->risc_ram[cnt] = htons(mb2); |
| 1da177e4 LT |
846 | } else { |
| 847 | rval = QLA_FUNCTION_FAILED; | |
| 848 | } | |
| 849 | } | |
| 850 | ||
| a7a167bf | 851 | if (rval == QLA_SUCCESS) |
| 73208dfd | 852 | qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]); |
| a7a167bf | 853 | |
| 3420d36c | 854 | qla2xxx_dump_post_process(base_vha, rval); |
| 1da177e4 LT |
855 | |
| 856 | qla2100_fw_dump_failed: | |
| 857 | if (!hardware_locked) | |
| 858 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
| 859 | } | |
| 860 | ||
| 6d9b61ed | 861 | void |
| 7b867cf7 | 862 | qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
| 6d9b61ed AV |
863 | { |
| 864 | int rval; | |
| c3a2f0df | 865 | uint32_t cnt; |
| 6d9b61ed | 866 | uint32_t risc_address; |
| 7b867cf7 | 867 | struct qla_hw_data *ha = vha->hw; |
| 6d9b61ed AV |
868 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
| 869 | uint32_t __iomem *dmp_reg; | |
| 870 | uint32_t *iter_reg; | |
| 871 | uint16_t __iomem *mbx_reg; | |
| 872 | unsigned long flags; | |
| 873 | struct qla24xx_fw_dump *fw; | |
| 874 | uint32_t ext_mem_cnt; | |
| c3a2f0df | 875 | void *nxt; |
| 73208dfd | 876 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
| 6d9b61ed | 877 | |
| a9083016 GM |
878 | if (IS_QLA82XX(ha)) |
| 879 | return; | |
| 880 | ||
| 6d9b61ed | 881 | risc_address = ext_mem_cnt = 0; |
| 6d9b61ed AV |
882 | flags = 0; |
| 883 | ||
| 884 | if (!hardware_locked) | |
| 885 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
| 886 | ||
| d4e3e04d | 887 | if (!ha->fw_dump) { |
| 7c3df132 SK |
888 | ql_log(ql_log_warn, vha, 0xd006, |
| 889 | "No buffer available for dump.\n"); | |
| 6d9b61ed AV |
890 | goto qla24xx_fw_dump_failed; |
| 891 | } | |
| 892 | ||
| 893 | if (ha->fw_dumped) { | |
| 7c3df132 SK |
894 | ql_log(ql_log_warn, vha, 0xd007, |
| 895 | "Firmware has been previously dumped (%p) " | |
| 896 | "-- ignoring request.\n", | |
| 897 | ha->fw_dump); | |
| 6d9b61ed AV |
898 | goto qla24xx_fw_dump_failed; |
| 899 | } | |
| a7a167bf AV |
900 | fw = &ha->fw_dump->isp.isp24; |
| 901 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
| 6d9b61ed | 902 | |
| a7a167bf | 903 | fw->host_status = htonl(RD_REG_DWORD(®->host_status)); |
| 6d9b61ed AV |
904 | |
| 905 | /* Pause RISC. */ | |
| c81d04c9 AV |
906 | rval = qla24xx_pause_risc(reg); |
| 907 | if (rval != QLA_SUCCESS) | |
| 908 | goto qla24xx_fw_dump_failed_0; | |
| 909 | ||
| 910 | /* Host interface registers. */ | |
| 911 | dmp_reg = ®->flash_addr; | |
| 912 | for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) | |
| 913 | fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 914 | ||
| 915 | /* Disable interrupts. */ | |
| 916 | WRT_REG_DWORD(®->ictrl, 0); | |
| 917 | RD_REG_DWORD(®->ictrl); | |
| 918 | ||
| 919 | /* Shadow registers. */ | |
| 920 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); | |
| 921 | RD_REG_DWORD(®->iobase_addr); | |
| 922 | WRT_REG_DWORD(®->iobase_select, 0xB0000000); | |
| 923 | fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 924 | ||
| 925 | WRT_REG_DWORD(®->iobase_select, 0xB0100000); | |
| 926 | fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 927 | ||
| 928 | WRT_REG_DWORD(®->iobase_select, 0xB0200000); | |
| 929 | fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 930 | ||
| 931 | WRT_REG_DWORD(®->iobase_select, 0xB0300000); | |
| 932 | fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 933 | ||
| 934 | WRT_REG_DWORD(®->iobase_select, 0xB0400000); | |
| 935 | fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 936 | ||
| 937 | WRT_REG_DWORD(®->iobase_select, 0xB0500000); | |
| 938 | fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 939 | ||
| 940 | WRT_REG_DWORD(®->iobase_select, 0xB0600000); | |
| 941 | fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 942 | ||
| 943 | /* Mailbox registers. */ | |
| 944 | mbx_reg = ®->mailbox0; | |
| 945 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) | |
| 946 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); | |
| 947 | ||
| 948 | /* Transfer sequence registers. */ | |
| 949 | iter_reg = fw->xseq_gp_reg; | |
| 950 | iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); | |
| 951 | iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); | |
| 952 | iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); | |
| 953 | iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); | |
| 954 | iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); | |
| 955 | iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); | |
| 956 | iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); | |
| 957 | qla24xx_read_window(reg, 0xBF70, 16, iter_reg); | |
| 958 | ||
| 959 | qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg); | |
| 960 | qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); | |
| 961 | ||
| 962 | /* Receive sequence registers. */ | |
| 963 | iter_reg = fw->rseq_gp_reg; | |
| 964 | iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); | |
| 965 | iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); | |
| 966 | iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); | |
| 967 | iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); | |
| 968 | iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); | |
| 969 | iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); | |
| 970 | iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); | |
| 971 | qla24xx_read_window(reg, 0xFF70, 16, iter_reg); | |
| 972 | ||
| 973 | qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg); | |
| 974 | qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); | |
| 975 | qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); | |
| 976 | ||
| 977 | /* Command DMA registers. */ | |
| 978 | qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); | |
| 979 | ||
| 980 | /* Queues. */ | |
| 981 | iter_reg = fw->req0_dma_reg; | |
| 982 | iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); | |
| 983 | dmp_reg = ®->iobase_q; | |
| 984 | for (cnt = 0; cnt < 7; cnt++) | |
| 985 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 986 | ||
| 987 | iter_reg = fw->resp0_dma_reg; | |
| 988 | iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); | |
| 989 | dmp_reg = ®->iobase_q; | |
| 990 | for (cnt = 0; cnt < 7; cnt++) | |
| 991 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 992 | ||
| 993 | iter_reg = fw->req1_dma_reg; | |
| 994 | iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); | |
| 995 | dmp_reg = ®->iobase_q; | |
| 996 | for (cnt = 0; cnt < 7; cnt++) | |
| 997 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 998 | ||
| 999 | /* Transmit DMA registers. */ | |
| 1000 | iter_reg = fw->xmt0_dma_reg; | |
| 1001 | iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); | |
| 1002 | qla24xx_read_window(reg, 0x7610, 16, iter_reg); | |
| 1003 | ||
| 1004 | iter_reg = fw->xmt1_dma_reg; | |
| 1005 | iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); | |
| 1006 | qla24xx_read_window(reg, 0x7630, 16, iter_reg); | |
| 1007 | ||
| 1008 | iter_reg = fw->xmt2_dma_reg; | |
| 1009 | iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); | |
| 1010 | qla24xx_read_window(reg, 0x7650, 16, iter_reg); | |
| 1011 | ||
| 1012 | iter_reg = fw->xmt3_dma_reg; | |
| 1013 | iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); | |
| 1014 | qla24xx_read_window(reg, 0x7670, 16, iter_reg); | |
| 1015 | ||
| 1016 | iter_reg = fw->xmt4_dma_reg; | |
| 1017 | iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); | |
| 1018 | qla24xx_read_window(reg, 0x7690, 16, iter_reg); | |
| 1019 | ||
| 1020 | qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); | |
| 1021 | ||
| 1022 | /* Receive DMA registers. */ | |
| 1023 | iter_reg = fw->rcvt0_data_dma_reg; | |
| 1024 | iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); | |
| 1025 | qla24xx_read_window(reg, 0x7710, 16, iter_reg); | |
| 1026 | ||
| 1027 | iter_reg = fw->rcvt1_data_dma_reg; | |
| 1028 | iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); | |
| 1029 | qla24xx_read_window(reg, 0x7730, 16, iter_reg); | |
| 1030 | ||
| 1031 | /* RISC registers. */ | |
| 1032 | iter_reg = fw->risc_gp_reg; | |
| 1033 | iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); | |
| 1034 | iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); | |
| 1035 | iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); | |
| 1036 | iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); | |
| 1037 | iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); | |
| 1038 | iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); | |
| 1039 | iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); | |
| 1040 | qla24xx_read_window(reg, 0x0F70, 16, iter_reg); | |
| 1041 | ||
| 1042 | /* Local memory controller registers. */ | |
| 1043 | iter_reg = fw->lmc_reg; | |
| 1044 | iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); | |
| 1045 | iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); | |
| 1046 | iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); | |
| 1047 | iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); | |
| 1048 | iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); | |
| 1049 | iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); | |
| 1050 | qla24xx_read_window(reg, 0x3060, 16, iter_reg); | |
| 1051 | ||
| 1052 | /* Fibre Protocol Module registers. */ | |
| 1053 | iter_reg = fw->fpm_hdw_reg; | |
| 1054 | iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); | |
| 1055 | iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); | |
| 1056 | iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); | |
| 1057 | iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); | |
| 1058 | iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); | |
| 1059 | iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); | |
| 1060 | iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); | |
| 1061 | iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); | |
| 1062 | iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); | |
| 1063 | iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); | |
| 1064 | iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); | |
| 1065 | qla24xx_read_window(reg, 0x40B0, 16, iter_reg); | |
| 1066 | ||
| 1067 | /* Frame Buffer registers. */ | |
| 1068 | iter_reg = fw->fb_hdw_reg; | |
| 1069 | iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); | |
| 1070 | iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); | |
| 1071 | iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); | |
| 1072 | iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); | |
| 1073 | iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); | |
| 1074 | iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); | |
| 1075 | iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); | |
| 1076 | iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); | |
| 1077 | iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); | |
| 1078 | iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); | |
| 1079 | qla24xx_read_window(reg, 0x61B0, 16, iter_reg); | |
| 1080 | ||
| 1081 | rval = qla24xx_soft_reset(ha); | |
| 1082 | if (rval != QLA_SUCCESS) | |
| 1083 | goto qla24xx_fw_dump_failed_0; | |
| 1084 | ||
| 1085 | rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), | |
| c5722708 | 1086 | &nxt); |
| c81d04c9 AV |
1087 | if (rval != QLA_SUCCESS) |
| 1088 | goto qla24xx_fw_dump_failed_0; | |
| 1089 | ||
| 73208dfd | 1090 | nxt = qla2xxx_copy_queues(ha, nxt); |
| bb99de67 AV |
1091 | |
| 1092 | qla24xx_copy_eft(ha, nxt); | |
| c81d04c9 AV |
1093 | |
| 1094 | qla24xx_fw_dump_failed_0: | |
| 3420d36c | 1095 | qla2xxx_dump_post_process(base_vha, rval); |
| 6d9b61ed | 1096 | |
| c3a2f0df AV |
1097 | qla24xx_fw_dump_failed: |
| 1098 | if (!hardware_locked) | |
| 1099 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
| 1100 | } | |
| 6d9b61ed | 1101 | |
| c3a2f0df | 1102 | void |
| 7b867cf7 | 1103 | qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
| c3a2f0df AV |
1104 | { |
| 1105 | int rval; | |
| 1106 | uint32_t cnt; | |
| 1107 | uint32_t risc_address; | |
| 7b867cf7 | 1108 | struct qla_hw_data *ha = vha->hw; |
| c3a2f0df AV |
1109 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
| 1110 | uint32_t __iomem *dmp_reg; | |
| 1111 | uint32_t *iter_reg; | |
| 1112 | uint16_t __iomem *mbx_reg; | |
| 1113 | unsigned long flags; | |
| 1114 | struct qla25xx_fw_dump *fw; | |
| 1115 | uint32_t ext_mem_cnt; | |
| d63ab533 | 1116 | void *nxt, *nxt_chain; |
| bb99de67 | 1117 | uint32_t *last_chain = NULL; |
| 73208dfd | 1118 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
| 6d9b61ed | 1119 | |
| c3a2f0df AV |
1120 | risc_address = ext_mem_cnt = 0; |
| 1121 | flags = 0; | |
| 6d9b61ed | 1122 | |
| c3a2f0df AV |
1123 | if (!hardware_locked) |
| 1124 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
| 6d9b61ed | 1125 | |
| c3a2f0df | 1126 | if (!ha->fw_dump) { |
| 7c3df132 SK |
1127 | ql_log(ql_log_warn, vha, 0xd008, |
| 1128 | "No buffer available for dump.\n"); | |
| c3a2f0df AV |
1129 | goto qla25xx_fw_dump_failed; |
| 1130 | } | |
| 6d9b61ed | 1131 | |
| c3a2f0df | 1132 | if (ha->fw_dumped) { |
| 7c3df132 SK |
1133 | ql_log(ql_log_warn, vha, 0xd009, |
| 1134 | "Firmware has been previously dumped (%p) " | |
| 1135 | "-- ignoring request.\n", | |
| 1136 | ha->fw_dump); | |
| c3a2f0df AV |
1137 | goto qla25xx_fw_dump_failed; |
| 1138 | } | |
| 1139 | fw = &ha->fw_dump->isp.isp25; | |
| 1140 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
| b5836927 | 1141 | ha->fw_dump->version = __constant_htonl(2); |
| 6d9b61ed | 1142 | |
| c3a2f0df | 1143 | fw->host_status = htonl(RD_REG_DWORD(®->host_status)); |
| 6d9b61ed | 1144 | |
| c3a2f0df | 1145 | /* Pause RISC. */ |
| c81d04c9 AV |
1146 | rval = qla24xx_pause_risc(reg); |
| 1147 | if (rval != QLA_SUCCESS) | |
| 1148 | goto qla25xx_fw_dump_failed_0; | |
| 1149 | ||
| b5836927 AV |
1150 | /* Host/Risc registers. */ |
| 1151 | iter_reg = fw->host_risc_reg; | |
| 1152 | iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); | |
| 1153 | qla24xx_read_window(reg, 0x7010, 16, iter_reg); | |
| 1154 | ||
| 1155 | /* PCIe registers. */ | |
| 1156 | WRT_REG_DWORD(®->iobase_addr, 0x7C00); | |
| 1157 | RD_REG_DWORD(®->iobase_addr); | |
| 1158 | WRT_REG_DWORD(®->iobase_window, 0x01); | |
| 1159 | dmp_reg = ®->iobase_c4; | |
| 1160 | fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1161 | fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1162 | fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); | |
| 1163 | fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); | |
| 73208dfd | 1164 | |
| b5836927 AV |
1165 | WRT_REG_DWORD(®->iobase_window, 0x00); |
| 1166 | RD_REG_DWORD(®->iobase_window); | |
| 1167 | ||
| c81d04c9 AV |
1168 | /* Host interface registers. */ |
| 1169 | dmp_reg = ®->flash_addr; | |
| 1170 | for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) | |
| 1171 | fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1172 | ||
| 1173 | /* Disable interrupts. */ | |
| 1174 | WRT_REG_DWORD(®->ictrl, 0); | |
| 1175 | RD_REG_DWORD(®->ictrl); | |
| 1176 | ||
| 1177 | /* Shadow registers. */ | |
| 1178 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); | |
| 1179 | RD_REG_DWORD(®->iobase_addr); | |
| 1180 | WRT_REG_DWORD(®->iobase_select, 0xB0000000); | |
| 1181 | fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1182 | ||
| 1183 | WRT_REG_DWORD(®->iobase_select, 0xB0100000); | |
| 1184 | fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1185 | ||
| 1186 | WRT_REG_DWORD(®->iobase_select, 0xB0200000); | |
| 1187 | fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1188 | ||
| 1189 | WRT_REG_DWORD(®->iobase_select, 0xB0300000); | |
| 1190 | fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1191 | ||
| 1192 | WRT_REG_DWORD(®->iobase_select, 0xB0400000); | |
| 1193 | fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1194 | ||
| 1195 | WRT_REG_DWORD(®->iobase_select, 0xB0500000); | |
| 1196 | fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1197 | ||
| 1198 | WRT_REG_DWORD(®->iobase_select, 0xB0600000); | |
| 1199 | fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1200 | ||
| 1201 | WRT_REG_DWORD(®->iobase_select, 0xB0700000); | |
| 1202 | fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1203 | ||
| 1204 | WRT_REG_DWORD(®->iobase_select, 0xB0800000); | |
| 1205 | fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1206 | ||
| 1207 | WRT_REG_DWORD(®->iobase_select, 0xB0900000); | |
| 1208 | fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1209 | ||
| 1210 | WRT_REG_DWORD(®->iobase_select, 0xB0A00000); | |
| 1211 | fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1212 | ||
| 1213 | /* RISC I/O register. */ | |
| 1214 | WRT_REG_DWORD(®->iobase_addr, 0x0010); | |
| 1215 | fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); | |
| 1216 | ||
| 1217 | /* Mailbox registers. */ | |
| 1218 | mbx_reg = ®->mailbox0; | |
| 1219 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) | |
| 1220 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); | |
| 1221 | ||
| 1222 | /* Transfer sequence registers. */ | |
| 1223 | iter_reg = fw->xseq_gp_reg; | |
| 1224 | iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); | |
| 1225 | iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); | |
| 1226 | iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); | |
| 1227 | iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); | |
| 1228 | iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); | |
| 1229 | iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); | |
| 1230 | iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); | |
| 1231 | qla24xx_read_window(reg, 0xBF70, 16, iter_reg); | |
| 1232 | ||
| 1233 | iter_reg = fw->xseq_0_reg; | |
| 1234 | iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); | |
| 1235 | iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); | |
| 1236 | qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); | |
| 1237 | ||
| 1238 | qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); | |
| 1239 | ||
| 1240 | /* Receive sequence registers. */ | |
| 1241 | iter_reg = fw->rseq_gp_reg; | |
| 1242 | iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); | |
| 1243 | iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); | |
| 1244 | iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); | |
| 1245 | iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); | |
| 1246 | iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); | |
| 1247 | iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); | |
| 1248 | iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); | |
| 1249 | qla24xx_read_window(reg, 0xFF70, 16, iter_reg); | |
| 1250 | ||
| 1251 | iter_reg = fw->rseq_0_reg; | |
| 1252 | iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); | |
| 1253 | qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); | |
| 1254 | ||
| 1255 | qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); | |
| 1256 | qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); | |
| 1257 | ||
| 1258 | /* Auxiliary sequence registers. */ | |
| 1259 | iter_reg = fw->aseq_gp_reg; | |
| 1260 | iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); | |
| 1261 | iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); | |
| 1262 | iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); | |
| 1263 | iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); | |
| 1264 | iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); | |
| 1265 | iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); | |
| 1266 | iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); | |
| 1267 | qla24xx_read_window(reg, 0xB070, 16, iter_reg); | |
| 1268 | ||
| 1269 | iter_reg = fw->aseq_0_reg; | |
| 1270 | iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); | |
| 1271 | qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); | |
| 1272 | ||
| 1273 | qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); | |
| 1274 | qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); | |
| 1275 | ||
| 1276 | /* Command DMA registers. */ | |
| 1277 | qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); | |
| 1278 | ||
| 1279 | /* Queues. */ | |
| 1280 | iter_reg = fw->req0_dma_reg; | |
| 1281 | iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); | |
| 1282 | dmp_reg = ®->iobase_q; | |
| 1283 | for (cnt = 0; cnt < 7; cnt++) | |
| 1284 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1285 | ||
| 1286 | iter_reg = fw->resp0_dma_reg; | |
| 1287 | iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); | |
| 1288 | dmp_reg = ®->iobase_q; | |
| 1289 | for (cnt = 0; cnt < 7; cnt++) | |
| 1290 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1291 | ||
| 1292 | iter_reg = fw->req1_dma_reg; | |
| 1293 | iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); | |
| 1294 | dmp_reg = ®->iobase_q; | |
| 1295 | for (cnt = 0; cnt < 7; cnt++) | |
| 1296 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1297 | ||
| 1298 | /* Transmit DMA registers. */ | |
| 1299 | iter_reg = fw->xmt0_dma_reg; | |
| 1300 | iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); | |
| 1301 | qla24xx_read_window(reg, 0x7610, 16, iter_reg); | |
| 1302 | ||
| 1303 | iter_reg = fw->xmt1_dma_reg; | |
| 1304 | iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); | |
| 1305 | qla24xx_read_window(reg, 0x7630, 16, iter_reg); | |
| 1306 | ||
| 1307 | iter_reg = fw->xmt2_dma_reg; | |
| 1308 | iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); | |
| 1309 | qla24xx_read_window(reg, 0x7650, 16, iter_reg); | |
| 1310 | ||
| 1311 | iter_reg = fw->xmt3_dma_reg; | |
| 1312 | iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); | |
| 1313 | qla24xx_read_window(reg, 0x7670, 16, iter_reg); | |
| 1314 | ||
| 1315 | iter_reg = fw->xmt4_dma_reg; | |
| 1316 | iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); | |
| 1317 | qla24xx_read_window(reg, 0x7690, 16, iter_reg); | |
| 1318 | ||
| 1319 | qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); | |
| 1320 | ||
| 1321 | /* Receive DMA registers. */ | |
| 1322 | iter_reg = fw->rcvt0_data_dma_reg; | |
| 1323 | iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); | |
| 1324 | qla24xx_read_window(reg, 0x7710, 16, iter_reg); | |
| 1325 | ||
| 1326 | iter_reg = fw->rcvt1_data_dma_reg; | |
| 1327 | iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); | |
| 1328 | qla24xx_read_window(reg, 0x7730, 16, iter_reg); | |
| 1329 | ||
| 1330 | /* RISC registers. */ | |
| 1331 | iter_reg = fw->risc_gp_reg; | |
| 1332 | iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); | |
| 1333 | iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); | |
| 1334 | iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); | |
| 1335 | iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); | |
| 1336 | iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); | |
| 1337 | iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); | |
| 1338 | iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); | |
| 1339 | qla24xx_read_window(reg, 0x0F70, 16, iter_reg); | |
| 1340 | ||
| 1341 | /* Local memory controller registers. */ | |
| 1342 | iter_reg = fw->lmc_reg; | |
| 1343 | iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); | |
| 1344 | iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); | |
| 1345 | iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); | |
| 1346 | iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); | |
| 1347 | iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); | |
| 1348 | iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); | |
| 1349 | iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); | |
| 1350 | qla24xx_read_window(reg, 0x3070, 16, iter_reg); | |
| 1351 | ||
| 1352 | /* Fibre Protocol Module registers. */ | |
| 1353 | iter_reg = fw->fpm_hdw_reg; | |
| 1354 | iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); | |
| 1355 | iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); | |
| 1356 | iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); | |
| 1357 | iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); | |
| 1358 | iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); | |
| 1359 | iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); | |
| 1360 | iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); | |
| 1361 | iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); | |
| 1362 | iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); | |
| 1363 | iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); | |
| 1364 | iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); | |
| 1365 | qla24xx_read_window(reg, 0x40B0, 16, iter_reg); | |
| 1366 | ||
| 1367 | /* Frame Buffer registers. */ | |
| 1368 | iter_reg = fw->fb_hdw_reg; | |
| 1369 | iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); | |
| 1370 | iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); | |
| 1371 | iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); | |
| 1372 | iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); | |
| 1373 | iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); | |
| 1374 | iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); | |
| 1375 | iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); | |
| 1376 | iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); | |
| 1377 | iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); | |
| 1378 | iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); | |
| 1379 | iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); | |
| 1380 | qla24xx_read_window(reg, 0x6F00, 16, iter_reg); | |
| 1381 | ||
| d63ab533 AV |
1382 | /* Multi queue registers */ |
| 1383 | nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, | |
| 1384 | &last_chain); | |
| 1385 | ||
| c81d04c9 AV |
1386 | rval = qla24xx_soft_reset(ha); |
| 1387 | if (rval != QLA_SUCCESS) | |
| 1388 | goto qla25xx_fw_dump_failed_0; | |
| 1389 | ||
| 1390 | rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), | |
| c5722708 | 1391 | &nxt); |
| c81d04c9 AV |
1392 | if (rval != QLA_SUCCESS) |
| 1393 | goto qla25xx_fw_dump_failed_0; | |
| 1394 | ||
| 73208dfd | 1395 | nxt = qla2xxx_copy_queues(ha, nxt); |
| c81d04c9 | 1396 | |
| bb99de67 | 1397 | nxt = qla24xx_copy_eft(ha, nxt); |
| df613b96 | 1398 | |
| d63ab533 | 1399 | /* Chain entries -- started with MQ. */ |
| 050c9bb1 GM |
1400 | nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain); |
| 1401 | nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain); | |
| bb99de67 AV |
1402 | if (last_chain) { |
| 1403 | ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT); | |
| 1404 | *last_chain |= __constant_htonl(DUMP_CHAIN_LAST); | |
| 1405 | } | |
| df613b96 | 1406 | |
| 050c9bb1 GM |
1407 | /* Adjust valid length. */ |
| 1408 | ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); | |
| 1409 | ||
| c81d04c9 | 1410 | qla25xx_fw_dump_failed_0: |
| 3420d36c | 1411 | qla2xxx_dump_post_process(base_vha, rval); |
| 6d9b61ed | 1412 | |
| c3a2f0df | 1413 | qla25xx_fw_dump_failed: |
| 6d9b61ed AV |
1414 | if (!hardware_locked) |
| 1415 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
| 1416 | } | |
| 3a03eb79 AV |
1417 | |
| 1418 | void | |
| 1419 | qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) | |
| 1420 | { | |
| 1421 | int rval; | |
| 1422 | uint32_t cnt; | |
| 1423 | uint32_t risc_address; | |
| 1424 | struct qla_hw_data *ha = vha->hw; | |
| 1425 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
| 1426 | uint32_t __iomem *dmp_reg; | |
| 1427 | uint32_t *iter_reg; | |
| 1428 | uint16_t __iomem *mbx_reg; | |
| 1429 | unsigned long flags; | |
| 1430 | struct qla81xx_fw_dump *fw; | |
| 1431 | uint32_t ext_mem_cnt; | |
| 1432 | void *nxt, *nxt_chain; | |
| 1433 | uint32_t *last_chain = NULL; | |
| 1434 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); | |
| 1435 | ||
| 1436 | risc_address = ext_mem_cnt = 0; | |
| 1437 | flags = 0; | |
| 1438 | ||
| 1439 | if (!hardware_locked) | |
| 1440 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
| 1441 | ||
| 1442 | if (!ha->fw_dump) { | |
| 7c3df132 SK |
1443 | ql_log(ql_log_warn, vha, 0xd00a, |
| 1444 | "No buffer available for dump.\n"); | |
| 3a03eb79 AV |
1445 | goto qla81xx_fw_dump_failed; |
| 1446 | } | |
| 1447 | ||
| 1448 | if (ha->fw_dumped) { | |
| 7c3df132 SK |
1449 | ql_log(ql_log_warn, vha, 0xd00b, |
| 1450 | "Firmware has been previously dumped (%p) " | |
| 1451 | "-- ignoring request.\n", | |
| 1452 | ha->fw_dump); | |
| 3a03eb79 AV |
1453 | goto qla81xx_fw_dump_failed; |
| 1454 | } | |
| 1455 | fw = &ha->fw_dump->isp.isp81; | |
| 1456 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
| 1457 | ||
| 1458 | fw->host_status = htonl(RD_REG_DWORD(®->host_status)); | |
| 1459 | ||
| 1460 | /* Pause RISC. */ | |
| 1461 | rval = qla24xx_pause_risc(reg); | |
| 1462 | if (rval != QLA_SUCCESS) | |
| 1463 | goto qla81xx_fw_dump_failed_0; | |
| 1464 | ||
| 1465 | /* Host/Risc registers. */ | |
| 1466 | iter_reg = fw->host_risc_reg; | |
| 1467 | iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); | |
| 1468 | qla24xx_read_window(reg, 0x7010, 16, iter_reg); | |
| 1469 | ||
| 1470 | /* PCIe registers. */ | |
| 1471 | WRT_REG_DWORD(®->iobase_addr, 0x7C00); | |
| 1472 | RD_REG_DWORD(®->iobase_addr); | |
| 1473 | WRT_REG_DWORD(®->iobase_window, 0x01); | |
| 1474 | dmp_reg = ®->iobase_c4; | |
| 1475 | fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1476 | fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1477 | fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); | |
| 1478 | fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); | |
| 1479 | ||
| 1480 | WRT_REG_DWORD(®->iobase_window, 0x00); | |
| 1481 | RD_REG_DWORD(®->iobase_window); | |
| 1482 | ||
| 1483 | /* Host interface registers. */ | |
| 1484 | dmp_reg = ®->flash_addr; | |
| 1485 | for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) | |
| 1486 | fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1487 | ||
| 1488 | /* Disable interrupts. */ | |
| 1489 | WRT_REG_DWORD(®->ictrl, 0); | |
| 1490 | RD_REG_DWORD(®->ictrl); | |
| 1491 | ||
| 1492 | /* Shadow registers. */ | |
| 1493 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); | |
| 1494 | RD_REG_DWORD(®->iobase_addr); | |
| 1495 | WRT_REG_DWORD(®->iobase_select, 0xB0000000); | |
| 1496 | fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1497 | ||
| 1498 | WRT_REG_DWORD(®->iobase_select, 0xB0100000); | |
| 1499 | fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1500 | ||
| 1501 | WRT_REG_DWORD(®->iobase_select, 0xB0200000); | |
| 1502 | fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1503 | ||
| 1504 | WRT_REG_DWORD(®->iobase_select, 0xB0300000); | |
| 1505 | fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1506 | ||
| 1507 | WRT_REG_DWORD(®->iobase_select, 0xB0400000); | |
| 1508 | fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1509 | ||
| 1510 | WRT_REG_DWORD(®->iobase_select, 0xB0500000); | |
| 1511 | fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1512 | ||
| 1513 | WRT_REG_DWORD(®->iobase_select, 0xB0600000); | |
| 1514 | fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1515 | ||
| 1516 | WRT_REG_DWORD(®->iobase_select, 0xB0700000); | |
| 1517 | fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1518 | ||
| 1519 | WRT_REG_DWORD(®->iobase_select, 0xB0800000); | |
| 1520 | fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1521 | ||
| 1522 | WRT_REG_DWORD(®->iobase_select, 0xB0900000); | |
| 1523 | fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1524 | ||
| 1525 | WRT_REG_DWORD(®->iobase_select, 0xB0A00000); | |
| 1526 | fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1527 | ||
| 1528 | /* RISC I/O register. */ | |
| 1529 | WRT_REG_DWORD(®->iobase_addr, 0x0010); | |
| 1530 | fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); | |
| 1531 | ||
| 1532 | /* Mailbox registers. */ | |
| 1533 | mbx_reg = ®->mailbox0; | |
| 1534 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) | |
| 1535 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); | |
| 1536 | ||
| 1537 | /* Transfer sequence registers. */ | |
| 1538 | iter_reg = fw->xseq_gp_reg; | |
| 1539 | iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); | |
| 1540 | iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); | |
| 1541 | iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); | |
| 1542 | iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); | |
| 1543 | iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); | |
| 1544 | iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); | |
| 1545 | iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); | |
| 1546 | qla24xx_read_window(reg, 0xBF70, 16, iter_reg); | |
| 1547 | ||
| 1548 | iter_reg = fw->xseq_0_reg; | |
| 1549 | iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); | |
| 1550 | iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); | |
| 1551 | qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); | |
| 1552 | ||
| 1553 | qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); | |
| 1554 | ||
| 1555 | /* Receive sequence registers. */ | |
| 1556 | iter_reg = fw->rseq_gp_reg; | |
| 1557 | iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); | |
| 1558 | iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); | |
| 1559 | iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); | |
| 1560 | iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); | |
| 1561 | iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); | |
| 1562 | iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); | |
| 1563 | iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); | |
| 1564 | qla24xx_read_window(reg, 0xFF70, 16, iter_reg); | |
| 1565 | ||
| 1566 | iter_reg = fw->rseq_0_reg; | |
| 1567 | iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); | |
| 1568 | qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); | |
| 1569 | ||
| 1570 | qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); | |
| 1571 | qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); | |
| 1572 | ||
| 1573 | /* Auxiliary sequence registers. */ | |
| 1574 | iter_reg = fw->aseq_gp_reg; | |
| 1575 | iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); | |
| 1576 | iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); | |
| 1577 | iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); | |
| 1578 | iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); | |
| 1579 | iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); | |
| 1580 | iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); | |
| 1581 | iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); | |
| 1582 | qla24xx_read_window(reg, 0xB070, 16, iter_reg); | |
| 1583 | ||
| 1584 | iter_reg = fw->aseq_0_reg; | |
| 1585 | iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); | |
| 1586 | qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); | |
| 1587 | ||
| 1588 | qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); | |
| 1589 | qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); | |
| 1590 | ||
| 1591 | /* Command DMA registers. */ | |
| 1592 | qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); | |
| 1593 | ||
| 1594 | /* Queues. */ | |
| 1595 | iter_reg = fw->req0_dma_reg; | |
| 1596 | iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); | |
| 1597 | dmp_reg = ®->iobase_q; | |
| 1598 | for (cnt = 0; cnt < 7; cnt++) | |
| 1599 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1600 | ||
| 1601 | iter_reg = fw->resp0_dma_reg; | |
| 1602 | iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); | |
| 1603 | dmp_reg = ®->iobase_q; | |
| 1604 | for (cnt = 0; cnt < 7; cnt++) | |
| 1605 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1606 | ||
| 1607 | iter_reg = fw->req1_dma_reg; | |
| 1608 | iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); | |
| 1609 | dmp_reg = ®->iobase_q; | |
| 1610 | for (cnt = 0; cnt < 7; cnt++) | |
| 1611 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1612 | ||
| 1613 | /* Transmit DMA registers. */ | |
| 1614 | iter_reg = fw->xmt0_dma_reg; | |
| 1615 | iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); | |
| 1616 | qla24xx_read_window(reg, 0x7610, 16, iter_reg); | |
| 1617 | ||
| 1618 | iter_reg = fw->xmt1_dma_reg; | |
| 1619 | iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); | |
| 1620 | qla24xx_read_window(reg, 0x7630, 16, iter_reg); | |
| 1621 | ||
| 1622 | iter_reg = fw->xmt2_dma_reg; | |
| 1623 | iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); | |
| 1624 | qla24xx_read_window(reg, 0x7650, 16, iter_reg); | |
| 1625 | ||
| 1626 | iter_reg = fw->xmt3_dma_reg; | |
| 1627 | iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); | |
| 1628 | qla24xx_read_window(reg, 0x7670, 16, iter_reg); | |
| 1629 | ||
| 1630 | iter_reg = fw->xmt4_dma_reg; | |
| 1631 | iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); | |
| 1632 | qla24xx_read_window(reg, 0x7690, 16, iter_reg); | |
| 1633 | ||
| 1634 | qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); | |
| 1635 | ||
| 1636 | /* Receive DMA registers. */ | |
| 1637 | iter_reg = fw->rcvt0_data_dma_reg; | |
| 1638 | iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); | |
| 1639 | qla24xx_read_window(reg, 0x7710, 16, iter_reg); | |
| 1640 | ||
| 1641 | iter_reg = fw->rcvt1_data_dma_reg; | |
| 1642 | iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); | |
| 1643 | qla24xx_read_window(reg, 0x7730, 16, iter_reg); | |
| 1644 | ||
| 1645 | /* RISC registers. */ | |
| 1646 | iter_reg = fw->risc_gp_reg; | |
| 1647 | iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); | |
| 1648 | iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); | |
| 1649 | iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); | |
| 1650 | iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); | |
| 1651 | iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); | |
| 1652 | iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); | |
| 1653 | iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); | |
| 1654 | qla24xx_read_window(reg, 0x0F70, 16, iter_reg); | |
| 1655 | ||
| 1656 | /* Local memory controller registers. */ | |
| 1657 | iter_reg = fw->lmc_reg; | |
| 1658 | iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); | |
| 1659 | iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); | |
| 1660 | iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); | |
| 1661 | iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); | |
| 1662 | iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); | |
| 1663 | iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); | |
| 1664 | iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); | |
| 1665 | qla24xx_read_window(reg, 0x3070, 16, iter_reg); | |
| 1666 | ||
| 1667 | /* Fibre Protocol Module registers. */ | |
| 1668 | iter_reg = fw->fpm_hdw_reg; | |
| 1669 | iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); | |
| 1670 | iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); | |
| 1671 | iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); | |
| 1672 | iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); | |
| 1673 | iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); | |
| 1674 | iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); | |
| 1675 | iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); | |
| 1676 | iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); | |
| 1677 | iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); | |
| 1678 | iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); | |
| 1679 | iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); | |
| 1680 | iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg); | |
| 1681 | iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg); | |
| 1682 | qla24xx_read_window(reg, 0x40D0, 16, iter_reg); | |
| 1683 | ||
| 1684 | /* Frame Buffer registers. */ | |
| 1685 | iter_reg = fw->fb_hdw_reg; | |
| 1686 | iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); | |
| 1687 | iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); | |
| 1688 | iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); | |
| 1689 | iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); | |
| 1690 | iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); | |
| 1691 | iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); | |
| 1692 | iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); | |
| 1693 | iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); | |
| 1694 | iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); | |
| 1695 | iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); | |
| 1696 | iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); | |
| 1697 | iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg); | |
| 1698 | qla24xx_read_window(reg, 0x6F00, 16, iter_reg); | |
| 1699 | ||
| 1700 | /* Multi queue registers */ | |
| 1701 | nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, | |
| 1702 | &last_chain); | |
| 1703 | ||
| 1704 | rval = qla24xx_soft_reset(ha); | |
| 1705 | if (rval != QLA_SUCCESS) | |
| 1706 | goto qla81xx_fw_dump_failed_0; | |
| 1707 | ||
| 1708 | rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), | |
| 1709 | &nxt); | |
| 1710 | if (rval != QLA_SUCCESS) | |
| 1711 | goto qla81xx_fw_dump_failed_0; | |
| 1712 | ||
| 1713 | nxt = qla2xxx_copy_queues(ha, nxt); | |
| 1714 | ||
| 1715 | nxt = qla24xx_copy_eft(ha, nxt); | |
| 1716 | ||
| 1717 | /* Chain entries -- started with MQ. */ | |
| 050c9bb1 GM |
1718 | nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain); |
| 1719 | nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain); | |
| 3a03eb79 AV |
1720 | if (last_chain) { |
| 1721 | ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT); | |
| 1722 | *last_chain |= __constant_htonl(DUMP_CHAIN_LAST); | |
| 1723 | } | |
| 1724 | ||
| 050c9bb1 GM |
1725 | /* Adjust valid length. */ |
| 1726 | ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); | |
| 1727 | ||
| 3a03eb79 | 1728 | qla81xx_fw_dump_failed_0: |
| 3420d36c | 1729 | qla2xxx_dump_post_process(base_vha, rval); |
| 3a03eb79 AV |
1730 | |
| 1731 | qla81xx_fw_dump_failed: | |
| 1732 | if (!hardware_locked) | |
| 1733 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
| 1734 | } | |
| 1735 | ||
| 6246b8a1 GM |
1736 | void |
| 1737 | qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) | |
| 1738 | { | |
| 1739 | int rval; | |
| 1740 | uint32_t cnt, reg_data; | |
| 1741 | uint32_t risc_address; | |
| 1742 | struct qla_hw_data *ha = vha->hw; | |
| 1743 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
| 1744 | uint32_t __iomem *dmp_reg; | |
| 1745 | uint32_t *iter_reg; | |
| 1746 | uint16_t __iomem *mbx_reg; | |
| 1747 | unsigned long flags; | |
| 1748 | struct qla83xx_fw_dump *fw; | |
| 1749 | uint32_t ext_mem_cnt; | |
| 1750 | void *nxt, *nxt_chain; | |
| 1751 | uint32_t *last_chain = NULL; | |
| 1752 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); | |
| 1753 | ||
| 1754 | risc_address = ext_mem_cnt = 0; | |
| 1755 | flags = 0; | |
| 1756 | ||
| 1757 | if (!hardware_locked) | |
| 1758 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
| 1759 | ||
| 1760 | if (!ha->fw_dump) { | |
| 1761 | ql_log(ql_log_warn, vha, 0xd00c, | |
| 1762 | "No buffer available for dump!!!\n"); | |
| 1763 | goto qla83xx_fw_dump_failed; | |
| 1764 | } | |
| 1765 | ||
| 1766 | if (ha->fw_dumped) { | |
| 1767 | ql_log(ql_log_warn, vha, 0xd00d, | |
| 1768 | "Firmware has been previously dumped (%p) -- ignoring " | |
| 1769 | "request...\n", ha->fw_dump); | |
| 1770 | goto qla83xx_fw_dump_failed; | |
| 1771 | } | |
| 1772 | fw = &ha->fw_dump->isp.isp83; | |
| 1773 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
| 1774 | ||
| 1775 | fw->host_status = htonl(RD_REG_DWORD(®->host_status)); | |
| 1776 | ||
| 1777 | /* Pause RISC. */ | |
| 1778 | rval = qla24xx_pause_risc(reg); | |
| 1779 | if (rval != QLA_SUCCESS) | |
| 1780 | goto qla83xx_fw_dump_failed_0; | |
| 1781 | ||
| 1782 | WRT_REG_DWORD(®->iobase_addr, 0x6000); | |
| 1783 | dmp_reg = ®->iobase_window; | |
| 1784 | reg_data = RD_REG_DWORD(dmp_reg); | |
| 1785 | WRT_REG_DWORD(dmp_reg, 0); | |
| 1786 | ||
| 1787 | dmp_reg = ®->unused_4_1[0]; | |
| 1788 | reg_data = RD_REG_DWORD(dmp_reg); | |
| 1789 | WRT_REG_DWORD(dmp_reg, 0); | |
| 1790 | ||
| 1791 | WRT_REG_DWORD(®->iobase_addr, 0x6010); | |
| 1792 | dmp_reg = ®->unused_4_1[2]; | |
| 1793 | reg_data = RD_REG_DWORD(dmp_reg); | |
| 1794 | WRT_REG_DWORD(dmp_reg, 0); | |
| 1795 | ||
| 1796 | /* select PCR and disable ecc checking and correction */ | |
| 1797 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); | |
| 1798 | RD_REG_DWORD(®->iobase_addr); | |
| 1799 | WRT_REG_DWORD(®->iobase_select, 0x60000000); /* write to F0h = PCR */ | |
| 1800 | ||
| 1801 | /* Host/Risc registers. */ | |
| 1802 | iter_reg = fw->host_risc_reg; | |
| 1803 | iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); | |
| 1804 | iter_reg = qla24xx_read_window(reg, 0x7010, 16, iter_reg); | |
| 1805 | qla24xx_read_window(reg, 0x7040, 16, iter_reg); | |
| 1806 | ||
| 1807 | /* PCIe registers. */ | |
| 1808 | WRT_REG_DWORD(®->iobase_addr, 0x7C00); | |
| 1809 | RD_REG_DWORD(®->iobase_addr); | |
| 1810 | WRT_REG_DWORD(®->iobase_window, 0x01); | |
| 1811 | dmp_reg = ®->iobase_c4; | |
| 1812 | fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1813 | fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1814 | fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); | |
| 1815 | fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); | |
| 1816 | ||
| 1817 | WRT_REG_DWORD(®->iobase_window, 0x00); | |
| 1818 | RD_REG_DWORD(®->iobase_window); | |
| 1819 | ||
| 1820 | /* Host interface registers. */ | |
| 1821 | dmp_reg = ®->flash_addr; | |
| 1822 | for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) | |
| 1823 | fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1824 | ||
| 1825 | /* Disable interrupts. */ | |
| 1826 | WRT_REG_DWORD(®->ictrl, 0); | |
| 1827 | RD_REG_DWORD(®->ictrl); | |
| 1828 | ||
| 1829 | /* Shadow registers. */ | |
| 1830 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); | |
| 1831 | RD_REG_DWORD(®->iobase_addr); | |
| 1832 | WRT_REG_DWORD(®->iobase_select, 0xB0000000); | |
| 1833 | fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1834 | ||
| 1835 | WRT_REG_DWORD(®->iobase_select, 0xB0100000); | |
| 1836 | fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1837 | ||
| 1838 | WRT_REG_DWORD(®->iobase_select, 0xB0200000); | |
| 1839 | fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1840 | ||
| 1841 | WRT_REG_DWORD(®->iobase_select, 0xB0300000); | |
| 1842 | fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1843 | ||
| 1844 | WRT_REG_DWORD(®->iobase_select, 0xB0400000); | |
| 1845 | fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1846 | ||
| 1847 | WRT_REG_DWORD(®->iobase_select, 0xB0500000); | |
| 1848 | fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1849 | ||
| 1850 | WRT_REG_DWORD(®->iobase_select, 0xB0600000); | |
| 1851 | fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1852 | ||
| 1853 | WRT_REG_DWORD(®->iobase_select, 0xB0700000); | |
| 1854 | fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1855 | ||
| 1856 | WRT_REG_DWORD(®->iobase_select, 0xB0800000); | |
| 1857 | fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1858 | ||
| 1859 | WRT_REG_DWORD(®->iobase_select, 0xB0900000); | |
| 1860 | fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1861 | ||
| 1862 | WRT_REG_DWORD(®->iobase_select, 0xB0A00000); | |
| 1863 | fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
| 1864 | ||
| 1865 | /* RISC I/O register. */ | |
| 1866 | WRT_REG_DWORD(®->iobase_addr, 0x0010); | |
| 1867 | fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); | |
| 1868 | ||
| 1869 | /* Mailbox registers. */ | |
| 1870 | mbx_reg = ®->mailbox0; | |
| 1871 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) | |
| 1872 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); | |
| 1873 | ||
| 1874 | /* Transfer sequence registers. */ | |
| 1875 | iter_reg = fw->xseq_gp_reg; | |
| 1876 | iter_reg = qla24xx_read_window(reg, 0xBE00, 16, iter_reg); | |
| 1877 | iter_reg = qla24xx_read_window(reg, 0xBE10, 16, iter_reg); | |
| 1878 | iter_reg = qla24xx_read_window(reg, 0xBE20, 16, iter_reg); | |
| 1879 | iter_reg = qla24xx_read_window(reg, 0xBE30, 16, iter_reg); | |
| 1880 | iter_reg = qla24xx_read_window(reg, 0xBE40, 16, iter_reg); | |
| 1881 | iter_reg = qla24xx_read_window(reg, 0xBE50, 16, iter_reg); | |
| 1882 | iter_reg = qla24xx_read_window(reg, 0xBE60, 16, iter_reg); | |
| 1883 | iter_reg = qla24xx_read_window(reg, 0xBE70, 16, iter_reg); | |
| 1884 | iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); | |
| 1885 | iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); | |
| 1886 | iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); | |
| 1887 | iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); | |
| 1888 | iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); | |
| 1889 | iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); | |
| 1890 | iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); | |
| 1891 | qla24xx_read_window(reg, 0xBF70, 16, iter_reg); | |
| 1892 | ||
| 1893 | iter_reg = fw->xseq_0_reg; | |
| 1894 | iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); | |
| 1895 | iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); | |
| 1896 | qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); | |
| 1897 | ||
| 1898 | qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); | |
| 1899 | ||
| 1900 | qla24xx_read_window(reg, 0xBEF0, 16, fw->xseq_2_reg); | |
| 1901 | ||
| 1902 | /* Receive sequence registers. */ | |
| 1903 | iter_reg = fw->rseq_gp_reg; | |
| 1904 | iter_reg = qla24xx_read_window(reg, 0xFE00, 16, iter_reg); | |
| 1905 | iter_reg = qla24xx_read_window(reg, 0xFE10, 16, iter_reg); | |
| 1906 | iter_reg = qla24xx_read_window(reg, 0xFE20, 16, iter_reg); | |
| 1907 | iter_reg = qla24xx_read_window(reg, 0xFE30, 16, iter_reg); | |
| 1908 | iter_reg = qla24xx_read_window(reg, 0xFE40, 16, iter_reg); | |
| 1909 | iter_reg = qla24xx_read_window(reg, 0xFE50, 16, iter_reg); | |
| 1910 | iter_reg = qla24xx_read_window(reg, 0xFE60, 16, iter_reg); | |
| 1911 | iter_reg = qla24xx_read_window(reg, 0xFE70, 16, iter_reg); | |
| 1912 | iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); | |
| 1913 | iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); | |
| 1914 | iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); | |
| 1915 | iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); | |
| 1916 | iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); | |
| 1917 | iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); | |
| 1918 | iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); | |
| 1919 | qla24xx_read_window(reg, 0xFF70, 16, iter_reg); | |
| 1920 | ||
| 1921 | iter_reg = fw->rseq_0_reg; | |
| 1922 | iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); | |
| 1923 | qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); | |
| 1924 | ||
| 1925 | qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); | |
| 1926 | qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); | |
| 1927 | qla24xx_read_window(reg, 0xFEF0, 16, fw->rseq_3_reg); | |
| 1928 | ||
| 1929 | /* Auxiliary sequence registers. */ | |
| 1930 | iter_reg = fw->aseq_gp_reg; | |
| 1931 | iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); | |
| 1932 | iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); | |
| 1933 | iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); | |
| 1934 | iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); | |
| 1935 | iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); | |
| 1936 | iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); | |
| 1937 | iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); | |
| 1938 | iter_reg = qla24xx_read_window(reg, 0xB070, 16, iter_reg); | |
| 1939 | iter_reg = qla24xx_read_window(reg, 0xB100, 16, iter_reg); | |
| 1940 | iter_reg = qla24xx_read_window(reg, 0xB110, 16, iter_reg); | |
| 1941 | iter_reg = qla24xx_read_window(reg, 0xB120, 16, iter_reg); | |
| 1942 | iter_reg = qla24xx_read_window(reg, 0xB130, 16, iter_reg); | |
| 1943 | iter_reg = qla24xx_read_window(reg, 0xB140, 16, iter_reg); | |
| 1944 | iter_reg = qla24xx_read_window(reg, 0xB150, 16, iter_reg); | |
| 1945 | iter_reg = qla24xx_read_window(reg, 0xB160, 16, iter_reg); | |
| 1946 | qla24xx_read_window(reg, 0xB170, 16, iter_reg); | |
| 1947 | ||
| 1948 | iter_reg = fw->aseq_0_reg; | |
| 1949 | iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); | |
| 1950 | qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); | |
| 1951 | ||
| 1952 | qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); | |
| 1953 | qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); | |
| 1954 | qla24xx_read_window(reg, 0xB1F0, 16, fw->aseq_3_reg); | |
| 1955 | ||
| 1956 | /* Command DMA registers. */ | |
| 1957 | iter_reg = fw->cmd_dma_reg; | |
| 1958 | iter_reg = qla24xx_read_window(reg, 0x7100, 16, iter_reg); | |
| 1959 | iter_reg = qla24xx_read_window(reg, 0x7120, 16, iter_reg); | |
| 1960 | iter_reg = qla24xx_read_window(reg, 0x7130, 16, iter_reg); | |
| 1961 | qla24xx_read_window(reg, 0x71F0, 16, iter_reg); | |
| 1962 | ||
| 1963 | /* Queues. */ | |
| 1964 | iter_reg = fw->req0_dma_reg; | |
| 1965 | iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); | |
| 1966 | dmp_reg = ®->iobase_q; | |
| 1967 | for (cnt = 0; cnt < 7; cnt++) | |
| 1968 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1969 | ||
| 1970 | iter_reg = fw->resp0_dma_reg; | |
| 1971 | iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); | |
| 1972 | dmp_reg = ®->iobase_q; | |
| 1973 | for (cnt = 0; cnt < 7; cnt++) | |
| 1974 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1975 | ||
| 1976 | iter_reg = fw->req1_dma_reg; | |
| 1977 | iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); | |
| 1978 | dmp_reg = ®->iobase_q; | |
| 1979 | for (cnt = 0; cnt < 7; cnt++) | |
| 1980 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
| 1981 | ||
| 1982 | /* Transmit DMA registers. */ | |
| 1983 | iter_reg = fw->xmt0_dma_reg; | |
| 1984 | iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); | |
| 1985 | qla24xx_read_window(reg, 0x7610, 16, iter_reg); | |
| 1986 | ||
| 1987 | iter_reg = fw->xmt1_dma_reg; | |
| 1988 | iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); | |
| 1989 | qla24xx_read_window(reg, 0x7630, 16, iter_reg); | |
| 1990 | ||
| 1991 | iter_reg = fw->xmt2_dma_reg; | |
| 1992 | iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); | |
| 1993 | qla24xx_read_window(reg, 0x7650, 16, iter_reg); | |
| 1994 | ||
| 1995 | iter_reg = fw->xmt3_dma_reg; | |
| 1996 | iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); | |
| 1997 | qla24xx_read_window(reg, 0x7670, 16, iter_reg); | |
| 1998 | ||
| 1999 | iter_reg = fw->xmt4_dma_reg; | |
| 2000 | iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); | |
| 2001 | qla24xx_read_window(reg, 0x7690, 16, iter_reg); | |
| 2002 | ||
| 2003 | qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); | |
| 2004 | ||
| 2005 | /* Receive DMA registers. */ | |
| 2006 | iter_reg = fw->rcvt0_data_dma_reg; | |
| 2007 | iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); | |
| 2008 | qla24xx_read_window(reg, 0x7710, 16, iter_reg); | |
| 2009 | ||
| 2010 | iter_reg = fw->rcvt1_data_dma_reg; | |
| 2011 | iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); | |
| 2012 | qla24xx_read_window(reg, 0x7730, 16, iter_reg); | |
| 2013 | ||
| 2014 | /* RISC registers. */ | |
| 2015 | iter_reg = fw->risc_gp_reg; | |
| 2016 | iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); | |
| 2017 | iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); | |
| 2018 | iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); | |
| 2019 | iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); | |
| 2020 | iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); | |
| 2021 | iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); | |
| 2022 | iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); | |
| 2023 | qla24xx_read_window(reg, 0x0F70, 16, iter_reg); | |
| 2024 | ||
| 2025 | /* Local memory controller registers. */ | |
| 2026 | iter_reg = fw->lmc_reg; | |
| 2027 | iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); | |
| 2028 | iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); | |
| 2029 | iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); | |
| 2030 | iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); | |
| 2031 | iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); | |
| 2032 | iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); | |
| 2033 | iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); | |
| 2034 | qla24xx_read_window(reg, 0x3070, 16, iter_reg); | |
| 2035 | ||
| 2036 | /* Fibre Protocol Module registers. */ | |
| 2037 | iter_reg = fw->fpm_hdw_reg; | |
| 2038 | iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); | |
| 2039 | iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); | |
| 2040 | iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); | |
| 2041 | iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); | |
| 2042 | iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); | |
| 2043 | iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); | |
| 2044 | iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); | |
| 2045 | iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); | |
| 2046 | iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); | |
| 2047 | iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); | |
| 2048 | iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); | |
| 2049 | iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg); | |
| 2050 | iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg); | |
| 2051 | iter_reg = qla24xx_read_window(reg, 0x40D0, 16, iter_reg); | |
| 2052 | iter_reg = qla24xx_read_window(reg, 0x40E0, 16, iter_reg); | |
| 2053 | qla24xx_read_window(reg, 0x40F0, 16, iter_reg); | |
| 2054 | ||
| 2055 | /* RQ0 Array registers. */ | |
| 2056 | iter_reg = fw->rq0_array_reg; | |
| 2057 | iter_reg = qla24xx_read_window(reg, 0x5C00, 16, iter_reg); | |
| 2058 | iter_reg = qla24xx_read_window(reg, 0x5C10, 16, iter_reg); | |
| 2059 | iter_reg = qla24xx_read_window(reg, 0x5C20, 16, iter_reg); | |
| 2060 | iter_reg = qla24xx_read_window(reg, 0x5C30, 16, iter_reg); | |
| 2061 | iter_reg = qla24xx_read_window(reg, 0x5C40, 16, iter_reg); | |
| 2062 | iter_reg = qla24xx_read_window(reg, 0x5C50, 16, iter_reg); | |
| 2063 | iter_reg = qla24xx_read_window(reg, 0x5C60, 16, iter_reg); | |
| 2064 | iter_reg = qla24xx_read_window(reg, 0x5C70, 16, iter_reg); | |
| 2065 | iter_reg = qla24xx_read_window(reg, 0x5C80, 16, iter_reg); | |
| 2066 | iter_reg = qla24xx_read_window(reg, 0x5C90, 16, iter_reg); | |
| 2067 | iter_reg = qla24xx_read_window(reg, 0x5CA0, 16, iter_reg); | |
| 2068 | iter_reg = qla24xx_read_window(reg, 0x5CB0, 16, iter_reg); | |
| 2069 | iter_reg = qla24xx_read_window(reg, 0x5CC0, 16, iter_reg); | |
| 2070 | iter_reg = qla24xx_read_window(reg, 0x5CD0, 16, iter_reg); | |
| 2071 | iter_reg = qla24xx_read_window(reg, 0x5CE0, 16, iter_reg); | |
| 2072 | qla24xx_read_window(reg, 0x5CF0, 16, iter_reg); | |
| 2073 | ||
| 2074 | /* RQ1 Array registers. */ | |
| 2075 | iter_reg = fw->rq1_array_reg; | |
| 2076 | iter_reg = qla24xx_read_window(reg, 0x5D00, 16, iter_reg); | |
| 2077 | iter_reg = qla24xx_read_window(reg, 0x5D10, 16, iter_reg); | |
| 2078 | iter_reg = qla24xx_read_window(reg, 0x5D20, 16, iter_reg); | |
| 2079 | iter_reg = qla24xx_read_window(reg, 0x5D30, 16, iter_reg); | |
| 2080 | iter_reg = qla24xx_read_window(reg, 0x5D40, 16, iter_reg); | |
| 2081 | iter_reg = qla24xx_read_window(reg, 0x5D50, 16, iter_reg); | |
| 2082 | iter_reg = qla24xx_read_window(reg, 0x5D60, 16, iter_reg); | |
| 2083 | iter_reg = qla24xx_read_window(reg, 0x5D70, 16, iter_reg); | |
| 2084 | iter_reg = qla24xx_read_window(reg, 0x5D80, 16, iter_reg); | |
| 2085 | iter_reg = qla24xx_read_window(reg, 0x5D90, 16, iter_reg); | |
| 2086 | iter_reg = qla24xx_read_window(reg, 0x5DA0, 16, iter_reg); | |
| 2087 | iter_reg = qla24xx_read_window(reg, 0x5DB0, 16, iter_reg); | |
| 2088 | iter_reg = qla24xx_read_window(reg, 0x5DC0, 16, iter_reg); | |
| 2089 | iter_reg = qla24xx_read_window(reg, 0x5DD0, 16, iter_reg); | |
| 2090 | iter_reg = qla24xx_read_window(reg, 0x5DE0, 16, iter_reg); | |
| 2091 | qla24xx_read_window(reg, 0x5DF0, 16, iter_reg); | |
| 2092 | ||
| 2093 | /* RP0 Array registers. */ | |
| 2094 | iter_reg = fw->rp0_array_reg; | |
| 2095 | iter_reg = qla24xx_read_window(reg, 0x5E00, 16, iter_reg); | |
| 2096 | iter_reg = qla24xx_read_window(reg, 0x5E10, 16, iter_reg); | |
| 2097 | iter_reg = qla24xx_read_window(reg, 0x5E20, 16, iter_reg); | |
| 2098 | iter_reg = qla24xx_read_window(reg, 0x5E30, 16, iter_reg); | |
| 2099 | iter_reg = qla24xx_read_window(reg, 0x5E40, 16, iter_reg); | |
| 2100 | iter_reg = qla24xx_read_window(reg, 0x5E50, 16, iter_reg); | |
| 2101 | iter_reg = qla24xx_read_window(reg, 0x5E60, 16, iter_reg); | |
| 2102 | iter_reg = qla24xx_read_window(reg, 0x5E70, 16, iter_reg); | |
| 2103 | iter_reg = qla24xx_read_window(reg, 0x5E80, 16, iter_reg); | |
| 2104 | iter_reg = qla24xx_read_window(reg, 0x5E90, 16, iter_reg); | |
| 2105 | iter_reg = qla24xx_read_window(reg, 0x5EA0, 16, iter_reg); | |
| 2106 | iter_reg = qla24xx_read_window(reg, 0x5EB0, 16, iter_reg); | |
| 2107 | iter_reg = qla24xx_read_window(reg, 0x5EC0, 16, iter_reg); | |
| 2108 | iter_reg = qla24xx_read_window(reg, 0x5ED0, 16, iter_reg); | |
| 2109 | iter_reg = qla24xx_read_window(reg, 0x5EE0, 16, iter_reg); | |
| 2110 | qla24xx_read_window(reg, 0x5EF0, 16, iter_reg); | |
| 2111 | ||
| 2112 | /* RP1 Array registers. */ | |
| 2113 | iter_reg = fw->rp1_array_reg; | |
| 2114 | iter_reg = qla24xx_read_window(reg, 0x5F00, 16, iter_reg); | |
| 2115 | iter_reg = qla24xx_read_window(reg, 0x5F10, 16, iter_reg); | |
| 2116 | iter_reg = qla24xx_read_window(reg, 0x5F20, 16, iter_reg); | |
| 2117 | iter_reg = qla24xx_read_window(reg, 0x5F30, 16, iter_reg); | |
| 2118 | iter_reg = qla24xx_read_window(reg, 0x5F40, 16, iter_reg); | |
| 2119 | iter_reg = qla24xx_read_window(reg, 0x5F50, 16, iter_reg); | |
| 2120 | iter_reg = qla24xx_read_window(reg, 0x5F60, 16, iter_reg); | |
| 2121 | iter_reg = qla24xx_read_window(reg, 0x5F70, 16, iter_reg); | |
| 2122 | iter_reg = qla24xx_read_window(reg, 0x5F80, 16, iter_reg); | |
| 2123 | iter_reg = qla24xx_read_window(reg, 0x5F90, 16, iter_reg); | |
| 2124 | iter_reg = qla24xx_read_window(reg, 0x5FA0, 16, iter_reg); | |
| 2125 | iter_reg = qla24xx_read_window(reg, 0x5FB0, 16, iter_reg); | |
| 2126 | iter_reg = qla24xx_read_window(reg, 0x5FC0, 16, iter_reg); | |
| 2127 | iter_reg = qla24xx_read_window(reg, 0x5FD0, 16, iter_reg); | |
| 2128 | iter_reg = qla24xx_read_window(reg, 0x5FE0, 16, iter_reg); | |
| 2129 | qla24xx_read_window(reg, 0x5FF0, 16, iter_reg); | |
| 2130 | ||
| 2131 | iter_reg = fw->at0_array_reg; | |
| 2132 | iter_reg = qla24xx_read_window(reg, 0x7080, 16, iter_reg); | |
| 2133 | iter_reg = qla24xx_read_window(reg, 0x7090, 16, iter_reg); | |
| 2134 | iter_reg = qla24xx_read_window(reg, 0x70A0, 16, iter_reg); | |
| 2135 | iter_reg = qla24xx_read_window(reg, 0x70B0, 16, iter_reg); | |
| 2136 | iter_reg = qla24xx_read_window(reg, 0x70C0, 16, iter_reg); | |
| 2137 | iter_reg = qla24xx_read_window(reg, 0x70D0, 16, iter_reg); | |
| 2138 | iter_reg = qla24xx_read_window(reg, 0x70E0, 16, iter_reg); | |
| 2139 | qla24xx_read_window(reg, 0x70F0, 16, iter_reg); | |
| 2140 | ||
| 2141 | /* I/O Queue Control registers. */ | |
| 2142 | qla24xx_read_window(reg, 0x7800, 16, fw->queue_control_reg); | |
| 2143 | ||
| 2144 | /* Frame Buffer registers. */ | |
| 2145 | iter_reg = fw->fb_hdw_reg; | |
| 2146 | iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); | |
| 2147 | iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); | |
| 2148 | iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); | |
| 2149 | iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); | |
| 2150 | iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); | |
| 2151 | iter_reg = qla24xx_read_window(reg, 0x6060, 16, iter_reg); | |
| 2152 | iter_reg = qla24xx_read_window(reg, 0x6070, 16, iter_reg); | |
| 2153 | iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); | |
| 2154 | iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); | |
| 2155 | iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); | |
| 2156 | iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); | |
| 2157 | iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); | |
| 2158 | iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); | |
| 2159 | iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg); | |
| 2160 | iter_reg = qla24xx_read_window(reg, 0x6530, 16, iter_reg); | |
| 2161 | iter_reg = qla24xx_read_window(reg, 0x6540, 16, iter_reg); | |
| 2162 | iter_reg = qla24xx_read_window(reg, 0x6550, 16, iter_reg); | |
| 2163 | iter_reg = qla24xx_read_window(reg, 0x6560, 16, iter_reg); | |
| 2164 | iter_reg = qla24xx_read_window(reg, 0x6570, 16, iter_reg); | |
| 2165 | iter_reg = qla24xx_read_window(reg, 0x6580, 16, iter_reg); | |
| 2166 | iter_reg = qla24xx_read_window(reg, 0x6590, 16, iter_reg); | |
| 2167 | iter_reg = qla24xx_read_window(reg, 0x65A0, 16, iter_reg); | |
| 2168 | iter_reg = qla24xx_read_window(reg, 0x65B0, 16, iter_reg); | |
| 2169 | iter_reg = qla24xx_read_window(reg, 0x65C0, 16, iter_reg); | |
| 2170 | iter_reg = qla24xx_read_window(reg, 0x65D0, 16, iter_reg); | |
| 2171 | iter_reg = qla24xx_read_window(reg, 0x65E0, 16, iter_reg); | |
| 2172 | qla24xx_read_window(reg, 0x6F00, 16, iter_reg); | |
| 2173 | ||
| 2174 | /* Multi queue registers */ | |
| 2175 | nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, | |
| 2176 | &last_chain); | |
| 2177 | ||
| 2178 | rval = qla24xx_soft_reset(ha); | |
| 2179 | if (rval != QLA_SUCCESS) { | |
| 2180 | ql_log(ql_log_warn, vha, 0xd00e, | |
| 2181 | "SOFT RESET FAILED, forcing continuation of dump!!!\n"); | |
| 2182 | rval = QLA_SUCCESS; | |
| 2183 | ||
| 2184 | ql_log(ql_log_warn, vha, 0xd00f, "try a bigger hammer!!!\n"); | |
| 2185 | ||
| 2186 | WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET); | |
| 2187 | RD_REG_DWORD(®->hccr); | |
| 2188 | ||
| 2189 | WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE); | |
| 2190 | RD_REG_DWORD(®->hccr); | |
| 2191 | ||
| 2192 | WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); | |
| 2193 | RD_REG_DWORD(®->hccr); | |
| 2194 | ||
| 2195 | for (cnt = 30000; cnt && (RD_REG_WORD(®->mailbox0)); cnt--) | |
| 2196 | udelay(5); | |
| 2197 | ||
| 2198 | if (!cnt) { | |
| 2199 | nxt = fw->code_ram; | |
| 2200 | nxt += sizeof(fw->code_ram), | |
| 2201 | nxt += (ha->fw_memory_size - 0x100000 + 1); | |
| 2202 | goto copy_queue; | |
| 2203 | } else | |
| 2204 | ql_log(ql_log_warn, vha, 0xd010, | |
| 2205 | "bigger hammer success?\n"); | |
| 2206 | } | |
| 2207 | ||
| 2208 | rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), | |
| 2209 | &nxt); | |
| 2210 | if (rval != QLA_SUCCESS) | |
| 2211 | goto qla83xx_fw_dump_failed_0; | |
| 2212 | ||
| 2213 | copy_queue: | |
| 2214 | nxt = qla2xxx_copy_queues(ha, nxt); | |
| 2215 | ||
| 2216 | nxt = qla24xx_copy_eft(ha, nxt); | |
| 2217 | ||
| 2218 | /* Chain entries -- started with MQ. */ | |
| 2219 | nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain); | |
| 2220 | nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain); | |
| 2221 | if (last_chain) { | |
| 2222 | ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT); | |
| 2223 | *last_chain |= __constant_htonl(DUMP_CHAIN_LAST); | |
| 2224 | } | |
| 2225 | ||
| 2226 | /* Adjust valid length. */ | |
| 2227 | ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); | |
| 2228 | ||
| 2229 | qla83xx_fw_dump_failed_0: | |
| 2230 | qla2xxx_dump_post_process(base_vha, rval); | |
| 2231 | ||
| 2232 | qla83xx_fw_dump_failed: | |
| 2233 | if (!hardware_locked) | |
| 2234 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
| 2235 | } | |
| 2236 | ||
| 1da177e4 LT |
2237 | /****************************************************************************/ |
| 2238 | /* Driver Debug Functions. */ | |
| 2239 | /****************************************************************************/ | |
| cfb0919c CD |
2240 | |
| 2241 | static inline int | |
| 2242 | ql_mask_match(uint32_t level) | |
| 2243 | { | |
| 2244 | if (ql2xextended_error_logging == 1) | |
| 2245 | ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; | |
| 2246 | return (level & ql2xextended_error_logging) == level; | |
| 2247 | } | |
| 2248 | ||
| 3ce8866c SK |
2249 | /* |
| 2250 | * This function is for formatting and logging debug information. | |
| 2251 | * It is to be used when vha is available. It formats the message | |
| 2252 | * and logs it to the messages file. | |
| 2253 | * parameters: | |
| 2254 | * level: The level of the debug messages to be printed. | |
| 2255 | * If ql2xextended_error_logging value is correctly set, | |
| 2256 | * this message will appear in the messages file. | |
| 2257 | * vha: Pointer to the scsi_qla_host_t. | |
| 2258 | * id: This is a unique identifier for the level. It identifies the | |
| 2259 | * part of the code from where the message originated. | |
| 2260 | * msg: The message to be displayed. | |
| 2261 | */ | |
| 2262 | void | |
| 086b3e8a JP |
2263 | ql_dbg(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...) |
| 2264 | { | |
| 2265 | va_list va; | |
| 2266 | struct va_format vaf; | |
| 3ce8866c | 2267 | |
| cfb0919c | 2268 | if (!ql_mask_match(level)) |
| 086b3e8a | 2269 | return; |
| 3ce8866c | 2270 | |
| 086b3e8a | 2271 | va_start(va, fmt); |
| 3ce8866c | 2272 | |
| 086b3e8a JP |
2273 | vaf.fmt = fmt; |
| 2274 | vaf.va = &va; | |
| 3ce8866c | 2275 | |
| 086b3e8a JP |
2276 | if (vha != NULL) { |
| 2277 | const struct pci_dev *pdev = vha->hw->pdev; | |
| 2278 | /* <module-name> <pci-name> <msg-id>:<host> Message */ | |
| 2279 | pr_warn("%s [%s]-%04x:%ld: %pV", | |
| 2280 | QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, | |
| 2281 | vha->host_no, &vaf); | |
| 2282 | } else { | |
| 2283 | pr_warn("%s [%s]-%04x: : %pV", | |
| 2284 | QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf); | |
| 3ce8866c SK |
2285 | } |
| 2286 | ||
| 086b3e8a | 2287 | va_end(va); |
| 3ce8866c SK |
2288 | |
| 2289 | } | |
| 2290 | ||
| 2291 | /* | |
| 2292 | * This function is for formatting and logging debug information. | |
| 2293 | * It is to be used when vha is not available and pci is availble, | |
| 2294 | * i.e., before host allocation. It formats the message and logs it | |
| 2295 | * to the messages file. | |
| 2296 | * parameters: | |
| 2297 | * level: The level of the debug messages to be printed. | |
| 2298 | * If ql2xextended_error_logging value is correctly set, | |
| 2299 | * this message will appear in the messages file. | |
| 2300 | * pdev: Pointer to the struct pci_dev. | |
| 2301 | * id: This is a unique id for the level. It identifies the part | |
| 2302 | * of the code from where the message originated. | |
| 2303 | * msg: The message to be displayed. | |
| 2304 | */ | |
| 2305 | void | |
| 086b3e8a JP |
2306 | ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id, |
| 2307 | const char *fmt, ...) | |
| 2308 | { | |
| 2309 | va_list va; | |
| 2310 | struct va_format vaf; | |
| 3ce8866c SK |
2311 | |
| 2312 | if (pdev == NULL) | |
| 2313 | return; | |
| cfb0919c | 2314 | if (!ql_mask_match(level)) |
| 086b3e8a | 2315 | return; |
| 3ce8866c | 2316 | |
| 086b3e8a | 2317 | va_start(va, fmt); |
| 3ce8866c | 2318 | |
| 086b3e8a JP |
2319 | vaf.fmt = fmt; |
| 2320 | vaf.va = &va; | |
| 3ce8866c | 2321 | |
| 086b3e8a JP |
2322 | /* <module-name> <dev-name>:<msg-id> Message */ |
| 2323 | pr_warn("%s [%s]-%04x: : %pV", | |
| 2324 | QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, &vaf); | |
| 3ce8866c | 2325 | |
| 086b3e8a | 2326 | va_end(va); |
| 3ce8866c SK |
2327 | } |
| 2328 | ||
| 2329 | /* | |
| 2330 | * This function is for formatting and logging log messages. | |
| 2331 | * It is to be used when vha is available. It formats the message | |
| 2332 | * and logs it to the messages file. All the messages will be logged | |
| 2333 | * irrespective of value of ql2xextended_error_logging. | |
| 2334 | * parameters: | |
| 2335 | * level: The level of the log messages to be printed in the | |
| 2336 | * messages file. | |
| 2337 | * vha: Pointer to the scsi_qla_host_t | |
| 2338 | * id: This is a unique id for the level. It identifies the | |
| 2339 | * part of the code from where the message originated. | |
| 2340 | * msg: The message to be displayed. | |
| 2341 | */ | |
| 2342 | void | |
| 086b3e8a JP |
2343 | ql_log(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...) |
| 2344 | { | |
| 2345 | va_list va; | |
| 2346 | struct va_format vaf; | |
| 2347 | char pbuf[128]; | |
| 3ce8866c | 2348 | |
| 086b3e8a JP |
2349 | if (level > ql_errlev) |
| 2350 | return; | |
| 3ce8866c | 2351 | |
| 086b3e8a JP |
2352 | if (vha != NULL) { |
| 2353 | const struct pci_dev *pdev = vha->hw->pdev; | |
| 2354 | /* <module-name> <msg-id>:<host> Message */ | |
| 2355 | snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x:%ld: ", | |
| 2356 | QL_MSGHDR, dev_name(&(pdev->dev)), id, vha->host_no); | |
| 2357 | } else { | |
| 2358 | snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ", | |
| 2359 | QL_MSGHDR, "0000:00:00.0", id); | |
| 2360 | } | |
| 2361 | pbuf[sizeof(pbuf) - 1] = 0; | |
| 2362 | ||
| 2363 | va_start(va, fmt); | |
| 2364 | ||
| 2365 | vaf.fmt = fmt; | |
| 2366 | vaf.va = &va; | |
| 2367 | ||
| 2368 | switch (level) { | |
| 70a3fc76 | 2369 | case ql_log_fatal: /* FATAL LOG */ |
| 086b3e8a JP |
2370 | pr_crit("%s%pV", pbuf, &vaf); |
| 2371 | break; | |
| 70a3fc76 | 2372 | case ql_log_warn: |
| 086b3e8a JP |
2373 | pr_err("%s%pV", pbuf, &vaf); |
| 2374 | break; | |
| 70a3fc76 | 2375 | case ql_log_info: |
| 086b3e8a JP |
2376 | pr_warn("%s%pV", pbuf, &vaf); |
| 2377 | break; | |
| 2378 | default: | |
| 2379 | pr_info("%s%pV", pbuf, &vaf); | |
| 2380 | break; | |
| 3ce8866c SK |
2381 | } |
| 2382 | ||
| 086b3e8a | 2383 | va_end(va); |
| 3ce8866c SK |
2384 | } |
| 2385 | ||
| 2386 | /* | |
| 2387 | * This function is for formatting and logging log messages. | |
| 2388 | * It is to be used when vha is not available and pci is availble, | |
| 2389 | * i.e., before host allocation. It formats the message and logs | |
| 2390 | * it to the messages file. All the messages are logged irrespective | |
| 2391 | * of the value of ql2xextended_error_logging. | |
| 2392 | * parameters: | |
| 2393 | * level: The level of the log messages to be printed in the | |
| 2394 | * messages file. | |
| 2395 | * pdev: Pointer to the struct pci_dev. | |
| 2396 | * id: This is a unique id for the level. It identifies the | |
| 2397 | * part of the code from where the message originated. | |
| 2398 | * msg: The message to be displayed. | |
| 2399 | */ | |
| 2400 | void | |
| 086b3e8a JP |
2401 | ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id, |
| 2402 | const char *fmt, ...) | |
| 2403 | { | |
| 2404 | va_list va; | |
| 2405 | struct va_format vaf; | |
| 2406 | char pbuf[128]; | |
| 3ce8866c SK |
2407 | |
| 2408 | if (pdev == NULL) | |
| 2409 | return; | |
| 086b3e8a JP |
2410 | if (level > ql_errlev) |
| 2411 | return; | |
| 3ce8866c | 2412 | |
| 086b3e8a JP |
2413 | /* <module-name> <dev-name>:<msg-id> Message */ |
| 2414 | snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ", | |
| 2415 | QL_MSGHDR, dev_name(&(pdev->dev)), id); | |
| 2416 | pbuf[sizeof(pbuf) - 1] = 0; | |
| 2417 | ||
| 2418 | va_start(va, fmt); | |
| 2419 | ||
| 2420 | vaf.fmt = fmt; | |
| 2421 | vaf.va = &va; | |
| 2422 | ||
| 2423 | switch (level) { | |
| 70a3fc76 | 2424 | case ql_log_fatal: /* FATAL LOG */ |
| 086b3e8a JP |
2425 | pr_crit("%s%pV", pbuf, &vaf); |
| 2426 | break; | |
| 70a3fc76 | 2427 | case ql_log_warn: |
| 086b3e8a JP |
2428 | pr_err("%s%pV", pbuf, &vaf); |
| 2429 | break; | |
| 70a3fc76 | 2430 | case ql_log_info: |
| 086b3e8a JP |
2431 | pr_warn("%s%pV", pbuf, &vaf); |
| 2432 | break; | |
| 2433 | default: | |
| 2434 | pr_info("%s%pV", pbuf, &vaf); | |
| 2435 | break; | |
| 3ce8866c SK |
2436 | } |
| 2437 | ||
| 086b3e8a | 2438 | va_end(va); |
| 3ce8866c SK |
2439 | } |
| 2440 | ||
| 2441 | void | |
| 2442 | ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id) | |
| 2443 | { | |
| 2444 | int i; | |
| 2445 | struct qla_hw_data *ha = vha->hw; | |
| 2446 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
| 2447 | struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; | |
| 2448 | struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82; | |
| 2449 | uint16_t __iomem *mbx_reg; | |
| 2450 | ||
| cfb0919c CD |
2451 | if (!ql_mask_match(level)) |
| 2452 | return; | |
| 3ce8866c | 2453 | |
| cfb0919c CD |
2454 | if (IS_QLA82XX(ha)) |
| 2455 | mbx_reg = ®82->mailbox_in[0]; | |
| 2456 | else if (IS_FWI2_CAPABLE(ha)) | |
| 2457 | mbx_reg = ®24->mailbox0; | |
| 2458 | else | |
| 2459 | mbx_reg = MAILBOX_REG(ha, reg, 0); | |
| 2460 | ||
| 2461 | ql_dbg(level, vha, id, "Mailbox registers:\n"); | |
| 2462 | for (i = 0; i < 6; i++) | |
| 2463 | ql_dbg(level, vha, id, | |
| 2464 | "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++)); | |
| 3ce8866c SK |
2465 | } |
| 2466 | ||
| 2467 | ||
| 2468 | void | |
| 2469 | ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id, | |
| 2470 | uint8_t *b, uint32_t size) | |
| 2471 | { | |
| 2472 | uint32_t cnt; | |
| 2473 | uint8_t c; | |
| cfb0919c CD |
2474 | |
| 2475 | if (!ql_mask_match(level)) | |
| 2476 | return; | |
| 2477 | ||
| 2478 | ql_dbg(level, vha, id, " 0 1 2 3 4 5 6 7 8 " | |
| 2479 | "9 Ah Bh Ch Dh Eh Fh\n"); | |
| 2480 | ql_dbg(level, vha, id, "----------------------------------" | |
| 2481 | "----------------------------\n"); | |
| 2482 | ||
| 2483 | ql_dbg(level, vha, id, " "); | |
| 2484 | for (cnt = 0; cnt < size;) { | |
| 2485 | c = *b++; | |
| 2486 | printk("%02x", (uint32_t) c); | |
| 2487 | cnt++; | |
| 2488 | if (!(cnt % 16)) | |
| 2489 | printk("\n"); | |
| 2490 | else | |
| 2491 | printk(" "); | |
| 3ce8866c | 2492 | } |
| cfb0919c CD |
2493 | if (cnt % 16) |
| 2494 | ql_dbg(level, vha, id, "\n"); | |
| 3ce8866c | 2495 | } |