Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
fa90c54f | 2 | * QLogic Fibre Channel HBA Driver |
1e63395c | 3 | * Copyright (c) 2003-2013 QLogic Corporation |
1da177e4 | 4 | * |
fa90c54f | 5 | * See LICENSE.qla2xxx for copyright and licensing details. |
1da177e4 | 6 | */ |
3ce8866c SK |
7 | |
8 | /* | |
9 | * Table for showing the current message id in use for particular level | |
10 | * Change this table for addition of log/debug messages. | |
e02587d7 AE |
11 | * ---------------------------------------------------------------------- |
12 | * | Level | Last Value Used | Holes | | |
13 | * ---------------------------------------------------------------------- | |
6ddcfef7 | 14 | * | Module Init and Probe | 0x0159 | 0x4b,0xba,0xfa | |
c46e65c7 | 15 | * | Mailbox commands | 0x1181 | 0x111a-0x111b | |
e9f4f418 | 16 | * | | | 0x1155-0x1158 | |
1ae47cf3 | 17 | * | | | 0x1018-0x1019 | |
6ddcfef7 | 18 | * | | | 0x1115-0x1116 | |
1ae47cf3 | 19 | * | | | 0x10ca | |
8ae6d9c7 | 20 | * | Device Discovery | 0x2095 | 0x2020-0x2022, | |
6593d5bd | 21 | * | | | 0x2011-0x2012, | |
2a8593f8 | 22 | * | | | 0x2016 | |
8ae6d9c7 | 23 | * | Queue Command and IO tracing | 0x3058 | 0x3006-0x300b | |
9e522cd8 | 24 | * | | | 0x3027-0x3028 | |
8ae6d9c7 GM |
25 | * | | | 0x303d-0x3041 | |
26 | * | | | 0x302d,0x3033 | | |
27 | * | | | 0x3036,0x3038 | | |
28 | * | | | 0x303a | | |
29 | * | DPC Thread | 0x4022 | 0x4002,0x4013 | | |
454073c9 | 30 | * | Async Events | 0x5087 | 0x502b-0x502f | |
9ba56b95 | 31 | * | | | 0x5047,0x5052 | |
6ddcfef7 | 32 | * | | | 0x5084,0x5075 | |
a78951b2 | 33 | * | | | 0x503d,0x5044 | |
71e56003 | 34 | * | Timer Routines | 0x6012 | | |
8c2cf7d4 | 35 | * | User Space Interactions | 0x70e1 | 0x7018,0x702e, | |
78d56df6 | 36 | * | | | 0x7020,0x7024, | |
733a95bd JC |
37 | * | | | 0x7039,0x7045, | |
38 | * | | | 0x7073-0x7075, | | |
8ae6d9c7 | 39 | * | | | 0x707b,0x708c, | |
a9b6f722 SK |
40 | * | | | 0x70a5,0x70a6, | |
41 | * | | | 0x70a8,0x70ab, | | |
8ae6d9c7 | 42 | * | | | 0x70ad-0x70ae, | |
1ae47cf3 | 43 | * | | | 0x70d1-0x70db, | |
a44c72f3 | 44 | * | | | 0x7047,0x703b | |
6ddcfef7 | 45 | * | | | 0x70de-0x70df, | |
5854771e | 46 | * | Task Management | 0x803d | 0x8025-0x8026 | |
cfb0919c | 47 | * | | | 0x800b,0x8039 | |
5f28d2d7 | 48 | * | AER/EEH | 0x9011 | | |
e02587d7 | 49 | * | Virtual Port | 0xa007 | | |
7ec0effd AD |
50 | * | ISP82XX Specific | 0xb14c | 0xb002,0xb024 | |
51 | * | | | 0xb09e,0xb0ae | | |
52 | * | | | 0xb0e0-0xb0ef | | |
53 | * | | | 0xb085,0xb0dc | | |
54 | * | | | 0xb107,0xb108 | | |
55 | * | | | 0xb111,0xb11e | | |
56 | * | | | 0xb12c,0xb12d | | |
57 | * | | | 0xb13a,0xb142 | | |
58 | * | | | 0xb13c-0xb140 | | |
6ddcfef7 | 59 | * | | | 0xb149 | |
6246b8a1 GM |
60 | * | MultiQ | 0xc00c | | |
61 | * | Misc | 0xd010 | | | |
6ddcfef7 SK |
62 | * | Target Mode | 0xe070 | 0xe021 | |
63 | * | Target Mode Management | 0xf072 | 0xf002-0xf003 | | |
64 | * | | | 0xf046-0xf049 | | |
2d70c103 | 65 | * | Target Mode Task Management | 0x1000b | | |
e02587d7 | 66 | * ---------------------------------------------------------------------- |
3ce8866c SK |
67 | */ |
68 | ||
1da177e4 LT |
69 | #include "qla_def.h" |
70 | ||
71 | #include <linux/delay.h> | |
72 | ||
3ce8866c SK |
73 | static uint32_t ql_dbg_offset = 0x800; |
74 | ||
a7a167bf | 75 | static inline void |
7b867cf7 | 76 | qla2xxx_prep_dump(struct qla_hw_data *ha, struct qla2xxx_fw_dump *fw_dump) |
a7a167bf AV |
77 | { |
78 | fw_dump->fw_major_version = htonl(ha->fw_major_version); | |
79 | fw_dump->fw_minor_version = htonl(ha->fw_minor_version); | |
80 | fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version); | |
81 | fw_dump->fw_attributes = htonl(ha->fw_attributes); | |
82 | ||
83 | fw_dump->vendor = htonl(ha->pdev->vendor); | |
84 | fw_dump->device = htonl(ha->pdev->device); | |
85 | fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor); | |
86 | fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device); | |
87 | } | |
88 | ||
89 | static inline void * | |
73208dfd | 90 | qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr) |
a7a167bf | 91 | { |
73208dfd AC |
92 | struct req_que *req = ha->req_q_map[0]; |
93 | struct rsp_que *rsp = ha->rsp_q_map[0]; | |
a7a167bf | 94 | /* Request queue. */ |
7b867cf7 | 95 | memcpy(ptr, req->ring, req->length * |
a7a167bf AV |
96 | sizeof(request_t)); |
97 | ||
98 | /* Response queue. */ | |
7b867cf7 AC |
99 | ptr += req->length * sizeof(request_t); |
100 | memcpy(ptr, rsp->ring, rsp->length * | |
a7a167bf AV |
101 | sizeof(response_t)); |
102 | ||
7b867cf7 | 103 | return ptr + (rsp->length * sizeof(response_t)); |
a7a167bf | 104 | } |
1da177e4 | 105 | |
c3a2f0df | 106 | static int |
7b867cf7 | 107 | qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram, |
c5722708 | 108 | uint32_t ram_dwords, void **nxt) |
c3a2f0df AV |
109 | { |
110 | int rval; | |
c5722708 AV |
111 | uint32_t cnt, stat, timer, dwords, idx; |
112 | uint16_t mb0; | |
c3a2f0df | 113 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
c5722708 AV |
114 | dma_addr_t dump_dma = ha->gid_list_dma; |
115 | uint32_t *dump = (uint32_t *)ha->gid_list; | |
c3a2f0df AV |
116 | |
117 | rval = QLA_SUCCESS; | |
c5722708 | 118 | mb0 = 0; |
c3a2f0df | 119 | |
c5722708 | 120 | WRT_REG_WORD(®->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED); |
c3a2f0df AV |
121 | clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); |
122 | ||
642ef983 | 123 | dwords = qla2x00_gid_list_size(ha) / 4; |
c5722708 AV |
124 | for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS; |
125 | cnt += dwords, addr += dwords) { | |
126 | if (cnt + dwords > ram_dwords) | |
127 | dwords = ram_dwords - cnt; | |
c3a2f0df | 128 | |
c5722708 AV |
129 | WRT_REG_WORD(®->mailbox1, LSW(addr)); |
130 | WRT_REG_WORD(®->mailbox8, MSW(addr)); | |
c3a2f0df | 131 | |
c5722708 AV |
132 | WRT_REG_WORD(®->mailbox2, MSW(dump_dma)); |
133 | WRT_REG_WORD(®->mailbox3, LSW(dump_dma)); | |
134 | WRT_REG_WORD(®->mailbox6, MSW(MSD(dump_dma))); | |
135 | WRT_REG_WORD(®->mailbox7, LSW(MSD(dump_dma))); | |
c3a2f0df | 136 | |
c5722708 AV |
137 | WRT_REG_WORD(®->mailbox4, MSW(dwords)); |
138 | WRT_REG_WORD(®->mailbox5, LSW(dwords)); | |
c3a2f0df AV |
139 | WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); |
140 | ||
141 | for (timer = 6000000; timer; timer--) { | |
142 | /* Check for pending interrupts. */ | |
143 | stat = RD_REG_DWORD(®->host_status); | |
144 | if (stat & HSRX_RISC_INT) { | |
145 | stat &= 0xff; | |
146 | ||
147 | if (stat == 0x1 || stat == 0x2 || | |
148 | stat == 0x10 || stat == 0x11) { | |
149 | set_bit(MBX_INTERRUPT, | |
150 | &ha->mbx_cmd_flags); | |
151 | ||
c5722708 | 152 | mb0 = RD_REG_WORD(®->mailbox0); |
c3a2f0df AV |
153 | |
154 | WRT_REG_DWORD(®->hccr, | |
155 | HCCRX_CLR_RISC_INT); | |
156 | RD_REG_DWORD(®->hccr); | |
157 | break; | |
158 | } | |
159 | ||
160 | /* Clear this intr; it wasn't a mailbox intr */ | |
161 | WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); | |
162 | RD_REG_DWORD(®->hccr); | |
163 | } | |
164 | udelay(5); | |
165 | } | |
166 | ||
167 | if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { | |
c5722708 AV |
168 | rval = mb0 & MBS_MASK; |
169 | for (idx = 0; idx < dwords; idx++) | |
170 | ram[cnt + idx] = swab32(dump[idx]); | |
c3a2f0df AV |
171 | } else { |
172 | rval = QLA_FUNCTION_FAILED; | |
173 | } | |
174 | } | |
175 | ||
c5722708 | 176 | *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL; |
c3a2f0df AV |
177 | return rval; |
178 | } | |
179 | ||
c5722708 | 180 | static int |
7b867cf7 | 181 | qla24xx_dump_memory(struct qla_hw_data *ha, uint32_t *code_ram, |
c5722708 AV |
182 | uint32_t cram_size, void **nxt) |
183 | { | |
184 | int rval; | |
185 | ||
186 | /* Code RAM. */ | |
187 | rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt); | |
188 | if (rval != QLA_SUCCESS) | |
189 | return rval; | |
190 | ||
191 | /* External Memory. */ | |
192 | return qla24xx_dump_ram(ha, 0x100000, *nxt, | |
193 | ha->fw_memory_size - 0x100000 + 1, nxt); | |
194 | } | |
195 | ||
c81d04c9 AV |
196 | static uint32_t * |
197 | qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase, | |
198 | uint32_t count, uint32_t *buf) | |
199 | { | |
200 | uint32_t __iomem *dmp_reg; | |
201 | ||
202 | WRT_REG_DWORD(®->iobase_addr, iobase); | |
203 | dmp_reg = ®->iobase_window; | |
204 | while (count--) | |
205 | *buf++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
206 | ||
207 | return buf; | |
208 | } | |
209 | ||
210 | static inline int | |
211 | qla24xx_pause_risc(struct device_reg_24xx __iomem *reg) | |
212 | { | |
213 | int rval = QLA_SUCCESS; | |
214 | uint32_t cnt; | |
215 | ||
c3b058af | 216 | WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE); |
aed10881 AV |
217 | for (cnt = 30000; |
218 | ((RD_REG_DWORD(®->host_status) & HSRX_RISC_PAUSED) == 0) && | |
c3b058af AV |
219 | rval == QLA_SUCCESS; cnt--) { |
220 | if (cnt) | |
221 | udelay(100); | |
222 | else | |
223 | rval = QLA_FUNCTION_TIMEOUT; | |
c81d04c9 AV |
224 | } |
225 | ||
226 | return rval; | |
227 | } | |
228 | ||
229 | static int | |
7b867cf7 | 230 | qla24xx_soft_reset(struct qla_hw_data *ha) |
c81d04c9 AV |
231 | { |
232 | int rval = QLA_SUCCESS; | |
233 | uint32_t cnt; | |
234 | uint16_t mb0, wd; | |
235 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
236 | ||
237 | /* Reset RISC. */ | |
238 | WRT_REG_DWORD(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); | |
239 | for (cnt = 0; cnt < 30000; cnt++) { | |
240 | if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) | |
241 | break; | |
242 | ||
243 | udelay(10); | |
244 | } | |
245 | ||
246 | WRT_REG_DWORD(®->ctrl_status, | |
247 | CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); | |
248 | pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); | |
249 | ||
250 | udelay(100); | |
251 | /* Wait for firmware to complete NVRAM accesses. */ | |
252 | mb0 = (uint32_t) RD_REG_WORD(®->mailbox0); | |
253 | for (cnt = 10000 ; cnt && mb0; cnt--) { | |
254 | udelay(5); | |
255 | mb0 = (uint32_t) RD_REG_WORD(®->mailbox0); | |
256 | barrier(); | |
257 | } | |
258 | ||
259 | /* Wait for soft-reset to complete. */ | |
260 | for (cnt = 0; cnt < 30000; cnt++) { | |
261 | if ((RD_REG_DWORD(®->ctrl_status) & | |
262 | CSRX_ISP_SOFT_RESET) == 0) | |
263 | break; | |
264 | ||
265 | udelay(10); | |
266 | } | |
267 | WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); | |
268 | RD_REG_DWORD(®->hccr); /* PCI Posting. */ | |
269 | ||
270 | for (cnt = 30000; RD_REG_WORD(®->mailbox0) != 0 && | |
271 | rval == QLA_SUCCESS; cnt--) { | |
272 | if (cnt) | |
273 | udelay(100); | |
274 | else | |
275 | rval = QLA_FUNCTION_TIMEOUT; | |
276 | } | |
277 | ||
278 | return rval; | |
279 | } | |
280 | ||
c5722708 | 281 | static int |
7b867cf7 | 282 | qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint16_t *ram, |
e18e963b | 283 | uint32_t ram_words, void **nxt) |
c5722708 AV |
284 | { |
285 | int rval; | |
286 | uint32_t cnt, stat, timer, words, idx; | |
287 | uint16_t mb0; | |
288 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
289 | dma_addr_t dump_dma = ha->gid_list_dma; | |
290 | uint16_t *dump = (uint16_t *)ha->gid_list; | |
291 | ||
292 | rval = QLA_SUCCESS; | |
293 | mb0 = 0; | |
294 | ||
295 | WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED); | |
296 | clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | |
297 | ||
642ef983 | 298 | words = qla2x00_gid_list_size(ha) / 2; |
c5722708 AV |
299 | for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS; |
300 | cnt += words, addr += words) { | |
301 | if (cnt + words > ram_words) | |
302 | words = ram_words - cnt; | |
303 | ||
304 | WRT_MAILBOX_REG(ha, reg, 1, LSW(addr)); | |
305 | WRT_MAILBOX_REG(ha, reg, 8, MSW(addr)); | |
306 | ||
307 | WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma)); | |
308 | WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma)); | |
309 | WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma))); | |
310 | WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma))); | |
311 | ||
312 | WRT_MAILBOX_REG(ha, reg, 4, words); | |
313 | WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); | |
314 | ||
315 | for (timer = 6000000; timer; timer--) { | |
316 | /* Check for pending interrupts. */ | |
317 | stat = RD_REG_DWORD(®->u.isp2300.host_status); | |
318 | if (stat & HSR_RISC_INT) { | |
319 | stat &= 0xff; | |
320 | ||
321 | if (stat == 0x1 || stat == 0x2) { | |
322 | set_bit(MBX_INTERRUPT, | |
323 | &ha->mbx_cmd_flags); | |
324 | ||
325 | mb0 = RD_MAILBOX_REG(ha, reg, 0); | |
326 | ||
327 | /* Release mailbox registers. */ | |
328 | WRT_REG_WORD(®->semaphore, 0); | |
329 | WRT_REG_WORD(®->hccr, | |
330 | HCCR_CLR_RISC_INT); | |
331 | RD_REG_WORD(®->hccr); | |
332 | break; | |
333 | } else if (stat == 0x10 || stat == 0x11) { | |
334 | set_bit(MBX_INTERRUPT, | |
335 | &ha->mbx_cmd_flags); | |
336 | ||
337 | mb0 = RD_MAILBOX_REG(ha, reg, 0); | |
338 | ||
339 | WRT_REG_WORD(®->hccr, | |
340 | HCCR_CLR_RISC_INT); | |
341 | RD_REG_WORD(®->hccr); | |
342 | break; | |
343 | } | |
344 | ||
345 | /* clear this intr; it wasn't a mailbox intr */ | |
346 | WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); | |
347 | RD_REG_WORD(®->hccr); | |
348 | } | |
349 | udelay(5); | |
350 | } | |
351 | ||
352 | if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { | |
353 | rval = mb0 & MBS_MASK; | |
354 | for (idx = 0; idx < words; idx++) | |
355 | ram[cnt + idx] = swab16(dump[idx]); | |
356 | } else { | |
357 | rval = QLA_FUNCTION_FAILED; | |
358 | } | |
359 | } | |
360 | ||
361 | *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL; | |
362 | return rval; | |
363 | } | |
364 | ||
c81d04c9 AV |
365 | static inline void |
366 | qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count, | |
367 | uint16_t *buf) | |
368 | { | |
369 | uint16_t __iomem *dmp_reg = ®->u.isp2300.fb_cmd; | |
370 | ||
371 | while (count--) | |
372 | *buf++ = htons(RD_REG_WORD(dmp_reg++)); | |
373 | } | |
374 | ||
bb99de67 AV |
375 | static inline void * |
376 | qla24xx_copy_eft(struct qla_hw_data *ha, void *ptr) | |
377 | { | |
378 | if (!ha->eft) | |
379 | return ptr; | |
380 | ||
381 | memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size)); | |
382 | return ptr + ntohl(ha->fw_dump->eft_size); | |
383 | } | |
384 | ||
385 | static inline void * | |
386 | qla25xx_copy_fce(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) | |
387 | { | |
388 | uint32_t cnt; | |
389 | uint32_t *iter_reg; | |
390 | struct qla2xxx_fce_chain *fcec = ptr; | |
391 | ||
392 | if (!ha->fce) | |
393 | return ptr; | |
394 | ||
395 | *last_chain = &fcec->type; | |
396 | fcec->type = __constant_htonl(DUMP_CHAIN_FCE); | |
397 | fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) + | |
398 | fce_calc_size(ha->fce_bufs)); | |
399 | fcec->size = htonl(fce_calc_size(ha->fce_bufs)); | |
400 | fcec->addr_l = htonl(LSD(ha->fce_dma)); | |
401 | fcec->addr_h = htonl(MSD(ha->fce_dma)); | |
402 | ||
403 | iter_reg = fcec->eregs; | |
404 | for (cnt = 0; cnt < 8; cnt++) | |
405 | *iter_reg++ = htonl(ha->fce_mb[cnt]); | |
406 | ||
407 | memcpy(iter_reg, ha->fce, ntohl(fcec->size)); | |
408 | ||
3cb0a67d | 409 | return (char *)iter_reg + ntohl(fcec->size); |
bb99de67 AV |
410 | } |
411 | ||
2d70c103 NB |
412 | static inline void * |
413 | qla2xxx_copy_atioqueues(struct qla_hw_data *ha, void *ptr, | |
414 | uint32_t **last_chain) | |
415 | { | |
416 | struct qla2xxx_mqueue_chain *q; | |
417 | struct qla2xxx_mqueue_header *qh; | |
418 | uint32_t num_queues; | |
419 | int que; | |
420 | struct { | |
421 | int length; | |
422 | void *ring; | |
423 | } aq, *aqp; | |
424 | ||
00876ae8 | 425 | if (!ha->tgt.atio_ring) |
2d70c103 NB |
426 | return ptr; |
427 | ||
428 | num_queues = 1; | |
429 | aqp = &aq; | |
430 | aqp->length = ha->tgt.atio_q_length; | |
431 | aqp->ring = ha->tgt.atio_ring; | |
432 | ||
433 | for (que = 0; que < num_queues; que++) { | |
434 | /* aqp = ha->atio_q_map[que]; */ | |
435 | q = ptr; | |
436 | *last_chain = &q->type; | |
437 | q->type = __constant_htonl(DUMP_CHAIN_QUEUE); | |
438 | q->chain_size = htonl( | |
439 | sizeof(struct qla2xxx_mqueue_chain) + | |
440 | sizeof(struct qla2xxx_mqueue_header) + | |
441 | (aqp->length * sizeof(request_t))); | |
442 | ptr += sizeof(struct qla2xxx_mqueue_chain); | |
443 | ||
444 | /* Add header. */ | |
445 | qh = ptr; | |
446 | qh->queue = __constant_htonl(TYPE_ATIO_QUEUE); | |
447 | qh->number = htonl(que); | |
448 | qh->size = htonl(aqp->length * sizeof(request_t)); | |
449 | ptr += sizeof(struct qla2xxx_mqueue_header); | |
450 | ||
451 | /* Add data. */ | |
452 | memcpy(ptr, aqp->ring, aqp->length * sizeof(request_t)); | |
453 | ||
454 | ptr += aqp->length * sizeof(request_t); | |
455 | } | |
456 | ||
457 | return ptr; | |
458 | } | |
459 | ||
050c9bb1 GM |
460 | static inline void * |
461 | qla25xx_copy_mqueues(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) | |
462 | { | |
463 | struct qla2xxx_mqueue_chain *q; | |
464 | struct qla2xxx_mqueue_header *qh; | |
465 | struct req_que *req; | |
466 | struct rsp_que *rsp; | |
467 | int que; | |
468 | ||
469 | if (!ha->mqenable) | |
470 | return ptr; | |
471 | ||
472 | /* Request queues */ | |
473 | for (que = 1; que < ha->max_req_queues; que++) { | |
474 | req = ha->req_q_map[que]; | |
475 | if (!req) | |
476 | break; | |
477 | ||
478 | /* Add chain. */ | |
479 | q = ptr; | |
480 | *last_chain = &q->type; | |
481 | q->type = __constant_htonl(DUMP_CHAIN_QUEUE); | |
482 | q->chain_size = htonl( | |
483 | sizeof(struct qla2xxx_mqueue_chain) + | |
484 | sizeof(struct qla2xxx_mqueue_header) + | |
485 | (req->length * sizeof(request_t))); | |
486 | ptr += sizeof(struct qla2xxx_mqueue_chain); | |
487 | ||
488 | /* Add header. */ | |
489 | qh = ptr; | |
490 | qh->queue = __constant_htonl(TYPE_REQUEST_QUEUE); | |
491 | qh->number = htonl(que); | |
492 | qh->size = htonl(req->length * sizeof(request_t)); | |
493 | ptr += sizeof(struct qla2xxx_mqueue_header); | |
494 | ||
495 | /* Add data. */ | |
496 | memcpy(ptr, req->ring, req->length * sizeof(request_t)); | |
497 | ptr += req->length * sizeof(request_t); | |
498 | } | |
499 | ||
500 | /* Response queues */ | |
501 | for (que = 1; que < ha->max_rsp_queues; que++) { | |
502 | rsp = ha->rsp_q_map[que]; | |
503 | if (!rsp) | |
504 | break; | |
505 | ||
506 | /* Add chain. */ | |
507 | q = ptr; | |
508 | *last_chain = &q->type; | |
509 | q->type = __constant_htonl(DUMP_CHAIN_QUEUE); | |
510 | q->chain_size = htonl( | |
511 | sizeof(struct qla2xxx_mqueue_chain) + | |
512 | sizeof(struct qla2xxx_mqueue_header) + | |
513 | (rsp->length * sizeof(response_t))); | |
514 | ptr += sizeof(struct qla2xxx_mqueue_chain); | |
515 | ||
516 | /* Add header. */ | |
517 | qh = ptr; | |
518 | qh->queue = __constant_htonl(TYPE_RESPONSE_QUEUE); | |
519 | qh->number = htonl(que); | |
520 | qh->size = htonl(rsp->length * sizeof(response_t)); | |
521 | ptr += sizeof(struct qla2xxx_mqueue_header); | |
522 | ||
523 | /* Add data. */ | |
524 | memcpy(ptr, rsp->ring, rsp->length * sizeof(response_t)); | |
525 | ptr += rsp->length * sizeof(response_t); | |
526 | } | |
527 | ||
528 | return ptr; | |
529 | } | |
530 | ||
d63ab533 AV |
531 | static inline void * |
532 | qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) | |
533 | { | |
534 | uint32_t cnt, que_idx; | |
2afa19a9 | 535 | uint8_t que_cnt; |
d63ab533 | 536 | struct qla2xxx_mq_chain *mq = ptr; |
da9b1d5c | 537 | device_reg_t __iomem *reg; |
d63ab533 | 538 | |
6246b8a1 | 539 | if (!ha->mqenable || IS_QLA83XX(ha)) |
d63ab533 AV |
540 | return ptr; |
541 | ||
542 | mq = ptr; | |
543 | *last_chain = &mq->type; | |
544 | mq->type = __constant_htonl(DUMP_CHAIN_MQ); | |
545 | mq->chain_size = __constant_htonl(sizeof(struct qla2xxx_mq_chain)); | |
546 | ||
2afa19a9 AC |
547 | que_cnt = ha->max_req_queues > ha->max_rsp_queues ? |
548 | ha->max_req_queues : ha->max_rsp_queues; | |
d63ab533 AV |
549 | mq->count = htonl(que_cnt); |
550 | for (cnt = 0; cnt < que_cnt; cnt++) { | |
da9b1d5c | 551 | reg = ISP_QUE_REG(ha, cnt); |
d63ab533 | 552 | que_idx = cnt * 4; |
da9b1d5c AV |
553 | mq->qregs[que_idx] = |
554 | htonl(RD_REG_DWORD(®->isp25mq.req_q_in)); | |
555 | mq->qregs[que_idx+1] = | |
556 | htonl(RD_REG_DWORD(®->isp25mq.req_q_out)); | |
557 | mq->qregs[que_idx+2] = | |
558 | htonl(RD_REG_DWORD(®->isp25mq.rsp_q_in)); | |
559 | mq->qregs[que_idx+3] = | |
560 | htonl(RD_REG_DWORD(®->isp25mq.rsp_q_out)); | |
d63ab533 AV |
561 | } |
562 | ||
563 | return ptr + sizeof(struct qla2xxx_mq_chain); | |
564 | } | |
565 | ||
08de2844 | 566 | void |
3420d36c AV |
567 | qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval) |
568 | { | |
569 | struct qla_hw_data *ha = vha->hw; | |
570 | ||
571 | if (rval != QLA_SUCCESS) { | |
7c3df132 SK |
572 | ql_log(ql_log_warn, vha, 0xd000, |
573 | "Failed to dump firmware (%x).\n", rval); | |
3420d36c AV |
574 | ha->fw_dumped = 0; |
575 | } else { | |
7c3df132 | 576 | ql_log(ql_log_info, vha, 0xd001, |
3420d36c AV |
577 | "Firmware dump saved to temp buffer (%ld/%p).\n", |
578 | vha->host_no, ha->fw_dump); | |
579 | ha->fw_dumped = 1; | |
580 | qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); | |
581 | } | |
582 | } | |
583 | ||
1da177e4 LT |
584 | /** |
585 | * qla2300_fw_dump() - Dumps binary data from the 2300 firmware. | |
586 | * @ha: HA context | |
587 | * @hardware_locked: Called with the hardware_lock | |
588 | */ | |
589 | void | |
7b867cf7 | 590 | qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
1da177e4 LT |
591 | { |
592 | int rval; | |
c5722708 | 593 | uint32_t cnt; |
7b867cf7 | 594 | struct qla_hw_data *ha = vha->hw; |
3d71644c | 595 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 LT |
596 | uint16_t __iomem *dmp_reg; |
597 | unsigned long flags; | |
598 | struct qla2300_fw_dump *fw; | |
c5722708 | 599 | void *nxt; |
73208dfd | 600 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
1da177e4 | 601 | |
1da177e4 LT |
602 | flags = 0; |
603 | ||
604 | if (!hardware_locked) | |
605 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
606 | ||
d4e3e04d | 607 | if (!ha->fw_dump) { |
7c3df132 SK |
608 | ql_log(ql_log_warn, vha, 0xd002, |
609 | "No buffer available for dump.\n"); | |
1da177e4 LT |
610 | goto qla2300_fw_dump_failed; |
611 | } | |
612 | ||
d4e3e04d | 613 | if (ha->fw_dumped) { |
7c3df132 SK |
614 | ql_log(ql_log_warn, vha, 0xd003, |
615 | "Firmware has been previously dumped (%p) " | |
616 | "-- ignoring request.\n", | |
617 | ha->fw_dump); | |
1da177e4 LT |
618 | goto qla2300_fw_dump_failed; |
619 | } | |
a7a167bf AV |
620 | fw = &ha->fw_dump->isp.isp23; |
621 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
1da177e4 LT |
622 | |
623 | rval = QLA_SUCCESS; | |
a7a167bf | 624 | fw->hccr = htons(RD_REG_WORD(®->hccr)); |
1da177e4 LT |
625 | |
626 | /* Pause RISC. */ | |
fa2a1ce5 | 627 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); |
1da177e4 LT |
628 | if (IS_QLA2300(ha)) { |
629 | for (cnt = 30000; | |
630 | (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && | |
631 | rval == QLA_SUCCESS; cnt--) { | |
632 | if (cnt) | |
633 | udelay(100); | |
634 | else | |
635 | rval = QLA_FUNCTION_TIMEOUT; | |
636 | } | |
637 | } else { | |
638 | RD_REG_WORD(®->hccr); /* PCI Posting. */ | |
639 | udelay(10); | |
640 | } | |
641 | ||
642 | if (rval == QLA_SUCCESS) { | |
c81d04c9 | 643 | dmp_reg = ®->flash_address; |
fa2a1ce5 | 644 | for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) |
a7a167bf | 645 | fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 646 | |
c81d04c9 | 647 | dmp_reg = ®->u.isp2300.req_q_in; |
fa2a1ce5 | 648 | for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++) |
a7a167bf | 649 | fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 650 | |
c81d04c9 | 651 | dmp_reg = ®->u.isp2300.mailbox0; |
fa2a1ce5 | 652 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) |
a7a167bf | 653 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 LT |
654 | |
655 | WRT_REG_WORD(®->ctrl_status, 0x40); | |
c81d04c9 | 656 | qla2xxx_read_window(reg, 32, fw->resp_dma_reg); |
1da177e4 LT |
657 | |
658 | WRT_REG_WORD(®->ctrl_status, 0x50); | |
c81d04c9 | 659 | qla2xxx_read_window(reg, 48, fw->dma_reg); |
1da177e4 LT |
660 | |
661 | WRT_REG_WORD(®->ctrl_status, 0x00); | |
c81d04c9 | 662 | dmp_reg = ®->risc_hw; |
fa2a1ce5 | 663 | for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) |
a7a167bf | 664 | fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 665 | |
fa2a1ce5 | 666 | WRT_REG_WORD(®->pcr, 0x2000); |
c81d04c9 | 667 | qla2xxx_read_window(reg, 16, fw->risc_gp0_reg); |
1da177e4 | 668 | |
fa2a1ce5 | 669 | WRT_REG_WORD(®->pcr, 0x2200); |
c81d04c9 | 670 | qla2xxx_read_window(reg, 16, fw->risc_gp1_reg); |
1da177e4 | 671 | |
fa2a1ce5 | 672 | WRT_REG_WORD(®->pcr, 0x2400); |
c81d04c9 | 673 | qla2xxx_read_window(reg, 16, fw->risc_gp2_reg); |
1da177e4 | 674 | |
fa2a1ce5 | 675 | WRT_REG_WORD(®->pcr, 0x2600); |
c81d04c9 | 676 | qla2xxx_read_window(reg, 16, fw->risc_gp3_reg); |
1da177e4 | 677 | |
fa2a1ce5 | 678 | WRT_REG_WORD(®->pcr, 0x2800); |
c81d04c9 | 679 | qla2xxx_read_window(reg, 16, fw->risc_gp4_reg); |
1da177e4 | 680 | |
fa2a1ce5 | 681 | WRT_REG_WORD(®->pcr, 0x2A00); |
c81d04c9 | 682 | qla2xxx_read_window(reg, 16, fw->risc_gp5_reg); |
1da177e4 | 683 | |
fa2a1ce5 | 684 | WRT_REG_WORD(®->pcr, 0x2C00); |
c81d04c9 | 685 | qla2xxx_read_window(reg, 16, fw->risc_gp6_reg); |
1da177e4 | 686 | |
fa2a1ce5 | 687 | WRT_REG_WORD(®->pcr, 0x2E00); |
c81d04c9 | 688 | qla2xxx_read_window(reg, 16, fw->risc_gp7_reg); |
1da177e4 | 689 | |
fa2a1ce5 | 690 | WRT_REG_WORD(®->ctrl_status, 0x10); |
c81d04c9 | 691 | qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg); |
1da177e4 | 692 | |
fa2a1ce5 | 693 | WRT_REG_WORD(®->ctrl_status, 0x20); |
c81d04c9 | 694 | qla2xxx_read_window(reg, 64, fw->fpm_b0_reg); |
1da177e4 | 695 | |
fa2a1ce5 | 696 | WRT_REG_WORD(®->ctrl_status, 0x30); |
c81d04c9 | 697 | qla2xxx_read_window(reg, 64, fw->fpm_b1_reg); |
1da177e4 LT |
698 | |
699 | /* Reset RISC. */ | |
700 | WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); | |
701 | for (cnt = 0; cnt < 30000; cnt++) { | |
702 | if ((RD_REG_WORD(®->ctrl_status) & | |
703 | CSR_ISP_SOFT_RESET) == 0) | |
704 | break; | |
705 | ||
706 | udelay(10); | |
707 | } | |
708 | } | |
709 | ||
710 | if (!IS_QLA2300(ha)) { | |
711 | for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && | |
712 | rval == QLA_SUCCESS; cnt--) { | |
713 | if (cnt) | |
714 | udelay(100); | |
715 | else | |
716 | rval = QLA_FUNCTION_TIMEOUT; | |
717 | } | |
718 | } | |
719 | ||
c5722708 AV |
720 | /* Get RISC SRAM. */ |
721 | if (rval == QLA_SUCCESS) | |
722 | rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram, | |
723 | sizeof(fw->risc_ram) / 2, &nxt); | |
1da177e4 | 724 | |
c5722708 AV |
725 | /* Get stack SRAM. */ |
726 | if (rval == QLA_SUCCESS) | |
727 | rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram, | |
728 | sizeof(fw->stack_ram) / 2, &nxt); | |
1da177e4 | 729 | |
c5722708 AV |
730 | /* Get data SRAM. */ |
731 | if (rval == QLA_SUCCESS) | |
732 | rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram, | |
733 | ha->fw_memory_size - 0x11000 + 1, &nxt); | |
1da177e4 | 734 | |
a7a167bf | 735 | if (rval == QLA_SUCCESS) |
73208dfd | 736 | qla2xxx_copy_queues(ha, nxt); |
a7a167bf | 737 | |
3420d36c | 738 | qla2xxx_dump_post_process(base_vha, rval); |
1da177e4 LT |
739 | |
740 | qla2300_fw_dump_failed: | |
741 | if (!hardware_locked) | |
742 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
743 | } | |
744 | ||
1da177e4 LT |
745 | /** |
746 | * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware. | |
747 | * @ha: HA context | |
748 | * @hardware_locked: Called with the hardware_lock | |
749 | */ | |
750 | void | |
7b867cf7 | 751 | qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
1da177e4 LT |
752 | { |
753 | int rval; | |
754 | uint32_t cnt, timer; | |
755 | uint16_t risc_address; | |
756 | uint16_t mb0, mb2; | |
7b867cf7 | 757 | struct qla_hw_data *ha = vha->hw; |
3d71644c | 758 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 LT |
759 | uint16_t __iomem *dmp_reg; |
760 | unsigned long flags; | |
761 | struct qla2100_fw_dump *fw; | |
73208dfd | 762 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
1da177e4 LT |
763 | |
764 | risc_address = 0; | |
765 | mb0 = mb2 = 0; | |
766 | flags = 0; | |
767 | ||
768 | if (!hardware_locked) | |
769 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
770 | ||
d4e3e04d | 771 | if (!ha->fw_dump) { |
7c3df132 SK |
772 | ql_log(ql_log_warn, vha, 0xd004, |
773 | "No buffer available for dump.\n"); | |
1da177e4 LT |
774 | goto qla2100_fw_dump_failed; |
775 | } | |
776 | ||
d4e3e04d | 777 | if (ha->fw_dumped) { |
7c3df132 SK |
778 | ql_log(ql_log_warn, vha, 0xd005, |
779 | "Firmware has been previously dumped (%p) " | |
780 | "-- ignoring request.\n", | |
781 | ha->fw_dump); | |
1da177e4 LT |
782 | goto qla2100_fw_dump_failed; |
783 | } | |
a7a167bf AV |
784 | fw = &ha->fw_dump->isp.isp21; |
785 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
1da177e4 LT |
786 | |
787 | rval = QLA_SUCCESS; | |
a7a167bf | 788 | fw->hccr = htons(RD_REG_WORD(®->hccr)); |
1da177e4 LT |
789 | |
790 | /* Pause RISC. */ | |
fa2a1ce5 | 791 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); |
1da177e4 LT |
792 | for (cnt = 30000; (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && |
793 | rval == QLA_SUCCESS; cnt--) { | |
794 | if (cnt) | |
795 | udelay(100); | |
796 | else | |
797 | rval = QLA_FUNCTION_TIMEOUT; | |
798 | } | |
799 | if (rval == QLA_SUCCESS) { | |
c81d04c9 | 800 | dmp_reg = ®->flash_address; |
fa2a1ce5 | 801 | for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) |
a7a167bf | 802 | fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 803 | |
c81d04c9 | 804 | dmp_reg = ®->u.isp2100.mailbox0; |
1da177e4 | 805 | for (cnt = 0; cnt < ha->mbx_count; cnt++) { |
c81d04c9 AV |
806 | if (cnt == 8) |
807 | dmp_reg = ®->u_end.isp2200.mailbox8; | |
808 | ||
a7a167bf | 809 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 LT |
810 | } |
811 | ||
c81d04c9 | 812 | dmp_reg = ®->u.isp2100.unused_2[0]; |
fa2a1ce5 | 813 | for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++) |
a7a167bf | 814 | fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 LT |
815 | |
816 | WRT_REG_WORD(®->ctrl_status, 0x00); | |
c81d04c9 | 817 | dmp_reg = ®->risc_hw; |
fa2a1ce5 | 818 | for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) |
a7a167bf | 819 | fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 820 | |
fa2a1ce5 | 821 | WRT_REG_WORD(®->pcr, 0x2000); |
c81d04c9 | 822 | qla2xxx_read_window(reg, 16, fw->risc_gp0_reg); |
1da177e4 | 823 | |
fa2a1ce5 | 824 | WRT_REG_WORD(®->pcr, 0x2100); |
c81d04c9 | 825 | qla2xxx_read_window(reg, 16, fw->risc_gp1_reg); |
1da177e4 | 826 | |
fa2a1ce5 | 827 | WRT_REG_WORD(®->pcr, 0x2200); |
c81d04c9 | 828 | qla2xxx_read_window(reg, 16, fw->risc_gp2_reg); |
1da177e4 | 829 | |
fa2a1ce5 | 830 | WRT_REG_WORD(®->pcr, 0x2300); |
c81d04c9 | 831 | qla2xxx_read_window(reg, 16, fw->risc_gp3_reg); |
1da177e4 | 832 | |
fa2a1ce5 | 833 | WRT_REG_WORD(®->pcr, 0x2400); |
c81d04c9 | 834 | qla2xxx_read_window(reg, 16, fw->risc_gp4_reg); |
1da177e4 | 835 | |
fa2a1ce5 | 836 | WRT_REG_WORD(®->pcr, 0x2500); |
c81d04c9 | 837 | qla2xxx_read_window(reg, 16, fw->risc_gp5_reg); |
1da177e4 | 838 | |
fa2a1ce5 | 839 | WRT_REG_WORD(®->pcr, 0x2600); |
c81d04c9 | 840 | qla2xxx_read_window(reg, 16, fw->risc_gp6_reg); |
1da177e4 | 841 | |
fa2a1ce5 | 842 | WRT_REG_WORD(®->pcr, 0x2700); |
c81d04c9 | 843 | qla2xxx_read_window(reg, 16, fw->risc_gp7_reg); |
1da177e4 | 844 | |
fa2a1ce5 | 845 | WRT_REG_WORD(®->ctrl_status, 0x10); |
c81d04c9 | 846 | qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg); |
1da177e4 | 847 | |
fa2a1ce5 | 848 | WRT_REG_WORD(®->ctrl_status, 0x20); |
c81d04c9 | 849 | qla2xxx_read_window(reg, 64, fw->fpm_b0_reg); |
1da177e4 | 850 | |
fa2a1ce5 | 851 | WRT_REG_WORD(®->ctrl_status, 0x30); |
c81d04c9 | 852 | qla2xxx_read_window(reg, 64, fw->fpm_b1_reg); |
1da177e4 LT |
853 | |
854 | /* Reset the ISP. */ | |
855 | WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); | |
856 | } | |
857 | ||
858 | for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && | |
859 | rval == QLA_SUCCESS; cnt--) { | |
860 | if (cnt) | |
861 | udelay(100); | |
862 | else | |
863 | rval = QLA_FUNCTION_TIMEOUT; | |
864 | } | |
865 | ||
866 | /* Pause RISC. */ | |
867 | if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) && | |
868 | (RD_REG_WORD(®->mctr) & (BIT_1 | BIT_0)) != 0))) { | |
869 | ||
fa2a1ce5 | 870 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); |
1da177e4 LT |
871 | for (cnt = 30000; |
872 | (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && | |
873 | rval == QLA_SUCCESS; cnt--) { | |
874 | if (cnt) | |
875 | udelay(100); | |
876 | else | |
877 | rval = QLA_FUNCTION_TIMEOUT; | |
878 | } | |
879 | if (rval == QLA_SUCCESS) { | |
880 | /* Set memory configuration and timing. */ | |
881 | if (IS_QLA2100(ha)) | |
882 | WRT_REG_WORD(®->mctr, 0xf1); | |
883 | else | |
884 | WRT_REG_WORD(®->mctr, 0xf2); | |
885 | RD_REG_WORD(®->mctr); /* PCI Posting. */ | |
886 | ||
887 | /* Release RISC. */ | |
888 | WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); | |
889 | } | |
890 | } | |
891 | ||
892 | if (rval == QLA_SUCCESS) { | |
893 | /* Get RISC SRAM. */ | |
894 | risc_address = 0x1000; | |
895 | WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD); | |
896 | clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | |
897 | } | |
898 | for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS; | |
899 | cnt++, risc_address++) { | |
900 | WRT_MAILBOX_REG(ha, reg, 1, risc_address); | |
901 | WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); | |
902 | ||
903 | for (timer = 6000000; timer != 0; timer--) { | |
904 | /* Check for pending interrupts. */ | |
905 | if (RD_REG_WORD(®->istatus) & ISR_RISC_INT) { | |
906 | if (RD_REG_WORD(®->semaphore) & BIT_0) { | |
907 | set_bit(MBX_INTERRUPT, | |
908 | &ha->mbx_cmd_flags); | |
909 | ||
910 | mb0 = RD_MAILBOX_REG(ha, reg, 0); | |
911 | mb2 = RD_MAILBOX_REG(ha, reg, 2); | |
912 | ||
913 | WRT_REG_WORD(®->semaphore, 0); | |
914 | WRT_REG_WORD(®->hccr, | |
915 | HCCR_CLR_RISC_INT); | |
916 | RD_REG_WORD(®->hccr); | |
917 | break; | |
918 | } | |
919 | WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); | |
920 | RD_REG_WORD(®->hccr); | |
921 | } | |
922 | udelay(5); | |
923 | } | |
924 | ||
925 | if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { | |
926 | rval = mb0 & MBS_MASK; | |
a7a167bf | 927 | fw->risc_ram[cnt] = htons(mb2); |
1da177e4 LT |
928 | } else { |
929 | rval = QLA_FUNCTION_FAILED; | |
930 | } | |
931 | } | |
932 | ||
a7a167bf | 933 | if (rval == QLA_SUCCESS) |
73208dfd | 934 | qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]); |
a7a167bf | 935 | |
3420d36c | 936 | qla2xxx_dump_post_process(base_vha, rval); |
1da177e4 LT |
937 | |
938 | qla2100_fw_dump_failed: | |
939 | if (!hardware_locked) | |
940 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
941 | } | |
942 | ||
6d9b61ed | 943 | void |
7b867cf7 | 944 | qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
6d9b61ed AV |
945 | { |
946 | int rval; | |
c3a2f0df | 947 | uint32_t cnt; |
6d9b61ed | 948 | uint32_t risc_address; |
7b867cf7 | 949 | struct qla_hw_data *ha = vha->hw; |
6d9b61ed AV |
950 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
951 | uint32_t __iomem *dmp_reg; | |
952 | uint32_t *iter_reg; | |
953 | uint16_t __iomem *mbx_reg; | |
954 | unsigned long flags; | |
955 | struct qla24xx_fw_dump *fw; | |
956 | uint32_t ext_mem_cnt; | |
c3a2f0df | 957 | void *nxt; |
2d70c103 NB |
958 | void *nxt_chain; |
959 | uint32_t *last_chain = NULL; | |
73208dfd | 960 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
6d9b61ed | 961 | |
7ec0effd | 962 | if (IS_P3P_TYPE(ha)) |
a9083016 GM |
963 | return; |
964 | ||
6d9b61ed | 965 | risc_address = ext_mem_cnt = 0; |
6d9b61ed AV |
966 | flags = 0; |
967 | ||
968 | if (!hardware_locked) | |
969 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
970 | ||
d4e3e04d | 971 | if (!ha->fw_dump) { |
7c3df132 SK |
972 | ql_log(ql_log_warn, vha, 0xd006, |
973 | "No buffer available for dump.\n"); | |
6d9b61ed AV |
974 | goto qla24xx_fw_dump_failed; |
975 | } | |
976 | ||
977 | if (ha->fw_dumped) { | |
7c3df132 SK |
978 | ql_log(ql_log_warn, vha, 0xd007, |
979 | "Firmware has been previously dumped (%p) " | |
980 | "-- ignoring request.\n", | |
981 | ha->fw_dump); | |
6d9b61ed AV |
982 | goto qla24xx_fw_dump_failed; |
983 | } | |
a7a167bf AV |
984 | fw = &ha->fw_dump->isp.isp24; |
985 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
6d9b61ed | 986 | |
a7a167bf | 987 | fw->host_status = htonl(RD_REG_DWORD(®->host_status)); |
6d9b61ed AV |
988 | |
989 | /* Pause RISC. */ | |
c81d04c9 AV |
990 | rval = qla24xx_pause_risc(reg); |
991 | if (rval != QLA_SUCCESS) | |
992 | goto qla24xx_fw_dump_failed_0; | |
993 | ||
994 | /* Host interface registers. */ | |
995 | dmp_reg = ®->flash_addr; | |
996 | for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) | |
997 | fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); | |
998 | ||
999 | /* Disable interrupts. */ | |
1000 | WRT_REG_DWORD(®->ictrl, 0); | |
1001 | RD_REG_DWORD(®->ictrl); | |
1002 | ||
1003 | /* Shadow registers. */ | |
1004 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); | |
1005 | RD_REG_DWORD(®->iobase_addr); | |
1006 | WRT_REG_DWORD(®->iobase_select, 0xB0000000); | |
1007 | fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1008 | ||
1009 | WRT_REG_DWORD(®->iobase_select, 0xB0100000); | |
1010 | fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1011 | ||
1012 | WRT_REG_DWORD(®->iobase_select, 0xB0200000); | |
1013 | fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1014 | ||
1015 | WRT_REG_DWORD(®->iobase_select, 0xB0300000); | |
1016 | fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1017 | ||
1018 | WRT_REG_DWORD(®->iobase_select, 0xB0400000); | |
1019 | fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1020 | ||
1021 | WRT_REG_DWORD(®->iobase_select, 0xB0500000); | |
1022 | fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1023 | ||
1024 | WRT_REG_DWORD(®->iobase_select, 0xB0600000); | |
1025 | fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1026 | ||
1027 | /* Mailbox registers. */ | |
1028 | mbx_reg = ®->mailbox0; | |
1029 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) | |
1030 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); | |
1031 | ||
1032 | /* Transfer sequence registers. */ | |
1033 | iter_reg = fw->xseq_gp_reg; | |
1034 | iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); | |
1035 | iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); | |
1036 | iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); | |
1037 | iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); | |
1038 | iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); | |
1039 | iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); | |
1040 | iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); | |
1041 | qla24xx_read_window(reg, 0xBF70, 16, iter_reg); | |
1042 | ||
1043 | qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg); | |
1044 | qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); | |
1045 | ||
1046 | /* Receive sequence registers. */ | |
1047 | iter_reg = fw->rseq_gp_reg; | |
1048 | iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); | |
1049 | iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); | |
1050 | iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); | |
1051 | iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); | |
1052 | iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); | |
1053 | iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); | |
1054 | iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); | |
1055 | qla24xx_read_window(reg, 0xFF70, 16, iter_reg); | |
1056 | ||
1057 | qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg); | |
1058 | qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); | |
1059 | qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); | |
1060 | ||
1061 | /* Command DMA registers. */ | |
1062 | qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); | |
1063 | ||
1064 | /* Queues. */ | |
1065 | iter_reg = fw->req0_dma_reg; | |
1066 | iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); | |
1067 | dmp_reg = ®->iobase_q; | |
1068 | for (cnt = 0; cnt < 7; cnt++) | |
1069 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1070 | ||
1071 | iter_reg = fw->resp0_dma_reg; | |
1072 | iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); | |
1073 | dmp_reg = ®->iobase_q; | |
1074 | for (cnt = 0; cnt < 7; cnt++) | |
1075 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1076 | ||
1077 | iter_reg = fw->req1_dma_reg; | |
1078 | iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); | |
1079 | dmp_reg = ®->iobase_q; | |
1080 | for (cnt = 0; cnt < 7; cnt++) | |
1081 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1082 | ||
1083 | /* Transmit DMA registers. */ | |
1084 | iter_reg = fw->xmt0_dma_reg; | |
1085 | iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); | |
1086 | qla24xx_read_window(reg, 0x7610, 16, iter_reg); | |
1087 | ||
1088 | iter_reg = fw->xmt1_dma_reg; | |
1089 | iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); | |
1090 | qla24xx_read_window(reg, 0x7630, 16, iter_reg); | |
1091 | ||
1092 | iter_reg = fw->xmt2_dma_reg; | |
1093 | iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); | |
1094 | qla24xx_read_window(reg, 0x7650, 16, iter_reg); | |
1095 | ||
1096 | iter_reg = fw->xmt3_dma_reg; | |
1097 | iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); | |
1098 | qla24xx_read_window(reg, 0x7670, 16, iter_reg); | |
1099 | ||
1100 | iter_reg = fw->xmt4_dma_reg; | |
1101 | iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); | |
1102 | qla24xx_read_window(reg, 0x7690, 16, iter_reg); | |
1103 | ||
1104 | qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); | |
1105 | ||
1106 | /* Receive DMA registers. */ | |
1107 | iter_reg = fw->rcvt0_data_dma_reg; | |
1108 | iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); | |
1109 | qla24xx_read_window(reg, 0x7710, 16, iter_reg); | |
1110 | ||
1111 | iter_reg = fw->rcvt1_data_dma_reg; | |
1112 | iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); | |
1113 | qla24xx_read_window(reg, 0x7730, 16, iter_reg); | |
1114 | ||
1115 | /* RISC registers. */ | |
1116 | iter_reg = fw->risc_gp_reg; | |
1117 | iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); | |
1118 | iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); | |
1119 | iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); | |
1120 | iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); | |
1121 | iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); | |
1122 | iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); | |
1123 | iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); | |
1124 | qla24xx_read_window(reg, 0x0F70, 16, iter_reg); | |
1125 | ||
1126 | /* Local memory controller registers. */ | |
1127 | iter_reg = fw->lmc_reg; | |
1128 | iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); | |
1129 | iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); | |
1130 | iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); | |
1131 | iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); | |
1132 | iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); | |
1133 | iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); | |
1134 | qla24xx_read_window(reg, 0x3060, 16, iter_reg); | |
1135 | ||
1136 | /* Fibre Protocol Module registers. */ | |
1137 | iter_reg = fw->fpm_hdw_reg; | |
1138 | iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); | |
1139 | iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); | |
1140 | iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); | |
1141 | iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); | |
1142 | iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); | |
1143 | iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); | |
1144 | iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); | |
1145 | iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); | |
1146 | iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); | |
1147 | iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); | |
1148 | iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); | |
1149 | qla24xx_read_window(reg, 0x40B0, 16, iter_reg); | |
1150 | ||
1151 | /* Frame Buffer registers. */ | |
1152 | iter_reg = fw->fb_hdw_reg; | |
1153 | iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); | |
1154 | iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); | |
1155 | iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); | |
1156 | iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); | |
1157 | iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); | |
1158 | iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); | |
1159 | iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); | |
1160 | iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); | |
1161 | iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); | |
1162 | iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); | |
1163 | qla24xx_read_window(reg, 0x61B0, 16, iter_reg); | |
1164 | ||
1165 | rval = qla24xx_soft_reset(ha); | |
1166 | if (rval != QLA_SUCCESS) | |
1167 | goto qla24xx_fw_dump_failed_0; | |
1168 | ||
1169 | rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), | |
c5722708 | 1170 | &nxt); |
c81d04c9 AV |
1171 | if (rval != QLA_SUCCESS) |
1172 | goto qla24xx_fw_dump_failed_0; | |
1173 | ||
73208dfd | 1174 | nxt = qla2xxx_copy_queues(ha, nxt); |
bb99de67 AV |
1175 | |
1176 | qla24xx_copy_eft(ha, nxt); | |
c81d04c9 | 1177 | |
2d70c103 NB |
1178 | nxt_chain = (void *)ha->fw_dump + ha->chain_offset; |
1179 | nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain); | |
1180 | if (last_chain) { | |
1181 | ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT); | |
1182 | *last_chain |= __constant_htonl(DUMP_CHAIN_LAST); | |
1183 | } | |
1184 | ||
1185 | /* Adjust valid length. */ | |
1186 | ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); | |
1187 | ||
c81d04c9 | 1188 | qla24xx_fw_dump_failed_0: |
3420d36c | 1189 | qla2xxx_dump_post_process(base_vha, rval); |
6d9b61ed | 1190 | |
c3a2f0df AV |
1191 | qla24xx_fw_dump_failed: |
1192 | if (!hardware_locked) | |
1193 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1194 | } | |
6d9b61ed | 1195 | |
c3a2f0df | 1196 | void |
7b867cf7 | 1197 | qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
c3a2f0df AV |
1198 | { |
1199 | int rval; | |
1200 | uint32_t cnt; | |
1201 | uint32_t risc_address; | |
7b867cf7 | 1202 | struct qla_hw_data *ha = vha->hw; |
c3a2f0df AV |
1203 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
1204 | uint32_t __iomem *dmp_reg; | |
1205 | uint32_t *iter_reg; | |
1206 | uint16_t __iomem *mbx_reg; | |
1207 | unsigned long flags; | |
1208 | struct qla25xx_fw_dump *fw; | |
1209 | uint32_t ext_mem_cnt; | |
d63ab533 | 1210 | void *nxt, *nxt_chain; |
bb99de67 | 1211 | uint32_t *last_chain = NULL; |
73208dfd | 1212 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
6d9b61ed | 1213 | |
c3a2f0df AV |
1214 | risc_address = ext_mem_cnt = 0; |
1215 | flags = 0; | |
6d9b61ed | 1216 | |
c3a2f0df AV |
1217 | if (!hardware_locked) |
1218 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
6d9b61ed | 1219 | |
c3a2f0df | 1220 | if (!ha->fw_dump) { |
7c3df132 SK |
1221 | ql_log(ql_log_warn, vha, 0xd008, |
1222 | "No buffer available for dump.\n"); | |
c3a2f0df AV |
1223 | goto qla25xx_fw_dump_failed; |
1224 | } | |
6d9b61ed | 1225 | |
c3a2f0df | 1226 | if (ha->fw_dumped) { |
7c3df132 SK |
1227 | ql_log(ql_log_warn, vha, 0xd009, |
1228 | "Firmware has been previously dumped (%p) " | |
1229 | "-- ignoring request.\n", | |
1230 | ha->fw_dump); | |
c3a2f0df AV |
1231 | goto qla25xx_fw_dump_failed; |
1232 | } | |
1233 | fw = &ha->fw_dump->isp.isp25; | |
1234 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
b5836927 | 1235 | ha->fw_dump->version = __constant_htonl(2); |
6d9b61ed | 1236 | |
c3a2f0df | 1237 | fw->host_status = htonl(RD_REG_DWORD(®->host_status)); |
6d9b61ed | 1238 | |
c3a2f0df | 1239 | /* Pause RISC. */ |
c81d04c9 AV |
1240 | rval = qla24xx_pause_risc(reg); |
1241 | if (rval != QLA_SUCCESS) | |
1242 | goto qla25xx_fw_dump_failed_0; | |
1243 | ||
b5836927 AV |
1244 | /* Host/Risc registers. */ |
1245 | iter_reg = fw->host_risc_reg; | |
1246 | iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); | |
1247 | qla24xx_read_window(reg, 0x7010, 16, iter_reg); | |
1248 | ||
1249 | /* PCIe registers. */ | |
1250 | WRT_REG_DWORD(®->iobase_addr, 0x7C00); | |
1251 | RD_REG_DWORD(®->iobase_addr); | |
1252 | WRT_REG_DWORD(®->iobase_window, 0x01); | |
1253 | dmp_reg = ®->iobase_c4; | |
1254 | fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1255 | fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1256 | fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); | |
1257 | fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); | |
73208dfd | 1258 | |
b5836927 AV |
1259 | WRT_REG_DWORD(®->iobase_window, 0x00); |
1260 | RD_REG_DWORD(®->iobase_window); | |
1261 | ||
c81d04c9 AV |
1262 | /* Host interface registers. */ |
1263 | dmp_reg = ®->flash_addr; | |
1264 | for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) | |
1265 | fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1266 | ||
1267 | /* Disable interrupts. */ | |
1268 | WRT_REG_DWORD(®->ictrl, 0); | |
1269 | RD_REG_DWORD(®->ictrl); | |
1270 | ||
1271 | /* Shadow registers. */ | |
1272 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); | |
1273 | RD_REG_DWORD(®->iobase_addr); | |
1274 | WRT_REG_DWORD(®->iobase_select, 0xB0000000); | |
1275 | fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1276 | ||
1277 | WRT_REG_DWORD(®->iobase_select, 0xB0100000); | |
1278 | fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1279 | ||
1280 | WRT_REG_DWORD(®->iobase_select, 0xB0200000); | |
1281 | fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1282 | ||
1283 | WRT_REG_DWORD(®->iobase_select, 0xB0300000); | |
1284 | fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1285 | ||
1286 | WRT_REG_DWORD(®->iobase_select, 0xB0400000); | |
1287 | fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1288 | ||
1289 | WRT_REG_DWORD(®->iobase_select, 0xB0500000); | |
1290 | fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1291 | ||
1292 | WRT_REG_DWORD(®->iobase_select, 0xB0600000); | |
1293 | fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1294 | ||
1295 | WRT_REG_DWORD(®->iobase_select, 0xB0700000); | |
1296 | fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1297 | ||
1298 | WRT_REG_DWORD(®->iobase_select, 0xB0800000); | |
1299 | fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1300 | ||
1301 | WRT_REG_DWORD(®->iobase_select, 0xB0900000); | |
1302 | fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1303 | ||
1304 | WRT_REG_DWORD(®->iobase_select, 0xB0A00000); | |
1305 | fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1306 | ||
1307 | /* RISC I/O register. */ | |
1308 | WRT_REG_DWORD(®->iobase_addr, 0x0010); | |
1309 | fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); | |
1310 | ||
1311 | /* Mailbox registers. */ | |
1312 | mbx_reg = ®->mailbox0; | |
1313 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) | |
1314 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); | |
1315 | ||
1316 | /* Transfer sequence registers. */ | |
1317 | iter_reg = fw->xseq_gp_reg; | |
1318 | iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); | |
1319 | iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); | |
1320 | iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); | |
1321 | iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); | |
1322 | iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); | |
1323 | iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); | |
1324 | iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); | |
1325 | qla24xx_read_window(reg, 0xBF70, 16, iter_reg); | |
1326 | ||
1327 | iter_reg = fw->xseq_0_reg; | |
1328 | iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); | |
1329 | iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); | |
1330 | qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); | |
1331 | ||
1332 | qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); | |
1333 | ||
1334 | /* Receive sequence registers. */ | |
1335 | iter_reg = fw->rseq_gp_reg; | |
1336 | iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); | |
1337 | iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); | |
1338 | iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); | |
1339 | iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); | |
1340 | iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); | |
1341 | iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); | |
1342 | iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); | |
1343 | qla24xx_read_window(reg, 0xFF70, 16, iter_reg); | |
1344 | ||
1345 | iter_reg = fw->rseq_0_reg; | |
1346 | iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); | |
1347 | qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); | |
1348 | ||
1349 | qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); | |
1350 | qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); | |
1351 | ||
1352 | /* Auxiliary sequence registers. */ | |
1353 | iter_reg = fw->aseq_gp_reg; | |
1354 | iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); | |
1355 | iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); | |
1356 | iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); | |
1357 | iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); | |
1358 | iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); | |
1359 | iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); | |
1360 | iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); | |
1361 | qla24xx_read_window(reg, 0xB070, 16, iter_reg); | |
1362 | ||
1363 | iter_reg = fw->aseq_0_reg; | |
1364 | iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); | |
1365 | qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); | |
1366 | ||
1367 | qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); | |
1368 | qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); | |
1369 | ||
1370 | /* Command DMA registers. */ | |
1371 | qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); | |
1372 | ||
1373 | /* Queues. */ | |
1374 | iter_reg = fw->req0_dma_reg; | |
1375 | iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); | |
1376 | dmp_reg = ®->iobase_q; | |
1377 | for (cnt = 0; cnt < 7; cnt++) | |
1378 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1379 | ||
1380 | iter_reg = fw->resp0_dma_reg; | |
1381 | iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); | |
1382 | dmp_reg = ®->iobase_q; | |
1383 | for (cnt = 0; cnt < 7; cnt++) | |
1384 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1385 | ||
1386 | iter_reg = fw->req1_dma_reg; | |
1387 | iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); | |
1388 | dmp_reg = ®->iobase_q; | |
1389 | for (cnt = 0; cnt < 7; cnt++) | |
1390 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1391 | ||
1392 | /* Transmit DMA registers. */ | |
1393 | iter_reg = fw->xmt0_dma_reg; | |
1394 | iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); | |
1395 | qla24xx_read_window(reg, 0x7610, 16, iter_reg); | |
1396 | ||
1397 | iter_reg = fw->xmt1_dma_reg; | |
1398 | iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); | |
1399 | qla24xx_read_window(reg, 0x7630, 16, iter_reg); | |
1400 | ||
1401 | iter_reg = fw->xmt2_dma_reg; | |
1402 | iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); | |
1403 | qla24xx_read_window(reg, 0x7650, 16, iter_reg); | |
1404 | ||
1405 | iter_reg = fw->xmt3_dma_reg; | |
1406 | iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); | |
1407 | qla24xx_read_window(reg, 0x7670, 16, iter_reg); | |
1408 | ||
1409 | iter_reg = fw->xmt4_dma_reg; | |
1410 | iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); | |
1411 | qla24xx_read_window(reg, 0x7690, 16, iter_reg); | |
1412 | ||
1413 | qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); | |
1414 | ||
1415 | /* Receive DMA registers. */ | |
1416 | iter_reg = fw->rcvt0_data_dma_reg; | |
1417 | iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); | |
1418 | qla24xx_read_window(reg, 0x7710, 16, iter_reg); | |
1419 | ||
1420 | iter_reg = fw->rcvt1_data_dma_reg; | |
1421 | iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); | |
1422 | qla24xx_read_window(reg, 0x7730, 16, iter_reg); | |
1423 | ||
1424 | /* RISC registers. */ | |
1425 | iter_reg = fw->risc_gp_reg; | |
1426 | iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); | |
1427 | iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); | |
1428 | iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); | |
1429 | iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); | |
1430 | iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); | |
1431 | iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); | |
1432 | iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); | |
1433 | qla24xx_read_window(reg, 0x0F70, 16, iter_reg); | |
1434 | ||
1435 | /* Local memory controller registers. */ | |
1436 | iter_reg = fw->lmc_reg; | |
1437 | iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); | |
1438 | iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); | |
1439 | iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); | |
1440 | iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); | |
1441 | iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); | |
1442 | iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); | |
1443 | iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); | |
1444 | qla24xx_read_window(reg, 0x3070, 16, iter_reg); | |
1445 | ||
1446 | /* Fibre Protocol Module registers. */ | |
1447 | iter_reg = fw->fpm_hdw_reg; | |
1448 | iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); | |
1449 | iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); | |
1450 | iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); | |
1451 | iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); | |
1452 | iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); | |
1453 | iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); | |
1454 | iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); | |
1455 | iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); | |
1456 | iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); | |
1457 | iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); | |
1458 | iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); | |
1459 | qla24xx_read_window(reg, 0x40B0, 16, iter_reg); | |
1460 | ||
1461 | /* Frame Buffer registers. */ | |
1462 | iter_reg = fw->fb_hdw_reg; | |
1463 | iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); | |
1464 | iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); | |
1465 | iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); | |
1466 | iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); | |
1467 | iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); | |
1468 | iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); | |
1469 | iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); | |
1470 | iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); | |
1471 | iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); | |
1472 | iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); | |
1473 | iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); | |
1474 | qla24xx_read_window(reg, 0x6F00, 16, iter_reg); | |
1475 | ||
d63ab533 AV |
1476 | /* Multi queue registers */ |
1477 | nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, | |
1478 | &last_chain); | |
1479 | ||
c81d04c9 AV |
1480 | rval = qla24xx_soft_reset(ha); |
1481 | if (rval != QLA_SUCCESS) | |
1482 | goto qla25xx_fw_dump_failed_0; | |
1483 | ||
1484 | rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), | |
c5722708 | 1485 | &nxt); |
c81d04c9 AV |
1486 | if (rval != QLA_SUCCESS) |
1487 | goto qla25xx_fw_dump_failed_0; | |
1488 | ||
73208dfd | 1489 | nxt = qla2xxx_copy_queues(ha, nxt); |
c81d04c9 | 1490 | |
7f544d00 | 1491 | qla24xx_copy_eft(ha, nxt); |
df613b96 | 1492 | |
d63ab533 | 1493 | /* Chain entries -- started with MQ. */ |
050c9bb1 GM |
1494 | nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain); |
1495 | nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain); | |
2d70c103 | 1496 | nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain); |
bb99de67 AV |
1497 | if (last_chain) { |
1498 | ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT); | |
1499 | *last_chain |= __constant_htonl(DUMP_CHAIN_LAST); | |
1500 | } | |
df613b96 | 1501 | |
050c9bb1 GM |
1502 | /* Adjust valid length. */ |
1503 | ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); | |
1504 | ||
c81d04c9 | 1505 | qla25xx_fw_dump_failed_0: |
3420d36c | 1506 | qla2xxx_dump_post_process(base_vha, rval); |
6d9b61ed | 1507 | |
c3a2f0df | 1508 | qla25xx_fw_dump_failed: |
6d9b61ed AV |
1509 | if (!hardware_locked) |
1510 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1511 | } | |
3a03eb79 AV |
1512 | |
1513 | void | |
1514 | qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) | |
1515 | { | |
1516 | int rval; | |
1517 | uint32_t cnt; | |
1518 | uint32_t risc_address; | |
1519 | struct qla_hw_data *ha = vha->hw; | |
1520 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
1521 | uint32_t __iomem *dmp_reg; | |
1522 | uint32_t *iter_reg; | |
1523 | uint16_t __iomem *mbx_reg; | |
1524 | unsigned long flags; | |
1525 | struct qla81xx_fw_dump *fw; | |
1526 | uint32_t ext_mem_cnt; | |
1527 | void *nxt, *nxt_chain; | |
1528 | uint32_t *last_chain = NULL; | |
1529 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); | |
1530 | ||
1531 | risc_address = ext_mem_cnt = 0; | |
1532 | flags = 0; | |
1533 | ||
1534 | if (!hardware_locked) | |
1535 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1536 | ||
1537 | if (!ha->fw_dump) { | |
7c3df132 SK |
1538 | ql_log(ql_log_warn, vha, 0xd00a, |
1539 | "No buffer available for dump.\n"); | |
3a03eb79 AV |
1540 | goto qla81xx_fw_dump_failed; |
1541 | } | |
1542 | ||
1543 | if (ha->fw_dumped) { | |
7c3df132 SK |
1544 | ql_log(ql_log_warn, vha, 0xd00b, |
1545 | "Firmware has been previously dumped (%p) " | |
1546 | "-- ignoring request.\n", | |
1547 | ha->fw_dump); | |
3a03eb79 AV |
1548 | goto qla81xx_fw_dump_failed; |
1549 | } | |
1550 | fw = &ha->fw_dump->isp.isp81; | |
1551 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
1552 | ||
1553 | fw->host_status = htonl(RD_REG_DWORD(®->host_status)); | |
1554 | ||
1555 | /* Pause RISC. */ | |
1556 | rval = qla24xx_pause_risc(reg); | |
1557 | if (rval != QLA_SUCCESS) | |
1558 | goto qla81xx_fw_dump_failed_0; | |
1559 | ||
1560 | /* Host/Risc registers. */ | |
1561 | iter_reg = fw->host_risc_reg; | |
1562 | iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); | |
1563 | qla24xx_read_window(reg, 0x7010, 16, iter_reg); | |
1564 | ||
1565 | /* PCIe registers. */ | |
1566 | WRT_REG_DWORD(®->iobase_addr, 0x7C00); | |
1567 | RD_REG_DWORD(®->iobase_addr); | |
1568 | WRT_REG_DWORD(®->iobase_window, 0x01); | |
1569 | dmp_reg = ®->iobase_c4; | |
1570 | fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1571 | fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1572 | fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); | |
1573 | fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); | |
1574 | ||
1575 | WRT_REG_DWORD(®->iobase_window, 0x00); | |
1576 | RD_REG_DWORD(®->iobase_window); | |
1577 | ||
1578 | /* Host interface registers. */ | |
1579 | dmp_reg = ®->flash_addr; | |
1580 | for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) | |
1581 | fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1582 | ||
1583 | /* Disable interrupts. */ | |
1584 | WRT_REG_DWORD(®->ictrl, 0); | |
1585 | RD_REG_DWORD(®->ictrl); | |
1586 | ||
1587 | /* Shadow registers. */ | |
1588 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); | |
1589 | RD_REG_DWORD(®->iobase_addr); | |
1590 | WRT_REG_DWORD(®->iobase_select, 0xB0000000); | |
1591 | fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1592 | ||
1593 | WRT_REG_DWORD(®->iobase_select, 0xB0100000); | |
1594 | fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1595 | ||
1596 | WRT_REG_DWORD(®->iobase_select, 0xB0200000); | |
1597 | fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1598 | ||
1599 | WRT_REG_DWORD(®->iobase_select, 0xB0300000); | |
1600 | fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1601 | ||
1602 | WRT_REG_DWORD(®->iobase_select, 0xB0400000); | |
1603 | fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1604 | ||
1605 | WRT_REG_DWORD(®->iobase_select, 0xB0500000); | |
1606 | fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1607 | ||
1608 | WRT_REG_DWORD(®->iobase_select, 0xB0600000); | |
1609 | fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1610 | ||
1611 | WRT_REG_DWORD(®->iobase_select, 0xB0700000); | |
1612 | fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1613 | ||
1614 | WRT_REG_DWORD(®->iobase_select, 0xB0800000); | |
1615 | fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1616 | ||
1617 | WRT_REG_DWORD(®->iobase_select, 0xB0900000); | |
1618 | fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1619 | ||
1620 | WRT_REG_DWORD(®->iobase_select, 0xB0A00000); | |
1621 | fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1622 | ||
1623 | /* RISC I/O register. */ | |
1624 | WRT_REG_DWORD(®->iobase_addr, 0x0010); | |
1625 | fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); | |
1626 | ||
1627 | /* Mailbox registers. */ | |
1628 | mbx_reg = ®->mailbox0; | |
1629 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) | |
1630 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); | |
1631 | ||
1632 | /* Transfer sequence registers. */ | |
1633 | iter_reg = fw->xseq_gp_reg; | |
1634 | iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); | |
1635 | iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); | |
1636 | iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); | |
1637 | iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); | |
1638 | iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); | |
1639 | iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); | |
1640 | iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); | |
1641 | qla24xx_read_window(reg, 0xBF70, 16, iter_reg); | |
1642 | ||
1643 | iter_reg = fw->xseq_0_reg; | |
1644 | iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); | |
1645 | iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); | |
1646 | qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); | |
1647 | ||
1648 | qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); | |
1649 | ||
1650 | /* Receive sequence registers. */ | |
1651 | iter_reg = fw->rseq_gp_reg; | |
1652 | iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); | |
1653 | iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); | |
1654 | iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); | |
1655 | iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); | |
1656 | iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); | |
1657 | iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); | |
1658 | iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); | |
1659 | qla24xx_read_window(reg, 0xFF70, 16, iter_reg); | |
1660 | ||
1661 | iter_reg = fw->rseq_0_reg; | |
1662 | iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); | |
1663 | qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); | |
1664 | ||
1665 | qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); | |
1666 | qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); | |
1667 | ||
1668 | /* Auxiliary sequence registers. */ | |
1669 | iter_reg = fw->aseq_gp_reg; | |
1670 | iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); | |
1671 | iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); | |
1672 | iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); | |
1673 | iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); | |
1674 | iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); | |
1675 | iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); | |
1676 | iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); | |
1677 | qla24xx_read_window(reg, 0xB070, 16, iter_reg); | |
1678 | ||
1679 | iter_reg = fw->aseq_0_reg; | |
1680 | iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); | |
1681 | qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); | |
1682 | ||
1683 | qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); | |
1684 | qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); | |
1685 | ||
1686 | /* Command DMA registers. */ | |
1687 | qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); | |
1688 | ||
1689 | /* Queues. */ | |
1690 | iter_reg = fw->req0_dma_reg; | |
1691 | iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); | |
1692 | dmp_reg = ®->iobase_q; | |
1693 | for (cnt = 0; cnt < 7; cnt++) | |
1694 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1695 | ||
1696 | iter_reg = fw->resp0_dma_reg; | |
1697 | iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); | |
1698 | dmp_reg = ®->iobase_q; | |
1699 | for (cnt = 0; cnt < 7; cnt++) | |
1700 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1701 | ||
1702 | iter_reg = fw->req1_dma_reg; | |
1703 | iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); | |
1704 | dmp_reg = ®->iobase_q; | |
1705 | for (cnt = 0; cnt < 7; cnt++) | |
1706 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1707 | ||
1708 | /* Transmit DMA registers. */ | |
1709 | iter_reg = fw->xmt0_dma_reg; | |
1710 | iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); | |
1711 | qla24xx_read_window(reg, 0x7610, 16, iter_reg); | |
1712 | ||
1713 | iter_reg = fw->xmt1_dma_reg; | |
1714 | iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); | |
1715 | qla24xx_read_window(reg, 0x7630, 16, iter_reg); | |
1716 | ||
1717 | iter_reg = fw->xmt2_dma_reg; | |
1718 | iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); | |
1719 | qla24xx_read_window(reg, 0x7650, 16, iter_reg); | |
1720 | ||
1721 | iter_reg = fw->xmt3_dma_reg; | |
1722 | iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); | |
1723 | qla24xx_read_window(reg, 0x7670, 16, iter_reg); | |
1724 | ||
1725 | iter_reg = fw->xmt4_dma_reg; | |
1726 | iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); | |
1727 | qla24xx_read_window(reg, 0x7690, 16, iter_reg); | |
1728 | ||
1729 | qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); | |
1730 | ||
1731 | /* Receive DMA registers. */ | |
1732 | iter_reg = fw->rcvt0_data_dma_reg; | |
1733 | iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); | |
1734 | qla24xx_read_window(reg, 0x7710, 16, iter_reg); | |
1735 | ||
1736 | iter_reg = fw->rcvt1_data_dma_reg; | |
1737 | iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); | |
1738 | qla24xx_read_window(reg, 0x7730, 16, iter_reg); | |
1739 | ||
1740 | /* RISC registers. */ | |
1741 | iter_reg = fw->risc_gp_reg; | |
1742 | iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); | |
1743 | iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); | |
1744 | iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); | |
1745 | iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); | |
1746 | iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); | |
1747 | iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); | |
1748 | iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); | |
1749 | qla24xx_read_window(reg, 0x0F70, 16, iter_reg); | |
1750 | ||
1751 | /* Local memory controller registers. */ | |
1752 | iter_reg = fw->lmc_reg; | |
1753 | iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); | |
1754 | iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); | |
1755 | iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); | |
1756 | iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); | |
1757 | iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); | |
1758 | iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); | |
1759 | iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); | |
1760 | qla24xx_read_window(reg, 0x3070, 16, iter_reg); | |
1761 | ||
1762 | /* Fibre Protocol Module registers. */ | |
1763 | iter_reg = fw->fpm_hdw_reg; | |
1764 | iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); | |
1765 | iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); | |
1766 | iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); | |
1767 | iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); | |
1768 | iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); | |
1769 | iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); | |
1770 | iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); | |
1771 | iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); | |
1772 | iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); | |
1773 | iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); | |
1774 | iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); | |
1775 | iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg); | |
1776 | iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg); | |
1777 | qla24xx_read_window(reg, 0x40D0, 16, iter_reg); | |
1778 | ||
1779 | /* Frame Buffer registers. */ | |
1780 | iter_reg = fw->fb_hdw_reg; | |
1781 | iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); | |
1782 | iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); | |
1783 | iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); | |
1784 | iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); | |
1785 | iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); | |
1786 | iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); | |
1787 | iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); | |
1788 | iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); | |
1789 | iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); | |
1790 | iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); | |
1791 | iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); | |
1792 | iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg); | |
1793 | qla24xx_read_window(reg, 0x6F00, 16, iter_reg); | |
1794 | ||
1795 | /* Multi queue registers */ | |
1796 | nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, | |
1797 | &last_chain); | |
1798 | ||
1799 | rval = qla24xx_soft_reset(ha); | |
1800 | if (rval != QLA_SUCCESS) | |
1801 | goto qla81xx_fw_dump_failed_0; | |
1802 | ||
1803 | rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), | |
1804 | &nxt); | |
1805 | if (rval != QLA_SUCCESS) | |
1806 | goto qla81xx_fw_dump_failed_0; | |
1807 | ||
1808 | nxt = qla2xxx_copy_queues(ha, nxt); | |
1809 | ||
7f544d00 | 1810 | qla24xx_copy_eft(ha, nxt); |
3a03eb79 AV |
1811 | |
1812 | /* Chain entries -- started with MQ. */ | |
050c9bb1 GM |
1813 | nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain); |
1814 | nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain); | |
2d70c103 | 1815 | nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain); |
3a03eb79 AV |
1816 | if (last_chain) { |
1817 | ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT); | |
1818 | *last_chain |= __constant_htonl(DUMP_CHAIN_LAST); | |
1819 | } | |
1820 | ||
050c9bb1 GM |
1821 | /* Adjust valid length. */ |
1822 | ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); | |
1823 | ||
3a03eb79 | 1824 | qla81xx_fw_dump_failed_0: |
3420d36c | 1825 | qla2xxx_dump_post_process(base_vha, rval); |
3a03eb79 AV |
1826 | |
1827 | qla81xx_fw_dump_failed: | |
1828 | if (!hardware_locked) | |
1829 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1830 | } | |
1831 | ||
6246b8a1 GM |
1832 | void |
1833 | qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) | |
1834 | { | |
1835 | int rval; | |
1836 | uint32_t cnt, reg_data; | |
1837 | uint32_t risc_address; | |
1838 | struct qla_hw_data *ha = vha->hw; | |
1839 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
1840 | uint32_t __iomem *dmp_reg; | |
1841 | uint32_t *iter_reg; | |
1842 | uint16_t __iomem *mbx_reg; | |
1843 | unsigned long flags; | |
1844 | struct qla83xx_fw_dump *fw; | |
1845 | uint32_t ext_mem_cnt; | |
1846 | void *nxt, *nxt_chain; | |
1847 | uint32_t *last_chain = NULL; | |
1848 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); | |
1849 | ||
1850 | risc_address = ext_mem_cnt = 0; | |
1851 | flags = 0; | |
1852 | ||
1853 | if (!hardware_locked) | |
1854 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1855 | ||
1856 | if (!ha->fw_dump) { | |
1857 | ql_log(ql_log_warn, vha, 0xd00c, | |
1858 | "No buffer available for dump!!!\n"); | |
1859 | goto qla83xx_fw_dump_failed; | |
1860 | } | |
1861 | ||
1862 | if (ha->fw_dumped) { | |
1863 | ql_log(ql_log_warn, vha, 0xd00d, | |
1864 | "Firmware has been previously dumped (%p) -- ignoring " | |
1865 | "request...\n", ha->fw_dump); | |
1866 | goto qla83xx_fw_dump_failed; | |
1867 | } | |
1868 | fw = &ha->fw_dump->isp.isp83; | |
1869 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
1870 | ||
1871 | fw->host_status = htonl(RD_REG_DWORD(®->host_status)); | |
1872 | ||
1873 | /* Pause RISC. */ | |
1874 | rval = qla24xx_pause_risc(reg); | |
1875 | if (rval != QLA_SUCCESS) | |
1876 | goto qla83xx_fw_dump_failed_0; | |
1877 | ||
1878 | WRT_REG_DWORD(®->iobase_addr, 0x6000); | |
1879 | dmp_reg = ®->iobase_window; | |
1880 | reg_data = RD_REG_DWORD(dmp_reg); | |
1881 | WRT_REG_DWORD(dmp_reg, 0); | |
1882 | ||
1883 | dmp_reg = ®->unused_4_1[0]; | |
1884 | reg_data = RD_REG_DWORD(dmp_reg); | |
1885 | WRT_REG_DWORD(dmp_reg, 0); | |
1886 | ||
1887 | WRT_REG_DWORD(®->iobase_addr, 0x6010); | |
1888 | dmp_reg = ®->unused_4_1[2]; | |
1889 | reg_data = RD_REG_DWORD(dmp_reg); | |
1890 | WRT_REG_DWORD(dmp_reg, 0); | |
1891 | ||
1892 | /* select PCR and disable ecc checking and correction */ | |
1893 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); | |
1894 | RD_REG_DWORD(®->iobase_addr); | |
1895 | WRT_REG_DWORD(®->iobase_select, 0x60000000); /* write to F0h = PCR */ | |
1896 | ||
1897 | /* Host/Risc registers. */ | |
1898 | iter_reg = fw->host_risc_reg; | |
1899 | iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); | |
1900 | iter_reg = qla24xx_read_window(reg, 0x7010, 16, iter_reg); | |
1901 | qla24xx_read_window(reg, 0x7040, 16, iter_reg); | |
1902 | ||
1903 | /* PCIe registers. */ | |
1904 | WRT_REG_DWORD(®->iobase_addr, 0x7C00); | |
1905 | RD_REG_DWORD(®->iobase_addr); | |
1906 | WRT_REG_DWORD(®->iobase_window, 0x01); | |
1907 | dmp_reg = ®->iobase_c4; | |
1908 | fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1909 | fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1910 | fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); | |
1911 | fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); | |
1912 | ||
1913 | WRT_REG_DWORD(®->iobase_window, 0x00); | |
1914 | RD_REG_DWORD(®->iobase_window); | |
1915 | ||
1916 | /* Host interface registers. */ | |
1917 | dmp_reg = ®->flash_addr; | |
1918 | for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) | |
1919 | fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1920 | ||
1921 | /* Disable interrupts. */ | |
1922 | WRT_REG_DWORD(®->ictrl, 0); | |
1923 | RD_REG_DWORD(®->ictrl); | |
1924 | ||
1925 | /* Shadow registers. */ | |
1926 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); | |
1927 | RD_REG_DWORD(®->iobase_addr); | |
1928 | WRT_REG_DWORD(®->iobase_select, 0xB0000000); | |
1929 | fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1930 | ||
1931 | WRT_REG_DWORD(®->iobase_select, 0xB0100000); | |
1932 | fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1933 | ||
1934 | WRT_REG_DWORD(®->iobase_select, 0xB0200000); | |
1935 | fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1936 | ||
1937 | WRT_REG_DWORD(®->iobase_select, 0xB0300000); | |
1938 | fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1939 | ||
1940 | WRT_REG_DWORD(®->iobase_select, 0xB0400000); | |
1941 | fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1942 | ||
1943 | WRT_REG_DWORD(®->iobase_select, 0xB0500000); | |
1944 | fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1945 | ||
1946 | WRT_REG_DWORD(®->iobase_select, 0xB0600000); | |
1947 | fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1948 | ||
1949 | WRT_REG_DWORD(®->iobase_select, 0xB0700000); | |
1950 | fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1951 | ||
1952 | WRT_REG_DWORD(®->iobase_select, 0xB0800000); | |
1953 | fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1954 | ||
1955 | WRT_REG_DWORD(®->iobase_select, 0xB0900000); | |
1956 | fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1957 | ||
1958 | WRT_REG_DWORD(®->iobase_select, 0xB0A00000); | |
1959 | fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1960 | ||
1961 | /* RISC I/O register. */ | |
1962 | WRT_REG_DWORD(®->iobase_addr, 0x0010); | |
1963 | fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); | |
1964 | ||
1965 | /* Mailbox registers. */ | |
1966 | mbx_reg = ®->mailbox0; | |
1967 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) | |
1968 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); | |
1969 | ||
1970 | /* Transfer sequence registers. */ | |
1971 | iter_reg = fw->xseq_gp_reg; | |
1972 | iter_reg = qla24xx_read_window(reg, 0xBE00, 16, iter_reg); | |
1973 | iter_reg = qla24xx_read_window(reg, 0xBE10, 16, iter_reg); | |
1974 | iter_reg = qla24xx_read_window(reg, 0xBE20, 16, iter_reg); | |
1975 | iter_reg = qla24xx_read_window(reg, 0xBE30, 16, iter_reg); | |
1976 | iter_reg = qla24xx_read_window(reg, 0xBE40, 16, iter_reg); | |
1977 | iter_reg = qla24xx_read_window(reg, 0xBE50, 16, iter_reg); | |
1978 | iter_reg = qla24xx_read_window(reg, 0xBE60, 16, iter_reg); | |
1979 | iter_reg = qla24xx_read_window(reg, 0xBE70, 16, iter_reg); | |
1980 | iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); | |
1981 | iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); | |
1982 | iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); | |
1983 | iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); | |
1984 | iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); | |
1985 | iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); | |
1986 | iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); | |
1987 | qla24xx_read_window(reg, 0xBF70, 16, iter_reg); | |
1988 | ||
1989 | iter_reg = fw->xseq_0_reg; | |
1990 | iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); | |
1991 | iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); | |
1992 | qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); | |
1993 | ||
1994 | qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); | |
1995 | ||
1996 | qla24xx_read_window(reg, 0xBEF0, 16, fw->xseq_2_reg); | |
1997 | ||
1998 | /* Receive sequence registers. */ | |
1999 | iter_reg = fw->rseq_gp_reg; | |
2000 | iter_reg = qla24xx_read_window(reg, 0xFE00, 16, iter_reg); | |
2001 | iter_reg = qla24xx_read_window(reg, 0xFE10, 16, iter_reg); | |
2002 | iter_reg = qla24xx_read_window(reg, 0xFE20, 16, iter_reg); | |
2003 | iter_reg = qla24xx_read_window(reg, 0xFE30, 16, iter_reg); | |
2004 | iter_reg = qla24xx_read_window(reg, 0xFE40, 16, iter_reg); | |
2005 | iter_reg = qla24xx_read_window(reg, 0xFE50, 16, iter_reg); | |
2006 | iter_reg = qla24xx_read_window(reg, 0xFE60, 16, iter_reg); | |
2007 | iter_reg = qla24xx_read_window(reg, 0xFE70, 16, iter_reg); | |
2008 | iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); | |
2009 | iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); | |
2010 | iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); | |
2011 | iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); | |
2012 | iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); | |
2013 | iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); | |
2014 | iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); | |
2015 | qla24xx_read_window(reg, 0xFF70, 16, iter_reg); | |
2016 | ||
2017 | iter_reg = fw->rseq_0_reg; | |
2018 | iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); | |
2019 | qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); | |
2020 | ||
2021 | qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); | |
2022 | qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); | |
2023 | qla24xx_read_window(reg, 0xFEF0, 16, fw->rseq_3_reg); | |
2024 | ||
2025 | /* Auxiliary sequence registers. */ | |
2026 | iter_reg = fw->aseq_gp_reg; | |
2027 | iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); | |
2028 | iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); | |
2029 | iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); | |
2030 | iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); | |
2031 | iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); | |
2032 | iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); | |
2033 | iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); | |
2034 | iter_reg = qla24xx_read_window(reg, 0xB070, 16, iter_reg); | |
2035 | iter_reg = qla24xx_read_window(reg, 0xB100, 16, iter_reg); | |
2036 | iter_reg = qla24xx_read_window(reg, 0xB110, 16, iter_reg); | |
2037 | iter_reg = qla24xx_read_window(reg, 0xB120, 16, iter_reg); | |
2038 | iter_reg = qla24xx_read_window(reg, 0xB130, 16, iter_reg); | |
2039 | iter_reg = qla24xx_read_window(reg, 0xB140, 16, iter_reg); | |
2040 | iter_reg = qla24xx_read_window(reg, 0xB150, 16, iter_reg); | |
2041 | iter_reg = qla24xx_read_window(reg, 0xB160, 16, iter_reg); | |
2042 | qla24xx_read_window(reg, 0xB170, 16, iter_reg); | |
2043 | ||
2044 | iter_reg = fw->aseq_0_reg; | |
2045 | iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); | |
2046 | qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); | |
2047 | ||
2048 | qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); | |
2049 | qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); | |
2050 | qla24xx_read_window(reg, 0xB1F0, 16, fw->aseq_3_reg); | |
2051 | ||
2052 | /* Command DMA registers. */ | |
2053 | iter_reg = fw->cmd_dma_reg; | |
2054 | iter_reg = qla24xx_read_window(reg, 0x7100, 16, iter_reg); | |
2055 | iter_reg = qla24xx_read_window(reg, 0x7120, 16, iter_reg); | |
2056 | iter_reg = qla24xx_read_window(reg, 0x7130, 16, iter_reg); | |
2057 | qla24xx_read_window(reg, 0x71F0, 16, iter_reg); | |
2058 | ||
2059 | /* Queues. */ | |
2060 | iter_reg = fw->req0_dma_reg; | |
2061 | iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); | |
2062 | dmp_reg = ®->iobase_q; | |
2063 | for (cnt = 0; cnt < 7; cnt++) | |
2064 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
2065 | ||
2066 | iter_reg = fw->resp0_dma_reg; | |
2067 | iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); | |
2068 | dmp_reg = ®->iobase_q; | |
2069 | for (cnt = 0; cnt < 7; cnt++) | |
2070 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
2071 | ||
2072 | iter_reg = fw->req1_dma_reg; | |
2073 | iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); | |
2074 | dmp_reg = ®->iobase_q; | |
2075 | for (cnt = 0; cnt < 7; cnt++) | |
2076 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
2077 | ||
2078 | /* Transmit DMA registers. */ | |
2079 | iter_reg = fw->xmt0_dma_reg; | |
2080 | iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); | |
2081 | qla24xx_read_window(reg, 0x7610, 16, iter_reg); | |
2082 | ||
2083 | iter_reg = fw->xmt1_dma_reg; | |
2084 | iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); | |
2085 | qla24xx_read_window(reg, 0x7630, 16, iter_reg); | |
2086 | ||
2087 | iter_reg = fw->xmt2_dma_reg; | |
2088 | iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); | |
2089 | qla24xx_read_window(reg, 0x7650, 16, iter_reg); | |
2090 | ||
2091 | iter_reg = fw->xmt3_dma_reg; | |
2092 | iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); | |
2093 | qla24xx_read_window(reg, 0x7670, 16, iter_reg); | |
2094 | ||
2095 | iter_reg = fw->xmt4_dma_reg; | |
2096 | iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); | |
2097 | qla24xx_read_window(reg, 0x7690, 16, iter_reg); | |
2098 | ||
2099 | qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); | |
2100 | ||
2101 | /* Receive DMA registers. */ | |
2102 | iter_reg = fw->rcvt0_data_dma_reg; | |
2103 | iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); | |
2104 | qla24xx_read_window(reg, 0x7710, 16, iter_reg); | |
2105 | ||
2106 | iter_reg = fw->rcvt1_data_dma_reg; | |
2107 | iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); | |
2108 | qla24xx_read_window(reg, 0x7730, 16, iter_reg); | |
2109 | ||
2110 | /* RISC registers. */ | |
2111 | iter_reg = fw->risc_gp_reg; | |
2112 | iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); | |
2113 | iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); | |
2114 | iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); | |
2115 | iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); | |
2116 | iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); | |
2117 | iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); | |
2118 | iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); | |
2119 | qla24xx_read_window(reg, 0x0F70, 16, iter_reg); | |
2120 | ||
2121 | /* Local memory controller registers. */ | |
2122 | iter_reg = fw->lmc_reg; | |
2123 | iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); | |
2124 | iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); | |
2125 | iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); | |
2126 | iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); | |
2127 | iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); | |
2128 | iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); | |
2129 | iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); | |
2130 | qla24xx_read_window(reg, 0x3070, 16, iter_reg); | |
2131 | ||
2132 | /* Fibre Protocol Module registers. */ | |
2133 | iter_reg = fw->fpm_hdw_reg; | |
2134 | iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); | |
2135 | iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); | |
2136 | iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); | |
2137 | iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); | |
2138 | iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); | |
2139 | iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); | |
2140 | iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); | |
2141 | iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); | |
2142 | iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); | |
2143 | iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); | |
2144 | iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); | |
2145 | iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg); | |
2146 | iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg); | |
2147 | iter_reg = qla24xx_read_window(reg, 0x40D0, 16, iter_reg); | |
2148 | iter_reg = qla24xx_read_window(reg, 0x40E0, 16, iter_reg); | |
2149 | qla24xx_read_window(reg, 0x40F0, 16, iter_reg); | |
2150 | ||
2151 | /* RQ0 Array registers. */ | |
2152 | iter_reg = fw->rq0_array_reg; | |
2153 | iter_reg = qla24xx_read_window(reg, 0x5C00, 16, iter_reg); | |
2154 | iter_reg = qla24xx_read_window(reg, 0x5C10, 16, iter_reg); | |
2155 | iter_reg = qla24xx_read_window(reg, 0x5C20, 16, iter_reg); | |
2156 | iter_reg = qla24xx_read_window(reg, 0x5C30, 16, iter_reg); | |
2157 | iter_reg = qla24xx_read_window(reg, 0x5C40, 16, iter_reg); | |
2158 | iter_reg = qla24xx_read_window(reg, 0x5C50, 16, iter_reg); | |
2159 | iter_reg = qla24xx_read_window(reg, 0x5C60, 16, iter_reg); | |
2160 | iter_reg = qla24xx_read_window(reg, 0x5C70, 16, iter_reg); | |
2161 | iter_reg = qla24xx_read_window(reg, 0x5C80, 16, iter_reg); | |
2162 | iter_reg = qla24xx_read_window(reg, 0x5C90, 16, iter_reg); | |
2163 | iter_reg = qla24xx_read_window(reg, 0x5CA0, 16, iter_reg); | |
2164 | iter_reg = qla24xx_read_window(reg, 0x5CB0, 16, iter_reg); | |
2165 | iter_reg = qla24xx_read_window(reg, 0x5CC0, 16, iter_reg); | |
2166 | iter_reg = qla24xx_read_window(reg, 0x5CD0, 16, iter_reg); | |
2167 | iter_reg = qla24xx_read_window(reg, 0x5CE0, 16, iter_reg); | |
2168 | qla24xx_read_window(reg, 0x5CF0, 16, iter_reg); | |
2169 | ||
2170 | /* RQ1 Array registers. */ | |
2171 | iter_reg = fw->rq1_array_reg; | |
2172 | iter_reg = qla24xx_read_window(reg, 0x5D00, 16, iter_reg); | |
2173 | iter_reg = qla24xx_read_window(reg, 0x5D10, 16, iter_reg); | |
2174 | iter_reg = qla24xx_read_window(reg, 0x5D20, 16, iter_reg); | |
2175 | iter_reg = qla24xx_read_window(reg, 0x5D30, 16, iter_reg); | |
2176 | iter_reg = qla24xx_read_window(reg, 0x5D40, 16, iter_reg); | |
2177 | iter_reg = qla24xx_read_window(reg, 0x5D50, 16, iter_reg); | |
2178 | iter_reg = qla24xx_read_window(reg, 0x5D60, 16, iter_reg); | |
2179 | iter_reg = qla24xx_read_window(reg, 0x5D70, 16, iter_reg); | |
2180 | iter_reg = qla24xx_read_window(reg, 0x5D80, 16, iter_reg); | |
2181 | iter_reg = qla24xx_read_window(reg, 0x5D90, 16, iter_reg); | |
2182 | iter_reg = qla24xx_read_window(reg, 0x5DA0, 16, iter_reg); | |
2183 | iter_reg = qla24xx_read_window(reg, 0x5DB0, 16, iter_reg); | |
2184 | iter_reg = qla24xx_read_window(reg, 0x5DC0, 16, iter_reg); | |
2185 | iter_reg = qla24xx_read_window(reg, 0x5DD0, 16, iter_reg); | |
2186 | iter_reg = qla24xx_read_window(reg, 0x5DE0, 16, iter_reg); | |
2187 | qla24xx_read_window(reg, 0x5DF0, 16, iter_reg); | |
2188 | ||
2189 | /* RP0 Array registers. */ | |
2190 | iter_reg = fw->rp0_array_reg; | |
2191 | iter_reg = qla24xx_read_window(reg, 0x5E00, 16, iter_reg); | |
2192 | iter_reg = qla24xx_read_window(reg, 0x5E10, 16, iter_reg); | |
2193 | iter_reg = qla24xx_read_window(reg, 0x5E20, 16, iter_reg); | |
2194 | iter_reg = qla24xx_read_window(reg, 0x5E30, 16, iter_reg); | |
2195 | iter_reg = qla24xx_read_window(reg, 0x5E40, 16, iter_reg); | |
2196 | iter_reg = qla24xx_read_window(reg, 0x5E50, 16, iter_reg); | |
2197 | iter_reg = qla24xx_read_window(reg, 0x5E60, 16, iter_reg); | |
2198 | iter_reg = qla24xx_read_window(reg, 0x5E70, 16, iter_reg); | |
2199 | iter_reg = qla24xx_read_window(reg, 0x5E80, 16, iter_reg); | |
2200 | iter_reg = qla24xx_read_window(reg, 0x5E90, 16, iter_reg); | |
2201 | iter_reg = qla24xx_read_window(reg, 0x5EA0, 16, iter_reg); | |
2202 | iter_reg = qla24xx_read_window(reg, 0x5EB0, 16, iter_reg); | |
2203 | iter_reg = qla24xx_read_window(reg, 0x5EC0, 16, iter_reg); | |
2204 | iter_reg = qla24xx_read_window(reg, 0x5ED0, 16, iter_reg); | |
2205 | iter_reg = qla24xx_read_window(reg, 0x5EE0, 16, iter_reg); | |
2206 | qla24xx_read_window(reg, 0x5EF0, 16, iter_reg); | |
2207 | ||
2208 | /* RP1 Array registers. */ | |
2209 | iter_reg = fw->rp1_array_reg; | |
2210 | iter_reg = qla24xx_read_window(reg, 0x5F00, 16, iter_reg); | |
2211 | iter_reg = qla24xx_read_window(reg, 0x5F10, 16, iter_reg); | |
2212 | iter_reg = qla24xx_read_window(reg, 0x5F20, 16, iter_reg); | |
2213 | iter_reg = qla24xx_read_window(reg, 0x5F30, 16, iter_reg); | |
2214 | iter_reg = qla24xx_read_window(reg, 0x5F40, 16, iter_reg); | |
2215 | iter_reg = qla24xx_read_window(reg, 0x5F50, 16, iter_reg); | |
2216 | iter_reg = qla24xx_read_window(reg, 0x5F60, 16, iter_reg); | |
2217 | iter_reg = qla24xx_read_window(reg, 0x5F70, 16, iter_reg); | |
2218 | iter_reg = qla24xx_read_window(reg, 0x5F80, 16, iter_reg); | |
2219 | iter_reg = qla24xx_read_window(reg, 0x5F90, 16, iter_reg); | |
2220 | iter_reg = qla24xx_read_window(reg, 0x5FA0, 16, iter_reg); | |
2221 | iter_reg = qla24xx_read_window(reg, 0x5FB0, 16, iter_reg); | |
2222 | iter_reg = qla24xx_read_window(reg, 0x5FC0, 16, iter_reg); | |
2223 | iter_reg = qla24xx_read_window(reg, 0x5FD0, 16, iter_reg); | |
2224 | iter_reg = qla24xx_read_window(reg, 0x5FE0, 16, iter_reg); | |
2225 | qla24xx_read_window(reg, 0x5FF0, 16, iter_reg); | |
2226 | ||
2227 | iter_reg = fw->at0_array_reg; | |
2228 | iter_reg = qla24xx_read_window(reg, 0x7080, 16, iter_reg); | |
2229 | iter_reg = qla24xx_read_window(reg, 0x7090, 16, iter_reg); | |
2230 | iter_reg = qla24xx_read_window(reg, 0x70A0, 16, iter_reg); | |
2231 | iter_reg = qla24xx_read_window(reg, 0x70B0, 16, iter_reg); | |
2232 | iter_reg = qla24xx_read_window(reg, 0x70C0, 16, iter_reg); | |
2233 | iter_reg = qla24xx_read_window(reg, 0x70D0, 16, iter_reg); | |
2234 | iter_reg = qla24xx_read_window(reg, 0x70E0, 16, iter_reg); | |
2235 | qla24xx_read_window(reg, 0x70F0, 16, iter_reg); | |
2236 | ||
2237 | /* I/O Queue Control registers. */ | |
2238 | qla24xx_read_window(reg, 0x7800, 16, fw->queue_control_reg); | |
2239 | ||
2240 | /* Frame Buffer registers. */ | |
2241 | iter_reg = fw->fb_hdw_reg; | |
2242 | iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); | |
2243 | iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); | |
2244 | iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); | |
2245 | iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); | |
2246 | iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); | |
2247 | iter_reg = qla24xx_read_window(reg, 0x6060, 16, iter_reg); | |
2248 | iter_reg = qla24xx_read_window(reg, 0x6070, 16, iter_reg); | |
2249 | iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); | |
2250 | iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); | |
2251 | iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); | |
2252 | iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); | |
2253 | iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); | |
2254 | iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); | |
2255 | iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg); | |
2256 | iter_reg = qla24xx_read_window(reg, 0x6530, 16, iter_reg); | |
2257 | iter_reg = qla24xx_read_window(reg, 0x6540, 16, iter_reg); | |
2258 | iter_reg = qla24xx_read_window(reg, 0x6550, 16, iter_reg); | |
2259 | iter_reg = qla24xx_read_window(reg, 0x6560, 16, iter_reg); | |
2260 | iter_reg = qla24xx_read_window(reg, 0x6570, 16, iter_reg); | |
2261 | iter_reg = qla24xx_read_window(reg, 0x6580, 16, iter_reg); | |
2262 | iter_reg = qla24xx_read_window(reg, 0x6590, 16, iter_reg); | |
2263 | iter_reg = qla24xx_read_window(reg, 0x65A0, 16, iter_reg); | |
2264 | iter_reg = qla24xx_read_window(reg, 0x65B0, 16, iter_reg); | |
2265 | iter_reg = qla24xx_read_window(reg, 0x65C0, 16, iter_reg); | |
2266 | iter_reg = qla24xx_read_window(reg, 0x65D0, 16, iter_reg); | |
2267 | iter_reg = qla24xx_read_window(reg, 0x65E0, 16, iter_reg); | |
2268 | qla24xx_read_window(reg, 0x6F00, 16, iter_reg); | |
2269 | ||
2270 | /* Multi queue registers */ | |
2271 | nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, | |
2272 | &last_chain); | |
2273 | ||
2274 | rval = qla24xx_soft_reset(ha); | |
2275 | if (rval != QLA_SUCCESS) { | |
2276 | ql_log(ql_log_warn, vha, 0xd00e, | |
2277 | "SOFT RESET FAILED, forcing continuation of dump!!!\n"); | |
2278 | rval = QLA_SUCCESS; | |
2279 | ||
2280 | ql_log(ql_log_warn, vha, 0xd00f, "try a bigger hammer!!!\n"); | |
2281 | ||
2282 | WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET); | |
2283 | RD_REG_DWORD(®->hccr); | |
2284 | ||
2285 | WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE); | |
2286 | RD_REG_DWORD(®->hccr); | |
2287 | ||
2288 | WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); | |
2289 | RD_REG_DWORD(®->hccr); | |
2290 | ||
2291 | for (cnt = 30000; cnt && (RD_REG_WORD(®->mailbox0)); cnt--) | |
2292 | udelay(5); | |
2293 | ||
2294 | if (!cnt) { | |
2295 | nxt = fw->code_ram; | |
8c0bc701 | 2296 | nxt += sizeof(fw->code_ram); |
6246b8a1 GM |
2297 | nxt += (ha->fw_memory_size - 0x100000 + 1); |
2298 | goto copy_queue; | |
2299 | } else | |
2300 | ql_log(ql_log_warn, vha, 0xd010, | |
2301 | "bigger hammer success?\n"); | |
2302 | } | |
2303 | ||
2304 | rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), | |
2305 | &nxt); | |
2306 | if (rval != QLA_SUCCESS) | |
2307 | goto qla83xx_fw_dump_failed_0; | |
2308 | ||
2309 | copy_queue: | |
2310 | nxt = qla2xxx_copy_queues(ha, nxt); | |
2311 | ||
7f544d00 | 2312 | qla24xx_copy_eft(ha, nxt); |
6246b8a1 GM |
2313 | |
2314 | /* Chain entries -- started with MQ. */ | |
2315 | nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain); | |
2316 | nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain); | |
2d70c103 | 2317 | nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain); |
6246b8a1 GM |
2318 | if (last_chain) { |
2319 | ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT); | |
2320 | *last_chain |= __constant_htonl(DUMP_CHAIN_LAST); | |
2321 | } | |
2322 | ||
2323 | /* Adjust valid length. */ | |
2324 | ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); | |
2325 | ||
2326 | qla83xx_fw_dump_failed_0: | |
2327 | qla2xxx_dump_post_process(base_vha, rval); | |
2328 | ||
2329 | qla83xx_fw_dump_failed: | |
2330 | if (!hardware_locked) | |
2331 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
2332 | } | |
2333 | ||
1da177e4 LT |
2334 | /****************************************************************************/ |
2335 | /* Driver Debug Functions. */ | |
2336 | /****************************************************************************/ | |
cfb0919c CD |
2337 | |
2338 | static inline int | |
2339 | ql_mask_match(uint32_t level) | |
2340 | { | |
2341 | if (ql2xextended_error_logging == 1) | |
2342 | ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; | |
2343 | return (level & ql2xextended_error_logging) == level; | |
2344 | } | |
2345 | ||
3ce8866c SK |
2346 | /* |
2347 | * This function is for formatting and logging debug information. | |
2348 | * It is to be used when vha is available. It formats the message | |
2349 | * and logs it to the messages file. | |
2350 | * parameters: | |
2351 | * level: The level of the debug messages to be printed. | |
2352 | * If ql2xextended_error_logging value is correctly set, | |
2353 | * this message will appear in the messages file. | |
2354 | * vha: Pointer to the scsi_qla_host_t. | |
2355 | * id: This is a unique identifier for the level. It identifies the | |
2356 | * part of the code from where the message originated. | |
2357 | * msg: The message to be displayed. | |
2358 | */ | |
2359 | void | |
086b3e8a JP |
2360 | ql_dbg(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...) |
2361 | { | |
2362 | va_list va; | |
2363 | struct va_format vaf; | |
3ce8866c | 2364 | |
cfb0919c | 2365 | if (!ql_mask_match(level)) |
086b3e8a | 2366 | return; |
3ce8866c | 2367 | |
086b3e8a | 2368 | va_start(va, fmt); |
3ce8866c | 2369 | |
086b3e8a JP |
2370 | vaf.fmt = fmt; |
2371 | vaf.va = &va; | |
3ce8866c | 2372 | |
086b3e8a JP |
2373 | if (vha != NULL) { |
2374 | const struct pci_dev *pdev = vha->hw->pdev; | |
2375 | /* <module-name> <pci-name> <msg-id>:<host> Message */ | |
2376 | pr_warn("%s [%s]-%04x:%ld: %pV", | |
2377 | QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, | |
2378 | vha->host_no, &vaf); | |
2379 | } else { | |
2380 | pr_warn("%s [%s]-%04x: : %pV", | |
2381 | QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf); | |
3ce8866c SK |
2382 | } |
2383 | ||
086b3e8a | 2384 | va_end(va); |
3ce8866c SK |
2385 | |
2386 | } | |
2387 | ||
2388 | /* | |
2389 | * This function is for formatting and logging debug information. | |
d6a03581 | 2390 | * It is to be used when vha is not available and pci is available, |
3ce8866c SK |
2391 | * i.e., before host allocation. It formats the message and logs it |
2392 | * to the messages file. | |
2393 | * parameters: | |
2394 | * level: The level of the debug messages to be printed. | |
2395 | * If ql2xextended_error_logging value is correctly set, | |
2396 | * this message will appear in the messages file. | |
2397 | * pdev: Pointer to the struct pci_dev. | |
2398 | * id: This is a unique id for the level. It identifies the part | |
2399 | * of the code from where the message originated. | |
2400 | * msg: The message to be displayed. | |
2401 | */ | |
2402 | void | |
086b3e8a JP |
2403 | ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id, |
2404 | const char *fmt, ...) | |
2405 | { | |
2406 | va_list va; | |
2407 | struct va_format vaf; | |
3ce8866c SK |
2408 | |
2409 | if (pdev == NULL) | |
2410 | return; | |
cfb0919c | 2411 | if (!ql_mask_match(level)) |
086b3e8a | 2412 | return; |
3ce8866c | 2413 | |
086b3e8a | 2414 | va_start(va, fmt); |
3ce8866c | 2415 | |
086b3e8a JP |
2416 | vaf.fmt = fmt; |
2417 | vaf.va = &va; | |
3ce8866c | 2418 | |
086b3e8a JP |
2419 | /* <module-name> <dev-name>:<msg-id> Message */ |
2420 | pr_warn("%s [%s]-%04x: : %pV", | |
2421 | QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, &vaf); | |
3ce8866c | 2422 | |
086b3e8a | 2423 | va_end(va); |
3ce8866c SK |
2424 | } |
2425 | ||
2426 | /* | |
2427 | * This function is for formatting and logging log messages. | |
2428 | * It is to be used when vha is available. It formats the message | |
2429 | * and logs it to the messages file. All the messages will be logged | |
2430 | * irrespective of value of ql2xextended_error_logging. | |
2431 | * parameters: | |
2432 | * level: The level of the log messages to be printed in the | |
2433 | * messages file. | |
2434 | * vha: Pointer to the scsi_qla_host_t | |
2435 | * id: This is a unique id for the level. It identifies the | |
2436 | * part of the code from where the message originated. | |
2437 | * msg: The message to be displayed. | |
2438 | */ | |
2439 | void | |
086b3e8a JP |
2440 | ql_log(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...) |
2441 | { | |
2442 | va_list va; | |
2443 | struct va_format vaf; | |
2444 | char pbuf[128]; | |
3ce8866c | 2445 | |
086b3e8a JP |
2446 | if (level > ql_errlev) |
2447 | return; | |
3ce8866c | 2448 | |
086b3e8a JP |
2449 | if (vha != NULL) { |
2450 | const struct pci_dev *pdev = vha->hw->pdev; | |
2451 | /* <module-name> <msg-id>:<host> Message */ | |
2452 | snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x:%ld: ", | |
2453 | QL_MSGHDR, dev_name(&(pdev->dev)), id, vha->host_no); | |
2454 | } else { | |
2455 | snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ", | |
2456 | QL_MSGHDR, "0000:00:00.0", id); | |
2457 | } | |
2458 | pbuf[sizeof(pbuf) - 1] = 0; | |
2459 | ||
2460 | va_start(va, fmt); | |
2461 | ||
2462 | vaf.fmt = fmt; | |
2463 | vaf.va = &va; | |
2464 | ||
2465 | switch (level) { | |
70a3fc76 | 2466 | case ql_log_fatal: /* FATAL LOG */ |
086b3e8a JP |
2467 | pr_crit("%s%pV", pbuf, &vaf); |
2468 | break; | |
70a3fc76 | 2469 | case ql_log_warn: |
086b3e8a JP |
2470 | pr_err("%s%pV", pbuf, &vaf); |
2471 | break; | |
70a3fc76 | 2472 | case ql_log_info: |
086b3e8a JP |
2473 | pr_warn("%s%pV", pbuf, &vaf); |
2474 | break; | |
2475 | default: | |
2476 | pr_info("%s%pV", pbuf, &vaf); | |
2477 | break; | |
3ce8866c SK |
2478 | } |
2479 | ||
086b3e8a | 2480 | va_end(va); |
3ce8866c SK |
2481 | } |
2482 | ||
2483 | /* | |
2484 | * This function is for formatting and logging log messages. | |
d6a03581 | 2485 | * It is to be used when vha is not available and pci is available, |
3ce8866c SK |
2486 | * i.e., before host allocation. It formats the message and logs |
2487 | * it to the messages file. All the messages are logged irrespective | |
2488 | * of the value of ql2xextended_error_logging. | |
2489 | * parameters: | |
2490 | * level: The level of the log messages to be printed in the | |
2491 | * messages file. | |
2492 | * pdev: Pointer to the struct pci_dev. | |
2493 | * id: This is a unique id for the level. It identifies the | |
2494 | * part of the code from where the message originated. | |
2495 | * msg: The message to be displayed. | |
2496 | */ | |
2497 | void | |
086b3e8a JP |
2498 | ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id, |
2499 | const char *fmt, ...) | |
2500 | { | |
2501 | va_list va; | |
2502 | struct va_format vaf; | |
2503 | char pbuf[128]; | |
3ce8866c SK |
2504 | |
2505 | if (pdev == NULL) | |
2506 | return; | |
086b3e8a JP |
2507 | if (level > ql_errlev) |
2508 | return; | |
3ce8866c | 2509 | |
086b3e8a JP |
2510 | /* <module-name> <dev-name>:<msg-id> Message */ |
2511 | snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ", | |
2512 | QL_MSGHDR, dev_name(&(pdev->dev)), id); | |
2513 | pbuf[sizeof(pbuf) - 1] = 0; | |
2514 | ||
2515 | va_start(va, fmt); | |
2516 | ||
2517 | vaf.fmt = fmt; | |
2518 | vaf.va = &va; | |
2519 | ||
2520 | switch (level) { | |
70a3fc76 | 2521 | case ql_log_fatal: /* FATAL LOG */ |
086b3e8a JP |
2522 | pr_crit("%s%pV", pbuf, &vaf); |
2523 | break; | |
70a3fc76 | 2524 | case ql_log_warn: |
086b3e8a JP |
2525 | pr_err("%s%pV", pbuf, &vaf); |
2526 | break; | |
70a3fc76 | 2527 | case ql_log_info: |
086b3e8a JP |
2528 | pr_warn("%s%pV", pbuf, &vaf); |
2529 | break; | |
2530 | default: | |
2531 | pr_info("%s%pV", pbuf, &vaf); | |
2532 | break; | |
3ce8866c SK |
2533 | } |
2534 | ||
086b3e8a | 2535 | va_end(va); |
3ce8866c SK |
2536 | } |
2537 | ||
2538 | void | |
2539 | ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id) | |
2540 | { | |
2541 | int i; | |
2542 | struct qla_hw_data *ha = vha->hw; | |
2543 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
2544 | struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; | |
2545 | struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82; | |
2546 | uint16_t __iomem *mbx_reg; | |
2547 | ||
cfb0919c CD |
2548 | if (!ql_mask_match(level)) |
2549 | return; | |
3ce8866c | 2550 | |
7ec0effd | 2551 | if (IS_P3P_TYPE(ha)) |
cfb0919c CD |
2552 | mbx_reg = ®82->mailbox_in[0]; |
2553 | else if (IS_FWI2_CAPABLE(ha)) | |
2554 | mbx_reg = ®24->mailbox0; | |
2555 | else | |
2556 | mbx_reg = MAILBOX_REG(ha, reg, 0); | |
2557 | ||
2558 | ql_dbg(level, vha, id, "Mailbox registers:\n"); | |
2559 | for (i = 0; i < 6; i++) | |
2560 | ql_dbg(level, vha, id, | |
2561 | "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++)); | |
3ce8866c SK |
2562 | } |
2563 | ||
2564 | ||
2565 | void | |
2566 | ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id, | |
2567 | uint8_t *b, uint32_t size) | |
2568 | { | |
2569 | uint32_t cnt; | |
2570 | uint8_t c; | |
cfb0919c CD |
2571 | |
2572 | if (!ql_mask_match(level)) | |
2573 | return; | |
2574 | ||
2575 | ql_dbg(level, vha, id, " 0 1 2 3 4 5 6 7 8 " | |
2576 | "9 Ah Bh Ch Dh Eh Fh\n"); | |
2577 | ql_dbg(level, vha, id, "----------------------------------" | |
2578 | "----------------------------\n"); | |
2579 | ||
2580 | ql_dbg(level, vha, id, " "); | |
2581 | for (cnt = 0; cnt < size;) { | |
2582 | c = *b++; | |
2583 | printk("%02x", (uint32_t) c); | |
2584 | cnt++; | |
2585 | if (!(cnt % 16)) | |
2586 | printk("\n"); | |
2587 | else | |
2588 | printk(" "); | |
3ce8866c | 2589 | } |
cfb0919c CD |
2590 | if (cnt % 16) |
2591 | ql_dbg(level, vha, id, "\n"); | |
3ce8866c | 2592 | } |