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qla2xxx: ABTS cause double free of qla_tgt_cmd +.
[deliverable/linux.git] / drivers / scsi / qla2xxx / qla_dbg.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4 6 */
3ce8866c
SK		 7
8/*
9 * Table for showing the current message id in use for particular level
10 * Change this table for addition of log/debug messages.
e02587d7
AE		 11 * ----------------------------------------------------------------------
12 * | Level | Last Value Used | Holes |
13 * ----------------------------------------------------------------------
f73cb695
CD		 14 * | Module Init and Probe | 0x017d | 0x004b,0x0141 |
15 * | | | 0x0144,0x0146 |
16 * | | | 0x015b-0x0160 |
17 * | | | 0x016e-0x0170 |
e8887c51 18 * | Mailbox commands | 0x118d | 0x1018-0x1019 |
f73cb695 19 * | | | 0x10ca |
6ddcfef7 20 * | | | 0x1115-0x1116 |
f73cb695
CD		 21 * | | | 0x111a-0x111b |
22 * | | | 0x1155-0x1158 |
8ae6d9c7 23 * | Device Discovery | 0x2095 | 0x2020-0x2022, |
6593d5bd 24 * | | | 0x2011-0x2012, |
2a8593f8 25 * | | | 0x2016 |
36008cf1 26 * | Queue Command and IO tracing | 0x3059 | 0x3006-0x300b |
9e522cd8 27 * | | | 0x3027-0x3028 |
8ae6d9c7
GM		 28 * | | | 0x303d-0x3041 |
29 * | | | 0x302d,0x3033 |
30 * | | | 0x3036,0x3038 |
31 * | | | 0x303a |
e8f5e95d 32 * | DPC Thread | 0x4023 | 0x4002,0x4013 |
454073c9 33 * | Async Events | 0x5087 | 0x502b-0x502f |
9ba56b95 34 * | | | 0x5047,0x5052 |
6ddcfef7 35 * | | | 0x5084,0x5075 |
a78951b2 36 * | | | 0x503d,0x5044 |
faef62d1 37 * | | | 0x507b |
71e56003 38 * | Timer Routines | 0x6012 | |
f73cb695
CD		 39 * | User Space Interactions | 0x70e2 | 0x7018,0x702e |
40 * | | | 0x7020,0x7024 |
41 * | | | 0x7039,0x7045 |
42 * | | | 0x7073-0x7075 |
43 * | | | 0x70a5-0x70a6 |
44 * | | | 0x70a8,0x70ab |
45 * | | | 0x70ad-0x70ae |
46 * | | | 0x70d7-0x70db |
47 * | | | 0x70de-0x70df |
5854771e 48 * | Task Management | 0x803d | 0x8025-0x8026 |
cfb0919c 49 * | | | 0x800b,0x8039 |
5f28d2d7 50 * | AER/EEH | 0x9011 | |
e02587d7 51 * | Virtual Port | 0xa007 | |
27f4b72f 52 * | ISP82XX Specific | 0xb157 | 0xb002,0xb024 |
7ec0effd 53 * | | | 0xb09e,0xb0ae |
a018d8ff 54 * | | | 0xb0c3,0xb0c6 |
7ec0effd
AD		 55 * | | | 0xb0e0-0xb0ef |
56 * | | | 0xb085,0xb0dc |
57 * | | | 0xb107,0xb108 |
58 * | | | 0xb111,0xb11e |
59 * | | | 0xb12c,0xb12d |
60 * | | | 0xb13a,0xb142 |
61 * | | | 0xb13c-0xb140 |
6ddcfef7 62 * | | | 0xb149 |
6246b8a1 63 * | MultiQ | 0xc00c | |
c0496401 64 * | Misc | 0xd212 | 0xd017-0xd019 |
f73cb695 65 * | | | 0xd020 |
c0496401 66 * | | | 0xd030-0xd0ff |
f73cb695 67 * | | | 0xd101-0xd1fe |
c0496401 68 * | | | 0xd213-0xd2fe |
f83adb61 69 * | Target Mode | 0xe078 | |
6ddcfef7
SK		 70 * | Target Mode Management | 0xf072 | 0xf002-0xf003 |
71 * | | | 0xf046-0xf049 |
2d70c103 72 * | Target Mode Task Management | 0x1000b | |
e02587d7 73 * ----------------------------------------------------------------------
3ce8866c
SK		 74 */
75
1da177e4
LT		 76#include "qla_def.h"
77
78#include <linux/delay.h>
79
3ce8866c
SK		 80static uint32_t ql_dbg_offset = 0x800;
81
a7a167bf 82static inline void
7b867cf7 83qla2xxx_prep_dump(struct qla_hw_data *ha, struct qla2xxx_fw_dump *fw_dump)
a7a167bf
AV		 84{
85 fw_dump->fw_major_version = htonl(ha->fw_major_version);
86 fw_dump->fw_minor_version = htonl(ha->fw_minor_version);
87 fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version);
88 fw_dump->fw_attributes = htonl(ha->fw_attributes);
89
90 fw_dump->vendor = htonl(ha->pdev->vendor);
91 fw_dump->device = htonl(ha->pdev->device);
92 fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor);
93 fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device);
94}
95
96static inline void *
73208dfd 97qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr)
a7a167bf 98{
73208dfd
AC		 99 struct req_que *req = ha->req_q_map[0];
100 struct rsp_que *rsp = ha->rsp_q_map[0];
a7a167bf 101 /* Request queue. */
7b867cf7 102 memcpy(ptr, req->ring, req->length *
a7a167bf
AV		 103 sizeof(request_t));
104
105 /* Response queue. */
7b867cf7
AC		 106 ptr += req->length * sizeof(request_t);
107 memcpy(ptr, rsp->ring, rsp->length *
a7a167bf
AV		 108 sizeof(response_t));
109
7b867cf7 110 return ptr + (rsp->length * sizeof(response_t));
a7a167bf 111}
1da177e4 112
f73cb695
CD		 113int
114qla27xx_dump_mpi_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram,
115 uint32_t ram_dwords, void **nxt)
116{
117 int rval;
118 uint32_t cnt, stat, timer, dwords, idx;
119 uint16_t mb0, mb1;
120 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
121 dma_addr_t dump_dma = ha->gid_list_dma;
122 uint32_t *dump = (uint32_t *)ha->gid_list;
123
124 rval = QLA_SUCCESS;
125 mb0 = 0;
126
127 WRT_REG_WORD(&reg->mailbox0, MBC_LOAD_DUMP_MPI_RAM);
128 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
129
130 dwords = qla2x00_gid_list_size(ha) / 4;
131 for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
132 cnt += dwords, addr += dwords) {
133 if (cnt + dwords > ram_dwords)
134 dwords = ram_dwords - cnt;
135
136 WRT_REG_WORD(&reg->mailbox1, LSW(addr));
137 WRT_REG_WORD(&reg->mailbox8, MSW(addr));
138
139 WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
140 WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
141 WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
142 WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
143
144 WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
145 WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
146
147 WRT_REG_WORD(&reg->mailbox9, 0);
148 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
149
150 ha->flags.mbox_int = 0;
151 for (timer = 6000000; timer; timer--) {
152 /* Check for pending interrupts. */
153 stat = RD_REG_DWORD(&reg->host_status);
154 if (stat & HSRX_RISC_INT) {
155 stat &= 0xff;
156
157 if (stat == 0x1 || stat == 0x2 ||
158 stat == 0x10 || stat == 0x11) {
159 set_bit(MBX_INTERRUPT,
160 &ha->mbx_cmd_flags);
161
162 mb0 = RD_REG_WORD(&reg->mailbox0);
163 mb1 = RD_REG_WORD(&reg->mailbox1);
164
165 WRT_REG_DWORD(&reg->hccr,
166 HCCRX_CLR_RISC_INT);
167 RD_REG_DWORD(&reg->hccr);
168 break;
169 }
170
171 /* Clear this intr; it wasn't a mailbox intr */
172 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
173 RD_REG_DWORD(&reg->hccr);
174 }
175 udelay(5);
176 }
177 ha->flags.mbox_int = 1;
178
179 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
180 rval = mb0 & MBS_MASK;
181 for (idx = 0; idx < dwords; idx++)
182 ram[cnt + idx] = IS_QLA27XX(ha) ?
183 le32_to_cpu(dump[idx]) : swab32(dump[idx]);
184 } else {
185 rval = QLA_FUNCTION_FAILED;
186 }
187 }
188
189 *nxt = rval == QLA_SUCCESS ? &ram[cnt] : NULL;
190 return rval;
191}
192
193int
7b867cf7 194qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram,
c5722708 195 uint32_t ram_dwords, void **nxt)
c3a2f0df
AV		 196{
197 int rval;
c5722708
AV		 198 uint32_t cnt, stat, timer, dwords, idx;
199 uint16_t mb0;
c3a2f0df 200 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
c5722708
AV		 201 dma_addr_t dump_dma = ha->gid_list_dma;
202 uint32_t *dump = (uint32_t *)ha->gid_list;
c3a2f0df
AV		 203
204 rval = QLA_SUCCESS;
c5722708 205 mb0 = 0;
c3a2f0df 206
c5722708 207 WRT_REG_WORD(&reg->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
c3a2f0df
AV		 208 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
209
642ef983 210 dwords = qla2x00_gid_list_size(ha) / 4;
c5722708
AV		 211 for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
212 cnt += dwords, addr += dwords) {
213 if (cnt + dwords > ram_dwords)
214 dwords = ram_dwords - cnt;
c3a2f0df 215
c5722708
AV		 216 WRT_REG_WORD(&reg->mailbox1, LSW(addr));
217 WRT_REG_WORD(&reg->mailbox8, MSW(addr));
c3a2f0df 218
c5722708
AV		 219 WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
220 WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
221 WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
222 WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
c3a2f0df 223
c5722708
AV		 224 WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
225 WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
c3a2f0df
AV		 226 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
227
f73cb695 228 ha->flags.mbox_int = 0;
c3a2f0df
AV		 229 for (timer = 6000000; timer; timer--) {
230 /* Check for pending interrupts. */
231 stat = RD_REG_DWORD(&reg->host_status);
232 if (stat & HSRX_RISC_INT) {
233 stat &= 0xff;
234
235 if (stat == 0x1 || stat == 0x2 ||
236 stat == 0x10 || stat == 0x11) {
237 set_bit(MBX_INTERRUPT,
238 &ha->mbx_cmd_flags);
239
c5722708 240 mb0 = RD_REG_WORD(&reg->mailbox0);
c3a2f0df
AV		 241
242 WRT_REG_DWORD(&reg->hccr,
243 HCCRX_CLR_RISC_INT);
244 RD_REG_DWORD(&reg->hccr);
245 break;
246 }
247
248 /* Clear this intr; it wasn't a mailbox intr */
249 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
250 RD_REG_DWORD(&reg->hccr);
251 }
252 udelay(5);
253 }
f73cb695 254 ha->flags.mbox_int = 1;
c3a2f0df
AV		 255
256 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
c5722708
AV		 257 rval = mb0 & MBS_MASK;
258 for (idx = 0; idx < dwords; idx++)
f73cb695
CD		 259 ram[cnt + idx] = IS_QLA27XX(ha) ?
260 le32_to_cpu(dump[idx]) : swab32(dump[idx]);
c3a2f0df
AV		 261 } else {
262 rval = QLA_FUNCTION_FAILED;
263 }
264 }
265
c5722708 266 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
c3a2f0df
AV		 267 return rval;
268}
269
c5722708 270static int
7b867cf7 271qla24xx_dump_memory(struct qla_hw_data *ha, uint32_t *code_ram,
c5722708
AV		 272 uint32_t cram_size, void **nxt)
273{
274 int rval;
275
276 /* Code RAM. */
277 rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt);
278 if (rval != QLA_SUCCESS)
279 return rval;
280
61f098dd
HP		 281 set_bit(RISC_SRAM_DUMP_CMPL, &ha->fw_dump_cap_flags);
282
c5722708 283 /* External Memory. */
61f098dd 284 rval = qla24xx_dump_ram(ha, 0x100000, *nxt,
c5722708 285 ha->fw_memory_size - 0x100000 + 1, nxt);
61f098dd
HP		 286 if (rval == QLA_SUCCESS)
287 set_bit(RISC_EXT_MEM_DUMP_CMPL, &ha->fw_dump_cap_flags);
288
289 return rval;
c5722708
AV		 290}
291
c81d04c9
AV		 292static uint32_t *
293qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
294 uint32_t count, uint32_t *buf)
295{
296 uint32_t __iomem *dmp_reg;
297
298 WRT_REG_DWORD(&reg->iobase_addr, iobase);
299 dmp_reg = &reg->iobase_window;
300 while (count--)
301 *buf++ = htonl(RD_REG_DWORD(dmp_reg++));
302
303 return buf;
304}
305
2f389fc4 306void
61f098dd 307qla24xx_pause_risc(struct device_reg_24xx __iomem *reg, struct qla_hw_data *ha)
c81d04c9 308{
c3b058af 309 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
c81d04c9 310
2f389fc4
HP		 311 /* 100 usec delay is sufficient enough for hardware to pause RISC */
312 udelay(100);
61f098dd
HP		 313 if (RD_REG_DWORD(&reg->host_status) & HSRX_RISC_PAUSED)
314 set_bit(RISC_PAUSE_CMPL, &ha->fw_dump_cap_flags);
c81d04c9
AV		 315}
316
f73cb695 317int
7b867cf7 318qla24xx_soft_reset(struct qla_hw_data *ha)
c81d04c9
AV		 319{
320 int rval = QLA_SUCCESS;
321 uint32_t cnt;
2f389fc4 322 uint16_t wd;
c81d04c9
AV		 323 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
324
2f389fc4
HP		 325 /*
326 * Reset RISC. The delay is dependent on system architecture.
327 * Driver can proceed with the reset sequence after waiting
328 * for a timeout period.
329 */
c81d04c9
AV		 330 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
331 for (cnt = 0; cnt < 30000; cnt++) {
332 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
333 break;
334
335 udelay(10);
336 }
61f098dd
HP		 337 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE))
338 set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags);
c81d04c9
AV		 339
340 WRT_REG_DWORD(&reg->ctrl_status,
341 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
342 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
343
344 udelay(100);
c81d04c9
AV		 345
346 /* Wait for soft-reset to complete. */
347 for (cnt = 0; cnt < 30000; cnt++) {
348 if ((RD_REG_DWORD(&reg->ctrl_status) &
349 CSRX_ISP_SOFT_RESET) == 0)
350 break;
351
352 udelay(10);
353 }
61f098dd
HP		 354 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))
355 set_bit(ISP_RESET_CMPL, &ha->fw_dump_cap_flags);
356
c81d04c9
AV		 357 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
358 RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
359
2f389fc4 360 for (cnt = 10000; RD_REG_WORD(&reg->mailbox0) != 0 &&
c81d04c9
AV		 361 rval == QLA_SUCCESS; cnt--) {
362 if (cnt)
2f389fc4 363 udelay(10);
c81d04c9
AV		 364 else
365 rval = QLA_FUNCTION_TIMEOUT;
366 }
61f098dd
HP		 367 if (rval == QLA_SUCCESS)
368 set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
c81d04c9
AV		 369
370 return rval;
371}
372
c5722708 373static int
7b867cf7 374qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint16_t *ram,
e18e963b 375 uint32_t ram_words, void **nxt)
c5722708
AV		 376{
377 int rval;
378 uint32_t cnt, stat, timer, words, idx;
379 uint16_t mb0;
380 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
381 dma_addr_t dump_dma = ha->gid_list_dma;
382 uint16_t *dump = (uint16_t *)ha->gid_list;
383
384 rval = QLA_SUCCESS;
385 mb0 = 0;
386
387 WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED);
388 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
389
642ef983 390 words = qla2x00_gid_list_size(ha) / 2;
c5722708
AV		 391 for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS;
392 cnt += words, addr += words) {
393 if (cnt + words > ram_words)
394 words = ram_words - cnt;
395
396 WRT_MAILBOX_REG(ha, reg, 1, LSW(addr));
397 WRT_MAILBOX_REG(ha, reg, 8, MSW(addr));
398
399 WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma));
400 WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma));
401 WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma)));
402 WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma)));
403
404 WRT_MAILBOX_REG(ha, reg, 4, words);
405 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
406
407 for (timer = 6000000; timer; timer--) {
408 /* Check for pending interrupts. */
409 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
410 if (stat & HSR_RISC_INT) {
411 stat &= 0xff;
412
413 if (stat == 0x1 || stat == 0x2) {
414 set_bit(MBX_INTERRUPT,
415 &ha->mbx_cmd_flags);
416
417 mb0 = RD_MAILBOX_REG(ha, reg, 0);
418
419 /* Release mailbox registers. */
420 WRT_REG_WORD(&reg->semaphore, 0);
421 WRT_REG_WORD(&reg->hccr,
422 HCCR_CLR_RISC_INT);
423 RD_REG_WORD(&reg->hccr);
424 break;
425 } else if (stat == 0x10 || stat == 0x11) {
426 set_bit(MBX_INTERRUPT,
427 &ha->mbx_cmd_flags);
428
429 mb0 = RD_MAILBOX_REG(ha, reg, 0);
430
431 WRT_REG_WORD(&reg->hccr,
432 HCCR_CLR_RISC_INT);
433 RD_REG_WORD(&reg->hccr);
434 break;
435 }
436
437 /* clear this intr; it wasn't a mailbox intr */
438 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
439 RD_REG_WORD(&reg->hccr);
440 }
441 udelay(5);
442 }
443
444 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
445 rval = mb0 & MBS_MASK;
446 for (idx = 0; idx < words; idx++)
447 ram[cnt + idx] = swab16(dump[idx]);
448 } else {
449 rval = QLA_FUNCTION_FAILED;
450 }
451 }
452
453 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
454 return rval;
455}
456
c81d04c9
AV		 457static inline void
458qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
459 uint16_t *buf)
460{
461 uint16_t __iomem *dmp_reg = &reg->u.isp2300.fb_cmd;
462
463 while (count--)
464 *buf++ = htons(RD_REG_WORD(dmp_reg++));
465}
466
bb99de67
AV		 467static inline void *
468qla24xx_copy_eft(struct qla_hw_data *ha, void *ptr)
469{
470 if (!ha->eft)
471 return ptr;
472
473 memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size));
474 return ptr + ntohl(ha->fw_dump->eft_size);
475}
476
477static inline void *
478qla25xx_copy_fce(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
479{
480 uint32_t cnt;
481 uint32_t *iter_reg;
482 struct qla2xxx_fce_chain *fcec = ptr;
483
484 if (!ha->fce)
485 return ptr;
486
487 *last_chain = &fcec->type;
488 fcec->type = __constant_htonl(DUMP_CHAIN_FCE);
489 fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) +
490 fce_calc_size(ha->fce_bufs));
491 fcec->size = htonl(fce_calc_size(ha->fce_bufs));
492 fcec->addr_l = htonl(LSD(ha->fce_dma));
493 fcec->addr_h = htonl(MSD(ha->fce_dma));
494
495 iter_reg = fcec->eregs;
496 for (cnt = 0; cnt < 8; cnt++)
497 *iter_reg++ = htonl(ha->fce_mb[cnt]);
498
499 memcpy(iter_reg, ha->fce, ntohl(fcec->size));
500
3cb0a67d 501 return (char *)iter_reg + ntohl(fcec->size);
bb99de67
AV		 502}
503
2d70c103
NB		 504static inline void *
505qla2xxx_copy_atioqueues(struct qla_hw_data *ha, void *ptr,
506 uint32_t **last_chain)
507{
508 struct qla2xxx_mqueue_chain *q;
509 struct qla2xxx_mqueue_header *qh;
510 uint32_t num_queues;
511 int que;
512 struct {
513 int length;
514 void *ring;
515 } aq, *aqp;
516
00876ae8 517 if (!ha->tgt.atio_ring)
2d70c103
NB		 518 return ptr;
519
520 num_queues = 1;
521 aqp = &aq;
522 aqp->length = ha->tgt.atio_q_length;
523 aqp->ring = ha->tgt.atio_ring;
524
525 for (que = 0; que < num_queues; que++) {
526 /* aqp = ha->atio_q_map[que]; */
527 q = ptr;
528 *last_chain = &q->type;
529 q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
530 q->chain_size = htonl(
531 sizeof(struct qla2xxx_mqueue_chain) +
532 sizeof(struct qla2xxx_mqueue_header) +
533 (aqp->length * sizeof(request_t)));
534 ptr += sizeof(struct qla2xxx_mqueue_chain);
535
536 /* Add header. */
537 qh = ptr;
538 qh->queue = __constant_htonl(TYPE_ATIO_QUEUE);
539 qh->number = htonl(que);
540 qh->size = htonl(aqp->length * sizeof(request_t));
541 ptr += sizeof(struct qla2xxx_mqueue_header);
542
543 /* Add data. */
544 memcpy(ptr, aqp->ring, aqp->length * sizeof(request_t));
545
546 ptr += aqp->length * sizeof(request_t);
547 }
548
549 return ptr;
550}
551
050c9bb1
GM		 552static inline void *
553qla25xx_copy_mqueues(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
554{
555 struct qla2xxx_mqueue_chain *q;
556 struct qla2xxx_mqueue_header *qh;
557 struct req_que *req;
558 struct rsp_que *rsp;
559 int que;
560
561 if (!ha->mqenable)
562 return ptr;
563
564 /* Request queues */
565 for (que = 1; que < ha->max_req_queues; que++) {
566 req = ha->req_q_map[que];
567 if (!req)
568 break;
569
570 /* Add chain. */
571 q = ptr;
572 *last_chain = &q->type;
573 q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
574 q->chain_size = htonl(
575 sizeof(struct qla2xxx_mqueue_chain) +
576 sizeof(struct qla2xxx_mqueue_header) +
577 (req->length * sizeof(request_t)));
578 ptr += sizeof(struct qla2xxx_mqueue_chain);
579
580 /* Add header. */
581 qh = ptr;
582 qh->queue = __constant_htonl(TYPE_REQUEST_QUEUE);
583 qh->number = htonl(que);
584 qh->size = htonl(req->length * sizeof(request_t));
585 ptr += sizeof(struct qla2xxx_mqueue_header);
586
587 /* Add data. */
588 memcpy(ptr, req->ring, req->length * sizeof(request_t));
589 ptr += req->length * sizeof(request_t);
590 }
591
592 /* Response queues */
593 for (que = 1; que < ha->max_rsp_queues; que++) {
594 rsp = ha->rsp_q_map[que];
595 if (!rsp)
596 break;
597
598 /* Add chain. */
599 q = ptr;
600 *last_chain = &q->type;
601 q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
602 q->chain_size = htonl(
603 sizeof(struct qla2xxx_mqueue_chain) +
604 sizeof(struct qla2xxx_mqueue_header) +
605 (rsp->length * sizeof(response_t)));
606 ptr += sizeof(struct qla2xxx_mqueue_chain);
607
608 /* Add header. */
609 qh = ptr;
610 qh->queue = __constant_htonl(TYPE_RESPONSE_QUEUE);
611 qh->number = htonl(que);
612 qh->size = htonl(rsp->length * sizeof(response_t));
613 ptr += sizeof(struct qla2xxx_mqueue_header);
614
615 /* Add data. */
616 memcpy(ptr, rsp->ring, rsp->length * sizeof(response_t));
617 ptr += rsp->length * sizeof(response_t);
618 }
619
620 return ptr;
621}
622
d63ab533
AV		 623static inline void *
624qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
625{
626 uint32_t cnt, que_idx;
2afa19a9 627 uint8_t que_cnt;
d63ab533 628 struct qla2xxx_mq_chain *mq = ptr;
da9b1d5c 629 device_reg_t __iomem *reg;
d63ab533 630
f73cb695 631 if (!ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha))
d63ab533
AV		 632 return ptr;
633
634 mq = ptr;
635 *last_chain = &mq->type;
636 mq->type = __constant_htonl(DUMP_CHAIN_MQ);
637 mq->chain_size = __constant_htonl(sizeof(struct qla2xxx_mq_chain));
638
2afa19a9
AC		 639 que_cnt = ha->max_req_queues > ha->max_rsp_queues ?
640 ha->max_req_queues : ha->max_rsp_queues;
d63ab533
AV		 641 mq->count = htonl(que_cnt);
642 for (cnt = 0; cnt < que_cnt; cnt++) {
da9b1d5c 643 reg = ISP_QUE_REG(ha, cnt);
d63ab533 644 que_idx = cnt * 4;
da9b1d5c
AV		 645 mq->qregs[que_idx] =
646 htonl(RD_REG_DWORD(&reg->isp25mq.req_q_in));
647 mq->qregs[que_idx+1] =
648 htonl(RD_REG_DWORD(&reg->isp25mq.req_q_out));
649 mq->qregs[que_idx+2] =
650 htonl(RD_REG_DWORD(&reg->isp25mq.rsp_q_in));
651 mq->qregs[que_idx+3] =
652 htonl(RD_REG_DWORD(&reg->isp25mq.rsp_q_out));
d63ab533
AV		 653 }
654
655 return ptr + sizeof(struct qla2xxx_mq_chain);
656}
657
08de2844 658void
3420d36c
AV		 659qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval)
660{
661 struct qla_hw_data *ha = vha->hw;
662
663 if (rval != QLA_SUCCESS) {
7c3df132 664 ql_log(ql_log_warn, vha, 0xd000,
61f098dd
HP		 665 "Failed to dump firmware (%x), dump status flags (0x%lx).\n",
666 rval, ha->fw_dump_cap_flags);
3420d36c
AV		 667 ha->fw_dumped = 0;
668 } else {
7c3df132 669 ql_log(ql_log_info, vha, 0xd001,
61f098dd
HP		 670 "Firmware dump saved to temp buffer (%ld/%p), dump status flags (0x%lx).\n",
671 vha->host_no, ha->fw_dump, ha->fw_dump_cap_flags);
3420d36c
AV		 672 ha->fw_dumped = 1;
673 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
674 }
675}
676
1da177e4
LT		 677/**
678 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
679 * @ha: HA context
680 * @hardware_locked: Called with the hardware_lock
681 */
682void
7b867cf7 683qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1da177e4
LT		 684{
685 int rval;
c5722708 686 uint32_t cnt;
7b867cf7 687 struct qla_hw_data *ha = vha->hw;
3d71644c 688 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 689 uint16_t __iomem *dmp_reg;
690 unsigned long flags;
691 struct qla2300_fw_dump *fw;
c5722708 692 void *nxt;
73208dfd 693 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 694
1da177e4
LT		 695 flags = 0;
696
697 if (!hardware_locked)
698 spin_lock_irqsave(&ha->hardware_lock, flags);
699
d4e3e04d 700 if (!ha->fw_dump) {
7c3df132
SK		 701 ql_log(ql_log_warn, vha, 0xd002,
702 "No buffer available for dump.\n");
1da177e4
LT		 703 goto qla2300_fw_dump_failed;
704 }
705
d4e3e04d 706 if (ha->fw_dumped) {
7c3df132
SK		 707 ql_log(ql_log_warn, vha, 0xd003,
708 "Firmware has been previously dumped (%p) "
709 "-- ignoring request.\n",
710 ha->fw_dump);
1da177e4
LT		 711 goto qla2300_fw_dump_failed;
712 }
a7a167bf
AV		 713 fw = &ha->fw_dump->isp.isp23;
714 qla2xxx_prep_dump(ha, ha->fw_dump);
1da177e4
LT		 715
716 rval = QLA_SUCCESS;
a7a167bf 717 fw->hccr = htons(RD_REG_WORD(&reg->hccr));
1da177e4
LT		 718
719 /* Pause RISC. */
fa2a1ce5 720 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1da177e4
LT		 721 if (IS_QLA2300(ha)) {
722 for (cnt = 30000;
723 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
724 rval == QLA_SUCCESS; cnt--) {
725 if (cnt)
726 udelay(100);
727 else
728 rval = QLA_FUNCTION_TIMEOUT;
729 }
730 } else {
731 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
732 udelay(10);
733 }
734
735 if (rval == QLA_SUCCESS) {
c81d04c9 736 dmp_reg = &reg->flash_address;
fa2a1ce5 737 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
a7a167bf 738 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 739
c81d04c9 740 dmp_reg = &reg->u.isp2300.req_q_in;
fa2a1ce5 741 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
a7a167bf 742 fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 743
c81d04c9 744 dmp_reg = &reg->u.isp2300.mailbox0;
fa2a1ce5 745 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
a7a167bf 746 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4
LT		 747
748 WRT_REG_WORD(&reg->ctrl_status, 0x40);
c81d04c9 749 qla2xxx_read_window(reg, 32, fw->resp_dma_reg);
1da177e4
LT		 750
751 WRT_REG_WORD(&reg->ctrl_status, 0x50);
c81d04c9 752 qla2xxx_read_window(reg, 48, fw->dma_reg);
1da177e4
LT		 753
754 WRT_REG_WORD(&reg->ctrl_status, 0x00);
c81d04c9 755 dmp_reg = &reg->risc_hw;
fa2a1ce5 756 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
a7a167bf 757 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 758
fa2a1ce5 759 WRT_REG_WORD(&reg->pcr, 0x2000);
c81d04c9 760 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
1da177e4 761
fa2a1ce5 762 WRT_REG_WORD(&reg->pcr, 0x2200);
c81d04c9 763 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
1da177e4 764
fa2a1ce5 765 WRT_REG_WORD(&reg->pcr, 0x2400);
c81d04c9 766 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
1da177e4 767
fa2a1ce5 768 WRT_REG_WORD(&reg->pcr, 0x2600);
c81d04c9 769 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
1da177e4 770
fa2a1ce5 771 WRT_REG_WORD(&reg->pcr, 0x2800);
c81d04c9 772 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
1da177e4 773
fa2a1ce5 774 WRT_REG_WORD(&reg->pcr, 0x2A00);
c81d04c9 775 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
1da177e4 776
fa2a1ce5 777 WRT_REG_WORD(&reg->pcr, 0x2C00);
c81d04c9 778 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
1da177e4 779
fa2a1ce5 780 WRT_REG_WORD(&reg->pcr, 0x2E00);
c81d04c9 781 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
1da177e4 782
fa2a1ce5 783 WRT_REG_WORD(&reg->ctrl_status, 0x10);
c81d04c9 784 qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg);
1da177e4 785
fa2a1ce5 786 WRT_REG_WORD(&reg->ctrl_status, 0x20);
c81d04c9 787 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
1da177e4 788
fa2a1ce5 789 WRT_REG_WORD(&reg->ctrl_status, 0x30);
c81d04c9 790 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
1da177e4
LT		 791
792 /* Reset RISC. */
793 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
794 for (cnt = 0; cnt < 30000; cnt++) {
795 if ((RD_REG_WORD(&reg->ctrl_status) &
796 CSR_ISP_SOFT_RESET) == 0)
797 break;
798
799 udelay(10);
800 }
801 }
802
803 if (!IS_QLA2300(ha)) {
804 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
805 rval == QLA_SUCCESS; cnt--) {
806 if (cnt)
807 udelay(100);
808 else
809 rval = QLA_FUNCTION_TIMEOUT;
810 }
811 }
812
c5722708
AV		 813 /* Get RISC SRAM. */
814 if (rval == QLA_SUCCESS)
815 rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram,
816 sizeof(fw->risc_ram) / 2, &nxt);
1da177e4 817
c5722708
AV		 818 /* Get stack SRAM. */
819 if (rval == QLA_SUCCESS)
820 rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram,
821 sizeof(fw->stack_ram) / 2, &nxt);
1da177e4 822
c5722708
AV		 823 /* Get data SRAM. */
824 if (rval == QLA_SUCCESS)
825 rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram,
826 ha->fw_memory_size - 0x11000 + 1, &nxt);
1da177e4 827
a7a167bf 828 if (rval == QLA_SUCCESS)
73208dfd 829 qla2xxx_copy_queues(ha, nxt);
a7a167bf 830
3420d36c 831 qla2xxx_dump_post_process(base_vha, rval);
1da177e4
LT		 832
833qla2300_fw_dump_failed:
834 if (!hardware_locked)
835 spin_unlock_irqrestore(&ha->hardware_lock, flags);
836}
837
1da177e4
LT		 838/**
839 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
840 * @ha: HA context
841 * @hardware_locked: Called with the hardware_lock
842 */
843void
7b867cf7 844qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1da177e4
LT		 845{
846 int rval;
847 uint32_t cnt, timer;
848 uint16_t risc_address;
849 uint16_t mb0, mb2;
7b867cf7 850 struct qla_hw_data *ha = vha->hw;
3d71644c 851 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 852 uint16_t __iomem *dmp_reg;
853 unsigned long flags;
854 struct qla2100_fw_dump *fw;
73208dfd 855 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 856
857 risc_address = 0;
858 mb0 = mb2 = 0;
859 flags = 0;
860
861 if (!hardware_locked)
862 spin_lock_irqsave(&ha->hardware_lock, flags);
863
d4e3e04d 864 if (!ha->fw_dump) {
7c3df132
SK		 865 ql_log(ql_log_warn, vha, 0xd004,
866 "No buffer available for dump.\n");
1da177e4
LT		 867 goto qla2100_fw_dump_failed;
868 }
869
d4e3e04d 870 if (ha->fw_dumped) {
7c3df132
SK		 871 ql_log(ql_log_warn, vha, 0xd005,
872 "Firmware has been previously dumped (%p) "
873 "-- ignoring request.\n",
874 ha->fw_dump);
1da177e4
LT		 875 goto qla2100_fw_dump_failed;
876 }
a7a167bf
AV		 877 fw = &ha->fw_dump->isp.isp21;
878 qla2xxx_prep_dump(ha, ha->fw_dump);
1da177e4
LT		 879
880 rval = QLA_SUCCESS;
a7a167bf 881 fw->hccr = htons(RD_REG_WORD(&reg->hccr));
1da177e4
LT		 882
883 /* Pause RISC. */
fa2a1ce5 884 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1da177e4
LT		 885 for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
886 rval == QLA_SUCCESS; cnt--) {
887 if (cnt)
888 udelay(100);
889 else
890 rval = QLA_FUNCTION_TIMEOUT;
891 }
892 if (rval == QLA_SUCCESS) {
c81d04c9 893 dmp_reg = &reg->flash_address;
fa2a1ce5 894 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
a7a167bf 895 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 896
c81d04c9 897 dmp_reg = &reg->u.isp2100.mailbox0;
1da177e4 898 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
c81d04c9
AV		 899 if (cnt == 8)
900 dmp_reg = &reg->u_end.isp2200.mailbox8;
901
a7a167bf 902 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4
LT		 903 }
904
c81d04c9 905 dmp_reg = &reg->u.isp2100.unused_2[0];
fa2a1ce5 906 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
a7a167bf 907 fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4
LT		 908
909 WRT_REG_WORD(&reg->ctrl_status, 0x00);
c81d04c9 910 dmp_reg = &reg->risc_hw;
fa2a1ce5 911 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
a7a167bf 912 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 913
fa2a1ce5 914 WRT_REG_WORD(&reg->pcr, 0x2000);
c81d04c9 915 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
1da177e4 916
fa2a1ce5 917 WRT_REG_WORD(&reg->pcr, 0x2100);
c81d04c9 918 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
1da177e4 919
fa2a1ce5 920 WRT_REG_WORD(&reg->pcr, 0x2200);
c81d04c9 921 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
1da177e4 922
fa2a1ce5 923 WRT_REG_WORD(&reg->pcr, 0x2300);
c81d04c9 924 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
1da177e4 925
fa2a1ce5 926 WRT_REG_WORD(&reg->pcr, 0x2400);
c81d04c9 927 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
1da177e4 928
fa2a1ce5 929 WRT_REG_WORD(&reg->pcr, 0x2500);
c81d04c9 930 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
1da177e4 931
fa2a1ce5 932 WRT_REG_WORD(&reg->pcr, 0x2600);
c81d04c9 933 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
1da177e4 934
fa2a1ce5 935 WRT_REG_WORD(&reg->pcr, 0x2700);
c81d04c9 936 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
1da177e4 937
fa2a1ce5 938 WRT_REG_WORD(&reg->ctrl_status, 0x10);
c81d04c9 939 qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg);
1da177e4 940
fa2a1ce5 941 WRT_REG_WORD(&reg->ctrl_status, 0x20);
c81d04c9 942 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
1da177e4 943
fa2a1ce5 944 WRT_REG_WORD(&reg->ctrl_status, 0x30);
c81d04c9 945 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
1da177e4
LT		 946
947 /* Reset the ISP. */
948 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
949 }
950
951 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
952 rval == QLA_SUCCESS; cnt--) {
953 if (cnt)
954 udelay(100);
955 else
956 rval = QLA_FUNCTION_TIMEOUT;
957 }
958
959 /* Pause RISC. */
960 if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) &&
961 (RD_REG_WORD(&reg->mctr) & (BIT_1 | BIT_0)) != 0))) {
962
fa2a1ce5 963 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1da177e4
LT		 964 for (cnt = 30000;
965 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
966 rval == QLA_SUCCESS; cnt--) {
967 if (cnt)
968 udelay(100);
969 else
970 rval = QLA_FUNCTION_TIMEOUT;
971 }
972 if (rval == QLA_SUCCESS) {
973 /* Set memory configuration and timing. */
974 if (IS_QLA2100(ha))
975 WRT_REG_WORD(&reg->mctr, 0xf1);
976 else
977 WRT_REG_WORD(&reg->mctr, 0xf2);
978 RD_REG_WORD(&reg->mctr); /* PCI Posting. */
979
980 /* Release RISC. */
981 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
982 }
983 }
984
985 if (rval == QLA_SUCCESS) {
986 /* Get RISC SRAM. */
987 risc_address = 0x1000;
988 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
989 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
990 }
991 for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
992 cnt++, risc_address++) {
993 WRT_MAILBOX_REG(ha, reg, 1, risc_address);
994 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
995
996 for (timer = 6000000; timer != 0; timer--) {
997 /* Check for pending interrupts. */
998 if (RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) {
999 if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
1000 set_bit(MBX_INTERRUPT,
1001 &ha->mbx_cmd_flags);
1002
1003 mb0 = RD_MAILBOX_REG(ha, reg, 0);
1004 mb2 = RD_MAILBOX_REG(ha, reg, 2);
1005
1006 WRT_REG_WORD(&reg->semaphore, 0);
1007 WRT_REG_WORD(&reg->hccr,
1008 HCCR_CLR_RISC_INT);
1009 RD_REG_WORD(&reg->hccr);
1010 break;
1011 }
1012 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
1013 RD_REG_WORD(&reg->hccr);
1014 }
1015 udelay(5);
1016 }
1017
1018 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
1019 rval = mb0 & MBS_MASK;
a7a167bf 1020 fw->risc_ram[cnt] = htons(mb2);
1da177e4
LT		 1021 } else {
1022 rval = QLA_FUNCTION_FAILED;
1023 }
1024 }
1025
a7a167bf 1026 if (rval == QLA_SUCCESS)
73208dfd 1027 qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]);
a7a167bf 1028
3420d36c 1029 qla2xxx_dump_post_process(base_vha, rval);
1da177e4
LT		 1030
1031qla2100_fw_dump_failed:
1032 if (!hardware_locked)
1033 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1034}
1035
6d9b61ed 1036void
7b867cf7 1037qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
6d9b61ed
AV		 1038{
1039 int rval;
c3a2f0df 1040 uint32_t cnt;
6d9b61ed 1041 uint32_t risc_address;
7b867cf7 1042 struct qla_hw_data *ha = vha->hw;
6d9b61ed
AV		 1043 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1044 uint32_t __iomem *dmp_reg;
1045 uint32_t *iter_reg;
1046 uint16_t __iomem *mbx_reg;
1047 unsigned long flags;
1048 struct qla24xx_fw_dump *fw;
1049 uint32_t ext_mem_cnt;
c3a2f0df 1050 void *nxt;
2d70c103
NB		 1051 void *nxt_chain;
1052 uint32_t *last_chain = NULL;
73208dfd 1053 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
6d9b61ed 1054
7ec0effd 1055 if (IS_P3P_TYPE(ha))
a9083016
GM		 1056 return;
1057
6d9b61ed 1058 risc_address = ext_mem_cnt = 0;
6d9b61ed 1059 flags = 0;
61f098dd 1060 ha->fw_dump_cap_flags = 0;
6d9b61ed
AV		 1061
1062 if (!hardware_locked)
1063 spin_lock_irqsave(&ha->hardware_lock, flags);
1064
d4e3e04d 1065 if (!ha->fw_dump) {
7c3df132
SK		 1066 ql_log(ql_log_warn, vha, 0xd006,
1067 "No buffer available for dump.\n");
6d9b61ed
AV		 1068 goto qla24xx_fw_dump_failed;
1069 }
1070
1071 if (ha->fw_dumped) {
7c3df132
SK		 1072 ql_log(ql_log_warn, vha, 0xd007,
1073 "Firmware has been previously dumped (%p) "
1074 "-- ignoring request.\n",
1075 ha->fw_dump);
6d9b61ed
AV		 1076 goto qla24xx_fw_dump_failed;
1077 }
a7a167bf
AV		 1078 fw = &ha->fw_dump->isp.isp24;
1079 qla2xxx_prep_dump(ha, ha->fw_dump);
6d9b61ed 1080
a7a167bf 1081 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
6d9b61ed 1082
2f389fc4
HP		 1083 /*
1084 * Pause RISC. No need to track timeout, as resetting the chip
1085 * is the right approach incase of pause timeout
1086 */
61f098dd 1087 qla24xx_pause_risc(reg, ha);
c81d04c9
AV		 1088
1089 /* Host interface registers. */
1090 dmp_reg = &reg->flash_addr;
1091 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1092 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1093
1094 /* Disable interrupts. */
1095 WRT_REG_DWORD(&reg->ictrl, 0);
1096 RD_REG_DWORD(&reg->ictrl);
1097
1098 /* Shadow registers. */
1099 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1100 RD_REG_DWORD(&reg->iobase_addr);
1101 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1102 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1103
1104 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1105 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1106
1107 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1108 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1109
1110 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1111 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1112
1113 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1114 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1115
1116 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1117 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1118
1119 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1120 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1121
1122 /* Mailbox registers. */
1123 mbx_reg = &reg->mailbox0;
1124 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1125 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1126
1127 /* Transfer sequence registers. */
1128 iter_reg = fw->xseq_gp_reg;
1129 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1130 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1131 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1132 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1133 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1134 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1135 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1136 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1137
1138 qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg);
1139 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1140
1141 /* Receive sequence registers. */
1142 iter_reg = fw->rseq_gp_reg;
1143 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1144 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1145 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1146 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1147 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1148 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1149 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1150 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1151
1152 qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg);
1153 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1154 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1155
1156 /* Command DMA registers. */
1157 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1158
1159 /* Queues. */
1160 iter_reg = fw->req0_dma_reg;
1161 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1162 dmp_reg = &reg->iobase_q;
1163 for (cnt = 0; cnt < 7; cnt++)
1164 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1165
1166 iter_reg = fw->resp0_dma_reg;
1167 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1168 dmp_reg = &reg->iobase_q;
1169 for (cnt = 0; cnt < 7; cnt++)
1170 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1171
1172 iter_reg = fw->req1_dma_reg;
1173 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1174 dmp_reg = &reg->iobase_q;
1175 for (cnt = 0; cnt < 7; cnt++)
1176 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1177
1178 /* Transmit DMA registers. */
1179 iter_reg = fw->xmt0_dma_reg;
1180 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1181 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1182
1183 iter_reg = fw->xmt1_dma_reg;
1184 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1185 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1186
1187 iter_reg = fw->xmt2_dma_reg;
1188 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1189 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1190
1191 iter_reg = fw->xmt3_dma_reg;
1192 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1193 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1194
1195 iter_reg = fw->xmt4_dma_reg;
1196 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1197 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1198
1199 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1200
1201 /* Receive DMA registers. */
1202 iter_reg = fw->rcvt0_data_dma_reg;
1203 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1204 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1205
1206 iter_reg = fw->rcvt1_data_dma_reg;
1207 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1208 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1209
1210 /* RISC registers. */
1211 iter_reg = fw->risc_gp_reg;
1212 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1213 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1214 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1215 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1216 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1217 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1218 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1219 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1220
1221 /* Local memory controller registers. */
1222 iter_reg = fw->lmc_reg;
1223 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1224 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1225 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1226 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1227 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1228 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1229 qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1230
1231 /* Fibre Protocol Module registers. */
1232 iter_reg = fw->fpm_hdw_reg;
1233 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1234 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1235 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1236 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1237 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1238 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1239 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1240 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1241 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1242 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1243 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1244 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1245
1246 /* Frame Buffer registers. */
1247 iter_reg = fw->fb_hdw_reg;
1248 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1249 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1250 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1251 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1252 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1253 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1254 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1255 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1256 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1257 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1258 qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1259
1260 rval = qla24xx_soft_reset(ha);
1261 if (rval != QLA_SUCCESS)
1262 goto qla24xx_fw_dump_failed_0;
1263
1264 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
c5722708 1265 &nxt);
c81d04c9
AV		 1266 if (rval != QLA_SUCCESS)
1267 goto qla24xx_fw_dump_failed_0;
1268
73208dfd 1269 nxt = qla2xxx_copy_queues(ha, nxt);
bb99de67
AV		 1270
1271 qla24xx_copy_eft(ha, nxt);
c81d04c9 1272
2d70c103
NB		 1273 nxt_chain = (void *)ha->fw_dump + ha->chain_offset;
1274 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
1275 if (last_chain) {
1276 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1277 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1278 }
1279
1280 /* Adjust valid length. */
1281 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
1282
c81d04c9 1283qla24xx_fw_dump_failed_0:
3420d36c 1284 qla2xxx_dump_post_process(base_vha, rval);
6d9b61ed 1285
c3a2f0df
AV		 1286qla24xx_fw_dump_failed:
1287 if (!hardware_locked)
1288 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1289}
6d9b61ed 1290
c3a2f0df 1291void
7b867cf7 1292qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
c3a2f0df
AV		 1293{
1294 int rval;
1295 uint32_t cnt;
1296 uint32_t risc_address;
7b867cf7 1297 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 1298 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1299 uint32_t __iomem *dmp_reg;
1300 uint32_t *iter_reg;
1301 uint16_t __iomem *mbx_reg;
1302 unsigned long flags;
1303 struct qla25xx_fw_dump *fw;
1304 uint32_t ext_mem_cnt;
d63ab533 1305 void *nxt, *nxt_chain;
bb99de67 1306 uint32_t *last_chain = NULL;
73208dfd 1307 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
6d9b61ed 1308
c3a2f0df
AV		 1309 risc_address = ext_mem_cnt = 0;
1310 flags = 0;
61f098dd 1311 ha->fw_dump_cap_flags = 0;
6d9b61ed 1312
c3a2f0df
AV		 1313 if (!hardware_locked)
1314 spin_lock_irqsave(&ha->hardware_lock, flags);
6d9b61ed 1315
c3a2f0df 1316 if (!ha->fw_dump) {
7c3df132
SK		 1317 ql_log(ql_log_warn, vha, 0xd008,
1318 "No buffer available for dump.\n");
c3a2f0df
AV		 1319 goto qla25xx_fw_dump_failed;
1320 }
6d9b61ed 1321
c3a2f0df 1322 if (ha->fw_dumped) {
7c3df132
SK		 1323 ql_log(ql_log_warn, vha, 0xd009,
1324 "Firmware has been previously dumped (%p) "
1325 "-- ignoring request.\n",
1326 ha->fw_dump);
c3a2f0df
AV		 1327 goto qla25xx_fw_dump_failed;
1328 }
1329 fw = &ha->fw_dump->isp.isp25;
1330 qla2xxx_prep_dump(ha, ha->fw_dump);
b5836927 1331 ha->fw_dump->version = __constant_htonl(2);
6d9b61ed 1332
c3a2f0df 1333 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
6d9b61ed 1334
2f389fc4
HP		 1335 /*
1336 * Pause RISC. No need to track timeout, as resetting the chip
1337 * is the right approach incase of pause timeout
1338 */
61f098dd 1339 qla24xx_pause_risc(reg, ha);
c81d04c9 1340
b5836927
AV		 1341 /* Host/Risc registers. */
1342 iter_reg = fw->host_risc_reg;
1343 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1344 qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1345
1346 /* PCIe registers. */
1347 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1348 RD_REG_DWORD(&reg->iobase_addr);
1349 WRT_REG_DWORD(&reg->iobase_window, 0x01);
1350 dmp_reg = &reg->iobase_c4;
1351 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1352 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1353 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1354 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
73208dfd 1355
b5836927
AV		 1356 WRT_REG_DWORD(&reg->iobase_window, 0x00);
1357 RD_REG_DWORD(&reg->iobase_window);
1358
c81d04c9
AV		 1359 /* Host interface registers. */
1360 dmp_reg = &reg->flash_addr;
1361 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1362 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1363
1364 /* Disable interrupts. */
1365 WRT_REG_DWORD(&reg->ictrl, 0);
1366 RD_REG_DWORD(&reg->ictrl);
1367
1368 /* Shadow registers. */
1369 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1370 RD_REG_DWORD(&reg->iobase_addr);
1371 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1372 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1373
1374 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1375 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1376
1377 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1378 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1379
1380 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1381 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1382
1383 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1384 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1385
1386 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1387 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1388
1389 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1390 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1391
1392 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1393 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1394
1395 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1396 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1397
1398 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1399 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1400
1401 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1402 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1403
1404 /* RISC I/O register. */
1405 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1406 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1407
1408 /* Mailbox registers. */
1409 mbx_reg = &reg->mailbox0;
1410 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1411 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1412
1413 /* Transfer sequence registers. */
1414 iter_reg = fw->xseq_gp_reg;
1415 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1416 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1417 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1418 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1419 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1420 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1421 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1422 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1423
1424 iter_reg = fw->xseq_0_reg;
1425 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1426 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1427 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1428
1429 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1430
1431 /* Receive sequence registers. */
1432 iter_reg = fw->rseq_gp_reg;
1433 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1434 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1435 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1436 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1437 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1438 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1439 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1440 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1441
1442 iter_reg = fw->rseq_0_reg;
1443 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1444 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1445
1446 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1447 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1448
1449 /* Auxiliary sequence registers. */
1450 iter_reg = fw->aseq_gp_reg;
1451 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1452 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1453 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1454 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1455 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1456 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1457 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1458 qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1459
1460 iter_reg = fw->aseq_0_reg;
1461 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1462 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1463
1464 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1465 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1466
1467 /* Command DMA registers. */
1468 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1469
1470 /* Queues. */
1471 iter_reg = fw->req0_dma_reg;
1472 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1473 dmp_reg = &reg->iobase_q;
1474 for (cnt = 0; cnt < 7; cnt++)
1475 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1476
1477 iter_reg = fw->resp0_dma_reg;
1478 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1479 dmp_reg = &reg->iobase_q;
1480 for (cnt = 0; cnt < 7; cnt++)
1481 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1482
1483 iter_reg = fw->req1_dma_reg;
1484 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1485 dmp_reg = &reg->iobase_q;
1486 for (cnt = 0; cnt < 7; cnt++)
1487 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1488
1489 /* Transmit DMA registers. */
1490 iter_reg = fw->xmt0_dma_reg;
1491 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1492 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1493
1494 iter_reg = fw->xmt1_dma_reg;
1495 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1496 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1497
1498 iter_reg = fw->xmt2_dma_reg;
1499 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1500 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1501
1502 iter_reg = fw->xmt3_dma_reg;
1503 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1504 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1505
1506 iter_reg = fw->xmt4_dma_reg;
1507 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1508 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1509
1510 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1511
1512 /* Receive DMA registers. */
1513 iter_reg = fw->rcvt0_data_dma_reg;
1514 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1515 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1516
1517 iter_reg = fw->rcvt1_data_dma_reg;
1518 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1519 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1520
1521 /* RISC registers. */
1522 iter_reg = fw->risc_gp_reg;
1523 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1524 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1525 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1526 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1527 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1528 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1529 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1530 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1531
1532 /* Local memory controller registers. */
1533 iter_reg = fw->lmc_reg;
1534 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1535 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1536 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1537 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1538 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1539 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1540 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1541 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1542
1543 /* Fibre Protocol Module registers. */
1544 iter_reg = fw->fpm_hdw_reg;
1545 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1546 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1547 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1548 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1549 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1550 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1551 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1552 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1553 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1554 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1555 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1556 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1557
1558 /* Frame Buffer registers. */
1559 iter_reg = fw->fb_hdw_reg;
1560 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1561 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1562 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1563 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1564 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1565 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1566 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1567 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1568 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1569 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1570 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1571 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1572
d63ab533
AV		 1573 /* Multi queue registers */
1574 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
1575 &last_chain);
1576
c81d04c9
AV		 1577 rval = qla24xx_soft_reset(ha);
1578 if (rval != QLA_SUCCESS)
1579 goto qla25xx_fw_dump_failed_0;
1580
1581 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
c5722708 1582 &nxt);
c81d04c9
AV		 1583 if (rval != QLA_SUCCESS)
1584 goto qla25xx_fw_dump_failed_0;
1585
73208dfd 1586 nxt = qla2xxx_copy_queues(ha, nxt);
c81d04c9 1587
7f544d00 1588 qla24xx_copy_eft(ha, nxt);
df613b96 1589
d63ab533 1590 /* Chain entries -- started with MQ. */
050c9bb1
GM		 1591 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
1592 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
2d70c103 1593 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
bb99de67
AV		 1594 if (last_chain) {
1595 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1596 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1597 }
df613b96 1598
050c9bb1
GM		 1599 /* Adjust valid length. */
1600 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
1601
c81d04c9 1602qla25xx_fw_dump_failed_0:
3420d36c 1603 qla2xxx_dump_post_process(base_vha, rval);
6d9b61ed 1604
c3a2f0df 1605qla25xx_fw_dump_failed:
6d9b61ed
AV		 1606 if (!hardware_locked)
1607 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1608}
3a03eb79
AV		 1609
1610void
1611qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1612{
1613 int rval;
1614 uint32_t cnt;
1615 uint32_t risc_address;
1616 struct qla_hw_data *ha = vha->hw;
1617 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1618 uint32_t __iomem *dmp_reg;
1619 uint32_t *iter_reg;
1620 uint16_t __iomem *mbx_reg;
1621 unsigned long flags;
1622 struct qla81xx_fw_dump *fw;
1623 uint32_t ext_mem_cnt;
1624 void *nxt, *nxt_chain;
1625 uint32_t *last_chain = NULL;
1626 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1627
1628 risc_address = ext_mem_cnt = 0;
1629 flags = 0;
61f098dd 1630 ha->fw_dump_cap_flags = 0;
3a03eb79
AV		 1631
1632 if (!hardware_locked)
1633 spin_lock_irqsave(&ha->hardware_lock, flags);
1634
1635 if (!ha->fw_dump) {
7c3df132
SK		 1636 ql_log(ql_log_warn, vha, 0xd00a,
1637 "No buffer available for dump.\n");
3a03eb79
AV		 1638 goto qla81xx_fw_dump_failed;
1639 }
1640
1641 if (ha->fw_dumped) {
7c3df132
SK		 1642 ql_log(ql_log_warn, vha, 0xd00b,
1643 "Firmware has been previously dumped (%p) "
1644 "-- ignoring request.\n",
1645 ha->fw_dump);
3a03eb79
AV		 1646 goto qla81xx_fw_dump_failed;
1647 }
1648 fw = &ha->fw_dump->isp.isp81;
1649 qla2xxx_prep_dump(ha, ha->fw_dump);
1650
1651 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
1652
2f389fc4
HP		 1653 /*
1654 * Pause RISC. No need to track timeout, as resetting the chip
1655 * is the right approach incase of pause timeout
1656 */
61f098dd 1657 qla24xx_pause_risc(reg, ha);
3a03eb79
AV		 1658
1659 /* Host/Risc registers. */
1660 iter_reg = fw->host_risc_reg;
1661 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1662 qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1663
1664 /* PCIe registers. */
1665 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1666 RD_REG_DWORD(&reg->iobase_addr);
1667 WRT_REG_DWORD(&reg->iobase_window, 0x01);
1668 dmp_reg = &reg->iobase_c4;
1669 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1670 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1671 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1672 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
1673
1674 WRT_REG_DWORD(&reg->iobase_window, 0x00);
1675 RD_REG_DWORD(&reg->iobase_window);
1676
1677 /* Host interface registers. */
1678 dmp_reg = &reg->flash_addr;
1679 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1680 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1681
1682 /* Disable interrupts. */
1683 WRT_REG_DWORD(&reg->ictrl, 0);
1684 RD_REG_DWORD(&reg->ictrl);
1685
1686 /* Shadow registers. */
1687 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1688 RD_REG_DWORD(&reg->iobase_addr);
1689 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1690 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1691
1692 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1693 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1694
1695 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1696 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1697
1698 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1699 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1700
1701 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1702 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1703
1704 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1705 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1706
1707 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1708 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1709
1710 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1711 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1712
1713 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1714 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1715
1716 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1717 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1718
1719 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1720 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1721
1722 /* RISC I/O register. */
1723 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1724 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1725
1726 /* Mailbox registers. */
1727 mbx_reg = &reg->mailbox0;
1728 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1729 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1730
1731 /* Transfer sequence registers. */
1732 iter_reg = fw->xseq_gp_reg;
1733 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1734 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1735 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1736 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1737 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1738 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1739 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1740 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1741
1742 iter_reg = fw->xseq_0_reg;
1743 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1744 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1745 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1746
1747 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1748
1749 /* Receive sequence registers. */
1750 iter_reg = fw->rseq_gp_reg;
1751 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1752 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1753 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1754 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1755 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1756 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1757 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1758 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1759
1760 iter_reg = fw->rseq_0_reg;
1761 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1762 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1763
1764 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1765 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1766
1767 /* Auxiliary sequence registers. */
1768 iter_reg = fw->aseq_gp_reg;
1769 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1770 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1771 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1772 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1773 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1774 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1775 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1776 qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1777
1778 iter_reg = fw->aseq_0_reg;
1779 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1780 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1781
1782 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1783 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1784
1785 /* Command DMA registers. */
1786 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1787
1788 /* Queues. */
1789 iter_reg = fw->req0_dma_reg;
1790 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1791 dmp_reg = &reg->iobase_q;
1792 for (cnt = 0; cnt < 7; cnt++)
1793 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1794
1795 iter_reg = fw->resp0_dma_reg;
1796 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1797 dmp_reg = &reg->iobase_q;
1798 for (cnt = 0; cnt < 7; cnt++)
1799 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1800
1801 iter_reg = fw->req1_dma_reg;
1802 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1803 dmp_reg = &reg->iobase_q;
1804 for (cnt = 0; cnt < 7; cnt++)
1805 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1806
1807 /* Transmit DMA registers. */
1808 iter_reg = fw->xmt0_dma_reg;
1809 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1810 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1811
1812 iter_reg = fw->xmt1_dma_reg;
1813 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1814 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1815
1816 iter_reg = fw->xmt2_dma_reg;
1817 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1818 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1819
1820 iter_reg = fw->xmt3_dma_reg;
1821 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1822 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1823
1824 iter_reg = fw->xmt4_dma_reg;
1825 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1826 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1827
1828 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1829
1830 /* Receive DMA registers. */
1831 iter_reg = fw->rcvt0_data_dma_reg;
1832 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1833 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1834
1835 iter_reg = fw->rcvt1_data_dma_reg;
1836 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1837 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1838
1839 /* RISC registers. */
1840 iter_reg = fw->risc_gp_reg;
1841 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1842 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1843 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1844 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1845 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1846 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1847 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1848 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1849
1850 /* Local memory controller registers. */
1851 iter_reg = fw->lmc_reg;
1852 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1853 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1854 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1855 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1856 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1857 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1858 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1859 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1860
1861 /* Fibre Protocol Module registers. */
1862 iter_reg = fw->fpm_hdw_reg;
1863 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1864 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1865 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1866 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1867 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1868 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1869 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1870 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1871 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1872 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1873 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1874 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1875 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
1876 qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
1877
1878 /* Frame Buffer registers. */
1879 iter_reg = fw->fb_hdw_reg;
1880 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1881 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1882 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1883 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1884 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1885 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1886 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1887 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1888 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1889 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1890 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1891 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
1892 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1893
1894 /* Multi queue registers */
1895 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
1896 &last_chain);
1897
1898 rval = qla24xx_soft_reset(ha);
1899 if (rval != QLA_SUCCESS)
1900 goto qla81xx_fw_dump_failed_0;
1901
1902 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1903 &nxt);
1904 if (rval != QLA_SUCCESS)
1905 goto qla81xx_fw_dump_failed_0;
1906
1907 nxt = qla2xxx_copy_queues(ha, nxt);
1908
7f544d00 1909 qla24xx_copy_eft(ha, nxt);
3a03eb79
AV		 1910
1911 /* Chain entries -- started with MQ. */
050c9bb1
GM		 1912 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
1913 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
2d70c103 1914 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
3a03eb79
AV		 1915 if (last_chain) {
1916 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1917 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1918 }
1919
050c9bb1
GM		 1920 /* Adjust valid length. */
1921 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
1922
3a03eb79 1923qla81xx_fw_dump_failed_0:
3420d36c 1924 qla2xxx_dump_post_process(base_vha, rval);
3a03eb79
AV		 1925
1926qla81xx_fw_dump_failed:
1927 if (!hardware_locked)
1928 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1929}
1930
6246b8a1
GM		 1931void
1932qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1933{
1934 int rval;
1935 uint32_t cnt, reg_data;
1936 uint32_t risc_address;
1937 struct qla_hw_data *ha = vha->hw;
1938 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1939 uint32_t __iomem *dmp_reg;
1940 uint32_t *iter_reg;
1941 uint16_t __iomem *mbx_reg;
1942 unsigned long flags;
1943 struct qla83xx_fw_dump *fw;
1944 uint32_t ext_mem_cnt;
1945 void *nxt, *nxt_chain;
1946 uint32_t *last_chain = NULL;
1947 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1948
1949 risc_address = ext_mem_cnt = 0;
1950 flags = 0;
61f098dd 1951 ha->fw_dump_cap_flags = 0;
6246b8a1
GM		 1952
1953 if (!hardware_locked)
1954 spin_lock_irqsave(&ha->hardware_lock, flags);
1955
1956 if (!ha->fw_dump) {
1957 ql_log(ql_log_warn, vha, 0xd00c,
1958 "No buffer available for dump!!!\n");
1959 goto qla83xx_fw_dump_failed;
1960 }
1961
1962 if (ha->fw_dumped) {
1963 ql_log(ql_log_warn, vha, 0xd00d,
1964 "Firmware has been previously dumped (%p) -- ignoring "
1965 "request...\n", ha->fw_dump);
1966 goto qla83xx_fw_dump_failed;
1967 }
1968 fw = &ha->fw_dump->isp.isp83;
1969 qla2xxx_prep_dump(ha, ha->fw_dump);
1970
1971 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
1972
2f389fc4
HP		 1973 /*
1974 * Pause RISC. No need to track timeout, as resetting the chip
1975 * is the right approach incase of pause timeout
1976 */
61f098dd 1977 qla24xx_pause_risc(reg, ha);
6246b8a1
GM		 1978
1979 WRT_REG_DWORD(&reg->iobase_addr, 0x6000);
1980 dmp_reg = &reg->iobase_window;
1981 reg_data = RD_REG_DWORD(dmp_reg);
1982 WRT_REG_DWORD(dmp_reg, 0);
1983
1984 dmp_reg = &reg->unused_4_1[0];
1985 reg_data = RD_REG_DWORD(dmp_reg);
1986 WRT_REG_DWORD(dmp_reg, 0);
1987
1988 WRT_REG_DWORD(&reg->iobase_addr, 0x6010);
1989 dmp_reg = &reg->unused_4_1[2];
1990 reg_data = RD_REG_DWORD(dmp_reg);
1991 WRT_REG_DWORD(dmp_reg, 0);
1992
1993 /* select PCR and disable ecc checking and correction */
1994 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1995 RD_REG_DWORD(&reg->iobase_addr);
1996 WRT_REG_DWORD(&reg->iobase_select, 0x60000000); /* write to F0h = PCR */
1997
1998 /* Host/Risc registers. */
1999 iter_reg = fw->host_risc_reg;
2000 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
2001 iter_reg = qla24xx_read_window(reg, 0x7010, 16, iter_reg);
2002 qla24xx_read_window(reg, 0x7040, 16, iter_reg);
2003
2004 /* PCIe registers. */
2005 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
2006 RD_REG_DWORD(&reg->iobase_addr);
2007 WRT_REG_DWORD(&reg->iobase_window, 0x01);
2008 dmp_reg = &reg->iobase_c4;
2009 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
2010 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
2011 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
2012 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
2013
2014 WRT_REG_DWORD(&reg->iobase_window, 0x00);
2015 RD_REG_DWORD(&reg->iobase_window);
2016
2017 /* Host interface registers. */
2018 dmp_reg = &reg->flash_addr;
2019 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
2020 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
2021
2022 /* Disable interrupts. */
2023 WRT_REG_DWORD(&reg->ictrl, 0);
2024 RD_REG_DWORD(&reg->ictrl);
2025
2026 /* Shadow registers. */
2027 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
2028 RD_REG_DWORD(&reg->iobase_addr);
2029 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
2030 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
2031
2032 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
2033 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
2034
2035 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
2036 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
2037
2038 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
2039 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
2040
2041 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
2042 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
2043
2044 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
2045 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
2046
2047 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
2048 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
2049
2050 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
2051 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
2052
2053 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
2054 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
2055
2056 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
2057 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
2058
2059 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
2060 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
2061
2062 /* RISC I/O register. */
2063 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
2064 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
2065
2066 /* Mailbox registers. */
2067 mbx_reg = &reg->mailbox0;
2068 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
2069 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
2070
2071 /* Transfer sequence registers. */
2072 iter_reg = fw->xseq_gp_reg;
2073 iter_reg = qla24xx_read_window(reg, 0xBE00, 16, iter_reg);
2074 iter_reg = qla24xx_read_window(reg, 0xBE10, 16, iter_reg);
2075 iter_reg = qla24xx_read_window(reg, 0xBE20, 16, iter_reg);
2076 iter_reg = qla24xx_read_window(reg, 0xBE30, 16, iter_reg);
2077 iter_reg = qla24xx_read_window(reg, 0xBE40, 16, iter_reg);
2078 iter_reg = qla24xx_read_window(reg, 0xBE50, 16, iter_reg);
2079 iter_reg = qla24xx_read_window(reg, 0xBE60, 16, iter_reg);
2080 iter_reg = qla24xx_read_window(reg, 0xBE70, 16, iter_reg);
2081 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
2082 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
2083 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
2084 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
2085 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
2086 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
2087 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
2088 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
2089
2090 iter_reg = fw->xseq_0_reg;
2091 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
2092 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
2093 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
2094
2095 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
2096
2097 qla24xx_read_window(reg, 0xBEF0, 16, fw->xseq_2_reg);
2098
2099 /* Receive sequence registers. */
2100 iter_reg = fw->rseq_gp_reg;
2101 iter_reg = qla24xx_read_window(reg, 0xFE00, 16, iter_reg);
2102 iter_reg = qla24xx_read_window(reg, 0xFE10, 16, iter_reg);
2103 iter_reg = qla24xx_read_window(reg, 0xFE20, 16, iter_reg);
2104 iter_reg = qla24xx_read_window(reg, 0xFE30, 16, iter_reg);
2105 iter_reg = qla24xx_read_window(reg, 0xFE40, 16, iter_reg);
2106 iter_reg = qla24xx_read_window(reg, 0xFE50, 16, iter_reg);
2107 iter_reg = qla24xx_read_window(reg, 0xFE60, 16, iter_reg);
2108 iter_reg = qla24xx_read_window(reg, 0xFE70, 16, iter_reg);
2109 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
2110 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
2111 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
2112 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
2113 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
2114 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
2115 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
2116 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
2117
2118 iter_reg = fw->rseq_0_reg;
2119 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
2120 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
2121
2122 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
2123 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
2124 qla24xx_read_window(reg, 0xFEF0, 16, fw->rseq_3_reg);
2125
2126 /* Auxiliary sequence registers. */
2127 iter_reg = fw->aseq_gp_reg;
2128 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
2129 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
2130 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
2131 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
2132 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
2133 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
2134 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
2135 iter_reg = qla24xx_read_window(reg, 0xB070, 16, iter_reg);
2136 iter_reg = qla24xx_read_window(reg, 0xB100, 16, iter_reg);
2137 iter_reg = qla24xx_read_window(reg, 0xB110, 16, iter_reg);
2138 iter_reg = qla24xx_read_window(reg, 0xB120, 16, iter_reg);
2139 iter_reg = qla24xx_read_window(reg, 0xB130, 16, iter_reg);
2140 iter_reg = qla24xx_read_window(reg, 0xB140, 16, iter_reg);
2141 iter_reg = qla24xx_read_window(reg, 0xB150, 16, iter_reg);
2142 iter_reg = qla24xx_read_window(reg, 0xB160, 16, iter_reg);
2143 qla24xx_read_window(reg, 0xB170, 16, iter_reg);
2144
2145 iter_reg = fw->aseq_0_reg;
2146 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
2147 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
2148
2149 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
2150 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
2151 qla24xx_read_window(reg, 0xB1F0, 16, fw->aseq_3_reg);
2152
2153 /* Command DMA registers. */
2154 iter_reg = fw->cmd_dma_reg;
2155 iter_reg = qla24xx_read_window(reg, 0x7100, 16, iter_reg);
2156 iter_reg = qla24xx_read_window(reg, 0x7120, 16, iter_reg);
2157 iter_reg = qla24xx_read_window(reg, 0x7130, 16, iter_reg);
2158 qla24xx_read_window(reg, 0x71F0, 16, iter_reg);
2159
2160 /* Queues. */
2161 iter_reg = fw->req0_dma_reg;
2162 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
2163 dmp_reg = &reg->iobase_q;
2164 for (cnt = 0; cnt < 7; cnt++)
2165 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
2166
2167 iter_reg = fw->resp0_dma_reg;
2168 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
2169 dmp_reg = &reg->iobase_q;
2170 for (cnt = 0; cnt < 7; cnt++)
2171 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
2172
2173 iter_reg = fw->req1_dma_reg;
2174 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
2175 dmp_reg = &reg->iobase_q;
2176 for (cnt = 0; cnt < 7; cnt++)
2177 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
2178
2179 /* Transmit DMA registers. */
2180 iter_reg = fw->xmt0_dma_reg;
2181 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
2182 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
2183
2184 iter_reg = fw->xmt1_dma_reg;
2185 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
2186 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
2187
2188 iter_reg = fw->xmt2_dma_reg;
2189 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
2190 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
2191
2192 iter_reg = fw->xmt3_dma_reg;
2193 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
2194 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
2195
2196 iter_reg = fw->xmt4_dma_reg;
2197 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
2198 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
2199
2200 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
2201
2202 /* Receive DMA registers. */
2203 iter_reg = fw->rcvt0_data_dma_reg;
2204 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
2205 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
2206
2207 iter_reg = fw->rcvt1_data_dma_reg;
2208 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
2209 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
2210
2211 /* RISC registers. */
2212 iter_reg = fw->risc_gp_reg;
2213 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
2214 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
2215 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
2216 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
2217 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
2218 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
2219 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
2220 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
2221
2222 /* Local memory controller registers. */
2223 iter_reg = fw->lmc_reg;
2224 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
2225 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
2226 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
2227 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
2228 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
2229 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
2230 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
2231 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
2232
2233 /* Fibre Protocol Module registers. */
2234 iter_reg = fw->fpm_hdw_reg;
2235 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
2236 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
2237 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
2238 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
2239 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
2240 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
2241 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
2242 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
2243 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
2244 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
2245 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
2246 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
2247 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
2248 iter_reg = qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
2249 iter_reg = qla24xx_read_window(reg, 0x40E0, 16, iter_reg);
2250 qla24xx_read_window(reg, 0x40F0, 16, iter_reg);
2251
2252 /* RQ0 Array registers. */
2253 iter_reg = fw->rq0_array_reg;
2254 iter_reg = qla24xx_read_window(reg, 0x5C00, 16, iter_reg);
2255 iter_reg = qla24xx_read_window(reg, 0x5C10, 16, iter_reg);
2256 iter_reg = qla24xx_read_window(reg, 0x5C20, 16, iter_reg);
2257 iter_reg = qla24xx_read_window(reg, 0x5C30, 16, iter_reg);
2258 iter_reg = qla24xx_read_window(reg, 0x5C40, 16, iter_reg);
2259 iter_reg = qla24xx_read_window(reg, 0x5C50, 16, iter_reg);
2260 iter_reg = qla24xx_read_window(reg, 0x5C60, 16, iter_reg);
2261 iter_reg = qla24xx_read_window(reg, 0x5C70, 16, iter_reg);
2262 iter_reg = qla24xx_read_window(reg, 0x5C80, 16, iter_reg);
2263 iter_reg = qla24xx_read_window(reg, 0x5C90, 16, iter_reg);
2264 iter_reg = qla24xx_read_window(reg, 0x5CA0, 16, iter_reg);
2265 iter_reg = qla24xx_read_window(reg, 0x5CB0, 16, iter_reg);
2266 iter_reg = qla24xx_read_window(reg, 0x5CC0, 16, iter_reg);
2267 iter_reg = qla24xx_read_window(reg, 0x5CD0, 16, iter_reg);
2268 iter_reg = qla24xx_read_window(reg, 0x5CE0, 16, iter_reg);
2269 qla24xx_read_window(reg, 0x5CF0, 16, iter_reg);
2270
2271 /* RQ1 Array registers. */
2272 iter_reg = fw->rq1_array_reg;
2273 iter_reg = qla24xx_read_window(reg, 0x5D00, 16, iter_reg);
2274 iter_reg = qla24xx_read_window(reg, 0x5D10, 16, iter_reg);
2275 iter_reg = qla24xx_read_window(reg, 0x5D20, 16, iter_reg);
2276 iter_reg = qla24xx_read_window(reg, 0x5D30, 16, iter_reg);
2277 iter_reg = qla24xx_read_window(reg, 0x5D40, 16, iter_reg);
2278 iter_reg = qla24xx_read_window(reg, 0x5D50, 16, iter_reg);
2279 iter_reg = qla24xx_read_window(reg, 0x5D60, 16, iter_reg);
2280 iter_reg = qla24xx_read_window(reg, 0x5D70, 16, iter_reg);
2281 iter_reg = qla24xx_read_window(reg, 0x5D80, 16, iter_reg);
2282 iter_reg = qla24xx_read_window(reg, 0x5D90, 16, iter_reg);
2283 iter_reg = qla24xx_read_window(reg, 0x5DA0, 16, iter_reg);
2284 iter_reg = qla24xx_read_window(reg, 0x5DB0, 16, iter_reg);
2285 iter_reg = qla24xx_read_window(reg, 0x5DC0, 16, iter_reg);
2286 iter_reg = qla24xx_read_window(reg, 0x5DD0, 16, iter_reg);
2287 iter_reg = qla24xx_read_window(reg, 0x5DE0, 16, iter_reg);
2288 qla24xx_read_window(reg, 0x5DF0, 16, iter_reg);
2289
2290 /* RP0 Array registers. */
2291 iter_reg = fw->rp0_array_reg;
2292 iter_reg = qla24xx_read_window(reg, 0x5E00, 16, iter_reg);
2293 iter_reg = qla24xx_read_window(reg, 0x5E10, 16, iter_reg);
2294 iter_reg = qla24xx_read_window(reg, 0x5E20, 16, iter_reg);
2295 iter_reg = qla24xx_read_window(reg, 0x5E30, 16, iter_reg);
2296 iter_reg = qla24xx_read_window(reg, 0x5E40, 16, iter_reg);
2297 iter_reg = qla24xx_read_window(reg, 0x5E50, 16, iter_reg);
2298 iter_reg = qla24xx_read_window(reg, 0x5E60, 16, iter_reg);
2299 iter_reg = qla24xx_read_window(reg, 0x5E70, 16, iter_reg);
2300 iter_reg = qla24xx_read_window(reg, 0x5E80, 16, iter_reg);
2301 iter_reg = qla24xx_read_window(reg, 0x5E90, 16, iter_reg);
2302 iter_reg = qla24xx_read_window(reg, 0x5EA0, 16, iter_reg);
2303 iter_reg = qla24xx_read_window(reg, 0x5EB0, 16, iter_reg);
2304 iter_reg = qla24xx_read_window(reg, 0x5EC0, 16, iter_reg);
2305 iter_reg = qla24xx_read_window(reg, 0x5ED0, 16, iter_reg);
2306 iter_reg = qla24xx_read_window(reg, 0x5EE0, 16, iter_reg);
2307 qla24xx_read_window(reg, 0x5EF0, 16, iter_reg);
2308
2309 /* RP1 Array registers. */
2310 iter_reg = fw->rp1_array_reg;
2311 iter_reg = qla24xx_read_window(reg, 0x5F00, 16, iter_reg);
2312 iter_reg = qla24xx_read_window(reg, 0x5F10, 16, iter_reg);
2313 iter_reg = qla24xx_read_window(reg, 0x5F20, 16, iter_reg);
2314 iter_reg = qla24xx_read_window(reg, 0x5F30, 16, iter_reg);
2315 iter_reg = qla24xx_read_window(reg, 0x5F40, 16, iter_reg);
2316 iter_reg = qla24xx_read_window(reg, 0x5F50, 16, iter_reg);
2317 iter_reg = qla24xx_read_window(reg, 0x5F60, 16, iter_reg);
2318 iter_reg = qla24xx_read_window(reg, 0x5F70, 16, iter_reg);
2319 iter_reg = qla24xx_read_window(reg, 0x5F80, 16, iter_reg);
2320 iter_reg = qla24xx_read_window(reg, 0x5F90, 16, iter_reg);
2321 iter_reg = qla24xx_read_window(reg, 0x5FA0, 16, iter_reg);
2322 iter_reg = qla24xx_read_window(reg, 0x5FB0, 16, iter_reg);
2323 iter_reg = qla24xx_read_window(reg, 0x5FC0, 16, iter_reg);
2324 iter_reg = qla24xx_read_window(reg, 0x5FD0, 16, iter_reg);
2325 iter_reg = qla24xx_read_window(reg, 0x5FE0, 16, iter_reg);
2326 qla24xx_read_window(reg, 0x5FF0, 16, iter_reg);
2327
2328 iter_reg = fw->at0_array_reg;
2329 iter_reg = qla24xx_read_window(reg, 0x7080, 16, iter_reg);
2330 iter_reg = qla24xx_read_window(reg, 0x7090, 16, iter_reg);
2331 iter_reg = qla24xx_read_window(reg, 0x70A0, 16, iter_reg);
2332 iter_reg = qla24xx_read_window(reg, 0x70B0, 16, iter_reg);
2333 iter_reg = qla24xx_read_window(reg, 0x70C0, 16, iter_reg);
2334 iter_reg = qla24xx_read_window(reg, 0x70D0, 16, iter_reg);
2335 iter_reg = qla24xx_read_window(reg, 0x70E0, 16, iter_reg);
2336 qla24xx_read_window(reg, 0x70F0, 16, iter_reg);
2337
2338 /* I/O Queue Control registers. */
2339 qla24xx_read_window(reg, 0x7800, 16, fw->queue_control_reg);
2340
2341 /* Frame Buffer registers. */
2342 iter_reg = fw->fb_hdw_reg;
2343 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
2344 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
2345 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
2346 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
2347 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
2348 iter_reg = qla24xx_read_window(reg, 0x6060, 16, iter_reg);
2349 iter_reg = qla24xx_read_window(reg, 0x6070, 16, iter_reg);
2350 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
2351 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
2352 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
2353 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
2354 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
2355 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
2356 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
2357 iter_reg = qla24xx_read_window(reg, 0x6530, 16, iter_reg);
2358 iter_reg = qla24xx_read_window(reg, 0x6540, 16, iter_reg);
2359 iter_reg = qla24xx_read_window(reg, 0x6550, 16, iter_reg);
2360 iter_reg = qla24xx_read_window(reg, 0x6560, 16, iter_reg);
2361 iter_reg = qla24xx_read_window(reg, 0x6570, 16, iter_reg);
2362 iter_reg = qla24xx_read_window(reg, 0x6580, 16, iter_reg);
2363 iter_reg = qla24xx_read_window(reg, 0x6590, 16, iter_reg);
2364 iter_reg = qla24xx_read_window(reg, 0x65A0, 16, iter_reg);
2365 iter_reg = qla24xx_read_window(reg, 0x65B0, 16, iter_reg);
2366 iter_reg = qla24xx_read_window(reg, 0x65C0, 16, iter_reg);
2367 iter_reg = qla24xx_read_window(reg, 0x65D0, 16, iter_reg);
2368 iter_reg = qla24xx_read_window(reg, 0x65E0, 16, iter_reg);
2369 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
2370
2371 /* Multi queue registers */
2372 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
2373 &last_chain);
2374
2375 rval = qla24xx_soft_reset(ha);
2376 if (rval != QLA_SUCCESS) {
2377 ql_log(ql_log_warn, vha, 0xd00e,
2378 "SOFT RESET FAILED, forcing continuation of dump!!!\n");
2379 rval = QLA_SUCCESS;
2380
2381 ql_log(ql_log_warn, vha, 0xd00f, "try a bigger hammer!!!\n");
2382
2383 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
2384 RD_REG_DWORD(&reg->hccr);
2385
2386 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
2387 RD_REG_DWORD(&reg->hccr);
2388
2389 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
2390 RD_REG_DWORD(&reg->hccr);
2391
2392 for (cnt = 30000; cnt && (RD_REG_WORD(&reg->mailbox0)); cnt--)
2393 udelay(5);
2394
2395 if (!cnt) {
2396 nxt = fw->code_ram;
8c0bc701 2397 nxt += sizeof(fw->code_ram);
6246b8a1
GM		 2398 nxt += (ha->fw_memory_size - 0x100000 + 1);
2399 goto copy_queue;
61f098dd
HP		 2400 } else {
2401 set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
6246b8a1
GM		 2402 ql_log(ql_log_warn, vha, 0xd010,
2403 "bigger hammer success?\n");
61f098dd 2404 }
6246b8a1
GM		 2405 }
2406
2407 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
2408 &nxt);
2409 if (rval != QLA_SUCCESS)
2410 goto qla83xx_fw_dump_failed_0;
2411
2412copy_queue:
2413 nxt = qla2xxx_copy_queues(ha, nxt);
2414
7f544d00 2415 qla24xx_copy_eft(ha, nxt);
6246b8a1
GM		 2416
2417 /* Chain entries -- started with MQ. */
2418 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
2419 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
2d70c103 2420 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
6246b8a1
GM		 2421 if (last_chain) {
2422 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
2423 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
2424 }
2425
2426 /* Adjust valid length. */
2427 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
2428
2429qla83xx_fw_dump_failed_0:
2430 qla2xxx_dump_post_process(base_vha, rval);
2431
2432qla83xx_fw_dump_failed:
2433 if (!hardware_locked)
2434 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2435}
2436
1da177e4
LT		 2437/****************************************************************************/
2438/* Driver Debug Functions. */
2439/****************************************************************************/
cfb0919c
CD		 2440
2441static inline int
2442ql_mask_match(uint32_t level)
2443{
2444 if (ql2xextended_error_logging == 1)
2445 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
2446 return (level & ql2xextended_error_logging) == level;
2447}
2448
3ce8866c
SK		 2449/*
2450 * This function is for formatting and logging debug information.
2451 * It is to be used when vha is available. It formats the message
2452 * and logs it to the messages file.
2453 * parameters:
2454 * level: The level of the debug messages to be printed.
2455 * If ql2xextended_error_logging value is correctly set,
2456 * this message will appear in the messages file.
2457 * vha: Pointer to the scsi_qla_host_t.
2458 * id: This is a unique identifier for the level. It identifies the
2459 * part of the code from where the message originated.
2460 * msg: The message to be displayed.
2461 */
2462void
086b3e8a
JP		 2463ql_dbg(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...)
2464{
2465 va_list va;
2466 struct va_format vaf;
3ce8866c 2467
cfb0919c 2468 if (!ql_mask_match(level))
086b3e8a 2469 return;
3ce8866c 2470
086b3e8a 2471 va_start(va, fmt);
3ce8866c 2472
086b3e8a
JP		 2473 vaf.fmt = fmt;
2474 vaf.va = &va;
3ce8866c 2475
086b3e8a
JP		 2476 if (vha != NULL) {
2477 const struct pci_dev *pdev = vha->hw->pdev;
2478 /* <module-name> <pci-name> <msg-id>:<host> Message */
2479 pr_warn("%s [%s]-%04x:%ld: %pV",
2480 QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset,
2481 vha->host_no, &vaf);
2482 } else {
2483 pr_warn("%s [%s]-%04x: : %pV",
2484 QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf);
3ce8866c
SK		 2485 }
2486
086b3e8a 2487 va_end(va);
3ce8866c
SK		 2488
2489}
2490
2491/*
2492 * This function is for formatting and logging debug information.
d6a03581 2493 * It is to be used when vha is not available and pci is available,
3ce8866c
SK		 2494 * i.e., before host allocation. It formats the message and logs it
2495 * to the messages file.
2496 * parameters:
2497 * level: The level of the debug messages to be printed.
2498 * If ql2xextended_error_logging value is correctly set,
2499 * this message will appear in the messages file.
2500 * pdev: Pointer to the struct pci_dev.
2501 * id: This is a unique id for the level. It identifies the part
2502 * of the code from where the message originated.
2503 * msg: The message to be displayed.
2504 */
2505void
086b3e8a
JP		 2506ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
2507 const char *fmt, ...)
2508{
2509 va_list va;
2510 struct va_format vaf;
3ce8866c
SK		 2511
2512 if (pdev == NULL)
2513 return;
cfb0919c 2514 if (!ql_mask_match(level))
086b3e8a 2515 return;
3ce8866c 2516
086b3e8a 2517 va_start(va, fmt);
3ce8866c 2518
086b3e8a
JP		 2519 vaf.fmt = fmt;
2520 vaf.va = &va;
3ce8866c 2521
086b3e8a
JP		 2522 /* <module-name> <dev-name>:<msg-id> Message */
2523 pr_warn("%s [%s]-%04x: : %pV",
2524 QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, &vaf);
3ce8866c 2525
086b3e8a 2526 va_end(va);
3ce8866c
SK		 2527}
2528
2529/*
2530 * This function is for formatting and logging log messages.
2531 * It is to be used when vha is available. It formats the message
2532 * and logs it to the messages file. All the messages will be logged
2533 * irrespective of value of ql2xextended_error_logging.
2534 * parameters:
2535 * level: The level of the log messages to be printed in the
2536 * messages file.
2537 * vha: Pointer to the scsi_qla_host_t
2538 * id: This is a unique id for the level. It identifies the
2539 * part of the code from where the message originated.
2540 * msg: The message to be displayed.
2541 */
2542void
086b3e8a
JP		 2543ql_log(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...)
2544{
2545 va_list va;
2546 struct va_format vaf;
2547 char pbuf[128];
3ce8866c 2548
086b3e8a
JP		 2549 if (level > ql_errlev)
2550 return;
3ce8866c 2551
086b3e8a
JP		 2552 if (vha != NULL) {
2553 const struct pci_dev *pdev = vha->hw->pdev;
2554 /* <module-name> <msg-id>:<host> Message */
2555 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x:%ld: ",
2556 QL_MSGHDR, dev_name(&(pdev->dev)), id, vha->host_no);
2557 } else {
2558 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
2559 QL_MSGHDR, "0000:00:00.0", id);
2560 }
2561 pbuf[sizeof(pbuf) - 1] = 0;
2562
2563 va_start(va, fmt);
2564
2565 vaf.fmt = fmt;
2566 vaf.va = &va;
2567
2568 switch (level) {
70a3fc76 2569 case ql_log_fatal: /* FATAL LOG */
086b3e8a
JP		 2570 pr_crit("%s%pV", pbuf, &vaf);
2571 break;
70a3fc76 2572 case ql_log_warn:
086b3e8a
JP		 2573 pr_err("%s%pV", pbuf, &vaf);
2574 break;
70a3fc76 2575 case ql_log_info:
086b3e8a
JP		 2576 pr_warn("%s%pV", pbuf, &vaf);
2577 break;
2578 default:
2579 pr_info("%s%pV", pbuf, &vaf);
2580 break;
3ce8866c
SK		 2581 }
2582
086b3e8a 2583 va_end(va);
3ce8866c
SK		 2584}
2585
2586/*
2587 * This function is for formatting and logging log messages.
d6a03581 2588 * It is to be used when vha is not available and pci is available,
3ce8866c
SK		 2589 * i.e., before host allocation. It formats the message and logs
2590 * it to the messages file. All the messages are logged irrespective
2591 * of the value of ql2xextended_error_logging.
2592 * parameters:
2593 * level: The level of the log messages to be printed in the
2594 * messages file.
2595 * pdev: Pointer to the struct pci_dev.
2596 * id: This is a unique id for the level. It identifies the
2597 * part of the code from where the message originated.
2598 * msg: The message to be displayed.
2599 */
2600void
086b3e8a
JP		 2601ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
2602 const char *fmt, ...)
2603{
2604 va_list va;
2605 struct va_format vaf;
2606 char pbuf[128];
3ce8866c
SK		 2607
2608 if (pdev == NULL)
2609 return;
086b3e8a
JP		 2610 if (level > ql_errlev)
2611 return;
3ce8866c 2612
086b3e8a
JP		 2613 /* <module-name> <dev-name>:<msg-id> Message */
2614 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
2615 QL_MSGHDR, dev_name(&(pdev->dev)), id);
2616 pbuf[sizeof(pbuf) - 1] = 0;
2617
2618 va_start(va, fmt);
2619
2620 vaf.fmt = fmt;
2621 vaf.va = &va;
2622
2623 switch (level) {
70a3fc76 2624 case ql_log_fatal: /* FATAL LOG */
086b3e8a
JP		 2625 pr_crit("%s%pV", pbuf, &vaf);
2626 break;
70a3fc76 2627 case ql_log_warn:
086b3e8a
JP		 2628 pr_err("%s%pV", pbuf, &vaf);
2629 break;
70a3fc76 2630 case ql_log_info:
086b3e8a
JP		 2631 pr_warn("%s%pV", pbuf, &vaf);
2632 break;
2633 default:
2634 pr_info("%s%pV", pbuf, &vaf);
2635 break;
3ce8866c
SK		 2636 }
2637
086b3e8a 2638 va_end(va);
3ce8866c
SK		 2639}
2640
2641void
2642ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id)
2643{
2644 int i;
2645 struct qla_hw_data *ha = vha->hw;
2646 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2647 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
2648 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
2649 uint16_t __iomem *mbx_reg;
2650
cfb0919c
CD		 2651 if (!ql_mask_match(level))
2652 return;
3ce8866c 2653
7ec0effd 2654 if (IS_P3P_TYPE(ha))
cfb0919c
CD		 2655 mbx_reg = &reg82->mailbox_in[0];
2656 else if (IS_FWI2_CAPABLE(ha))
2657 mbx_reg = &reg24->mailbox0;
2658 else
2659 mbx_reg = MAILBOX_REG(ha, reg, 0);
2660
2661 ql_dbg(level, vha, id, "Mailbox registers:\n");
2662 for (i = 0; i < 6; i++)
2663 ql_dbg(level, vha, id,
2664 "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++));
3ce8866c
SK		 2665}
2666
2667
2668void
2669ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id,
2670 uint8_t *b, uint32_t size)
2671{
2672 uint32_t cnt;
2673 uint8_t c;
cfb0919c
CD		 2674
2675 if (!ql_mask_match(level))
2676 return;
2677
2678 ql_dbg(level, vha, id, " 0 1 2 3 4 5 6 7 8 "
2679 "9 Ah Bh Ch Dh Eh Fh\n");
2680 ql_dbg(level, vha, id, "----------------------------------"
2681 "----------------------------\n");
2682
2683 ql_dbg(level, vha, id, " ");
2684 for (cnt = 0; cnt < size;) {
2685 c = *b++;
2686 printk("%02x", (uint32_t) c);
2687 cnt++;
2688 if (!(cnt % 16))
2689 printk("\n");
2690 else
2691 printk(" ");
3ce8866c 2692 }
cfb0919c
CD		 2693 if (cnt % 16)
2694 ql_dbg(level, vha, id, "\n");
3ce8866c 2695}
Linux kernel - Deliverables
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