projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[SCSI] qla2xxx: Clean up qla84xx_mgmt_cmd()
[deliverable/linux.git] / drivers / scsi / qla2xxx / qla_dbg.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
1e63395c 3 * Copyright (c) 2003-2013 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4 6 */
3ce8866c
SK		 7
8/*
9 * Table for showing the current message id in use for particular level
10 * Change this table for addition of log/debug messages.
e02587d7
AE		 11 * ----------------------------------------------------------------------
12 * | Level | Last Value Used | Holes |
13 * ----------------------------------------------------------------------
8ae6d9c7 14 * | Module Init and Probe | 0x014f | 0x4b,0xba,0xfa |
754d1243 15 * | Mailbox commands | 0x117a | 0x111a-0x111b |
e9f4f418 16 * | | | 0x1155-0x1158 |
8ae6d9c7 17 * | Device Discovery | 0x2095 | 0x2020-0x2022, |
2a8593f8 18 * | | | 0x2016 |
8ae6d9c7 19 * | Queue Command and IO tracing | 0x3058 | 0x3006-0x300b |
9e522cd8 20 * | | | 0x3027-0x3028 |
8ae6d9c7
GM		 21 * | | | 0x303d-0x3041 |
22 * | | | 0x302d,0x3033 |
23 * | | | 0x3036,0x3038 |
24 * | | | 0x303a |
25 * | DPC Thread | 0x4022 | 0x4002,0x4013 |
26 * | Async Events | 0x5081 | 0x502b-0x502f |
9ba56b95 27 * | | | 0x5047,0x5052 |
8ae6d9c7 28 * | | | 0x5040,0x5075 |
5988aeb2 29 * | Timer Routines | 0x6011 | |
8ae6d9c7 30 * | User Space Interactions | 0x70dd | 0x7018,0x702e, |
78d56df6 31 * | | | 0x7020,0x7024, |
733a95bd
JC		 32 * | | | 0x7039,0x7045, |
33 * | | | 0x7073-0x7075, |
8ae6d9c7 34 * | | | 0x707b,0x708c, |
a9b6f722
SK		 35 * | | | 0x70a5,0x70a6, |
36 * | | | 0x70a8,0x70ab, |
8ae6d9c7 37 * | | | 0x70ad-0x70ae, |
090fc2e2 38 * | | | 0x70d1-0x70da, |
a44c72f3 39 * | | | 0x7047,0x703b |
cfb0919c
CD		 40 * | Task Management | 0x803c | 0x8025-0x8026 |
41 * | | | 0x800b,0x8039 |
5f28d2d7 42 * | AER/EEH | 0x9011 | |
e02587d7 43 * | Virtual Port | 0xa007 | |
6c315553 44 * | ISP82XX Specific | 0xb086 | 0xb002,0xb024 |
6246b8a1
GM		 45 * | MultiQ | 0xc00c | |
46 * | Misc | 0xd010 | |
33c36c0a 47 * | Target Mode | 0xe070 | |
aa230bc5 48 * | Target Mode Management | 0xf072 | |
2d70c103 49 * | Target Mode Task Management | 0x1000b | |
e02587d7 50 * ----------------------------------------------------------------------
3ce8866c
SK		 51 */
52
1da177e4
LT		 53#include "qla_def.h"
54
55#include <linux/delay.h>
56
3ce8866c
SK		 57static uint32_t ql_dbg_offset = 0x800;
58
a7a167bf 59static inline void
7b867cf7 60qla2xxx_prep_dump(struct qla_hw_data *ha, struct qla2xxx_fw_dump *fw_dump)
a7a167bf
AV		 61{
62 fw_dump->fw_major_version = htonl(ha->fw_major_version);
63 fw_dump->fw_minor_version = htonl(ha->fw_minor_version);
64 fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version);
65 fw_dump->fw_attributes = htonl(ha->fw_attributes);
66
67 fw_dump->vendor = htonl(ha->pdev->vendor);
68 fw_dump->device = htonl(ha->pdev->device);
69 fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor);
70 fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device);
71}
72
73static inline void *
73208dfd 74qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr)
a7a167bf 75{
73208dfd
AC		 76 struct req_que *req = ha->req_q_map[0];
77 struct rsp_que *rsp = ha->rsp_q_map[0];
a7a167bf 78 /* Request queue. */
7b867cf7 79 memcpy(ptr, req->ring, req->length *
a7a167bf
AV		 80 sizeof(request_t));
81
82 /* Response queue. */
7b867cf7
AC		 83 ptr += req->length * sizeof(request_t);
84 memcpy(ptr, rsp->ring, rsp->length *
a7a167bf
AV		 85 sizeof(response_t));
86
7b867cf7 87 return ptr + (rsp->length * sizeof(response_t));
a7a167bf 88}
1da177e4 89
c3a2f0df 90static int
7b867cf7 91qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram,
c5722708 92 uint32_t ram_dwords, void **nxt)
c3a2f0df
AV		 93{
94 int rval;
c5722708
AV		 95 uint32_t cnt, stat, timer, dwords, idx;
96 uint16_t mb0;
c3a2f0df 97 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
c5722708
AV		 98 dma_addr_t dump_dma = ha->gid_list_dma;
99 uint32_t *dump = (uint32_t *)ha->gid_list;
c3a2f0df
AV		 100
101 rval = QLA_SUCCESS;
c5722708 102 mb0 = 0;
c3a2f0df 103
c5722708 104 WRT_REG_WORD(&reg->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
c3a2f0df
AV		 105 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
106
642ef983 107 dwords = qla2x00_gid_list_size(ha) / 4;
c5722708
AV		 108 for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
109 cnt += dwords, addr += dwords) {
110 if (cnt + dwords > ram_dwords)
111 dwords = ram_dwords - cnt;
c3a2f0df 112
c5722708
AV		 113 WRT_REG_WORD(&reg->mailbox1, LSW(addr));
114 WRT_REG_WORD(&reg->mailbox8, MSW(addr));
c3a2f0df 115
c5722708
AV		 116 WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
117 WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
118 WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
119 WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
c3a2f0df 120
c5722708
AV		 121 WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
122 WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
c3a2f0df
AV		 123 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
124
125 for (timer = 6000000; timer; timer--) {
126 /* Check for pending interrupts. */
127 stat = RD_REG_DWORD(&reg->host_status);
128 if (stat & HSRX_RISC_INT) {
129 stat &= 0xff;
130
131 if (stat == 0x1 || stat == 0x2 ||
132 stat == 0x10 || stat == 0x11) {
133 set_bit(MBX_INTERRUPT,
134 &ha->mbx_cmd_flags);
135
c5722708 136 mb0 = RD_REG_WORD(&reg->mailbox0);
c3a2f0df
AV		 137
138 WRT_REG_DWORD(&reg->hccr,
139 HCCRX_CLR_RISC_INT);
140 RD_REG_DWORD(&reg->hccr);
141 break;
142 }
143
144 /* Clear this intr; it wasn't a mailbox intr */
145 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
146 RD_REG_DWORD(&reg->hccr);
147 }
148 udelay(5);
149 }
150
151 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
c5722708
AV		 152 rval = mb0 & MBS_MASK;
153 for (idx = 0; idx < dwords; idx++)
154 ram[cnt + idx] = swab32(dump[idx]);
c3a2f0df
AV		 155 } else {
156 rval = QLA_FUNCTION_FAILED;
157 }
158 }
159
c5722708 160 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
c3a2f0df
AV		 161 return rval;
162}
163
c5722708 164static int
7b867cf7 165qla24xx_dump_memory(struct qla_hw_data *ha, uint32_t *code_ram,
c5722708
AV		 166 uint32_t cram_size, void **nxt)
167{
168 int rval;
169
170 /* Code RAM. */
171 rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt);
172 if (rval != QLA_SUCCESS)
173 return rval;
174
175 /* External Memory. */
176 return qla24xx_dump_ram(ha, 0x100000, *nxt,
177 ha->fw_memory_size - 0x100000 + 1, nxt);
178}
179
c81d04c9
AV		 180static uint32_t *
181qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
182 uint32_t count, uint32_t *buf)
183{
184 uint32_t __iomem *dmp_reg;
185
186 WRT_REG_DWORD(&reg->iobase_addr, iobase);
187 dmp_reg = &reg->iobase_window;
188 while (count--)
189 *buf++ = htonl(RD_REG_DWORD(dmp_reg++));
190
191 return buf;
192}
193
194static inline int
195qla24xx_pause_risc(struct device_reg_24xx __iomem *reg)
196{
197 int rval = QLA_SUCCESS;
198 uint32_t cnt;
199
c3b058af 200 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
aed10881
AV		 201 for (cnt = 30000;
202 ((RD_REG_DWORD(&reg->host_status) & HSRX_RISC_PAUSED) == 0) &&
c3b058af
AV		 203 rval == QLA_SUCCESS; cnt--) {
204 if (cnt)
205 udelay(100);
206 else
207 rval = QLA_FUNCTION_TIMEOUT;
c81d04c9
AV		 208 }
209
210 return rval;
211}
212
213static int
7b867cf7 214qla24xx_soft_reset(struct qla_hw_data *ha)
c81d04c9
AV		 215{
216 int rval = QLA_SUCCESS;
217 uint32_t cnt;
218 uint16_t mb0, wd;
219 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
220
221 /* Reset RISC. */
222 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
223 for (cnt = 0; cnt < 30000; cnt++) {
224 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
225 break;
226
227 udelay(10);
228 }
229
230 WRT_REG_DWORD(&reg->ctrl_status,
231 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
232 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
233
234 udelay(100);
235 /* Wait for firmware to complete NVRAM accesses. */
236 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
237 for (cnt = 10000 ; cnt && mb0; cnt--) {
238 udelay(5);
239 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
240 barrier();
241 }
242
243 /* Wait for soft-reset to complete. */
244 for (cnt = 0; cnt < 30000; cnt++) {
245 if ((RD_REG_DWORD(&reg->ctrl_status) &
246 CSRX_ISP_SOFT_RESET) == 0)
247 break;
248
249 udelay(10);
250 }
251 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
252 RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
253
254 for (cnt = 30000; RD_REG_WORD(&reg->mailbox0) != 0 &&
255 rval == QLA_SUCCESS; cnt--) {
256 if (cnt)
257 udelay(100);
258 else
259 rval = QLA_FUNCTION_TIMEOUT;
260 }
261
262 return rval;
263}
264
c5722708 265static int
7b867cf7 266qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint16_t *ram,
e18e963b 267 uint32_t ram_words, void **nxt)
c5722708
AV		 268{
269 int rval;
270 uint32_t cnt, stat, timer, words, idx;
271 uint16_t mb0;
272 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
273 dma_addr_t dump_dma = ha->gid_list_dma;
274 uint16_t *dump = (uint16_t *)ha->gid_list;
275
276 rval = QLA_SUCCESS;
277 mb0 = 0;
278
279 WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED);
280 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
281
642ef983 282 words = qla2x00_gid_list_size(ha) / 2;
c5722708
AV		 283 for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS;
284 cnt += words, addr += words) {
285 if (cnt + words > ram_words)
286 words = ram_words - cnt;
287
288 WRT_MAILBOX_REG(ha, reg, 1, LSW(addr));
289 WRT_MAILBOX_REG(ha, reg, 8, MSW(addr));
290
291 WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma));
292 WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma));
293 WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma)));
294 WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma)));
295
296 WRT_MAILBOX_REG(ha, reg, 4, words);
297 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
298
299 for (timer = 6000000; timer; timer--) {
300 /* Check for pending interrupts. */
301 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
302 if (stat & HSR_RISC_INT) {
303 stat &= 0xff;
304
305 if (stat == 0x1 || stat == 0x2) {
306 set_bit(MBX_INTERRUPT,
307 &ha->mbx_cmd_flags);
308
309 mb0 = RD_MAILBOX_REG(ha, reg, 0);
310
311 /* Release mailbox registers. */
312 WRT_REG_WORD(&reg->semaphore, 0);
313 WRT_REG_WORD(&reg->hccr,
314 HCCR_CLR_RISC_INT);
315 RD_REG_WORD(&reg->hccr);
316 break;
317 } else if (stat == 0x10 || stat == 0x11) {
318 set_bit(MBX_INTERRUPT,
319 &ha->mbx_cmd_flags);
320
321 mb0 = RD_MAILBOX_REG(ha, reg, 0);
322
323 WRT_REG_WORD(&reg->hccr,
324 HCCR_CLR_RISC_INT);
325 RD_REG_WORD(&reg->hccr);
326 break;
327 }
328
329 /* clear this intr; it wasn't a mailbox intr */
330 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
331 RD_REG_WORD(&reg->hccr);
332 }
333 udelay(5);
334 }
335
336 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
337 rval = mb0 & MBS_MASK;
338 for (idx = 0; idx < words; idx++)
339 ram[cnt + idx] = swab16(dump[idx]);
340 } else {
341 rval = QLA_FUNCTION_FAILED;
342 }
343 }
344
345 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
346 return rval;
347}
348
c81d04c9
AV		 349static inline void
350qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
351 uint16_t *buf)
352{
353 uint16_t __iomem *dmp_reg = &reg->u.isp2300.fb_cmd;
354
355 while (count--)
356 *buf++ = htons(RD_REG_WORD(dmp_reg++));
357}
358
bb99de67
AV		 359static inline void *
360qla24xx_copy_eft(struct qla_hw_data *ha, void *ptr)
361{
362 if (!ha->eft)
363 return ptr;
364
365 memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size));
366 return ptr + ntohl(ha->fw_dump->eft_size);
367}
368
369static inline void *
370qla25xx_copy_fce(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
371{
372 uint32_t cnt;
373 uint32_t *iter_reg;
374 struct qla2xxx_fce_chain *fcec = ptr;
375
376 if (!ha->fce)
377 return ptr;
378
379 *last_chain = &fcec->type;
380 fcec->type = __constant_htonl(DUMP_CHAIN_FCE);
381 fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) +
382 fce_calc_size(ha->fce_bufs));
383 fcec->size = htonl(fce_calc_size(ha->fce_bufs));
384 fcec->addr_l = htonl(LSD(ha->fce_dma));
385 fcec->addr_h = htonl(MSD(ha->fce_dma));
386
387 iter_reg = fcec->eregs;
388 for (cnt = 0; cnt < 8; cnt++)
389 *iter_reg++ = htonl(ha->fce_mb[cnt]);
390
391 memcpy(iter_reg, ha->fce, ntohl(fcec->size));
392
3cb0a67d 393 return (char *)iter_reg + ntohl(fcec->size);
bb99de67
AV		 394}
395
2d70c103
NB		 396static inline void *
397qla2xxx_copy_atioqueues(struct qla_hw_data *ha, void *ptr,
398 uint32_t **last_chain)
399{
400 struct qla2xxx_mqueue_chain *q;
401 struct qla2xxx_mqueue_header *qh;
402 uint32_t num_queues;
403 int que;
404 struct {
405 int length;
406 void *ring;
407 } aq, *aqp;
408
00876ae8 409 if (!ha->tgt.atio_ring)
2d70c103
NB		 410 return ptr;
411
412 num_queues = 1;
413 aqp = &aq;
414 aqp->length = ha->tgt.atio_q_length;
415 aqp->ring = ha->tgt.atio_ring;
416
417 for (que = 0; que < num_queues; que++) {
418 /* aqp = ha->atio_q_map[que]; */
419 q = ptr;
420 *last_chain = &q->type;
421 q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
422 q->chain_size = htonl(
423 sizeof(struct qla2xxx_mqueue_chain) +
424 sizeof(struct qla2xxx_mqueue_header) +
425 (aqp->length * sizeof(request_t)));
426 ptr += sizeof(struct qla2xxx_mqueue_chain);
427
428 /* Add header. */
429 qh = ptr;
430 qh->queue = __constant_htonl(TYPE_ATIO_QUEUE);
431 qh->number = htonl(que);
432 qh->size = htonl(aqp->length * sizeof(request_t));
433 ptr += sizeof(struct qla2xxx_mqueue_header);
434
435 /* Add data. */
436 memcpy(ptr, aqp->ring, aqp->length * sizeof(request_t));
437
438 ptr += aqp->length * sizeof(request_t);
439 }
440
441 return ptr;
442}
443
050c9bb1
GM		 444static inline void *
445qla25xx_copy_mqueues(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
446{
447 struct qla2xxx_mqueue_chain *q;
448 struct qla2xxx_mqueue_header *qh;
449 struct req_que *req;
450 struct rsp_que *rsp;
451 int que;
452
453 if (!ha->mqenable)
454 return ptr;
455
456 /* Request queues */
457 for (que = 1; que < ha->max_req_queues; que++) {
458 req = ha->req_q_map[que];
459 if (!req)
460 break;
461
462 /* Add chain. */
463 q = ptr;
464 *last_chain = &q->type;
465 q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
466 q->chain_size = htonl(
467 sizeof(struct qla2xxx_mqueue_chain) +
468 sizeof(struct qla2xxx_mqueue_header) +
469 (req->length * sizeof(request_t)));
470 ptr += sizeof(struct qla2xxx_mqueue_chain);
471
472 /* Add header. */
473 qh = ptr;
474 qh->queue = __constant_htonl(TYPE_REQUEST_QUEUE);
475 qh->number = htonl(que);
476 qh->size = htonl(req->length * sizeof(request_t));
477 ptr += sizeof(struct qla2xxx_mqueue_header);
478
479 /* Add data. */
480 memcpy(ptr, req->ring, req->length * sizeof(request_t));
481 ptr += req->length * sizeof(request_t);
482 }
483
484 /* Response queues */
485 for (que = 1; que < ha->max_rsp_queues; que++) {
486 rsp = ha->rsp_q_map[que];
487 if (!rsp)
488 break;
489
490 /* Add chain. */
491 q = ptr;
492 *last_chain = &q->type;
493 q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
494 q->chain_size = htonl(
495 sizeof(struct qla2xxx_mqueue_chain) +
496 sizeof(struct qla2xxx_mqueue_header) +
497 (rsp->length * sizeof(response_t)));
498 ptr += sizeof(struct qla2xxx_mqueue_chain);
499
500 /* Add header. */
501 qh = ptr;
502 qh->queue = __constant_htonl(TYPE_RESPONSE_QUEUE);
503 qh->number = htonl(que);
504 qh->size = htonl(rsp->length * sizeof(response_t));
505 ptr += sizeof(struct qla2xxx_mqueue_header);
506
507 /* Add data. */
508 memcpy(ptr, rsp->ring, rsp->length * sizeof(response_t));
509 ptr += rsp->length * sizeof(response_t);
510 }
511
512 return ptr;
513}
514
d63ab533
AV		 515static inline void *
516qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
517{
518 uint32_t cnt, que_idx;
2afa19a9 519 uint8_t que_cnt;
d63ab533
AV		 520 struct qla2xxx_mq_chain *mq = ptr;
521 struct device_reg_25xxmq __iomem *reg;
522
6246b8a1 523 if (!ha->mqenable || IS_QLA83XX(ha))
d63ab533
AV		 524 return ptr;
525
526 mq = ptr;
527 *last_chain = &mq->type;
528 mq->type = __constant_htonl(DUMP_CHAIN_MQ);
529 mq->chain_size = __constant_htonl(sizeof(struct qla2xxx_mq_chain));
530
2afa19a9
AC		 531 que_cnt = ha->max_req_queues > ha->max_rsp_queues ?
532 ha->max_req_queues : ha->max_rsp_queues;
d63ab533
AV		 533 mq->count = htonl(que_cnt);
534 for (cnt = 0; cnt < que_cnt; cnt++) {
fa492630
SK		 535 reg = (struct device_reg_25xxmq __iomem *)
536 (ha->mqiobase + cnt * QLA_QUE_PAGE);
d63ab533
AV		 537 que_idx = cnt * 4;
538 mq->qregs[que_idx] = htonl(RD_REG_DWORD(&reg->req_q_in));
539 mq->qregs[que_idx+1] = htonl(RD_REG_DWORD(&reg->req_q_out));
540 mq->qregs[que_idx+2] = htonl(RD_REG_DWORD(&reg->rsp_q_in));
541 mq->qregs[que_idx+3] = htonl(RD_REG_DWORD(&reg->rsp_q_out));
542 }
543
544 return ptr + sizeof(struct qla2xxx_mq_chain);
545}
546
08de2844 547void
3420d36c
AV		 548qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval)
549{
550 struct qla_hw_data *ha = vha->hw;
551
552 if (rval != QLA_SUCCESS) {
7c3df132
SK		 553 ql_log(ql_log_warn, vha, 0xd000,
554 "Failed to dump firmware (%x).\n", rval);
3420d36c
AV		 555 ha->fw_dumped = 0;
556 } else {
7c3df132 557 ql_log(ql_log_info, vha, 0xd001,
3420d36c
AV		 558 "Firmware dump saved to temp buffer (%ld/%p).\n",
559 vha->host_no, ha->fw_dump);
560 ha->fw_dumped = 1;
561 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
562 }
563}
564
1da177e4
LT		 565/**
566 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
567 * @ha: HA context
568 * @hardware_locked: Called with the hardware_lock
569 */
570void
7b867cf7 571qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1da177e4
LT		 572{
573 int rval;
c5722708 574 uint32_t cnt;
7b867cf7 575 struct qla_hw_data *ha = vha->hw;
3d71644c 576 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 577 uint16_t __iomem *dmp_reg;
578 unsigned long flags;
579 struct qla2300_fw_dump *fw;
c5722708 580 void *nxt;
73208dfd 581 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 582
1da177e4
LT		 583 flags = 0;
584
585 if (!hardware_locked)
586 spin_lock_irqsave(&ha->hardware_lock, flags);
587
d4e3e04d 588 if (!ha->fw_dump) {
7c3df132
SK		 589 ql_log(ql_log_warn, vha, 0xd002,
590 "No buffer available for dump.\n");
1da177e4
LT		 591 goto qla2300_fw_dump_failed;
592 }
593
d4e3e04d 594 if (ha->fw_dumped) {
7c3df132
SK		 595 ql_log(ql_log_warn, vha, 0xd003,
596 "Firmware has been previously dumped (%p) "
597 "-- ignoring request.\n",
598 ha->fw_dump);
1da177e4
LT		 599 goto qla2300_fw_dump_failed;
600 }
a7a167bf
AV		 601 fw = &ha->fw_dump->isp.isp23;
602 qla2xxx_prep_dump(ha, ha->fw_dump);
1da177e4
LT		 603
604 rval = QLA_SUCCESS;
a7a167bf 605 fw->hccr = htons(RD_REG_WORD(&reg->hccr));
1da177e4
LT		 606
607 /* Pause RISC. */
fa2a1ce5 608 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1da177e4
LT		 609 if (IS_QLA2300(ha)) {
610 for (cnt = 30000;
611 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
612 rval == QLA_SUCCESS; cnt--) {
613 if (cnt)
614 udelay(100);
615 else
616 rval = QLA_FUNCTION_TIMEOUT;
617 }
618 } else {
619 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
620 udelay(10);
621 }
622
623 if (rval == QLA_SUCCESS) {
c81d04c9 624 dmp_reg = &reg->flash_address;
fa2a1ce5 625 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
a7a167bf 626 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 627
c81d04c9 628 dmp_reg = &reg->u.isp2300.req_q_in;
fa2a1ce5 629 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
a7a167bf 630 fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 631
c81d04c9 632 dmp_reg = &reg->u.isp2300.mailbox0;
fa2a1ce5 633 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
a7a167bf 634 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4
LT		 635
636 WRT_REG_WORD(&reg->ctrl_status, 0x40);
c81d04c9 637 qla2xxx_read_window(reg, 32, fw->resp_dma_reg);
1da177e4
LT		 638
639 WRT_REG_WORD(&reg->ctrl_status, 0x50);
c81d04c9 640 qla2xxx_read_window(reg, 48, fw->dma_reg);
1da177e4
LT		 641
642 WRT_REG_WORD(&reg->ctrl_status, 0x00);
c81d04c9 643 dmp_reg = &reg->risc_hw;
fa2a1ce5 644 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
a7a167bf 645 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 646
fa2a1ce5 647 WRT_REG_WORD(&reg->pcr, 0x2000);
c81d04c9 648 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
1da177e4 649
fa2a1ce5 650 WRT_REG_WORD(&reg->pcr, 0x2200);
c81d04c9 651 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
1da177e4 652
fa2a1ce5 653 WRT_REG_WORD(&reg->pcr, 0x2400);
c81d04c9 654 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
1da177e4 655
fa2a1ce5 656 WRT_REG_WORD(&reg->pcr, 0x2600);
c81d04c9 657 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
1da177e4 658
fa2a1ce5 659 WRT_REG_WORD(&reg->pcr, 0x2800);
c81d04c9 660 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
1da177e4 661
fa2a1ce5 662 WRT_REG_WORD(&reg->pcr, 0x2A00);
c81d04c9 663 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
1da177e4 664
fa2a1ce5 665 WRT_REG_WORD(&reg->pcr, 0x2C00);
c81d04c9 666 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
1da177e4 667
fa2a1ce5 668 WRT_REG_WORD(&reg->pcr, 0x2E00);
c81d04c9 669 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
1da177e4 670
fa2a1ce5 671 WRT_REG_WORD(&reg->ctrl_status, 0x10);
c81d04c9 672 qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg);
1da177e4 673
fa2a1ce5 674 WRT_REG_WORD(&reg->ctrl_status, 0x20);
c81d04c9 675 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
1da177e4 676
fa2a1ce5 677 WRT_REG_WORD(&reg->ctrl_status, 0x30);
c81d04c9 678 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
1da177e4
LT		 679
680 /* Reset RISC. */
681 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
682 for (cnt = 0; cnt < 30000; cnt++) {
683 if ((RD_REG_WORD(&reg->ctrl_status) &
684 CSR_ISP_SOFT_RESET) == 0)
685 break;
686
687 udelay(10);
688 }
689 }
690
691 if (!IS_QLA2300(ha)) {
692 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
693 rval == QLA_SUCCESS; cnt--) {
694 if (cnt)
695 udelay(100);
696 else
697 rval = QLA_FUNCTION_TIMEOUT;
698 }
699 }
700
c5722708
AV		 701 /* Get RISC SRAM. */
702 if (rval == QLA_SUCCESS)
703 rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram,
704 sizeof(fw->risc_ram) / 2, &nxt);
1da177e4 705
c5722708
AV		 706 /* Get stack SRAM. */
707 if (rval == QLA_SUCCESS)
708 rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram,
709 sizeof(fw->stack_ram) / 2, &nxt);
1da177e4 710
c5722708
AV		 711 /* Get data SRAM. */
712 if (rval == QLA_SUCCESS)
713 rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram,
714 ha->fw_memory_size - 0x11000 + 1, &nxt);
1da177e4 715
a7a167bf 716 if (rval == QLA_SUCCESS)
73208dfd 717 qla2xxx_copy_queues(ha, nxt);
a7a167bf 718
3420d36c 719 qla2xxx_dump_post_process(base_vha, rval);
1da177e4
LT		 720
721qla2300_fw_dump_failed:
722 if (!hardware_locked)
723 spin_unlock_irqrestore(&ha->hardware_lock, flags);
724}
725
1da177e4
LT		 726/**
727 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
728 * @ha: HA context
729 * @hardware_locked: Called with the hardware_lock
730 */
731void
7b867cf7 732qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1da177e4
LT		 733{
734 int rval;
735 uint32_t cnt, timer;
736 uint16_t risc_address;
737 uint16_t mb0, mb2;
7b867cf7 738 struct qla_hw_data *ha = vha->hw;
3d71644c 739 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 740 uint16_t __iomem *dmp_reg;
741 unsigned long flags;
742 struct qla2100_fw_dump *fw;
73208dfd 743 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 744
745 risc_address = 0;
746 mb0 = mb2 = 0;
747 flags = 0;
748
749 if (!hardware_locked)
750 spin_lock_irqsave(&ha->hardware_lock, flags);
751
d4e3e04d 752 if (!ha->fw_dump) {
7c3df132
SK		 753 ql_log(ql_log_warn, vha, 0xd004,
754 "No buffer available for dump.\n");
1da177e4
LT		 755 goto qla2100_fw_dump_failed;
756 }
757
d4e3e04d 758 if (ha->fw_dumped) {
7c3df132
SK		 759 ql_log(ql_log_warn, vha, 0xd005,
760 "Firmware has been previously dumped (%p) "
761 "-- ignoring request.\n",
762 ha->fw_dump);
1da177e4
LT		 763 goto qla2100_fw_dump_failed;
764 }
a7a167bf
AV		 765 fw = &ha->fw_dump->isp.isp21;
766 qla2xxx_prep_dump(ha, ha->fw_dump);
1da177e4
LT		 767
768 rval = QLA_SUCCESS;
a7a167bf 769 fw->hccr = htons(RD_REG_WORD(&reg->hccr));
1da177e4
LT		 770
771 /* Pause RISC. */
fa2a1ce5 772 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1da177e4
LT		 773 for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
774 rval == QLA_SUCCESS; cnt--) {
775 if (cnt)
776 udelay(100);
777 else
778 rval = QLA_FUNCTION_TIMEOUT;
779 }
780 if (rval == QLA_SUCCESS) {
c81d04c9 781 dmp_reg = &reg->flash_address;
fa2a1ce5 782 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
a7a167bf 783 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 784
c81d04c9 785 dmp_reg = &reg->u.isp2100.mailbox0;
1da177e4 786 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
c81d04c9
AV		 787 if (cnt == 8)
788 dmp_reg = &reg->u_end.isp2200.mailbox8;
789
a7a167bf 790 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4
LT		 791 }
792
c81d04c9 793 dmp_reg = &reg->u.isp2100.unused_2[0];
fa2a1ce5 794 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
a7a167bf 795 fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4
LT		 796
797 WRT_REG_WORD(&reg->ctrl_status, 0x00);
c81d04c9 798 dmp_reg = &reg->risc_hw;
fa2a1ce5 799 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
a7a167bf 800 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 801
fa2a1ce5 802 WRT_REG_WORD(&reg->pcr, 0x2000);
c81d04c9 803 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
1da177e4 804
fa2a1ce5 805 WRT_REG_WORD(&reg->pcr, 0x2100);
c81d04c9 806 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
1da177e4 807
fa2a1ce5 808 WRT_REG_WORD(&reg->pcr, 0x2200);
c81d04c9 809 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
1da177e4 810
fa2a1ce5 811 WRT_REG_WORD(&reg->pcr, 0x2300);
c81d04c9 812 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
1da177e4 813
fa2a1ce5 814 WRT_REG_WORD(&reg->pcr, 0x2400);
c81d04c9 815 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
1da177e4 816
fa2a1ce5 817 WRT_REG_WORD(&reg->pcr, 0x2500);
c81d04c9 818 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
1da177e4 819
fa2a1ce5 820 WRT_REG_WORD(&reg->pcr, 0x2600);
c81d04c9 821 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
1da177e4 822
fa2a1ce5 823 WRT_REG_WORD(&reg->pcr, 0x2700);
c81d04c9 824 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
1da177e4 825
fa2a1ce5 826 WRT_REG_WORD(&reg->ctrl_status, 0x10);
c81d04c9 827 qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg);
1da177e4 828
fa2a1ce5 829 WRT_REG_WORD(&reg->ctrl_status, 0x20);
c81d04c9 830 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
1da177e4 831
fa2a1ce5 832 WRT_REG_WORD(&reg->ctrl_status, 0x30);
c81d04c9 833 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
1da177e4
LT		 834
835 /* Reset the ISP. */
836 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
837 }
838
839 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
840 rval == QLA_SUCCESS; cnt--) {
841 if (cnt)
842 udelay(100);
843 else
844 rval = QLA_FUNCTION_TIMEOUT;
845 }
846
847 /* Pause RISC. */
848 if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) &&
849 (RD_REG_WORD(&reg->mctr) & (BIT_1 | BIT_0)) != 0))) {
850
fa2a1ce5 851 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1da177e4
LT		 852 for (cnt = 30000;
853 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
854 rval == QLA_SUCCESS; cnt--) {
855 if (cnt)
856 udelay(100);
857 else
858 rval = QLA_FUNCTION_TIMEOUT;
859 }
860 if (rval == QLA_SUCCESS) {
861 /* Set memory configuration and timing. */
862 if (IS_QLA2100(ha))
863 WRT_REG_WORD(&reg->mctr, 0xf1);
864 else
865 WRT_REG_WORD(&reg->mctr, 0xf2);
866 RD_REG_WORD(&reg->mctr); /* PCI Posting. */
867
868 /* Release RISC. */
869 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
870 }
871 }
872
873 if (rval == QLA_SUCCESS) {
874 /* Get RISC SRAM. */
875 risc_address = 0x1000;
876 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
877 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
878 }
879 for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
880 cnt++, risc_address++) {
881 WRT_MAILBOX_REG(ha, reg, 1, risc_address);
882 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
883
884 for (timer = 6000000; timer != 0; timer--) {
885 /* Check for pending interrupts. */
886 if (RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) {
887 if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
888 set_bit(MBX_INTERRUPT,
889 &ha->mbx_cmd_flags);
890
891 mb0 = RD_MAILBOX_REG(ha, reg, 0);
892 mb2 = RD_MAILBOX_REG(ha, reg, 2);
893
894 WRT_REG_WORD(&reg->semaphore, 0);
895 WRT_REG_WORD(&reg->hccr,
896 HCCR_CLR_RISC_INT);
897 RD_REG_WORD(&reg->hccr);
898 break;
899 }
900 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
901 RD_REG_WORD(&reg->hccr);
902 }
903 udelay(5);
904 }
905
906 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
907 rval = mb0 & MBS_MASK;
a7a167bf 908 fw->risc_ram[cnt] = htons(mb2);
1da177e4
LT		 909 } else {
910 rval = QLA_FUNCTION_FAILED;
911 }
912 }
913
a7a167bf 914 if (rval == QLA_SUCCESS)
73208dfd 915 qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]);
a7a167bf 916
3420d36c 917 qla2xxx_dump_post_process(base_vha, rval);
1da177e4
LT		 918
919qla2100_fw_dump_failed:
920 if (!hardware_locked)
921 spin_unlock_irqrestore(&ha->hardware_lock, flags);
922}
923
6d9b61ed 924void
7b867cf7 925qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
6d9b61ed
AV		 926{
927 int rval;
c3a2f0df 928 uint32_t cnt;
6d9b61ed 929 uint32_t risc_address;
7b867cf7 930 struct qla_hw_data *ha = vha->hw;
6d9b61ed
AV		 931 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
932 uint32_t __iomem *dmp_reg;
933 uint32_t *iter_reg;
934 uint16_t __iomem *mbx_reg;
935 unsigned long flags;
936 struct qla24xx_fw_dump *fw;
937 uint32_t ext_mem_cnt;
c3a2f0df 938 void *nxt;
2d70c103
NB		 939 void *nxt_chain;
940 uint32_t *last_chain = NULL;
73208dfd 941 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
6d9b61ed 942
a9083016
GM		 943 if (IS_QLA82XX(ha))
944 return;
945
6d9b61ed 946 risc_address = ext_mem_cnt = 0;
6d9b61ed
AV		 947 flags = 0;
948
949 if (!hardware_locked)
950 spin_lock_irqsave(&ha->hardware_lock, flags);
951
d4e3e04d 952 if (!ha->fw_dump) {
7c3df132
SK		 953 ql_log(ql_log_warn, vha, 0xd006,
954 "No buffer available for dump.\n");
6d9b61ed
AV		 955 goto qla24xx_fw_dump_failed;
956 }
957
958 if (ha->fw_dumped) {
7c3df132
SK		 959 ql_log(ql_log_warn, vha, 0xd007,
960 "Firmware has been previously dumped (%p) "
961 "-- ignoring request.\n",
962 ha->fw_dump);
6d9b61ed
AV		 963 goto qla24xx_fw_dump_failed;
964 }
a7a167bf
AV		 965 fw = &ha->fw_dump->isp.isp24;
966 qla2xxx_prep_dump(ha, ha->fw_dump);
6d9b61ed 967
a7a167bf 968 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
6d9b61ed
AV		 969
970 /* Pause RISC. */
c81d04c9
AV		 971 rval = qla24xx_pause_risc(reg);
972 if (rval != QLA_SUCCESS)
973 goto qla24xx_fw_dump_failed_0;
974
975 /* Host interface registers. */
976 dmp_reg = &reg->flash_addr;
977 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
978 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
979
980 /* Disable interrupts. */
981 WRT_REG_DWORD(&reg->ictrl, 0);
982 RD_REG_DWORD(&reg->ictrl);
983
984 /* Shadow registers. */
985 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
986 RD_REG_DWORD(&reg->iobase_addr);
987 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
988 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
989
990 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
991 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
992
993 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
994 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
995
996 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
997 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
998
999 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1000 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1001
1002 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1003 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1004
1005 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1006 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1007
1008 /* Mailbox registers. */
1009 mbx_reg = &reg->mailbox0;
1010 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1011 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1012
1013 /* Transfer sequence registers. */
1014 iter_reg = fw->xseq_gp_reg;
1015 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1016 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1017 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1018 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1019 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1020 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1021 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1022 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1023
1024 qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg);
1025 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1026
1027 /* Receive sequence registers. */
1028 iter_reg = fw->rseq_gp_reg;
1029 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1030 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1031 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1032 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1033 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1034 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1035 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1036 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1037
1038 qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg);
1039 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1040 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1041
1042 /* Command DMA registers. */
1043 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1044
1045 /* Queues. */
1046 iter_reg = fw->req0_dma_reg;
1047 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1048 dmp_reg = &reg->iobase_q;
1049 for (cnt = 0; cnt < 7; cnt++)
1050 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1051
1052 iter_reg = fw->resp0_dma_reg;
1053 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1054 dmp_reg = &reg->iobase_q;
1055 for (cnt = 0; cnt < 7; cnt++)
1056 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1057
1058 iter_reg = fw->req1_dma_reg;
1059 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1060 dmp_reg = &reg->iobase_q;
1061 for (cnt = 0; cnt < 7; cnt++)
1062 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1063
1064 /* Transmit DMA registers. */
1065 iter_reg = fw->xmt0_dma_reg;
1066 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1067 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1068
1069 iter_reg = fw->xmt1_dma_reg;
1070 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1071 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1072
1073 iter_reg = fw->xmt2_dma_reg;
1074 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1075 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1076
1077 iter_reg = fw->xmt3_dma_reg;
1078 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1079 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1080
1081 iter_reg = fw->xmt4_dma_reg;
1082 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1083 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1084
1085 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1086
1087 /* Receive DMA registers. */
1088 iter_reg = fw->rcvt0_data_dma_reg;
1089 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1090 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1091
1092 iter_reg = fw->rcvt1_data_dma_reg;
1093 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1094 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1095
1096 /* RISC registers. */
1097 iter_reg = fw->risc_gp_reg;
1098 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1099 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1100 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1101 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1102 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1103 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1104 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1105 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1106
1107 /* Local memory controller registers. */
1108 iter_reg = fw->lmc_reg;
1109 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1110 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1111 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1112 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1113 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1114 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1115 qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1116
1117 /* Fibre Protocol Module registers. */
1118 iter_reg = fw->fpm_hdw_reg;
1119 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1120 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1121 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1122 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1123 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1124 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1125 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1126 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1127 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1128 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1129 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1130 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1131
1132 /* Frame Buffer registers. */
1133 iter_reg = fw->fb_hdw_reg;
1134 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1135 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1136 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1137 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1138 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1139 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1140 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1141 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1142 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1143 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1144 qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1145
1146 rval = qla24xx_soft_reset(ha);
1147 if (rval != QLA_SUCCESS)
1148 goto qla24xx_fw_dump_failed_0;
1149
1150 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
c5722708 1151 &nxt);
c81d04c9
AV		 1152 if (rval != QLA_SUCCESS)
1153 goto qla24xx_fw_dump_failed_0;
1154
73208dfd 1155 nxt = qla2xxx_copy_queues(ha, nxt);
bb99de67
AV		 1156
1157 qla24xx_copy_eft(ha, nxt);
c81d04c9 1158
2d70c103
NB		 1159 nxt_chain = (void *)ha->fw_dump + ha->chain_offset;
1160 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
1161 if (last_chain) {
1162 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1163 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1164 }
1165
1166 /* Adjust valid length. */
1167 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
1168
c81d04c9 1169qla24xx_fw_dump_failed_0:
3420d36c 1170 qla2xxx_dump_post_process(base_vha, rval);
6d9b61ed 1171
c3a2f0df
AV		 1172qla24xx_fw_dump_failed:
1173 if (!hardware_locked)
1174 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1175}
6d9b61ed 1176
c3a2f0df 1177void
7b867cf7 1178qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
c3a2f0df
AV		 1179{
1180 int rval;
1181 uint32_t cnt;
1182 uint32_t risc_address;
7b867cf7 1183 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 1184 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1185 uint32_t __iomem *dmp_reg;
1186 uint32_t *iter_reg;
1187 uint16_t __iomem *mbx_reg;
1188 unsigned long flags;
1189 struct qla25xx_fw_dump *fw;
1190 uint32_t ext_mem_cnt;
d63ab533 1191 void *nxt, *nxt_chain;
bb99de67 1192 uint32_t *last_chain = NULL;
73208dfd 1193 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
6d9b61ed 1194
c3a2f0df
AV		 1195 risc_address = ext_mem_cnt = 0;
1196 flags = 0;
6d9b61ed 1197
c3a2f0df
AV		 1198 if (!hardware_locked)
1199 spin_lock_irqsave(&ha->hardware_lock, flags);
6d9b61ed 1200
c3a2f0df 1201 if (!ha->fw_dump) {
7c3df132
SK		 1202 ql_log(ql_log_warn, vha, 0xd008,
1203 "No buffer available for dump.\n");
c3a2f0df
AV		 1204 goto qla25xx_fw_dump_failed;
1205 }
6d9b61ed 1206
c3a2f0df 1207 if (ha->fw_dumped) {
7c3df132
SK		 1208 ql_log(ql_log_warn, vha, 0xd009,
1209 "Firmware has been previously dumped (%p) "
1210 "-- ignoring request.\n",
1211 ha->fw_dump);
c3a2f0df
AV		 1212 goto qla25xx_fw_dump_failed;
1213 }
1214 fw = &ha->fw_dump->isp.isp25;
1215 qla2xxx_prep_dump(ha, ha->fw_dump);
b5836927 1216 ha->fw_dump->version = __constant_htonl(2);
6d9b61ed 1217
c3a2f0df 1218 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
6d9b61ed 1219
c3a2f0df 1220 /* Pause RISC. */
c81d04c9
AV		 1221 rval = qla24xx_pause_risc(reg);
1222 if (rval != QLA_SUCCESS)
1223 goto qla25xx_fw_dump_failed_0;
1224
b5836927
AV		 1225 /* Host/Risc registers. */
1226 iter_reg = fw->host_risc_reg;
1227 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1228 qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1229
1230 /* PCIe registers. */
1231 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1232 RD_REG_DWORD(&reg->iobase_addr);
1233 WRT_REG_DWORD(&reg->iobase_window, 0x01);
1234 dmp_reg = &reg->iobase_c4;
1235 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1236 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1237 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1238 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
73208dfd 1239
b5836927
AV		 1240 WRT_REG_DWORD(&reg->iobase_window, 0x00);
1241 RD_REG_DWORD(&reg->iobase_window);
1242
c81d04c9
AV		 1243 /* Host interface registers. */
1244 dmp_reg = &reg->flash_addr;
1245 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1246 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1247
1248 /* Disable interrupts. */
1249 WRT_REG_DWORD(&reg->ictrl, 0);
1250 RD_REG_DWORD(&reg->ictrl);
1251
1252 /* Shadow registers. */
1253 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1254 RD_REG_DWORD(&reg->iobase_addr);
1255 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1256 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1257
1258 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1259 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1260
1261 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1262 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1263
1264 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1265 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1266
1267 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1268 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1269
1270 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1271 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1272
1273 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1274 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1275
1276 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1277 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1278
1279 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1280 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1281
1282 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1283 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1284
1285 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1286 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1287
1288 /* RISC I/O register. */
1289 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1290 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1291
1292 /* Mailbox registers. */
1293 mbx_reg = &reg->mailbox0;
1294 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1295 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1296
1297 /* Transfer sequence registers. */
1298 iter_reg = fw->xseq_gp_reg;
1299 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1300 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1301 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1302 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1303 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1304 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1305 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1306 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1307
1308 iter_reg = fw->xseq_0_reg;
1309 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1310 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1311 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1312
1313 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1314
1315 /* Receive sequence registers. */
1316 iter_reg = fw->rseq_gp_reg;
1317 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1318 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1319 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1320 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1321 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1322 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1323 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1324 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1325
1326 iter_reg = fw->rseq_0_reg;
1327 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1328 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1329
1330 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1331 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1332
1333 /* Auxiliary sequence registers. */
1334 iter_reg = fw->aseq_gp_reg;
1335 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1336 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1337 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1338 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1339 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1340 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1341 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1342 qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1343
1344 iter_reg = fw->aseq_0_reg;
1345 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1346 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1347
1348 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1349 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1350
1351 /* Command DMA registers. */
1352 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1353
1354 /* Queues. */
1355 iter_reg = fw->req0_dma_reg;
1356 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1357 dmp_reg = &reg->iobase_q;
1358 for (cnt = 0; cnt < 7; cnt++)
1359 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1360
1361 iter_reg = fw->resp0_dma_reg;
1362 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1363 dmp_reg = &reg->iobase_q;
1364 for (cnt = 0; cnt < 7; cnt++)
1365 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1366
1367 iter_reg = fw->req1_dma_reg;
1368 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1369 dmp_reg = &reg->iobase_q;
1370 for (cnt = 0; cnt < 7; cnt++)
1371 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1372
1373 /* Transmit DMA registers. */
1374 iter_reg = fw->xmt0_dma_reg;
1375 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1376 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1377
1378 iter_reg = fw->xmt1_dma_reg;
1379 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1380 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1381
1382 iter_reg = fw->xmt2_dma_reg;
1383 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1384 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1385
1386 iter_reg = fw->xmt3_dma_reg;
1387 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1388 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1389
1390 iter_reg = fw->xmt4_dma_reg;
1391 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1392 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1393
1394 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1395
1396 /* Receive DMA registers. */
1397 iter_reg = fw->rcvt0_data_dma_reg;
1398 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1399 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1400
1401 iter_reg = fw->rcvt1_data_dma_reg;
1402 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1403 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1404
1405 /* RISC registers. */
1406 iter_reg = fw->risc_gp_reg;
1407 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1408 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1409 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1410 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1411 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1412 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1413 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1414 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1415
1416 /* Local memory controller registers. */
1417 iter_reg = fw->lmc_reg;
1418 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1419 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1420 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1421 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1422 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1423 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1424 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1425 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1426
1427 /* Fibre Protocol Module registers. */
1428 iter_reg = fw->fpm_hdw_reg;
1429 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1430 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1431 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1432 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1433 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1434 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1435 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1436 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1437 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1438 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1439 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1440 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1441
1442 /* Frame Buffer registers. */
1443 iter_reg = fw->fb_hdw_reg;
1444 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1445 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1446 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1447 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1448 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1449 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1450 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1451 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1452 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1453 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1454 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1455 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1456
d63ab533
AV		 1457 /* Multi queue registers */
1458 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
1459 &last_chain);
1460
c81d04c9
AV		 1461 rval = qla24xx_soft_reset(ha);
1462 if (rval != QLA_SUCCESS)
1463 goto qla25xx_fw_dump_failed_0;
1464
1465 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
c5722708 1466 &nxt);
c81d04c9
AV		 1467 if (rval != QLA_SUCCESS)
1468 goto qla25xx_fw_dump_failed_0;
1469
73208dfd 1470 nxt = qla2xxx_copy_queues(ha, nxt);
c81d04c9 1471
bb99de67 1472 nxt = qla24xx_copy_eft(ha, nxt);
df613b96 1473
d63ab533 1474 /* Chain entries -- started with MQ. */
050c9bb1
GM		 1475 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
1476 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
2d70c103 1477 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
bb99de67
AV		 1478 if (last_chain) {
1479 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1480 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1481 }
df613b96 1482
050c9bb1
GM		 1483 /* Adjust valid length. */
1484 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
1485
c81d04c9 1486qla25xx_fw_dump_failed_0:
3420d36c 1487 qla2xxx_dump_post_process(base_vha, rval);
6d9b61ed 1488
c3a2f0df 1489qla25xx_fw_dump_failed:
6d9b61ed
AV		 1490 if (!hardware_locked)
1491 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1492}
3a03eb79
AV		 1493
1494void
1495qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1496{
1497 int rval;
1498 uint32_t cnt;
1499 uint32_t risc_address;
1500 struct qla_hw_data *ha = vha->hw;
1501 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1502 uint32_t __iomem *dmp_reg;
1503 uint32_t *iter_reg;
1504 uint16_t __iomem *mbx_reg;
1505 unsigned long flags;
1506 struct qla81xx_fw_dump *fw;
1507 uint32_t ext_mem_cnt;
1508 void *nxt, *nxt_chain;
1509 uint32_t *last_chain = NULL;
1510 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1511
1512 risc_address = ext_mem_cnt = 0;
1513 flags = 0;
1514
1515 if (!hardware_locked)
1516 spin_lock_irqsave(&ha->hardware_lock, flags);
1517
1518 if (!ha->fw_dump) {
7c3df132
SK		 1519 ql_log(ql_log_warn, vha, 0xd00a,
1520 "No buffer available for dump.\n");
3a03eb79
AV		 1521 goto qla81xx_fw_dump_failed;
1522 }
1523
1524 if (ha->fw_dumped) {
7c3df132
SK		 1525 ql_log(ql_log_warn, vha, 0xd00b,
1526 "Firmware has been previously dumped (%p) "
1527 "-- ignoring request.\n",
1528 ha->fw_dump);
3a03eb79
AV		 1529 goto qla81xx_fw_dump_failed;
1530 }
1531 fw = &ha->fw_dump->isp.isp81;
1532 qla2xxx_prep_dump(ha, ha->fw_dump);
1533
1534 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
1535
1536 /* Pause RISC. */
1537 rval = qla24xx_pause_risc(reg);
1538 if (rval != QLA_SUCCESS)
1539 goto qla81xx_fw_dump_failed_0;
1540
1541 /* Host/Risc registers. */
1542 iter_reg = fw->host_risc_reg;
1543 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1544 qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1545
1546 /* PCIe registers. */
1547 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1548 RD_REG_DWORD(&reg->iobase_addr);
1549 WRT_REG_DWORD(&reg->iobase_window, 0x01);
1550 dmp_reg = &reg->iobase_c4;
1551 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1552 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1553 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1554 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
1555
1556 WRT_REG_DWORD(&reg->iobase_window, 0x00);
1557 RD_REG_DWORD(&reg->iobase_window);
1558
1559 /* Host interface registers. */
1560 dmp_reg = &reg->flash_addr;
1561 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1562 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1563
1564 /* Disable interrupts. */
1565 WRT_REG_DWORD(&reg->ictrl, 0);
1566 RD_REG_DWORD(&reg->ictrl);
1567
1568 /* Shadow registers. */
1569 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1570 RD_REG_DWORD(&reg->iobase_addr);
1571 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1572 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1573
1574 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1575 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1576
1577 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1578 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1579
1580 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1581 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1582
1583 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1584 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1585
1586 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1587 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1588
1589 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1590 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1591
1592 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1593 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1594
1595 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1596 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1597
1598 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1599 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1600
1601 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1602 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1603
1604 /* RISC I/O register. */
1605 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1606 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1607
1608 /* Mailbox registers. */
1609 mbx_reg = &reg->mailbox0;
1610 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1611 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1612
1613 /* Transfer sequence registers. */
1614 iter_reg = fw->xseq_gp_reg;
1615 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1616 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1617 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1618 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1619 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1620 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1621 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1622 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1623
1624 iter_reg = fw->xseq_0_reg;
1625 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1626 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1627 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1628
1629 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1630
1631 /* Receive sequence registers. */
1632 iter_reg = fw->rseq_gp_reg;
1633 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1634 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1635 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1636 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1637 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1638 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1639 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1640 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1641
1642 iter_reg = fw->rseq_0_reg;
1643 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1644 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1645
1646 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1647 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1648
1649 /* Auxiliary sequence registers. */
1650 iter_reg = fw->aseq_gp_reg;
1651 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1652 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1653 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1654 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1655 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1656 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1657 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1658 qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1659
1660 iter_reg = fw->aseq_0_reg;
1661 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1662 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1663
1664 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1665 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1666
1667 /* Command DMA registers. */
1668 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1669
1670 /* Queues. */
1671 iter_reg = fw->req0_dma_reg;
1672 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1673 dmp_reg = &reg->iobase_q;
1674 for (cnt = 0; cnt < 7; cnt++)
1675 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1676
1677 iter_reg = fw->resp0_dma_reg;
1678 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1679 dmp_reg = &reg->iobase_q;
1680 for (cnt = 0; cnt < 7; cnt++)
1681 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1682
1683 iter_reg = fw->req1_dma_reg;
1684 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1685 dmp_reg = &reg->iobase_q;
1686 for (cnt = 0; cnt < 7; cnt++)
1687 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1688
1689 /* Transmit DMA registers. */
1690 iter_reg = fw->xmt0_dma_reg;
1691 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1692 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1693
1694 iter_reg = fw->xmt1_dma_reg;
1695 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1696 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1697
1698 iter_reg = fw->xmt2_dma_reg;
1699 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1700 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1701
1702 iter_reg = fw->xmt3_dma_reg;
1703 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1704 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1705
1706 iter_reg = fw->xmt4_dma_reg;
1707 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1708 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1709
1710 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1711
1712 /* Receive DMA registers. */
1713 iter_reg = fw->rcvt0_data_dma_reg;
1714 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1715 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1716
1717 iter_reg = fw->rcvt1_data_dma_reg;
1718 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1719 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1720
1721 /* RISC registers. */
1722 iter_reg = fw->risc_gp_reg;
1723 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1724 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1725 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1726 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1727 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1728 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1729 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1730 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1731
1732 /* Local memory controller registers. */
1733 iter_reg = fw->lmc_reg;
1734 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1735 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1736 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1737 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1738 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1739 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1740 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1741 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1742
1743 /* Fibre Protocol Module registers. */
1744 iter_reg = fw->fpm_hdw_reg;
1745 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1746 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1747 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1748 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1749 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1750 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1751 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1752 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1753 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1754 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1755 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1756 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1757 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
1758 qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
1759
1760 /* Frame Buffer registers. */
1761 iter_reg = fw->fb_hdw_reg;
1762 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1763 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1764 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1765 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1766 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1767 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1768 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1769 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1770 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1771 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1772 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1773 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
1774 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1775
1776 /* Multi queue registers */
1777 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
1778 &last_chain);
1779
1780 rval = qla24xx_soft_reset(ha);
1781 if (rval != QLA_SUCCESS)
1782 goto qla81xx_fw_dump_failed_0;
1783
1784 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1785 &nxt);
1786 if (rval != QLA_SUCCESS)
1787 goto qla81xx_fw_dump_failed_0;
1788
1789 nxt = qla2xxx_copy_queues(ha, nxt);
1790
1791 nxt = qla24xx_copy_eft(ha, nxt);
1792
1793 /* Chain entries -- started with MQ. */
050c9bb1
GM		 1794 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
1795 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
2d70c103 1796 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
3a03eb79
AV		 1797 if (last_chain) {
1798 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1799 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1800 }
1801
050c9bb1
GM		 1802 /* Adjust valid length. */
1803 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
1804
3a03eb79 1805qla81xx_fw_dump_failed_0:
3420d36c 1806 qla2xxx_dump_post_process(base_vha, rval);
3a03eb79
AV		 1807
1808qla81xx_fw_dump_failed:
1809 if (!hardware_locked)
1810 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1811}
1812
6246b8a1
GM		 1813void
1814qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1815{
1816 int rval;
1817 uint32_t cnt, reg_data;
1818 uint32_t risc_address;
1819 struct qla_hw_data *ha = vha->hw;
1820 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1821 uint32_t __iomem *dmp_reg;
1822 uint32_t *iter_reg;
1823 uint16_t __iomem *mbx_reg;
1824 unsigned long flags;
1825 struct qla83xx_fw_dump *fw;
1826 uint32_t ext_mem_cnt;
1827 void *nxt, *nxt_chain;
1828 uint32_t *last_chain = NULL;
1829 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1830
1831 risc_address = ext_mem_cnt = 0;
1832 flags = 0;
1833
1834 if (!hardware_locked)
1835 spin_lock_irqsave(&ha->hardware_lock, flags);
1836
1837 if (!ha->fw_dump) {
1838 ql_log(ql_log_warn, vha, 0xd00c,
1839 "No buffer available for dump!!!\n");
1840 goto qla83xx_fw_dump_failed;
1841 }
1842
1843 if (ha->fw_dumped) {
1844 ql_log(ql_log_warn, vha, 0xd00d,
1845 "Firmware has been previously dumped (%p) -- ignoring "
1846 "request...\n", ha->fw_dump);
1847 goto qla83xx_fw_dump_failed;
1848 }
1849 fw = &ha->fw_dump->isp.isp83;
1850 qla2xxx_prep_dump(ha, ha->fw_dump);
1851
1852 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
1853
1854 /* Pause RISC. */
1855 rval = qla24xx_pause_risc(reg);
1856 if (rval != QLA_SUCCESS)
1857 goto qla83xx_fw_dump_failed_0;
1858
1859 WRT_REG_DWORD(&reg->iobase_addr, 0x6000);
1860 dmp_reg = &reg->iobase_window;
1861 reg_data = RD_REG_DWORD(dmp_reg);
1862 WRT_REG_DWORD(dmp_reg, 0);
1863
1864 dmp_reg = &reg->unused_4_1[0];
1865 reg_data = RD_REG_DWORD(dmp_reg);
1866 WRT_REG_DWORD(dmp_reg, 0);
1867
1868 WRT_REG_DWORD(&reg->iobase_addr, 0x6010);
1869 dmp_reg = &reg->unused_4_1[2];
1870 reg_data = RD_REG_DWORD(dmp_reg);
1871 WRT_REG_DWORD(dmp_reg, 0);
1872
1873 /* select PCR and disable ecc checking and correction */
1874 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1875 RD_REG_DWORD(&reg->iobase_addr);
1876 WRT_REG_DWORD(&reg->iobase_select, 0x60000000); /* write to F0h = PCR */
1877
1878 /* Host/Risc registers. */
1879 iter_reg = fw->host_risc_reg;
1880 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1881 iter_reg = qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1882 qla24xx_read_window(reg, 0x7040, 16, iter_reg);
1883
1884 /* PCIe registers. */
1885 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1886 RD_REG_DWORD(&reg->iobase_addr);
1887 WRT_REG_DWORD(&reg->iobase_window, 0x01);
1888 dmp_reg = &reg->iobase_c4;
1889 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1890 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1891 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1892 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
1893
1894 WRT_REG_DWORD(&reg->iobase_window, 0x00);
1895 RD_REG_DWORD(&reg->iobase_window);
1896
1897 /* Host interface registers. */
1898 dmp_reg = &reg->flash_addr;
1899 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1900 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1901
1902 /* Disable interrupts. */
1903 WRT_REG_DWORD(&reg->ictrl, 0);
1904 RD_REG_DWORD(&reg->ictrl);
1905
1906 /* Shadow registers. */
1907 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1908 RD_REG_DWORD(&reg->iobase_addr);
1909 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1910 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1911
1912 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1913 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1914
1915 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1916 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1917
1918 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1919 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1920
1921 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1922 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1923
1924 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1925 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1926
1927 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1928 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1929
1930 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1931 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1932
1933 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1934 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1935
1936 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1937 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1938
1939 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1940 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1941
1942 /* RISC I/O register. */
1943 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1944 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1945
1946 /* Mailbox registers. */
1947 mbx_reg = &reg->mailbox0;
1948 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1949 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1950
1951 /* Transfer sequence registers. */
1952 iter_reg = fw->xseq_gp_reg;
1953 iter_reg = qla24xx_read_window(reg, 0xBE00, 16, iter_reg);
1954 iter_reg = qla24xx_read_window(reg, 0xBE10, 16, iter_reg);
1955 iter_reg = qla24xx_read_window(reg, 0xBE20, 16, iter_reg);
1956 iter_reg = qla24xx_read_window(reg, 0xBE30, 16, iter_reg);
1957 iter_reg = qla24xx_read_window(reg, 0xBE40, 16, iter_reg);
1958 iter_reg = qla24xx_read_window(reg, 0xBE50, 16, iter_reg);
1959 iter_reg = qla24xx_read_window(reg, 0xBE60, 16, iter_reg);
1960 iter_reg = qla24xx_read_window(reg, 0xBE70, 16, iter_reg);
1961 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1962 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1963 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1964 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1965 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1966 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1967 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1968 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1969
1970 iter_reg = fw->xseq_0_reg;
1971 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1972 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1973 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1974
1975 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1976
1977 qla24xx_read_window(reg, 0xBEF0, 16, fw->xseq_2_reg);
1978
1979 /* Receive sequence registers. */
1980 iter_reg = fw->rseq_gp_reg;
1981 iter_reg = qla24xx_read_window(reg, 0xFE00, 16, iter_reg);
1982 iter_reg = qla24xx_read_window(reg, 0xFE10, 16, iter_reg);
1983 iter_reg = qla24xx_read_window(reg, 0xFE20, 16, iter_reg);
1984 iter_reg = qla24xx_read_window(reg, 0xFE30, 16, iter_reg);
1985 iter_reg = qla24xx_read_window(reg, 0xFE40, 16, iter_reg);
1986 iter_reg = qla24xx_read_window(reg, 0xFE50, 16, iter_reg);
1987 iter_reg = qla24xx_read_window(reg, 0xFE60, 16, iter_reg);
1988 iter_reg = qla24xx_read_window(reg, 0xFE70, 16, iter_reg);
1989 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1990 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1991 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1992 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1993 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1994 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1995 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1996 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1997
1998 iter_reg = fw->rseq_0_reg;
1999 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
2000 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
2001
2002 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
2003 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
2004 qla24xx_read_window(reg, 0xFEF0, 16, fw->rseq_3_reg);
2005
2006 /* Auxiliary sequence registers. */
2007 iter_reg = fw->aseq_gp_reg;
2008 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
2009 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
2010 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
2011 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
2012 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
2013 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
2014 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
2015 iter_reg = qla24xx_read_window(reg, 0xB070, 16, iter_reg);
2016 iter_reg = qla24xx_read_window(reg, 0xB100, 16, iter_reg);
2017 iter_reg = qla24xx_read_window(reg, 0xB110, 16, iter_reg);
2018 iter_reg = qla24xx_read_window(reg, 0xB120, 16, iter_reg);
2019 iter_reg = qla24xx_read_window(reg, 0xB130, 16, iter_reg);
2020 iter_reg = qla24xx_read_window(reg, 0xB140, 16, iter_reg);
2021 iter_reg = qla24xx_read_window(reg, 0xB150, 16, iter_reg);
2022 iter_reg = qla24xx_read_window(reg, 0xB160, 16, iter_reg);
2023 qla24xx_read_window(reg, 0xB170, 16, iter_reg);
2024
2025 iter_reg = fw->aseq_0_reg;
2026 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
2027 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
2028
2029 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
2030 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
2031 qla24xx_read_window(reg, 0xB1F0, 16, fw->aseq_3_reg);
2032
2033 /* Command DMA registers. */
2034 iter_reg = fw->cmd_dma_reg;
2035 iter_reg = qla24xx_read_window(reg, 0x7100, 16, iter_reg);
2036 iter_reg = qla24xx_read_window(reg, 0x7120, 16, iter_reg);
2037 iter_reg = qla24xx_read_window(reg, 0x7130, 16, iter_reg);
2038 qla24xx_read_window(reg, 0x71F0, 16, iter_reg);
2039
2040 /* Queues. */
2041 iter_reg = fw->req0_dma_reg;
2042 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
2043 dmp_reg = &reg->iobase_q;
2044 for (cnt = 0; cnt < 7; cnt++)
2045 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
2046
2047 iter_reg = fw->resp0_dma_reg;
2048 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
2049 dmp_reg = &reg->iobase_q;
2050 for (cnt = 0; cnt < 7; cnt++)
2051 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
2052
2053 iter_reg = fw->req1_dma_reg;
2054 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
2055 dmp_reg = &reg->iobase_q;
2056 for (cnt = 0; cnt < 7; cnt++)
2057 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
2058
2059 /* Transmit DMA registers. */
2060 iter_reg = fw->xmt0_dma_reg;
2061 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
2062 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
2063
2064 iter_reg = fw->xmt1_dma_reg;
2065 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
2066 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
2067
2068 iter_reg = fw->xmt2_dma_reg;
2069 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
2070 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
2071
2072 iter_reg = fw->xmt3_dma_reg;
2073 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
2074 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
2075
2076 iter_reg = fw->xmt4_dma_reg;
2077 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
2078 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
2079
2080 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
2081
2082 /* Receive DMA registers. */
2083 iter_reg = fw->rcvt0_data_dma_reg;
2084 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
2085 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
2086
2087 iter_reg = fw->rcvt1_data_dma_reg;
2088 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
2089 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
2090
2091 /* RISC registers. */
2092 iter_reg = fw->risc_gp_reg;
2093 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
2094 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
2095 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
2096 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
2097 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
2098 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
2099 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
2100 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
2101
2102 /* Local memory controller registers. */
2103 iter_reg = fw->lmc_reg;
2104 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
2105 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
2106 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
2107 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
2108 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
2109 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
2110 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
2111 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
2112
2113 /* Fibre Protocol Module registers. */
2114 iter_reg = fw->fpm_hdw_reg;
2115 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
2116 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
2117 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
2118 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
2119 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
2120 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
2121 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
2122 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
2123 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
2124 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
2125 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
2126 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
2127 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
2128 iter_reg = qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
2129 iter_reg = qla24xx_read_window(reg, 0x40E0, 16, iter_reg);
2130 qla24xx_read_window(reg, 0x40F0, 16, iter_reg);
2131
2132 /* RQ0 Array registers. */
2133 iter_reg = fw->rq0_array_reg;
2134 iter_reg = qla24xx_read_window(reg, 0x5C00, 16, iter_reg);
2135 iter_reg = qla24xx_read_window(reg, 0x5C10, 16, iter_reg);
2136 iter_reg = qla24xx_read_window(reg, 0x5C20, 16, iter_reg);
2137 iter_reg = qla24xx_read_window(reg, 0x5C30, 16, iter_reg);
2138 iter_reg = qla24xx_read_window(reg, 0x5C40, 16, iter_reg);
2139 iter_reg = qla24xx_read_window(reg, 0x5C50, 16, iter_reg);
2140 iter_reg = qla24xx_read_window(reg, 0x5C60, 16, iter_reg);
2141 iter_reg = qla24xx_read_window(reg, 0x5C70, 16, iter_reg);
2142 iter_reg = qla24xx_read_window(reg, 0x5C80, 16, iter_reg);
2143 iter_reg = qla24xx_read_window(reg, 0x5C90, 16, iter_reg);
2144 iter_reg = qla24xx_read_window(reg, 0x5CA0, 16, iter_reg);
2145 iter_reg = qla24xx_read_window(reg, 0x5CB0, 16, iter_reg);
2146 iter_reg = qla24xx_read_window(reg, 0x5CC0, 16, iter_reg);
2147 iter_reg = qla24xx_read_window(reg, 0x5CD0, 16, iter_reg);
2148 iter_reg = qla24xx_read_window(reg, 0x5CE0, 16, iter_reg);
2149 qla24xx_read_window(reg, 0x5CF0, 16, iter_reg);
2150
2151 /* RQ1 Array registers. */
2152 iter_reg = fw->rq1_array_reg;
2153 iter_reg = qla24xx_read_window(reg, 0x5D00, 16, iter_reg);
2154 iter_reg = qla24xx_read_window(reg, 0x5D10, 16, iter_reg);
2155 iter_reg = qla24xx_read_window(reg, 0x5D20, 16, iter_reg);
2156 iter_reg = qla24xx_read_window(reg, 0x5D30, 16, iter_reg);
2157 iter_reg = qla24xx_read_window(reg, 0x5D40, 16, iter_reg);
2158 iter_reg = qla24xx_read_window(reg, 0x5D50, 16, iter_reg);
2159 iter_reg = qla24xx_read_window(reg, 0x5D60, 16, iter_reg);
2160 iter_reg = qla24xx_read_window(reg, 0x5D70, 16, iter_reg);
2161 iter_reg = qla24xx_read_window(reg, 0x5D80, 16, iter_reg);
2162 iter_reg = qla24xx_read_window(reg, 0x5D90, 16, iter_reg);
2163 iter_reg = qla24xx_read_window(reg, 0x5DA0, 16, iter_reg);
2164 iter_reg = qla24xx_read_window(reg, 0x5DB0, 16, iter_reg);
2165 iter_reg = qla24xx_read_window(reg, 0x5DC0, 16, iter_reg);
2166 iter_reg = qla24xx_read_window(reg, 0x5DD0, 16, iter_reg);
2167 iter_reg = qla24xx_read_window(reg, 0x5DE0, 16, iter_reg);
2168 qla24xx_read_window(reg, 0x5DF0, 16, iter_reg);
2169
2170 /* RP0 Array registers. */
2171 iter_reg = fw->rp0_array_reg;
2172 iter_reg = qla24xx_read_window(reg, 0x5E00, 16, iter_reg);
2173 iter_reg = qla24xx_read_window(reg, 0x5E10, 16, iter_reg);
2174 iter_reg = qla24xx_read_window(reg, 0x5E20, 16, iter_reg);
2175 iter_reg = qla24xx_read_window(reg, 0x5E30, 16, iter_reg);
2176 iter_reg = qla24xx_read_window(reg, 0x5E40, 16, iter_reg);
2177 iter_reg = qla24xx_read_window(reg, 0x5E50, 16, iter_reg);
2178 iter_reg = qla24xx_read_window(reg, 0x5E60, 16, iter_reg);
2179 iter_reg = qla24xx_read_window(reg, 0x5E70, 16, iter_reg);
2180 iter_reg = qla24xx_read_window(reg, 0x5E80, 16, iter_reg);
2181 iter_reg = qla24xx_read_window(reg, 0x5E90, 16, iter_reg);
2182 iter_reg = qla24xx_read_window(reg, 0x5EA0, 16, iter_reg);
2183 iter_reg = qla24xx_read_window(reg, 0x5EB0, 16, iter_reg);
2184 iter_reg = qla24xx_read_window(reg, 0x5EC0, 16, iter_reg);
2185 iter_reg = qla24xx_read_window(reg, 0x5ED0, 16, iter_reg);
2186 iter_reg = qla24xx_read_window(reg, 0x5EE0, 16, iter_reg);
2187 qla24xx_read_window(reg, 0x5EF0, 16, iter_reg);
2188
2189 /* RP1 Array registers. */
2190 iter_reg = fw->rp1_array_reg;
2191 iter_reg = qla24xx_read_window(reg, 0x5F00, 16, iter_reg);
2192 iter_reg = qla24xx_read_window(reg, 0x5F10, 16, iter_reg);
2193 iter_reg = qla24xx_read_window(reg, 0x5F20, 16, iter_reg);
2194 iter_reg = qla24xx_read_window(reg, 0x5F30, 16, iter_reg);
2195 iter_reg = qla24xx_read_window(reg, 0x5F40, 16, iter_reg);
2196 iter_reg = qla24xx_read_window(reg, 0x5F50, 16, iter_reg);
2197 iter_reg = qla24xx_read_window(reg, 0x5F60, 16, iter_reg);
2198 iter_reg = qla24xx_read_window(reg, 0x5F70, 16, iter_reg);
2199 iter_reg = qla24xx_read_window(reg, 0x5F80, 16, iter_reg);
2200 iter_reg = qla24xx_read_window(reg, 0x5F90, 16, iter_reg);
2201 iter_reg = qla24xx_read_window(reg, 0x5FA0, 16, iter_reg);
2202 iter_reg = qla24xx_read_window(reg, 0x5FB0, 16, iter_reg);
2203 iter_reg = qla24xx_read_window(reg, 0x5FC0, 16, iter_reg);
2204 iter_reg = qla24xx_read_window(reg, 0x5FD0, 16, iter_reg);
2205 iter_reg = qla24xx_read_window(reg, 0x5FE0, 16, iter_reg);
2206 qla24xx_read_window(reg, 0x5FF0, 16, iter_reg);
2207
2208 iter_reg = fw->at0_array_reg;
2209 iter_reg = qla24xx_read_window(reg, 0x7080, 16, iter_reg);
2210 iter_reg = qla24xx_read_window(reg, 0x7090, 16, iter_reg);
2211 iter_reg = qla24xx_read_window(reg, 0x70A0, 16, iter_reg);
2212 iter_reg = qla24xx_read_window(reg, 0x70B0, 16, iter_reg);
2213 iter_reg = qla24xx_read_window(reg, 0x70C0, 16, iter_reg);
2214 iter_reg = qla24xx_read_window(reg, 0x70D0, 16, iter_reg);
2215 iter_reg = qla24xx_read_window(reg, 0x70E0, 16, iter_reg);
2216 qla24xx_read_window(reg, 0x70F0, 16, iter_reg);
2217
2218 /* I/O Queue Control registers. */
2219 qla24xx_read_window(reg, 0x7800, 16, fw->queue_control_reg);
2220
2221 /* Frame Buffer registers. */
2222 iter_reg = fw->fb_hdw_reg;
2223 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
2224 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
2225 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
2226 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
2227 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
2228 iter_reg = qla24xx_read_window(reg, 0x6060, 16, iter_reg);
2229 iter_reg = qla24xx_read_window(reg, 0x6070, 16, iter_reg);
2230 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
2231 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
2232 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
2233 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
2234 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
2235 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
2236 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
2237 iter_reg = qla24xx_read_window(reg, 0x6530, 16, iter_reg);
2238 iter_reg = qla24xx_read_window(reg, 0x6540, 16, iter_reg);
2239 iter_reg = qla24xx_read_window(reg, 0x6550, 16, iter_reg);
2240 iter_reg = qla24xx_read_window(reg, 0x6560, 16, iter_reg);
2241 iter_reg = qla24xx_read_window(reg, 0x6570, 16, iter_reg);
2242 iter_reg = qla24xx_read_window(reg, 0x6580, 16, iter_reg);
2243 iter_reg = qla24xx_read_window(reg, 0x6590, 16, iter_reg);
2244 iter_reg = qla24xx_read_window(reg, 0x65A0, 16, iter_reg);
2245 iter_reg = qla24xx_read_window(reg, 0x65B0, 16, iter_reg);
2246 iter_reg = qla24xx_read_window(reg, 0x65C0, 16, iter_reg);
2247 iter_reg = qla24xx_read_window(reg, 0x65D0, 16, iter_reg);
2248 iter_reg = qla24xx_read_window(reg, 0x65E0, 16, iter_reg);
2249 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
2250
2251 /* Multi queue registers */
2252 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
2253 &last_chain);
2254
2255 rval = qla24xx_soft_reset(ha);
2256 if (rval != QLA_SUCCESS) {
2257 ql_log(ql_log_warn, vha, 0xd00e,
2258 "SOFT RESET FAILED, forcing continuation of dump!!!\n");
2259 rval = QLA_SUCCESS;
2260
2261 ql_log(ql_log_warn, vha, 0xd00f, "try a bigger hammer!!!\n");
2262
2263 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
2264 RD_REG_DWORD(&reg->hccr);
2265
2266 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
2267 RD_REG_DWORD(&reg->hccr);
2268
2269 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
2270 RD_REG_DWORD(&reg->hccr);
2271
2272 for (cnt = 30000; cnt && (RD_REG_WORD(&reg->mailbox0)); cnt--)
2273 udelay(5);
2274
2275 if (!cnt) {
2276 nxt = fw->code_ram;
8c0bc701 2277 nxt += sizeof(fw->code_ram);
6246b8a1
GM		 2278 nxt += (ha->fw_memory_size - 0x100000 + 1);
2279 goto copy_queue;
2280 } else
2281 ql_log(ql_log_warn, vha, 0xd010,
2282 "bigger hammer success?\n");
2283 }
2284
2285 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
2286 &nxt);
2287 if (rval != QLA_SUCCESS)
2288 goto qla83xx_fw_dump_failed_0;
2289
2290copy_queue:
2291 nxt = qla2xxx_copy_queues(ha, nxt);
2292
2293 nxt = qla24xx_copy_eft(ha, nxt);
2294
2295 /* Chain entries -- started with MQ. */
2296 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
2297 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
2d70c103 2298 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
6246b8a1
GM		 2299 if (last_chain) {
2300 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
2301 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
2302 }
2303
2304 /* Adjust valid length. */
2305 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
2306
2307qla83xx_fw_dump_failed_0:
2308 qla2xxx_dump_post_process(base_vha, rval);
2309
2310qla83xx_fw_dump_failed:
2311 if (!hardware_locked)
2312 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2313}
2314
1da177e4
LT		 2315/****************************************************************************/
2316/* Driver Debug Functions. */
2317/****************************************************************************/
cfb0919c
CD		 2318
2319static inline int
2320ql_mask_match(uint32_t level)
2321{
2322 if (ql2xextended_error_logging == 1)
2323 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
2324 return (level & ql2xextended_error_logging) == level;
2325}
2326
3ce8866c
SK		 2327/*
2328 * This function is for formatting and logging debug information.
2329 * It is to be used when vha is available. It formats the message
2330 * and logs it to the messages file.
2331 * parameters:
2332 * level: The level of the debug messages to be printed.
2333 * If ql2xextended_error_logging value is correctly set,
2334 * this message will appear in the messages file.
2335 * vha: Pointer to the scsi_qla_host_t.
2336 * id: This is a unique identifier for the level. It identifies the
2337 * part of the code from where the message originated.
2338 * msg: The message to be displayed.
2339 */
2340void
086b3e8a
JP		 2341ql_dbg(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...)
2342{
2343 va_list va;
2344 struct va_format vaf;
3ce8866c 2345
cfb0919c 2346 if (!ql_mask_match(level))
086b3e8a 2347 return;
3ce8866c 2348
086b3e8a 2349 va_start(va, fmt);
3ce8866c 2350
086b3e8a
JP		 2351 vaf.fmt = fmt;
2352 vaf.va = &va;
3ce8866c 2353
086b3e8a
JP		 2354 if (vha != NULL) {
2355 const struct pci_dev *pdev = vha->hw->pdev;
2356 /* <module-name> <pci-name> <msg-id>:<host> Message */
2357 pr_warn("%s [%s]-%04x:%ld: %pV",
2358 QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset,
2359 vha->host_no, &vaf);
2360 } else {
2361 pr_warn("%s [%s]-%04x: : %pV",
2362 QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf);
3ce8866c
SK		 2363 }
2364
086b3e8a 2365 va_end(va);
3ce8866c
SK		 2366
2367}
2368
2369/*
2370 * This function is for formatting and logging debug information.
d6a03581 2371 * It is to be used when vha is not available and pci is available,
3ce8866c
SK		 2372 * i.e., before host allocation. It formats the message and logs it
2373 * to the messages file.
2374 * parameters:
2375 * level: The level of the debug messages to be printed.
2376 * If ql2xextended_error_logging value is correctly set,
2377 * this message will appear in the messages file.
2378 * pdev: Pointer to the struct pci_dev.
2379 * id: This is a unique id for the level. It identifies the part
2380 * of the code from where the message originated.
2381 * msg: The message to be displayed.
2382 */
2383void
086b3e8a
JP		 2384ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
2385 const char *fmt, ...)
2386{
2387 va_list va;
2388 struct va_format vaf;
3ce8866c
SK		 2389
2390 if (pdev == NULL)
2391 return;
cfb0919c 2392 if (!ql_mask_match(level))
086b3e8a 2393 return;
3ce8866c 2394
086b3e8a 2395 va_start(va, fmt);
3ce8866c 2396
086b3e8a
JP		 2397 vaf.fmt = fmt;
2398 vaf.va = &va;
3ce8866c 2399
086b3e8a
JP		 2400 /* <module-name> <dev-name>:<msg-id> Message */
2401 pr_warn("%s [%s]-%04x: : %pV",
2402 QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, &vaf);
3ce8866c 2403
086b3e8a 2404 va_end(va);
3ce8866c
SK		 2405}
2406
2407/*
2408 * This function is for formatting and logging log messages.
2409 * It is to be used when vha is available. It formats the message
2410 * and logs it to the messages file. All the messages will be logged
2411 * irrespective of value of ql2xextended_error_logging.
2412 * parameters:
2413 * level: The level of the log messages to be printed in the
2414 * messages file.
2415 * vha: Pointer to the scsi_qla_host_t
2416 * id: This is a unique id for the level. It identifies the
2417 * part of the code from where the message originated.
2418 * msg: The message to be displayed.
2419 */
2420void
086b3e8a
JP		 2421ql_log(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...)
2422{
2423 va_list va;
2424 struct va_format vaf;
2425 char pbuf[128];
3ce8866c 2426
086b3e8a
JP		 2427 if (level > ql_errlev)
2428 return;
3ce8866c 2429
086b3e8a
JP		 2430 if (vha != NULL) {
2431 const struct pci_dev *pdev = vha->hw->pdev;
2432 /* <module-name> <msg-id>:<host> Message */
2433 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x:%ld: ",
2434 QL_MSGHDR, dev_name(&(pdev->dev)), id, vha->host_no);
2435 } else {
2436 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
2437 QL_MSGHDR, "0000:00:00.0", id);
2438 }
2439 pbuf[sizeof(pbuf) - 1] = 0;
2440
2441 va_start(va, fmt);
2442
2443 vaf.fmt = fmt;
2444 vaf.va = &va;
2445
2446 switch (level) {
70a3fc76 2447 case ql_log_fatal: /* FATAL LOG */
086b3e8a
JP		 2448 pr_crit("%s%pV", pbuf, &vaf);
2449 break;
70a3fc76 2450 case ql_log_warn:
086b3e8a
JP		 2451 pr_err("%s%pV", pbuf, &vaf);
2452 break;
70a3fc76 2453 case ql_log_info:
086b3e8a
JP		 2454 pr_warn("%s%pV", pbuf, &vaf);
2455 break;
2456 default:
2457 pr_info("%s%pV", pbuf, &vaf);
2458 break;
3ce8866c
SK		 2459 }
2460
086b3e8a 2461 va_end(va);
3ce8866c
SK		 2462}
2463
2464/*
2465 * This function is for formatting and logging log messages.
d6a03581 2466 * It is to be used when vha is not available and pci is available,
3ce8866c
SK		 2467 * i.e., before host allocation. It formats the message and logs
2468 * it to the messages file. All the messages are logged irrespective
2469 * of the value of ql2xextended_error_logging.
2470 * parameters:
2471 * level: The level of the log messages to be printed in the
2472 * messages file.
2473 * pdev: Pointer to the struct pci_dev.
2474 * id: This is a unique id for the level. It identifies the
2475 * part of the code from where the message originated.
2476 * msg: The message to be displayed.
2477 */
2478void
086b3e8a
JP		 2479ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
2480 const char *fmt, ...)
2481{
2482 va_list va;
2483 struct va_format vaf;
2484 char pbuf[128];
3ce8866c
SK		 2485
2486 if (pdev == NULL)
2487 return;
086b3e8a
JP		 2488 if (level > ql_errlev)
2489 return;
3ce8866c 2490
086b3e8a
JP		 2491 /* <module-name> <dev-name>:<msg-id> Message */
2492 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
2493 QL_MSGHDR, dev_name(&(pdev->dev)), id);
2494 pbuf[sizeof(pbuf) - 1] = 0;
2495
2496 va_start(va, fmt);
2497
2498 vaf.fmt = fmt;
2499 vaf.va = &va;
2500
2501 switch (level) {
70a3fc76 2502 case ql_log_fatal: /* FATAL LOG */
086b3e8a
JP		 2503 pr_crit("%s%pV", pbuf, &vaf);
2504 break;
70a3fc76 2505 case ql_log_warn:
086b3e8a
JP		 2506 pr_err("%s%pV", pbuf, &vaf);
2507 break;
70a3fc76 2508 case ql_log_info:
086b3e8a
JP		 2509 pr_warn("%s%pV", pbuf, &vaf);
2510 break;
2511 default:
2512 pr_info("%s%pV", pbuf, &vaf);
2513 break;
3ce8866c
SK		 2514 }
2515
086b3e8a 2516 va_end(va);
3ce8866c
SK		 2517}
2518
2519void
2520ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id)
2521{
2522 int i;
2523 struct qla_hw_data *ha = vha->hw;
2524 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2525 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
2526 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
2527 uint16_t __iomem *mbx_reg;
2528
cfb0919c
CD		 2529 if (!ql_mask_match(level))
2530 return;
3ce8866c 2531
cfb0919c
CD		 2532 if (IS_QLA82XX(ha))
2533 mbx_reg = &reg82->mailbox_in[0];
2534 else if (IS_FWI2_CAPABLE(ha))
2535 mbx_reg = &reg24->mailbox0;
2536 else
2537 mbx_reg = MAILBOX_REG(ha, reg, 0);
2538
2539 ql_dbg(level, vha, id, "Mailbox registers:\n");
2540 for (i = 0; i < 6; i++)
2541 ql_dbg(level, vha, id,
2542 "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++));
3ce8866c
SK		 2543}
2544
2545
2546void
2547ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id,
2548 uint8_t *b, uint32_t size)
2549{
2550 uint32_t cnt;
2551 uint8_t c;
cfb0919c
CD		 2552
2553 if (!ql_mask_match(level))
2554 return;
2555
2556 ql_dbg(level, vha, id, " 0 1 2 3 4 5 6 7 8 "
2557 "9 Ah Bh Ch Dh Eh Fh\n");
2558 ql_dbg(level, vha, id, "----------------------------------"
2559 "----------------------------\n");
2560
2561 ql_dbg(level, vha, id, " ");
2562 for (cnt = 0; cnt < size;) {
2563 c = *b++;
2564 printk("%02x", (uint32_t) c);
2565 cnt++;
2566 if (!(cnt % 16))
2567 printk("\n");
2568 else
2569 printk(" ");
3ce8866c 2570 }
cfb0919c
CD		 2571 if (cnt % 16)
2572 ql_dbg(level, vha, id, "\n");
3ce8866c 2573}
Linux kernel - Deliverables
This page took 0.815484 seconds and 5 git commands to generate.