Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
fa90c54f | 2 | * QLogic Fibre Channel HBA Driver |
07e264b7 | 3 | * Copyright (c) 2003-2011 QLogic Corporation |
1da177e4 | 4 | * |
fa90c54f | 5 | * See LICENSE.qla2xxx for copyright and licensing details. |
1da177e4 | 6 | */ |
3ce8866c SK |
7 | |
8 | /* | |
9 | * Table for showing the current message id in use for particular level | |
10 | * Change this table for addition of log/debug messages. | |
e02587d7 AE |
11 | * ---------------------------------------------------------------------- |
12 | * | Level | Last Value Used | Holes | | |
13 | * ---------------------------------------------------------------------- | |
0b91d116 | 14 | * | Module Init and Probe | 0x0120 | 0x4b,0xba,0xfa | |
af11f64d AV |
15 | * | Mailbox commands | 0x113e | 0x112c-0x112e | |
16 | * | | | 0x113a | | |
557cf785 | 17 | * | Device Discovery | 0x2086 | 0x2020-0x2022 | |
9ba56b95 | 18 | * | Queue Command and IO tracing | 0x302f | 0x3006,0x3008 | |
6246b8a1 | 19 | * | | | 0x302d-0x302e | |
e02587d7 | 20 | * | DPC Thread | 0x401c | | |
3256b435 | 21 | * | Async Events | 0x505d | 0x502b-0x502f | |
9ba56b95 | 22 | * | | | 0x5047,0x5052 | |
6246b8a1 | 23 | * | Timer Routines | 0x6011 | 0x600e-0x600f | |
d051a5aa AV |
24 | * | User Space Interactions | 0x709e | 0x7018,0x702e | |
25 | * | | | 0x7039,0x7045 | | |
cfb0919c CD |
26 | * | Task Management | 0x803c | 0x8025-0x8026 | |
27 | * | | | 0x800b,0x8039 | | |
e02587d7 AE |
28 | * | AER/EEH | 0x900f | | |
29 | * | Virtual Port | 0xa007 | | | |
3256b435 | 30 | * | ISP82XX Specific | 0xb054 | 0xb053 | |
6246b8a1 GM |
31 | * | MultiQ | 0xc00c | | |
32 | * | Misc | 0xd010 | | | |
e02587d7 | 33 | * ---------------------------------------------------------------------- |
3ce8866c SK |
34 | */ |
35 | ||
1da177e4 LT |
36 | #include "qla_def.h" |
37 | ||
38 | #include <linux/delay.h> | |
39 | ||
3ce8866c SK |
40 | static uint32_t ql_dbg_offset = 0x800; |
41 | ||
a7a167bf | 42 | static inline void |
7b867cf7 | 43 | qla2xxx_prep_dump(struct qla_hw_data *ha, struct qla2xxx_fw_dump *fw_dump) |
a7a167bf AV |
44 | { |
45 | fw_dump->fw_major_version = htonl(ha->fw_major_version); | |
46 | fw_dump->fw_minor_version = htonl(ha->fw_minor_version); | |
47 | fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version); | |
48 | fw_dump->fw_attributes = htonl(ha->fw_attributes); | |
49 | ||
50 | fw_dump->vendor = htonl(ha->pdev->vendor); | |
51 | fw_dump->device = htonl(ha->pdev->device); | |
52 | fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor); | |
53 | fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device); | |
54 | } | |
55 | ||
56 | static inline void * | |
73208dfd | 57 | qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr) |
a7a167bf | 58 | { |
73208dfd AC |
59 | struct req_que *req = ha->req_q_map[0]; |
60 | struct rsp_que *rsp = ha->rsp_q_map[0]; | |
a7a167bf | 61 | /* Request queue. */ |
7b867cf7 | 62 | memcpy(ptr, req->ring, req->length * |
a7a167bf AV |
63 | sizeof(request_t)); |
64 | ||
65 | /* Response queue. */ | |
7b867cf7 AC |
66 | ptr += req->length * sizeof(request_t); |
67 | memcpy(ptr, rsp->ring, rsp->length * | |
a7a167bf AV |
68 | sizeof(response_t)); |
69 | ||
7b867cf7 | 70 | return ptr + (rsp->length * sizeof(response_t)); |
a7a167bf | 71 | } |
1da177e4 | 72 | |
c3a2f0df | 73 | static int |
7b867cf7 | 74 | qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram, |
c5722708 | 75 | uint32_t ram_dwords, void **nxt) |
c3a2f0df AV |
76 | { |
77 | int rval; | |
c5722708 AV |
78 | uint32_t cnt, stat, timer, dwords, idx; |
79 | uint16_t mb0; | |
c3a2f0df | 80 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
c5722708 AV |
81 | dma_addr_t dump_dma = ha->gid_list_dma; |
82 | uint32_t *dump = (uint32_t *)ha->gid_list; | |
c3a2f0df AV |
83 | |
84 | rval = QLA_SUCCESS; | |
c5722708 | 85 | mb0 = 0; |
c3a2f0df | 86 | |
c5722708 | 87 | WRT_REG_WORD(®->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED); |
c3a2f0df AV |
88 | clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); |
89 | ||
c5722708 AV |
90 | dwords = GID_LIST_SIZE / 4; |
91 | for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS; | |
92 | cnt += dwords, addr += dwords) { | |
93 | if (cnt + dwords > ram_dwords) | |
94 | dwords = ram_dwords - cnt; | |
c3a2f0df | 95 | |
c5722708 AV |
96 | WRT_REG_WORD(®->mailbox1, LSW(addr)); |
97 | WRT_REG_WORD(®->mailbox8, MSW(addr)); | |
c3a2f0df | 98 | |
c5722708 AV |
99 | WRT_REG_WORD(®->mailbox2, MSW(dump_dma)); |
100 | WRT_REG_WORD(®->mailbox3, LSW(dump_dma)); | |
101 | WRT_REG_WORD(®->mailbox6, MSW(MSD(dump_dma))); | |
102 | WRT_REG_WORD(®->mailbox7, LSW(MSD(dump_dma))); | |
c3a2f0df | 103 | |
c5722708 AV |
104 | WRT_REG_WORD(®->mailbox4, MSW(dwords)); |
105 | WRT_REG_WORD(®->mailbox5, LSW(dwords)); | |
c3a2f0df AV |
106 | WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); |
107 | ||
108 | for (timer = 6000000; timer; timer--) { | |
109 | /* Check for pending interrupts. */ | |
110 | stat = RD_REG_DWORD(®->host_status); | |
111 | if (stat & HSRX_RISC_INT) { | |
112 | stat &= 0xff; | |
113 | ||
114 | if (stat == 0x1 || stat == 0x2 || | |
115 | stat == 0x10 || stat == 0x11) { | |
116 | set_bit(MBX_INTERRUPT, | |
117 | &ha->mbx_cmd_flags); | |
118 | ||
c5722708 | 119 | mb0 = RD_REG_WORD(®->mailbox0); |
c3a2f0df AV |
120 | |
121 | WRT_REG_DWORD(®->hccr, | |
122 | HCCRX_CLR_RISC_INT); | |
123 | RD_REG_DWORD(®->hccr); | |
124 | break; | |
125 | } | |
126 | ||
127 | /* Clear this intr; it wasn't a mailbox intr */ | |
128 | WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); | |
129 | RD_REG_DWORD(®->hccr); | |
130 | } | |
131 | udelay(5); | |
132 | } | |
133 | ||
134 | if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { | |
c5722708 AV |
135 | rval = mb0 & MBS_MASK; |
136 | for (idx = 0; idx < dwords; idx++) | |
137 | ram[cnt + idx] = swab32(dump[idx]); | |
c3a2f0df AV |
138 | } else { |
139 | rval = QLA_FUNCTION_FAILED; | |
140 | } | |
141 | } | |
142 | ||
c5722708 | 143 | *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL; |
c3a2f0df AV |
144 | return rval; |
145 | } | |
146 | ||
c5722708 | 147 | static int |
7b867cf7 | 148 | qla24xx_dump_memory(struct qla_hw_data *ha, uint32_t *code_ram, |
c5722708 AV |
149 | uint32_t cram_size, void **nxt) |
150 | { | |
151 | int rval; | |
152 | ||
153 | /* Code RAM. */ | |
154 | rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt); | |
155 | if (rval != QLA_SUCCESS) | |
156 | return rval; | |
157 | ||
158 | /* External Memory. */ | |
159 | return qla24xx_dump_ram(ha, 0x100000, *nxt, | |
160 | ha->fw_memory_size - 0x100000 + 1, nxt); | |
161 | } | |
162 | ||
c81d04c9 AV |
163 | static uint32_t * |
164 | qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase, | |
165 | uint32_t count, uint32_t *buf) | |
166 | { | |
167 | uint32_t __iomem *dmp_reg; | |
168 | ||
169 | WRT_REG_DWORD(®->iobase_addr, iobase); | |
170 | dmp_reg = ®->iobase_window; | |
171 | while (count--) | |
172 | *buf++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
173 | ||
174 | return buf; | |
175 | } | |
176 | ||
177 | static inline int | |
178 | qla24xx_pause_risc(struct device_reg_24xx __iomem *reg) | |
179 | { | |
180 | int rval = QLA_SUCCESS; | |
181 | uint32_t cnt; | |
182 | ||
c3b058af | 183 | WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE); |
aed10881 AV |
184 | for (cnt = 30000; |
185 | ((RD_REG_DWORD(®->host_status) & HSRX_RISC_PAUSED) == 0) && | |
c3b058af AV |
186 | rval == QLA_SUCCESS; cnt--) { |
187 | if (cnt) | |
188 | udelay(100); | |
189 | else | |
190 | rval = QLA_FUNCTION_TIMEOUT; | |
c81d04c9 AV |
191 | } |
192 | ||
193 | return rval; | |
194 | } | |
195 | ||
196 | static int | |
7b867cf7 | 197 | qla24xx_soft_reset(struct qla_hw_data *ha) |
c81d04c9 AV |
198 | { |
199 | int rval = QLA_SUCCESS; | |
200 | uint32_t cnt; | |
201 | uint16_t mb0, wd; | |
202 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
203 | ||
204 | /* Reset RISC. */ | |
205 | WRT_REG_DWORD(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); | |
206 | for (cnt = 0; cnt < 30000; cnt++) { | |
207 | if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) | |
208 | break; | |
209 | ||
210 | udelay(10); | |
211 | } | |
212 | ||
213 | WRT_REG_DWORD(®->ctrl_status, | |
214 | CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); | |
215 | pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); | |
216 | ||
217 | udelay(100); | |
218 | /* Wait for firmware to complete NVRAM accesses. */ | |
219 | mb0 = (uint32_t) RD_REG_WORD(®->mailbox0); | |
220 | for (cnt = 10000 ; cnt && mb0; cnt--) { | |
221 | udelay(5); | |
222 | mb0 = (uint32_t) RD_REG_WORD(®->mailbox0); | |
223 | barrier(); | |
224 | } | |
225 | ||
226 | /* Wait for soft-reset to complete. */ | |
227 | for (cnt = 0; cnt < 30000; cnt++) { | |
228 | if ((RD_REG_DWORD(®->ctrl_status) & | |
229 | CSRX_ISP_SOFT_RESET) == 0) | |
230 | break; | |
231 | ||
232 | udelay(10); | |
233 | } | |
234 | WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); | |
235 | RD_REG_DWORD(®->hccr); /* PCI Posting. */ | |
236 | ||
237 | for (cnt = 30000; RD_REG_WORD(®->mailbox0) != 0 && | |
238 | rval == QLA_SUCCESS; cnt--) { | |
239 | if (cnt) | |
240 | udelay(100); | |
241 | else | |
242 | rval = QLA_FUNCTION_TIMEOUT; | |
243 | } | |
244 | ||
245 | return rval; | |
246 | } | |
247 | ||
c5722708 | 248 | static int |
7b867cf7 | 249 | qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint16_t *ram, |
e18e963b | 250 | uint32_t ram_words, void **nxt) |
c5722708 AV |
251 | { |
252 | int rval; | |
253 | uint32_t cnt, stat, timer, words, idx; | |
254 | uint16_t mb0; | |
255 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
256 | dma_addr_t dump_dma = ha->gid_list_dma; | |
257 | uint16_t *dump = (uint16_t *)ha->gid_list; | |
258 | ||
259 | rval = QLA_SUCCESS; | |
260 | mb0 = 0; | |
261 | ||
262 | WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED); | |
263 | clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | |
264 | ||
265 | words = GID_LIST_SIZE / 2; | |
266 | for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS; | |
267 | cnt += words, addr += words) { | |
268 | if (cnt + words > ram_words) | |
269 | words = ram_words - cnt; | |
270 | ||
271 | WRT_MAILBOX_REG(ha, reg, 1, LSW(addr)); | |
272 | WRT_MAILBOX_REG(ha, reg, 8, MSW(addr)); | |
273 | ||
274 | WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma)); | |
275 | WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma)); | |
276 | WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma))); | |
277 | WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma))); | |
278 | ||
279 | WRT_MAILBOX_REG(ha, reg, 4, words); | |
280 | WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); | |
281 | ||
282 | for (timer = 6000000; timer; timer--) { | |
283 | /* Check for pending interrupts. */ | |
284 | stat = RD_REG_DWORD(®->u.isp2300.host_status); | |
285 | if (stat & HSR_RISC_INT) { | |
286 | stat &= 0xff; | |
287 | ||
288 | if (stat == 0x1 || stat == 0x2) { | |
289 | set_bit(MBX_INTERRUPT, | |
290 | &ha->mbx_cmd_flags); | |
291 | ||
292 | mb0 = RD_MAILBOX_REG(ha, reg, 0); | |
293 | ||
294 | /* Release mailbox registers. */ | |
295 | WRT_REG_WORD(®->semaphore, 0); | |
296 | WRT_REG_WORD(®->hccr, | |
297 | HCCR_CLR_RISC_INT); | |
298 | RD_REG_WORD(®->hccr); | |
299 | break; | |
300 | } else if (stat == 0x10 || stat == 0x11) { | |
301 | set_bit(MBX_INTERRUPT, | |
302 | &ha->mbx_cmd_flags); | |
303 | ||
304 | mb0 = RD_MAILBOX_REG(ha, reg, 0); | |
305 | ||
306 | WRT_REG_WORD(®->hccr, | |
307 | HCCR_CLR_RISC_INT); | |
308 | RD_REG_WORD(®->hccr); | |
309 | break; | |
310 | } | |
311 | ||
312 | /* clear this intr; it wasn't a mailbox intr */ | |
313 | WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); | |
314 | RD_REG_WORD(®->hccr); | |
315 | } | |
316 | udelay(5); | |
317 | } | |
318 | ||
319 | if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { | |
320 | rval = mb0 & MBS_MASK; | |
321 | for (idx = 0; idx < words; idx++) | |
322 | ram[cnt + idx] = swab16(dump[idx]); | |
323 | } else { | |
324 | rval = QLA_FUNCTION_FAILED; | |
325 | } | |
326 | } | |
327 | ||
328 | *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL; | |
329 | return rval; | |
330 | } | |
331 | ||
c81d04c9 AV |
332 | static inline void |
333 | qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count, | |
334 | uint16_t *buf) | |
335 | { | |
336 | uint16_t __iomem *dmp_reg = ®->u.isp2300.fb_cmd; | |
337 | ||
338 | while (count--) | |
339 | *buf++ = htons(RD_REG_WORD(dmp_reg++)); | |
340 | } | |
341 | ||
bb99de67 AV |
342 | static inline void * |
343 | qla24xx_copy_eft(struct qla_hw_data *ha, void *ptr) | |
344 | { | |
345 | if (!ha->eft) | |
346 | return ptr; | |
347 | ||
348 | memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size)); | |
349 | return ptr + ntohl(ha->fw_dump->eft_size); | |
350 | } | |
351 | ||
352 | static inline void * | |
353 | qla25xx_copy_fce(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) | |
354 | { | |
355 | uint32_t cnt; | |
356 | uint32_t *iter_reg; | |
357 | struct qla2xxx_fce_chain *fcec = ptr; | |
358 | ||
359 | if (!ha->fce) | |
360 | return ptr; | |
361 | ||
362 | *last_chain = &fcec->type; | |
363 | fcec->type = __constant_htonl(DUMP_CHAIN_FCE); | |
364 | fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) + | |
365 | fce_calc_size(ha->fce_bufs)); | |
366 | fcec->size = htonl(fce_calc_size(ha->fce_bufs)); | |
367 | fcec->addr_l = htonl(LSD(ha->fce_dma)); | |
368 | fcec->addr_h = htonl(MSD(ha->fce_dma)); | |
369 | ||
370 | iter_reg = fcec->eregs; | |
371 | for (cnt = 0; cnt < 8; cnt++) | |
372 | *iter_reg++ = htonl(ha->fce_mb[cnt]); | |
373 | ||
374 | memcpy(iter_reg, ha->fce, ntohl(fcec->size)); | |
375 | ||
3cb0a67d | 376 | return (char *)iter_reg + ntohl(fcec->size); |
bb99de67 AV |
377 | } |
378 | ||
050c9bb1 GM |
379 | static inline void * |
380 | qla25xx_copy_mqueues(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) | |
381 | { | |
382 | struct qla2xxx_mqueue_chain *q; | |
383 | struct qla2xxx_mqueue_header *qh; | |
384 | struct req_que *req; | |
385 | struct rsp_que *rsp; | |
386 | int que; | |
387 | ||
388 | if (!ha->mqenable) | |
389 | return ptr; | |
390 | ||
391 | /* Request queues */ | |
392 | for (que = 1; que < ha->max_req_queues; que++) { | |
393 | req = ha->req_q_map[que]; | |
394 | if (!req) | |
395 | break; | |
396 | ||
397 | /* Add chain. */ | |
398 | q = ptr; | |
399 | *last_chain = &q->type; | |
400 | q->type = __constant_htonl(DUMP_CHAIN_QUEUE); | |
401 | q->chain_size = htonl( | |
402 | sizeof(struct qla2xxx_mqueue_chain) + | |
403 | sizeof(struct qla2xxx_mqueue_header) + | |
404 | (req->length * sizeof(request_t))); | |
405 | ptr += sizeof(struct qla2xxx_mqueue_chain); | |
406 | ||
407 | /* Add header. */ | |
408 | qh = ptr; | |
409 | qh->queue = __constant_htonl(TYPE_REQUEST_QUEUE); | |
410 | qh->number = htonl(que); | |
411 | qh->size = htonl(req->length * sizeof(request_t)); | |
412 | ptr += sizeof(struct qla2xxx_mqueue_header); | |
413 | ||
414 | /* Add data. */ | |
415 | memcpy(ptr, req->ring, req->length * sizeof(request_t)); | |
416 | ptr += req->length * sizeof(request_t); | |
417 | } | |
418 | ||
419 | /* Response queues */ | |
420 | for (que = 1; que < ha->max_rsp_queues; que++) { | |
421 | rsp = ha->rsp_q_map[que]; | |
422 | if (!rsp) | |
423 | break; | |
424 | ||
425 | /* Add chain. */ | |
426 | q = ptr; | |
427 | *last_chain = &q->type; | |
428 | q->type = __constant_htonl(DUMP_CHAIN_QUEUE); | |
429 | q->chain_size = htonl( | |
430 | sizeof(struct qla2xxx_mqueue_chain) + | |
431 | sizeof(struct qla2xxx_mqueue_header) + | |
432 | (rsp->length * sizeof(response_t))); | |
433 | ptr += sizeof(struct qla2xxx_mqueue_chain); | |
434 | ||
435 | /* Add header. */ | |
436 | qh = ptr; | |
437 | qh->queue = __constant_htonl(TYPE_RESPONSE_QUEUE); | |
438 | qh->number = htonl(que); | |
439 | qh->size = htonl(rsp->length * sizeof(response_t)); | |
440 | ptr += sizeof(struct qla2xxx_mqueue_header); | |
441 | ||
442 | /* Add data. */ | |
443 | memcpy(ptr, rsp->ring, rsp->length * sizeof(response_t)); | |
444 | ptr += rsp->length * sizeof(response_t); | |
445 | } | |
446 | ||
447 | return ptr; | |
448 | } | |
449 | ||
d63ab533 AV |
450 | static inline void * |
451 | qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) | |
452 | { | |
453 | uint32_t cnt, que_idx; | |
2afa19a9 | 454 | uint8_t que_cnt; |
d63ab533 AV |
455 | struct qla2xxx_mq_chain *mq = ptr; |
456 | struct device_reg_25xxmq __iomem *reg; | |
457 | ||
6246b8a1 | 458 | if (!ha->mqenable || IS_QLA83XX(ha)) |
d63ab533 AV |
459 | return ptr; |
460 | ||
461 | mq = ptr; | |
462 | *last_chain = &mq->type; | |
463 | mq->type = __constant_htonl(DUMP_CHAIN_MQ); | |
464 | mq->chain_size = __constant_htonl(sizeof(struct qla2xxx_mq_chain)); | |
465 | ||
2afa19a9 AC |
466 | que_cnt = ha->max_req_queues > ha->max_rsp_queues ? |
467 | ha->max_req_queues : ha->max_rsp_queues; | |
d63ab533 AV |
468 | mq->count = htonl(que_cnt); |
469 | for (cnt = 0; cnt < que_cnt; cnt++) { | |
470 | reg = (struct device_reg_25xxmq *) ((void *) | |
471 | ha->mqiobase + cnt * QLA_QUE_PAGE); | |
472 | que_idx = cnt * 4; | |
473 | mq->qregs[que_idx] = htonl(RD_REG_DWORD(®->req_q_in)); | |
474 | mq->qregs[que_idx+1] = htonl(RD_REG_DWORD(®->req_q_out)); | |
475 | mq->qregs[que_idx+2] = htonl(RD_REG_DWORD(®->rsp_q_in)); | |
476 | mq->qregs[que_idx+3] = htonl(RD_REG_DWORD(®->rsp_q_out)); | |
477 | } | |
478 | ||
479 | return ptr + sizeof(struct qla2xxx_mq_chain); | |
480 | } | |
481 | ||
08de2844 | 482 | void |
3420d36c AV |
483 | qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval) |
484 | { | |
485 | struct qla_hw_data *ha = vha->hw; | |
486 | ||
487 | if (rval != QLA_SUCCESS) { | |
7c3df132 SK |
488 | ql_log(ql_log_warn, vha, 0xd000, |
489 | "Failed to dump firmware (%x).\n", rval); | |
3420d36c AV |
490 | ha->fw_dumped = 0; |
491 | } else { | |
7c3df132 | 492 | ql_log(ql_log_info, vha, 0xd001, |
3420d36c AV |
493 | "Firmware dump saved to temp buffer (%ld/%p).\n", |
494 | vha->host_no, ha->fw_dump); | |
495 | ha->fw_dumped = 1; | |
496 | qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); | |
497 | } | |
498 | } | |
499 | ||
1da177e4 LT |
500 | /** |
501 | * qla2300_fw_dump() - Dumps binary data from the 2300 firmware. | |
502 | * @ha: HA context | |
503 | * @hardware_locked: Called with the hardware_lock | |
504 | */ | |
505 | void | |
7b867cf7 | 506 | qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
1da177e4 LT |
507 | { |
508 | int rval; | |
c5722708 | 509 | uint32_t cnt; |
7b867cf7 | 510 | struct qla_hw_data *ha = vha->hw; |
3d71644c | 511 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 LT |
512 | uint16_t __iomem *dmp_reg; |
513 | unsigned long flags; | |
514 | struct qla2300_fw_dump *fw; | |
c5722708 | 515 | void *nxt; |
73208dfd | 516 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
1da177e4 | 517 | |
1da177e4 LT |
518 | flags = 0; |
519 | ||
520 | if (!hardware_locked) | |
521 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
522 | ||
d4e3e04d | 523 | if (!ha->fw_dump) { |
7c3df132 SK |
524 | ql_log(ql_log_warn, vha, 0xd002, |
525 | "No buffer available for dump.\n"); | |
1da177e4 LT |
526 | goto qla2300_fw_dump_failed; |
527 | } | |
528 | ||
d4e3e04d | 529 | if (ha->fw_dumped) { |
7c3df132 SK |
530 | ql_log(ql_log_warn, vha, 0xd003, |
531 | "Firmware has been previously dumped (%p) " | |
532 | "-- ignoring request.\n", | |
533 | ha->fw_dump); | |
1da177e4 LT |
534 | goto qla2300_fw_dump_failed; |
535 | } | |
a7a167bf AV |
536 | fw = &ha->fw_dump->isp.isp23; |
537 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
1da177e4 LT |
538 | |
539 | rval = QLA_SUCCESS; | |
a7a167bf | 540 | fw->hccr = htons(RD_REG_WORD(®->hccr)); |
1da177e4 LT |
541 | |
542 | /* Pause RISC. */ | |
fa2a1ce5 | 543 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); |
1da177e4 LT |
544 | if (IS_QLA2300(ha)) { |
545 | for (cnt = 30000; | |
546 | (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && | |
547 | rval == QLA_SUCCESS; cnt--) { | |
548 | if (cnt) | |
549 | udelay(100); | |
550 | else | |
551 | rval = QLA_FUNCTION_TIMEOUT; | |
552 | } | |
553 | } else { | |
554 | RD_REG_WORD(®->hccr); /* PCI Posting. */ | |
555 | udelay(10); | |
556 | } | |
557 | ||
558 | if (rval == QLA_SUCCESS) { | |
c81d04c9 | 559 | dmp_reg = ®->flash_address; |
fa2a1ce5 | 560 | for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) |
a7a167bf | 561 | fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 562 | |
c81d04c9 | 563 | dmp_reg = ®->u.isp2300.req_q_in; |
fa2a1ce5 | 564 | for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++) |
a7a167bf | 565 | fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 566 | |
c81d04c9 | 567 | dmp_reg = ®->u.isp2300.mailbox0; |
fa2a1ce5 | 568 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) |
a7a167bf | 569 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 LT |
570 | |
571 | WRT_REG_WORD(®->ctrl_status, 0x40); | |
c81d04c9 | 572 | qla2xxx_read_window(reg, 32, fw->resp_dma_reg); |
1da177e4 LT |
573 | |
574 | WRT_REG_WORD(®->ctrl_status, 0x50); | |
c81d04c9 | 575 | qla2xxx_read_window(reg, 48, fw->dma_reg); |
1da177e4 LT |
576 | |
577 | WRT_REG_WORD(®->ctrl_status, 0x00); | |
c81d04c9 | 578 | dmp_reg = ®->risc_hw; |
fa2a1ce5 | 579 | for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) |
a7a167bf | 580 | fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 581 | |
fa2a1ce5 | 582 | WRT_REG_WORD(®->pcr, 0x2000); |
c81d04c9 | 583 | qla2xxx_read_window(reg, 16, fw->risc_gp0_reg); |
1da177e4 | 584 | |
fa2a1ce5 | 585 | WRT_REG_WORD(®->pcr, 0x2200); |
c81d04c9 | 586 | qla2xxx_read_window(reg, 16, fw->risc_gp1_reg); |
1da177e4 | 587 | |
fa2a1ce5 | 588 | WRT_REG_WORD(®->pcr, 0x2400); |
c81d04c9 | 589 | qla2xxx_read_window(reg, 16, fw->risc_gp2_reg); |
1da177e4 | 590 | |
fa2a1ce5 | 591 | WRT_REG_WORD(®->pcr, 0x2600); |
c81d04c9 | 592 | qla2xxx_read_window(reg, 16, fw->risc_gp3_reg); |
1da177e4 | 593 | |
fa2a1ce5 | 594 | WRT_REG_WORD(®->pcr, 0x2800); |
c81d04c9 | 595 | qla2xxx_read_window(reg, 16, fw->risc_gp4_reg); |
1da177e4 | 596 | |
fa2a1ce5 | 597 | WRT_REG_WORD(®->pcr, 0x2A00); |
c81d04c9 | 598 | qla2xxx_read_window(reg, 16, fw->risc_gp5_reg); |
1da177e4 | 599 | |
fa2a1ce5 | 600 | WRT_REG_WORD(®->pcr, 0x2C00); |
c81d04c9 | 601 | qla2xxx_read_window(reg, 16, fw->risc_gp6_reg); |
1da177e4 | 602 | |
fa2a1ce5 | 603 | WRT_REG_WORD(®->pcr, 0x2E00); |
c81d04c9 | 604 | qla2xxx_read_window(reg, 16, fw->risc_gp7_reg); |
1da177e4 | 605 | |
fa2a1ce5 | 606 | WRT_REG_WORD(®->ctrl_status, 0x10); |
c81d04c9 | 607 | qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg); |
1da177e4 | 608 | |
fa2a1ce5 | 609 | WRT_REG_WORD(®->ctrl_status, 0x20); |
c81d04c9 | 610 | qla2xxx_read_window(reg, 64, fw->fpm_b0_reg); |
1da177e4 | 611 | |
fa2a1ce5 | 612 | WRT_REG_WORD(®->ctrl_status, 0x30); |
c81d04c9 | 613 | qla2xxx_read_window(reg, 64, fw->fpm_b1_reg); |
1da177e4 LT |
614 | |
615 | /* Reset RISC. */ | |
616 | WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); | |
617 | for (cnt = 0; cnt < 30000; cnt++) { | |
618 | if ((RD_REG_WORD(®->ctrl_status) & | |
619 | CSR_ISP_SOFT_RESET) == 0) | |
620 | break; | |
621 | ||
622 | udelay(10); | |
623 | } | |
624 | } | |
625 | ||
626 | if (!IS_QLA2300(ha)) { | |
627 | for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && | |
628 | rval == QLA_SUCCESS; cnt--) { | |
629 | if (cnt) | |
630 | udelay(100); | |
631 | else | |
632 | rval = QLA_FUNCTION_TIMEOUT; | |
633 | } | |
634 | } | |
635 | ||
c5722708 AV |
636 | /* Get RISC SRAM. */ |
637 | if (rval == QLA_SUCCESS) | |
638 | rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram, | |
639 | sizeof(fw->risc_ram) / 2, &nxt); | |
1da177e4 | 640 | |
c5722708 AV |
641 | /* Get stack SRAM. */ |
642 | if (rval == QLA_SUCCESS) | |
643 | rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram, | |
644 | sizeof(fw->stack_ram) / 2, &nxt); | |
1da177e4 | 645 | |
c5722708 AV |
646 | /* Get data SRAM. */ |
647 | if (rval == QLA_SUCCESS) | |
648 | rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram, | |
649 | ha->fw_memory_size - 0x11000 + 1, &nxt); | |
1da177e4 | 650 | |
a7a167bf | 651 | if (rval == QLA_SUCCESS) |
73208dfd | 652 | qla2xxx_copy_queues(ha, nxt); |
a7a167bf | 653 | |
3420d36c | 654 | qla2xxx_dump_post_process(base_vha, rval); |
1da177e4 LT |
655 | |
656 | qla2300_fw_dump_failed: | |
657 | if (!hardware_locked) | |
658 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
659 | } | |
660 | ||
1da177e4 LT |
661 | /** |
662 | * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware. | |
663 | * @ha: HA context | |
664 | * @hardware_locked: Called with the hardware_lock | |
665 | */ | |
666 | void | |
7b867cf7 | 667 | qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
1da177e4 LT |
668 | { |
669 | int rval; | |
670 | uint32_t cnt, timer; | |
671 | uint16_t risc_address; | |
672 | uint16_t mb0, mb2; | |
7b867cf7 | 673 | struct qla_hw_data *ha = vha->hw; |
3d71644c | 674 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 LT |
675 | uint16_t __iomem *dmp_reg; |
676 | unsigned long flags; | |
677 | struct qla2100_fw_dump *fw; | |
73208dfd | 678 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
1da177e4 LT |
679 | |
680 | risc_address = 0; | |
681 | mb0 = mb2 = 0; | |
682 | flags = 0; | |
683 | ||
684 | if (!hardware_locked) | |
685 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
686 | ||
d4e3e04d | 687 | if (!ha->fw_dump) { |
7c3df132 SK |
688 | ql_log(ql_log_warn, vha, 0xd004, |
689 | "No buffer available for dump.\n"); | |
1da177e4 LT |
690 | goto qla2100_fw_dump_failed; |
691 | } | |
692 | ||
d4e3e04d | 693 | if (ha->fw_dumped) { |
7c3df132 SK |
694 | ql_log(ql_log_warn, vha, 0xd005, |
695 | "Firmware has been previously dumped (%p) " | |
696 | "-- ignoring request.\n", | |
697 | ha->fw_dump); | |
1da177e4 LT |
698 | goto qla2100_fw_dump_failed; |
699 | } | |
a7a167bf AV |
700 | fw = &ha->fw_dump->isp.isp21; |
701 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
1da177e4 LT |
702 | |
703 | rval = QLA_SUCCESS; | |
a7a167bf | 704 | fw->hccr = htons(RD_REG_WORD(®->hccr)); |
1da177e4 LT |
705 | |
706 | /* Pause RISC. */ | |
fa2a1ce5 | 707 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); |
1da177e4 LT |
708 | for (cnt = 30000; (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && |
709 | rval == QLA_SUCCESS; cnt--) { | |
710 | if (cnt) | |
711 | udelay(100); | |
712 | else | |
713 | rval = QLA_FUNCTION_TIMEOUT; | |
714 | } | |
715 | if (rval == QLA_SUCCESS) { | |
c81d04c9 | 716 | dmp_reg = ®->flash_address; |
fa2a1ce5 | 717 | for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) |
a7a167bf | 718 | fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 719 | |
c81d04c9 | 720 | dmp_reg = ®->u.isp2100.mailbox0; |
1da177e4 | 721 | for (cnt = 0; cnt < ha->mbx_count; cnt++) { |
c81d04c9 AV |
722 | if (cnt == 8) |
723 | dmp_reg = ®->u_end.isp2200.mailbox8; | |
724 | ||
a7a167bf | 725 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 LT |
726 | } |
727 | ||
c81d04c9 | 728 | dmp_reg = ®->u.isp2100.unused_2[0]; |
fa2a1ce5 | 729 | for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++) |
a7a167bf | 730 | fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 LT |
731 | |
732 | WRT_REG_WORD(®->ctrl_status, 0x00); | |
c81d04c9 | 733 | dmp_reg = ®->risc_hw; |
fa2a1ce5 | 734 | for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) |
a7a167bf | 735 | fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 736 | |
fa2a1ce5 | 737 | WRT_REG_WORD(®->pcr, 0x2000); |
c81d04c9 | 738 | qla2xxx_read_window(reg, 16, fw->risc_gp0_reg); |
1da177e4 | 739 | |
fa2a1ce5 | 740 | WRT_REG_WORD(®->pcr, 0x2100); |
c81d04c9 | 741 | qla2xxx_read_window(reg, 16, fw->risc_gp1_reg); |
1da177e4 | 742 | |
fa2a1ce5 | 743 | WRT_REG_WORD(®->pcr, 0x2200); |
c81d04c9 | 744 | qla2xxx_read_window(reg, 16, fw->risc_gp2_reg); |
1da177e4 | 745 | |
fa2a1ce5 | 746 | WRT_REG_WORD(®->pcr, 0x2300); |
c81d04c9 | 747 | qla2xxx_read_window(reg, 16, fw->risc_gp3_reg); |
1da177e4 | 748 | |
fa2a1ce5 | 749 | WRT_REG_WORD(®->pcr, 0x2400); |
c81d04c9 | 750 | qla2xxx_read_window(reg, 16, fw->risc_gp4_reg); |
1da177e4 | 751 | |
fa2a1ce5 | 752 | WRT_REG_WORD(®->pcr, 0x2500); |
c81d04c9 | 753 | qla2xxx_read_window(reg, 16, fw->risc_gp5_reg); |
1da177e4 | 754 | |
fa2a1ce5 | 755 | WRT_REG_WORD(®->pcr, 0x2600); |
c81d04c9 | 756 | qla2xxx_read_window(reg, 16, fw->risc_gp6_reg); |
1da177e4 | 757 | |
fa2a1ce5 | 758 | WRT_REG_WORD(®->pcr, 0x2700); |
c81d04c9 | 759 | qla2xxx_read_window(reg, 16, fw->risc_gp7_reg); |
1da177e4 | 760 | |
fa2a1ce5 | 761 | WRT_REG_WORD(®->ctrl_status, 0x10); |
c81d04c9 | 762 | qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg); |
1da177e4 | 763 | |
fa2a1ce5 | 764 | WRT_REG_WORD(®->ctrl_status, 0x20); |
c81d04c9 | 765 | qla2xxx_read_window(reg, 64, fw->fpm_b0_reg); |
1da177e4 | 766 | |
fa2a1ce5 | 767 | WRT_REG_WORD(®->ctrl_status, 0x30); |
c81d04c9 | 768 | qla2xxx_read_window(reg, 64, fw->fpm_b1_reg); |
1da177e4 LT |
769 | |
770 | /* Reset the ISP. */ | |
771 | WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); | |
772 | } | |
773 | ||
774 | for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && | |
775 | rval == QLA_SUCCESS; cnt--) { | |
776 | if (cnt) | |
777 | udelay(100); | |
778 | else | |
779 | rval = QLA_FUNCTION_TIMEOUT; | |
780 | } | |
781 | ||
782 | /* Pause RISC. */ | |
783 | if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) && | |
784 | (RD_REG_WORD(®->mctr) & (BIT_1 | BIT_0)) != 0))) { | |
785 | ||
fa2a1ce5 | 786 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); |
1da177e4 LT |
787 | for (cnt = 30000; |
788 | (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && | |
789 | rval == QLA_SUCCESS; cnt--) { | |
790 | if (cnt) | |
791 | udelay(100); | |
792 | else | |
793 | rval = QLA_FUNCTION_TIMEOUT; | |
794 | } | |
795 | if (rval == QLA_SUCCESS) { | |
796 | /* Set memory configuration and timing. */ | |
797 | if (IS_QLA2100(ha)) | |
798 | WRT_REG_WORD(®->mctr, 0xf1); | |
799 | else | |
800 | WRT_REG_WORD(®->mctr, 0xf2); | |
801 | RD_REG_WORD(®->mctr); /* PCI Posting. */ | |
802 | ||
803 | /* Release RISC. */ | |
804 | WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); | |
805 | } | |
806 | } | |
807 | ||
808 | if (rval == QLA_SUCCESS) { | |
809 | /* Get RISC SRAM. */ | |
810 | risc_address = 0x1000; | |
811 | WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD); | |
812 | clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | |
813 | } | |
814 | for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS; | |
815 | cnt++, risc_address++) { | |
816 | WRT_MAILBOX_REG(ha, reg, 1, risc_address); | |
817 | WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); | |
818 | ||
819 | for (timer = 6000000; timer != 0; timer--) { | |
820 | /* Check for pending interrupts. */ | |
821 | if (RD_REG_WORD(®->istatus) & ISR_RISC_INT) { | |
822 | if (RD_REG_WORD(®->semaphore) & BIT_0) { | |
823 | set_bit(MBX_INTERRUPT, | |
824 | &ha->mbx_cmd_flags); | |
825 | ||
826 | mb0 = RD_MAILBOX_REG(ha, reg, 0); | |
827 | mb2 = RD_MAILBOX_REG(ha, reg, 2); | |
828 | ||
829 | WRT_REG_WORD(®->semaphore, 0); | |
830 | WRT_REG_WORD(®->hccr, | |
831 | HCCR_CLR_RISC_INT); | |
832 | RD_REG_WORD(®->hccr); | |
833 | break; | |
834 | } | |
835 | WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); | |
836 | RD_REG_WORD(®->hccr); | |
837 | } | |
838 | udelay(5); | |
839 | } | |
840 | ||
841 | if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { | |
842 | rval = mb0 & MBS_MASK; | |
a7a167bf | 843 | fw->risc_ram[cnt] = htons(mb2); |
1da177e4 LT |
844 | } else { |
845 | rval = QLA_FUNCTION_FAILED; | |
846 | } | |
847 | } | |
848 | ||
a7a167bf | 849 | if (rval == QLA_SUCCESS) |
73208dfd | 850 | qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]); |
a7a167bf | 851 | |
3420d36c | 852 | qla2xxx_dump_post_process(base_vha, rval); |
1da177e4 LT |
853 | |
854 | qla2100_fw_dump_failed: | |
855 | if (!hardware_locked) | |
856 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
857 | } | |
858 | ||
6d9b61ed | 859 | void |
7b867cf7 | 860 | qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
6d9b61ed AV |
861 | { |
862 | int rval; | |
c3a2f0df | 863 | uint32_t cnt; |
6d9b61ed | 864 | uint32_t risc_address; |
7b867cf7 | 865 | struct qla_hw_data *ha = vha->hw; |
6d9b61ed AV |
866 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
867 | uint32_t __iomem *dmp_reg; | |
868 | uint32_t *iter_reg; | |
869 | uint16_t __iomem *mbx_reg; | |
870 | unsigned long flags; | |
871 | struct qla24xx_fw_dump *fw; | |
872 | uint32_t ext_mem_cnt; | |
c3a2f0df | 873 | void *nxt; |
73208dfd | 874 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
6d9b61ed | 875 | |
a9083016 GM |
876 | if (IS_QLA82XX(ha)) |
877 | return; | |
878 | ||
6d9b61ed | 879 | risc_address = ext_mem_cnt = 0; |
6d9b61ed AV |
880 | flags = 0; |
881 | ||
882 | if (!hardware_locked) | |
883 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
884 | ||
d4e3e04d | 885 | if (!ha->fw_dump) { |
7c3df132 SK |
886 | ql_log(ql_log_warn, vha, 0xd006, |
887 | "No buffer available for dump.\n"); | |
6d9b61ed AV |
888 | goto qla24xx_fw_dump_failed; |
889 | } | |
890 | ||
891 | if (ha->fw_dumped) { | |
7c3df132 SK |
892 | ql_log(ql_log_warn, vha, 0xd007, |
893 | "Firmware has been previously dumped (%p) " | |
894 | "-- ignoring request.\n", | |
895 | ha->fw_dump); | |
6d9b61ed AV |
896 | goto qla24xx_fw_dump_failed; |
897 | } | |
a7a167bf AV |
898 | fw = &ha->fw_dump->isp.isp24; |
899 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
6d9b61ed | 900 | |
a7a167bf | 901 | fw->host_status = htonl(RD_REG_DWORD(®->host_status)); |
6d9b61ed AV |
902 | |
903 | /* Pause RISC. */ | |
c81d04c9 AV |
904 | rval = qla24xx_pause_risc(reg); |
905 | if (rval != QLA_SUCCESS) | |
906 | goto qla24xx_fw_dump_failed_0; | |
907 | ||
908 | /* Host interface registers. */ | |
909 | dmp_reg = ®->flash_addr; | |
910 | for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) | |
911 | fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); | |
912 | ||
913 | /* Disable interrupts. */ | |
914 | WRT_REG_DWORD(®->ictrl, 0); | |
915 | RD_REG_DWORD(®->ictrl); | |
916 | ||
917 | /* Shadow registers. */ | |
918 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); | |
919 | RD_REG_DWORD(®->iobase_addr); | |
920 | WRT_REG_DWORD(®->iobase_select, 0xB0000000); | |
921 | fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
922 | ||
923 | WRT_REG_DWORD(®->iobase_select, 0xB0100000); | |
924 | fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
925 | ||
926 | WRT_REG_DWORD(®->iobase_select, 0xB0200000); | |
927 | fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
928 | ||
929 | WRT_REG_DWORD(®->iobase_select, 0xB0300000); | |
930 | fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
931 | ||
932 | WRT_REG_DWORD(®->iobase_select, 0xB0400000); | |
933 | fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
934 | ||
935 | WRT_REG_DWORD(®->iobase_select, 0xB0500000); | |
936 | fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
937 | ||
938 | WRT_REG_DWORD(®->iobase_select, 0xB0600000); | |
939 | fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
940 | ||
941 | /* Mailbox registers. */ | |
942 | mbx_reg = ®->mailbox0; | |
943 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) | |
944 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); | |
945 | ||
946 | /* Transfer sequence registers. */ | |
947 | iter_reg = fw->xseq_gp_reg; | |
948 | iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); | |
949 | iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); | |
950 | iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); | |
951 | iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); | |
952 | iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); | |
953 | iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); | |
954 | iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); | |
955 | qla24xx_read_window(reg, 0xBF70, 16, iter_reg); | |
956 | ||
957 | qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg); | |
958 | qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); | |
959 | ||
960 | /* Receive sequence registers. */ | |
961 | iter_reg = fw->rseq_gp_reg; | |
962 | iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); | |
963 | iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); | |
964 | iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); | |
965 | iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); | |
966 | iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); | |
967 | iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); | |
968 | iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); | |
969 | qla24xx_read_window(reg, 0xFF70, 16, iter_reg); | |
970 | ||
971 | qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg); | |
972 | qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); | |
973 | qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); | |
974 | ||
975 | /* Command DMA registers. */ | |
976 | qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); | |
977 | ||
978 | /* Queues. */ | |
979 | iter_reg = fw->req0_dma_reg; | |
980 | iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); | |
981 | dmp_reg = ®->iobase_q; | |
982 | for (cnt = 0; cnt < 7; cnt++) | |
983 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
984 | ||
985 | iter_reg = fw->resp0_dma_reg; | |
986 | iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); | |
987 | dmp_reg = ®->iobase_q; | |
988 | for (cnt = 0; cnt < 7; cnt++) | |
989 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
990 | ||
991 | iter_reg = fw->req1_dma_reg; | |
992 | iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); | |
993 | dmp_reg = ®->iobase_q; | |
994 | for (cnt = 0; cnt < 7; cnt++) | |
995 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
996 | ||
997 | /* Transmit DMA registers. */ | |
998 | iter_reg = fw->xmt0_dma_reg; | |
999 | iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); | |
1000 | qla24xx_read_window(reg, 0x7610, 16, iter_reg); | |
1001 | ||
1002 | iter_reg = fw->xmt1_dma_reg; | |
1003 | iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); | |
1004 | qla24xx_read_window(reg, 0x7630, 16, iter_reg); | |
1005 | ||
1006 | iter_reg = fw->xmt2_dma_reg; | |
1007 | iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); | |
1008 | qla24xx_read_window(reg, 0x7650, 16, iter_reg); | |
1009 | ||
1010 | iter_reg = fw->xmt3_dma_reg; | |
1011 | iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); | |
1012 | qla24xx_read_window(reg, 0x7670, 16, iter_reg); | |
1013 | ||
1014 | iter_reg = fw->xmt4_dma_reg; | |
1015 | iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); | |
1016 | qla24xx_read_window(reg, 0x7690, 16, iter_reg); | |
1017 | ||
1018 | qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); | |
1019 | ||
1020 | /* Receive DMA registers. */ | |
1021 | iter_reg = fw->rcvt0_data_dma_reg; | |
1022 | iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); | |
1023 | qla24xx_read_window(reg, 0x7710, 16, iter_reg); | |
1024 | ||
1025 | iter_reg = fw->rcvt1_data_dma_reg; | |
1026 | iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); | |
1027 | qla24xx_read_window(reg, 0x7730, 16, iter_reg); | |
1028 | ||
1029 | /* RISC registers. */ | |
1030 | iter_reg = fw->risc_gp_reg; | |
1031 | iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); | |
1032 | iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); | |
1033 | iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); | |
1034 | iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); | |
1035 | iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); | |
1036 | iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); | |
1037 | iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); | |
1038 | qla24xx_read_window(reg, 0x0F70, 16, iter_reg); | |
1039 | ||
1040 | /* Local memory controller registers. */ | |
1041 | iter_reg = fw->lmc_reg; | |
1042 | iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); | |
1043 | iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); | |
1044 | iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); | |
1045 | iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); | |
1046 | iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); | |
1047 | iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); | |
1048 | qla24xx_read_window(reg, 0x3060, 16, iter_reg); | |
1049 | ||
1050 | /* Fibre Protocol Module registers. */ | |
1051 | iter_reg = fw->fpm_hdw_reg; | |
1052 | iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); | |
1053 | iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); | |
1054 | iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); | |
1055 | iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); | |
1056 | iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); | |
1057 | iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); | |
1058 | iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); | |
1059 | iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); | |
1060 | iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); | |
1061 | iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); | |
1062 | iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); | |
1063 | qla24xx_read_window(reg, 0x40B0, 16, iter_reg); | |
1064 | ||
1065 | /* Frame Buffer registers. */ | |
1066 | iter_reg = fw->fb_hdw_reg; | |
1067 | iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); | |
1068 | iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); | |
1069 | iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); | |
1070 | iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); | |
1071 | iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); | |
1072 | iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); | |
1073 | iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); | |
1074 | iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); | |
1075 | iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); | |
1076 | iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); | |
1077 | qla24xx_read_window(reg, 0x61B0, 16, iter_reg); | |
1078 | ||
1079 | rval = qla24xx_soft_reset(ha); | |
1080 | if (rval != QLA_SUCCESS) | |
1081 | goto qla24xx_fw_dump_failed_0; | |
1082 | ||
1083 | rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), | |
c5722708 | 1084 | &nxt); |
c81d04c9 AV |
1085 | if (rval != QLA_SUCCESS) |
1086 | goto qla24xx_fw_dump_failed_0; | |
1087 | ||
73208dfd | 1088 | nxt = qla2xxx_copy_queues(ha, nxt); |
bb99de67 AV |
1089 | |
1090 | qla24xx_copy_eft(ha, nxt); | |
c81d04c9 AV |
1091 | |
1092 | qla24xx_fw_dump_failed_0: | |
3420d36c | 1093 | qla2xxx_dump_post_process(base_vha, rval); |
6d9b61ed | 1094 | |
c3a2f0df AV |
1095 | qla24xx_fw_dump_failed: |
1096 | if (!hardware_locked) | |
1097 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1098 | } | |
6d9b61ed | 1099 | |
c3a2f0df | 1100 | void |
7b867cf7 | 1101 | qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
c3a2f0df AV |
1102 | { |
1103 | int rval; | |
1104 | uint32_t cnt; | |
1105 | uint32_t risc_address; | |
7b867cf7 | 1106 | struct qla_hw_data *ha = vha->hw; |
c3a2f0df AV |
1107 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
1108 | uint32_t __iomem *dmp_reg; | |
1109 | uint32_t *iter_reg; | |
1110 | uint16_t __iomem *mbx_reg; | |
1111 | unsigned long flags; | |
1112 | struct qla25xx_fw_dump *fw; | |
1113 | uint32_t ext_mem_cnt; | |
d63ab533 | 1114 | void *nxt, *nxt_chain; |
bb99de67 | 1115 | uint32_t *last_chain = NULL; |
73208dfd | 1116 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
6d9b61ed | 1117 | |
c3a2f0df AV |
1118 | risc_address = ext_mem_cnt = 0; |
1119 | flags = 0; | |
6d9b61ed | 1120 | |
c3a2f0df AV |
1121 | if (!hardware_locked) |
1122 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
6d9b61ed | 1123 | |
c3a2f0df | 1124 | if (!ha->fw_dump) { |
7c3df132 SK |
1125 | ql_log(ql_log_warn, vha, 0xd008, |
1126 | "No buffer available for dump.\n"); | |
c3a2f0df AV |
1127 | goto qla25xx_fw_dump_failed; |
1128 | } | |
6d9b61ed | 1129 | |
c3a2f0df | 1130 | if (ha->fw_dumped) { |
7c3df132 SK |
1131 | ql_log(ql_log_warn, vha, 0xd009, |
1132 | "Firmware has been previously dumped (%p) " | |
1133 | "-- ignoring request.\n", | |
1134 | ha->fw_dump); | |
c3a2f0df AV |
1135 | goto qla25xx_fw_dump_failed; |
1136 | } | |
1137 | fw = &ha->fw_dump->isp.isp25; | |
1138 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
b5836927 | 1139 | ha->fw_dump->version = __constant_htonl(2); |
6d9b61ed | 1140 | |
c3a2f0df | 1141 | fw->host_status = htonl(RD_REG_DWORD(®->host_status)); |
6d9b61ed | 1142 | |
c3a2f0df | 1143 | /* Pause RISC. */ |
c81d04c9 AV |
1144 | rval = qla24xx_pause_risc(reg); |
1145 | if (rval != QLA_SUCCESS) | |
1146 | goto qla25xx_fw_dump_failed_0; | |
1147 | ||
b5836927 AV |
1148 | /* Host/Risc registers. */ |
1149 | iter_reg = fw->host_risc_reg; | |
1150 | iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); | |
1151 | qla24xx_read_window(reg, 0x7010, 16, iter_reg); | |
1152 | ||
1153 | /* PCIe registers. */ | |
1154 | WRT_REG_DWORD(®->iobase_addr, 0x7C00); | |
1155 | RD_REG_DWORD(®->iobase_addr); | |
1156 | WRT_REG_DWORD(®->iobase_window, 0x01); | |
1157 | dmp_reg = ®->iobase_c4; | |
1158 | fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1159 | fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1160 | fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); | |
1161 | fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); | |
73208dfd | 1162 | |
b5836927 AV |
1163 | WRT_REG_DWORD(®->iobase_window, 0x00); |
1164 | RD_REG_DWORD(®->iobase_window); | |
1165 | ||
c81d04c9 AV |
1166 | /* Host interface registers. */ |
1167 | dmp_reg = ®->flash_addr; | |
1168 | for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) | |
1169 | fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1170 | ||
1171 | /* Disable interrupts. */ | |
1172 | WRT_REG_DWORD(®->ictrl, 0); | |
1173 | RD_REG_DWORD(®->ictrl); | |
1174 | ||
1175 | /* Shadow registers. */ | |
1176 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); | |
1177 | RD_REG_DWORD(®->iobase_addr); | |
1178 | WRT_REG_DWORD(®->iobase_select, 0xB0000000); | |
1179 | fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1180 | ||
1181 | WRT_REG_DWORD(®->iobase_select, 0xB0100000); | |
1182 | fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1183 | ||
1184 | WRT_REG_DWORD(®->iobase_select, 0xB0200000); | |
1185 | fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1186 | ||
1187 | WRT_REG_DWORD(®->iobase_select, 0xB0300000); | |
1188 | fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1189 | ||
1190 | WRT_REG_DWORD(®->iobase_select, 0xB0400000); | |
1191 | fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1192 | ||
1193 | WRT_REG_DWORD(®->iobase_select, 0xB0500000); | |
1194 | fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1195 | ||
1196 | WRT_REG_DWORD(®->iobase_select, 0xB0600000); | |
1197 | fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1198 | ||
1199 | WRT_REG_DWORD(®->iobase_select, 0xB0700000); | |
1200 | fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1201 | ||
1202 | WRT_REG_DWORD(®->iobase_select, 0xB0800000); | |
1203 | fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1204 | ||
1205 | WRT_REG_DWORD(®->iobase_select, 0xB0900000); | |
1206 | fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1207 | ||
1208 | WRT_REG_DWORD(®->iobase_select, 0xB0A00000); | |
1209 | fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1210 | ||
1211 | /* RISC I/O register. */ | |
1212 | WRT_REG_DWORD(®->iobase_addr, 0x0010); | |
1213 | fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); | |
1214 | ||
1215 | /* Mailbox registers. */ | |
1216 | mbx_reg = ®->mailbox0; | |
1217 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) | |
1218 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); | |
1219 | ||
1220 | /* Transfer sequence registers. */ | |
1221 | iter_reg = fw->xseq_gp_reg; | |
1222 | iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); | |
1223 | iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); | |
1224 | iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); | |
1225 | iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); | |
1226 | iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); | |
1227 | iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); | |
1228 | iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); | |
1229 | qla24xx_read_window(reg, 0xBF70, 16, iter_reg); | |
1230 | ||
1231 | iter_reg = fw->xseq_0_reg; | |
1232 | iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); | |
1233 | iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); | |
1234 | qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); | |
1235 | ||
1236 | qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); | |
1237 | ||
1238 | /* Receive sequence registers. */ | |
1239 | iter_reg = fw->rseq_gp_reg; | |
1240 | iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); | |
1241 | iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); | |
1242 | iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); | |
1243 | iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); | |
1244 | iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); | |
1245 | iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); | |
1246 | iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); | |
1247 | qla24xx_read_window(reg, 0xFF70, 16, iter_reg); | |
1248 | ||
1249 | iter_reg = fw->rseq_0_reg; | |
1250 | iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); | |
1251 | qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); | |
1252 | ||
1253 | qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); | |
1254 | qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); | |
1255 | ||
1256 | /* Auxiliary sequence registers. */ | |
1257 | iter_reg = fw->aseq_gp_reg; | |
1258 | iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); | |
1259 | iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); | |
1260 | iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); | |
1261 | iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); | |
1262 | iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); | |
1263 | iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); | |
1264 | iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); | |
1265 | qla24xx_read_window(reg, 0xB070, 16, iter_reg); | |
1266 | ||
1267 | iter_reg = fw->aseq_0_reg; | |
1268 | iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); | |
1269 | qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); | |
1270 | ||
1271 | qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); | |
1272 | qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); | |
1273 | ||
1274 | /* Command DMA registers. */ | |
1275 | qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); | |
1276 | ||
1277 | /* Queues. */ | |
1278 | iter_reg = fw->req0_dma_reg; | |
1279 | iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); | |
1280 | dmp_reg = ®->iobase_q; | |
1281 | for (cnt = 0; cnt < 7; cnt++) | |
1282 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1283 | ||
1284 | iter_reg = fw->resp0_dma_reg; | |
1285 | iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); | |
1286 | dmp_reg = ®->iobase_q; | |
1287 | for (cnt = 0; cnt < 7; cnt++) | |
1288 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1289 | ||
1290 | iter_reg = fw->req1_dma_reg; | |
1291 | iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); | |
1292 | dmp_reg = ®->iobase_q; | |
1293 | for (cnt = 0; cnt < 7; cnt++) | |
1294 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1295 | ||
1296 | /* Transmit DMA registers. */ | |
1297 | iter_reg = fw->xmt0_dma_reg; | |
1298 | iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); | |
1299 | qla24xx_read_window(reg, 0x7610, 16, iter_reg); | |
1300 | ||
1301 | iter_reg = fw->xmt1_dma_reg; | |
1302 | iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); | |
1303 | qla24xx_read_window(reg, 0x7630, 16, iter_reg); | |
1304 | ||
1305 | iter_reg = fw->xmt2_dma_reg; | |
1306 | iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); | |
1307 | qla24xx_read_window(reg, 0x7650, 16, iter_reg); | |
1308 | ||
1309 | iter_reg = fw->xmt3_dma_reg; | |
1310 | iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); | |
1311 | qla24xx_read_window(reg, 0x7670, 16, iter_reg); | |
1312 | ||
1313 | iter_reg = fw->xmt4_dma_reg; | |
1314 | iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); | |
1315 | qla24xx_read_window(reg, 0x7690, 16, iter_reg); | |
1316 | ||
1317 | qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); | |
1318 | ||
1319 | /* Receive DMA registers. */ | |
1320 | iter_reg = fw->rcvt0_data_dma_reg; | |
1321 | iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); | |
1322 | qla24xx_read_window(reg, 0x7710, 16, iter_reg); | |
1323 | ||
1324 | iter_reg = fw->rcvt1_data_dma_reg; | |
1325 | iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); | |
1326 | qla24xx_read_window(reg, 0x7730, 16, iter_reg); | |
1327 | ||
1328 | /* RISC registers. */ | |
1329 | iter_reg = fw->risc_gp_reg; | |
1330 | iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); | |
1331 | iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); | |
1332 | iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); | |
1333 | iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); | |
1334 | iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); | |
1335 | iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); | |
1336 | iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); | |
1337 | qla24xx_read_window(reg, 0x0F70, 16, iter_reg); | |
1338 | ||
1339 | /* Local memory controller registers. */ | |
1340 | iter_reg = fw->lmc_reg; | |
1341 | iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); | |
1342 | iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); | |
1343 | iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); | |
1344 | iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); | |
1345 | iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); | |
1346 | iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); | |
1347 | iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); | |
1348 | qla24xx_read_window(reg, 0x3070, 16, iter_reg); | |
1349 | ||
1350 | /* Fibre Protocol Module registers. */ | |
1351 | iter_reg = fw->fpm_hdw_reg; | |
1352 | iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); | |
1353 | iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); | |
1354 | iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); | |
1355 | iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); | |
1356 | iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); | |
1357 | iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); | |
1358 | iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); | |
1359 | iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); | |
1360 | iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); | |
1361 | iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); | |
1362 | iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); | |
1363 | qla24xx_read_window(reg, 0x40B0, 16, iter_reg); | |
1364 | ||
1365 | /* Frame Buffer registers. */ | |
1366 | iter_reg = fw->fb_hdw_reg; | |
1367 | iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); | |
1368 | iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); | |
1369 | iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); | |
1370 | iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); | |
1371 | iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); | |
1372 | iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); | |
1373 | iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); | |
1374 | iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); | |
1375 | iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); | |
1376 | iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); | |
1377 | iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); | |
1378 | qla24xx_read_window(reg, 0x6F00, 16, iter_reg); | |
1379 | ||
d63ab533 AV |
1380 | /* Multi queue registers */ |
1381 | nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, | |
1382 | &last_chain); | |
1383 | ||
c81d04c9 AV |
1384 | rval = qla24xx_soft_reset(ha); |
1385 | if (rval != QLA_SUCCESS) | |
1386 | goto qla25xx_fw_dump_failed_0; | |
1387 | ||
1388 | rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), | |
c5722708 | 1389 | &nxt); |
c81d04c9 AV |
1390 | if (rval != QLA_SUCCESS) |
1391 | goto qla25xx_fw_dump_failed_0; | |
1392 | ||
73208dfd | 1393 | nxt = qla2xxx_copy_queues(ha, nxt); |
c81d04c9 | 1394 | |
bb99de67 | 1395 | nxt = qla24xx_copy_eft(ha, nxt); |
df613b96 | 1396 | |
d63ab533 | 1397 | /* Chain entries -- started with MQ. */ |
050c9bb1 GM |
1398 | nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain); |
1399 | nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain); | |
bb99de67 AV |
1400 | if (last_chain) { |
1401 | ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT); | |
1402 | *last_chain |= __constant_htonl(DUMP_CHAIN_LAST); | |
1403 | } | |
df613b96 | 1404 | |
050c9bb1 GM |
1405 | /* Adjust valid length. */ |
1406 | ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); | |
1407 | ||
c81d04c9 | 1408 | qla25xx_fw_dump_failed_0: |
3420d36c | 1409 | qla2xxx_dump_post_process(base_vha, rval); |
6d9b61ed | 1410 | |
c3a2f0df | 1411 | qla25xx_fw_dump_failed: |
6d9b61ed AV |
1412 | if (!hardware_locked) |
1413 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1414 | } | |
3a03eb79 AV |
1415 | |
1416 | void | |
1417 | qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) | |
1418 | { | |
1419 | int rval; | |
1420 | uint32_t cnt; | |
1421 | uint32_t risc_address; | |
1422 | struct qla_hw_data *ha = vha->hw; | |
1423 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
1424 | uint32_t __iomem *dmp_reg; | |
1425 | uint32_t *iter_reg; | |
1426 | uint16_t __iomem *mbx_reg; | |
1427 | unsigned long flags; | |
1428 | struct qla81xx_fw_dump *fw; | |
1429 | uint32_t ext_mem_cnt; | |
1430 | void *nxt, *nxt_chain; | |
1431 | uint32_t *last_chain = NULL; | |
1432 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); | |
1433 | ||
1434 | risc_address = ext_mem_cnt = 0; | |
1435 | flags = 0; | |
1436 | ||
1437 | if (!hardware_locked) | |
1438 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1439 | ||
1440 | if (!ha->fw_dump) { | |
7c3df132 SK |
1441 | ql_log(ql_log_warn, vha, 0xd00a, |
1442 | "No buffer available for dump.\n"); | |
3a03eb79 AV |
1443 | goto qla81xx_fw_dump_failed; |
1444 | } | |
1445 | ||
1446 | if (ha->fw_dumped) { | |
7c3df132 SK |
1447 | ql_log(ql_log_warn, vha, 0xd00b, |
1448 | "Firmware has been previously dumped (%p) " | |
1449 | "-- ignoring request.\n", | |
1450 | ha->fw_dump); | |
3a03eb79 AV |
1451 | goto qla81xx_fw_dump_failed; |
1452 | } | |
1453 | fw = &ha->fw_dump->isp.isp81; | |
1454 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
1455 | ||
1456 | fw->host_status = htonl(RD_REG_DWORD(®->host_status)); | |
1457 | ||
1458 | /* Pause RISC. */ | |
1459 | rval = qla24xx_pause_risc(reg); | |
1460 | if (rval != QLA_SUCCESS) | |
1461 | goto qla81xx_fw_dump_failed_0; | |
1462 | ||
1463 | /* Host/Risc registers. */ | |
1464 | iter_reg = fw->host_risc_reg; | |
1465 | iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); | |
1466 | qla24xx_read_window(reg, 0x7010, 16, iter_reg); | |
1467 | ||
1468 | /* PCIe registers. */ | |
1469 | WRT_REG_DWORD(®->iobase_addr, 0x7C00); | |
1470 | RD_REG_DWORD(®->iobase_addr); | |
1471 | WRT_REG_DWORD(®->iobase_window, 0x01); | |
1472 | dmp_reg = ®->iobase_c4; | |
1473 | fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1474 | fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1475 | fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); | |
1476 | fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); | |
1477 | ||
1478 | WRT_REG_DWORD(®->iobase_window, 0x00); | |
1479 | RD_REG_DWORD(®->iobase_window); | |
1480 | ||
1481 | /* Host interface registers. */ | |
1482 | dmp_reg = ®->flash_addr; | |
1483 | for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) | |
1484 | fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1485 | ||
1486 | /* Disable interrupts. */ | |
1487 | WRT_REG_DWORD(®->ictrl, 0); | |
1488 | RD_REG_DWORD(®->ictrl); | |
1489 | ||
1490 | /* Shadow registers. */ | |
1491 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); | |
1492 | RD_REG_DWORD(®->iobase_addr); | |
1493 | WRT_REG_DWORD(®->iobase_select, 0xB0000000); | |
1494 | fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1495 | ||
1496 | WRT_REG_DWORD(®->iobase_select, 0xB0100000); | |
1497 | fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1498 | ||
1499 | WRT_REG_DWORD(®->iobase_select, 0xB0200000); | |
1500 | fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1501 | ||
1502 | WRT_REG_DWORD(®->iobase_select, 0xB0300000); | |
1503 | fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1504 | ||
1505 | WRT_REG_DWORD(®->iobase_select, 0xB0400000); | |
1506 | fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1507 | ||
1508 | WRT_REG_DWORD(®->iobase_select, 0xB0500000); | |
1509 | fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1510 | ||
1511 | WRT_REG_DWORD(®->iobase_select, 0xB0600000); | |
1512 | fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1513 | ||
1514 | WRT_REG_DWORD(®->iobase_select, 0xB0700000); | |
1515 | fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1516 | ||
1517 | WRT_REG_DWORD(®->iobase_select, 0xB0800000); | |
1518 | fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1519 | ||
1520 | WRT_REG_DWORD(®->iobase_select, 0xB0900000); | |
1521 | fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1522 | ||
1523 | WRT_REG_DWORD(®->iobase_select, 0xB0A00000); | |
1524 | fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1525 | ||
1526 | /* RISC I/O register. */ | |
1527 | WRT_REG_DWORD(®->iobase_addr, 0x0010); | |
1528 | fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); | |
1529 | ||
1530 | /* Mailbox registers. */ | |
1531 | mbx_reg = ®->mailbox0; | |
1532 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) | |
1533 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); | |
1534 | ||
1535 | /* Transfer sequence registers. */ | |
1536 | iter_reg = fw->xseq_gp_reg; | |
1537 | iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); | |
1538 | iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); | |
1539 | iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); | |
1540 | iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); | |
1541 | iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); | |
1542 | iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); | |
1543 | iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); | |
1544 | qla24xx_read_window(reg, 0xBF70, 16, iter_reg); | |
1545 | ||
1546 | iter_reg = fw->xseq_0_reg; | |
1547 | iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); | |
1548 | iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); | |
1549 | qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); | |
1550 | ||
1551 | qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); | |
1552 | ||
1553 | /* Receive sequence registers. */ | |
1554 | iter_reg = fw->rseq_gp_reg; | |
1555 | iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); | |
1556 | iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); | |
1557 | iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); | |
1558 | iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); | |
1559 | iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); | |
1560 | iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); | |
1561 | iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); | |
1562 | qla24xx_read_window(reg, 0xFF70, 16, iter_reg); | |
1563 | ||
1564 | iter_reg = fw->rseq_0_reg; | |
1565 | iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); | |
1566 | qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); | |
1567 | ||
1568 | qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); | |
1569 | qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); | |
1570 | ||
1571 | /* Auxiliary sequence registers. */ | |
1572 | iter_reg = fw->aseq_gp_reg; | |
1573 | iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); | |
1574 | iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); | |
1575 | iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); | |
1576 | iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); | |
1577 | iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); | |
1578 | iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); | |
1579 | iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); | |
1580 | qla24xx_read_window(reg, 0xB070, 16, iter_reg); | |
1581 | ||
1582 | iter_reg = fw->aseq_0_reg; | |
1583 | iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); | |
1584 | qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); | |
1585 | ||
1586 | qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); | |
1587 | qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); | |
1588 | ||
1589 | /* Command DMA registers. */ | |
1590 | qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); | |
1591 | ||
1592 | /* Queues. */ | |
1593 | iter_reg = fw->req0_dma_reg; | |
1594 | iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); | |
1595 | dmp_reg = ®->iobase_q; | |
1596 | for (cnt = 0; cnt < 7; cnt++) | |
1597 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1598 | ||
1599 | iter_reg = fw->resp0_dma_reg; | |
1600 | iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); | |
1601 | dmp_reg = ®->iobase_q; | |
1602 | for (cnt = 0; cnt < 7; cnt++) | |
1603 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1604 | ||
1605 | iter_reg = fw->req1_dma_reg; | |
1606 | iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); | |
1607 | dmp_reg = ®->iobase_q; | |
1608 | for (cnt = 0; cnt < 7; cnt++) | |
1609 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1610 | ||
1611 | /* Transmit DMA registers. */ | |
1612 | iter_reg = fw->xmt0_dma_reg; | |
1613 | iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); | |
1614 | qla24xx_read_window(reg, 0x7610, 16, iter_reg); | |
1615 | ||
1616 | iter_reg = fw->xmt1_dma_reg; | |
1617 | iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); | |
1618 | qla24xx_read_window(reg, 0x7630, 16, iter_reg); | |
1619 | ||
1620 | iter_reg = fw->xmt2_dma_reg; | |
1621 | iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); | |
1622 | qla24xx_read_window(reg, 0x7650, 16, iter_reg); | |
1623 | ||
1624 | iter_reg = fw->xmt3_dma_reg; | |
1625 | iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); | |
1626 | qla24xx_read_window(reg, 0x7670, 16, iter_reg); | |
1627 | ||
1628 | iter_reg = fw->xmt4_dma_reg; | |
1629 | iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); | |
1630 | qla24xx_read_window(reg, 0x7690, 16, iter_reg); | |
1631 | ||
1632 | qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); | |
1633 | ||
1634 | /* Receive DMA registers. */ | |
1635 | iter_reg = fw->rcvt0_data_dma_reg; | |
1636 | iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); | |
1637 | qla24xx_read_window(reg, 0x7710, 16, iter_reg); | |
1638 | ||
1639 | iter_reg = fw->rcvt1_data_dma_reg; | |
1640 | iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); | |
1641 | qla24xx_read_window(reg, 0x7730, 16, iter_reg); | |
1642 | ||
1643 | /* RISC registers. */ | |
1644 | iter_reg = fw->risc_gp_reg; | |
1645 | iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); | |
1646 | iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); | |
1647 | iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); | |
1648 | iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); | |
1649 | iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); | |
1650 | iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); | |
1651 | iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); | |
1652 | qla24xx_read_window(reg, 0x0F70, 16, iter_reg); | |
1653 | ||
1654 | /* Local memory controller registers. */ | |
1655 | iter_reg = fw->lmc_reg; | |
1656 | iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); | |
1657 | iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); | |
1658 | iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); | |
1659 | iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); | |
1660 | iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); | |
1661 | iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); | |
1662 | iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); | |
1663 | qla24xx_read_window(reg, 0x3070, 16, iter_reg); | |
1664 | ||
1665 | /* Fibre Protocol Module registers. */ | |
1666 | iter_reg = fw->fpm_hdw_reg; | |
1667 | iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); | |
1668 | iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); | |
1669 | iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); | |
1670 | iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); | |
1671 | iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); | |
1672 | iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); | |
1673 | iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); | |
1674 | iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); | |
1675 | iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); | |
1676 | iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); | |
1677 | iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); | |
1678 | iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg); | |
1679 | iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg); | |
1680 | qla24xx_read_window(reg, 0x40D0, 16, iter_reg); | |
1681 | ||
1682 | /* Frame Buffer registers. */ | |
1683 | iter_reg = fw->fb_hdw_reg; | |
1684 | iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); | |
1685 | iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); | |
1686 | iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); | |
1687 | iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); | |
1688 | iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); | |
1689 | iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); | |
1690 | iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); | |
1691 | iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); | |
1692 | iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); | |
1693 | iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); | |
1694 | iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); | |
1695 | iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg); | |
1696 | qla24xx_read_window(reg, 0x6F00, 16, iter_reg); | |
1697 | ||
1698 | /* Multi queue registers */ | |
1699 | nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, | |
1700 | &last_chain); | |
1701 | ||
1702 | rval = qla24xx_soft_reset(ha); | |
1703 | if (rval != QLA_SUCCESS) | |
1704 | goto qla81xx_fw_dump_failed_0; | |
1705 | ||
1706 | rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), | |
1707 | &nxt); | |
1708 | if (rval != QLA_SUCCESS) | |
1709 | goto qla81xx_fw_dump_failed_0; | |
1710 | ||
1711 | nxt = qla2xxx_copy_queues(ha, nxt); | |
1712 | ||
1713 | nxt = qla24xx_copy_eft(ha, nxt); | |
1714 | ||
1715 | /* Chain entries -- started with MQ. */ | |
050c9bb1 GM |
1716 | nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain); |
1717 | nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain); | |
3a03eb79 AV |
1718 | if (last_chain) { |
1719 | ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT); | |
1720 | *last_chain |= __constant_htonl(DUMP_CHAIN_LAST); | |
1721 | } | |
1722 | ||
050c9bb1 GM |
1723 | /* Adjust valid length. */ |
1724 | ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); | |
1725 | ||
3a03eb79 | 1726 | qla81xx_fw_dump_failed_0: |
3420d36c | 1727 | qla2xxx_dump_post_process(base_vha, rval); |
3a03eb79 AV |
1728 | |
1729 | qla81xx_fw_dump_failed: | |
1730 | if (!hardware_locked) | |
1731 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1732 | } | |
1733 | ||
6246b8a1 GM |
1734 | void |
1735 | qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) | |
1736 | { | |
1737 | int rval; | |
1738 | uint32_t cnt, reg_data; | |
1739 | uint32_t risc_address; | |
1740 | struct qla_hw_data *ha = vha->hw; | |
1741 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
1742 | uint32_t __iomem *dmp_reg; | |
1743 | uint32_t *iter_reg; | |
1744 | uint16_t __iomem *mbx_reg; | |
1745 | unsigned long flags; | |
1746 | struct qla83xx_fw_dump *fw; | |
1747 | uint32_t ext_mem_cnt; | |
1748 | void *nxt, *nxt_chain; | |
1749 | uint32_t *last_chain = NULL; | |
1750 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); | |
1751 | ||
1752 | risc_address = ext_mem_cnt = 0; | |
1753 | flags = 0; | |
1754 | ||
1755 | if (!hardware_locked) | |
1756 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1757 | ||
1758 | if (!ha->fw_dump) { | |
1759 | ql_log(ql_log_warn, vha, 0xd00c, | |
1760 | "No buffer available for dump!!!\n"); | |
1761 | goto qla83xx_fw_dump_failed; | |
1762 | } | |
1763 | ||
1764 | if (ha->fw_dumped) { | |
1765 | ql_log(ql_log_warn, vha, 0xd00d, | |
1766 | "Firmware has been previously dumped (%p) -- ignoring " | |
1767 | "request...\n", ha->fw_dump); | |
1768 | goto qla83xx_fw_dump_failed; | |
1769 | } | |
1770 | fw = &ha->fw_dump->isp.isp83; | |
1771 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
1772 | ||
1773 | fw->host_status = htonl(RD_REG_DWORD(®->host_status)); | |
1774 | ||
1775 | /* Pause RISC. */ | |
1776 | rval = qla24xx_pause_risc(reg); | |
1777 | if (rval != QLA_SUCCESS) | |
1778 | goto qla83xx_fw_dump_failed_0; | |
1779 | ||
1780 | WRT_REG_DWORD(®->iobase_addr, 0x6000); | |
1781 | dmp_reg = ®->iobase_window; | |
1782 | reg_data = RD_REG_DWORD(dmp_reg); | |
1783 | WRT_REG_DWORD(dmp_reg, 0); | |
1784 | ||
1785 | dmp_reg = ®->unused_4_1[0]; | |
1786 | reg_data = RD_REG_DWORD(dmp_reg); | |
1787 | WRT_REG_DWORD(dmp_reg, 0); | |
1788 | ||
1789 | WRT_REG_DWORD(®->iobase_addr, 0x6010); | |
1790 | dmp_reg = ®->unused_4_1[2]; | |
1791 | reg_data = RD_REG_DWORD(dmp_reg); | |
1792 | WRT_REG_DWORD(dmp_reg, 0); | |
1793 | ||
1794 | /* select PCR and disable ecc checking and correction */ | |
1795 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); | |
1796 | RD_REG_DWORD(®->iobase_addr); | |
1797 | WRT_REG_DWORD(®->iobase_select, 0x60000000); /* write to F0h = PCR */ | |
1798 | ||
1799 | /* Host/Risc registers. */ | |
1800 | iter_reg = fw->host_risc_reg; | |
1801 | iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); | |
1802 | iter_reg = qla24xx_read_window(reg, 0x7010, 16, iter_reg); | |
1803 | qla24xx_read_window(reg, 0x7040, 16, iter_reg); | |
1804 | ||
1805 | /* PCIe registers. */ | |
1806 | WRT_REG_DWORD(®->iobase_addr, 0x7C00); | |
1807 | RD_REG_DWORD(®->iobase_addr); | |
1808 | WRT_REG_DWORD(®->iobase_window, 0x01); | |
1809 | dmp_reg = ®->iobase_c4; | |
1810 | fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1811 | fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1812 | fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); | |
1813 | fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); | |
1814 | ||
1815 | WRT_REG_DWORD(®->iobase_window, 0x00); | |
1816 | RD_REG_DWORD(®->iobase_window); | |
1817 | ||
1818 | /* Host interface registers. */ | |
1819 | dmp_reg = ®->flash_addr; | |
1820 | for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) | |
1821 | fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1822 | ||
1823 | /* Disable interrupts. */ | |
1824 | WRT_REG_DWORD(®->ictrl, 0); | |
1825 | RD_REG_DWORD(®->ictrl); | |
1826 | ||
1827 | /* Shadow registers. */ | |
1828 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); | |
1829 | RD_REG_DWORD(®->iobase_addr); | |
1830 | WRT_REG_DWORD(®->iobase_select, 0xB0000000); | |
1831 | fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1832 | ||
1833 | WRT_REG_DWORD(®->iobase_select, 0xB0100000); | |
1834 | fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1835 | ||
1836 | WRT_REG_DWORD(®->iobase_select, 0xB0200000); | |
1837 | fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1838 | ||
1839 | WRT_REG_DWORD(®->iobase_select, 0xB0300000); | |
1840 | fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1841 | ||
1842 | WRT_REG_DWORD(®->iobase_select, 0xB0400000); | |
1843 | fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1844 | ||
1845 | WRT_REG_DWORD(®->iobase_select, 0xB0500000); | |
1846 | fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1847 | ||
1848 | WRT_REG_DWORD(®->iobase_select, 0xB0600000); | |
1849 | fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1850 | ||
1851 | WRT_REG_DWORD(®->iobase_select, 0xB0700000); | |
1852 | fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1853 | ||
1854 | WRT_REG_DWORD(®->iobase_select, 0xB0800000); | |
1855 | fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1856 | ||
1857 | WRT_REG_DWORD(®->iobase_select, 0xB0900000); | |
1858 | fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1859 | ||
1860 | WRT_REG_DWORD(®->iobase_select, 0xB0A00000); | |
1861 | fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1862 | ||
1863 | /* RISC I/O register. */ | |
1864 | WRT_REG_DWORD(®->iobase_addr, 0x0010); | |
1865 | fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); | |
1866 | ||
1867 | /* Mailbox registers. */ | |
1868 | mbx_reg = ®->mailbox0; | |
1869 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) | |
1870 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); | |
1871 | ||
1872 | /* Transfer sequence registers. */ | |
1873 | iter_reg = fw->xseq_gp_reg; | |
1874 | iter_reg = qla24xx_read_window(reg, 0xBE00, 16, iter_reg); | |
1875 | iter_reg = qla24xx_read_window(reg, 0xBE10, 16, iter_reg); | |
1876 | iter_reg = qla24xx_read_window(reg, 0xBE20, 16, iter_reg); | |
1877 | iter_reg = qla24xx_read_window(reg, 0xBE30, 16, iter_reg); | |
1878 | iter_reg = qla24xx_read_window(reg, 0xBE40, 16, iter_reg); | |
1879 | iter_reg = qla24xx_read_window(reg, 0xBE50, 16, iter_reg); | |
1880 | iter_reg = qla24xx_read_window(reg, 0xBE60, 16, iter_reg); | |
1881 | iter_reg = qla24xx_read_window(reg, 0xBE70, 16, iter_reg); | |
1882 | iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); | |
1883 | iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); | |
1884 | iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); | |
1885 | iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); | |
1886 | iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); | |
1887 | iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); | |
1888 | iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); | |
1889 | qla24xx_read_window(reg, 0xBF70, 16, iter_reg); | |
1890 | ||
1891 | iter_reg = fw->xseq_0_reg; | |
1892 | iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); | |
1893 | iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); | |
1894 | qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); | |
1895 | ||
1896 | qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); | |
1897 | ||
1898 | qla24xx_read_window(reg, 0xBEF0, 16, fw->xseq_2_reg); | |
1899 | ||
1900 | /* Receive sequence registers. */ | |
1901 | iter_reg = fw->rseq_gp_reg; | |
1902 | iter_reg = qla24xx_read_window(reg, 0xFE00, 16, iter_reg); | |
1903 | iter_reg = qla24xx_read_window(reg, 0xFE10, 16, iter_reg); | |
1904 | iter_reg = qla24xx_read_window(reg, 0xFE20, 16, iter_reg); | |
1905 | iter_reg = qla24xx_read_window(reg, 0xFE30, 16, iter_reg); | |
1906 | iter_reg = qla24xx_read_window(reg, 0xFE40, 16, iter_reg); | |
1907 | iter_reg = qla24xx_read_window(reg, 0xFE50, 16, iter_reg); | |
1908 | iter_reg = qla24xx_read_window(reg, 0xFE60, 16, iter_reg); | |
1909 | iter_reg = qla24xx_read_window(reg, 0xFE70, 16, iter_reg); | |
1910 | iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); | |
1911 | iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); | |
1912 | iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); | |
1913 | iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); | |
1914 | iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); | |
1915 | iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); | |
1916 | iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); | |
1917 | qla24xx_read_window(reg, 0xFF70, 16, iter_reg); | |
1918 | ||
1919 | iter_reg = fw->rseq_0_reg; | |
1920 | iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); | |
1921 | qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); | |
1922 | ||
1923 | qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); | |
1924 | qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); | |
1925 | qla24xx_read_window(reg, 0xFEF0, 16, fw->rseq_3_reg); | |
1926 | ||
1927 | /* Auxiliary sequence registers. */ | |
1928 | iter_reg = fw->aseq_gp_reg; | |
1929 | iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); | |
1930 | iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); | |
1931 | iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); | |
1932 | iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); | |
1933 | iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); | |
1934 | iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); | |
1935 | iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); | |
1936 | iter_reg = qla24xx_read_window(reg, 0xB070, 16, iter_reg); | |
1937 | iter_reg = qla24xx_read_window(reg, 0xB100, 16, iter_reg); | |
1938 | iter_reg = qla24xx_read_window(reg, 0xB110, 16, iter_reg); | |
1939 | iter_reg = qla24xx_read_window(reg, 0xB120, 16, iter_reg); | |
1940 | iter_reg = qla24xx_read_window(reg, 0xB130, 16, iter_reg); | |
1941 | iter_reg = qla24xx_read_window(reg, 0xB140, 16, iter_reg); | |
1942 | iter_reg = qla24xx_read_window(reg, 0xB150, 16, iter_reg); | |
1943 | iter_reg = qla24xx_read_window(reg, 0xB160, 16, iter_reg); | |
1944 | qla24xx_read_window(reg, 0xB170, 16, iter_reg); | |
1945 | ||
1946 | iter_reg = fw->aseq_0_reg; | |
1947 | iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); | |
1948 | qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); | |
1949 | ||
1950 | qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); | |
1951 | qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); | |
1952 | qla24xx_read_window(reg, 0xB1F0, 16, fw->aseq_3_reg); | |
1953 | ||
1954 | /* Command DMA registers. */ | |
1955 | iter_reg = fw->cmd_dma_reg; | |
1956 | iter_reg = qla24xx_read_window(reg, 0x7100, 16, iter_reg); | |
1957 | iter_reg = qla24xx_read_window(reg, 0x7120, 16, iter_reg); | |
1958 | iter_reg = qla24xx_read_window(reg, 0x7130, 16, iter_reg); | |
1959 | qla24xx_read_window(reg, 0x71F0, 16, iter_reg); | |
1960 | ||
1961 | /* Queues. */ | |
1962 | iter_reg = fw->req0_dma_reg; | |
1963 | iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); | |
1964 | dmp_reg = ®->iobase_q; | |
1965 | for (cnt = 0; cnt < 7; cnt++) | |
1966 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1967 | ||
1968 | iter_reg = fw->resp0_dma_reg; | |
1969 | iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); | |
1970 | dmp_reg = ®->iobase_q; | |
1971 | for (cnt = 0; cnt < 7; cnt++) | |
1972 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1973 | ||
1974 | iter_reg = fw->req1_dma_reg; | |
1975 | iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); | |
1976 | dmp_reg = ®->iobase_q; | |
1977 | for (cnt = 0; cnt < 7; cnt++) | |
1978 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1979 | ||
1980 | /* Transmit DMA registers. */ | |
1981 | iter_reg = fw->xmt0_dma_reg; | |
1982 | iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); | |
1983 | qla24xx_read_window(reg, 0x7610, 16, iter_reg); | |
1984 | ||
1985 | iter_reg = fw->xmt1_dma_reg; | |
1986 | iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); | |
1987 | qla24xx_read_window(reg, 0x7630, 16, iter_reg); | |
1988 | ||
1989 | iter_reg = fw->xmt2_dma_reg; | |
1990 | iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); | |
1991 | qla24xx_read_window(reg, 0x7650, 16, iter_reg); | |
1992 | ||
1993 | iter_reg = fw->xmt3_dma_reg; | |
1994 | iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); | |
1995 | qla24xx_read_window(reg, 0x7670, 16, iter_reg); | |
1996 | ||
1997 | iter_reg = fw->xmt4_dma_reg; | |
1998 | iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); | |
1999 | qla24xx_read_window(reg, 0x7690, 16, iter_reg); | |
2000 | ||
2001 | qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); | |
2002 | ||
2003 | /* Receive DMA registers. */ | |
2004 | iter_reg = fw->rcvt0_data_dma_reg; | |
2005 | iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); | |
2006 | qla24xx_read_window(reg, 0x7710, 16, iter_reg); | |
2007 | ||
2008 | iter_reg = fw->rcvt1_data_dma_reg; | |
2009 | iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); | |
2010 | qla24xx_read_window(reg, 0x7730, 16, iter_reg); | |
2011 | ||
2012 | /* RISC registers. */ | |
2013 | iter_reg = fw->risc_gp_reg; | |
2014 | iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); | |
2015 | iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); | |
2016 | iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); | |
2017 | iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); | |
2018 | iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); | |
2019 | iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); | |
2020 | iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); | |
2021 | qla24xx_read_window(reg, 0x0F70, 16, iter_reg); | |
2022 | ||
2023 | /* Local memory controller registers. */ | |
2024 | iter_reg = fw->lmc_reg; | |
2025 | iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); | |
2026 | iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); | |
2027 | iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); | |
2028 | iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); | |
2029 | iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); | |
2030 | iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); | |
2031 | iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); | |
2032 | qla24xx_read_window(reg, 0x3070, 16, iter_reg); | |
2033 | ||
2034 | /* Fibre Protocol Module registers. */ | |
2035 | iter_reg = fw->fpm_hdw_reg; | |
2036 | iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); | |
2037 | iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); | |
2038 | iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); | |
2039 | iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); | |
2040 | iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); | |
2041 | iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); | |
2042 | iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); | |
2043 | iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); | |
2044 | iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); | |
2045 | iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); | |
2046 | iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); | |
2047 | iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg); | |
2048 | iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg); | |
2049 | iter_reg = qla24xx_read_window(reg, 0x40D0, 16, iter_reg); | |
2050 | iter_reg = qla24xx_read_window(reg, 0x40E0, 16, iter_reg); | |
2051 | qla24xx_read_window(reg, 0x40F0, 16, iter_reg); | |
2052 | ||
2053 | /* RQ0 Array registers. */ | |
2054 | iter_reg = fw->rq0_array_reg; | |
2055 | iter_reg = qla24xx_read_window(reg, 0x5C00, 16, iter_reg); | |
2056 | iter_reg = qla24xx_read_window(reg, 0x5C10, 16, iter_reg); | |
2057 | iter_reg = qla24xx_read_window(reg, 0x5C20, 16, iter_reg); | |
2058 | iter_reg = qla24xx_read_window(reg, 0x5C30, 16, iter_reg); | |
2059 | iter_reg = qla24xx_read_window(reg, 0x5C40, 16, iter_reg); | |
2060 | iter_reg = qla24xx_read_window(reg, 0x5C50, 16, iter_reg); | |
2061 | iter_reg = qla24xx_read_window(reg, 0x5C60, 16, iter_reg); | |
2062 | iter_reg = qla24xx_read_window(reg, 0x5C70, 16, iter_reg); | |
2063 | iter_reg = qla24xx_read_window(reg, 0x5C80, 16, iter_reg); | |
2064 | iter_reg = qla24xx_read_window(reg, 0x5C90, 16, iter_reg); | |
2065 | iter_reg = qla24xx_read_window(reg, 0x5CA0, 16, iter_reg); | |
2066 | iter_reg = qla24xx_read_window(reg, 0x5CB0, 16, iter_reg); | |
2067 | iter_reg = qla24xx_read_window(reg, 0x5CC0, 16, iter_reg); | |
2068 | iter_reg = qla24xx_read_window(reg, 0x5CD0, 16, iter_reg); | |
2069 | iter_reg = qla24xx_read_window(reg, 0x5CE0, 16, iter_reg); | |
2070 | qla24xx_read_window(reg, 0x5CF0, 16, iter_reg); | |
2071 | ||
2072 | /* RQ1 Array registers. */ | |
2073 | iter_reg = fw->rq1_array_reg; | |
2074 | iter_reg = qla24xx_read_window(reg, 0x5D00, 16, iter_reg); | |
2075 | iter_reg = qla24xx_read_window(reg, 0x5D10, 16, iter_reg); | |
2076 | iter_reg = qla24xx_read_window(reg, 0x5D20, 16, iter_reg); | |
2077 | iter_reg = qla24xx_read_window(reg, 0x5D30, 16, iter_reg); | |
2078 | iter_reg = qla24xx_read_window(reg, 0x5D40, 16, iter_reg); | |
2079 | iter_reg = qla24xx_read_window(reg, 0x5D50, 16, iter_reg); | |
2080 | iter_reg = qla24xx_read_window(reg, 0x5D60, 16, iter_reg); | |
2081 | iter_reg = qla24xx_read_window(reg, 0x5D70, 16, iter_reg); | |
2082 | iter_reg = qla24xx_read_window(reg, 0x5D80, 16, iter_reg); | |
2083 | iter_reg = qla24xx_read_window(reg, 0x5D90, 16, iter_reg); | |
2084 | iter_reg = qla24xx_read_window(reg, 0x5DA0, 16, iter_reg); | |
2085 | iter_reg = qla24xx_read_window(reg, 0x5DB0, 16, iter_reg); | |
2086 | iter_reg = qla24xx_read_window(reg, 0x5DC0, 16, iter_reg); | |
2087 | iter_reg = qla24xx_read_window(reg, 0x5DD0, 16, iter_reg); | |
2088 | iter_reg = qla24xx_read_window(reg, 0x5DE0, 16, iter_reg); | |
2089 | qla24xx_read_window(reg, 0x5DF0, 16, iter_reg); | |
2090 | ||
2091 | /* RP0 Array registers. */ | |
2092 | iter_reg = fw->rp0_array_reg; | |
2093 | iter_reg = qla24xx_read_window(reg, 0x5E00, 16, iter_reg); | |
2094 | iter_reg = qla24xx_read_window(reg, 0x5E10, 16, iter_reg); | |
2095 | iter_reg = qla24xx_read_window(reg, 0x5E20, 16, iter_reg); | |
2096 | iter_reg = qla24xx_read_window(reg, 0x5E30, 16, iter_reg); | |
2097 | iter_reg = qla24xx_read_window(reg, 0x5E40, 16, iter_reg); | |
2098 | iter_reg = qla24xx_read_window(reg, 0x5E50, 16, iter_reg); | |
2099 | iter_reg = qla24xx_read_window(reg, 0x5E60, 16, iter_reg); | |
2100 | iter_reg = qla24xx_read_window(reg, 0x5E70, 16, iter_reg); | |
2101 | iter_reg = qla24xx_read_window(reg, 0x5E80, 16, iter_reg); | |
2102 | iter_reg = qla24xx_read_window(reg, 0x5E90, 16, iter_reg); | |
2103 | iter_reg = qla24xx_read_window(reg, 0x5EA0, 16, iter_reg); | |
2104 | iter_reg = qla24xx_read_window(reg, 0x5EB0, 16, iter_reg); | |
2105 | iter_reg = qla24xx_read_window(reg, 0x5EC0, 16, iter_reg); | |
2106 | iter_reg = qla24xx_read_window(reg, 0x5ED0, 16, iter_reg); | |
2107 | iter_reg = qla24xx_read_window(reg, 0x5EE0, 16, iter_reg); | |
2108 | qla24xx_read_window(reg, 0x5EF0, 16, iter_reg); | |
2109 | ||
2110 | /* RP1 Array registers. */ | |
2111 | iter_reg = fw->rp1_array_reg; | |
2112 | iter_reg = qla24xx_read_window(reg, 0x5F00, 16, iter_reg); | |
2113 | iter_reg = qla24xx_read_window(reg, 0x5F10, 16, iter_reg); | |
2114 | iter_reg = qla24xx_read_window(reg, 0x5F20, 16, iter_reg); | |
2115 | iter_reg = qla24xx_read_window(reg, 0x5F30, 16, iter_reg); | |
2116 | iter_reg = qla24xx_read_window(reg, 0x5F40, 16, iter_reg); | |
2117 | iter_reg = qla24xx_read_window(reg, 0x5F50, 16, iter_reg); | |
2118 | iter_reg = qla24xx_read_window(reg, 0x5F60, 16, iter_reg); | |
2119 | iter_reg = qla24xx_read_window(reg, 0x5F70, 16, iter_reg); | |
2120 | iter_reg = qla24xx_read_window(reg, 0x5F80, 16, iter_reg); | |
2121 | iter_reg = qla24xx_read_window(reg, 0x5F90, 16, iter_reg); | |
2122 | iter_reg = qla24xx_read_window(reg, 0x5FA0, 16, iter_reg); | |
2123 | iter_reg = qla24xx_read_window(reg, 0x5FB0, 16, iter_reg); | |
2124 | iter_reg = qla24xx_read_window(reg, 0x5FC0, 16, iter_reg); | |
2125 | iter_reg = qla24xx_read_window(reg, 0x5FD0, 16, iter_reg); | |
2126 | iter_reg = qla24xx_read_window(reg, 0x5FE0, 16, iter_reg); | |
2127 | qla24xx_read_window(reg, 0x5FF0, 16, iter_reg); | |
2128 | ||
2129 | iter_reg = fw->at0_array_reg; | |
2130 | iter_reg = qla24xx_read_window(reg, 0x7080, 16, iter_reg); | |
2131 | iter_reg = qla24xx_read_window(reg, 0x7090, 16, iter_reg); | |
2132 | iter_reg = qla24xx_read_window(reg, 0x70A0, 16, iter_reg); | |
2133 | iter_reg = qla24xx_read_window(reg, 0x70B0, 16, iter_reg); | |
2134 | iter_reg = qla24xx_read_window(reg, 0x70C0, 16, iter_reg); | |
2135 | iter_reg = qla24xx_read_window(reg, 0x70D0, 16, iter_reg); | |
2136 | iter_reg = qla24xx_read_window(reg, 0x70E0, 16, iter_reg); | |
2137 | qla24xx_read_window(reg, 0x70F0, 16, iter_reg); | |
2138 | ||
2139 | /* I/O Queue Control registers. */ | |
2140 | qla24xx_read_window(reg, 0x7800, 16, fw->queue_control_reg); | |
2141 | ||
2142 | /* Frame Buffer registers. */ | |
2143 | iter_reg = fw->fb_hdw_reg; | |
2144 | iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); | |
2145 | iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); | |
2146 | iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); | |
2147 | iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); | |
2148 | iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); | |
2149 | iter_reg = qla24xx_read_window(reg, 0x6060, 16, iter_reg); | |
2150 | iter_reg = qla24xx_read_window(reg, 0x6070, 16, iter_reg); | |
2151 | iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); | |
2152 | iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); | |
2153 | iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); | |
2154 | iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); | |
2155 | iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); | |
2156 | iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); | |
2157 | iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg); | |
2158 | iter_reg = qla24xx_read_window(reg, 0x6530, 16, iter_reg); | |
2159 | iter_reg = qla24xx_read_window(reg, 0x6540, 16, iter_reg); | |
2160 | iter_reg = qla24xx_read_window(reg, 0x6550, 16, iter_reg); | |
2161 | iter_reg = qla24xx_read_window(reg, 0x6560, 16, iter_reg); | |
2162 | iter_reg = qla24xx_read_window(reg, 0x6570, 16, iter_reg); | |
2163 | iter_reg = qla24xx_read_window(reg, 0x6580, 16, iter_reg); | |
2164 | iter_reg = qla24xx_read_window(reg, 0x6590, 16, iter_reg); | |
2165 | iter_reg = qla24xx_read_window(reg, 0x65A0, 16, iter_reg); | |
2166 | iter_reg = qla24xx_read_window(reg, 0x65B0, 16, iter_reg); | |
2167 | iter_reg = qla24xx_read_window(reg, 0x65C0, 16, iter_reg); | |
2168 | iter_reg = qla24xx_read_window(reg, 0x65D0, 16, iter_reg); | |
2169 | iter_reg = qla24xx_read_window(reg, 0x65E0, 16, iter_reg); | |
2170 | qla24xx_read_window(reg, 0x6F00, 16, iter_reg); | |
2171 | ||
2172 | /* Multi queue registers */ | |
2173 | nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, | |
2174 | &last_chain); | |
2175 | ||
2176 | rval = qla24xx_soft_reset(ha); | |
2177 | if (rval != QLA_SUCCESS) { | |
2178 | ql_log(ql_log_warn, vha, 0xd00e, | |
2179 | "SOFT RESET FAILED, forcing continuation of dump!!!\n"); | |
2180 | rval = QLA_SUCCESS; | |
2181 | ||
2182 | ql_log(ql_log_warn, vha, 0xd00f, "try a bigger hammer!!!\n"); | |
2183 | ||
2184 | WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET); | |
2185 | RD_REG_DWORD(®->hccr); | |
2186 | ||
2187 | WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE); | |
2188 | RD_REG_DWORD(®->hccr); | |
2189 | ||
2190 | WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); | |
2191 | RD_REG_DWORD(®->hccr); | |
2192 | ||
2193 | for (cnt = 30000; cnt && (RD_REG_WORD(®->mailbox0)); cnt--) | |
2194 | udelay(5); | |
2195 | ||
2196 | if (!cnt) { | |
2197 | nxt = fw->code_ram; | |
2198 | nxt += sizeof(fw->code_ram), | |
2199 | nxt += (ha->fw_memory_size - 0x100000 + 1); | |
2200 | goto copy_queue; | |
2201 | } else | |
2202 | ql_log(ql_log_warn, vha, 0xd010, | |
2203 | "bigger hammer success?\n"); | |
2204 | } | |
2205 | ||
2206 | rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), | |
2207 | &nxt); | |
2208 | if (rval != QLA_SUCCESS) | |
2209 | goto qla83xx_fw_dump_failed_0; | |
2210 | ||
2211 | copy_queue: | |
2212 | nxt = qla2xxx_copy_queues(ha, nxt); | |
2213 | ||
2214 | nxt = qla24xx_copy_eft(ha, nxt); | |
2215 | ||
2216 | /* Chain entries -- started with MQ. */ | |
2217 | nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain); | |
2218 | nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain); | |
2219 | if (last_chain) { | |
2220 | ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT); | |
2221 | *last_chain |= __constant_htonl(DUMP_CHAIN_LAST); | |
2222 | } | |
2223 | ||
2224 | /* Adjust valid length. */ | |
2225 | ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); | |
2226 | ||
2227 | qla83xx_fw_dump_failed_0: | |
2228 | qla2xxx_dump_post_process(base_vha, rval); | |
2229 | ||
2230 | qla83xx_fw_dump_failed: | |
2231 | if (!hardware_locked) | |
2232 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
2233 | } | |
2234 | ||
1da177e4 LT |
2235 | /****************************************************************************/ |
2236 | /* Driver Debug Functions. */ | |
2237 | /****************************************************************************/ | |
cfb0919c CD |
2238 | |
2239 | static inline int | |
2240 | ql_mask_match(uint32_t level) | |
2241 | { | |
2242 | if (ql2xextended_error_logging == 1) | |
2243 | ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; | |
2244 | return (level & ql2xextended_error_logging) == level; | |
2245 | } | |
2246 | ||
3ce8866c SK |
2247 | /* |
2248 | * This function is for formatting and logging debug information. | |
2249 | * It is to be used when vha is available. It formats the message | |
2250 | * and logs it to the messages file. | |
2251 | * parameters: | |
2252 | * level: The level of the debug messages to be printed. | |
2253 | * If ql2xextended_error_logging value is correctly set, | |
2254 | * this message will appear in the messages file. | |
2255 | * vha: Pointer to the scsi_qla_host_t. | |
2256 | * id: This is a unique identifier for the level. It identifies the | |
2257 | * part of the code from where the message originated. | |
2258 | * msg: The message to be displayed. | |
2259 | */ | |
2260 | void | |
086b3e8a JP |
2261 | ql_dbg(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...) |
2262 | { | |
2263 | va_list va; | |
2264 | struct va_format vaf; | |
3ce8866c | 2265 | |
cfb0919c | 2266 | if (!ql_mask_match(level)) |
086b3e8a | 2267 | return; |
3ce8866c | 2268 | |
086b3e8a | 2269 | va_start(va, fmt); |
3ce8866c | 2270 | |
086b3e8a JP |
2271 | vaf.fmt = fmt; |
2272 | vaf.va = &va; | |
3ce8866c | 2273 | |
086b3e8a JP |
2274 | if (vha != NULL) { |
2275 | const struct pci_dev *pdev = vha->hw->pdev; | |
2276 | /* <module-name> <pci-name> <msg-id>:<host> Message */ | |
2277 | pr_warn("%s [%s]-%04x:%ld: %pV", | |
2278 | QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, | |
2279 | vha->host_no, &vaf); | |
2280 | } else { | |
2281 | pr_warn("%s [%s]-%04x: : %pV", | |
2282 | QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf); | |
3ce8866c SK |
2283 | } |
2284 | ||
086b3e8a | 2285 | va_end(va); |
3ce8866c SK |
2286 | |
2287 | } | |
2288 | ||
2289 | /* | |
2290 | * This function is for formatting and logging debug information. | |
2291 | * It is to be used when vha is not available and pci is availble, | |
2292 | * i.e., before host allocation. It formats the message and logs it | |
2293 | * to the messages file. | |
2294 | * parameters: | |
2295 | * level: The level of the debug messages to be printed. | |
2296 | * If ql2xextended_error_logging value is correctly set, | |
2297 | * this message will appear in the messages file. | |
2298 | * pdev: Pointer to the struct pci_dev. | |
2299 | * id: This is a unique id for the level. It identifies the part | |
2300 | * of the code from where the message originated. | |
2301 | * msg: The message to be displayed. | |
2302 | */ | |
2303 | void | |
086b3e8a JP |
2304 | ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id, |
2305 | const char *fmt, ...) | |
2306 | { | |
2307 | va_list va; | |
2308 | struct va_format vaf; | |
3ce8866c SK |
2309 | |
2310 | if (pdev == NULL) | |
2311 | return; | |
cfb0919c | 2312 | if (!ql_mask_match(level)) |
086b3e8a | 2313 | return; |
3ce8866c | 2314 | |
086b3e8a | 2315 | va_start(va, fmt); |
3ce8866c | 2316 | |
086b3e8a JP |
2317 | vaf.fmt = fmt; |
2318 | vaf.va = &va; | |
3ce8866c | 2319 | |
086b3e8a JP |
2320 | /* <module-name> <dev-name>:<msg-id> Message */ |
2321 | pr_warn("%s [%s]-%04x: : %pV", | |
2322 | QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, &vaf); | |
3ce8866c | 2323 | |
086b3e8a | 2324 | va_end(va); |
3ce8866c SK |
2325 | } |
2326 | ||
2327 | /* | |
2328 | * This function is for formatting and logging log messages. | |
2329 | * It is to be used when vha is available. It formats the message | |
2330 | * and logs it to the messages file. All the messages will be logged | |
2331 | * irrespective of value of ql2xextended_error_logging. | |
2332 | * parameters: | |
2333 | * level: The level of the log messages to be printed in the | |
2334 | * messages file. | |
2335 | * vha: Pointer to the scsi_qla_host_t | |
2336 | * id: This is a unique id for the level. It identifies the | |
2337 | * part of the code from where the message originated. | |
2338 | * msg: The message to be displayed. | |
2339 | */ | |
2340 | void | |
086b3e8a JP |
2341 | ql_log(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...) |
2342 | { | |
2343 | va_list va; | |
2344 | struct va_format vaf; | |
2345 | char pbuf[128]; | |
3ce8866c | 2346 | |
086b3e8a JP |
2347 | if (level > ql_errlev) |
2348 | return; | |
3ce8866c | 2349 | |
086b3e8a JP |
2350 | if (vha != NULL) { |
2351 | const struct pci_dev *pdev = vha->hw->pdev; | |
2352 | /* <module-name> <msg-id>:<host> Message */ | |
2353 | snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x:%ld: ", | |
2354 | QL_MSGHDR, dev_name(&(pdev->dev)), id, vha->host_no); | |
2355 | } else { | |
2356 | snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ", | |
2357 | QL_MSGHDR, "0000:00:00.0", id); | |
2358 | } | |
2359 | pbuf[sizeof(pbuf) - 1] = 0; | |
2360 | ||
2361 | va_start(va, fmt); | |
2362 | ||
2363 | vaf.fmt = fmt; | |
2364 | vaf.va = &va; | |
2365 | ||
2366 | switch (level) { | |
70a3fc76 | 2367 | case ql_log_fatal: /* FATAL LOG */ |
086b3e8a JP |
2368 | pr_crit("%s%pV", pbuf, &vaf); |
2369 | break; | |
70a3fc76 | 2370 | case ql_log_warn: |
086b3e8a JP |
2371 | pr_err("%s%pV", pbuf, &vaf); |
2372 | break; | |
70a3fc76 | 2373 | case ql_log_info: |
086b3e8a JP |
2374 | pr_warn("%s%pV", pbuf, &vaf); |
2375 | break; | |
2376 | default: | |
2377 | pr_info("%s%pV", pbuf, &vaf); | |
2378 | break; | |
3ce8866c SK |
2379 | } |
2380 | ||
086b3e8a | 2381 | va_end(va); |
3ce8866c SK |
2382 | } |
2383 | ||
2384 | /* | |
2385 | * This function is for formatting and logging log messages. | |
2386 | * It is to be used when vha is not available and pci is availble, | |
2387 | * i.e., before host allocation. It formats the message and logs | |
2388 | * it to the messages file. All the messages are logged irrespective | |
2389 | * of the value of ql2xextended_error_logging. | |
2390 | * parameters: | |
2391 | * level: The level of the log messages to be printed in the | |
2392 | * messages file. | |
2393 | * pdev: Pointer to the struct pci_dev. | |
2394 | * id: This is a unique id for the level. It identifies the | |
2395 | * part of the code from where the message originated. | |
2396 | * msg: The message to be displayed. | |
2397 | */ | |
2398 | void | |
086b3e8a JP |
2399 | ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id, |
2400 | const char *fmt, ...) | |
2401 | { | |
2402 | va_list va; | |
2403 | struct va_format vaf; | |
2404 | char pbuf[128]; | |
3ce8866c SK |
2405 | |
2406 | if (pdev == NULL) | |
2407 | return; | |
086b3e8a JP |
2408 | if (level > ql_errlev) |
2409 | return; | |
3ce8866c | 2410 | |
086b3e8a JP |
2411 | /* <module-name> <dev-name>:<msg-id> Message */ |
2412 | snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ", | |
2413 | QL_MSGHDR, dev_name(&(pdev->dev)), id); | |
2414 | pbuf[sizeof(pbuf) - 1] = 0; | |
2415 | ||
2416 | va_start(va, fmt); | |
2417 | ||
2418 | vaf.fmt = fmt; | |
2419 | vaf.va = &va; | |
2420 | ||
2421 | switch (level) { | |
70a3fc76 | 2422 | case ql_log_fatal: /* FATAL LOG */ |
086b3e8a JP |
2423 | pr_crit("%s%pV", pbuf, &vaf); |
2424 | break; | |
70a3fc76 | 2425 | case ql_log_warn: |
086b3e8a JP |
2426 | pr_err("%s%pV", pbuf, &vaf); |
2427 | break; | |
70a3fc76 | 2428 | case ql_log_info: |
086b3e8a JP |
2429 | pr_warn("%s%pV", pbuf, &vaf); |
2430 | break; | |
2431 | default: | |
2432 | pr_info("%s%pV", pbuf, &vaf); | |
2433 | break; | |
3ce8866c SK |
2434 | } |
2435 | ||
086b3e8a | 2436 | va_end(va); |
3ce8866c SK |
2437 | } |
2438 | ||
2439 | void | |
2440 | ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id) | |
2441 | { | |
2442 | int i; | |
2443 | struct qla_hw_data *ha = vha->hw; | |
2444 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
2445 | struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; | |
2446 | struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82; | |
2447 | uint16_t __iomem *mbx_reg; | |
2448 | ||
cfb0919c CD |
2449 | if (!ql_mask_match(level)) |
2450 | return; | |
3ce8866c | 2451 | |
cfb0919c CD |
2452 | if (IS_QLA82XX(ha)) |
2453 | mbx_reg = ®82->mailbox_in[0]; | |
2454 | else if (IS_FWI2_CAPABLE(ha)) | |
2455 | mbx_reg = ®24->mailbox0; | |
2456 | else | |
2457 | mbx_reg = MAILBOX_REG(ha, reg, 0); | |
2458 | ||
2459 | ql_dbg(level, vha, id, "Mailbox registers:\n"); | |
2460 | for (i = 0; i < 6; i++) | |
2461 | ql_dbg(level, vha, id, | |
2462 | "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++)); | |
3ce8866c SK |
2463 | } |
2464 | ||
2465 | ||
2466 | void | |
2467 | ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id, | |
2468 | uint8_t *b, uint32_t size) | |
2469 | { | |
2470 | uint32_t cnt; | |
2471 | uint8_t c; | |
cfb0919c CD |
2472 | |
2473 | if (!ql_mask_match(level)) | |
2474 | return; | |
2475 | ||
2476 | ql_dbg(level, vha, id, " 0 1 2 3 4 5 6 7 8 " | |
2477 | "9 Ah Bh Ch Dh Eh Fh\n"); | |
2478 | ql_dbg(level, vha, id, "----------------------------------" | |
2479 | "----------------------------\n"); | |
2480 | ||
2481 | ql_dbg(level, vha, id, " "); | |
2482 | for (cnt = 0; cnt < size;) { | |
2483 | c = *b++; | |
2484 | printk("%02x", (uint32_t) c); | |
2485 | cnt++; | |
2486 | if (!(cnt % 16)) | |
2487 | printk("\n"); | |
2488 | else | |
2489 | printk(" "); | |
3ce8866c | 2490 | } |
cfb0919c CD |
2491 | if (cnt % 16) |
2492 | ql_dbg(level, vha, id, "\n"); | |
3ce8866c | 2493 | } |