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[SCSI] qla2xxx: Add setting of driver version string for vendor application.
[deliverable/linux.git] / drivers / scsi / qla2xxx / qla_dbg.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
1e63395c 3 * Copyright (c) 2003-2013 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4 6 */
3ce8866c
SK		 7
8/*
9 * Table for showing the current message id in use for particular level
10 * Change this table for addition of log/debug messages.
e02587d7
AE		 11 * ----------------------------------------------------------------------
12 * | Level | Last Value Used | Holes |
13 * ----------------------------------------------------------------------
7ec0effd 14 * | Module Init and Probe | 0x0151 | 0x4b,0xba,0xfa |
c46e65c7 15 * | Mailbox commands | 0x1181 | 0x111a-0x111b |
e9f4f418 16 * | | | 0x1155-0x1158 |
8ae6d9c7 17 * | Device Discovery | 0x2095 | 0x2020-0x2022, |
6593d5bd 18 * | | | 0x2011-0x2012, |
2a8593f8 19 * | | | 0x2016 |
8ae6d9c7 20 * | Queue Command and IO tracing | 0x3058 | 0x3006-0x300b |
9e522cd8 21 * | | | 0x3027-0x3028 |
8ae6d9c7
GM		 22 * | | | 0x303d-0x3041 |
23 * | | | 0x302d,0x3033 |
24 * | | | 0x3036,0x3038 |
25 * | | | 0x303a |
26 * | DPC Thread | 0x4022 | 0x4002,0x4013 |
27 * | Async Events | 0x5081 | 0x502b-0x502f |
9ba56b95 28 * | | | 0x5047,0x5052 |
8ae6d9c7 29 * | | | 0x5040,0x5075 |
a78951b2 30 * | | | 0x503d,0x5044 |
5988aeb2 31 * | Timer Routines | 0x6011 | |
8ae6d9c7 32 * | User Space Interactions | 0x70dd | 0x7018,0x702e, |
78d56df6 33 * | | | 0x7020,0x7024, |
733a95bd
JC		 34 * | | | 0x7039,0x7045, |
35 * | | | 0x7073-0x7075, |
8ae6d9c7 36 * | | | 0x707b,0x708c, |
a9b6f722
SK		 37 * | | | 0x70a5,0x70a6, |
38 * | | | 0x70a8,0x70ab, |
8ae6d9c7 39 * | | | 0x70ad-0x70ae, |
090fc2e2 40 * | | | 0x70d1-0x70da, |
a44c72f3 41 * | | | 0x7047,0x703b |
5854771e 42 * | Task Management | 0x803d | 0x8025-0x8026 |
cfb0919c 43 * | | | 0x800b,0x8039 |
5f28d2d7 44 * | AER/EEH | 0x9011 | |
e02587d7 45 * | Virtual Port | 0xa007 | |
7ec0effd
AD		 46 * | ISP82XX Specific | 0xb14c | 0xb002,0xb024 |
47 * | | | 0xb09e,0xb0ae |
48 * | | | 0xb0e0-0xb0ef |
49 * | | | 0xb085,0xb0dc |
50 * | | | 0xb107,0xb108 |
51 * | | | 0xb111,0xb11e |
52 * | | | 0xb12c,0xb12d |
53 * | | | 0xb13a,0xb142 |
54 * | | | 0xb13c-0xb140 |
6246b8a1
GM		 55 * | MultiQ | 0xc00c | |
56 * | Misc | 0xd010 | |
33c36c0a 57 * | Target Mode | 0xe070 | |
aa230bc5 58 * | Target Mode Management | 0xf072 | |
2d70c103 59 * | Target Mode Task Management | 0x1000b | |
e02587d7 60 * ----------------------------------------------------------------------
3ce8866c
SK		 61 */
62
1da177e4
LT		 63#include "qla_def.h"
64
65#include <linux/delay.h>
66
3ce8866c
SK		 67static uint32_t ql_dbg_offset = 0x800;
68
a7a167bf 69static inline void
7b867cf7 70qla2xxx_prep_dump(struct qla_hw_data *ha, struct qla2xxx_fw_dump *fw_dump)
a7a167bf
AV		 71{
72 fw_dump->fw_major_version = htonl(ha->fw_major_version);
73 fw_dump->fw_minor_version = htonl(ha->fw_minor_version);
74 fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version);
75 fw_dump->fw_attributes = htonl(ha->fw_attributes);
76
77 fw_dump->vendor = htonl(ha->pdev->vendor);
78 fw_dump->device = htonl(ha->pdev->device);
79 fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor);
80 fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device);
81}
82
83static inline void *
73208dfd 84qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr)
a7a167bf 85{
73208dfd
AC		 86 struct req_que *req = ha->req_q_map[0];
87 struct rsp_que *rsp = ha->rsp_q_map[0];
a7a167bf 88 /* Request queue. */
7b867cf7 89 memcpy(ptr, req->ring, req->length *
a7a167bf
AV		 90 sizeof(request_t));
91
92 /* Response queue. */
7b867cf7
AC		 93 ptr += req->length * sizeof(request_t);
94 memcpy(ptr, rsp->ring, rsp->length *
a7a167bf
AV		 95 sizeof(response_t));
96
7b867cf7 97 return ptr + (rsp->length * sizeof(response_t));
a7a167bf 98}
1da177e4 99
c3a2f0df 100static int
7b867cf7 101qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram,
c5722708 102 uint32_t ram_dwords, void **nxt)
c3a2f0df
AV		 103{
104 int rval;
c5722708
AV		 105 uint32_t cnt, stat, timer, dwords, idx;
106 uint16_t mb0;
c3a2f0df 107 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
c5722708
AV		 108 dma_addr_t dump_dma = ha->gid_list_dma;
109 uint32_t *dump = (uint32_t *)ha->gid_list;
c3a2f0df
AV		 110
111 rval = QLA_SUCCESS;
c5722708 112 mb0 = 0;
c3a2f0df 113
c5722708 114 WRT_REG_WORD(&reg->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
c3a2f0df
AV		 115 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
116
642ef983 117 dwords = qla2x00_gid_list_size(ha) / 4;
c5722708
AV		 118 for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
119 cnt += dwords, addr += dwords) {
120 if (cnt + dwords > ram_dwords)
121 dwords = ram_dwords - cnt;
c3a2f0df 122
c5722708
AV		 123 WRT_REG_WORD(&reg->mailbox1, LSW(addr));
124 WRT_REG_WORD(&reg->mailbox8, MSW(addr));
c3a2f0df 125
c5722708
AV		 126 WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
127 WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
128 WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
129 WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
c3a2f0df 130
c5722708
AV		 131 WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
132 WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
c3a2f0df
AV		 133 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
134
135 for (timer = 6000000; timer; timer--) {
136 /* Check for pending interrupts. */
137 stat = RD_REG_DWORD(&reg->host_status);
138 if (stat & HSRX_RISC_INT) {
139 stat &= 0xff;
140
141 if (stat == 0x1 || stat == 0x2 ||
142 stat == 0x10 || stat == 0x11) {
143 set_bit(MBX_INTERRUPT,
144 &ha->mbx_cmd_flags);
145
c5722708 146 mb0 = RD_REG_WORD(&reg->mailbox0);
c3a2f0df
AV		 147
148 WRT_REG_DWORD(&reg->hccr,
149 HCCRX_CLR_RISC_INT);
150 RD_REG_DWORD(&reg->hccr);
151 break;
152 }
153
154 /* Clear this intr; it wasn't a mailbox intr */
155 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
156 RD_REG_DWORD(&reg->hccr);
157 }
158 udelay(5);
159 }
160
161 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
c5722708
AV		 162 rval = mb0 & MBS_MASK;
163 for (idx = 0; idx < dwords; idx++)
164 ram[cnt + idx] = swab32(dump[idx]);
c3a2f0df
AV		 165 } else {
166 rval = QLA_FUNCTION_FAILED;
167 }
168 }
169
c5722708 170 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
c3a2f0df
AV		 171 return rval;
172}
173
c5722708 174static int
7b867cf7 175qla24xx_dump_memory(struct qla_hw_data *ha, uint32_t *code_ram,
c5722708
AV		 176 uint32_t cram_size, void **nxt)
177{
178 int rval;
179
180 /* Code RAM. */
181 rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt);
182 if (rval != QLA_SUCCESS)
183 return rval;
184
185 /* External Memory. */
186 return qla24xx_dump_ram(ha, 0x100000, *nxt,
187 ha->fw_memory_size - 0x100000 + 1, nxt);
188}
189
c81d04c9
AV		 190static uint32_t *
191qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
192 uint32_t count, uint32_t *buf)
193{
194 uint32_t __iomem *dmp_reg;
195
196 WRT_REG_DWORD(&reg->iobase_addr, iobase);
197 dmp_reg = &reg->iobase_window;
198 while (count--)
199 *buf++ = htonl(RD_REG_DWORD(dmp_reg++));
200
201 return buf;
202}
203
204static inline int
205qla24xx_pause_risc(struct device_reg_24xx __iomem *reg)
206{
207 int rval = QLA_SUCCESS;
208 uint32_t cnt;
209
c3b058af 210 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
aed10881
AV		 211 for (cnt = 30000;
212 ((RD_REG_DWORD(&reg->host_status) & HSRX_RISC_PAUSED) == 0) &&
c3b058af
AV		 213 rval == QLA_SUCCESS; cnt--) {
214 if (cnt)
215 udelay(100);
216 else
217 rval = QLA_FUNCTION_TIMEOUT;
c81d04c9
AV		 218 }
219
220 return rval;
221}
222
223static int
7b867cf7 224qla24xx_soft_reset(struct qla_hw_data *ha)
c81d04c9
AV		 225{
226 int rval = QLA_SUCCESS;
227 uint32_t cnt;
228 uint16_t mb0, wd;
229 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
230
231 /* Reset RISC. */
232 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
233 for (cnt = 0; cnt < 30000; cnt++) {
234 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
235 break;
236
237 udelay(10);
238 }
239
240 WRT_REG_DWORD(&reg->ctrl_status,
241 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
242 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
243
244 udelay(100);
245 /* Wait for firmware to complete NVRAM accesses. */
246 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
247 for (cnt = 10000 ; cnt && mb0; cnt--) {
248 udelay(5);
249 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
250 barrier();
251 }
252
253 /* Wait for soft-reset to complete. */
254 for (cnt = 0; cnt < 30000; cnt++) {
255 if ((RD_REG_DWORD(&reg->ctrl_status) &
256 CSRX_ISP_SOFT_RESET) == 0)
257 break;
258
259 udelay(10);
260 }
261 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
262 RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
263
264 for (cnt = 30000; RD_REG_WORD(&reg->mailbox0) != 0 &&
265 rval == QLA_SUCCESS; cnt--) {
266 if (cnt)
267 udelay(100);
268 else
269 rval = QLA_FUNCTION_TIMEOUT;
270 }
271
272 return rval;
273}
274
c5722708 275static int
7b867cf7 276qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint16_t *ram,
e18e963b 277 uint32_t ram_words, void **nxt)
c5722708
AV		 278{
279 int rval;
280 uint32_t cnt, stat, timer, words, idx;
281 uint16_t mb0;
282 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
283 dma_addr_t dump_dma = ha->gid_list_dma;
284 uint16_t *dump = (uint16_t *)ha->gid_list;
285
286 rval = QLA_SUCCESS;
287 mb0 = 0;
288
289 WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED);
290 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
291
642ef983 292 words = qla2x00_gid_list_size(ha) / 2;
c5722708
AV		 293 for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS;
294 cnt += words, addr += words) {
295 if (cnt + words > ram_words)
296 words = ram_words - cnt;
297
298 WRT_MAILBOX_REG(ha, reg, 1, LSW(addr));
299 WRT_MAILBOX_REG(ha, reg, 8, MSW(addr));
300
301 WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma));
302 WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma));
303 WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma)));
304 WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma)));
305
306 WRT_MAILBOX_REG(ha, reg, 4, words);
307 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
308
309 for (timer = 6000000; timer; timer--) {
310 /* Check for pending interrupts. */
311 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
312 if (stat & HSR_RISC_INT) {
313 stat &= 0xff;
314
315 if (stat == 0x1 || stat == 0x2) {
316 set_bit(MBX_INTERRUPT,
317 &ha->mbx_cmd_flags);
318
319 mb0 = RD_MAILBOX_REG(ha, reg, 0);
320
321 /* Release mailbox registers. */
322 WRT_REG_WORD(&reg->semaphore, 0);
323 WRT_REG_WORD(&reg->hccr,
324 HCCR_CLR_RISC_INT);
325 RD_REG_WORD(&reg->hccr);
326 break;
327 } else if (stat == 0x10 || stat == 0x11) {
328 set_bit(MBX_INTERRUPT,
329 &ha->mbx_cmd_flags);
330
331 mb0 = RD_MAILBOX_REG(ha, reg, 0);
332
333 WRT_REG_WORD(&reg->hccr,
334 HCCR_CLR_RISC_INT);
335 RD_REG_WORD(&reg->hccr);
336 break;
337 }
338
339 /* clear this intr; it wasn't a mailbox intr */
340 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
341 RD_REG_WORD(&reg->hccr);
342 }
343 udelay(5);
344 }
345
346 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
347 rval = mb0 & MBS_MASK;
348 for (idx = 0; idx < words; idx++)
349 ram[cnt + idx] = swab16(dump[idx]);
350 } else {
351 rval = QLA_FUNCTION_FAILED;
352 }
353 }
354
355 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
356 return rval;
357}
358
c81d04c9
AV		 359static inline void
360qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
361 uint16_t *buf)
362{
363 uint16_t __iomem *dmp_reg = &reg->u.isp2300.fb_cmd;
364
365 while (count--)
366 *buf++ = htons(RD_REG_WORD(dmp_reg++));
367}
368
bb99de67
AV		 369static inline void *
370qla24xx_copy_eft(struct qla_hw_data *ha, void *ptr)
371{
372 if (!ha->eft)
373 return ptr;
374
375 memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size));
376 return ptr + ntohl(ha->fw_dump->eft_size);
377}
378
379static inline void *
380qla25xx_copy_fce(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
381{
382 uint32_t cnt;
383 uint32_t *iter_reg;
384 struct qla2xxx_fce_chain *fcec = ptr;
385
386 if (!ha->fce)
387 return ptr;
388
389 *last_chain = &fcec->type;
390 fcec->type = __constant_htonl(DUMP_CHAIN_FCE);
391 fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) +
392 fce_calc_size(ha->fce_bufs));
393 fcec->size = htonl(fce_calc_size(ha->fce_bufs));
394 fcec->addr_l = htonl(LSD(ha->fce_dma));
395 fcec->addr_h = htonl(MSD(ha->fce_dma));
396
397 iter_reg = fcec->eregs;
398 for (cnt = 0; cnt < 8; cnt++)
399 *iter_reg++ = htonl(ha->fce_mb[cnt]);
400
401 memcpy(iter_reg, ha->fce, ntohl(fcec->size));
402
3cb0a67d 403 return (char *)iter_reg + ntohl(fcec->size);
bb99de67
AV		 404}
405
2d70c103
NB		 406static inline void *
407qla2xxx_copy_atioqueues(struct qla_hw_data *ha, void *ptr,
408 uint32_t **last_chain)
409{
410 struct qla2xxx_mqueue_chain *q;
411 struct qla2xxx_mqueue_header *qh;
412 uint32_t num_queues;
413 int que;
414 struct {
415 int length;
416 void *ring;
417 } aq, *aqp;
418
00876ae8 419 if (!ha->tgt.atio_ring)
2d70c103
NB		 420 return ptr;
421
422 num_queues = 1;
423 aqp = &aq;
424 aqp->length = ha->tgt.atio_q_length;
425 aqp->ring = ha->tgt.atio_ring;
426
427 for (que = 0; que < num_queues; que++) {
428 /* aqp = ha->atio_q_map[que]; */
429 q = ptr;
430 *last_chain = &q->type;
431 q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
432 q->chain_size = htonl(
433 sizeof(struct qla2xxx_mqueue_chain) +
434 sizeof(struct qla2xxx_mqueue_header) +
435 (aqp->length * sizeof(request_t)));
436 ptr += sizeof(struct qla2xxx_mqueue_chain);
437
438 /* Add header. */
439 qh = ptr;
440 qh->queue = __constant_htonl(TYPE_ATIO_QUEUE);
441 qh->number = htonl(que);
442 qh->size = htonl(aqp->length * sizeof(request_t));
443 ptr += sizeof(struct qla2xxx_mqueue_header);
444
445 /* Add data. */
446 memcpy(ptr, aqp->ring, aqp->length * sizeof(request_t));
447
448 ptr += aqp->length * sizeof(request_t);
449 }
450
451 return ptr;
452}
453
050c9bb1
GM		 454static inline void *
455qla25xx_copy_mqueues(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
456{
457 struct qla2xxx_mqueue_chain *q;
458 struct qla2xxx_mqueue_header *qh;
459 struct req_que *req;
460 struct rsp_que *rsp;
461 int que;
462
463 if (!ha->mqenable)
464 return ptr;
465
466 /* Request queues */
467 for (que = 1; que < ha->max_req_queues; que++) {
468 req = ha->req_q_map[que];
469 if (!req)
470 break;
471
472 /* Add chain. */
473 q = ptr;
474 *last_chain = &q->type;
475 q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
476 q->chain_size = htonl(
477 sizeof(struct qla2xxx_mqueue_chain) +
478 sizeof(struct qla2xxx_mqueue_header) +
479 (req->length * sizeof(request_t)));
480 ptr += sizeof(struct qla2xxx_mqueue_chain);
481
482 /* Add header. */
483 qh = ptr;
484 qh->queue = __constant_htonl(TYPE_REQUEST_QUEUE);
485 qh->number = htonl(que);
486 qh->size = htonl(req->length * sizeof(request_t));
487 ptr += sizeof(struct qla2xxx_mqueue_header);
488
489 /* Add data. */
490 memcpy(ptr, req->ring, req->length * sizeof(request_t));
491 ptr += req->length * sizeof(request_t);
492 }
493
494 /* Response queues */
495 for (que = 1; que < ha->max_rsp_queues; que++) {
496 rsp = ha->rsp_q_map[que];
497 if (!rsp)
498 break;
499
500 /* Add chain. */
501 q = ptr;
502 *last_chain = &q->type;
503 q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
504 q->chain_size = htonl(
505 sizeof(struct qla2xxx_mqueue_chain) +
506 sizeof(struct qla2xxx_mqueue_header) +
507 (rsp->length * sizeof(response_t)));
508 ptr += sizeof(struct qla2xxx_mqueue_chain);
509
510 /* Add header. */
511 qh = ptr;
512 qh->queue = __constant_htonl(TYPE_RESPONSE_QUEUE);
513 qh->number = htonl(que);
514 qh->size = htonl(rsp->length * sizeof(response_t));
515 ptr += sizeof(struct qla2xxx_mqueue_header);
516
517 /* Add data. */
518 memcpy(ptr, rsp->ring, rsp->length * sizeof(response_t));
519 ptr += rsp->length * sizeof(response_t);
520 }
521
522 return ptr;
523}
524
d63ab533
AV		 525static inline void *
526qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
527{
528 uint32_t cnt, que_idx;
2afa19a9 529 uint8_t que_cnt;
d63ab533 530 struct qla2xxx_mq_chain *mq = ptr;
da9b1d5c 531 device_reg_t __iomem *reg;
d63ab533 532
6246b8a1 533 if (!ha->mqenable || IS_QLA83XX(ha))
d63ab533
AV		 534 return ptr;
535
536 mq = ptr;
537 *last_chain = &mq->type;
538 mq->type = __constant_htonl(DUMP_CHAIN_MQ);
539 mq->chain_size = __constant_htonl(sizeof(struct qla2xxx_mq_chain));
540
2afa19a9
AC		 541 que_cnt = ha->max_req_queues > ha->max_rsp_queues ?
542 ha->max_req_queues : ha->max_rsp_queues;
d63ab533
AV		 543 mq->count = htonl(que_cnt);
544 for (cnt = 0; cnt < que_cnt; cnt++) {
da9b1d5c 545 reg = ISP_QUE_REG(ha, cnt);
d63ab533 546 que_idx = cnt * 4;
da9b1d5c
AV		 547 mq->qregs[que_idx] =
548 htonl(RD_REG_DWORD(&reg->isp25mq.req_q_in));
549 mq->qregs[que_idx+1] =
550 htonl(RD_REG_DWORD(&reg->isp25mq.req_q_out));
551 mq->qregs[que_idx+2] =
552 htonl(RD_REG_DWORD(&reg->isp25mq.rsp_q_in));
553 mq->qregs[que_idx+3] =
554 htonl(RD_REG_DWORD(&reg->isp25mq.rsp_q_out));
d63ab533
AV		 555 }
556
557 return ptr + sizeof(struct qla2xxx_mq_chain);
558}
559
08de2844 560void
3420d36c
AV		 561qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval)
562{
563 struct qla_hw_data *ha = vha->hw;
564
565 if (rval != QLA_SUCCESS) {
7c3df132
SK		 566 ql_log(ql_log_warn, vha, 0xd000,
567 "Failed to dump firmware (%x).\n", rval);
3420d36c
AV		 568 ha->fw_dumped = 0;
569 } else {
7c3df132 570 ql_log(ql_log_info, vha, 0xd001,
3420d36c
AV		 571 "Firmware dump saved to temp buffer (%ld/%p).\n",
572 vha->host_no, ha->fw_dump);
573 ha->fw_dumped = 1;
574 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
575 }
576}
577
1da177e4
LT		 578/**
579 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
580 * @ha: HA context
581 * @hardware_locked: Called with the hardware_lock
582 */
583void
7b867cf7 584qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1da177e4
LT		 585{
586 int rval;
c5722708 587 uint32_t cnt;
7b867cf7 588 struct qla_hw_data *ha = vha->hw;
3d71644c 589 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 590 uint16_t __iomem *dmp_reg;
591 unsigned long flags;
592 struct qla2300_fw_dump *fw;
c5722708 593 void *nxt;
73208dfd 594 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 595
1da177e4
LT		 596 flags = 0;
597
598 if (!hardware_locked)
599 spin_lock_irqsave(&ha->hardware_lock, flags);
600
d4e3e04d 601 if (!ha->fw_dump) {
7c3df132
SK		 602 ql_log(ql_log_warn, vha, 0xd002,
603 "No buffer available for dump.\n");
1da177e4
LT		 604 goto qla2300_fw_dump_failed;
605 }
606
d4e3e04d 607 if (ha->fw_dumped) {
7c3df132
SK		 608 ql_log(ql_log_warn, vha, 0xd003,
609 "Firmware has been previously dumped (%p) "
610 "-- ignoring request.\n",
611 ha->fw_dump);
1da177e4
LT		 612 goto qla2300_fw_dump_failed;
613 }
a7a167bf
AV		 614 fw = &ha->fw_dump->isp.isp23;
615 qla2xxx_prep_dump(ha, ha->fw_dump);
1da177e4
LT		 616
617 rval = QLA_SUCCESS;
a7a167bf 618 fw->hccr = htons(RD_REG_WORD(&reg->hccr));
1da177e4
LT		 619
620 /* Pause RISC. */
fa2a1ce5 621 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1da177e4
LT		 622 if (IS_QLA2300(ha)) {
623 for (cnt = 30000;
624 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
625 rval == QLA_SUCCESS; cnt--) {
626 if (cnt)
627 udelay(100);
628 else
629 rval = QLA_FUNCTION_TIMEOUT;
630 }
631 } else {
632 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
633 udelay(10);
634 }
635
636 if (rval == QLA_SUCCESS) {
c81d04c9 637 dmp_reg = &reg->flash_address;
fa2a1ce5 638 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
a7a167bf 639 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 640
c81d04c9 641 dmp_reg = &reg->u.isp2300.req_q_in;
fa2a1ce5 642 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
a7a167bf 643 fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 644
c81d04c9 645 dmp_reg = &reg->u.isp2300.mailbox0;
fa2a1ce5 646 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
a7a167bf 647 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4
LT		 648
649 WRT_REG_WORD(&reg->ctrl_status, 0x40);
c81d04c9 650 qla2xxx_read_window(reg, 32, fw->resp_dma_reg);
1da177e4
LT		 651
652 WRT_REG_WORD(&reg->ctrl_status, 0x50);
c81d04c9 653 qla2xxx_read_window(reg, 48, fw->dma_reg);
1da177e4
LT		 654
655 WRT_REG_WORD(&reg->ctrl_status, 0x00);
c81d04c9 656 dmp_reg = &reg->risc_hw;
fa2a1ce5 657 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
a7a167bf 658 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 659
fa2a1ce5 660 WRT_REG_WORD(&reg->pcr, 0x2000);
c81d04c9 661 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
1da177e4 662
fa2a1ce5 663 WRT_REG_WORD(&reg->pcr, 0x2200);
c81d04c9 664 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
1da177e4 665
fa2a1ce5 666 WRT_REG_WORD(&reg->pcr, 0x2400);
c81d04c9 667 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
1da177e4 668
fa2a1ce5 669 WRT_REG_WORD(&reg->pcr, 0x2600);
c81d04c9 670 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
1da177e4 671
fa2a1ce5 672 WRT_REG_WORD(&reg->pcr, 0x2800);
c81d04c9 673 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
1da177e4 674
fa2a1ce5 675 WRT_REG_WORD(&reg->pcr, 0x2A00);
c81d04c9 676 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
1da177e4 677
fa2a1ce5 678 WRT_REG_WORD(&reg->pcr, 0x2C00);
c81d04c9 679 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
1da177e4 680
fa2a1ce5 681 WRT_REG_WORD(&reg->pcr, 0x2E00);
c81d04c9 682 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
1da177e4 683
fa2a1ce5 684 WRT_REG_WORD(&reg->ctrl_status, 0x10);
c81d04c9 685 qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg);
1da177e4 686
fa2a1ce5 687 WRT_REG_WORD(&reg->ctrl_status, 0x20);
c81d04c9 688 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
1da177e4 689
fa2a1ce5 690 WRT_REG_WORD(&reg->ctrl_status, 0x30);
c81d04c9 691 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
1da177e4
LT		 692
693 /* Reset RISC. */
694 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
695 for (cnt = 0; cnt < 30000; cnt++) {
696 if ((RD_REG_WORD(&reg->ctrl_status) &
697 CSR_ISP_SOFT_RESET) == 0)
698 break;
699
700 udelay(10);
701 }
702 }
703
704 if (!IS_QLA2300(ha)) {
705 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
706 rval == QLA_SUCCESS; cnt--) {
707 if (cnt)
708 udelay(100);
709 else
710 rval = QLA_FUNCTION_TIMEOUT;
711 }
712 }
713
c5722708
AV		 714 /* Get RISC SRAM. */
715 if (rval == QLA_SUCCESS)
716 rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram,
717 sizeof(fw->risc_ram) / 2, &nxt);
1da177e4 718
c5722708
AV		 719 /* Get stack SRAM. */
720 if (rval == QLA_SUCCESS)
721 rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram,
722 sizeof(fw->stack_ram) / 2, &nxt);
1da177e4 723
c5722708
AV		 724 /* Get data SRAM. */
725 if (rval == QLA_SUCCESS)
726 rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram,
727 ha->fw_memory_size - 0x11000 + 1, &nxt);
1da177e4 728
a7a167bf 729 if (rval == QLA_SUCCESS)
73208dfd 730 qla2xxx_copy_queues(ha, nxt);
a7a167bf 731
3420d36c 732 qla2xxx_dump_post_process(base_vha, rval);
1da177e4
LT		 733
734qla2300_fw_dump_failed:
735 if (!hardware_locked)
736 spin_unlock_irqrestore(&ha->hardware_lock, flags);
737}
738
1da177e4
LT		 739/**
740 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
741 * @ha: HA context
742 * @hardware_locked: Called with the hardware_lock
743 */
744void
7b867cf7 745qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1da177e4
LT		 746{
747 int rval;
748 uint32_t cnt, timer;
749 uint16_t risc_address;
750 uint16_t mb0, mb2;
7b867cf7 751 struct qla_hw_data *ha = vha->hw;
3d71644c 752 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 753 uint16_t __iomem *dmp_reg;
754 unsigned long flags;
755 struct qla2100_fw_dump *fw;
73208dfd 756 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 757
758 risc_address = 0;
759 mb0 = mb2 = 0;
760 flags = 0;
761
762 if (!hardware_locked)
763 spin_lock_irqsave(&ha->hardware_lock, flags);
764
d4e3e04d 765 if (!ha->fw_dump) {
7c3df132
SK		 766 ql_log(ql_log_warn, vha, 0xd004,
767 "No buffer available for dump.\n");
1da177e4
LT		 768 goto qla2100_fw_dump_failed;
769 }
770
d4e3e04d 771 if (ha->fw_dumped) {
7c3df132
SK		 772 ql_log(ql_log_warn, vha, 0xd005,
773 "Firmware has been previously dumped (%p) "
774 "-- ignoring request.\n",
775 ha->fw_dump);
1da177e4
LT		 776 goto qla2100_fw_dump_failed;
777 }
a7a167bf
AV		 778 fw = &ha->fw_dump->isp.isp21;
779 qla2xxx_prep_dump(ha, ha->fw_dump);
1da177e4
LT		 780
781 rval = QLA_SUCCESS;
a7a167bf 782 fw->hccr = htons(RD_REG_WORD(&reg->hccr));
1da177e4
LT		 783
784 /* Pause RISC. */
fa2a1ce5 785 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1da177e4
LT		 786 for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
787 rval == QLA_SUCCESS; cnt--) {
788 if (cnt)
789 udelay(100);
790 else
791 rval = QLA_FUNCTION_TIMEOUT;
792 }
793 if (rval == QLA_SUCCESS) {
c81d04c9 794 dmp_reg = &reg->flash_address;
fa2a1ce5 795 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
a7a167bf 796 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 797
c81d04c9 798 dmp_reg = &reg->u.isp2100.mailbox0;
1da177e4 799 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
c81d04c9
AV		 800 if (cnt == 8)
801 dmp_reg = &reg->u_end.isp2200.mailbox8;
802
a7a167bf 803 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4
LT		 804 }
805
c81d04c9 806 dmp_reg = &reg->u.isp2100.unused_2[0];
fa2a1ce5 807 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
a7a167bf 808 fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4
LT		 809
810 WRT_REG_WORD(&reg->ctrl_status, 0x00);
c81d04c9 811 dmp_reg = &reg->risc_hw;
fa2a1ce5 812 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
a7a167bf 813 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 814
fa2a1ce5 815 WRT_REG_WORD(&reg->pcr, 0x2000);
c81d04c9 816 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
1da177e4 817
fa2a1ce5 818 WRT_REG_WORD(&reg->pcr, 0x2100);
c81d04c9 819 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
1da177e4 820
fa2a1ce5 821 WRT_REG_WORD(&reg->pcr, 0x2200);
c81d04c9 822 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
1da177e4 823
fa2a1ce5 824 WRT_REG_WORD(&reg->pcr, 0x2300);
c81d04c9 825 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
1da177e4 826
fa2a1ce5 827 WRT_REG_WORD(&reg->pcr, 0x2400);
c81d04c9 828 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
1da177e4 829
fa2a1ce5 830 WRT_REG_WORD(&reg->pcr, 0x2500);
c81d04c9 831 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
1da177e4 832
fa2a1ce5 833 WRT_REG_WORD(&reg->pcr, 0x2600);
c81d04c9 834 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
1da177e4 835
fa2a1ce5 836 WRT_REG_WORD(&reg->pcr, 0x2700);
c81d04c9 837 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
1da177e4 838
fa2a1ce5 839 WRT_REG_WORD(&reg->ctrl_status, 0x10);
c81d04c9 840 qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg);
1da177e4 841
fa2a1ce5 842 WRT_REG_WORD(&reg->ctrl_status, 0x20);
c81d04c9 843 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
1da177e4 844
fa2a1ce5 845 WRT_REG_WORD(&reg->ctrl_status, 0x30);
c81d04c9 846 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
1da177e4
LT		 847
848 /* Reset the ISP. */
849 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
850 }
851
852 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
853 rval == QLA_SUCCESS; cnt--) {
854 if (cnt)
855 udelay(100);
856 else
857 rval = QLA_FUNCTION_TIMEOUT;
858 }
859
860 /* Pause RISC. */
861 if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) &&
862 (RD_REG_WORD(&reg->mctr) & (BIT_1 | BIT_0)) != 0))) {
863
fa2a1ce5 864 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1da177e4
LT		 865 for (cnt = 30000;
866 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
867 rval == QLA_SUCCESS; cnt--) {
868 if (cnt)
869 udelay(100);
870 else
871 rval = QLA_FUNCTION_TIMEOUT;
872 }
873 if (rval == QLA_SUCCESS) {
874 /* Set memory configuration and timing. */
875 if (IS_QLA2100(ha))
876 WRT_REG_WORD(&reg->mctr, 0xf1);
877 else
878 WRT_REG_WORD(&reg->mctr, 0xf2);
879 RD_REG_WORD(&reg->mctr); /* PCI Posting. */
880
881 /* Release RISC. */
882 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
883 }
884 }
885
886 if (rval == QLA_SUCCESS) {
887 /* Get RISC SRAM. */
888 risc_address = 0x1000;
889 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
890 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
891 }
892 for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
893 cnt++, risc_address++) {
894 WRT_MAILBOX_REG(ha, reg, 1, risc_address);
895 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
896
897 for (timer = 6000000; timer != 0; timer--) {
898 /* Check for pending interrupts. */
899 if (RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) {
900 if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
901 set_bit(MBX_INTERRUPT,
902 &ha->mbx_cmd_flags);
903
904 mb0 = RD_MAILBOX_REG(ha, reg, 0);
905 mb2 = RD_MAILBOX_REG(ha, reg, 2);
906
907 WRT_REG_WORD(&reg->semaphore, 0);
908 WRT_REG_WORD(&reg->hccr,
909 HCCR_CLR_RISC_INT);
910 RD_REG_WORD(&reg->hccr);
911 break;
912 }
913 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
914 RD_REG_WORD(&reg->hccr);
915 }
916 udelay(5);
917 }
918
919 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
920 rval = mb0 & MBS_MASK;
a7a167bf 921 fw->risc_ram[cnt] = htons(mb2);
1da177e4
LT		 922 } else {
923 rval = QLA_FUNCTION_FAILED;
924 }
925 }
926
a7a167bf 927 if (rval == QLA_SUCCESS)
73208dfd 928 qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]);
a7a167bf 929
3420d36c 930 qla2xxx_dump_post_process(base_vha, rval);
1da177e4
LT		 931
932qla2100_fw_dump_failed:
933 if (!hardware_locked)
934 spin_unlock_irqrestore(&ha->hardware_lock, flags);
935}
936
6d9b61ed 937void
7b867cf7 938qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
6d9b61ed
AV		 939{
940 int rval;
c3a2f0df 941 uint32_t cnt;
6d9b61ed 942 uint32_t risc_address;
7b867cf7 943 struct qla_hw_data *ha = vha->hw;
6d9b61ed
AV		 944 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
945 uint32_t __iomem *dmp_reg;
946 uint32_t *iter_reg;
947 uint16_t __iomem *mbx_reg;
948 unsigned long flags;
949 struct qla24xx_fw_dump *fw;
950 uint32_t ext_mem_cnt;
c3a2f0df 951 void *nxt;
2d70c103
NB		 952 void *nxt_chain;
953 uint32_t *last_chain = NULL;
73208dfd 954 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
6d9b61ed 955
7ec0effd 956 if (IS_P3P_TYPE(ha))
a9083016
GM		 957 return;
958
6d9b61ed 959 risc_address = ext_mem_cnt = 0;
6d9b61ed
AV		 960 flags = 0;
961
962 if (!hardware_locked)
963 spin_lock_irqsave(&ha->hardware_lock, flags);
964
d4e3e04d 965 if (!ha->fw_dump) {
7c3df132
SK		 966 ql_log(ql_log_warn, vha, 0xd006,
967 "No buffer available for dump.\n");
6d9b61ed
AV		 968 goto qla24xx_fw_dump_failed;
969 }
970
971 if (ha->fw_dumped) {
7c3df132
SK		 972 ql_log(ql_log_warn, vha, 0xd007,
973 "Firmware has been previously dumped (%p) "
974 "-- ignoring request.\n",
975 ha->fw_dump);
6d9b61ed
AV		 976 goto qla24xx_fw_dump_failed;
977 }
a7a167bf
AV		 978 fw = &ha->fw_dump->isp.isp24;
979 qla2xxx_prep_dump(ha, ha->fw_dump);
6d9b61ed 980
a7a167bf 981 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
6d9b61ed
AV		 982
983 /* Pause RISC. */
c81d04c9
AV		 984 rval = qla24xx_pause_risc(reg);
985 if (rval != QLA_SUCCESS)
986 goto qla24xx_fw_dump_failed_0;
987
988 /* Host interface registers. */
989 dmp_reg = &reg->flash_addr;
990 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
991 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
992
993 /* Disable interrupts. */
994 WRT_REG_DWORD(&reg->ictrl, 0);
995 RD_REG_DWORD(&reg->ictrl);
996
997 /* Shadow registers. */
998 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
999 RD_REG_DWORD(&reg->iobase_addr);
1000 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1001 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1002
1003 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1004 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1005
1006 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1007 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1008
1009 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1010 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1011
1012 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1013 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1014
1015 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1016 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1017
1018 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1019 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1020
1021 /* Mailbox registers. */
1022 mbx_reg = &reg->mailbox0;
1023 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1024 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1025
1026 /* Transfer sequence registers. */
1027 iter_reg = fw->xseq_gp_reg;
1028 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1029 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1030 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1031 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1032 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1033 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1034 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1035 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1036
1037 qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg);
1038 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1039
1040 /* Receive sequence registers. */
1041 iter_reg = fw->rseq_gp_reg;
1042 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1043 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1044 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1045 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1046 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1047 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1048 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1049 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1050
1051 qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg);
1052 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1053 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1054
1055 /* Command DMA registers. */
1056 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1057
1058 /* Queues. */
1059 iter_reg = fw->req0_dma_reg;
1060 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1061 dmp_reg = &reg->iobase_q;
1062 for (cnt = 0; cnt < 7; cnt++)
1063 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1064
1065 iter_reg = fw->resp0_dma_reg;
1066 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1067 dmp_reg = &reg->iobase_q;
1068 for (cnt = 0; cnt < 7; cnt++)
1069 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1070
1071 iter_reg = fw->req1_dma_reg;
1072 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1073 dmp_reg = &reg->iobase_q;
1074 for (cnt = 0; cnt < 7; cnt++)
1075 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1076
1077 /* Transmit DMA registers. */
1078 iter_reg = fw->xmt0_dma_reg;
1079 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1080 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1081
1082 iter_reg = fw->xmt1_dma_reg;
1083 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1084 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1085
1086 iter_reg = fw->xmt2_dma_reg;
1087 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1088 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1089
1090 iter_reg = fw->xmt3_dma_reg;
1091 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1092 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1093
1094 iter_reg = fw->xmt4_dma_reg;
1095 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1096 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1097
1098 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1099
1100 /* Receive DMA registers. */
1101 iter_reg = fw->rcvt0_data_dma_reg;
1102 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1103 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1104
1105 iter_reg = fw->rcvt1_data_dma_reg;
1106 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1107 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1108
1109 /* RISC registers. */
1110 iter_reg = fw->risc_gp_reg;
1111 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1112 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1113 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1114 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1115 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1116 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1117 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1118 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1119
1120 /* Local memory controller registers. */
1121 iter_reg = fw->lmc_reg;
1122 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1123 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1124 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1125 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1126 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1127 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1128 qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1129
1130 /* Fibre Protocol Module registers. */
1131 iter_reg = fw->fpm_hdw_reg;
1132 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1133 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1134 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1135 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1136 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1137 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1138 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1139 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1140 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1141 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1142 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1143 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1144
1145 /* Frame Buffer registers. */
1146 iter_reg = fw->fb_hdw_reg;
1147 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1148 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1149 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1150 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1151 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1152 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1153 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1154 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1155 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1156 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1157 qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1158
1159 rval = qla24xx_soft_reset(ha);
1160 if (rval != QLA_SUCCESS)
1161 goto qla24xx_fw_dump_failed_0;
1162
1163 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
c5722708 1164 &nxt);
c81d04c9
AV		 1165 if (rval != QLA_SUCCESS)
1166 goto qla24xx_fw_dump_failed_0;
1167
73208dfd 1168 nxt = qla2xxx_copy_queues(ha, nxt);
bb99de67
AV		 1169
1170 qla24xx_copy_eft(ha, nxt);
c81d04c9 1171
2d70c103
NB		 1172 nxt_chain = (void *)ha->fw_dump + ha->chain_offset;
1173 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
1174 if (last_chain) {
1175 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1176 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1177 }
1178
1179 /* Adjust valid length. */
1180 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
1181
c81d04c9 1182qla24xx_fw_dump_failed_0:
3420d36c 1183 qla2xxx_dump_post_process(base_vha, rval);
6d9b61ed 1184
c3a2f0df
AV		 1185qla24xx_fw_dump_failed:
1186 if (!hardware_locked)
1187 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1188}
6d9b61ed 1189
c3a2f0df 1190void
7b867cf7 1191qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
c3a2f0df
AV		 1192{
1193 int rval;
1194 uint32_t cnt;
1195 uint32_t risc_address;
7b867cf7 1196 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 1197 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1198 uint32_t __iomem *dmp_reg;
1199 uint32_t *iter_reg;
1200 uint16_t __iomem *mbx_reg;
1201 unsigned long flags;
1202 struct qla25xx_fw_dump *fw;
1203 uint32_t ext_mem_cnt;
d63ab533 1204 void *nxt, *nxt_chain;
bb99de67 1205 uint32_t *last_chain = NULL;
73208dfd 1206 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
6d9b61ed 1207
c3a2f0df
AV		 1208 risc_address = ext_mem_cnt = 0;
1209 flags = 0;
6d9b61ed 1210
c3a2f0df
AV		 1211 if (!hardware_locked)
1212 spin_lock_irqsave(&ha->hardware_lock, flags);
6d9b61ed 1213
c3a2f0df 1214 if (!ha->fw_dump) {
7c3df132
SK		 1215 ql_log(ql_log_warn, vha, 0xd008,
1216 "No buffer available for dump.\n");
c3a2f0df
AV		 1217 goto qla25xx_fw_dump_failed;
1218 }
6d9b61ed 1219
c3a2f0df 1220 if (ha->fw_dumped) {
7c3df132
SK		 1221 ql_log(ql_log_warn, vha, 0xd009,
1222 "Firmware has been previously dumped (%p) "
1223 "-- ignoring request.\n",
1224 ha->fw_dump);
c3a2f0df
AV		 1225 goto qla25xx_fw_dump_failed;
1226 }
1227 fw = &ha->fw_dump->isp.isp25;
1228 qla2xxx_prep_dump(ha, ha->fw_dump);
b5836927 1229 ha->fw_dump->version = __constant_htonl(2);
6d9b61ed 1230
c3a2f0df 1231 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
6d9b61ed 1232
c3a2f0df 1233 /* Pause RISC. */
c81d04c9
AV		 1234 rval = qla24xx_pause_risc(reg);
1235 if (rval != QLA_SUCCESS)
1236 goto qla25xx_fw_dump_failed_0;
1237
b5836927
AV		 1238 /* Host/Risc registers. */
1239 iter_reg = fw->host_risc_reg;
1240 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1241 qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1242
1243 /* PCIe registers. */
1244 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1245 RD_REG_DWORD(&reg->iobase_addr);
1246 WRT_REG_DWORD(&reg->iobase_window, 0x01);
1247 dmp_reg = &reg->iobase_c4;
1248 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1249 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1250 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1251 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
73208dfd 1252
b5836927
AV		 1253 WRT_REG_DWORD(&reg->iobase_window, 0x00);
1254 RD_REG_DWORD(&reg->iobase_window);
1255
c81d04c9
AV		 1256 /* Host interface registers. */
1257 dmp_reg = &reg->flash_addr;
1258 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1259 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1260
1261 /* Disable interrupts. */
1262 WRT_REG_DWORD(&reg->ictrl, 0);
1263 RD_REG_DWORD(&reg->ictrl);
1264
1265 /* Shadow registers. */
1266 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1267 RD_REG_DWORD(&reg->iobase_addr);
1268 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1269 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1270
1271 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1272 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1273
1274 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1275 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1276
1277 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1278 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1279
1280 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1281 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1282
1283 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1284 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1285
1286 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1287 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1288
1289 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1290 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1291
1292 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1293 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1294
1295 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1296 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1297
1298 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1299 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1300
1301 /* RISC I/O register. */
1302 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1303 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1304
1305 /* Mailbox registers. */
1306 mbx_reg = &reg->mailbox0;
1307 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1308 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1309
1310 /* Transfer sequence registers. */
1311 iter_reg = fw->xseq_gp_reg;
1312 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1313 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1314 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1315 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1316 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1317 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1318 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1319 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1320
1321 iter_reg = fw->xseq_0_reg;
1322 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1323 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1324 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1325
1326 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1327
1328 /* Receive sequence registers. */
1329 iter_reg = fw->rseq_gp_reg;
1330 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1331 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1332 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1333 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1334 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1335 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1336 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1337 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1338
1339 iter_reg = fw->rseq_0_reg;
1340 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1341 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1342
1343 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1344 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1345
1346 /* Auxiliary sequence registers. */
1347 iter_reg = fw->aseq_gp_reg;
1348 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1349 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1350 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1351 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1352 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1353 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1354 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1355 qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1356
1357 iter_reg = fw->aseq_0_reg;
1358 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1359 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1360
1361 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1362 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1363
1364 /* Command DMA registers. */
1365 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1366
1367 /* Queues. */
1368 iter_reg = fw->req0_dma_reg;
1369 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1370 dmp_reg = &reg->iobase_q;
1371 for (cnt = 0; cnt < 7; cnt++)
1372 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1373
1374 iter_reg = fw->resp0_dma_reg;
1375 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1376 dmp_reg = &reg->iobase_q;
1377 for (cnt = 0; cnt < 7; cnt++)
1378 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1379
1380 iter_reg = fw->req1_dma_reg;
1381 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1382 dmp_reg = &reg->iobase_q;
1383 for (cnt = 0; cnt < 7; cnt++)
1384 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1385
1386 /* Transmit DMA registers. */
1387 iter_reg = fw->xmt0_dma_reg;
1388 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1389 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1390
1391 iter_reg = fw->xmt1_dma_reg;
1392 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1393 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1394
1395 iter_reg = fw->xmt2_dma_reg;
1396 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1397 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1398
1399 iter_reg = fw->xmt3_dma_reg;
1400 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1401 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1402
1403 iter_reg = fw->xmt4_dma_reg;
1404 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1405 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1406
1407 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1408
1409 /* Receive DMA registers. */
1410 iter_reg = fw->rcvt0_data_dma_reg;
1411 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1412 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1413
1414 iter_reg = fw->rcvt1_data_dma_reg;
1415 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1416 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1417
1418 /* RISC registers. */
1419 iter_reg = fw->risc_gp_reg;
1420 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1421 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1422 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1423 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1424 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1425 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1426 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1427 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1428
1429 /* Local memory controller registers. */
1430 iter_reg = fw->lmc_reg;
1431 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1432 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1433 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1434 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1435 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1436 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1437 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1438 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1439
1440 /* Fibre Protocol Module registers. */
1441 iter_reg = fw->fpm_hdw_reg;
1442 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1443 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1444 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1445 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1446 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1447 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1448 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1449 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1450 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1451 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1452 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1453 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1454
1455 /* Frame Buffer registers. */
1456 iter_reg = fw->fb_hdw_reg;
1457 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1458 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1459 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1460 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1461 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1462 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1463 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1464 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1465 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1466 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1467 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1468 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1469
d63ab533
AV		 1470 /* Multi queue registers */
1471 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
1472 &last_chain);
1473
c81d04c9
AV		 1474 rval = qla24xx_soft_reset(ha);
1475 if (rval != QLA_SUCCESS)
1476 goto qla25xx_fw_dump_failed_0;
1477
1478 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
c5722708 1479 &nxt);
c81d04c9
AV		 1480 if (rval != QLA_SUCCESS)
1481 goto qla25xx_fw_dump_failed_0;
1482
73208dfd 1483 nxt = qla2xxx_copy_queues(ha, nxt);
c81d04c9 1484
7f544d00 1485 qla24xx_copy_eft(ha, nxt);
df613b96 1486
d63ab533 1487 /* Chain entries -- started with MQ. */
050c9bb1
GM		 1488 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
1489 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
2d70c103 1490 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
bb99de67
AV		 1491 if (last_chain) {
1492 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1493 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1494 }
df613b96 1495
050c9bb1
GM		 1496 /* Adjust valid length. */
1497 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
1498
c81d04c9 1499qla25xx_fw_dump_failed_0:
3420d36c 1500 qla2xxx_dump_post_process(base_vha, rval);
6d9b61ed 1501
c3a2f0df 1502qla25xx_fw_dump_failed:
6d9b61ed
AV		 1503 if (!hardware_locked)
1504 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1505}
3a03eb79
AV		 1506
1507void
1508qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1509{
1510 int rval;
1511 uint32_t cnt;
1512 uint32_t risc_address;
1513 struct qla_hw_data *ha = vha->hw;
1514 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1515 uint32_t __iomem *dmp_reg;
1516 uint32_t *iter_reg;
1517 uint16_t __iomem *mbx_reg;
1518 unsigned long flags;
1519 struct qla81xx_fw_dump *fw;
1520 uint32_t ext_mem_cnt;
1521 void *nxt, *nxt_chain;
1522 uint32_t *last_chain = NULL;
1523 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1524
1525 risc_address = ext_mem_cnt = 0;
1526 flags = 0;
1527
1528 if (!hardware_locked)
1529 spin_lock_irqsave(&ha->hardware_lock, flags);
1530
1531 if (!ha->fw_dump) {
7c3df132
SK		 1532 ql_log(ql_log_warn, vha, 0xd00a,
1533 "No buffer available for dump.\n");
3a03eb79
AV		 1534 goto qla81xx_fw_dump_failed;
1535 }
1536
1537 if (ha->fw_dumped) {
7c3df132
SK		 1538 ql_log(ql_log_warn, vha, 0xd00b,
1539 "Firmware has been previously dumped (%p) "
1540 "-- ignoring request.\n",
1541 ha->fw_dump);
3a03eb79
AV		 1542 goto qla81xx_fw_dump_failed;
1543 }
1544 fw = &ha->fw_dump->isp.isp81;
1545 qla2xxx_prep_dump(ha, ha->fw_dump);
1546
1547 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
1548
1549 /* Pause RISC. */
1550 rval = qla24xx_pause_risc(reg);
1551 if (rval != QLA_SUCCESS)
1552 goto qla81xx_fw_dump_failed_0;
1553
1554 /* Host/Risc registers. */
1555 iter_reg = fw->host_risc_reg;
1556 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1557 qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1558
1559 /* PCIe registers. */
1560 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1561 RD_REG_DWORD(&reg->iobase_addr);
1562 WRT_REG_DWORD(&reg->iobase_window, 0x01);
1563 dmp_reg = &reg->iobase_c4;
1564 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1565 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1566 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1567 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
1568
1569 WRT_REG_DWORD(&reg->iobase_window, 0x00);
1570 RD_REG_DWORD(&reg->iobase_window);
1571
1572 /* Host interface registers. */
1573 dmp_reg = &reg->flash_addr;
1574 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1575 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1576
1577 /* Disable interrupts. */
1578 WRT_REG_DWORD(&reg->ictrl, 0);
1579 RD_REG_DWORD(&reg->ictrl);
1580
1581 /* Shadow registers. */
1582 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1583 RD_REG_DWORD(&reg->iobase_addr);
1584 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1585 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1586
1587 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1588 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1589
1590 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1591 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1592
1593 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1594 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1595
1596 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1597 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1598
1599 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1600 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1601
1602 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1603 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1604
1605 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1606 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1607
1608 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1609 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1610
1611 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1612 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1613
1614 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1615 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1616
1617 /* RISC I/O register. */
1618 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1619 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1620
1621 /* Mailbox registers. */
1622 mbx_reg = &reg->mailbox0;
1623 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1624 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1625
1626 /* Transfer sequence registers. */
1627 iter_reg = fw->xseq_gp_reg;
1628 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1629 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1630 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1631 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1632 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1633 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1634 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1635 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1636
1637 iter_reg = fw->xseq_0_reg;
1638 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1639 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1640 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1641
1642 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1643
1644 /* Receive sequence registers. */
1645 iter_reg = fw->rseq_gp_reg;
1646 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1647 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1648 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1649 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1650 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1651 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1652 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1653 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1654
1655 iter_reg = fw->rseq_0_reg;
1656 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1657 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1658
1659 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1660 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1661
1662 /* Auxiliary sequence registers. */
1663 iter_reg = fw->aseq_gp_reg;
1664 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1665 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1666 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1667 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1668 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1669 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1670 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1671 qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1672
1673 iter_reg = fw->aseq_0_reg;
1674 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1675 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1676
1677 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1678 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1679
1680 /* Command DMA registers. */
1681 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1682
1683 /* Queues. */
1684 iter_reg = fw->req0_dma_reg;
1685 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1686 dmp_reg = &reg->iobase_q;
1687 for (cnt = 0; cnt < 7; cnt++)
1688 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1689
1690 iter_reg = fw->resp0_dma_reg;
1691 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1692 dmp_reg = &reg->iobase_q;
1693 for (cnt = 0; cnt < 7; cnt++)
1694 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1695
1696 iter_reg = fw->req1_dma_reg;
1697 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1698 dmp_reg = &reg->iobase_q;
1699 for (cnt = 0; cnt < 7; cnt++)
1700 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1701
1702 /* Transmit DMA registers. */
1703 iter_reg = fw->xmt0_dma_reg;
1704 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1705 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1706
1707 iter_reg = fw->xmt1_dma_reg;
1708 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1709 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1710
1711 iter_reg = fw->xmt2_dma_reg;
1712 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1713 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1714
1715 iter_reg = fw->xmt3_dma_reg;
1716 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1717 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1718
1719 iter_reg = fw->xmt4_dma_reg;
1720 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1721 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1722
1723 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1724
1725 /* Receive DMA registers. */
1726 iter_reg = fw->rcvt0_data_dma_reg;
1727 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1728 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1729
1730 iter_reg = fw->rcvt1_data_dma_reg;
1731 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1732 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1733
1734 /* RISC registers. */
1735 iter_reg = fw->risc_gp_reg;
1736 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1737 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1738 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1739 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1740 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1741 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1742 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1743 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1744
1745 /* Local memory controller registers. */
1746 iter_reg = fw->lmc_reg;
1747 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1748 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1749 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1750 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1751 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1752 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1753 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1754 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1755
1756 /* Fibre Protocol Module registers. */
1757 iter_reg = fw->fpm_hdw_reg;
1758 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1759 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1760 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1761 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1762 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1763 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1764 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1765 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1766 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1767 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1768 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1769 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1770 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
1771 qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
1772
1773 /* Frame Buffer registers. */
1774 iter_reg = fw->fb_hdw_reg;
1775 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1776 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1777 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1778 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1779 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1780 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1781 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1782 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1783 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1784 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1785 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1786 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
1787 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1788
1789 /* Multi queue registers */
1790 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
1791 &last_chain);
1792
1793 rval = qla24xx_soft_reset(ha);
1794 if (rval != QLA_SUCCESS)
1795 goto qla81xx_fw_dump_failed_0;
1796
1797 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1798 &nxt);
1799 if (rval != QLA_SUCCESS)
1800 goto qla81xx_fw_dump_failed_0;
1801
1802 nxt = qla2xxx_copy_queues(ha, nxt);
1803
7f544d00 1804 qla24xx_copy_eft(ha, nxt);
3a03eb79
AV		 1805
1806 /* Chain entries -- started with MQ. */
050c9bb1
GM		 1807 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
1808 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
2d70c103 1809 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
3a03eb79
AV		 1810 if (last_chain) {
1811 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1812 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1813 }
1814
050c9bb1
GM		 1815 /* Adjust valid length. */
1816 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
1817
3a03eb79 1818qla81xx_fw_dump_failed_0:
3420d36c 1819 qla2xxx_dump_post_process(base_vha, rval);
3a03eb79
AV		 1820
1821qla81xx_fw_dump_failed:
1822 if (!hardware_locked)
1823 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1824}
1825
6246b8a1
GM		 1826void
1827qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1828{
1829 int rval;
1830 uint32_t cnt, reg_data;
1831 uint32_t risc_address;
1832 struct qla_hw_data *ha = vha->hw;
1833 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1834 uint32_t __iomem *dmp_reg;
1835 uint32_t *iter_reg;
1836 uint16_t __iomem *mbx_reg;
1837 unsigned long flags;
1838 struct qla83xx_fw_dump *fw;
1839 uint32_t ext_mem_cnt;
1840 void *nxt, *nxt_chain;
1841 uint32_t *last_chain = NULL;
1842 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1843
1844 risc_address = ext_mem_cnt = 0;
1845 flags = 0;
1846
1847 if (!hardware_locked)
1848 spin_lock_irqsave(&ha->hardware_lock, flags);
1849
1850 if (!ha->fw_dump) {
1851 ql_log(ql_log_warn, vha, 0xd00c,
1852 "No buffer available for dump!!!\n");
1853 goto qla83xx_fw_dump_failed;
1854 }
1855
1856 if (ha->fw_dumped) {
1857 ql_log(ql_log_warn, vha, 0xd00d,
1858 "Firmware has been previously dumped (%p) -- ignoring "
1859 "request...\n", ha->fw_dump);
1860 goto qla83xx_fw_dump_failed;
1861 }
1862 fw = &ha->fw_dump->isp.isp83;
1863 qla2xxx_prep_dump(ha, ha->fw_dump);
1864
1865 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
1866
1867 /* Pause RISC. */
1868 rval = qla24xx_pause_risc(reg);
1869 if (rval != QLA_SUCCESS)
1870 goto qla83xx_fw_dump_failed_0;
1871
1872 WRT_REG_DWORD(&reg->iobase_addr, 0x6000);
1873 dmp_reg = &reg->iobase_window;
1874 reg_data = RD_REG_DWORD(dmp_reg);
1875 WRT_REG_DWORD(dmp_reg, 0);
1876
1877 dmp_reg = &reg->unused_4_1[0];
1878 reg_data = RD_REG_DWORD(dmp_reg);
1879 WRT_REG_DWORD(dmp_reg, 0);
1880
1881 WRT_REG_DWORD(&reg->iobase_addr, 0x6010);
1882 dmp_reg = &reg->unused_4_1[2];
1883 reg_data = RD_REG_DWORD(dmp_reg);
1884 WRT_REG_DWORD(dmp_reg, 0);
1885
1886 /* select PCR and disable ecc checking and correction */
1887 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1888 RD_REG_DWORD(&reg->iobase_addr);
1889 WRT_REG_DWORD(&reg->iobase_select, 0x60000000); /* write to F0h = PCR */
1890
1891 /* Host/Risc registers. */
1892 iter_reg = fw->host_risc_reg;
1893 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1894 iter_reg = qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1895 qla24xx_read_window(reg, 0x7040, 16, iter_reg);
1896
1897 /* PCIe registers. */
1898 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1899 RD_REG_DWORD(&reg->iobase_addr);
1900 WRT_REG_DWORD(&reg->iobase_window, 0x01);
1901 dmp_reg = &reg->iobase_c4;
1902 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1903 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1904 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1905 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
1906
1907 WRT_REG_DWORD(&reg->iobase_window, 0x00);
1908 RD_REG_DWORD(&reg->iobase_window);
1909
1910 /* Host interface registers. */
1911 dmp_reg = &reg->flash_addr;
1912 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1913 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1914
1915 /* Disable interrupts. */
1916 WRT_REG_DWORD(&reg->ictrl, 0);
1917 RD_REG_DWORD(&reg->ictrl);
1918
1919 /* Shadow registers. */
1920 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1921 RD_REG_DWORD(&reg->iobase_addr);
1922 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1923 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1924
1925 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1926 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1927
1928 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1929 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1930
1931 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1932 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1933
1934 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1935 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1936
1937 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1938 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1939
1940 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1941 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1942
1943 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1944 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1945
1946 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1947 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1948
1949 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1950 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1951
1952 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1953 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1954
1955 /* RISC I/O register. */
1956 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1957 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1958
1959 /* Mailbox registers. */
1960 mbx_reg = &reg->mailbox0;
1961 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1962 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1963
1964 /* Transfer sequence registers. */
1965 iter_reg = fw->xseq_gp_reg;
1966 iter_reg = qla24xx_read_window(reg, 0xBE00, 16, iter_reg);
1967 iter_reg = qla24xx_read_window(reg, 0xBE10, 16, iter_reg);
1968 iter_reg = qla24xx_read_window(reg, 0xBE20, 16, iter_reg);
1969 iter_reg = qla24xx_read_window(reg, 0xBE30, 16, iter_reg);
1970 iter_reg = qla24xx_read_window(reg, 0xBE40, 16, iter_reg);
1971 iter_reg = qla24xx_read_window(reg, 0xBE50, 16, iter_reg);
1972 iter_reg = qla24xx_read_window(reg, 0xBE60, 16, iter_reg);
1973 iter_reg = qla24xx_read_window(reg, 0xBE70, 16, iter_reg);
1974 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1975 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1976 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1977 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1978 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1979 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1980 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1981 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1982
1983 iter_reg = fw->xseq_0_reg;
1984 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1985 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1986 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1987
1988 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1989
1990 qla24xx_read_window(reg, 0xBEF0, 16, fw->xseq_2_reg);
1991
1992 /* Receive sequence registers. */
1993 iter_reg = fw->rseq_gp_reg;
1994 iter_reg = qla24xx_read_window(reg, 0xFE00, 16, iter_reg);
1995 iter_reg = qla24xx_read_window(reg, 0xFE10, 16, iter_reg);
1996 iter_reg = qla24xx_read_window(reg, 0xFE20, 16, iter_reg);
1997 iter_reg = qla24xx_read_window(reg, 0xFE30, 16, iter_reg);
1998 iter_reg = qla24xx_read_window(reg, 0xFE40, 16, iter_reg);
1999 iter_reg = qla24xx_read_window(reg, 0xFE50, 16, iter_reg);
2000 iter_reg = qla24xx_read_window(reg, 0xFE60, 16, iter_reg);
2001 iter_reg = qla24xx_read_window(reg, 0xFE70, 16, iter_reg);
2002 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
2003 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
2004 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
2005 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
2006 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
2007 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
2008 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
2009 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
2010
2011 iter_reg = fw->rseq_0_reg;
2012 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
2013 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
2014
2015 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
2016 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
2017 qla24xx_read_window(reg, 0xFEF0, 16, fw->rseq_3_reg);
2018
2019 /* Auxiliary sequence registers. */
2020 iter_reg = fw->aseq_gp_reg;
2021 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
2022 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
2023 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
2024 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
2025 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
2026 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
2027 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
2028 iter_reg = qla24xx_read_window(reg, 0xB070, 16, iter_reg);
2029 iter_reg = qla24xx_read_window(reg, 0xB100, 16, iter_reg);
2030 iter_reg = qla24xx_read_window(reg, 0xB110, 16, iter_reg);
2031 iter_reg = qla24xx_read_window(reg, 0xB120, 16, iter_reg);
2032 iter_reg = qla24xx_read_window(reg, 0xB130, 16, iter_reg);
2033 iter_reg = qla24xx_read_window(reg, 0xB140, 16, iter_reg);
2034 iter_reg = qla24xx_read_window(reg, 0xB150, 16, iter_reg);
2035 iter_reg = qla24xx_read_window(reg, 0xB160, 16, iter_reg);
2036 qla24xx_read_window(reg, 0xB170, 16, iter_reg);
2037
2038 iter_reg = fw->aseq_0_reg;
2039 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
2040 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
2041
2042 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
2043 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
2044 qla24xx_read_window(reg, 0xB1F0, 16, fw->aseq_3_reg);
2045
2046 /* Command DMA registers. */
2047 iter_reg = fw->cmd_dma_reg;
2048 iter_reg = qla24xx_read_window(reg, 0x7100, 16, iter_reg);
2049 iter_reg = qla24xx_read_window(reg, 0x7120, 16, iter_reg);
2050 iter_reg = qla24xx_read_window(reg, 0x7130, 16, iter_reg);
2051 qla24xx_read_window(reg, 0x71F0, 16, iter_reg);
2052
2053 /* Queues. */
2054 iter_reg = fw->req0_dma_reg;
2055 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
2056 dmp_reg = &reg->iobase_q;
2057 for (cnt = 0; cnt < 7; cnt++)
2058 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
2059
2060 iter_reg = fw->resp0_dma_reg;
2061 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
2062 dmp_reg = &reg->iobase_q;
2063 for (cnt = 0; cnt < 7; cnt++)
2064 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
2065
2066 iter_reg = fw->req1_dma_reg;
2067 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
2068 dmp_reg = &reg->iobase_q;
2069 for (cnt = 0; cnt < 7; cnt++)
2070 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
2071
2072 /* Transmit DMA registers. */
2073 iter_reg = fw->xmt0_dma_reg;
2074 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
2075 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
2076
2077 iter_reg = fw->xmt1_dma_reg;
2078 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
2079 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
2080
2081 iter_reg = fw->xmt2_dma_reg;
2082 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
2083 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
2084
2085 iter_reg = fw->xmt3_dma_reg;
2086 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
2087 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
2088
2089 iter_reg = fw->xmt4_dma_reg;
2090 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
2091 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
2092
2093 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
2094
2095 /* Receive DMA registers. */
2096 iter_reg = fw->rcvt0_data_dma_reg;
2097 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
2098 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
2099
2100 iter_reg = fw->rcvt1_data_dma_reg;
2101 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
2102 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
2103
2104 /* RISC registers. */
2105 iter_reg = fw->risc_gp_reg;
2106 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
2107 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
2108 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
2109 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
2110 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
2111 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
2112 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
2113 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
2114
2115 /* Local memory controller registers. */
2116 iter_reg = fw->lmc_reg;
2117 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
2118 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
2119 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
2120 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
2121 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
2122 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
2123 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
2124 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
2125
2126 /* Fibre Protocol Module registers. */
2127 iter_reg = fw->fpm_hdw_reg;
2128 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
2129 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
2130 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
2131 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
2132 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
2133 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
2134 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
2135 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
2136 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
2137 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
2138 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
2139 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
2140 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
2141 iter_reg = qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
2142 iter_reg = qla24xx_read_window(reg, 0x40E0, 16, iter_reg);
2143 qla24xx_read_window(reg, 0x40F0, 16, iter_reg);
2144
2145 /* RQ0 Array registers. */
2146 iter_reg = fw->rq0_array_reg;
2147 iter_reg = qla24xx_read_window(reg, 0x5C00, 16, iter_reg);
2148 iter_reg = qla24xx_read_window(reg, 0x5C10, 16, iter_reg);
2149 iter_reg = qla24xx_read_window(reg, 0x5C20, 16, iter_reg);
2150 iter_reg = qla24xx_read_window(reg, 0x5C30, 16, iter_reg);
2151 iter_reg = qla24xx_read_window(reg, 0x5C40, 16, iter_reg);
2152 iter_reg = qla24xx_read_window(reg, 0x5C50, 16, iter_reg);
2153 iter_reg = qla24xx_read_window(reg, 0x5C60, 16, iter_reg);
2154 iter_reg = qla24xx_read_window(reg, 0x5C70, 16, iter_reg);
2155 iter_reg = qla24xx_read_window(reg, 0x5C80, 16, iter_reg);
2156 iter_reg = qla24xx_read_window(reg, 0x5C90, 16, iter_reg);
2157 iter_reg = qla24xx_read_window(reg, 0x5CA0, 16, iter_reg);
2158 iter_reg = qla24xx_read_window(reg, 0x5CB0, 16, iter_reg);
2159 iter_reg = qla24xx_read_window(reg, 0x5CC0, 16, iter_reg);
2160 iter_reg = qla24xx_read_window(reg, 0x5CD0, 16, iter_reg);
2161 iter_reg = qla24xx_read_window(reg, 0x5CE0, 16, iter_reg);
2162 qla24xx_read_window(reg, 0x5CF0, 16, iter_reg);
2163
2164 /* RQ1 Array registers. */
2165 iter_reg = fw->rq1_array_reg;
2166 iter_reg = qla24xx_read_window(reg, 0x5D00, 16, iter_reg);
2167 iter_reg = qla24xx_read_window(reg, 0x5D10, 16, iter_reg);
2168 iter_reg = qla24xx_read_window(reg, 0x5D20, 16, iter_reg);
2169 iter_reg = qla24xx_read_window(reg, 0x5D30, 16, iter_reg);
2170 iter_reg = qla24xx_read_window(reg, 0x5D40, 16, iter_reg);
2171 iter_reg = qla24xx_read_window(reg, 0x5D50, 16, iter_reg);
2172 iter_reg = qla24xx_read_window(reg, 0x5D60, 16, iter_reg);
2173 iter_reg = qla24xx_read_window(reg, 0x5D70, 16, iter_reg);
2174 iter_reg = qla24xx_read_window(reg, 0x5D80, 16, iter_reg);
2175 iter_reg = qla24xx_read_window(reg, 0x5D90, 16, iter_reg);
2176 iter_reg = qla24xx_read_window(reg, 0x5DA0, 16, iter_reg);
2177 iter_reg = qla24xx_read_window(reg, 0x5DB0, 16, iter_reg);
2178 iter_reg = qla24xx_read_window(reg, 0x5DC0, 16, iter_reg);
2179 iter_reg = qla24xx_read_window(reg, 0x5DD0, 16, iter_reg);
2180 iter_reg = qla24xx_read_window(reg, 0x5DE0, 16, iter_reg);
2181 qla24xx_read_window(reg, 0x5DF0, 16, iter_reg);
2182
2183 /* RP0 Array registers. */
2184 iter_reg = fw->rp0_array_reg;
2185 iter_reg = qla24xx_read_window(reg, 0x5E00, 16, iter_reg);
2186 iter_reg = qla24xx_read_window(reg, 0x5E10, 16, iter_reg);
2187 iter_reg = qla24xx_read_window(reg, 0x5E20, 16, iter_reg);
2188 iter_reg = qla24xx_read_window(reg, 0x5E30, 16, iter_reg);
2189 iter_reg = qla24xx_read_window(reg, 0x5E40, 16, iter_reg);
2190 iter_reg = qla24xx_read_window(reg, 0x5E50, 16, iter_reg);
2191 iter_reg = qla24xx_read_window(reg, 0x5E60, 16, iter_reg);
2192 iter_reg = qla24xx_read_window(reg, 0x5E70, 16, iter_reg);
2193 iter_reg = qla24xx_read_window(reg, 0x5E80, 16, iter_reg);
2194 iter_reg = qla24xx_read_window(reg, 0x5E90, 16, iter_reg);
2195 iter_reg = qla24xx_read_window(reg, 0x5EA0, 16, iter_reg);
2196 iter_reg = qla24xx_read_window(reg, 0x5EB0, 16, iter_reg);
2197 iter_reg = qla24xx_read_window(reg, 0x5EC0, 16, iter_reg);
2198 iter_reg = qla24xx_read_window(reg, 0x5ED0, 16, iter_reg);
2199 iter_reg = qla24xx_read_window(reg, 0x5EE0, 16, iter_reg);
2200 qla24xx_read_window(reg, 0x5EF0, 16, iter_reg);
2201
2202 /* RP1 Array registers. */
2203 iter_reg = fw->rp1_array_reg;
2204 iter_reg = qla24xx_read_window(reg, 0x5F00, 16, iter_reg);
2205 iter_reg = qla24xx_read_window(reg, 0x5F10, 16, iter_reg);
2206 iter_reg = qla24xx_read_window(reg, 0x5F20, 16, iter_reg);
2207 iter_reg = qla24xx_read_window(reg, 0x5F30, 16, iter_reg);
2208 iter_reg = qla24xx_read_window(reg, 0x5F40, 16, iter_reg);
2209 iter_reg = qla24xx_read_window(reg, 0x5F50, 16, iter_reg);
2210 iter_reg = qla24xx_read_window(reg, 0x5F60, 16, iter_reg);
2211 iter_reg = qla24xx_read_window(reg, 0x5F70, 16, iter_reg);
2212 iter_reg = qla24xx_read_window(reg, 0x5F80, 16, iter_reg);
2213 iter_reg = qla24xx_read_window(reg, 0x5F90, 16, iter_reg);
2214 iter_reg = qla24xx_read_window(reg, 0x5FA0, 16, iter_reg);
2215 iter_reg = qla24xx_read_window(reg, 0x5FB0, 16, iter_reg);
2216 iter_reg = qla24xx_read_window(reg, 0x5FC0, 16, iter_reg);
2217 iter_reg = qla24xx_read_window(reg, 0x5FD0, 16, iter_reg);
2218 iter_reg = qla24xx_read_window(reg, 0x5FE0, 16, iter_reg);
2219 qla24xx_read_window(reg, 0x5FF0, 16, iter_reg);
2220
2221 iter_reg = fw->at0_array_reg;
2222 iter_reg = qla24xx_read_window(reg, 0x7080, 16, iter_reg);
2223 iter_reg = qla24xx_read_window(reg, 0x7090, 16, iter_reg);
2224 iter_reg = qla24xx_read_window(reg, 0x70A0, 16, iter_reg);
2225 iter_reg = qla24xx_read_window(reg, 0x70B0, 16, iter_reg);
2226 iter_reg = qla24xx_read_window(reg, 0x70C0, 16, iter_reg);
2227 iter_reg = qla24xx_read_window(reg, 0x70D0, 16, iter_reg);
2228 iter_reg = qla24xx_read_window(reg, 0x70E0, 16, iter_reg);
2229 qla24xx_read_window(reg, 0x70F0, 16, iter_reg);
2230
2231 /* I/O Queue Control registers. */
2232 qla24xx_read_window(reg, 0x7800, 16, fw->queue_control_reg);
2233
2234 /* Frame Buffer registers. */
2235 iter_reg = fw->fb_hdw_reg;
2236 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
2237 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
2238 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
2239 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
2240 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
2241 iter_reg = qla24xx_read_window(reg, 0x6060, 16, iter_reg);
2242 iter_reg = qla24xx_read_window(reg, 0x6070, 16, iter_reg);
2243 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
2244 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
2245 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
2246 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
2247 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
2248 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
2249 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
2250 iter_reg = qla24xx_read_window(reg, 0x6530, 16, iter_reg);
2251 iter_reg = qla24xx_read_window(reg, 0x6540, 16, iter_reg);
2252 iter_reg = qla24xx_read_window(reg, 0x6550, 16, iter_reg);
2253 iter_reg = qla24xx_read_window(reg, 0x6560, 16, iter_reg);
2254 iter_reg = qla24xx_read_window(reg, 0x6570, 16, iter_reg);
2255 iter_reg = qla24xx_read_window(reg, 0x6580, 16, iter_reg);
2256 iter_reg = qla24xx_read_window(reg, 0x6590, 16, iter_reg);
2257 iter_reg = qla24xx_read_window(reg, 0x65A0, 16, iter_reg);
2258 iter_reg = qla24xx_read_window(reg, 0x65B0, 16, iter_reg);
2259 iter_reg = qla24xx_read_window(reg, 0x65C0, 16, iter_reg);
2260 iter_reg = qla24xx_read_window(reg, 0x65D0, 16, iter_reg);
2261 iter_reg = qla24xx_read_window(reg, 0x65E0, 16, iter_reg);
2262 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
2263
2264 /* Multi queue registers */
2265 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
2266 &last_chain);
2267
2268 rval = qla24xx_soft_reset(ha);
2269 if (rval != QLA_SUCCESS) {
2270 ql_log(ql_log_warn, vha, 0xd00e,
2271 "SOFT RESET FAILED, forcing continuation of dump!!!\n");
2272 rval = QLA_SUCCESS;
2273
2274 ql_log(ql_log_warn, vha, 0xd00f, "try a bigger hammer!!!\n");
2275
2276 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
2277 RD_REG_DWORD(&reg->hccr);
2278
2279 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
2280 RD_REG_DWORD(&reg->hccr);
2281
2282 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
2283 RD_REG_DWORD(&reg->hccr);
2284
2285 for (cnt = 30000; cnt && (RD_REG_WORD(&reg->mailbox0)); cnt--)
2286 udelay(5);
2287
2288 if (!cnt) {
2289 nxt = fw->code_ram;
8c0bc701 2290 nxt += sizeof(fw->code_ram);
6246b8a1
GM		 2291 nxt += (ha->fw_memory_size - 0x100000 + 1);
2292 goto copy_queue;
2293 } else
2294 ql_log(ql_log_warn, vha, 0xd010,
2295 "bigger hammer success?\n");
2296 }
2297
2298 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
2299 &nxt);
2300 if (rval != QLA_SUCCESS)
2301 goto qla83xx_fw_dump_failed_0;
2302
2303copy_queue:
2304 nxt = qla2xxx_copy_queues(ha, nxt);
2305
7f544d00 2306 qla24xx_copy_eft(ha, nxt);
6246b8a1
GM		 2307
2308 /* Chain entries -- started with MQ. */
2309 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
2310 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
2d70c103 2311 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
6246b8a1
GM		 2312 if (last_chain) {
2313 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
2314 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
2315 }
2316
2317 /* Adjust valid length. */
2318 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
2319
2320qla83xx_fw_dump_failed_0:
2321 qla2xxx_dump_post_process(base_vha, rval);
2322
2323qla83xx_fw_dump_failed:
2324 if (!hardware_locked)
2325 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2326}
2327
1da177e4
LT		 2328/****************************************************************************/
2329/* Driver Debug Functions. */
2330/****************************************************************************/
cfb0919c
CD		 2331
2332static inline int
2333ql_mask_match(uint32_t level)
2334{
2335 if (ql2xextended_error_logging == 1)
2336 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
2337 return (level & ql2xextended_error_logging) == level;
2338}
2339
3ce8866c
SK		 2340/*
2341 * This function is for formatting and logging debug information.
2342 * It is to be used when vha is available. It formats the message
2343 * and logs it to the messages file.
2344 * parameters:
2345 * level: The level of the debug messages to be printed.
2346 * If ql2xextended_error_logging value is correctly set,
2347 * this message will appear in the messages file.
2348 * vha: Pointer to the scsi_qla_host_t.
2349 * id: This is a unique identifier for the level. It identifies the
2350 * part of the code from where the message originated.
2351 * msg: The message to be displayed.
2352 */
2353void
086b3e8a
JP		 2354ql_dbg(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...)
2355{
2356 va_list va;
2357 struct va_format vaf;
3ce8866c 2358
cfb0919c 2359 if (!ql_mask_match(level))
086b3e8a 2360 return;
3ce8866c 2361
086b3e8a 2362 va_start(va, fmt);
3ce8866c 2363
086b3e8a
JP		 2364 vaf.fmt = fmt;
2365 vaf.va = &va;
3ce8866c 2366
086b3e8a
JP		 2367 if (vha != NULL) {
2368 const struct pci_dev *pdev = vha->hw->pdev;
2369 /* <module-name> <pci-name> <msg-id>:<host> Message */
2370 pr_warn("%s [%s]-%04x:%ld: %pV",
2371 QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset,
2372 vha->host_no, &vaf);
2373 } else {
2374 pr_warn("%s [%s]-%04x: : %pV",
2375 QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf);
3ce8866c
SK		 2376 }
2377
086b3e8a 2378 va_end(va);
3ce8866c
SK		 2379
2380}
2381
2382/*
2383 * This function is for formatting and logging debug information.
d6a03581 2384 * It is to be used when vha is not available and pci is available,
3ce8866c
SK		 2385 * i.e., before host allocation. It formats the message and logs it
2386 * to the messages file.
2387 * parameters:
2388 * level: The level of the debug messages to be printed.
2389 * If ql2xextended_error_logging value is correctly set,
2390 * this message will appear in the messages file.
2391 * pdev: Pointer to the struct pci_dev.
2392 * id: This is a unique id for the level. It identifies the part
2393 * of the code from where the message originated.
2394 * msg: The message to be displayed.
2395 */
2396void
086b3e8a
JP		 2397ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
2398 const char *fmt, ...)
2399{
2400 va_list va;
2401 struct va_format vaf;
3ce8866c
SK		 2402
2403 if (pdev == NULL)
2404 return;
cfb0919c 2405 if (!ql_mask_match(level))
086b3e8a 2406 return;
3ce8866c 2407
086b3e8a 2408 va_start(va, fmt);
3ce8866c 2409
086b3e8a
JP		 2410 vaf.fmt = fmt;
2411 vaf.va = &va;
3ce8866c 2412
086b3e8a
JP		 2413 /* <module-name> <dev-name>:<msg-id> Message */
2414 pr_warn("%s [%s]-%04x: : %pV",
2415 QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, &vaf);
3ce8866c 2416
086b3e8a 2417 va_end(va);
3ce8866c
SK		 2418}
2419
2420/*
2421 * This function is for formatting and logging log messages.
2422 * It is to be used when vha is available. It formats the message
2423 * and logs it to the messages file. All the messages will be logged
2424 * irrespective of value of ql2xextended_error_logging.
2425 * parameters:
2426 * level: The level of the log messages to be printed in the
2427 * messages file.
2428 * vha: Pointer to the scsi_qla_host_t
2429 * id: This is a unique id for the level. It identifies the
2430 * part of the code from where the message originated.
2431 * msg: The message to be displayed.
2432 */
2433void
086b3e8a
JP		 2434ql_log(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...)
2435{
2436 va_list va;
2437 struct va_format vaf;
2438 char pbuf[128];
3ce8866c 2439
086b3e8a
JP		 2440 if (level > ql_errlev)
2441 return;
3ce8866c 2442
086b3e8a
JP		 2443 if (vha != NULL) {
2444 const struct pci_dev *pdev = vha->hw->pdev;
2445 /* <module-name> <msg-id>:<host> Message */
2446 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x:%ld: ",
2447 QL_MSGHDR, dev_name(&(pdev->dev)), id, vha->host_no);
2448 } else {
2449 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
2450 QL_MSGHDR, "0000:00:00.0", id);
2451 }
2452 pbuf[sizeof(pbuf) - 1] = 0;
2453
2454 va_start(va, fmt);
2455
2456 vaf.fmt = fmt;
2457 vaf.va = &va;
2458
2459 switch (level) {
70a3fc76 2460 case ql_log_fatal: /* FATAL LOG */
086b3e8a
JP		 2461 pr_crit("%s%pV", pbuf, &vaf);
2462 break;
70a3fc76 2463 case ql_log_warn:
086b3e8a
JP		 2464 pr_err("%s%pV", pbuf, &vaf);
2465 break;
70a3fc76 2466 case ql_log_info:
086b3e8a
JP		 2467 pr_warn("%s%pV", pbuf, &vaf);
2468 break;
2469 default:
2470 pr_info("%s%pV", pbuf, &vaf);
2471 break;
3ce8866c
SK		 2472 }
2473
086b3e8a 2474 va_end(va);
3ce8866c
SK		 2475}
2476
2477/*
2478 * This function is for formatting and logging log messages.
d6a03581 2479 * It is to be used when vha is not available and pci is available,
3ce8866c
SK		 2480 * i.e., before host allocation. It formats the message and logs
2481 * it to the messages file. All the messages are logged irrespective
2482 * of the value of ql2xextended_error_logging.
2483 * parameters:
2484 * level: The level of the log messages to be printed in the
2485 * messages file.
2486 * pdev: Pointer to the struct pci_dev.
2487 * id: This is a unique id for the level. It identifies the
2488 * part of the code from where the message originated.
2489 * msg: The message to be displayed.
2490 */
2491void
086b3e8a
JP		 2492ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
2493 const char *fmt, ...)
2494{
2495 va_list va;
2496 struct va_format vaf;
2497 char pbuf[128];
3ce8866c
SK		 2498
2499 if (pdev == NULL)
2500 return;
086b3e8a
JP		 2501 if (level > ql_errlev)
2502 return;
3ce8866c 2503
086b3e8a
JP		 2504 /* <module-name> <dev-name>:<msg-id> Message */
2505 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
2506 QL_MSGHDR, dev_name(&(pdev->dev)), id);
2507 pbuf[sizeof(pbuf) - 1] = 0;
2508
2509 va_start(va, fmt);
2510
2511 vaf.fmt = fmt;
2512 vaf.va = &va;
2513
2514 switch (level) {
70a3fc76 2515 case ql_log_fatal: /* FATAL LOG */
086b3e8a
JP		 2516 pr_crit("%s%pV", pbuf, &vaf);
2517 break;
70a3fc76 2518 case ql_log_warn:
086b3e8a
JP		 2519 pr_err("%s%pV", pbuf, &vaf);
2520 break;
70a3fc76 2521 case ql_log_info:
086b3e8a
JP		 2522 pr_warn("%s%pV", pbuf, &vaf);
2523 break;
2524 default:
2525 pr_info("%s%pV", pbuf, &vaf);
2526 break;
3ce8866c
SK		 2527 }
2528
086b3e8a 2529 va_end(va);
3ce8866c
SK		 2530}
2531
2532void
2533ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id)
2534{
2535 int i;
2536 struct qla_hw_data *ha = vha->hw;
2537 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2538 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
2539 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
2540 uint16_t __iomem *mbx_reg;
2541
cfb0919c
CD		 2542 if (!ql_mask_match(level))
2543 return;
3ce8866c 2544
7ec0effd 2545 if (IS_P3P_TYPE(ha))
cfb0919c
CD		 2546 mbx_reg = &reg82->mailbox_in[0];
2547 else if (IS_FWI2_CAPABLE(ha))
2548 mbx_reg = &reg24->mailbox0;
2549 else
2550 mbx_reg = MAILBOX_REG(ha, reg, 0);
2551
2552 ql_dbg(level, vha, id, "Mailbox registers:\n");
2553 for (i = 0; i < 6; i++)
2554 ql_dbg(level, vha, id,
2555 "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++));
3ce8866c
SK		 2556}
2557
2558
2559void
2560ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id,
2561 uint8_t *b, uint32_t size)
2562{
2563 uint32_t cnt;
2564 uint8_t c;
cfb0919c
CD		 2565
2566 if (!ql_mask_match(level))
2567 return;
2568
2569 ql_dbg(level, vha, id, " 0 1 2 3 4 5 6 7 8 "
2570 "9 Ah Bh Ch Dh Eh Fh\n");
2571 ql_dbg(level, vha, id, "----------------------------------"
2572 "----------------------------\n");
2573
2574 ql_dbg(level, vha, id, " ");
2575 for (cnt = 0; cnt < size;) {
2576 c = *b++;
2577 printk("%02x", (uint32_t) c);
2578 cnt++;
2579 if (!(cnt % 16))
2580 printk("\n");
2581 else
2582 printk(" ");
3ce8866c 2583 }
cfb0919c
CD		 2584 if (cnt % 16)
2585 ql_dbg(level, vha, id, "\n");
3ce8866c 2586}
Linux kernel - Deliverables
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