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[SCSI] qla2xxx: Avoid redundant RISC reset during (re)-initialization.
[deliverable/linux.git] / drivers / scsi / qla2xxx / qla_dbg.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
01e58d8e 3 * Copyright (c) 2003-2008 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/delay.h>
10
a7a167bf 11static inline void
7b867cf7 12qla2xxx_prep_dump(struct qla_hw_data *ha, struct qla2xxx_fw_dump *fw_dump)
a7a167bf
AV		 13{
14 fw_dump->fw_major_version = htonl(ha->fw_major_version);
15 fw_dump->fw_minor_version = htonl(ha->fw_minor_version);
16 fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version);
17 fw_dump->fw_attributes = htonl(ha->fw_attributes);
18
19 fw_dump->vendor = htonl(ha->pdev->vendor);
20 fw_dump->device = htonl(ha->pdev->device);
21 fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor);
22 fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device);
23}
24
25static inline void *
73208dfd 26qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr)
a7a167bf 27{
73208dfd
AC		 28 struct req_que *req = ha->req_q_map[0];
29 struct rsp_que *rsp = ha->rsp_q_map[0];
a7a167bf 30 /* Request queue. */
7b867cf7 31 memcpy(ptr, req->ring, req->length *
a7a167bf
AV		 32 sizeof(request_t));
33
34 /* Response queue. */
7b867cf7
AC		 35 ptr += req->length * sizeof(request_t);
36 memcpy(ptr, rsp->ring, rsp->length *
a7a167bf
AV		 37 sizeof(response_t));
38
7b867cf7 39 return ptr + (rsp->length * sizeof(response_t));
a7a167bf 40}
1da177e4 41
c3a2f0df 42static int
7b867cf7 43qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram,
c5722708 44 uint32_t ram_dwords, void **nxt)
c3a2f0df
AV		 45{
46 int rval;
c5722708
AV		 47 uint32_t cnt, stat, timer, dwords, idx;
48 uint16_t mb0;
c3a2f0df 49 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
c5722708
AV		 50 dma_addr_t dump_dma = ha->gid_list_dma;
51 uint32_t *dump = (uint32_t *)ha->gid_list;
c3a2f0df
AV		 52
53 rval = QLA_SUCCESS;
c5722708 54 mb0 = 0;
c3a2f0df 55
c5722708 56 WRT_REG_WORD(&reg->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
c3a2f0df
AV		 57 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
58
c5722708
AV		 59 dwords = GID_LIST_SIZE / 4;
60 for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
61 cnt += dwords, addr += dwords) {
62 if (cnt + dwords > ram_dwords)
63 dwords = ram_dwords - cnt;
c3a2f0df 64
c5722708
AV		 65 WRT_REG_WORD(&reg->mailbox1, LSW(addr));
66 WRT_REG_WORD(&reg->mailbox8, MSW(addr));
c3a2f0df 67
c5722708
AV		 68 WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
69 WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
70 WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
71 WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
c3a2f0df 72
c5722708
AV		 73 WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
74 WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
c3a2f0df
AV		 75 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
76
77 for (timer = 6000000; timer; timer--) {
78 /* Check for pending interrupts. */
79 stat = RD_REG_DWORD(&reg->host_status);
80 if (stat & HSRX_RISC_INT) {
81 stat &= 0xff;
82
83 if (stat == 0x1 || stat == 0x2 ||
84 stat == 0x10 || stat == 0x11) {
85 set_bit(MBX_INTERRUPT,
86 &ha->mbx_cmd_flags);
87
c5722708 88 mb0 = RD_REG_WORD(&reg->mailbox0);
c3a2f0df
AV		 89
90 WRT_REG_DWORD(&reg->hccr,
91 HCCRX_CLR_RISC_INT);
92 RD_REG_DWORD(&reg->hccr);
93 break;
94 }
95
96 /* Clear this intr; it wasn't a mailbox intr */
97 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
98 RD_REG_DWORD(&reg->hccr);
99 }
100 udelay(5);
101 }
102
103 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
c5722708
AV		 104 rval = mb0 & MBS_MASK;
105 for (idx = 0; idx < dwords; idx++)
106 ram[cnt + idx] = swab32(dump[idx]);
c3a2f0df
AV		 107 } else {
108 rval = QLA_FUNCTION_FAILED;
109 }
110 }
111
c5722708 112 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
c3a2f0df
AV		 113 return rval;
114}
115
c5722708 116static int
7b867cf7 117qla24xx_dump_memory(struct qla_hw_data *ha, uint32_t *code_ram,
c5722708
AV		 118 uint32_t cram_size, void **nxt)
119{
120 int rval;
121
122 /* Code RAM. */
123 rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt);
124 if (rval != QLA_SUCCESS)
125 return rval;
126
127 /* External Memory. */
128 return qla24xx_dump_ram(ha, 0x100000, *nxt,
129 ha->fw_memory_size - 0x100000 + 1, nxt);
130}
131
c81d04c9
AV		 132static uint32_t *
133qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
134 uint32_t count, uint32_t *buf)
135{
136 uint32_t __iomem *dmp_reg;
137
138 WRT_REG_DWORD(&reg->iobase_addr, iobase);
139 dmp_reg = &reg->iobase_window;
140 while (count--)
141 *buf++ = htonl(RD_REG_DWORD(dmp_reg++));
142
143 return buf;
144}
145
146static inline int
147qla24xx_pause_risc(struct device_reg_24xx __iomem *reg)
148{
149 int rval = QLA_SUCCESS;
150 uint32_t cnt;
151
c3b058af
AV		 152 if (RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE)
153 return rval;
154
155 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
156 for (cnt = 30000; (RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE) == 0 &&
157 rval == QLA_SUCCESS; cnt--) {
158 if (cnt)
159 udelay(100);
160 else
161 rval = QLA_FUNCTION_TIMEOUT;
c81d04c9
AV		 162 }
163
164 return rval;
165}
166
167static int
7b867cf7 168qla24xx_soft_reset(struct qla_hw_data *ha)
c81d04c9
AV		 169{
170 int rval = QLA_SUCCESS;
171 uint32_t cnt;
172 uint16_t mb0, wd;
173 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
174
175 /* Reset RISC. */
176 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
177 for (cnt = 0; cnt < 30000; cnt++) {
178 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
179 break;
180
181 udelay(10);
182 }
183
184 WRT_REG_DWORD(&reg->ctrl_status,
185 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
186 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
187
188 udelay(100);
189 /* Wait for firmware to complete NVRAM accesses. */
190 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
191 for (cnt = 10000 ; cnt && mb0; cnt--) {
192 udelay(5);
193 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
194 barrier();
195 }
196
197 /* Wait for soft-reset to complete. */
198 for (cnt = 0; cnt < 30000; cnt++) {
199 if ((RD_REG_DWORD(&reg->ctrl_status) &
200 CSRX_ISP_SOFT_RESET) == 0)
201 break;
202
203 udelay(10);
204 }
205 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
206 RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
207
208 for (cnt = 30000; RD_REG_WORD(&reg->mailbox0) != 0 &&
209 rval == QLA_SUCCESS; cnt--) {
210 if (cnt)
211 udelay(100);
212 else
213 rval = QLA_FUNCTION_TIMEOUT;
214 }
215
216 return rval;
217}
218
c5722708 219static int
7b867cf7
AC		 220qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint16_t *ram,
221 uint16_t ram_words, void **nxt)
c5722708
AV		 222{
223 int rval;
224 uint32_t cnt, stat, timer, words, idx;
225 uint16_t mb0;
226 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
227 dma_addr_t dump_dma = ha->gid_list_dma;
228 uint16_t *dump = (uint16_t *)ha->gid_list;
229
230 rval = QLA_SUCCESS;
231 mb0 = 0;
232
233 WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED);
234 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
235
236 words = GID_LIST_SIZE / 2;
237 for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS;
238 cnt += words, addr += words) {
239 if (cnt + words > ram_words)
240 words = ram_words - cnt;
241
242 WRT_MAILBOX_REG(ha, reg, 1, LSW(addr));
243 WRT_MAILBOX_REG(ha, reg, 8, MSW(addr));
244
245 WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma));
246 WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma));
247 WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma)));
248 WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma)));
249
250 WRT_MAILBOX_REG(ha, reg, 4, words);
251 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
252
253 for (timer = 6000000; timer; timer--) {
254 /* Check for pending interrupts. */
255 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
256 if (stat & HSR_RISC_INT) {
257 stat &= 0xff;
258
259 if (stat == 0x1 || stat == 0x2) {
260 set_bit(MBX_INTERRUPT,
261 &ha->mbx_cmd_flags);
262
263 mb0 = RD_MAILBOX_REG(ha, reg, 0);
264
265 /* Release mailbox registers. */
266 WRT_REG_WORD(&reg->semaphore, 0);
267 WRT_REG_WORD(&reg->hccr,
268 HCCR_CLR_RISC_INT);
269 RD_REG_WORD(&reg->hccr);
270 break;
271 } else if (stat == 0x10 || stat == 0x11) {
272 set_bit(MBX_INTERRUPT,
273 &ha->mbx_cmd_flags);
274
275 mb0 = RD_MAILBOX_REG(ha, reg, 0);
276
277 WRT_REG_WORD(&reg->hccr,
278 HCCR_CLR_RISC_INT);
279 RD_REG_WORD(&reg->hccr);
280 break;
281 }
282
283 /* clear this intr; it wasn't a mailbox intr */
284 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
285 RD_REG_WORD(&reg->hccr);
286 }
287 udelay(5);
288 }
289
290 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
291 rval = mb0 & MBS_MASK;
292 for (idx = 0; idx < words; idx++)
293 ram[cnt + idx] = swab16(dump[idx]);
294 } else {
295 rval = QLA_FUNCTION_FAILED;
296 }
297 }
298
299 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
300 return rval;
301}
302
c81d04c9
AV		 303static inline void
304qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
305 uint16_t *buf)
306{
307 uint16_t __iomem *dmp_reg = &reg->u.isp2300.fb_cmd;
308
309 while (count--)
310 *buf++ = htons(RD_REG_WORD(dmp_reg++));
311}
312
bb99de67
AV		 313static inline void *
314qla24xx_copy_eft(struct qla_hw_data *ha, void *ptr)
315{
316 if (!ha->eft)
317 return ptr;
318
319 memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size));
320 return ptr + ntohl(ha->fw_dump->eft_size);
321}
322
323static inline void *
324qla25xx_copy_fce(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
325{
326 uint32_t cnt;
327 uint32_t *iter_reg;
328 struct qla2xxx_fce_chain *fcec = ptr;
329
330 if (!ha->fce)
331 return ptr;
332
333 *last_chain = &fcec->type;
334 fcec->type = __constant_htonl(DUMP_CHAIN_FCE);
335 fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) +
336 fce_calc_size(ha->fce_bufs));
337 fcec->size = htonl(fce_calc_size(ha->fce_bufs));
338 fcec->addr_l = htonl(LSD(ha->fce_dma));
339 fcec->addr_h = htonl(MSD(ha->fce_dma));
340
341 iter_reg = fcec->eregs;
342 for (cnt = 0; cnt < 8; cnt++)
343 *iter_reg++ = htonl(ha->fce_mb[cnt]);
344
345 memcpy(iter_reg, ha->fce, ntohl(fcec->size));
346
347 return iter_reg;
348}
349
d63ab533
AV		 350static inline void *
351qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
352{
353 uint32_t cnt, que_idx;
2afa19a9 354 uint8_t que_cnt;
d63ab533
AV		 355 struct qla2xxx_mq_chain *mq = ptr;
356 struct device_reg_25xxmq __iomem *reg;
357
358 if (!ha->mqenable)
359 return ptr;
360
361 mq = ptr;
362 *last_chain = &mq->type;
363 mq->type = __constant_htonl(DUMP_CHAIN_MQ);
364 mq->chain_size = __constant_htonl(sizeof(struct qla2xxx_mq_chain));
365
2afa19a9
AC		 366 que_cnt = ha->max_req_queues > ha->max_rsp_queues ?
367 ha->max_req_queues : ha->max_rsp_queues;
d63ab533
AV		 368 mq->count = htonl(que_cnt);
369 for (cnt = 0; cnt < que_cnt; cnt++) {
370 reg = (struct device_reg_25xxmq *) ((void *)
371 ha->mqiobase + cnt * QLA_QUE_PAGE);
372 que_idx = cnt * 4;
373 mq->qregs[que_idx] = htonl(RD_REG_DWORD(&reg->req_q_in));
374 mq->qregs[que_idx+1] = htonl(RD_REG_DWORD(&reg->req_q_out));
375 mq->qregs[que_idx+2] = htonl(RD_REG_DWORD(&reg->rsp_q_in));
376 mq->qregs[que_idx+3] = htonl(RD_REG_DWORD(&reg->rsp_q_out));
377 }
378
379 return ptr + sizeof(struct qla2xxx_mq_chain);
380}
381
1da177e4
LT		 382/**
383 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
384 * @ha: HA context
385 * @hardware_locked: Called with the hardware_lock
386 */
387void
7b867cf7 388qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1da177e4
LT		 389{
390 int rval;
c5722708 391 uint32_t cnt;
7b867cf7 392 struct qla_hw_data *ha = vha->hw;
3d71644c 393 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 394 uint16_t __iomem *dmp_reg;
395 unsigned long flags;
396 struct qla2300_fw_dump *fw;
c5722708 397 void *nxt;
73208dfd 398 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 399
1da177e4
LT		 400 flags = 0;
401
402 if (!hardware_locked)
403 spin_lock_irqsave(&ha->hardware_lock, flags);
404
d4e3e04d 405 if (!ha->fw_dump) {
1da177e4 406 qla_printk(KERN_WARNING, ha,
d4e3e04d 407 "No buffer available for dump!!!\n");
1da177e4
LT		 408 goto qla2300_fw_dump_failed;
409 }
410
d4e3e04d 411 if (ha->fw_dumped) {
1da177e4 412 qla_printk(KERN_WARNING, ha,
d4e3e04d
AV		 413 "Firmware has been previously dumped (%p) -- ignoring "
414 "request...\n", ha->fw_dump);
1da177e4
LT		 415 goto qla2300_fw_dump_failed;
416 }
a7a167bf
AV		 417 fw = &ha->fw_dump->isp.isp23;
418 qla2xxx_prep_dump(ha, ha->fw_dump);
1da177e4
LT		 419
420 rval = QLA_SUCCESS;
a7a167bf 421 fw->hccr = htons(RD_REG_WORD(&reg->hccr));
1da177e4
LT		 422
423 /* Pause RISC. */
fa2a1ce5 424 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1da177e4
LT		 425 if (IS_QLA2300(ha)) {
426 for (cnt = 30000;
427 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
428 rval == QLA_SUCCESS; cnt--) {
429 if (cnt)
430 udelay(100);
431 else
432 rval = QLA_FUNCTION_TIMEOUT;
433 }
434 } else {
435 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
436 udelay(10);
437 }
438
439 if (rval == QLA_SUCCESS) {
c81d04c9 440 dmp_reg = &reg->flash_address;
fa2a1ce5 441 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
a7a167bf 442 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 443
c81d04c9 444 dmp_reg = &reg->u.isp2300.req_q_in;
fa2a1ce5 445 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
a7a167bf 446 fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 447
c81d04c9 448 dmp_reg = &reg->u.isp2300.mailbox0;
fa2a1ce5 449 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
a7a167bf 450 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4
LT		 451
452 WRT_REG_WORD(&reg->ctrl_status, 0x40);
c81d04c9 453 qla2xxx_read_window(reg, 32, fw->resp_dma_reg);
1da177e4
LT		 454
455 WRT_REG_WORD(&reg->ctrl_status, 0x50);
c81d04c9 456 qla2xxx_read_window(reg, 48, fw->dma_reg);
1da177e4
LT		 457
458 WRT_REG_WORD(&reg->ctrl_status, 0x00);
c81d04c9 459 dmp_reg = &reg->risc_hw;
fa2a1ce5 460 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
a7a167bf 461 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 462
fa2a1ce5 463 WRT_REG_WORD(&reg->pcr, 0x2000);
c81d04c9 464 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
1da177e4 465
fa2a1ce5 466 WRT_REG_WORD(&reg->pcr, 0x2200);
c81d04c9 467 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
1da177e4 468
fa2a1ce5 469 WRT_REG_WORD(&reg->pcr, 0x2400);
c81d04c9 470 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
1da177e4 471
fa2a1ce5 472 WRT_REG_WORD(&reg->pcr, 0x2600);
c81d04c9 473 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
1da177e4 474
fa2a1ce5 475 WRT_REG_WORD(&reg->pcr, 0x2800);
c81d04c9 476 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
1da177e4 477
fa2a1ce5 478 WRT_REG_WORD(&reg->pcr, 0x2A00);
c81d04c9 479 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
1da177e4 480
fa2a1ce5 481 WRT_REG_WORD(&reg->pcr, 0x2C00);
c81d04c9 482 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
1da177e4 483
fa2a1ce5 484 WRT_REG_WORD(&reg->pcr, 0x2E00);
c81d04c9 485 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
1da177e4 486
fa2a1ce5 487 WRT_REG_WORD(&reg->ctrl_status, 0x10);
c81d04c9 488 qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg);
1da177e4 489
fa2a1ce5 490 WRT_REG_WORD(&reg->ctrl_status, 0x20);
c81d04c9 491 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
1da177e4 492
fa2a1ce5 493 WRT_REG_WORD(&reg->ctrl_status, 0x30);
c81d04c9 494 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
1da177e4
LT		 495
496 /* Reset RISC. */
497 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
498 for (cnt = 0; cnt < 30000; cnt++) {
499 if ((RD_REG_WORD(&reg->ctrl_status) &
500 CSR_ISP_SOFT_RESET) == 0)
501 break;
502
503 udelay(10);
504 }
505 }
506
507 if (!IS_QLA2300(ha)) {
508 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
509 rval == QLA_SUCCESS; cnt--) {
510 if (cnt)
511 udelay(100);
512 else
513 rval = QLA_FUNCTION_TIMEOUT;
514 }
515 }
516
c5722708
AV		 517 /* Get RISC SRAM. */
518 if (rval == QLA_SUCCESS)
519 rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram,
520 sizeof(fw->risc_ram) / 2, &nxt);
1da177e4 521
c5722708
AV		 522 /* Get stack SRAM. */
523 if (rval == QLA_SUCCESS)
524 rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram,
525 sizeof(fw->stack_ram) / 2, &nxt);
1da177e4 526
c5722708
AV		 527 /* Get data SRAM. */
528 if (rval == QLA_SUCCESS)
529 rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram,
530 ha->fw_memory_size - 0x11000 + 1, &nxt);
1da177e4 531
a7a167bf 532 if (rval == QLA_SUCCESS)
73208dfd 533 qla2xxx_copy_queues(ha, nxt);
a7a167bf 534
1da177e4
LT		 535 if (rval != QLA_SUCCESS) {
536 qla_printk(KERN_WARNING, ha,
537 "Failed to dump firmware (%x)!!!\n", rval);
d4e3e04d 538 ha->fw_dumped = 0;
1da177e4 539
1da177e4
LT		 540 } else {
541 qla_printk(KERN_INFO, ha,
542 "Firmware dump saved to temp buffer (%ld/%p).\n",
73208dfd 543 base_vha->host_no, ha->fw_dump);
d4e3e04d 544 ha->fw_dumped = 1;
1da177e4
LT		 545 }
546
547qla2300_fw_dump_failed:
548 if (!hardware_locked)
549 spin_unlock_irqrestore(&ha->hardware_lock, flags);
550}
551
1da177e4
LT		 552/**
553 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
554 * @ha: HA context
555 * @hardware_locked: Called with the hardware_lock
556 */
557void
7b867cf7 558qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1da177e4
LT		 559{
560 int rval;
561 uint32_t cnt, timer;
562 uint16_t risc_address;
563 uint16_t mb0, mb2;
7b867cf7 564 struct qla_hw_data *ha = vha->hw;
3d71644c 565 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 566 uint16_t __iomem *dmp_reg;
567 unsigned long flags;
568 struct qla2100_fw_dump *fw;
73208dfd 569 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 570
571 risc_address = 0;
572 mb0 = mb2 = 0;
573 flags = 0;
574
575 if (!hardware_locked)
576 spin_lock_irqsave(&ha->hardware_lock, flags);
577
d4e3e04d 578 if (!ha->fw_dump) {
1da177e4 579 qla_printk(KERN_WARNING, ha,
d4e3e04d 580 "No buffer available for dump!!!\n");
1da177e4
LT		 581 goto qla2100_fw_dump_failed;
582 }
583
d4e3e04d 584 if (ha->fw_dumped) {
1da177e4 585 qla_printk(KERN_WARNING, ha,
d4e3e04d
AV		 586 "Firmware has been previously dumped (%p) -- ignoring "
587 "request...\n", ha->fw_dump);
1da177e4
LT		 588 goto qla2100_fw_dump_failed;
589 }
a7a167bf
AV		 590 fw = &ha->fw_dump->isp.isp21;
591 qla2xxx_prep_dump(ha, ha->fw_dump);
1da177e4
LT		 592
593 rval = QLA_SUCCESS;
a7a167bf 594 fw->hccr = htons(RD_REG_WORD(&reg->hccr));
1da177e4
LT		 595
596 /* Pause RISC. */
fa2a1ce5 597 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1da177e4
LT		 598 for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
599 rval == QLA_SUCCESS; cnt--) {
600 if (cnt)
601 udelay(100);
602 else
603 rval = QLA_FUNCTION_TIMEOUT;
604 }
605 if (rval == QLA_SUCCESS) {
c81d04c9 606 dmp_reg = &reg->flash_address;
fa2a1ce5 607 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
a7a167bf 608 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 609
c81d04c9 610 dmp_reg = &reg->u.isp2100.mailbox0;
1da177e4 611 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
c81d04c9
AV		 612 if (cnt == 8)
613 dmp_reg = &reg->u_end.isp2200.mailbox8;
614
a7a167bf 615 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4
LT		 616 }
617
c81d04c9 618 dmp_reg = &reg->u.isp2100.unused_2[0];
fa2a1ce5 619 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
a7a167bf 620 fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4
LT		 621
622 WRT_REG_WORD(&reg->ctrl_status, 0x00);
c81d04c9 623 dmp_reg = &reg->risc_hw;
fa2a1ce5 624 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
a7a167bf 625 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 626
fa2a1ce5 627 WRT_REG_WORD(&reg->pcr, 0x2000);
c81d04c9 628 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
1da177e4 629
fa2a1ce5 630 WRT_REG_WORD(&reg->pcr, 0x2100);
c81d04c9 631 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
1da177e4 632
fa2a1ce5 633 WRT_REG_WORD(&reg->pcr, 0x2200);
c81d04c9 634 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
1da177e4 635
fa2a1ce5 636 WRT_REG_WORD(&reg->pcr, 0x2300);
c81d04c9 637 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
1da177e4 638
fa2a1ce5 639 WRT_REG_WORD(&reg->pcr, 0x2400);
c81d04c9 640 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
1da177e4 641
fa2a1ce5 642 WRT_REG_WORD(&reg->pcr, 0x2500);
c81d04c9 643 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
1da177e4 644
fa2a1ce5 645 WRT_REG_WORD(&reg->pcr, 0x2600);
c81d04c9 646 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
1da177e4 647
fa2a1ce5 648 WRT_REG_WORD(&reg->pcr, 0x2700);
c81d04c9 649 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
1da177e4 650
fa2a1ce5 651 WRT_REG_WORD(&reg->ctrl_status, 0x10);
c81d04c9 652 qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg);
1da177e4 653
fa2a1ce5 654 WRT_REG_WORD(&reg->ctrl_status, 0x20);
c81d04c9 655 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
1da177e4 656
fa2a1ce5 657 WRT_REG_WORD(&reg->ctrl_status, 0x30);
c81d04c9 658 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
1da177e4
LT		 659
660 /* Reset the ISP. */
661 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
662 }
663
664 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
665 rval == QLA_SUCCESS; cnt--) {
666 if (cnt)
667 udelay(100);
668 else
669 rval = QLA_FUNCTION_TIMEOUT;
670 }
671
672 /* Pause RISC. */
673 if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) &&
674 (RD_REG_WORD(&reg->mctr) & (BIT_1 | BIT_0)) != 0))) {
675
fa2a1ce5 676 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1da177e4
LT		 677 for (cnt = 30000;
678 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
679 rval == QLA_SUCCESS; cnt--) {
680 if (cnt)
681 udelay(100);
682 else
683 rval = QLA_FUNCTION_TIMEOUT;
684 }
685 if (rval == QLA_SUCCESS) {
686 /* Set memory configuration and timing. */
687 if (IS_QLA2100(ha))
688 WRT_REG_WORD(&reg->mctr, 0xf1);
689 else
690 WRT_REG_WORD(&reg->mctr, 0xf2);
691 RD_REG_WORD(&reg->mctr); /* PCI Posting. */
692
693 /* Release RISC. */
694 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
695 }
696 }
697
698 if (rval == QLA_SUCCESS) {
699 /* Get RISC SRAM. */
700 risc_address = 0x1000;
701 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
702 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
703 }
704 for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
705 cnt++, risc_address++) {
706 WRT_MAILBOX_REG(ha, reg, 1, risc_address);
707 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
708
709 for (timer = 6000000; timer != 0; timer--) {
710 /* Check for pending interrupts. */
711 if (RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) {
712 if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
713 set_bit(MBX_INTERRUPT,
714 &ha->mbx_cmd_flags);
715
716 mb0 = RD_MAILBOX_REG(ha, reg, 0);
717 mb2 = RD_MAILBOX_REG(ha, reg, 2);
718
719 WRT_REG_WORD(&reg->semaphore, 0);
720 WRT_REG_WORD(&reg->hccr,
721 HCCR_CLR_RISC_INT);
722 RD_REG_WORD(&reg->hccr);
723 break;
724 }
725 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
726 RD_REG_WORD(&reg->hccr);
727 }
728 udelay(5);
729 }
730
731 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
732 rval = mb0 & MBS_MASK;
a7a167bf 733 fw->risc_ram[cnt] = htons(mb2);
1da177e4
LT		 734 } else {
735 rval = QLA_FUNCTION_FAILED;
736 }
737 }
738
a7a167bf 739 if (rval == QLA_SUCCESS)
73208dfd 740 qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]);
a7a167bf 741
1da177e4
LT		 742 if (rval != QLA_SUCCESS) {
743 qla_printk(KERN_WARNING, ha,
744 "Failed to dump firmware (%x)!!!\n", rval);
d4e3e04d 745 ha->fw_dumped = 0;
1da177e4 746
1da177e4
LT		 747 } else {
748 qla_printk(KERN_INFO, ha,
749 "Firmware dump saved to temp buffer (%ld/%p).\n",
73208dfd 750 base_vha->host_no, ha->fw_dump);
d4e3e04d 751 ha->fw_dumped = 1;
1da177e4
LT		 752 }
753
754qla2100_fw_dump_failed:
755 if (!hardware_locked)
756 spin_unlock_irqrestore(&ha->hardware_lock, flags);
757}
758
6d9b61ed 759void
7b867cf7 760qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
6d9b61ed
AV		 761{
762 int rval;
c3a2f0df 763 uint32_t cnt;
6d9b61ed 764 uint32_t risc_address;
7b867cf7 765 struct qla_hw_data *ha = vha->hw;
6d9b61ed
AV		 766 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
767 uint32_t __iomem *dmp_reg;
768 uint32_t *iter_reg;
769 uint16_t __iomem *mbx_reg;
770 unsigned long flags;
771 struct qla24xx_fw_dump *fw;
772 uint32_t ext_mem_cnt;
c3a2f0df 773 void *nxt;
73208dfd 774 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
6d9b61ed
AV		 775
776 risc_address = ext_mem_cnt = 0;
6d9b61ed
AV		 777 flags = 0;
778
779 if (!hardware_locked)
780 spin_lock_irqsave(&ha->hardware_lock, flags);
781
d4e3e04d 782 if (!ha->fw_dump) {
6d9b61ed
AV		 783 qla_printk(KERN_WARNING, ha,
784 "No buffer available for dump!!!\n");
785 goto qla24xx_fw_dump_failed;
786 }
787
788 if (ha->fw_dumped) {
789 qla_printk(KERN_WARNING, ha,
790 "Firmware has been previously dumped (%p) -- ignoring "
d4e3e04d 791 "request...\n", ha->fw_dump);
6d9b61ed
AV		 792 goto qla24xx_fw_dump_failed;
793 }
a7a167bf
AV		 794 fw = &ha->fw_dump->isp.isp24;
795 qla2xxx_prep_dump(ha, ha->fw_dump);
6d9b61ed 796
a7a167bf 797 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
6d9b61ed
AV		 798
799 /* Pause RISC. */
c81d04c9
AV		 800 rval = qla24xx_pause_risc(reg);
801 if (rval != QLA_SUCCESS)
802 goto qla24xx_fw_dump_failed_0;
803
804 /* Host interface registers. */
805 dmp_reg = &reg->flash_addr;
806 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
807 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
808
809 /* Disable interrupts. */
810 WRT_REG_DWORD(&reg->ictrl, 0);
811 RD_REG_DWORD(&reg->ictrl);
812
813 /* Shadow registers. */
814 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
815 RD_REG_DWORD(&reg->iobase_addr);
816 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
817 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
818
819 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
820 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
821
822 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
823 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
824
825 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
826 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
827
828 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
829 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
830
831 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
832 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
833
834 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
835 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
836
837 /* Mailbox registers. */
838 mbx_reg = &reg->mailbox0;
839 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
840 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
841
842 /* Transfer sequence registers. */
843 iter_reg = fw->xseq_gp_reg;
844 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
845 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
846 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
847 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
848 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
849 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
850 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
851 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
852
853 qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg);
854 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
855
856 /* Receive sequence registers. */
857 iter_reg = fw->rseq_gp_reg;
858 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
859 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
860 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
861 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
862 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
863 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
864 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
865 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
866
867 qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg);
868 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
869 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
870
871 /* Command DMA registers. */
872 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
873
874 /* Queues. */
875 iter_reg = fw->req0_dma_reg;
876 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
877 dmp_reg = &reg->iobase_q;
878 for (cnt = 0; cnt < 7; cnt++)
879 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
880
881 iter_reg = fw->resp0_dma_reg;
882 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
883 dmp_reg = &reg->iobase_q;
884 for (cnt = 0; cnt < 7; cnt++)
885 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
886
887 iter_reg = fw->req1_dma_reg;
888 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
889 dmp_reg = &reg->iobase_q;
890 for (cnt = 0; cnt < 7; cnt++)
891 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
892
893 /* Transmit DMA registers. */
894 iter_reg = fw->xmt0_dma_reg;
895 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
896 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
897
898 iter_reg = fw->xmt1_dma_reg;
899 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
900 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
901
902 iter_reg = fw->xmt2_dma_reg;
903 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
904 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
905
906 iter_reg = fw->xmt3_dma_reg;
907 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
908 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
909
910 iter_reg = fw->xmt4_dma_reg;
911 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
912 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
913
914 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
915
916 /* Receive DMA registers. */
917 iter_reg = fw->rcvt0_data_dma_reg;
918 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
919 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
920
921 iter_reg = fw->rcvt1_data_dma_reg;
922 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
923 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
924
925 /* RISC registers. */
926 iter_reg = fw->risc_gp_reg;
927 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
928 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
929 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
930 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
931 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
932 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
933 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
934 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
935
936 /* Local memory controller registers. */
937 iter_reg = fw->lmc_reg;
938 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
939 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
940 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
941 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
942 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
943 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
944 qla24xx_read_window(reg, 0x3060, 16, iter_reg);
945
946 /* Fibre Protocol Module registers. */
947 iter_reg = fw->fpm_hdw_reg;
948 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
949 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
950 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
951 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
952 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
953 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
954 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
955 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
956 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
957 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
958 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
959 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
960
961 /* Frame Buffer registers. */
962 iter_reg = fw->fb_hdw_reg;
963 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
964 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
965 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
966 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
967 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
968 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
969 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
970 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
971 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
972 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
973 qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
974
975 rval = qla24xx_soft_reset(ha);
976 if (rval != QLA_SUCCESS)
977 goto qla24xx_fw_dump_failed_0;
978
979 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
c5722708 980 &nxt);
c81d04c9
AV		 981 if (rval != QLA_SUCCESS)
982 goto qla24xx_fw_dump_failed_0;
983
73208dfd 984 nxt = qla2xxx_copy_queues(ha, nxt);
bb99de67
AV		 985
986 qla24xx_copy_eft(ha, nxt);
c81d04c9
AV		 987
988qla24xx_fw_dump_failed_0:
c3a2f0df
AV		 989 if (rval != QLA_SUCCESS) {
990 qla_printk(KERN_WARNING, ha,
991 "Failed to dump firmware (%x)!!!\n", rval);
992 ha->fw_dumped = 0;
6d9b61ed 993
c3a2f0df
AV		 994 } else {
995 qla_printk(KERN_INFO, ha,
996 "Firmware dump saved to temp buffer (%ld/%p).\n",
73208dfd 997 base_vha->host_no, ha->fw_dump);
c3a2f0df
AV		 998 ha->fw_dumped = 1;
999 }
6d9b61ed 1000
c3a2f0df
AV		 1001qla24xx_fw_dump_failed:
1002 if (!hardware_locked)
1003 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1004}
6d9b61ed 1005
c3a2f0df 1006void
7b867cf7 1007qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
c3a2f0df
AV		 1008{
1009 int rval;
1010 uint32_t cnt;
1011 uint32_t risc_address;
7b867cf7 1012 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 1013 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1014 uint32_t __iomem *dmp_reg;
1015 uint32_t *iter_reg;
1016 uint16_t __iomem *mbx_reg;
1017 unsigned long flags;
1018 struct qla25xx_fw_dump *fw;
1019 uint32_t ext_mem_cnt;
d63ab533 1020 void *nxt, *nxt_chain;
bb99de67 1021 uint32_t *last_chain = NULL;
73208dfd 1022 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
6d9b61ed 1023
c3a2f0df
AV		 1024 risc_address = ext_mem_cnt = 0;
1025 flags = 0;
6d9b61ed 1026
c3a2f0df
AV		 1027 if (!hardware_locked)
1028 spin_lock_irqsave(&ha->hardware_lock, flags);
6d9b61ed 1029
c3a2f0df
AV		 1030 if (!ha->fw_dump) {
1031 qla_printk(KERN_WARNING, ha,
1032 "No buffer available for dump!!!\n");
1033 goto qla25xx_fw_dump_failed;
1034 }
6d9b61ed 1035
c3a2f0df
AV		 1036 if (ha->fw_dumped) {
1037 qla_printk(KERN_WARNING, ha,
1038 "Firmware has been previously dumped (%p) -- ignoring "
1039 "request...\n", ha->fw_dump);
1040 goto qla25xx_fw_dump_failed;
1041 }
1042 fw = &ha->fw_dump->isp.isp25;
1043 qla2xxx_prep_dump(ha, ha->fw_dump);
b5836927 1044 ha->fw_dump->version = __constant_htonl(2);
6d9b61ed 1045
c3a2f0df 1046 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
6d9b61ed 1047
c3a2f0df 1048 /* Pause RISC. */
c81d04c9
AV		 1049 rval = qla24xx_pause_risc(reg);
1050 if (rval != QLA_SUCCESS)
1051 goto qla25xx_fw_dump_failed_0;
1052
b5836927
AV		 1053 /* Host/Risc registers. */
1054 iter_reg = fw->host_risc_reg;
1055 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1056 qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1057
1058 /* PCIe registers. */
1059 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1060 RD_REG_DWORD(&reg->iobase_addr);
1061 WRT_REG_DWORD(&reg->iobase_window, 0x01);
1062 dmp_reg = &reg->iobase_c4;
1063 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1064 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1065 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1066 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
73208dfd 1067
b5836927
AV		 1068 WRT_REG_DWORD(&reg->iobase_window, 0x00);
1069 RD_REG_DWORD(&reg->iobase_window);
1070
c81d04c9
AV		 1071 /* Host interface registers. */
1072 dmp_reg = &reg->flash_addr;
1073 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1074 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1075
1076 /* Disable interrupts. */
1077 WRT_REG_DWORD(&reg->ictrl, 0);
1078 RD_REG_DWORD(&reg->ictrl);
1079
1080 /* Shadow registers. */
1081 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1082 RD_REG_DWORD(&reg->iobase_addr);
1083 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1084 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1085
1086 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1087 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1088
1089 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1090 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1091
1092 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1093 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1094
1095 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1096 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1097
1098 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1099 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1100
1101 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1102 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1103
1104 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1105 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1106
1107 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1108 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1109
1110 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1111 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1112
1113 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1114 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1115
1116 /* RISC I/O register. */
1117 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1118 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1119
1120 /* Mailbox registers. */
1121 mbx_reg = &reg->mailbox0;
1122 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1123 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1124
1125 /* Transfer sequence registers. */
1126 iter_reg = fw->xseq_gp_reg;
1127 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1128 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1129 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1130 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1131 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1132 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1133 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1134 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1135
1136 iter_reg = fw->xseq_0_reg;
1137 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1138 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1139 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1140
1141 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1142
1143 /* Receive sequence registers. */
1144 iter_reg = fw->rseq_gp_reg;
1145 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1146 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1147 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1148 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1149 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1150 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1151 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1152 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1153
1154 iter_reg = fw->rseq_0_reg;
1155 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1156 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1157
1158 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1159 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1160
1161 /* Auxiliary sequence registers. */
1162 iter_reg = fw->aseq_gp_reg;
1163 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1164 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1165 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1166 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1167 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1168 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1169 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1170 qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1171
1172 iter_reg = fw->aseq_0_reg;
1173 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1174 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1175
1176 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1177 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1178
1179 /* Command DMA registers. */
1180 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1181
1182 /* Queues. */
1183 iter_reg = fw->req0_dma_reg;
1184 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1185 dmp_reg = &reg->iobase_q;
1186 for (cnt = 0; cnt < 7; cnt++)
1187 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1188
1189 iter_reg = fw->resp0_dma_reg;
1190 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1191 dmp_reg = &reg->iobase_q;
1192 for (cnt = 0; cnt < 7; cnt++)
1193 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1194
1195 iter_reg = fw->req1_dma_reg;
1196 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1197 dmp_reg = &reg->iobase_q;
1198 for (cnt = 0; cnt < 7; cnt++)
1199 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1200
1201 /* Transmit DMA registers. */
1202 iter_reg = fw->xmt0_dma_reg;
1203 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1204 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1205
1206 iter_reg = fw->xmt1_dma_reg;
1207 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1208 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1209
1210 iter_reg = fw->xmt2_dma_reg;
1211 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1212 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1213
1214 iter_reg = fw->xmt3_dma_reg;
1215 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1216 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1217
1218 iter_reg = fw->xmt4_dma_reg;
1219 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1220 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1221
1222 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1223
1224 /* Receive DMA registers. */
1225 iter_reg = fw->rcvt0_data_dma_reg;
1226 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1227 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1228
1229 iter_reg = fw->rcvt1_data_dma_reg;
1230 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1231 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1232
1233 /* RISC registers. */
1234 iter_reg = fw->risc_gp_reg;
1235 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1236 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1237 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1238 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1239 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1240 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1241 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1242 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1243
1244 /* Local memory controller registers. */
1245 iter_reg = fw->lmc_reg;
1246 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1247 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1248 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1249 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1250 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1251 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1252 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1253 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1254
1255 /* Fibre Protocol Module registers. */
1256 iter_reg = fw->fpm_hdw_reg;
1257 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1258 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1259 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1260 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1261 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1262 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1263 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1264 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1265 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1266 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1267 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1268 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1269
1270 /* Frame Buffer registers. */
1271 iter_reg = fw->fb_hdw_reg;
1272 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1273 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1274 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1275 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1276 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1277 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1278 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1279 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1280 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1281 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1282 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1283 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1284
d63ab533
AV		 1285 /* Multi queue registers */
1286 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
1287 &last_chain);
1288
c81d04c9
AV		 1289 rval = qla24xx_soft_reset(ha);
1290 if (rval != QLA_SUCCESS)
1291 goto qla25xx_fw_dump_failed_0;
1292
1293 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
c5722708 1294 &nxt);
c81d04c9
AV		 1295 if (rval != QLA_SUCCESS)
1296 goto qla25xx_fw_dump_failed_0;
1297
73208dfd 1298 nxt = qla2xxx_copy_queues(ha, nxt);
c81d04c9 1299
bb99de67 1300 nxt = qla24xx_copy_eft(ha, nxt);
df613b96 1301
d63ab533
AV		 1302 /* Chain entries -- started with MQ. */
1303 qla25xx_copy_fce(ha, nxt_chain, &last_chain);
bb99de67
AV		 1304 if (last_chain) {
1305 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1306 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1307 }
df613b96 1308
c81d04c9 1309qla25xx_fw_dump_failed_0:
c3a2f0df
AV		 1310 if (rval != QLA_SUCCESS) {
1311 qla_printk(KERN_WARNING, ha,
1312 "Failed to dump firmware (%x)!!!\n", rval);
1313 ha->fw_dumped = 0;
6d9b61ed
AV		 1314
1315 } else {
1316 qla_printk(KERN_INFO, ha,
1317 "Firmware dump saved to temp buffer (%ld/%p).\n",
73208dfd 1318 base_vha->host_no, ha->fw_dump);
6d9b61ed
AV		 1319 ha->fw_dumped = 1;
1320 }
1321
c3a2f0df 1322qla25xx_fw_dump_failed:
6d9b61ed
AV		 1323 if (!hardware_locked)
1324 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1325}
3a03eb79
AV		 1326
1327void
1328qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1329{
1330 int rval;
1331 uint32_t cnt;
1332 uint32_t risc_address;
1333 struct qla_hw_data *ha = vha->hw;
1334 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1335 uint32_t __iomem *dmp_reg;
1336 uint32_t *iter_reg;
1337 uint16_t __iomem *mbx_reg;
1338 unsigned long flags;
1339 struct qla81xx_fw_dump *fw;
1340 uint32_t ext_mem_cnt;
1341 void *nxt, *nxt_chain;
1342 uint32_t *last_chain = NULL;
1343 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1344
1345 risc_address = ext_mem_cnt = 0;
1346 flags = 0;
1347
1348 if (!hardware_locked)
1349 spin_lock_irqsave(&ha->hardware_lock, flags);
1350
1351 if (!ha->fw_dump) {
1352 qla_printk(KERN_WARNING, ha,
1353 "No buffer available for dump!!!\n");
1354 goto qla81xx_fw_dump_failed;
1355 }
1356
1357 if (ha->fw_dumped) {
1358 qla_printk(KERN_WARNING, ha,
1359 "Firmware has been previously dumped (%p) -- ignoring "
1360 "request...\n", ha->fw_dump);
1361 goto qla81xx_fw_dump_failed;
1362 }
1363 fw = &ha->fw_dump->isp.isp81;
1364 qla2xxx_prep_dump(ha, ha->fw_dump);
1365
1366 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
1367
1368 /* Pause RISC. */
1369 rval = qla24xx_pause_risc(reg);
1370 if (rval != QLA_SUCCESS)
1371 goto qla81xx_fw_dump_failed_0;
1372
1373 /* Host/Risc registers. */
1374 iter_reg = fw->host_risc_reg;
1375 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1376 qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1377
1378 /* PCIe registers. */
1379 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1380 RD_REG_DWORD(&reg->iobase_addr);
1381 WRT_REG_DWORD(&reg->iobase_window, 0x01);
1382 dmp_reg = &reg->iobase_c4;
1383 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1384 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1385 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1386 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
1387
1388 WRT_REG_DWORD(&reg->iobase_window, 0x00);
1389 RD_REG_DWORD(&reg->iobase_window);
1390
1391 /* Host interface registers. */
1392 dmp_reg = &reg->flash_addr;
1393 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1394 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1395
1396 /* Disable interrupts. */
1397 WRT_REG_DWORD(&reg->ictrl, 0);
1398 RD_REG_DWORD(&reg->ictrl);
1399
1400 /* Shadow registers. */
1401 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1402 RD_REG_DWORD(&reg->iobase_addr);
1403 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1404 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1405
1406 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1407 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1408
1409 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1410 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1411
1412 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1413 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1414
1415 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1416 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1417
1418 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1419 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1420
1421 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1422 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1423
1424 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1425 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1426
1427 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1428 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1429
1430 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1431 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1432
1433 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1434 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1435
1436 /* RISC I/O register. */
1437 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1438 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1439
1440 /* Mailbox registers. */
1441 mbx_reg = &reg->mailbox0;
1442 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1443 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1444
1445 /* Transfer sequence registers. */
1446 iter_reg = fw->xseq_gp_reg;
1447 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1448 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1449 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1450 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1451 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1452 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1453 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1454 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1455
1456 iter_reg = fw->xseq_0_reg;
1457 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1458 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1459 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1460
1461 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1462
1463 /* Receive sequence registers. */
1464 iter_reg = fw->rseq_gp_reg;
1465 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1466 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1467 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1468 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1469 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1470 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1471 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1472 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1473
1474 iter_reg = fw->rseq_0_reg;
1475 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1476 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1477
1478 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1479 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1480
1481 /* Auxiliary sequence registers. */
1482 iter_reg = fw->aseq_gp_reg;
1483 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1484 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1485 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1486 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1487 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1488 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1489 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1490 qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1491
1492 iter_reg = fw->aseq_0_reg;
1493 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1494 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1495
1496 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1497 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1498
1499 /* Command DMA registers. */
1500 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1501
1502 /* Queues. */
1503 iter_reg = fw->req0_dma_reg;
1504 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1505 dmp_reg = &reg->iobase_q;
1506 for (cnt = 0; cnt < 7; cnt++)
1507 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1508
1509 iter_reg = fw->resp0_dma_reg;
1510 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1511 dmp_reg = &reg->iobase_q;
1512 for (cnt = 0; cnt < 7; cnt++)
1513 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1514
1515 iter_reg = fw->req1_dma_reg;
1516 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1517 dmp_reg = &reg->iobase_q;
1518 for (cnt = 0; cnt < 7; cnt++)
1519 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1520
1521 /* Transmit DMA registers. */
1522 iter_reg = fw->xmt0_dma_reg;
1523 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1524 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1525
1526 iter_reg = fw->xmt1_dma_reg;
1527 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1528 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1529
1530 iter_reg = fw->xmt2_dma_reg;
1531 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1532 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1533
1534 iter_reg = fw->xmt3_dma_reg;
1535 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1536 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1537
1538 iter_reg = fw->xmt4_dma_reg;
1539 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1540 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1541
1542 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1543
1544 /* Receive DMA registers. */
1545 iter_reg = fw->rcvt0_data_dma_reg;
1546 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1547 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1548
1549 iter_reg = fw->rcvt1_data_dma_reg;
1550 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1551 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1552
1553 /* RISC registers. */
1554 iter_reg = fw->risc_gp_reg;
1555 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1556 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1557 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1558 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1559 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1560 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1561 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1562 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1563
1564 /* Local memory controller registers. */
1565 iter_reg = fw->lmc_reg;
1566 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1567 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1568 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1569 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1570 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1571 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1572 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1573 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1574
1575 /* Fibre Protocol Module registers. */
1576 iter_reg = fw->fpm_hdw_reg;
1577 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1578 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1579 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1580 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1581 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1582 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1583 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1584 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1585 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1586 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1587 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1588 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1589 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
1590 qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
1591
1592 /* Frame Buffer registers. */
1593 iter_reg = fw->fb_hdw_reg;
1594 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1595 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1596 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1597 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1598 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1599 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1600 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1601 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1602 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1603 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1604 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1605 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
1606 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1607
1608 /* Multi queue registers */
1609 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
1610 &last_chain);
1611
1612 rval = qla24xx_soft_reset(ha);
1613 if (rval != QLA_SUCCESS)
1614 goto qla81xx_fw_dump_failed_0;
1615
1616 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1617 &nxt);
1618 if (rval != QLA_SUCCESS)
1619 goto qla81xx_fw_dump_failed_0;
1620
1621 nxt = qla2xxx_copy_queues(ha, nxt);
1622
1623 nxt = qla24xx_copy_eft(ha, nxt);
1624
1625 /* Chain entries -- started with MQ. */
1626 qla25xx_copy_fce(ha, nxt_chain, &last_chain);
1627 if (last_chain) {
1628 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1629 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1630 }
1631
1632qla81xx_fw_dump_failed_0:
1633 if (rval != QLA_SUCCESS) {
1634 qla_printk(KERN_WARNING, ha,
1635 "Failed to dump firmware (%x)!!!\n", rval);
1636 ha->fw_dumped = 0;
1637
1638 } else {
1639 qla_printk(KERN_INFO, ha,
1640 "Firmware dump saved to temp buffer (%ld/%p).\n",
1641 base_vha->host_no, ha->fw_dump);
1642 ha->fw_dumped = 1;
1643 }
1644
1645qla81xx_fw_dump_failed:
1646 if (!hardware_locked)
1647 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1648}
1649
1da177e4
LT		 1650/****************************************************************************/
1651/* Driver Debug Functions. */
1652/****************************************************************************/
1653
fa2a1ce5 1654void
7b867cf7 1655qla2x00_dump_regs(scsi_qla_host_t *vha)
1da177e4 1656{
6afd9763 1657 int i;
7b867cf7 1658 struct qla_hw_data *ha = vha->hw;
3d71644c 1659 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
6afd9763
AV		 1660 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
1661 uint16_t __iomem *mbx_reg;
1662
1663 mbx_reg = IS_FWI2_CAPABLE(ha) ? &reg24->mailbox0:
1664 MAILBOX_REG(ha, reg, 0);
1da177e4
LT		 1665
1666 printk("Mailbox registers:\n");
6afd9763 1667 for (i = 0; i < 6; i++)
7b867cf7 1668 printk("scsi(%ld): mbox %d 0x%04x \n", vha->host_no, i,
6afd9763 1669 RD_REG_WORD(mbx_reg++));
1da177e4
LT		 1670}
1671
1672
1673void
fa2a1ce5 1674qla2x00_dump_buffer(uint8_t * b, uint32_t size)
1da177e4
LT		 1675{
1676 uint32_t cnt;
1677 uint8_t c;
1678
1679 printk(" 0 1 2 3 4 5 6 7 8 9 "
1680 "Ah Bh Ch Dh Eh Fh\n");
1681 printk("----------------------------------------"
1682 "----------------------\n");
1683
1684 for (cnt = 0; cnt < size;) {
1685 c = *b++;
1686 printk("%02x",(uint32_t) c);
1687 cnt++;
1688 if (!(cnt % 16))
1689 printk("\n");
1690 else
1691 printk(" ");
1692 }
1693 if (cnt % 16)
1694 printk("\n");
1695}
73208dfd
AC		 1696
1697
Linux kernel - Deliverables
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