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[SCSI] qla2xxx: Set default critical temperature value in cases when ISPFX00 firmware...
[deliverable/linux.git] / drivers / scsi / qla2xxx / qla_dbg.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
1e63395c 3 * Copyright (c) 2003-2013 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4 6 */
3ce8866c
SK		 7
8/*
9 * Table for showing the current message id in use for particular level
10 * Change this table for addition of log/debug messages.
e02587d7
AE		 11 * ----------------------------------------------------------------------
12 * | Level | Last Value Used | Holes |
13 * ----------------------------------------------------------------------
71e56003 14 * | Module Init and Probe | 0x0152 | 0x4b,0xba,0xfa |
c46e65c7 15 * | Mailbox commands | 0x1181 | 0x111a-0x111b |
e9f4f418 16 * | | | 0x1155-0x1158 |
1ae47cf3
JC		 17 * | | | 0x1018-0x1019 |
18 * | | | 0x10ca |
8ae6d9c7 19 * | Device Discovery | 0x2095 | 0x2020-0x2022, |
6593d5bd 20 * | | | 0x2011-0x2012, |
2a8593f8 21 * | | | 0x2016 |
8ae6d9c7 22 * | Queue Command and IO tracing | 0x3058 | 0x3006-0x300b |
9e522cd8 23 * | | | 0x3027-0x3028 |
8ae6d9c7
GM		 24 * | | | 0x303d-0x3041 |
25 * | | | 0x302d,0x3033 |
26 * | | | 0x3036,0x3038 |
27 * | | | 0x303a |
28 * | DPC Thread | 0x4022 | 0x4002,0x4013 |
4881d095 29 * | Async Events | 0x5086 | 0x502b-0x502f |
9ba56b95 30 * | | | 0x5047,0x5052 |
8ae6d9c7 31 * | | | 0x5040,0x5075 |
a78951b2 32 * | | | 0x503d,0x5044 |
71e56003 33 * | Timer Routines | 0x6012 | |
8ae6d9c7 34 * | User Space Interactions | 0x70dd | 0x7018,0x702e, |
78d56df6 35 * | | | 0x7020,0x7024, |
733a95bd
JC		 36 * | | | 0x7039,0x7045, |
37 * | | | 0x7073-0x7075, |
8ae6d9c7 38 * | | | 0x707b,0x708c, |
a9b6f722
SK		 39 * | | | 0x70a5,0x70a6, |
40 * | | | 0x70a8,0x70ab, |
8ae6d9c7 41 * | | | 0x70ad-0x70ae, |
1ae47cf3 42 * | | | 0x70d1-0x70db, |
a44c72f3 43 * | | | 0x7047,0x703b |
5854771e 44 * | Task Management | 0x803d | 0x8025-0x8026 |
cfb0919c 45 * | | | 0x800b,0x8039 |
5f28d2d7 46 * | AER/EEH | 0x9011 | |
e02587d7 47 * | Virtual Port | 0xa007 | |
7ec0effd
AD		 48 * | ISP82XX Specific | 0xb14c | 0xb002,0xb024 |
49 * | | | 0xb09e,0xb0ae |
50 * | | | 0xb0e0-0xb0ef |
51 * | | | 0xb085,0xb0dc |
52 * | | | 0xb107,0xb108 |
53 * | | | 0xb111,0xb11e |
54 * | | | 0xb12c,0xb12d |
55 * | | | 0xb13a,0xb142 |
56 * | | | 0xb13c-0xb140 |
6246b8a1
GM		 57 * | MultiQ | 0xc00c | |
58 * | Misc | 0xd010 | |
33c36c0a 59 * | Target Mode | 0xe070 | |
aa230bc5 60 * | Target Mode Management | 0xf072 | |
2d70c103 61 * | Target Mode Task Management | 0x1000b | |
e02587d7 62 * ----------------------------------------------------------------------
3ce8866c
SK		 63 */
64
1da177e4
LT		 65#include "qla_def.h"
66
67#include <linux/delay.h>
68
3ce8866c
SK		 69static uint32_t ql_dbg_offset = 0x800;
70
a7a167bf 71static inline void
7b867cf7 72qla2xxx_prep_dump(struct qla_hw_data *ha, struct qla2xxx_fw_dump *fw_dump)
a7a167bf
AV		 73{
74 fw_dump->fw_major_version = htonl(ha->fw_major_version);
75 fw_dump->fw_minor_version = htonl(ha->fw_minor_version);
76 fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version);
77 fw_dump->fw_attributes = htonl(ha->fw_attributes);
78
79 fw_dump->vendor = htonl(ha->pdev->vendor);
80 fw_dump->device = htonl(ha->pdev->device);
81 fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor);
82 fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device);
83}
84
85static inline void *
73208dfd 86qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr)
a7a167bf 87{
73208dfd
AC		 88 struct req_que *req = ha->req_q_map[0];
89 struct rsp_que *rsp = ha->rsp_q_map[0];
a7a167bf 90 /* Request queue. */
7b867cf7 91 memcpy(ptr, req->ring, req->length *
a7a167bf
AV		 92 sizeof(request_t));
93
94 /* Response queue. */
7b867cf7
AC		 95 ptr += req->length * sizeof(request_t);
96 memcpy(ptr, rsp->ring, rsp->length *
a7a167bf
AV		 97 sizeof(response_t));
98
7b867cf7 99 return ptr + (rsp->length * sizeof(response_t));
a7a167bf 100}
1da177e4 101
c3a2f0df 102static int
7b867cf7 103qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram,
c5722708 104 uint32_t ram_dwords, void **nxt)
c3a2f0df
AV		 105{
106 int rval;
c5722708
AV		 107 uint32_t cnt, stat, timer, dwords, idx;
108 uint16_t mb0;
c3a2f0df 109 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
c5722708
AV		 110 dma_addr_t dump_dma = ha->gid_list_dma;
111 uint32_t *dump = (uint32_t *)ha->gid_list;
c3a2f0df
AV		 112
113 rval = QLA_SUCCESS;
c5722708 114 mb0 = 0;
c3a2f0df 115
c5722708 116 WRT_REG_WORD(&reg->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
c3a2f0df
AV		 117 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
118
642ef983 119 dwords = qla2x00_gid_list_size(ha) / 4;
c5722708
AV		 120 for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
121 cnt += dwords, addr += dwords) {
122 if (cnt + dwords > ram_dwords)
123 dwords = ram_dwords - cnt;
c3a2f0df 124
c5722708
AV		 125 WRT_REG_WORD(&reg->mailbox1, LSW(addr));
126 WRT_REG_WORD(&reg->mailbox8, MSW(addr));
c3a2f0df 127
c5722708
AV		 128 WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
129 WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
130 WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
131 WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
c3a2f0df 132
c5722708
AV		 133 WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
134 WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
c3a2f0df
AV		 135 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
136
137 for (timer = 6000000; timer; timer--) {
138 /* Check for pending interrupts. */
139 stat = RD_REG_DWORD(&reg->host_status);
140 if (stat & HSRX_RISC_INT) {
141 stat &= 0xff;
142
143 if (stat == 0x1 || stat == 0x2 ||
144 stat == 0x10 || stat == 0x11) {
145 set_bit(MBX_INTERRUPT,
146 &ha->mbx_cmd_flags);
147
c5722708 148 mb0 = RD_REG_WORD(&reg->mailbox0);
c3a2f0df
AV		 149
150 WRT_REG_DWORD(&reg->hccr,
151 HCCRX_CLR_RISC_INT);
152 RD_REG_DWORD(&reg->hccr);
153 break;
154 }
155
156 /* Clear this intr; it wasn't a mailbox intr */
157 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
158 RD_REG_DWORD(&reg->hccr);
159 }
160 udelay(5);
161 }
162
163 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
c5722708
AV		 164 rval = mb0 & MBS_MASK;
165 for (idx = 0; idx < dwords; idx++)
166 ram[cnt + idx] = swab32(dump[idx]);
c3a2f0df
AV		 167 } else {
168 rval = QLA_FUNCTION_FAILED;
169 }
170 }
171
c5722708 172 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
c3a2f0df
AV		 173 return rval;
174}
175
c5722708 176static int
7b867cf7 177qla24xx_dump_memory(struct qla_hw_data *ha, uint32_t *code_ram,
c5722708
AV		 178 uint32_t cram_size, void **nxt)
179{
180 int rval;
181
182 /* Code RAM. */
183 rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt);
184 if (rval != QLA_SUCCESS)
185 return rval;
186
187 /* External Memory. */
188 return qla24xx_dump_ram(ha, 0x100000, *nxt,
189 ha->fw_memory_size - 0x100000 + 1, nxt);
190}
191
c81d04c9
AV		 192static uint32_t *
193qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
194 uint32_t count, uint32_t *buf)
195{
196 uint32_t __iomem *dmp_reg;
197
198 WRT_REG_DWORD(&reg->iobase_addr, iobase);
199 dmp_reg = &reg->iobase_window;
200 while (count--)
201 *buf++ = htonl(RD_REG_DWORD(dmp_reg++));
202
203 return buf;
204}
205
206static inline int
207qla24xx_pause_risc(struct device_reg_24xx __iomem *reg)
208{
209 int rval = QLA_SUCCESS;
210 uint32_t cnt;
211
c3b058af 212 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
aed10881
AV		 213 for (cnt = 30000;
214 ((RD_REG_DWORD(&reg->host_status) & HSRX_RISC_PAUSED) == 0) &&
c3b058af
AV		 215 rval == QLA_SUCCESS; cnt--) {
216 if (cnt)
217 udelay(100);
218 else
219 rval = QLA_FUNCTION_TIMEOUT;
c81d04c9
AV		 220 }
221
222 return rval;
223}
224
225static int
7b867cf7 226qla24xx_soft_reset(struct qla_hw_data *ha)
c81d04c9
AV		 227{
228 int rval = QLA_SUCCESS;
229 uint32_t cnt;
230 uint16_t mb0, wd;
231 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
232
233 /* Reset RISC. */
234 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
235 for (cnt = 0; cnt < 30000; cnt++) {
236 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
237 break;
238
239 udelay(10);
240 }
241
242 WRT_REG_DWORD(&reg->ctrl_status,
243 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
244 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
245
246 udelay(100);
247 /* Wait for firmware to complete NVRAM accesses. */
248 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
249 for (cnt = 10000 ; cnt && mb0; cnt--) {
250 udelay(5);
251 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
252 barrier();
253 }
254
255 /* Wait for soft-reset to complete. */
256 for (cnt = 0; cnt < 30000; cnt++) {
257 if ((RD_REG_DWORD(&reg->ctrl_status) &
258 CSRX_ISP_SOFT_RESET) == 0)
259 break;
260
261 udelay(10);
262 }
263 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
264 RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
265
266 for (cnt = 30000; RD_REG_WORD(&reg->mailbox0) != 0 &&
267 rval == QLA_SUCCESS; cnt--) {
268 if (cnt)
269 udelay(100);
270 else
271 rval = QLA_FUNCTION_TIMEOUT;
272 }
273
274 return rval;
275}
276
c5722708 277static int
7b867cf7 278qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint16_t *ram,
e18e963b 279 uint32_t ram_words, void **nxt)
c5722708
AV		 280{
281 int rval;
282 uint32_t cnt, stat, timer, words, idx;
283 uint16_t mb0;
284 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
285 dma_addr_t dump_dma = ha->gid_list_dma;
286 uint16_t *dump = (uint16_t *)ha->gid_list;
287
288 rval = QLA_SUCCESS;
289 mb0 = 0;
290
291 WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED);
292 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
293
642ef983 294 words = qla2x00_gid_list_size(ha) / 2;
c5722708
AV		 295 for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS;
296 cnt += words, addr += words) {
297 if (cnt + words > ram_words)
298 words = ram_words - cnt;
299
300 WRT_MAILBOX_REG(ha, reg, 1, LSW(addr));
301 WRT_MAILBOX_REG(ha, reg, 8, MSW(addr));
302
303 WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma));
304 WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma));
305 WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma)));
306 WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma)));
307
308 WRT_MAILBOX_REG(ha, reg, 4, words);
309 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
310
311 for (timer = 6000000; timer; timer--) {
312 /* Check for pending interrupts. */
313 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
314 if (stat & HSR_RISC_INT) {
315 stat &= 0xff;
316
317 if (stat == 0x1 || stat == 0x2) {
318 set_bit(MBX_INTERRUPT,
319 &ha->mbx_cmd_flags);
320
321 mb0 = RD_MAILBOX_REG(ha, reg, 0);
322
323 /* Release mailbox registers. */
324 WRT_REG_WORD(&reg->semaphore, 0);
325 WRT_REG_WORD(&reg->hccr,
326 HCCR_CLR_RISC_INT);
327 RD_REG_WORD(&reg->hccr);
328 break;
329 } else if (stat == 0x10 || stat == 0x11) {
330 set_bit(MBX_INTERRUPT,
331 &ha->mbx_cmd_flags);
332
333 mb0 = RD_MAILBOX_REG(ha, reg, 0);
334
335 WRT_REG_WORD(&reg->hccr,
336 HCCR_CLR_RISC_INT);
337 RD_REG_WORD(&reg->hccr);
338 break;
339 }
340
341 /* clear this intr; it wasn't a mailbox intr */
342 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
343 RD_REG_WORD(&reg->hccr);
344 }
345 udelay(5);
346 }
347
348 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
349 rval = mb0 & MBS_MASK;
350 for (idx = 0; idx < words; idx++)
351 ram[cnt + idx] = swab16(dump[idx]);
352 } else {
353 rval = QLA_FUNCTION_FAILED;
354 }
355 }
356
357 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
358 return rval;
359}
360
c81d04c9
AV		 361static inline void
362qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
363 uint16_t *buf)
364{
365 uint16_t __iomem *dmp_reg = &reg->u.isp2300.fb_cmd;
366
367 while (count--)
368 *buf++ = htons(RD_REG_WORD(dmp_reg++));
369}
370
bb99de67
AV		 371static inline void *
372qla24xx_copy_eft(struct qla_hw_data *ha, void *ptr)
373{
374 if (!ha->eft)
375 return ptr;
376
377 memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size));
378 return ptr + ntohl(ha->fw_dump->eft_size);
379}
380
381static inline void *
382qla25xx_copy_fce(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
383{
384 uint32_t cnt;
385 uint32_t *iter_reg;
386 struct qla2xxx_fce_chain *fcec = ptr;
387
388 if (!ha->fce)
389 return ptr;
390
391 *last_chain = &fcec->type;
392 fcec->type = __constant_htonl(DUMP_CHAIN_FCE);
393 fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) +
394 fce_calc_size(ha->fce_bufs));
395 fcec->size = htonl(fce_calc_size(ha->fce_bufs));
396 fcec->addr_l = htonl(LSD(ha->fce_dma));
397 fcec->addr_h = htonl(MSD(ha->fce_dma));
398
399 iter_reg = fcec->eregs;
400 for (cnt = 0; cnt < 8; cnt++)
401 *iter_reg++ = htonl(ha->fce_mb[cnt]);
402
403 memcpy(iter_reg, ha->fce, ntohl(fcec->size));
404
3cb0a67d 405 return (char *)iter_reg + ntohl(fcec->size);
bb99de67
AV		 406}
407
2d70c103
NB		 408static inline void *
409qla2xxx_copy_atioqueues(struct qla_hw_data *ha, void *ptr,
410 uint32_t **last_chain)
411{
412 struct qla2xxx_mqueue_chain *q;
413 struct qla2xxx_mqueue_header *qh;
414 uint32_t num_queues;
415 int que;
416 struct {
417 int length;
418 void *ring;
419 } aq, *aqp;
420
00876ae8 421 if (!ha->tgt.atio_ring)
2d70c103
NB		 422 return ptr;
423
424 num_queues = 1;
425 aqp = &aq;
426 aqp->length = ha->tgt.atio_q_length;
427 aqp->ring = ha->tgt.atio_ring;
428
429 for (que = 0; que < num_queues; que++) {
430 /* aqp = ha->atio_q_map[que]; */
431 q = ptr;
432 *last_chain = &q->type;
433 q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
434 q->chain_size = htonl(
435 sizeof(struct qla2xxx_mqueue_chain) +
436 sizeof(struct qla2xxx_mqueue_header) +
437 (aqp->length * sizeof(request_t)));
438 ptr += sizeof(struct qla2xxx_mqueue_chain);
439
440 /* Add header. */
441 qh = ptr;
442 qh->queue = __constant_htonl(TYPE_ATIO_QUEUE);
443 qh->number = htonl(que);
444 qh->size = htonl(aqp->length * sizeof(request_t));
445 ptr += sizeof(struct qla2xxx_mqueue_header);
446
447 /* Add data. */
448 memcpy(ptr, aqp->ring, aqp->length * sizeof(request_t));
449
450 ptr += aqp->length * sizeof(request_t);
451 }
452
453 return ptr;
454}
455
050c9bb1
GM		 456static inline void *
457qla25xx_copy_mqueues(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
458{
459 struct qla2xxx_mqueue_chain *q;
460 struct qla2xxx_mqueue_header *qh;
461 struct req_que *req;
462 struct rsp_que *rsp;
463 int que;
464
465 if (!ha->mqenable)
466 return ptr;
467
468 /* Request queues */
469 for (que = 1; que < ha->max_req_queues; que++) {
470 req = ha->req_q_map[que];
471 if (!req)
472 break;
473
474 /* Add chain. */
475 q = ptr;
476 *last_chain = &q->type;
477 q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
478 q->chain_size = htonl(
479 sizeof(struct qla2xxx_mqueue_chain) +
480 sizeof(struct qla2xxx_mqueue_header) +
481 (req->length * sizeof(request_t)));
482 ptr += sizeof(struct qla2xxx_mqueue_chain);
483
484 /* Add header. */
485 qh = ptr;
486 qh->queue = __constant_htonl(TYPE_REQUEST_QUEUE);
487 qh->number = htonl(que);
488 qh->size = htonl(req->length * sizeof(request_t));
489 ptr += sizeof(struct qla2xxx_mqueue_header);
490
491 /* Add data. */
492 memcpy(ptr, req->ring, req->length * sizeof(request_t));
493 ptr += req->length * sizeof(request_t);
494 }
495
496 /* Response queues */
497 for (que = 1; que < ha->max_rsp_queues; que++) {
498 rsp = ha->rsp_q_map[que];
499 if (!rsp)
500 break;
501
502 /* Add chain. */
503 q = ptr;
504 *last_chain = &q->type;
505 q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
506 q->chain_size = htonl(
507 sizeof(struct qla2xxx_mqueue_chain) +
508 sizeof(struct qla2xxx_mqueue_header) +
509 (rsp->length * sizeof(response_t)));
510 ptr += sizeof(struct qla2xxx_mqueue_chain);
511
512 /* Add header. */
513 qh = ptr;
514 qh->queue = __constant_htonl(TYPE_RESPONSE_QUEUE);
515 qh->number = htonl(que);
516 qh->size = htonl(rsp->length * sizeof(response_t));
517 ptr += sizeof(struct qla2xxx_mqueue_header);
518
519 /* Add data. */
520 memcpy(ptr, rsp->ring, rsp->length * sizeof(response_t));
521 ptr += rsp->length * sizeof(response_t);
522 }
523
524 return ptr;
525}
526
d63ab533
AV		 527static inline void *
528qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
529{
530 uint32_t cnt, que_idx;
2afa19a9 531 uint8_t que_cnt;
d63ab533 532 struct qla2xxx_mq_chain *mq = ptr;
da9b1d5c 533 device_reg_t __iomem *reg;
d63ab533 534
6246b8a1 535 if (!ha->mqenable || IS_QLA83XX(ha))
d63ab533
AV		 536 return ptr;
537
538 mq = ptr;
539 *last_chain = &mq->type;
540 mq->type = __constant_htonl(DUMP_CHAIN_MQ);
541 mq->chain_size = __constant_htonl(sizeof(struct qla2xxx_mq_chain));
542
2afa19a9
AC		 543 que_cnt = ha->max_req_queues > ha->max_rsp_queues ?
544 ha->max_req_queues : ha->max_rsp_queues;
d63ab533
AV		 545 mq->count = htonl(que_cnt);
546 for (cnt = 0; cnt < que_cnt; cnt++) {
da9b1d5c 547 reg = ISP_QUE_REG(ha, cnt);
d63ab533 548 que_idx = cnt * 4;
da9b1d5c
AV		 549 mq->qregs[que_idx] =
550 htonl(RD_REG_DWORD(&reg->isp25mq.req_q_in));
551 mq->qregs[que_idx+1] =
552 htonl(RD_REG_DWORD(&reg->isp25mq.req_q_out));
553 mq->qregs[que_idx+2] =
554 htonl(RD_REG_DWORD(&reg->isp25mq.rsp_q_in));
555 mq->qregs[que_idx+3] =
556 htonl(RD_REG_DWORD(&reg->isp25mq.rsp_q_out));
d63ab533
AV		 557 }
558
559 return ptr + sizeof(struct qla2xxx_mq_chain);
560}
561
08de2844 562void
3420d36c
AV		 563qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval)
564{
565 struct qla_hw_data *ha = vha->hw;
566
567 if (rval != QLA_SUCCESS) {
7c3df132
SK		 568 ql_log(ql_log_warn, vha, 0xd000,
569 "Failed to dump firmware (%x).\n", rval);
3420d36c
AV		 570 ha->fw_dumped = 0;
571 } else {
7c3df132 572 ql_log(ql_log_info, vha, 0xd001,
3420d36c
AV		 573 "Firmware dump saved to temp buffer (%ld/%p).\n",
574 vha->host_no, ha->fw_dump);
575 ha->fw_dumped = 1;
576 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
577 }
578}
579
1da177e4
LT		 580/**
581 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
582 * @ha: HA context
583 * @hardware_locked: Called with the hardware_lock
584 */
585void
7b867cf7 586qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1da177e4
LT		 587{
588 int rval;
c5722708 589 uint32_t cnt;
7b867cf7 590 struct qla_hw_data *ha = vha->hw;
3d71644c 591 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 592 uint16_t __iomem *dmp_reg;
593 unsigned long flags;
594 struct qla2300_fw_dump *fw;
c5722708 595 void *nxt;
73208dfd 596 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 597
1da177e4
LT		 598 flags = 0;
599
600 if (!hardware_locked)
601 spin_lock_irqsave(&ha->hardware_lock, flags);
602
d4e3e04d 603 if (!ha->fw_dump) {
7c3df132
SK		 604 ql_log(ql_log_warn, vha, 0xd002,
605 "No buffer available for dump.\n");
1da177e4
LT		 606 goto qla2300_fw_dump_failed;
607 }
608
d4e3e04d 609 if (ha->fw_dumped) {
7c3df132
SK		 610 ql_log(ql_log_warn, vha, 0xd003,
611 "Firmware has been previously dumped (%p) "
612 "-- ignoring request.\n",
613 ha->fw_dump);
1da177e4
LT		 614 goto qla2300_fw_dump_failed;
615 }
a7a167bf
AV		 616 fw = &ha->fw_dump->isp.isp23;
617 qla2xxx_prep_dump(ha, ha->fw_dump);
1da177e4
LT		 618
619 rval = QLA_SUCCESS;
a7a167bf 620 fw->hccr = htons(RD_REG_WORD(&reg->hccr));
1da177e4
LT		 621
622 /* Pause RISC. */
fa2a1ce5 623 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1da177e4
LT		 624 if (IS_QLA2300(ha)) {
625 for (cnt = 30000;
626 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
627 rval == QLA_SUCCESS; cnt--) {
628 if (cnt)
629 udelay(100);
630 else
631 rval = QLA_FUNCTION_TIMEOUT;
632 }
633 } else {
634 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
635 udelay(10);
636 }
637
638 if (rval == QLA_SUCCESS) {
c81d04c9 639 dmp_reg = &reg->flash_address;
fa2a1ce5 640 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
a7a167bf 641 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 642
c81d04c9 643 dmp_reg = &reg->u.isp2300.req_q_in;
fa2a1ce5 644 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
a7a167bf 645 fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 646
c81d04c9 647 dmp_reg = &reg->u.isp2300.mailbox0;
fa2a1ce5 648 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
a7a167bf 649 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4
LT		 650
651 WRT_REG_WORD(&reg->ctrl_status, 0x40);
c81d04c9 652 qla2xxx_read_window(reg, 32, fw->resp_dma_reg);
1da177e4
LT		 653
654 WRT_REG_WORD(&reg->ctrl_status, 0x50);
c81d04c9 655 qla2xxx_read_window(reg, 48, fw->dma_reg);
1da177e4
LT		 656
657 WRT_REG_WORD(&reg->ctrl_status, 0x00);
c81d04c9 658 dmp_reg = &reg->risc_hw;
fa2a1ce5 659 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
a7a167bf 660 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 661
fa2a1ce5 662 WRT_REG_WORD(&reg->pcr, 0x2000);
c81d04c9 663 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
1da177e4 664
fa2a1ce5 665 WRT_REG_WORD(&reg->pcr, 0x2200);
c81d04c9 666 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
1da177e4 667
fa2a1ce5 668 WRT_REG_WORD(&reg->pcr, 0x2400);
c81d04c9 669 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
1da177e4 670
fa2a1ce5 671 WRT_REG_WORD(&reg->pcr, 0x2600);
c81d04c9 672 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
1da177e4 673
fa2a1ce5 674 WRT_REG_WORD(&reg->pcr, 0x2800);
c81d04c9 675 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
1da177e4 676
fa2a1ce5 677 WRT_REG_WORD(&reg->pcr, 0x2A00);
c81d04c9 678 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
1da177e4 679
fa2a1ce5 680 WRT_REG_WORD(&reg->pcr, 0x2C00);
c81d04c9 681 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
1da177e4 682
fa2a1ce5 683 WRT_REG_WORD(&reg->pcr, 0x2E00);
c81d04c9 684 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
1da177e4 685
fa2a1ce5 686 WRT_REG_WORD(&reg->ctrl_status, 0x10);
c81d04c9 687 qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg);
1da177e4 688
fa2a1ce5 689 WRT_REG_WORD(&reg->ctrl_status, 0x20);
c81d04c9 690 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
1da177e4 691
fa2a1ce5 692 WRT_REG_WORD(&reg->ctrl_status, 0x30);
c81d04c9 693 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
1da177e4
LT		 694
695 /* Reset RISC. */
696 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
697 for (cnt = 0; cnt < 30000; cnt++) {
698 if ((RD_REG_WORD(&reg->ctrl_status) &
699 CSR_ISP_SOFT_RESET) == 0)
700 break;
701
702 udelay(10);
703 }
704 }
705
706 if (!IS_QLA2300(ha)) {
707 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
708 rval == QLA_SUCCESS; cnt--) {
709 if (cnt)
710 udelay(100);
711 else
712 rval = QLA_FUNCTION_TIMEOUT;
713 }
714 }
715
c5722708
AV		 716 /* Get RISC SRAM. */
717 if (rval == QLA_SUCCESS)
718 rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram,
719 sizeof(fw->risc_ram) / 2, &nxt);
1da177e4 720
c5722708
AV		 721 /* Get stack SRAM. */
722 if (rval == QLA_SUCCESS)
723 rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram,
724 sizeof(fw->stack_ram) / 2, &nxt);
1da177e4 725
c5722708
AV		 726 /* Get data SRAM. */
727 if (rval == QLA_SUCCESS)
728 rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram,
729 ha->fw_memory_size - 0x11000 + 1, &nxt);
1da177e4 730
a7a167bf 731 if (rval == QLA_SUCCESS)
73208dfd 732 qla2xxx_copy_queues(ha, nxt);
a7a167bf 733
3420d36c 734 qla2xxx_dump_post_process(base_vha, rval);
1da177e4
LT		 735
736qla2300_fw_dump_failed:
737 if (!hardware_locked)
738 spin_unlock_irqrestore(&ha->hardware_lock, flags);
739}
740
1da177e4
LT		 741/**
742 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
743 * @ha: HA context
744 * @hardware_locked: Called with the hardware_lock
745 */
746void
7b867cf7 747qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1da177e4
LT		 748{
749 int rval;
750 uint32_t cnt, timer;
751 uint16_t risc_address;
752 uint16_t mb0, mb2;
7b867cf7 753 struct qla_hw_data *ha = vha->hw;
3d71644c 754 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 755 uint16_t __iomem *dmp_reg;
756 unsigned long flags;
757 struct qla2100_fw_dump *fw;
73208dfd 758 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 759
760 risc_address = 0;
761 mb0 = mb2 = 0;
762 flags = 0;
763
764 if (!hardware_locked)
765 spin_lock_irqsave(&ha->hardware_lock, flags);
766
d4e3e04d 767 if (!ha->fw_dump) {
7c3df132
SK		 768 ql_log(ql_log_warn, vha, 0xd004,
769 "No buffer available for dump.\n");
1da177e4
LT		 770 goto qla2100_fw_dump_failed;
771 }
772
d4e3e04d 773 if (ha->fw_dumped) {
7c3df132
SK		 774 ql_log(ql_log_warn, vha, 0xd005,
775 "Firmware has been previously dumped (%p) "
776 "-- ignoring request.\n",
777 ha->fw_dump);
1da177e4
LT		 778 goto qla2100_fw_dump_failed;
779 }
a7a167bf
AV		 780 fw = &ha->fw_dump->isp.isp21;
781 qla2xxx_prep_dump(ha, ha->fw_dump);
1da177e4
LT		 782
783 rval = QLA_SUCCESS;
a7a167bf 784 fw->hccr = htons(RD_REG_WORD(&reg->hccr));
1da177e4
LT		 785
786 /* Pause RISC. */
fa2a1ce5 787 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1da177e4
LT		 788 for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
789 rval == QLA_SUCCESS; cnt--) {
790 if (cnt)
791 udelay(100);
792 else
793 rval = QLA_FUNCTION_TIMEOUT;
794 }
795 if (rval == QLA_SUCCESS) {
c81d04c9 796 dmp_reg = &reg->flash_address;
fa2a1ce5 797 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
a7a167bf 798 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 799
c81d04c9 800 dmp_reg = &reg->u.isp2100.mailbox0;
1da177e4 801 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
c81d04c9
AV		 802 if (cnt == 8)
803 dmp_reg = &reg->u_end.isp2200.mailbox8;
804
a7a167bf 805 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4
LT		 806 }
807
c81d04c9 808 dmp_reg = &reg->u.isp2100.unused_2[0];
fa2a1ce5 809 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
a7a167bf 810 fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4
LT		 811
812 WRT_REG_WORD(&reg->ctrl_status, 0x00);
c81d04c9 813 dmp_reg = &reg->risc_hw;
fa2a1ce5 814 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
a7a167bf 815 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 816
fa2a1ce5 817 WRT_REG_WORD(&reg->pcr, 0x2000);
c81d04c9 818 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
1da177e4 819
fa2a1ce5 820 WRT_REG_WORD(&reg->pcr, 0x2100);
c81d04c9 821 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
1da177e4 822
fa2a1ce5 823 WRT_REG_WORD(&reg->pcr, 0x2200);
c81d04c9 824 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
1da177e4 825
fa2a1ce5 826 WRT_REG_WORD(&reg->pcr, 0x2300);
c81d04c9 827 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
1da177e4 828
fa2a1ce5 829 WRT_REG_WORD(&reg->pcr, 0x2400);
c81d04c9 830 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
1da177e4 831
fa2a1ce5 832 WRT_REG_WORD(&reg->pcr, 0x2500);
c81d04c9 833 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
1da177e4 834
fa2a1ce5 835 WRT_REG_WORD(&reg->pcr, 0x2600);
c81d04c9 836 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
1da177e4 837
fa2a1ce5 838 WRT_REG_WORD(&reg->pcr, 0x2700);
c81d04c9 839 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
1da177e4 840
fa2a1ce5 841 WRT_REG_WORD(&reg->ctrl_status, 0x10);
c81d04c9 842 qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg);
1da177e4 843
fa2a1ce5 844 WRT_REG_WORD(&reg->ctrl_status, 0x20);
c81d04c9 845 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
1da177e4 846
fa2a1ce5 847 WRT_REG_WORD(&reg->ctrl_status, 0x30);
c81d04c9 848 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
1da177e4
LT		 849
850 /* Reset the ISP. */
851 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
852 }
853
854 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
855 rval == QLA_SUCCESS; cnt--) {
856 if (cnt)
857 udelay(100);
858 else
859 rval = QLA_FUNCTION_TIMEOUT;
860 }
861
862 /* Pause RISC. */
863 if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) &&
864 (RD_REG_WORD(&reg->mctr) & (BIT_1 | BIT_0)) != 0))) {
865
fa2a1ce5 866 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1da177e4
LT		 867 for (cnt = 30000;
868 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
869 rval == QLA_SUCCESS; cnt--) {
870 if (cnt)
871 udelay(100);
872 else
873 rval = QLA_FUNCTION_TIMEOUT;
874 }
875 if (rval == QLA_SUCCESS) {
876 /* Set memory configuration and timing. */
877 if (IS_QLA2100(ha))
878 WRT_REG_WORD(&reg->mctr, 0xf1);
879 else
880 WRT_REG_WORD(&reg->mctr, 0xf2);
881 RD_REG_WORD(&reg->mctr); /* PCI Posting. */
882
883 /* Release RISC. */
884 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
885 }
886 }
887
888 if (rval == QLA_SUCCESS) {
889 /* Get RISC SRAM. */
890 risc_address = 0x1000;
891 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
892 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
893 }
894 for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
895 cnt++, risc_address++) {
896 WRT_MAILBOX_REG(ha, reg, 1, risc_address);
897 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
898
899 for (timer = 6000000; timer != 0; timer--) {
900 /* Check for pending interrupts. */
901 if (RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) {
902 if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
903 set_bit(MBX_INTERRUPT,
904 &ha->mbx_cmd_flags);
905
906 mb0 = RD_MAILBOX_REG(ha, reg, 0);
907 mb2 = RD_MAILBOX_REG(ha, reg, 2);
908
909 WRT_REG_WORD(&reg->semaphore, 0);
910 WRT_REG_WORD(&reg->hccr,
911 HCCR_CLR_RISC_INT);
912 RD_REG_WORD(&reg->hccr);
913 break;
914 }
915 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
916 RD_REG_WORD(&reg->hccr);
917 }
918 udelay(5);
919 }
920
921 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
922 rval = mb0 & MBS_MASK;
a7a167bf 923 fw->risc_ram[cnt] = htons(mb2);
1da177e4
LT		 924 } else {
925 rval = QLA_FUNCTION_FAILED;
926 }
927 }
928
a7a167bf 929 if (rval == QLA_SUCCESS)
73208dfd 930 qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]);
a7a167bf 931
3420d36c 932 qla2xxx_dump_post_process(base_vha, rval);
1da177e4
LT		 933
934qla2100_fw_dump_failed:
935 if (!hardware_locked)
936 spin_unlock_irqrestore(&ha->hardware_lock, flags);
937}
938
6d9b61ed 939void
7b867cf7 940qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
6d9b61ed
AV		 941{
942 int rval;
c3a2f0df 943 uint32_t cnt;
6d9b61ed 944 uint32_t risc_address;
7b867cf7 945 struct qla_hw_data *ha = vha->hw;
6d9b61ed
AV		 946 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
947 uint32_t __iomem *dmp_reg;
948 uint32_t *iter_reg;
949 uint16_t __iomem *mbx_reg;
950 unsigned long flags;
951 struct qla24xx_fw_dump *fw;
952 uint32_t ext_mem_cnt;
c3a2f0df 953 void *nxt;
2d70c103
NB		 954 void *nxt_chain;
955 uint32_t *last_chain = NULL;
73208dfd 956 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
6d9b61ed 957
7ec0effd 958 if (IS_P3P_TYPE(ha))
a9083016
GM		 959 return;
960
6d9b61ed 961 risc_address = ext_mem_cnt = 0;
6d9b61ed
AV		 962 flags = 0;
963
964 if (!hardware_locked)
965 spin_lock_irqsave(&ha->hardware_lock, flags);
966
d4e3e04d 967 if (!ha->fw_dump) {
7c3df132
SK		 968 ql_log(ql_log_warn, vha, 0xd006,
969 "No buffer available for dump.\n");
6d9b61ed
AV		 970 goto qla24xx_fw_dump_failed;
971 }
972
973 if (ha->fw_dumped) {
7c3df132
SK		 974 ql_log(ql_log_warn, vha, 0xd007,
975 "Firmware has been previously dumped (%p) "
976 "-- ignoring request.\n",
977 ha->fw_dump);
6d9b61ed
AV		 978 goto qla24xx_fw_dump_failed;
979 }
a7a167bf
AV		 980 fw = &ha->fw_dump->isp.isp24;
981 qla2xxx_prep_dump(ha, ha->fw_dump);
6d9b61ed 982
a7a167bf 983 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
6d9b61ed
AV		 984
985 /* Pause RISC. */
c81d04c9
AV		 986 rval = qla24xx_pause_risc(reg);
987 if (rval != QLA_SUCCESS)
988 goto qla24xx_fw_dump_failed_0;
989
990 /* Host interface registers. */
991 dmp_reg = &reg->flash_addr;
992 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
993 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
994
995 /* Disable interrupts. */
996 WRT_REG_DWORD(&reg->ictrl, 0);
997 RD_REG_DWORD(&reg->ictrl);
998
999 /* Shadow registers. */
1000 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1001 RD_REG_DWORD(&reg->iobase_addr);
1002 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1003 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1004
1005 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1006 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1007
1008 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1009 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1010
1011 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1012 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1013
1014 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1015 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1016
1017 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1018 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1019
1020 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1021 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1022
1023 /* Mailbox registers. */
1024 mbx_reg = &reg->mailbox0;
1025 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1026 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1027
1028 /* Transfer sequence registers. */
1029 iter_reg = fw->xseq_gp_reg;
1030 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1031 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1032 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1033 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1034 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1035 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1036 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1037 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1038
1039 qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg);
1040 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1041
1042 /* Receive sequence registers. */
1043 iter_reg = fw->rseq_gp_reg;
1044 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1045 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1046 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1047 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1048 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1049 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1050 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1051 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1052
1053 qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg);
1054 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1055 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1056
1057 /* Command DMA registers. */
1058 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1059
1060 /* Queues. */
1061 iter_reg = fw->req0_dma_reg;
1062 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1063 dmp_reg = &reg->iobase_q;
1064 for (cnt = 0; cnt < 7; cnt++)
1065 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1066
1067 iter_reg = fw->resp0_dma_reg;
1068 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1069 dmp_reg = &reg->iobase_q;
1070 for (cnt = 0; cnt < 7; cnt++)
1071 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1072
1073 iter_reg = fw->req1_dma_reg;
1074 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1075 dmp_reg = &reg->iobase_q;
1076 for (cnt = 0; cnt < 7; cnt++)
1077 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1078
1079 /* Transmit DMA registers. */
1080 iter_reg = fw->xmt0_dma_reg;
1081 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1082 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1083
1084 iter_reg = fw->xmt1_dma_reg;
1085 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1086 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1087
1088 iter_reg = fw->xmt2_dma_reg;
1089 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1090 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1091
1092 iter_reg = fw->xmt3_dma_reg;
1093 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1094 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1095
1096 iter_reg = fw->xmt4_dma_reg;
1097 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1098 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1099
1100 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1101
1102 /* Receive DMA registers. */
1103 iter_reg = fw->rcvt0_data_dma_reg;
1104 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1105 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1106
1107 iter_reg = fw->rcvt1_data_dma_reg;
1108 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1109 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1110
1111 /* RISC registers. */
1112 iter_reg = fw->risc_gp_reg;
1113 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1114 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1115 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1116 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1117 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1118 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1119 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1120 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1121
1122 /* Local memory controller registers. */
1123 iter_reg = fw->lmc_reg;
1124 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1125 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1126 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1127 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1128 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1129 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1130 qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1131
1132 /* Fibre Protocol Module registers. */
1133 iter_reg = fw->fpm_hdw_reg;
1134 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1135 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1136 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1137 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1138 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1139 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1140 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1141 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1142 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1143 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1144 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1145 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1146
1147 /* Frame Buffer registers. */
1148 iter_reg = fw->fb_hdw_reg;
1149 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1150 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1151 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1152 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1153 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1154 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1155 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1156 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1157 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1158 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1159 qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1160
1161 rval = qla24xx_soft_reset(ha);
1162 if (rval != QLA_SUCCESS)
1163 goto qla24xx_fw_dump_failed_0;
1164
1165 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
c5722708 1166 &nxt);
c81d04c9
AV		 1167 if (rval != QLA_SUCCESS)
1168 goto qla24xx_fw_dump_failed_0;
1169
73208dfd 1170 nxt = qla2xxx_copy_queues(ha, nxt);
bb99de67
AV		 1171
1172 qla24xx_copy_eft(ha, nxt);
c81d04c9 1173
2d70c103
NB		 1174 nxt_chain = (void *)ha->fw_dump + ha->chain_offset;
1175 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
1176 if (last_chain) {
1177 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1178 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1179 }
1180
1181 /* Adjust valid length. */
1182 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
1183
c81d04c9 1184qla24xx_fw_dump_failed_0:
3420d36c 1185 qla2xxx_dump_post_process(base_vha, rval);
6d9b61ed 1186
c3a2f0df
AV		 1187qla24xx_fw_dump_failed:
1188 if (!hardware_locked)
1189 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1190}
6d9b61ed 1191
c3a2f0df 1192void
7b867cf7 1193qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
c3a2f0df
AV		 1194{
1195 int rval;
1196 uint32_t cnt;
1197 uint32_t risc_address;
7b867cf7 1198 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 1199 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1200 uint32_t __iomem *dmp_reg;
1201 uint32_t *iter_reg;
1202 uint16_t __iomem *mbx_reg;
1203 unsigned long flags;
1204 struct qla25xx_fw_dump *fw;
1205 uint32_t ext_mem_cnt;
d63ab533 1206 void *nxt, *nxt_chain;
bb99de67 1207 uint32_t *last_chain = NULL;
73208dfd 1208 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
6d9b61ed 1209
c3a2f0df
AV		 1210 risc_address = ext_mem_cnt = 0;
1211 flags = 0;
6d9b61ed 1212
c3a2f0df
AV		 1213 if (!hardware_locked)
1214 spin_lock_irqsave(&ha->hardware_lock, flags);
6d9b61ed 1215
c3a2f0df 1216 if (!ha->fw_dump) {
7c3df132
SK		 1217 ql_log(ql_log_warn, vha, 0xd008,
1218 "No buffer available for dump.\n");
c3a2f0df
AV		 1219 goto qla25xx_fw_dump_failed;
1220 }
6d9b61ed 1221
c3a2f0df 1222 if (ha->fw_dumped) {
7c3df132
SK		 1223 ql_log(ql_log_warn, vha, 0xd009,
1224 "Firmware has been previously dumped (%p) "
1225 "-- ignoring request.\n",
1226 ha->fw_dump);
c3a2f0df
AV		 1227 goto qla25xx_fw_dump_failed;
1228 }
1229 fw = &ha->fw_dump->isp.isp25;
1230 qla2xxx_prep_dump(ha, ha->fw_dump);
b5836927 1231 ha->fw_dump->version = __constant_htonl(2);
6d9b61ed 1232
c3a2f0df 1233 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
6d9b61ed 1234
c3a2f0df 1235 /* Pause RISC. */
c81d04c9
AV		 1236 rval = qla24xx_pause_risc(reg);
1237 if (rval != QLA_SUCCESS)
1238 goto qla25xx_fw_dump_failed_0;
1239
b5836927
AV		 1240 /* Host/Risc registers. */
1241 iter_reg = fw->host_risc_reg;
1242 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1243 qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1244
1245 /* PCIe registers. */
1246 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1247 RD_REG_DWORD(&reg->iobase_addr);
1248 WRT_REG_DWORD(&reg->iobase_window, 0x01);
1249 dmp_reg = &reg->iobase_c4;
1250 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1251 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1252 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1253 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
73208dfd 1254
b5836927
AV		 1255 WRT_REG_DWORD(&reg->iobase_window, 0x00);
1256 RD_REG_DWORD(&reg->iobase_window);
1257
c81d04c9
AV		 1258 /* Host interface registers. */
1259 dmp_reg = &reg->flash_addr;
1260 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1261 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1262
1263 /* Disable interrupts. */
1264 WRT_REG_DWORD(&reg->ictrl, 0);
1265 RD_REG_DWORD(&reg->ictrl);
1266
1267 /* Shadow registers. */
1268 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1269 RD_REG_DWORD(&reg->iobase_addr);
1270 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1271 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1272
1273 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1274 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1275
1276 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1277 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1278
1279 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1280 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1281
1282 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1283 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1284
1285 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1286 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1287
1288 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1289 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1290
1291 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1292 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1293
1294 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1295 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1296
1297 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1298 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1299
1300 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1301 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1302
1303 /* RISC I/O register. */
1304 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1305 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1306
1307 /* Mailbox registers. */
1308 mbx_reg = &reg->mailbox0;
1309 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1310 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1311
1312 /* Transfer sequence registers. */
1313 iter_reg = fw->xseq_gp_reg;
1314 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1315 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1316 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1317 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1318 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1319 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1320 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1321 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1322
1323 iter_reg = fw->xseq_0_reg;
1324 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1325 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1326 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1327
1328 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1329
1330 /* Receive sequence registers. */
1331 iter_reg = fw->rseq_gp_reg;
1332 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1333 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1334 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1335 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1336 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1337 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1338 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1339 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1340
1341 iter_reg = fw->rseq_0_reg;
1342 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1343 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1344
1345 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1346 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1347
1348 /* Auxiliary sequence registers. */
1349 iter_reg = fw->aseq_gp_reg;
1350 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1351 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1352 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1353 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1354 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1355 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1356 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1357 qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1358
1359 iter_reg = fw->aseq_0_reg;
1360 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1361 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1362
1363 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1364 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1365
1366 /* Command DMA registers. */
1367 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1368
1369 /* Queues. */
1370 iter_reg = fw->req0_dma_reg;
1371 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1372 dmp_reg = &reg->iobase_q;
1373 for (cnt = 0; cnt < 7; cnt++)
1374 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1375
1376 iter_reg = fw->resp0_dma_reg;
1377 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1378 dmp_reg = &reg->iobase_q;
1379 for (cnt = 0; cnt < 7; cnt++)
1380 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1381
1382 iter_reg = fw->req1_dma_reg;
1383 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1384 dmp_reg = &reg->iobase_q;
1385 for (cnt = 0; cnt < 7; cnt++)
1386 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1387
1388 /* Transmit DMA registers. */
1389 iter_reg = fw->xmt0_dma_reg;
1390 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1391 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1392
1393 iter_reg = fw->xmt1_dma_reg;
1394 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1395 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1396
1397 iter_reg = fw->xmt2_dma_reg;
1398 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1399 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1400
1401 iter_reg = fw->xmt3_dma_reg;
1402 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1403 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1404
1405 iter_reg = fw->xmt4_dma_reg;
1406 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1407 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1408
1409 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1410
1411 /* Receive DMA registers. */
1412 iter_reg = fw->rcvt0_data_dma_reg;
1413 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1414 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1415
1416 iter_reg = fw->rcvt1_data_dma_reg;
1417 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1418 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1419
1420 /* RISC registers. */
1421 iter_reg = fw->risc_gp_reg;
1422 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1423 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1424 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1425 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1426 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1427 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1428 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1429 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1430
1431 /* Local memory controller registers. */
1432 iter_reg = fw->lmc_reg;
1433 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1434 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1435 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1436 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1437 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1438 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1439 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1440 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1441
1442 /* Fibre Protocol Module registers. */
1443 iter_reg = fw->fpm_hdw_reg;
1444 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1445 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1446 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1447 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1448 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1449 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1450 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1451 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1452 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1453 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1454 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1455 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1456
1457 /* Frame Buffer registers. */
1458 iter_reg = fw->fb_hdw_reg;
1459 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1460 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1461 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1462 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1463 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1464 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1465 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1466 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1467 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1468 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1469 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1470 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1471
d63ab533
AV		 1472 /* Multi queue registers */
1473 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
1474 &last_chain);
1475
c81d04c9
AV		 1476 rval = qla24xx_soft_reset(ha);
1477 if (rval != QLA_SUCCESS)
1478 goto qla25xx_fw_dump_failed_0;
1479
1480 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
c5722708 1481 &nxt);
c81d04c9
AV		 1482 if (rval != QLA_SUCCESS)
1483 goto qla25xx_fw_dump_failed_0;
1484
73208dfd 1485 nxt = qla2xxx_copy_queues(ha, nxt);
c81d04c9 1486
7f544d00 1487 qla24xx_copy_eft(ha, nxt);
df613b96 1488
d63ab533 1489 /* Chain entries -- started with MQ. */
050c9bb1
GM		 1490 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
1491 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
2d70c103 1492 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
bb99de67
AV		 1493 if (last_chain) {
1494 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1495 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1496 }
df613b96 1497
050c9bb1
GM		 1498 /* Adjust valid length. */
1499 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
1500
c81d04c9 1501qla25xx_fw_dump_failed_0:
3420d36c 1502 qla2xxx_dump_post_process(base_vha, rval);
6d9b61ed 1503
c3a2f0df 1504qla25xx_fw_dump_failed:
6d9b61ed
AV		 1505 if (!hardware_locked)
1506 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1507}
3a03eb79
AV		 1508
1509void
1510qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1511{
1512 int rval;
1513 uint32_t cnt;
1514 uint32_t risc_address;
1515 struct qla_hw_data *ha = vha->hw;
1516 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1517 uint32_t __iomem *dmp_reg;
1518 uint32_t *iter_reg;
1519 uint16_t __iomem *mbx_reg;
1520 unsigned long flags;
1521 struct qla81xx_fw_dump *fw;
1522 uint32_t ext_mem_cnt;
1523 void *nxt, *nxt_chain;
1524 uint32_t *last_chain = NULL;
1525 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1526
1527 risc_address = ext_mem_cnt = 0;
1528 flags = 0;
1529
1530 if (!hardware_locked)
1531 spin_lock_irqsave(&ha->hardware_lock, flags);
1532
1533 if (!ha->fw_dump) {
7c3df132
SK		 1534 ql_log(ql_log_warn, vha, 0xd00a,
1535 "No buffer available for dump.\n");
3a03eb79
AV		 1536 goto qla81xx_fw_dump_failed;
1537 }
1538
1539 if (ha->fw_dumped) {
7c3df132
SK		 1540 ql_log(ql_log_warn, vha, 0xd00b,
1541 "Firmware has been previously dumped (%p) "
1542 "-- ignoring request.\n",
1543 ha->fw_dump);
3a03eb79
AV		 1544 goto qla81xx_fw_dump_failed;
1545 }
1546 fw = &ha->fw_dump->isp.isp81;
1547 qla2xxx_prep_dump(ha, ha->fw_dump);
1548
1549 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
1550
1551 /* Pause RISC. */
1552 rval = qla24xx_pause_risc(reg);
1553 if (rval != QLA_SUCCESS)
1554 goto qla81xx_fw_dump_failed_0;
1555
1556 /* Host/Risc registers. */
1557 iter_reg = fw->host_risc_reg;
1558 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1559 qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1560
1561 /* PCIe registers. */
1562 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1563 RD_REG_DWORD(&reg->iobase_addr);
1564 WRT_REG_DWORD(&reg->iobase_window, 0x01);
1565 dmp_reg = &reg->iobase_c4;
1566 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1567 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1568 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1569 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
1570
1571 WRT_REG_DWORD(&reg->iobase_window, 0x00);
1572 RD_REG_DWORD(&reg->iobase_window);
1573
1574 /* Host interface registers. */
1575 dmp_reg = &reg->flash_addr;
1576 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1577 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1578
1579 /* Disable interrupts. */
1580 WRT_REG_DWORD(&reg->ictrl, 0);
1581 RD_REG_DWORD(&reg->ictrl);
1582
1583 /* Shadow registers. */
1584 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1585 RD_REG_DWORD(&reg->iobase_addr);
1586 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1587 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1588
1589 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1590 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1591
1592 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1593 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1594
1595 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1596 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1597
1598 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1599 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1600
1601 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1602 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1603
1604 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1605 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1606
1607 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1608 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1609
1610 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1611 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1612
1613 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1614 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1615
1616 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1617 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1618
1619 /* RISC I/O register. */
1620 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1621 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1622
1623 /* Mailbox registers. */
1624 mbx_reg = &reg->mailbox0;
1625 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1626 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1627
1628 /* Transfer sequence registers. */
1629 iter_reg = fw->xseq_gp_reg;
1630 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1631 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1632 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1633 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1634 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1635 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1636 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1637 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1638
1639 iter_reg = fw->xseq_0_reg;
1640 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1641 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1642 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1643
1644 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1645
1646 /* Receive sequence registers. */
1647 iter_reg = fw->rseq_gp_reg;
1648 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1649 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1650 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1651 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1652 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1653 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1654 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1655 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1656
1657 iter_reg = fw->rseq_0_reg;
1658 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1659 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1660
1661 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1662 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1663
1664 /* Auxiliary sequence registers. */
1665 iter_reg = fw->aseq_gp_reg;
1666 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1667 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1668 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1669 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1670 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1671 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1672 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1673 qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1674
1675 iter_reg = fw->aseq_0_reg;
1676 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1677 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1678
1679 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1680 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1681
1682 /* Command DMA registers. */
1683 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1684
1685 /* Queues. */
1686 iter_reg = fw->req0_dma_reg;
1687 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1688 dmp_reg = &reg->iobase_q;
1689 for (cnt = 0; cnt < 7; cnt++)
1690 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1691
1692 iter_reg = fw->resp0_dma_reg;
1693 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1694 dmp_reg = &reg->iobase_q;
1695 for (cnt = 0; cnt < 7; cnt++)
1696 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1697
1698 iter_reg = fw->req1_dma_reg;
1699 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1700 dmp_reg = &reg->iobase_q;
1701 for (cnt = 0; cnt < 7; cnt++)
1702 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1703
1704 /* Transmit DMA registers. */
1705 iter_reg = fw->xmt0_dma_reg;
1706 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1707 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1708
1709 iter_reg = fw->xmt1_dma_reg;
1710 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1711 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1712
1713 iter_reg = fw->xmt2_dma_reg;
1714 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1715 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1716
1717 iter_reg = fw->xmt3_dma_reg;
1718 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1719 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1720
1721 iter_reg = fw->xmt4_dma_reg;
1722 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1723 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1724
1725 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1726
1727 /* Receive DMA registers. */
1728 iter_reg = fw->rcvt0_data_dma_reg;
1729 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1730 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1731
1732 iter_reg = fw->rcvt1_data_dma_reg;
1733 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1734 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1735
1736 /* RISC registers. */
1737 iter_reg = fw->risc_gp_reg;
1738 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1739 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1740 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1741 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1742 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1743 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1744 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1745 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1746
1747 /* Local memory controller registers. */
1748 iter_reg = fw->lmc_reg;
1749 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1750 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1751 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1752 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1753 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1754 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1755 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1756 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1757
1758 /* Fibre Protocol Module registers. */
1759 iter_reg = fw->fpm_hdw_reg;
1760 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1761 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1762 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1763 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1764 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1765 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1766 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1767 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1768 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1769 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1770 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1771 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1772 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
1773 qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
1774
1775 /* Frame Buffer registers. */
1776 iter_reg = fw->fb_hdw_reg;
1777 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1778 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1779 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1780 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1781 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1782 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1783 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1784 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1785 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1786 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1787 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1788 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
1789 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1790
1791 /* Multi queue registers */
1792 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
1793 &last_chain);
1794
1795 rval = qla24xx_soft_reset(ha);
1796 if (rval != QLA_SUCCESS)
1797 goto qla81xx_fw_dump_failed_0;
1798
1799 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1800 &nxt);
1801 if (rval != QLA_SUCCESS)
1802 goto qla81xx_fw_dump_failed_0;
1803
1804 nxt = qla2xxx_copy_queues(ha, nxt);
1805
7f544d00 1806 qla24xx_copy_eft(ha, nxt);
3a03eb79
AV		 1807
1808 /* Chain entries -- started with MQ. */
050c9bb1
GM		 1809 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
1810 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
2d70c103 1811 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
3a03eb79
AV		 1812 if (last_chain) {
1813 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1814 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1815 }
1816
050c9bb1
GM		 1817 /* Adjust valid length. */
1818 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
1819
3a03eb79 1820qla81xx_fw_dump_failed_0:
3420d36c 1821 qla2xxx_dump_post_process(base_vha, rval);
3a03eb79
AV		 1822
1823qla81xx_fw_dump_failed:
1824 if (!hardware_locked)
1825 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1826}
1827
6246b8a1
GM		 1828void
1829qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1830{
1831 int rval;
1832 uint32_t cnt, reg_data;
1833 uint32_t risc_address;
1834 struct qla_hw_data *ha = vha->hw;
1835 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1836 uint32_t __iomem *dmp_reg;
1837 uint32_t *iter_reg;
1838 uint16_t __iomem *mbx_reg;
1839 unsigned long flags;
1840 struct qla83xx_fw_dump *fw;
1841 uint32_t ext_mem_cnt;
1842 void *nxt, *nxt_chain;
1843 uint32_t *last_chain = NULL;
1844 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1845
1846 risc_address = ext_mem_cnt = 0;
1847 flags = 0;
1848
1849 if (!hardware_locked)
1850 spin_lock_irqsave(&ha->hardware_lock, flags);
1851
1852 if (!ha->fw_dump) {
1853 ql_log(ql_log_warn, vha, 0xd00c,
1854 "No buffer available for dump!!!\n");
1855 goto qla83xx_fw_dump_failed;
1856 }
1857
1858 if (ha->fw_dumped) {
1859 ql_log(ql_log_warn, vha, 0xd00d,
1860 "Firmware has been previously dumped (%p) -- ignoring "
1861 "request...\n", ha->fw_dump);
1862 goto qla83xx_fw_dump_failed;
1863 }
1864 fw = &ha->fw_dump->isp.isp83;
1865 qla2xxx_prep_dump(ha, ha->fw_dump);
1866
1867 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
1868
1869 /* Pause RISC. */
1870 rval = qla24xx_pause_risc(reg);
1871 if (rval != QLA_SUCCESS)
1872 goto qla83xx_fw_dump_failed_0;
1873
1874 WRT_REG_DWORD(&reg->iobase_addr, 0x6000);
1875 dmp_reg = &reg->iobase_window;
1876 reg_data = RD_REG_DWORD(dmp_reg);
1877 WRT_REG_DWORD(dmp_reg, 0);
1878
1879 dmp_reg = &reg->unused_4_1[0];
1880 reg_data = RD_REG_DWORD(dmp_reg);
1881 WRT_REG_DWORD(dmp_reg, 0);
1882
1883 WRT_REG_DWORD(&reg->iobase_addr, 0x6010);
1884 dmp_reg = &reg->unused_4_1[2];
1885 reg_data = RD_REG_DWORD(dmp_reg);
1886 WRT_REG_DWORD(dmp_reg, 0);
1887
1888 /* select PCR and disable ecc checking and correction */
1889 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1890 RD_REG_DWORD(&reg->iobase_addr);
1891 WRT_REG_DWORD(&reg->iobase_select, 0x60000000); /* write to F0h = PCR */
1892
1893 /* Host/Risc registers. */
1894 iter_reg = fw->host_risc_reg;
1895 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1896 iter_reg = qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1897 qla24xx_read_window(reg, 0x7040, 16, iter_reg);
1898
1899 /* PCIe registers. */
1900 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1901 RD_REG_DWORD(&reg->iobase_addr);
1902 WRT_REG_DWORD(&reg->iobase_window, 0x01);
1903 dmp_reg = &reg->iobase_c4;
1904 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1905 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1906 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1907 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
1908
1909 WRT_REG_DWORD(&reg->iobase_window, 0x00);
1910 RD_REG_DWORD(&reg->iobase_window);
1911
1912 /* Host interface registers. */
1913 dmp_reg = &reg->flash_addr;
1914 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1915 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1916
1917 /* Disable interrupts. */
1918 WRT_REG_DWORD(&reg->ictrl, 0);
1919 RD_REG_DWORD(&reg->ictrl);
1920
1921 /* Shadow registers. */
1922 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1923 RD_REG_DWORD(&reg->iobase_addr);
1924 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1925 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1926
1927 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1928 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1929
1930 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1931 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1932
1933 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1934 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1935
1936 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1937 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1938
1939 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1940 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1941
1942 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1943 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1944
1945 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1946 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1947
1948 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1949 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1950
1951 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1952 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1953
1954 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1955 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1956
1957 /* RISC I/O register. */
1958 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1959 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1960
1961 /* Mailbox registers. */
1962 mbx_reg = &reg->mailbox0;
1963 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1964 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1965
1966 /* Transfer sequence registers. */
1967 iter_reg = fw->xseq_gp_reg;
1968 iter_reg = qla24xx_read_window(reg, 0xBE00, 16, iter_reg);
1969 iter_reg = qla24xx_read_window(reg, 0xBE10, 16, iter_reg);
1970 iter_reg = qla24xx_read_window(reg, 0xBE20, 16, iter_reg);
1971 iter_reg = qla24xx_read_window(reg, 0xBE30, 16, iter_reg);
1972 iter_reg = qla24xx_read_window(reg, 0xBE40, 16, iter_reg);
1973 iter_reg = qla24xx_read_window(reg, 0xBE50, 16, iter_reg);
1974 iter_reg = qla24xx_read_window(reg, 0xBE60, 16, iter_reg);
1975 iter_reg = qla24xx_read_window(reg, 0xBE70, 16, iter_reg);
1976 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1977 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1978 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1979 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1980 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1981 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1982 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1983 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1984
1985 iter_reg = fw->xseq_0_reg;
1986 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1987 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1988 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1989
1990 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1991
1992 qla24xx_read_window(reg, 0xBEF0, 16, fw->xseq_2_reg);
1993
1994 /* Receive sequence registers. */
1995 iter_reg = fw->rseq_gp_reg;
1996 iter_reg = qla24xx_read_window(reg, 0xFE00, 16, iter_reg);
1997 iter_reg = qla24xx_read_window(reg, 0xFE10, 16, iter_reg);
1998 iter_reg = qla24xx_read_window(reg, 0xFE20, 16, iter_reg);
1999 iter_reg = qla24xx_read_window(reg, 0xFE30, 16, iter_reg);
2000 iter_reg = qla24xx_read_window(reg, 0xFE40, 16, iter_reg);
2001 iter_reg = qla24xx_read_window(reg, 0xFE50, 16, iter_reg);
2002 iter_reg = qla24xx_read_window(reg, 0xFE60, 16, iter_reg);
2003 iter_reg = qla24xx_read_window(reg, 0xFE70, 16, iter_reg);
2004 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
2005 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
2006 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
2007 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
2008 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
2009 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
2010 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
2011 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
2012
2013 iter_reg = fw->rseq_0_reg;
2014 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
2015 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
2016
2017 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
2018 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
2019 qla24xx_read_window(reg, 0xFEF0, 16, fw->rseq_3_reg);
2020
2021 /* Auxiliary sequence registers. */
2022 iter_reg = fw->aseq_gp_reg;
2023 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
2024 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
2025 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
2026 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
2027 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
2028 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
2029 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
2030 iter_reg = qla24xx_read_window(reg, 0xB070, 16, iter_reg);
2031 iter_reg = qla24xx_read_window(reg, 0xB100, 16, iter_reg);
2032 iter_reg = qla24xx_read_window(reg, 0xB110, 16, iter_reg);
2033 iter_reg = qla24xx_read_window(reg, 0xB120, 16, iter_reg);
2034 iter_reg = qla24xx_read_window(reg, 0xB130, 16, iter_reg);
2035 iter_reg = qla24xx_read_window(reg, 0xB140, 16, iter_reg);
2036 iter_reg = qla24xx_read_window(reg, 0xB150, 16, iter_reg);
2037 iter_reg = qla24xx_read_window(reg, 0xB160, 16, iter_reg);
2038 qla24xx_read_window(reg, 0xB170, 16, iter_reg);
2039
2040 iter_reg = fw->aseq_0_reg;
2041 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
2042 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
2043
2044 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
2045 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
2046 qla24xx_read_window(reg, 0xB1F0, 16, fw->aseq_3_reg);
2047
2048 /* Command DMA registers. */
2049 iter_reg = fw->cmd_dma_reg;
2050 iter_reg = qla24xx_read_window(reg, 0x7100, 16, iter_reg);
2051 iter_reg = qla24xx_read_window(reg, 0x7120, 16, iter_reg);
2052 iter_reg = qla24xx_read_window(reg, 0x7130, 16, iter_reg);
2053 qla24xx_read_window(reg, 0x71F0, 16, iter_reg);
2054
2055 /* Queues. */
2056 iter_reg = fw->req0_dma_reg;
2057 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
2058 dmp_reg = &reg->iobase_q;
2059 for (cnt = 0; cnt < 7; cnt++)
2060 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
2061
2062 iter_reg = fw->resp0_dma_reg;
2063 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
2064 dmp_reg = &reg->iobase_q;
2065 for (cnt = 0; cnt < 7; cnt++)
2066 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
2067
2068 iter_reg = fw->req1_dma_reg;
2069 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
2070 dmp_reg = &reg->iobase_q;
2071 for (cnt = 0; cnt < 7; cnt++)
2072 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
2073
2074 /* Transmit DMA registers. */
2075 iter_reg = fw->xmt0_dma_reg;
2076 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
2077 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
2078
2079 iter_reg = fw->xmt1_dma_reg;
2080 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
2081 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
2082
2083 iter_reg = fw->xmt2_dma_reg;
2084 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
2085 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
2086
2087 iter_reg = fw->xmt3_dma_reg;
2088 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
2089 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
2090
2091 iter_reg = fw->xmt4_dma_reg;
2092 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
2093 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
2094
2095 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
2096
2097 /* Receive DMA registers. */
2098 iter_reg = fw->rcvt0_data_dma_reg;
2099 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
2100 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
2101
2102 iter_reg = fw->rcvt1_data_dma_reg;
2103 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
2104 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
2105
2106 /* RISC registers. */
2107 iter_reg = fw->risc_gp_reg;
2108 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
2109 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
2110 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
2111 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
2112 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
2113 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
2114 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
2115 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
2116
2117 /* Local memory controller registers. */
2118 iter_reg = fw->lmc_reg;
2119 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
2120 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
2121 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
2122 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
2123 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
2124 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
2125 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
2126 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
2127
2128 /* Fibre Protocol Module registers. */
2129 iter_reg = fw->fpm_hdw_reg;
2130 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
2131 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
2132 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
2133 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
2134 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
2135 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
2136 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
2137 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
2138 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
2139 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
2140 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
2141 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
2142 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
2143 iter_reg = qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
2144 iter_reg = qla24xx_read_window(reg, 0x40E0, 16, iter_reg);
2145 qla24xx_read_window(reg, 0x40F0, 16, iter_reg);
2146
2147 /* RQ0 Array registers. */
2148 iter_reg = fw->rq0_array_reg;
2149 iter_reg = qla24xx_read_window(reg, 0x5C00, 16, iter_reg);
2150 iter_reg = qla24xx_read_window(reg, 0x5C10, 16, iter_reg);
2151 iter_reg = qla24xx_read_window(reg, 0x5C20, 16, iter_reg);
2152 iter_reg = qla24xx_read_window(reg, 0x5C30, 16, iter_reg);
2153 iter_reg = qla24xx_read_window(reg, 0x5C40, 16, iter_reg);
2154 iter_reg = qla24xx_read_window(reg, 0x5C50, 16, iter_reg);
2155 iter_reg = qla24xx_read_window(reg, 0x5C60, 16, iter_reg);
2156 iter_reg = qla24xx_read_window(reg, 0x5C70, 16, iter_reg);
2157 iter_reg = qla24xx_read_window(reg, 0x5C80, 16, iter_reg);
2158 iter_reg = qla24xx_read_window(reg, 0x5C90, 16, iter_reg);
2159 iter_reg = qla24xx_read_window(reg, 0x5CA0, 16, iter_reg);
2160 iter_reg = qla24xx_read_window(reg, 0x5CB0, 16, iter_reg);
2161 iter_reg = qla24xx_read_window(reg, 0x5CC0, 16, iter_reg);
2162 iter_reg = qla24xx_read_window(reg, 0x5CD0, 16, iter_reg);
2163 iter_reg = qla24xx_read_window(reg, 0x5CE0, 16, iter_reg);
2164 qla24xx_read_window(reg, 0x5CF0, 16, iter_reg);
2165
2166 /* RQ1 Array registers. */
2167 iter_reg = fw->rq1_array_reg;
2168 iter_reg = qla24xx_read_window(reg, 0x5D00, 16, iter_reg);
2169 iter_reg = qla24xx_read_window(reg, 0x5D10, 16, iter_reg);
2170 iter_reg = qla24xx_read_window(reg, 0x5D20, 16, iter_reg);
2171 iter_reg = qla24xx_read_window(reg, 0x5D30, 16, iter_reg);
2172 iter_reg = qla24xx_read_window(reg, 0x5D40, 16, iter_reg);
2173 iter_reg = qla24xx_read_window(reg, 0x5D50, 16, iter_reg);
2174 iter_reg = qla24xx_read_window(reg, 0x5D60, 16, iter_reg);
2175 iter_reg = qla24xx_read_window(reg, 0x5D70, 16, iter_reg);
2176 iter_reg = qla24xx_read_window(reg, 0x5D80, 16, iter_reg);
2177 iter_reg = qla24xx_read_window(reg, 0x5D90, 16, iter_reg);
2178 iter_reg = qla24xx_read_window(reg, 0x5DA0, 16, iter_reg);
2179 iter_reg = qla24xx_read_window(reg, 0x5DB0, 16, iter_reg);
2180 iter_reg = qla24xx_read_window(reg, 0x5DC0, 16, iter_reg);
2181 iter_reg = qla24xx_read_window(reg, 0x5DD0, 16, iter_reg);
2182 iter_reg = qla24xx_read_window(reg, 0x5DE0, 16, iter_reg);
2183 qla24xx_read_window(reg, 0x5DF0, 16, iter_reg);
2184
2185 /* RP0 Array registers. */
2186 iter_reg = fw->rp0_array_reg;
2187 iter_reg = qla24xx_read_window(reg, 0x5E00, 16, iter_reg);
2188 iter_reg = qla24xx_read_window(reg, 0x5E10, 16, iter_reg);
2189 iter_reg = qla24xx_read_window(reg, 0x5E20, 16, iter_reg);
2190 iter_reg = qla24xx_read_window(reg, 0x5E30, 16, iter_reg);
2191 iter_reg = qla24xx_read_window(reg, 0x5E40, 16, iter_reg);
2192 iter_reg = qla24xx_read_window(reg, 0x5E50, 16, iter_reg);
2193 iter_reg = qla24xx_read_window(reg, 0x5E60, 16, iter_reg);
2194 iter_reg = qla24xx_read_window(reg, 0x5E70, 16, iter_reg);
2195 iter_reg = qla24xx_read_window(reg, 0x5E80, 16, iter_reg);
2196 iter_reg = qla24xx_read_window(reg, 0x5E90, 16, iter_reg);
2197 iter_reg = qla24xx_read_window(reg, 0x5EA0, 16, iter_reg);
2198 iter_reg = qla24xx_read_window(reg, 0x5EB0, 16, iter_reg);
2199 iter_reg = qla24xx_read_window(reg, 0x5EC0, 16, iter_reg);
2200 iter_reg = qla24xx_read_window(reg, 0x5ED0, 16, iter_reg);
2201 iter_reg = qla24xx_read_window(reg, 0x5EE0, 16, iter_reg);
2202 qla24xx_read_window(reg, 0x5EF0, 16, iter_reg);
2203
2204 /* RP1 Array registers. */
2205 iter_reg = fw->rp1_array_reg;
2206 iter_reg = qla24xx_read_window(reg, 0x5F00, 16, iter_reg);
2207 iter_reg = qla24xx_read_window(reg, 0x5F10, 16, iter_reg);
2208 iter_reg = qla24xx_read_window(reg, 0x5F20, 16, iter_reg);
2209 iter_reg = qla24xx_read_window(reg, 0x5F30, 16, iter_reg);
2210 iter_reg = qla24xx_read_window(reg, 0x5F40, 16, iter_reg);
2211 iter_reg = qla24xx_read_window(reg, 0x5F50, 16, iter_reg);
2212 iter_reg = qla24xx_read_window(reg, 0x5F60, 16, iter_reg);
2213 iter_reg = qla24xx_read_window(reg, 0x5F70, 16, iter_reg);
2214 iter_reg = qla24xx_read_window(reg, 0x5F80, 16, iter_reg);
2215 iter_reg = qla24xx_read_window(reg, 0x5F90, 16, iter_reg);
2216 iter_reg = qla24xx_read_window(reg, 0x5FA0, 16, iter_reg);
2217 iter_reg = qla24xx_read_window(reg, 0x5FB0, 16, iter_reg);
2218 iter_reg = qla24xx_read_window(reg, 0x5FC0, 16, iter_reg);
2219 iter_reg = qla24xx_read_window(reg, 0x5FD0, 16, iter_reg);
2220 iter_reg = qla24xx_read_window(reg, 0x5FE0, 16, iter_reg);
2221 qla24xx_read_window(reg, 0x5FF0, 16, iter_reg);
2222
2223 iter_reg = fw->at0_array_reg;
2224 iter_reg = qla24xx_read_window(reg, 0x7080, 16, iter_reg);
2225 iter_reg = qla24xx_read_window(reg, 0x7090, 16, iter_reg);
2226 iter_reg = qla24xx_read_window(reg, 0x70A0, 16, iter_reg);
2227 iter_reg = qla24xx_read_window(reg, 0x70B0, 16, iter_reg);
2228 iter_reg = qla24xx_read_window(reg, 0x70C0, 16, iter_reg);
2229 iter_reg = qla24xx_read_window(reg, 0x70D0, 16, iter_reg);
2230 iter_reg = qla24xx_read_window(reg, 0x70E0, 16, iter_reg);
2231 qla24xx_read_window(reg, 0x70F0, 16, iter_reg);
2232
2233 /* I/O Queue Control registers. */
2234 qla24xx_read_window(reg, 0x7800, 16, fw->queue_control_reg);
2235
2236 /* Frame Buffer registers. */
2237 iter_reg = fw->fb_hdw_reg;
2238 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
2239 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
2240 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
2241 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
2242 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
2243 iter_reg = qla24xx_read_window(reg, 0x6060, 16, iter_reg);
2244 iter_reg = qla24xx_read_window(reg, 0x6070, 16, iter_reg);
2245 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
2246 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
2247 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
2248 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
2249 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
2250 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
2251 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
2252 iter_reg = qla24xx_read_window(reg, 0x6530, 16, iter_reg);
2253 iter_reg = qla24xx_read_window(reg, 0x6540, 16, iter_reg);
2254 iter_reg = qla24xx_read_window(reg, 0x6550, 16, iter_reg);
2255 iter_reg = qla24xx_read_window(reg, 0x6560, 16, iter_reg);
2256 iter_reg = qla24xx_read_window(reg, 0x6570, 16, iter_reg);
2257 iter_reg = qla24xx_read_window(reg, 0x6580, 16, iter_reg);
2258 iter_reg = qla24xx_read_window(reg, 0x6590, 16, iter_reg);
2259 iter_reg = qla24xx_read_window(reg, 0x65A0, 16, iter_reg);
2260 iter_reg = qla24xx_read_window(reg, 0x65B0, 16, iter_reg);
2261 iter_reg = qla24xx_read_window(reg, 0x65C0, 16, iter_reg);
2262 iter_reg = qla24xx_read_window(reg, 0x65D0, 16, iter_reg);
2263 iter_reg = qla24xx_read_window(reg, 0x65E0, 16, iter_reg);
2264 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
2265
2266 /* Multi queue registers */
2267 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
2268 &last_chain);
2269
2270 rval = qla24xx_soft_reset(ha);
2271 if (rval != QLA_SUCCESS) {
2272 ql_log(ql_log_warn, vha, 0xd00e,
2273 "SOFT RESET FAILED, forcing continuation of dump!!!\n");
2274 rval = QLA_SUCCESS;
2275
2276 ql_log(ql_log_warn, vha, 0xd00f, "try a bigger hammer!!!\n");
2277
2278 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
2279 RD_REG_DWORD(&reg->hccr);
2280
2281 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
2282 RD_REG_DWORD(&reg->hccr);
2283
2284 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
2285 RD_REG_DWORD(&reg->hccr);
2286
2287 for (cnt = 30000; cnt && (RD_REG_WORD(&reg->mailbox0)); cnt--)
2288 udelay(5);
2289
2290 if (!cnt) {
2291 nxt = fw->code_ram;
8c0bc701 2292 nxt += sizeof(fw->code_ram);
6246b8a1
GM		 2293 nxt += (ha->fw_memory_size - 0x100000 + 1);
2294 goto copy_queue;
2295 } else
2296 ql_log(ql_log_warn, vha, 0xd010,
2297 "bigger hammer success?\n");
2298 }
2299
2300 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
2301 &nxt);
2302 if (rval != QLA_SUCCESS)
2303 goto qla83xx_fw_dump_failed_0;
2304
2305copy_queue:
2306 nxt = qla2xxx_copy_queues(ha, nxt);
2307
7f544d00 2308 qla24xx_copy_eft(ha, nxt);
6246b8a1
GM		 2309
2310 /* Chain entries -- started with MQ. */
2311 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
2312 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
2d70c103 2313 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
6246b8a1
GM		 2314 if (last_chain) {
2315 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
2316 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
2317 }
2318
2319 /* Adjust valid length. */
2320 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
2321
2322qla83xx_fw_dump_failed_0:
2323 qla2xxx_dump_post_process(base_vha, rval);
2324
2325qla83xx_fw_dump_failed:
2326 if (!hardware_locked)
2327 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2328}
2329
1da177e4
LT		 2330/****************************************************************************/
2331/* Driver Debug Functions. */
2332/****************************************************************************/
cfb0919c
CD		 2333
2334static inline int
2335ql_mask_match(uint32_t level)
2336{
2337 if (ql2xextended_error_logging == 1)
2338 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
2339 return (level & ql2xextended_error_logging) == level;
2340}
2341
3ce8866c
SK		 2342/*
2343 * This function is for formatting and logging debug information.
2344 * It is to be used when vha is available. It formats the message
2345 * and logs it to the messages file.
2346 * parameters:
2347 * level: The level of the debug messages to be printed.
2348 * If ql2xextended_error_logging value is correctly set,
2349 * this message will appear in the messages file.
2350 * vha: Pointer to the scsi_qla_host_t.
2351 * id: This is a unique identifier for the level. It identifies the
2352 * part of the code from where the message originated.
2353 * msg: The message to be displayed.
2354 */
2355void
086b3e8a
JP		 2356ql_dbg(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...)
2357{
2358 va_list va;
2359 struct va_format vaf;
3ce8866c 2360
cfb0919c 2361 if (!ql_mask_match(level))
086b3e8a 2362 return;
3ce8866c 2363
086b3e8a 2364 va_start(va, fmt);
3ce8866c 2365
086b3e8a
JP		 2366 vaf.fmt = fmt;
2367 vaf.va = &va;
3ce8866c 2368
086b3e8a
JP		 2369 if (vha != NULL) {
2370 const struct pci_dev *pdev = vha->hw->pdev;
2371 /* <module-name> <pci-name> <msg-id>:<host> Message */
2372 pr_warn("%s [%s]-%04x:%ld: %pV",
2373 QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset,
2374 vha->host_no, &vaf);
2375 } else {
2376 pr_warn("%s [%s]-%04x: : %pV",
2377 QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf);
3ce8866c
SK		 2378 }
2379
086b3e8a 2380 va_end(va);
3ce8866c
SK		 2381
2382}
2383
2384/*
2385 * This function is for formatting and logging debug information.
d6a03581 2386 * It is to be used when vha is not available and pci is available,
3ce8866c
SK		 2387 * i.e., before host allocation. It formats the message and logs it
2388 * to the messages file.
2389 * parameters:
2390 * level: The level of the debug messages to be printed.
2391 * If ql2xextended_error_logging value is correctly set,
2392 * this message will appear in the messages file.
2393 * pdev: Pointer to the struct pci_dev.
2394 * id: This is a unique id for the level. It identifies the part
2395 * of the code from where the message originated.
2396 * msg: The message to be displayed.
2397 */
2398void
086b3e8a
JP		 2399ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
2400 const char *fmt, ...)
2401{
2402 va_list va;
2403 struct va_format vaf;
3ce8866c
SK		 2404
2405 if (pdev == NULL)
2406 return;
cfb0919c 2407 if (!ql_mask_match(level))
086b3e8a 2408 return;
3ce8866c 2409
086b3e8a 2410 va_start(va, fmt);
3ce8866c 2411
086b3e8a
JP		 2412 vaf.fmt = fmt;
2413 vaf.va = &va;
3ce8866c 2414
086b3e8a
JP		 2415 /* <module-name> <dev-name>:<msg-id> Message */
2416 pr_warn("%s [%s]-%04x: : %pV",
2417 QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, &vaf);
3ce8866c 2418
086b3e8a 2419 va_end(va);
3ce8866c
SK		 2420}
2421
2422/*
2423 * This function is for formatting and logging log messages.
2424 * It is to be used when vha is available. It formats the message
2425 * and logs it to the messages file. All the messages will be logged
2426 * irrespective of value of ql2xextended_error_logging.
2427 * parameters:
2428 * level: The level of the log messages to be printed in the
2429 * messages file.
2430 * vha: Pointer to the scsi_qla_host_t
2431 * id: This is a unique id for the level. It identifies the
2432 * part of the code from where the message originated.
2433 * msg: The message to be displayed.
2434 */
2435void
086b3e8a
JP		 2436ql_log(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...)
2437{
2438 va_list va;
2439 struct va_format vaf;
2440 char pbuf[128];
3ce8866c 2441
086b3e8a
JP		 2442 if (level > ql_errlev)
2443 return;
3ce8866c 2444
086b3e8a
JP		 2445 if (vha != NULL) {
2446 const struct pci_dev *pdev = vha->hw->pdev;
2447 /* <module-name> <msg-id>:<host> Message */
2448 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x:%ld: ",
2449 QL_MSGHDR, dev_name(&(pdev->dev)), id, vha->host_no);
2450 } else {
2451 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
2452 QL_MSGHDR, "0000:00:00.0", id);
2453 }
2454 pbuf[sizeof(pbuf) - 1] = 0;
2455
2456 va_start(va, fmt);
2457
2458 vaf.fmt = fmt;
2459 vaf.va = &va;
2460
2461 switch (level) {
70a3fc76 2462 case ql_log_fatal: /* FATAL LOG */
086b3e8a
JP		 2463 pr_crit("%s%pV", pbuf, &vaf);
2464 break;
70a3fc76 2465 case ql_log_warn:
086b3e8a
JP		 2466 pr_err("%s%pV", pbuf, &vaf);
2467 break;
70a3fc76 2468 case ql_log_info:
086b3e8a
JP		 2469 pr_warn("%s%pV", pbuf, &vaf);
2470 break;
2471 default:
2472 pr_info("%s%pV", pbuf, &vaf);
2473 break;
3ce8866c
SK		 2474 }
2475
086b3e8a 2476 va_end(va);
3ce8866c
SK		 2477}
2478
2479/*
2480 * This function is for formatting and logging log messages.
d6a03581 2481 * It is to be used when vha is not available and pci is available,
3ce8866c
SK		 2482 * i.e., before host allocation. It formats the message and logs
2483 * it to the messages file. All the messages are logged irrespective
2484 * of the value of ql2xextended_error_logging.
2485 * parameters:
2486 * level: The level of the log messages to be printed in the
2487 * messages file.
2488 * pdev: Pointer to the struct pci_dev.
2489 * id: This is a unique id for the level. It identifies the
2490 * part of the code from where the message originated.
2491 * msg: The message to be displayed.
2492 */
2493void
086b3e8a
JP		 2494ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
2495 const char *fmt, ...)
2496{
2497 va_list va;
2498 struct va_format vaf;
2499 char pbuf[128];
3ce8866c
SK		 2500
2501 if (pdev == NULL)
2502 return;
086b3e8a
JP		 2503 if (level > ql_errlev)
2504 return;
3ce8866c 2505
086b3e8a
JP		 2506 /* <module-name> <dev-name>:<msg-id> Message */
2507 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
2508 QL_MSGHDR, dev_name(&(pdev->dev)), id);
2509 pbuf[sizeof(pbuf) - 1] = 0;
2510
2511 va_start(va, fmt);
2512
2513 vaf.fmt = fmt;
2514 vaf.va = &va;
2515
2516 switch (level) {
70a3fc76 2517 case ql_log_fatal: /* FATAL LOG */
086b3e8a
JP		 2518 pr_crit("%s%pV", pbuf, &vaf);
2519 break;
70a3fc76 2520 case ql_log_warn:
086b3e8a
JP		 2521 pr_err("%s%pV", pbuf, &vaf);
2522 break;
70a3fc76 2523 case ql_log_info:
086b3e8a
JP		 2524 pr_warn("%s%pV", pbuf, &vaf);
2525 break;
2526 default:
2527 pr_info("%s%pV", pbuf, &vaf);
2528 break;
3ce8866c
SK		 2529 }
2530
086b3e8a 2531 va_end(va);
3ce8866c
SK		 2532}
2533
2534void
2535ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id)
2536{
2537 int i;
2538 struct qla_hw_data *ha = vha->hw;
2539 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2540 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
2541 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
2542 uint16_t __iomem *mbx_reg;
2543
cfb0919c
CD		 2544 if (!ql_mask_match(level))
2545 return;
3ce8866c 2546
7ec0effd 2547 if (IS_P3P_TYPE(ha))
cfb0919c
CD		 2548 mbx_reg = &reg82->mailbox_in[0];
2549 else if (IS_FWI2_CAPABLE(ha))
2550 mbx_reg = &reg24->mailbox0;
2551 else
2552 mbx_reg = MAILBOX_REG(ha, reg, 0);
2553
2554 ql_dbg(level, vha, id, "Mailbox registers:\n");
2555 for (i = 0; i < 6; i++)
2556 ql_dbg(level, vha, id,
2557 "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++));
3ce8866c
SK		 2558}
2559
2560
2561void
2562ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id,
2563 uint8_t *b, uint32_t size)
2564{
2565 uint32_t cnt;
2566 uint8_t c;
cfb0919c
CD		 2567
2568 if (!ql_mask_match(level))
2569 return;
2570
2571 ql_dbg(level, vha, id, " 0 1 2 3 4 5 6 7 8 "
2572 "9 Ah Bh Ch Dh Eh Fh\n");
2573 ql_dbg(level, vha, id, "----------------------------------"
2574 "----------------------------\n");
2575
2576 ql_dbg(level, vha, id, " ");
2577 for (cnt = 0; cnt < size;) {
2578 c = *b++;
2579 printk("%02x", (uint32_t) c);
2580 cnt++;
2581 if (!(cnt % 16))
2582 printk("\n");
2583 else
2584 printk(" ");
3ce8866c 2585 }
cfb0919c
CD		 2586 if (cnt % 16)
2587 ql_dbg(level, vha, id, "\n");
3ce8866c 2588}
Linux kernel - Deliverables
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