Commit | Line | Data |
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fa90c54f AV |
1 | /* |
2 | * QLogic Fibre Channel HBA Driver | |
3 | * Copyright (c) 2003-2005 QLogic Corporation | |
1da177e4 | 4 | * |
fa90c54f AV |
5 | * See LICENSE.qla2xxx for copyright and licensing details. |
6 | */ | |
1da177e4 LT |
7 | /* |
8 | * Driver debug definitions. | |
9 | */ | |
10 | /* #define QL_DEBUG_LEVEL_1 */ /* Output register accesses to COM1 */ | |
11 | /* #define QL_DEBUG_LEVEL_2 */ /* Output error msgs to COM1 */ | |
12 | /* #define QL_DEBUG_LEVEL_3 */ /* Output function trace msgs to COM1 */ | |
13 | /* #define QL_DEBUG_LEVEL_4 */ /* Output NVRAM trace msgs to COM1 */ | |
14 | /* #define QL_DEBUG_LEVEL_5 */ /* Output ring trace msgs to COM1 */ | |
15 | /* #define QL_DEBUG_LEVEL_6 */ /* Output WATCHDOG timer trace to COM1 */ | |
16 | /* #define QL_DEBUG_LEVEL_7 */ /* Output RISC load trace msgs to COM1 */ | |
17 | /* #define QL_DEBUG_LEVEL_8 */ /* Output ring saturation msgs to COM1 */ | |
18 | /* #define QL_DEBUG_LEVEL_9 */ /* Output IOCTL trace msgs */ | |
19 | /* #define QL_DEBUG_LEVEL_10 */ /* Output IOCTL error msgs */ | |
20 | /* #define QL_DEBUG_LEVEL_11 */ /* Output Mbx Cmd trace msgs */ | |
21 | /* #define QL_DEBUG_LEVEL_12 */ /* Output IP trace msgs */ | |
22 | /* #define QL_DEBUG_LEVEL_13 */ /* Output fdmi function trace msgs */ | |
23 | /* #define QL_DEBUG_LEVEL_14 */ /* Output RSCN trace msgs */ | |
24 | /* | |
25 | * Local Macro Definitions. | |
26 | */ | |
27 | #if defined(QL_DEBUG_LEVEL_1) || defined(QL_DEBUG_LEVEL_2) || \ | |
28 | defined(QL_DEBUG_LEVEL_3) || defined(QL_DEBUG_LEVEL_4) || \ | |
29 | defined(QL_DEBUG_LEVEL_5) || defined(QL_DEBUG_LEVEL_6) || \ | |
30 | defined(QL_DEBUG_LEVEL_7) || defined(QL_DEBUG_LEVEL_8) || \ | |
31 | defined(QL_DEBUG_LEVEL_9) || defined(QL_DEBUG_LEVEL_10) || \ | |
32 | defined(QL_DEBUG_LEVEL_11) || defined(QL_DEBUG_LEVEL_12) || \ | |
33 | defined(QL_DEBUG_LEVEL_13) || defined(QL_DEBUG_LEVEL_14) | |
34 | #define QL_DEBUG_ROUTINES | |
35 | #endif | |
36 | ||
37 | /* | |
38 | * Macros use for debugging the driver. | |
39 | */ | |
1da177e4 | 40 | |
d7a297ba | 41 | #define DEBUG(x) do { if (qla2_extended_error_logging) { x; } } while (0) |
1da177e4 LT |
42 | |
43 | #if defined(QL_DEBUG_LEVEL_1) | |
744f11fd | 44 | #define DEBUG1(x) do {x;} while (0) |
1da177e4 | 45 | #else |
744f11fd | 46 | #define DEBUG1(x) do {} while (0) |
1da177e4 LT |
47 | #endif |
48 | ||
d7a297ba FD |
49 | #define DEBUG2(x) do { if (qla2_extended_error_logging) { x; } } while (0) |
50 | #define DEBUG2_3(x) do { if (qla2_extended_error_logging) { x; } } while (0) | |
51 | #define DEBUG2_3_11(x) do { if (qla2_extended_error_logging) { x; } } while (0) | |
52 | #define DEBUG2_9_10(x) do { if (qla2_extended_error_logging) { x; } } while (0) | |
53 | #define DEBUG2_11(x) do { if (qla2_extended_error_logging) { x; } } while (0) | |
54 | #define DEBUG2_13(x) do { if (qla2_extended_error_logging) { x; } } while (0) | |
1da177e4 LT |
55 | |
56 | #if defined(QL_DEBUG_LEVEL_3) | |
744f11fd | 57 | #define DEBUG3(x) do {x;} while (0) |
744f11fd | 58 | #define DEBUG3_11(x) do {x;} while (0) |
1da177e4 | 59 | #else |
744f11fd | 60 | #define DEBUG3(x) do {} while (0) |
1da177e4 LT |
61 | #endif |
62 | ||
63 | #if defined(QL_DEBUG_LEVEL_4) | |
744f11fd | 64 | #define DEBUG4(x) do {x;} while (0) |
1da177e4 | 65 | #else |
744f11fd | 66 | #define DEBUG4(x) do {} while (0) |
1da177e4 LT |
67 | #endif |
68 | ||
69 | #if defined(QL_DEBUG_LEVEL_5) | |
744f11fd | 70 | #define DEBUG5(x) do {x;} while (0) |
1da177e4 | 71 | #else |
744f11fd | 72 | #define DEBUG5(x) do {} while (0) |
1da177e4 LT |
73 | #endif |
74 | ||
75 | #if defined(QL_DEBUG_LEVEL_7) | |
744f11fd | 76 | #define DEBUG7(x) do {x;} while (0) |
1da177e4 | 77 | #else |
744f11fd | 78 | #define DEBUG7(x) do {} while (0) |
1da177e4 LT |
79 | #endif |
80 | ||
81 | #if defined(QL_DEBUG_LEVEL_9) | |
744f11fd AV |
82 | #define DEBUG9(x) do {x;} while (0) |
83 | #define DEBUG9_10(x) do {x;} while (0) | |
1da177e4 | 84 | #else |
744f11fd | 85 | #define DEBUG9(x) do {} while (0) |
1da177e4 LT |
86 | #endif |
87 | ||
88 | #if defined(QL_DEBUG_LEVEL_10) | |
744f11fd | 89 | #define DEBUG10(x) do {x;} while (0) |
744f11fd | 90 | #define DEBUG9_10(x) do {x;} while (0) |
1da177e4 | 91 | #else |
744f11fd | 92 | #define DEBUG10(x) do {} while (0) |
1da177e4 | 93 | #if !defined(DEBUG9_10) |
744f11fd | 94 | #define DEBUG9_10(x) do {} while (0) |
1da177e4 LT |
95 | #endif |
96 | #endif | |
97 | ||
98 | #if defined(QL_DEBUG_LEVEL_11) | |
744f11fd | 99 | #define DEBUG11(x) do{x;} while(0) |
1da177e4 | 100 | #if !defined(DEBUG3_11) |
744f11fd | 101 | #define DEBUG3_11(x) do{x;} while(0) |
1da177e4 LT |
102 | #endif |
103 | #else | |
744f11fd | 104 | #define DEBUG11(x) do{} while(0) |
1da177e4 | 105 | #if !defined(QL_DEBUG_LEVEL_3) |
744f11fd | 106 | #define DEBUG3_11(x) do{} while(0) |
1da177e4 LT |
107 | #endif |
108 | #endif | |
109 | ||
110 | #if defined(QL_DEBUG_LEVEL_12) | |
744f11fd | 111 | #define DEBUG12(x) do {x;} while (0) |
1da177e4 | 112 | #else |
744f11fd | 113 | #define DEBUG12(x) do {} while (0) |
1da177e4 LT |
114 | #endif |
115 | ||
116 | #if defined(QL_DEBUG_LEVEL_13) | |
117 | #define DEBUG13(x) do {x;} while (0) | |
118 | #else | |
119 | #define DEBUG13(x) do {} while (0) | |
120 | #endif | |
121 | ||
122 | #if defined(QL_DEBUG_LEVEL_14) | |
123 | #define DEBUG14(x) do {x;} while (0) | |
124 | #else | |
125 | #define DEBUG14(x) do {} while (0) | |
126 | #endif | |
127 | ||
128 | /* | |
129 | * Firmware Dump structure definition | |
130 | */ | |
1da177e4 LT |
131 | |
132 | struct qla2300_fw_dump { | |
133 | uint16_t hccr; | |
134 | uint16_t pbiu_reg[8]; | |
135 | uint16_t risc_host_reg[8]; | |
136 | uint16_t mailbox_reg[32]; | |
137 | uint16_t resp_dma_reg[32]; | |
138 | uint16_t dma_reg[48]; | |
139 | uint16_t risc_hdw_reg[16]; | |
140 | uint16_t risc_gp0_reg[16]; | |
141 | uint16_t risc_gp1_reg[16]; | |
142 | uint16_t risc_gp2_reg[16]; | |
143 | uint16_t risc_gp3_reg[16]; | |
144 | uint16_t risc_gp4_reg[16]; | |
145 | uint16_t risc_gp5_reg[16]; | |
146 | uint16_t risc_gp6_reg[16]; | |
147 | uint16_t risc_gp7_reg[16]; | |
148 | uint16_t frame_buf_hdw_reg[64]; | |
149 | uint16_t fpm_b0_reg[64]; | |
150 | uint16_t fpm_b1_reg[64]; | |
151 | uint16_t risc_ram[0xf800]; | |
152 | uint16_t stack_ram[0x1000]; | |
153 | uint16_t data_ram[1]; | |
154 | }; | |
155 | ||
156 | struct qla2100_fw_dump { | |
157 | uint16_t hccr; | |
158 | uint16_t pbiu_reg[8]; | |
159 | uint16_t mailbox_reg[32]; | |
160 | uint16_t dma_reg[48]; | |
161 | uint16_t risc_hdw_reg[16]; | |
162 | uint16_t risc_gp0_reg[16]; | |
163 | uint16_t risc_gp1_reg[16]; | |
164 | uint16_t risc_gp2_reg[16]; | |
165 | uint16_t risc_gp3_reg[16]; | |
166 | uint16_t risc_gp4_reg[16]; | |
167 | uint16_t risc_gp5_reg[16]; | |
168 | uint16_t risc_gp6_reg[16]; | |
169 | uint16_t risc_gp7_reg[16]; | |
170 | uint16_t frame_buf_hdw_reg[16]; | |
171 | uint16_t fpm_b0_reg[64]; | |
172 | uint16_t fpm_b1_reg[64]; | |
173 | uint16_t risc_ram[0xf000]; | |
174 | }; | |
175 | ||
6d9b61ed | 176 | struct qla24xx_fw_dump { |
210d5350 | 177 | uint32_t host_status; |
6d9b61ed | 178 | uint32_t host_reg[32]; |
210d5350 | 179 | uint32_t shadow_reg[7]; |
6d9b61ed AV |
180 | uint16_t mailbox_reg[32]; |
181 | uint32_t xseq_gp_reg[128]; | |
182 | uint32_t xseq_0_reg[16]; | |
183 | uint32_t xseq_1_reg[16]; | |
184 | uint32_t rseq_gp_reg[128]; | |
185 | uint32_t rseq_0_reg[16]; | |
186 | uint32_t rseq_1_reg[16]; | |
187 | uint32_t rseq_2_reg[16]; | |
188 | uint32_t cmd_dma_reg[16]; | |
189 | uint32_t req0_dma_reg[15]; | |
190 | uint32_t resp0_dma_reg[15]; | |
191 | uint32_t req1_dma_reg[15]; | |
192 | uint32_t xmt0_dma_reg[32]; | |
193 | uint32_t xmt1_dma_reg[32]; | |
194 | uint32_t xmt2_dma_reg[32]; | |
195 | uint32_t xmt3_dma_reg[32]; | |
196 | uint32_t xmt4_dma_reg[32]; | |
197 | uint32_t xmt_data_dma_reg[16]; | |
198 | uint32_t rcvt0_data_dma_reg[32]; | |
199 | uint32_t rcvt1_data_dma_reg[32]; | |
200 | uint32_t risc_gp_reg[128]; | |
6d9b61ed AV |
201 | uint32_t lmc_reg[112]; |
202 | uint32_t fpm_hdw_reg[192]; | |
203 | uint32_t fb_hdw_reg[176]; | |
204 | uint32_t code_ram[0x2000]; | |
205 | uint32_t ext_mem[1]; | |
206 | }; | |
a7a167bf AV |
207 | |
208 | #define EFT_NUM_BUFFERS 4 | |
209 | #define EFT_BYTES_PER_BUFFER 0x4000 | |
210 | #define EFT_SIZE ((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS)) | |
211 | ||
212 | struct qla2xxx_fw_dump { | |
213 | uint8_t signature[4]; | |
214 | uint32_t version; | |
215 | ||
216 | uint32_t fw_major_version; | |
217 | uint32_t fw_minor_version; | |
218 | uint32_t fw_subminor_version; | |
219 | uint32_t fw_attributes; | |
220 | ||
221 | uint32_t vendor; | |
222 | uint32_t device; | |
223 | uint32_t subsystem_vendor; | |
224 | uint32_t subsystem_device; | |
225 | ||
226 | uint32_t fixed_size; | |
227 | uint32_t mem_size; | |
228 | uint32_t req_q_size; | |
229 | uint32_t rsp_q_size; | |
230 | ||
231 | uint32_t eft_size; | |
232 | uint32_t eft_addr_l; | |
233 | uint32_t eft_addr_h; | |
234 | ||
235 | uint32_t header_size; | |
236 | ||
237 | union { | |
238 | struct qla2100_fw_dump isp21; | |
239 | struct qla2300_fw_dump isp23; | |
240 | struct qla24xx_fw_dump isp24; | |
241 | } isp; | |
242 | }; |