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Merge branch 'acpi-lpss'
[deliverable/linux.git] / drivers / scsi / qla2xxx / qla_init.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
1e63395c 3 * Copyright (c) 2003-2013 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
73208dfd 8#include "qla_gbl.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/slab.h>
0107109e 12#include <linux/vmalloc.h>
1da177e4
LT		 13
14#include "qla_devtbl.h"
15
4e08df3f
DM		 16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
4e08df3f
DM		 18#endif
19
2d70c103
NB		 20#include <target/target_core_base.h>
21#include "qla_target.h"
22
1da177e4
LT		 23/*
24* QLogic ISP2x00 Hardware Support Function Prototypes.
25*/
1da177e4 26static int qla2x00_isp_firmware(scsi_qla_host_t *);
1da177e4 27static int qla2x00_setup_chip(scsi_qla_host_t *);
1da177e4
LT		 28static int qla2x00_init_rings(scsi_qla_host_t *);
29static int qla2x00_fw_ready(scsi_qla_host_t *);
30static int qla2x00_configure_hba(scsi_qla_host_t *);
1da177e4
LT		 31static int qla2x00_configure_loop(scsi_qla_host_t *);
32static int qla2x00_configure_local_loop(scsi_qla_host_t *);
1da177e4
LT		 33static int qla2x00_configure_fabric(scsi_qla_host_t *);
34static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *);
1da177e4
LT		 35static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
36 uint16_t *);
1da177e4
LT		 37
38static int qla2x00_restart_isp(scsi_qla_host_t *);
1da177e4 39
4d4df193
HK		 40static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
41static int qla84xx_init_chip(scsi_qla_host_t *);
73208dfd 42static int qla25xx_init_queues(struct qla_hw_data *);
4d4df193 43
ac280b67
AV		 44/* SRB Extensions ---------------------------------------------------------- */
45
9ba56b95
GM		 46void
47qla2x00_sp_timeout(unsigned long __data)
ac280b67
AV		 48{
49 srb_t *sp = (srb_t *)__data;
4916392b 50 struct srb_iocb *iocb;
ac280b67
AV		 51 fc_port_t *fcport = sp->fcport;
52 struct qla_hw_data *ha = fcport->vha->hw;
53 struct req_que *req;
54 unsigned long flags;
55
56 spin_lock_irqsave(&ha->hardware_lock, flags);
57 req = ha->req_q_map[0];
58 req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 59 iocb = &sp->u.iocb_cmd;
4916392b 60 iocb->timeout(sp);
9ba56b95 61 sp->free(fcport->vha, sp);
6ac52608 62 spin_unlock_irqrestore(&ha->hardware_lock, flags);
ac280b67
AV		 63}
64
9ba56b95
GM		 65void
66qla2x00_sp_free(void *data, void *ptr)
ac280b67 67{
9ba56b95
GM		 68 srb_t *sp = (srb_t *)ptr;
69 struct srb_iocb *iocb = &sp->u.iocb_cmd;
70 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
ac280b67 71
4d97cc53 72 del_timer(&iocb->timer);
b00ee7d7 73 qla2x00_rel_sp(vha, sp);
ac280b67
AV		 74}
75
ac280b67
AV		 76/* Asynchronous Login/Logout Routines -------------------------------------- */
77
a9b6f722 78unsigned long
5b91490e
AV		 79qla2x00_get_async_timeout(struct scsi_qla_host *vha)
80{
81 unsigned long tmo;
82 struct qla_hw_data *ha = vha->hw;
83
84 /* Firmware should use switch negotiated r_a_tov for timeout. */
85 tmo = ha->r_a_tov / 10 * 2;
86 if (!IS_FWI2_CAPABLE(ha)) {
87 /*
88 * Except for earlier ISPs where the timeout is seeded from the
89 * initialization control block.
90 */
91 tmo = ha->login_timeout;
92 }
93 return tmo;
94}
ac280b67
AV		 95
96static void
9ba56b95 97qla2x00_async_iocb_timeout(void *data)
ac280b67 98{
9ba56b95 99 srb_t *sp = (srb_t *)data;
ac280b67 100 fc_port_t *fcport = sp->fcport;
ac280b67 101
7c3df132 102 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
cfb0919c 103 "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n",
9ba56b95 104 sp->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area,
7c3df132 105 fcport->d_id.b.al_pa);
ac280b67 106
5ff1d584 107 fcport->flags &= ~FCF_ASYNC_SENT;
9ba56b95
GM		 108 if (sp->type == SRB_LOGIN_CMD) {
109 struct srb_iocb *lio = &sp->u.iocb_cmd;
ac280b67 110 qla2x00_post_async_logout_work(fcport->vha, fcport, NULL);
6ac52608
AV		 111 /* Retry as needed. */
112 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
113 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
114 QLA_LOGIO_LOGIN_RETRIED : 0;
115 qla2x00_post_async_login_done_work(fcport->vha, fcport,
116 lio->u.logio.data);
117 }
ac280b67
AV		 118}
119
99b0bec7 120static void
9ba56b95 121qla2x00_async_login_sp_done(void *data, void *ptr, int res)
99b0bec7 122{
9ba56b95
GM		 123 srb_t *sp = (srb_t *)ptr;
124 struct srb_iocb *lio = &sp->u.iocb_cmd;
125 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
126
127 if (!test_bit(UNLOADING, &vha->dpc_flags))
128 qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport,
129 lio->u.logio.data);
130 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 131}
132
ac280b67
AV		 133int
134qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
135 uint16_t *data)
136{
ac280b67 137 srb_t *sp;
4916392b 138 struct srb_iocb *lio;
ac280b67
AV		 139 int rval;
140
141 rval = QLA_FUNCTION_FAILED;
9ba56b95 142 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 143 if (!sp)
144 goto done;
145
9ba56b95
GM		 146 sp->type = SRB_LOGIN_CMD;
147 sp->name = "login";
148 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
149
150 lio = &sp->u.iocb_cmd;
3822263e 151 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 152 sp->done = qla2x00_async_login_sp_done;
4916392b 153 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
ac280b67 154 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 155 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
ac280b67
AV		 156 rval = qla2x00_start_sp(sp);
157 if (rval != QLA_SUCCESS)
158 goto done_free_sp;
159
7c3df132 160 ql_dbg(ql_dbg_disc, vha, 0x2072,
cfb0919c
CD		 161 "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x "
162 "retries=%d.\n", sp->handle, fcport->loop_id,
163 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
164 fcport->login_retry);
ac280b67
AV		 165 return rval;
166
167done_free_sp:
9ba56b95 168 sp->free(fcport->vha, sp);
ac280b67
AV		 169done:
170 return rval;
171}
172
99b0bec7 173static void
9ba56b95 174qla2x00_async_logout_sp_done(void *data, void *ptr, int res)
99b0bec7 175{
9ba56b95
GM		 176 srb_t *sp = (srb_t *)ptr;
177 struct srb_iocb *lio = &sp->u.iocb_cmd;
178 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
179
180 if (!test_bit(UNLOADING, &vha->dpc_flags))
181 qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport,
182 lio->u.logio.data);
183 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 184}
185
ac280b67
AV		 186int
187qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
188{
ac280b67 189 srb_t *sp;
4916392b 190 struct srb_iocb *lio;
ac280b67
AV		 191 int rval;
192
193 rval = QLA_FUNCTION_FAILED;
9ba56b95 194 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 195 if (!sp)
196 goto done;
197
9ba56b95
GM		 198 sp->type = SRB_LOGOUT_CMD;
199 sp->name = "logout";
200 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
201
202 lio = &sp->u.iocb_cmd;
3822263e 203 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 204 sp->done = qla2x00_async_logout_sp_done;
ac280b67
AV		 205 rval = qla2x00_start_sp(sp);
206 if (rval != QLA_SUCCESS)
207 goto done_free_sp;
208
7c3df132 209 ql_dbg(ql_dbg_disc, vha, 0x2070,
cfb0919c
CD		 210 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
211 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
212 fcport->d_id.b.area, fcport->d_id.b.al_pa);
ac280b67
AV		 213 return rval;
214
215done_free_sp:
9ba56b95 216 sp->free(fcport->vha, sp);
ac280b67
AV		 217done:
218 return rval;
219}
220
5ff1d584 221static void
9ba56b95 222qla2x00_async_adisc_sp_done(void *data, void *ptr, int res)
5ff1d584 223{
9ba56b95
GM		 224 srb_t *sp = (srb_t *)ptr;
225 struct srb_iocb *lio = &sp->u.iocb_cmd;
226 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
227
228 if (!test_bit(UNLOADING, &vha->dpc_flags))
229 qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport,
230 lio->u.logio.data);
231 sp->free(sp->fcport->vha, sp);
5ff1d584
AV		 232}
233
234int
235qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
236 uint16_t *data)
237{
5ff1d584 238 srb_t *sp;
4916392b 239 struct srb_iocb *lio;
5ff1d584
AV		 240 int rval;
241
242 rval = QLA_FUNCTION_FAILED;
9ba56b95 243 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
5ff1d584
AV		 244 if (!sp)
245 goto done;
246
9ba56b95
GM		 247 sp->type = SRB_ADISC_CMD;
248 sp->name = "adisc";
249 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
250
251 lio = &sp->u.iocb_cmd;
3822263e 252 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 253 sp->done = qla2x00_async_adisc_sp_done;
5ff1d584 254 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 255 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
5ff1d584
AV		 256 rval = qla2x00_start_sp(sp);
257 if (rval != QLA_SUCCESS)
258 goto done_free_sp;
259
7c3df132 260 ql_dbg(ql_dbg_disc, vha, 0x206f,
cfb0919c
CD		 261 "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
262 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
263 fcport->d_id.b.area, fcport->d_id.b.al_pa);
5ff1d584
AV		 264 return rval;
265
266done_free_sp:
9ba56b95 267 sp->free(fcport->vha, sp);
5ff1d584
AV		 268done:
269 return rval;
270}
271
3822263e 272static void
9ba56b95 273qla2x00_async_tm_cmd_done(void *data, void *ptr, int res)
3822263e 274{
9ba56b95
GM		 275 srb_t *sp = (srb_t *)ptr;
276 struct srb_iocb *iocb = &sp->u.iocb_cmd;
277 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
278 uint32_t flags;
279 uint16_t lun;
280 int rval;
3822263e 281
9ba56b95
GM		 282 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
283 flags = iocb->u.tmf.flags;
284 lun = (uint16_t)iocb->u.tmf.lun;
285
286 /* Issue Marker IOCB */
287 rval = qla2x00_marker(vha, vha->hw->req_q_map[0],
288 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
289 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
290
291 if ((rval != QLA_SUCCESS) || iocb->u.tmf.data) {
292 ql_dbg(ql_dbg_taskm, vha, 0x8030,
293 "TM IOCB failed (%x).\n", rval);
294 }
295 }
296 sp->free(sp->fcport->vha, sp);
3822263e
MI		 297}
298
299int
9ba56b95 300qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t tm_flags, uint32_t lun,
3822263e
MI		 301 uint32_t tag)
302{
303 struct scsi_qla_host *vha = fcport->vha;
3822263e 304 srb_t *sp;
3822263e
MI		 305 struct srb_iocb *tcf;
306 int rval;
307
308 rval = QLA_FUNCTION_FAILED;
9ba56b95 309 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
3822263e
MI		 310 if (!sp)
311 goto done;
312
9ba56b95
GM		 313 sp->type = SRB_TM_CMD;
314 sp->name = "tmf";
315 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
316
317 tcf = &sp->u.iocb_cmd;
318 tcf->u.tmf.flags = tm_flags;
3822263e
MI		 319 tcf->u.tmf.lun = lun;
320 tcf->u.tmf.data = tag;
321 tcf->timeout = qla2x00_async_iocb_timeout;
9ba56b95 322 sp->done = qla2x00_async_tm_cmd_done;
3822263e
MI		 323
324 rval = qla2x00_start_sp(sp);
325 if (rval != QLA_SUCCESS)
326 goto done_free_sp;
327
7c3df132 328 ql_dbg(ql_dbg_taskm, vha, 0x802f,
cfb0919c
CD		 329 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
330 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
331 fcport->d_id.b.area, fcport->d_id.b.al_pa);
3822263e
MI		 332 return rval;
333
334done_free_sp:
9ba56b95 335 sp->free(fcport->vha, sp);
3822263e
MI		 336done:
337 return rval;
338}
339
4916392b 340void
ac280b67
AV		 341qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport,
342 uint16_t *data)
343{
344 int rval;
ac280b67
AV		 345
346 switch (data[0]) {
347 case MBS_COMMAND_COMPLETE:
a4f92a32
AV		 348 /*
349 * Driver must validate login state - If PRLI not complete,
350 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
351 * requests.
352 */
353 rval = qla2x00_get_port_database(vha, fcport, 0);
0eba25df
AE		 354 if (rval == QLA_NOT_LOGGED_IN) {
355 fcport->flags &= ~FCF_ASYNC_SENT;
356 fcport->flags |= FCF_LOGIN_NEEDED;
357 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
358 break;
359 }
360
a4f92a32
AV		 361 if (rval != QLA_SUCCESS) {
362 qla2x00_post_async_logout_work(vha, fcport, NULL);
363 qla2x00_post_async_login_work(vha, fcport, NULL);
364 break;
365 }
99b0bec7 366 if (fcport->flags & FCF_FCP2_DEVICE) {
5ff1d584
AV		 367 qla2x00_post_async_adisc_work(vha, fcport, data);
368 break;
99b0bec7
AV		 369 }
370 qla2x00_update_fcport(vha, fcport);
ac280b67
AV		 371 break;
372 case MBS_COMMAND_ERROR:
5ff1d584 373 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 374 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
375 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
376 else
80d79440 377 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 378 break;
379 case MBS_PORT_ID_USED:
380 fcport->loop_id = data[1];
6ac52608 381 qla2x00_post_async_logout_work(vha, fcport, NULL);
ac280b67
AV		 382 qla2x00_post_async_login_work(vha, fcport, NULL);
383 break;
384 case MBS_LOOP_ID_USED:
385 fcport->loop_id++;
386 rval = qla2x00_find_new_loop_id(vha, fcport);
387 if (rval != QLA_SUCCESS) {
5ff1d584 388 fcport->flags &= ~FCF_ASYNC_SENT;
80d79440 389 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 390 break;
391 }
392 qla2x00_post_async_login_work(vha, fcport, NULL);
393 break;
394 }
4916392b 395 return;
ac280b67
AV		 396}
397
4916392b 398void
ac280b67
AV		 399qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
400 uint16_t *data)
401{
402 qla2x00_mark_device_lost(vha, fcport, 1, 0);
4916392b 403 return;
ac280b67
AV		 404}
405
4916392b 406void
5ff1d584
AV		 407qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
408 uint16_t *data)
409{
410 if (data[0] == MBS_COMMAND_COMPLETE) {
411 qla2x00_update_fcport(vha, fcport);
412
4916392b 413 return;
5ff1d584
AV		 414 }
415
416 /* Retry login. */
417 fcport->flags &= ~FCF_ASYNC_SENT;
418 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
419 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
420 else
80d79440 421 qla2x00_mark_device_lost(vha, fcport, 1, 0);
5ff1d584 422
4916392b 423 return;
5ff1d584
AV		 424}
425
1da177e4
LT		 426/****************************************************************************/
427/* QLogic ISP2x00 Hardware Support Functions. */
428/****************************************************************************/
429
fa492630 430static int
7d613ac6
SV		 431qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
432{
433 int rval = QLA_SUCCESS;
434 struct qla_hw_data *ha = vha->hw;
435 uint32_t idc_major_ver, idc_minor_ver;
711aa7f7 436 uint16_t config[4];
7d613ac6
SV		 437
438 qla83xx_idc_lock(vha, 0);
439
440 /* SV: TODO: Assign initialization timeout from
441 * flash-info / other param
442 */
443 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
444 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
445
446 /* Set our fcoe function presence */
447 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
448 ql_dbg(ql_dbg_p3p, vha, 0xb077,
449 "Error while setting DRV-Presence.\n");
450 rval = QLA_FUNCTION_FAILED;
451 goto exit;
452 }
453
454 /* Decide the reset ownership */
455 qla83xx_reset_ownership(vha);
456
457 /*
458 * On first protocol driver load:
459 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
460 * register.
461 * Others: Check compatibility with current IDC Major version.
462 */
463 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
464 if (ha->flags.nic_core_reset_owner) {
465 /* Set IDC Major version */
466 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
467 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
468
469 /* Clearing IDC-Lock-Recovery register */
470 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
471 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
472 /*
473 * Clear further IDC participation if we are not compatible with
474 * the current IDC Major Version.
475 */
476 ql_log(ql_log_warn, vha, 0xb07d,
477 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
478 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
479 __qla83xx_clear_drv_presence(vha);
480 rval = QLA_FUNCTION_FAILED;
481 goto exit;
482 }
483 /* Each function sets its supported Minor version. */
484 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
485 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
486 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
487
711aa7f7
SK		 488 if (ha->flags.nic_core_reset_owner) {
489 memset(config, 0, sizeof(config));
490 if (!qla81xx_get_port_config(vha, config))
491 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
492 QLA8XXX_DEV_READY);
493 }
494
7d613ac6
SV		 495 rval = qla83xx_idc_state_handler(vha);
496
497exit:
498 qla83xx_idc_unlock(vha, 0);
499
500 return rval;
501}
502
1da177e4
LT		 503/*
504* qla2x00_initialize_adapter
505* Initialize board.
506*
507* Input:
508* ha = adapter block pointer.
509*
510* Returns:
511* 0 = success
512*/
513int
e315cd28 514qla2x00_initialize_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 515{
516 int rval;
e315cd28 517 struct qla_hw_data *ha = vha->hw;
73208dfd 518 struct req_que *req = ha->req_q_map[0];
2533cf67 519
1da177e4 520 /* Clear adapter flags. */
e315cd28 521 vha->flags.online = 0;
2533cf67 522 ha->flags.chip_reset_done = 0;
e315cd28 523 vha->flags.reset_active = 0;
85880801
AV		 524 ha->flags.pci_channel_io_perm_failure = 0;
525 ha->flags.eeh_busy = 0;
fe52f6e1 526 ha->thermal_support = THERMAL_SUPPORT_I2C|THERMAL_SUPPORT_ISP;
e315cd28
AC		 527 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
528 atomic_set(&vha->loop_state, LOOP_DOWN);
529 vha->device_flags = DFLG_NO_CABLE;
530 vha->dpc_flags = 0;
531 vha->flags.management_server_logged_in = 0;
532 vha->marker_needed = 0;
1da177e4
LT		 533 ha->isp_abort_cnt = 0;
534 ha->beacon_blink_led = 0;
535
73208dfd
AC		 536 set_bit(0, ha->req_qid_map);
537 set_bit(0, ha->rsp_qid_map);
538
cfb0919c 539 ql_dbg(ql_dbg_init, vha, 0x0040,
7c3df132 540 "Configuring PCI space...\n");
e315cd28 541 rval = ha->isp_ops->pci_config(vha);
1da177e4 542 if (rval) {
7c3df132
SK		 543 ql_log(ql_log_warn, vha, 0x0044,
544 "Unable to configure PCI space.\n");
1da177e4
LT		 545 return (rval);
546 }
547
e315cd28 548 ha->isp_ops->reset_chip(vha);
1da177e4 549
e315cd28 550 rval = qla2xxx_get_flash_info(vha);
c00d8994 551 if (rval) {
7c3df132
SK		 552 ql_log(ql_log_fatal, vha, 0x004f,
553 "Unable to validate FLASH data.\n");
c00d8994
AV		 554 return (rval);
555 }
556
73208dfd 557 ha->isp_ops->get_flash_version(vha, req->ring);
cfb0919c 558 ql_dbg(ql_dbg_init, vha, 0x0061,
7c3df132 559 "Configure NVRAM parameters...\n");
0107109e 560
e315cd28 561 ha->isp_ops->nvram_config(vha);
1da177e4 562
d4c760c2
AV		 563 if (ha->flags.disable_serdes) {
564 /* Mask HBA via NVRAM settings? */
7c3df132
SK		 565 ql_log(ql_log_info, vha, 0x0077,
566 "Masking HBA WWPN "
d4c760c2 567 "%02x%02x%02x%02x%02x%02x%02x%02x (via NVRAM).\n",
e315cd28
AC		 568 vha->port_name[0], vha->port_name[1],
569 vha->port_name[2], vha->port_name[3],
570 vha->port_name[4], vha->port_name[5],
571 vha->port_name[6], vha->port_name[7]);
d4c760c2
AV		 572 return QLA_FUNCTION_FAILED;
573 }
574
cfb0919c 575 ql_dbg(ql_dbg_init, vha, 0x0078,
7c3df132 576 "Verifying loaded RISC code...\n");
1da177e4 577
e315cd28
AC		 578 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
579 rval = ha->isp_ops->chip_diag(vha);
d19044c3
AV		 580 if (rval)
581 return (rval);
e315cd28 582 rval = qla2x00_setup_chip(vha);
d19044c3
AV		 583 if (rval)
584 return (rval);
1da177e4 585 }
a9083016 586
4d4df193 587 if (IS_QLA84XX(ha)) {
e315cd28 588 ha->cs84xx = qla84xx_get_chip(vha);
4d4df193 589 if (!ha->cs84xx) {
7c3df132 590 ql_log(ql_log_warn, vha, 0x00d0,
4d4df193
HK		 591 "Unable to configure ISP84XX.\n");
592 return QLA_FUNCTION_FAILED;
593 }
594 }
2d70c103
NB		 595
596 if (qla_ini_mode_enabled(vha))
597 rval = qla2x00_init_rings(vha);
598
2533cf67 599 ha->flags.chip_reset_done = 1;
1da177e4 600
9a069e19 601 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
6c452a45 602 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
9a069e19
GM		 603 rval = qla84xx_init_chip(vha);
604 if (rval != QLA_SUCCESS) {
7c3df132
SK		 605 ql_log(ql_log_warn, vha, 0x00d4,
606 "Unable to initialize ISP84XX.\n");
9a069e19
GM		 607 qla84xx_put_chip(vha);
608 }
609 }
610
7d613ac6
SV		 611 /* Load the NIC Core f/w if we are the first protocol driver. */
612 if (IS_QLA8031(ha)) {
613 rval = qla83xx_nic_core_fw_load(vha);
614 if (rval)
615 ql_log(ql_log_warn, vha, 0x0124,
616 "Error in initializing NIC Core f/w.\n");
617 }
618
2f0f3f4f
MI		 619 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
620 qla24xx_read_fcp_prio_cfg(vha);
09ff701a 621
1da177e4
LT		 622 return (rval);
623}
624
625/**
abbd8870 626 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
1da177e4
LT		 627 * @ha: HA context
628 *
629 * Returns 0 on success.
630 */
abbd8870 631int
e315cd28 632qla2100_pci_config(scsi_qla_host_t *vha)
1da177e4 633{
a157b101 634 uint16_t w;
abbd8870 635 unsigned long flags;
e315cd28 636 struct qla_hw_data *ha = vha->hw;
3d71644c 637 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 638
1da177e4 639 pci_set_master(ha->pdev);
af6177d8 640 pci_try_set_mwi(ha->pdev);
1da177e4 641
1da177e4 642 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 643 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
abbd8870
AV		 644 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
645
737faece 646 pci_disable_rom(ha->pdev);
1da177e4
LT		 647
648 /* Get PCI bus information. */
649 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 650 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
1da177e4
LT		 651 spin_unlock_irqrestore(&ha->hardware_lock, flags);
652
abbd8870
AV		 653 return QLA_SUCCESS;
654}
1da177e4 655
abbd8870
AV		 656/**
657 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
658 * @ha: HA context
659 *
660 * Returns 0 on success.
661 */
662int
e315cd28 663qla2300_pci_config(scsi_qla_host_t *vha)
abbd8870 664{
a157b101 665 uint16_t w;
abbd8870
AV		 666 unsigned long flags = 0;
667 uint32_t cnt;
e315cd28 668 struct qla_hw_data *ha = vha->hw;
3d71644c 669 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 670
abbd8870 671 pci_set_master(ha->pdev);
af6177d8 672 pci_try_set_mwi(ha->pdev);
1da177e4 673
abbd8870 674 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 675 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1da177e4 676
abbd8870
AV		 677 if (IS_QLA2322(ha) || IS_QLA6322(ha))
678 w &= ~PCI_COMMAND_INTX_DISABLE;
a157b101 679 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1da177e4 680
abbd8870
AV		 681 /*
682 * If this is a 2300 card and not 2312, reset the
683 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
684 * the 2310 also reports itself as a 2300 so we need to get the
685 * fb revision level -- a 6 indicates it really is a 2300 and
686 * not a 2310.
687 */
688 if (IS_QLA2300(ha)) {
689 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 690
abbd8870 691 /* Pause RISC. */
3d71644c 692 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
abbd8870 693 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 694 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
abbd8870 695 break;
1da177e4 696
abbd8870
AV		 697 udelay(10);
698 }
1da177e4 699
abbd8870 700 /* Select FPM registers. */
3d71644c
AV		 701 WRT_REG_WORD(&reg->ctrl_status, 0x20);
702 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 703
704 /* Get the fb rev level */
3d71644c 705 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
abbd8870
AV		 706
707 if (ha->fb_rev == FPM_2300)
a157b101 708 pci_clear_mwi(ha->pdev);
abbd8870
AV		 709
710 /* Deselect FPM registers. */
3d71644c
AV		 711 WRT_REG_WORD(&reg->ctrl_status, 0x0);
712 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 713
714 /* Release RISC module. */
3d71644c 715 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
abbd8870 716 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 717 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
abbd8870
AV		 718 break;
719
720 udelay(10);
1da177e4 721 }
1da177e4 722
abbd8870
AV		 723 spin_unlock_irqrestore(&ha->hardware_lock, flags);
724 }
1da177e4 725
abbd8870
AV		 726 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
727
737faece 728 pci_disable_rom(ha->pdev);
1da177e4 729
abbd8870
AV		 730 /* Get PCI bus information. */
731 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 732 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 733 spin_unlock_irqrestore(&ha->hardware_lock, flags);
734
735 return QLA_SUCCESS;
1da177e4
LT		 736}
737
0107109e
AV		 738/**
739 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
740 * @ha: HA context
741 *
742 * Returns 0 on success.
743 */
744int
e315cd28 745qla24xx_pci_config(scsi_qla_host_t *vha)
0107109e 746{
a157b101 747 uint16_t w;
0107109e 748 unsigned long flags = 0;
e315cd28 749 struct qla_hw_data *ha = vha->hw;
0107109e 750 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
0107109e
AV		 751
752 pci_set_master(ha->pdev);
af6177d8 753 pci_try_set_mwi(ha->pdev);
0107109e
AV		 754
755 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 756 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
0107109e
AV		 757 w &= ~PCI_COMMAND_INTX_DISABLE;
758 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
759
760 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
761
762 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
f85ec187
AV		 763 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
764 pcix_set_mmrbc(ha->pdev, 2048);
0107109e
AV		 765
766 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 767 if (pci_is_pcie(ha->pdev))
5ffd3a52 768 pcie_set_readrq(ha->pdev, 4096);
0107109e 769
737faece 770 pci_disable_rom(ha->pdev);
0107109e 771
44c10138 772 ha->chip_revision = ha->pdev->revision;
a8488abe 773
0107109e
AV		 774 /* Get PCI bus information. */
775 spin_lock_irqsave(&ha->hardware_lock, flags);
776 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
777 spin_unlock_irqrestore(&ha->hardware_lock, flags);
778
779 return QLA_SUCCESS;
780}
781
c3a2f0df
AV		 782/**
783 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
784 * @ha: HA context
785 *
786 * Returns 0 on success.
787 */
788int
e315cd28 789qla25xx_pci_config(scsi_qla_host_t *vha)
c3a2f0df
AV		 790{
791 uint16_t w;
e315cd28 792 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 793
794 pci_set_master(ha->pdev);
795 pci_try_set_mwi(ha->pdev);
796
797 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
798 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
799 w &= ~PCI_COMMAND_INTX_DISABLE;
800 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
801
802 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 803 if (pci_is_pcie(ha->pdev))
5ffd3a52 804 pcie_set_readrq(ha->pdev, 4096);
c3a2f0df 805
737faece 806 pci_disable_rom(ha->pdev);
c3a2f0df
AV		 807
808 ha->chip_revision = ha->pdev->revision;
809
810 return QLA_SUCCESS;
811}
812
1da177e4
LT		 813/**
814 * qla2x00_isp_firmware() - Choose firmware image.
815 * @ha: HA context
816 *
817 * Returns 0 on success.
818 */
819static int
e315cd28 820qla2x00_isp_firmware(scsi_qla_host_t *vha)
1da177e4
LT		 821{
822 int rval;
42e421b1
AV		 823 uint16_t loop_id, topo, sw_cap;
824 uint8_t domain, area, al_pa;
e315cd28 825 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 826
827 /* Assume loading risc code */
fa2a1ce5 828 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 829
830 if (ha->flags.disable_risc_code_load) {
7c3df132 831 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
1da177e4
LT		 832
833 /* Verify checksum of loaded RISC code. */
e315cd28 834 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
42e421b1
AV		 835 if (rval == QLA_SUCCESS) {
836 /* And, verify we are not in ROM code. */
e315cd28 837 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
42e421b1
AV		 838 &area, &domain, &topo, &sw_cap);
839 }
1da177e4
LT		 840 }
841
7c3df132
SK		 842 if (rval)
843 ql_dbg(ql_dbg_init, vha, 0x007a,
844 "**** Load RISC code ****.\n");
1da177e4
LT		 845
846 return (rval);
847}
848
849/**
850 * qla2x00_reset_chip() - Reset ISP chip.
851 * @ha: HA context
852 *
853 * Returns 0 on success.
854 */
abbd8870 855void
e315cd28 856qla2x00_reset_chip(scsi_qla_host_t *vha)
1da177e4
LT		 857{
858 unsigned long flags = 0;
e315cd28 859 struct qla_hw_data *ha = vha->hw;
3d71644c 860 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 861 uint32_t cnt;
1da177e4
LT		 862 uint16_t cmd;
863
85880801
AV		 864 if (unlikely(pci_channel_offline(ha->pdev)))
865 return;
866
fd34f556 867 ha->isp_ops->disable_intrs(ha);
1da177e4
LT		 868
869 spin_lock_irqsave(&ha->hardware_lock, flags);
870
871 /* Turn off master enable */
872 cmd = 0;
873 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
874 cmd &= ~PCI_COMMAND_MASTER;
875 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
876
877 if (!IS_QLA2100(ha)) {
878 /* Pause RISC. */
879 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
880 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
881 for (cnt = 0; cnt < 30000; cnt++) {
882 if ((RD_REG_WORD(&reg->hccr) &
883 HCCR_RISC_PAUSE) != 0)
884 break;
885 udelay(100);
886 }
887 } else {
888 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
889 udelay(10);
890 }
891
892 /* Select FPM registers. */
893 WRT_REG_WORD(&reg->ctrl_status, 0x20);
894 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
895
896 /* FPM Soft Reset. */
897 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
898 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
899
900 /* Toggle Fpm Reset. */
901 if (!IS_QLA2200(ha)) {
902 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
903 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
904 }
905
906 /* Select frame buffer registers. */
907 WRT_REG_WORD(&reg->ctrl_status, 0x10);
908 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
909
910 /* Reset frame buffer FIFOs. */
911 if (IS_QLA2200(ha)) {
912 WRT_FB_CMD_REG(ha, reg, 0xa000);
913 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
914 } else {
915 WRT_FB_CMD_REG(ha, reg, 0x00fc);
916
917 /* Read back fb_cmd until zero or 3 seconds max */
918 for (cnt = 0; cnt < 3000; cnt++) {
919 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
920 break;
921 udelay(100);
922 }
923 }
924
925 /* Select RISC module registers. */
926 WRT_REG_WORD(&reg->ctrl_status, 0);
927 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
928
929 /* Reset RISC processor. */
930 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
931 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
932
933 /* Release RISC processor. */
934 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
935 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
936 }
937
938 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
939 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
940
941 /* Reset ISP chip. */
942 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
943
944 /* Wait for RISC to recover from reset. */
945 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
946 /*
947 * It is necessary to for a delay here since the card doesn't
948 * respond to PCI reads during a reset. On some architectures
949 * this will result in an MCA.
950 */
951 udelay(20);
952 for (cnt = 30000; cnt; cnt--) {
953 if ((RD_REG_WORD(&reg->ctrl_status) &
954 CSR_ISP_SOFT_RESET) == 0)
955 break;
956 udelay(100);
957 }
958 } else
959 udelay(10);
960
961 /* Reset RISC processor. */
962 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
963
964 WRT_REG_WORD(&reg->semaphore, 0);
965
966 /* Release RISC processor. */
967 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
968 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
969
970 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
971 for (cnt = 0; cnt < 30000; cnt++) {
ffb39f03 972 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1da177e4 973 break;
1da177e4
LT		 974
975 udelay(100);
976 }
977 } else
978 udelay(100);
979
980 /* Turn on master enable */
981 cmd |= PCI_COMMAND_MASTER;
982 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
983
984 /* Disable RISC pause on FPM parity error. */
985 if (!IS_QLA2100(ha)) {
986 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
987 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
988 }
989
990 spin_unlock_irqrestore(&ha->hardware_lock, flags);
991}
992
b1d46989
MI		 993/**
994 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
995 *
996 * Returns 0 on success.
997 */
fa492630 998static int
b1d46989
MI		 999qla81xx_reset_mpi(scsi_qla_host_t *vha)
1000{
1001 uint16_t mb[4] = {0x1010, 0, 1, 0};
1002
6246b8a1
GM		 1003 if (!IS_QLA81XX(vha->hw))
1004 return QLA_SUCCESS;
1005
b1d46989
MI		 1006 return qla81xx_write_mpi_register(vha, mb);
1007}
1008
0107109e 1009/**
88c26663 1010 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
0107109e
AV		 1011 * @ha: HA context
1012 *
1013 * Returns 0 on success.
1014 */
88c26663 1015static inline void
e315cd28 1016qla24xx_reset_risc(scsi_qla_host_t *vha)
0107109e
AV		 1017{
1018 unsigned long flags = 0;
e315cd28 1019 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 1020 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1021 uint32_t cnt, d2;
335a1cc9 1022 uint16_t wd;
b1d46989 1023 static int abts_cnt; /* ISP abort retry counts */
0107109e 1024
0107109e
AV		 1025 spin_lock_irqsave(&ha->hardware_lock, flags);
1026
1027 /* Reset RISC. */
1028 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1029 for (cnt = 0; cnt < 30000; cnt++) {
1030 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
1031 break;
1032
1033 udelay(10);
1034 }
1035
1036 WRT_REG_DWORD(&reg->ctrl_status,
1037 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335a1cc9 1038 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
88c26663 1039
335a1cc9 1040 udelay(100);
88c26663 1041 /* Wait for firmware to complete NVRAM accesses. */
88c26663
AV		 1042 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1043 for (cnt = 10000 ; cnt && d2; cnt--) {
1044 udelay(5);
1045 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1046 barrier();
1047 }
1048
335a1cc9 1049 /* Wait for soft-reset to complete. */
0107109e
AV		 1050 d2 = RD_REG_DWORD(&reg->ctrl_status);
1051 for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) {
1052 udelay(5);
1053 d2 = RD_REG_DWORD(&reg->ctrl_status);
1054 barrier();
1055 }
1056
b1d46989
MI		 1057 /* If required, do an MPI FW reset now */
1058 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
1059 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
1060 if (++abts_cnt < 5) {
1061 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1062 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
1063 } else {
1064 /*
1065 * We exhausted the ISP abort retries. We have to
1066 * set the board offline.
1067 */
1068 abts_cnt = 0;
1069 vha->flags.online = 0;
1070 }
1071 }
1072 }
1073
0107109e
AV		 1074 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
1075 RD_REG_DWORD(&reg->hccr);
1076
1077 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
1078 RD_REG_DWORD(&reg->hccr);
1079
1080 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
1081 RD_REG_DWORD(&reg->hccr);
1082
1083 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1084 for (cnt = 6000000 ; cnt && d2; cnt--) {
1085 udelay(5);
1086 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1087 barrier();
1088 }
1089
1090 spin_unlock_irqrestore(&ha->hardware_lock, flags);
124f85e6
AV		 1091
1092 if (IS_NOPOLLING_TYPE(ha))
1093 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 1094}
1095
4ea2c9c7
JC		 1096static void
1097qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
1098{
1099 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1100
1101 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1102 *data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);
1103
1104}
1105
1106static void
1107qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
1108{
1109 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1110
1111 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1112 WRT_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
1113}
1114
1115static void
1116qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
1117{
1118 struct qla_hw_data *ha = vha->hw;
1119 uint32_t wd32 = 0;
1120 uint delta_msec = 100;
1121 uint elapsed_msec = 0;
1122 uint timeout_msec;
1123 ulong n;
1124
1125 if (!IS_QLA25XX(ha) && !IS_QLA2031(ha))
1126 return;
1127
1128attempt:
1129 timeout_msec = TIMEOUT_SEMAPHORE;
1130 n = timeout_msec / delta_msec;
1131 while (n--) {
1132 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
1133 qla25xx_read_risc_sema_reg(vha, &wd32);
1134 if (wd32 & RISC_SEMAPHORE)
1135 break;
1136 msleep(delta_msec);
1137 elapsed_msec += delta_msec;
1138 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1139 goto force;
1140 }
1141
1142 if (!(wd32 & RISC_SEMAPHORE))
1143 goto force;
1144
1145 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1146 goto acquired;
1147
1148 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
1149 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
1150 n = timeout_msec / delta_msec;
1151 while (n--) {
1152 qla25xx_read_risc_sema_reg(vha, &wd32);
1153 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1154 break;
1155 msleep(delta_msec);
1156 elapsed_msec += delta_msec;
1157 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1158 goto force;
1159 }
1160
1161 if (wd32 & RISC_SEMAPHORE_FORCE)
1162 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
1163
1164 goto attempt;
1165
1166force:
1167 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
1168
1169acquired:
1170 return;
1171}
1172
88c26663
AV		 1173/**
1174 * qla24xx_reset_chip() - Reset ISP24xx chip.
1175 * @ha: HA context
1176 *
1177 * Returns 0 on success.
1178 */
1179void
e315cd28 1180qla24xx_reset_chip(scsi_qla_host_t *vha)
88c26663 1181{
e315cd28 1182 struct qla_hw_data *ha = vha->hw;
85880801
AV		 1183
1184 if (pci_channel_offline(ha->pdev) &&
1185 ha->flags.pci_channel_io_perm_failure) {
1186 return;
1187 }
1188
fd34f556 1189 ha->isp_ops->disable_intrs(ha);
88c26663 1190
4ea2c9c7
JC		 1191 qla25xx_manipulate_risc_semaphore(vha);
1192
88c26663 1193 /* Perform RISC reset. */
e315cd28 1194 qla24xx_reset_risc(vha);
88c26663
AV		 1195}
1196
1da177e4
LT		 1197/**
1198 * qla2x00_chip_diag() - Test chip for proper operation.
1199 * @ha: HA context
1200 *
1201 * Returns 0 on success.
1202 */
abbd8870 1203int
e315cd28 1204qla2x00_chip_diag(scsi_qla_host_t *vha)
1da177e4
LT		 1205{
1206 int rval;
e315cd28 1207 struct qla_hw_data *ha = vha->hw;
3d71644c 1208 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 1209 unsigned long flags = 0;
1210 uint16_t data;
1211 uint32_t cnt;
1212 uint16_t mb[5];
73208dfd 1213 struct req_que *req = ha->req_q_map[0];
1da177e4
LT		 1214
1215 /* Assume a failed state */
1216 rval = QLA_FUNCTION_FAILED;
1217
7c3df132
SK		 1218 ql_dbg(ql_dbg_init, vha, 0x007b,
1219 "Testing device at %lx.\n", (u_long)&reg->flash_address);
1da177e4
LT		 1220
1221 spin_lock_irqsave(&ha->hardware_lock, flags);
1222
1223 /* Reset ISP chip. */
1224 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1225
1226 /*
1227 * We need to have a delay here since the card will not respond while
1228 * in reset causing an MCA on some architectures.
1229 */
1230 udelay(20);
1231 data = qla2x00_debounce_register(&reg->ctrl_status);
1232 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
1233 udelay(5);
1234 data = RD_REG_WORD(&reg->ctrl_status);
1235 barrier();
1236 }
1237
1238 if (!cnt)
1239 goto chip_diag_failed;
1240
7c3df132
SK		 1241 ql_dbg(ql_dbg_init, vha, 0x007c,
1242 "Reset register cleared by chip reset.\n");
1da177e4
LT		 1243
1244 /* Reset RISC processor. */
1245 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1246 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1247
1248 /* Workaround for QLA2312 PCI parity error */
1249 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1250 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
1251 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
1252 udelay(5);
1253 data = RD_MAILBOX_REG(ha, reg, 0);
fa2a1ce5 1254 barrier();
1da177e4
LT		 1255 }
1256 } else
1257 udelay(10);
1258
1259 if (!cnt)
1260 goto chip_diag_failed;
1261
1262 /* Check product ID of chip */
7c3df132 1263 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
1da177e4
LT		 1264
1265 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
1266 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
1267 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
1268 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
1269 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
1270 mb[3] != PROD_ID_3) {
7c3df132
SK		 1271 ql_log(ql_log_warn, vha, 0x0062,
1272 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
1273 mb[1], mb[2], mb[3]);
1da177e4
LT		 1274
1275 goto chip_diag_failed;
1276 }
1277 ha->product_id[0] = mb[1];
1278 ha->product_id[1] = mb[2];
1279 ha->product_id[2] = mb[3];
1280 ha->product_id[3] = mb[4];
1281
1282 /* Adjust fw RISC transfer size */
73208dfd 1283 if (req->length > 1024)
1da177e4
LT		 1284 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
1285 else
1286 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
73208dfd 1287 req->length;
1da177e4
LT		 1288
1289 if (IS_QLA2200(ha) &&
1290 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
1291 /* Limit firmware transfer size with a 2200A */
7c3df132 1292 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1da177e4 1293
ea5b6382 1294 ha->device_type |= DT_ISP2200A;
1da177e4
LT		 1295 ha->fw_transfer_size = 128;
1296 }
1297
1298 /* Wrap Incoming Mailboxes Test. */
1299 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1300
7c3df132 1301 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
e315cd28 1302 rval = qla2x00_mbx_reg_test(vha);
7c3df132
SK		 1303 if (rval)
1304 ql_log(ql_log_warn, vha, 0x0080,
1305 "Failed mailbox send register test.\n");
1306 else
1da177e4
LT		 1307 /* Flag a successful rval */
1308 rval = QLA_SUCCESS;
1da177e4
LT		 1309 spin_lock_irqsave(&ha->hardware_lock, flags);
1310
1311chip_diag_failed:
1312 if (rval)
7c3df132
SK		 1313 ql_log(ql_log_info, vha, 0x0081,
1314 "Chip diagnostics **** FAILED ****.\n");
1da177e4
LT		 1315
1316 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1317
1318 return (rval);
1319}
1320
0107109e
AV		 1321/**
1322 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
1323 * @ha: HA context
1324 *
1325 * Returns 0 on success.
1326 */
1327int
e315cd28 1328qla24xx_chip_diag(scsi_qla_host_t *vha)
0107109e
AV		 1329{
1330 int rval;
e315cd28 1331 struct qla_hw_data *ha = vha->hw;
73208dfd 1332 struct req_que *req = ha->req_q_map[0];
0107109e 1333
a9083016
GM		 1334 if (IS_QLA82XX(ha))
1335 return QLA_SUCCESS;
1336
73208dfd 1337 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
0107109e 1338
e315cd28 1339 rval = qla2x00_mbx_reg_test(vha);
0107109e 1340 if (rval) {
7c3df132
SK		 1341 ql_log(ql_log_warn, vha, 0x0082,
1342 "Failed mailbox send register test.\n");
0107109e
AV		 1343 } else {
1344 /* Flag a successful rval */
1345 rval = QLA_SUCCESS;
1346 }
1347
1348 return rval;
1349}
1350
a7a167bf 1351void
e315cd28 1352qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
0107109e 1353{
a7a167bf
AV		 1354 int rval;
1355 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
73208dfd 1356 eft_size, fce_size, mq_size;
df613b96
AV		 1357 dma_addr_t tc_dma;
1358 void *tc;
e315cd28 1359 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 1360 struct req_que *req = ha->req_q_map[0];
1361 struct rsp_que *rsp = ha->rsp_q_map[0];
a7a167bf
AV		 1362
1363 if (ha->fw_dump) {
7c3df132
SK		 1364 ql_dbg(ql_dbg_init, vha, 0x00bd,
1365 "Firmware dump already allocated.\n");
a7a167bf
AV		 1366 return;
1367 }
d4e3e04d 1368
0107109e 1369 ha->fw_dumped = 0;
73208dfd 1370 fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
d4e3e04d 1371 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
a7a167bf 1372 fixed_size = sizeof(struct qla2100_fw_dump);
d4e3e04d 1373 } else if (IS_QLA23XX(ha)) {
a7a167bf
AV		 1374 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
1375 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
1376 sizeof(uint16_t);
e428924c 1377 } else if (IS_FWI2_CAPABLE(ha)) {
6246b8a1
GM		 1378 if (IS_QLA83XX(ha))
1379 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
1380 else if (IS_QLA81XX(ha))
3a03eb79
AV		 1381 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
1382 else if (IS_QLA25XX(ha))
1383 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
1384 else
1385 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
a7a167bf
AV		 1386 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
1387 sizeof(uint32_t);
050c9bb1 1388 if (ha->mqenable) {
6246b8a1
GM		 1389 if (!IS_QLA83XX(ha))
1390 mq_size = sizeof(struct qla2xxx_mq_chain);
050c9bb1
GM		 1391 /*
1392 * Allocate maximum buffer size for all queues.
1393 * Resizing must be done at end-of-dump processing.
1394 */
1395 mq_size += ha->max_req_queues *
1396 (req->length * sizeof(request_t));
1397 mq_size += ha->max_rsp_queues *
1398 (rsp->length * sizeof(response_t));
1399 }
00876ae8 1400 if (ha->tgt.atio_ring)
2d70c103 1401 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
df613b96 1402 /* Allocate memory for Fibre Channel Event Buffer. */
6246b8a1 1403 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha))
436a7b11 1404 goto try_eft;
df613b96
AV		 1405
1406 tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
1407 GFP_KERNEL);
1408 if (!tc) {
7c3df132
SK		 1409 ql_log(ql_log_warn, vha, 0x00be,
1410 "Unable to allocate (%d KB) for FCE.\n",
1411 FCE_SIZE / 1024);
17d98630 1412 goto try_eft;
df613b96
AV		 1413 }
1414
1415 memset(tc, 0, FCE_SIZE);
e315cd28 1416 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
df613b96
AV		 1417 ha->fce_mb, &ha->fce_bufs);
1418 if (rval) {
7c3df132
SK		 1419 ql_log(ql_log_warn, vha, 0x00bf,
1420 "Unable to initialize FCE (%d).\n", rval);
df613b96
AV		 1421 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
1422 tc_dma);
1423 ha->flags.fce_enabled = 0;
17d98630 1424 goto try_eft;
df613b96 1425 }
cfb0919c 1426 ql_dbg(ql_dbg_init, vha, 0x00c0,
7c3df132 1427 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
df613b96 1428
7d9dade3 1429 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
df613b96
AV		 1430 ha->flags.fce_enabled = 1;
1431 ha->fce_dma = tc_dma;
1432 ha->fce = tc;
436a7b11
AV		 1433try_eft:
1434 /* Allocate memory for Extended Trace Buffer. */
1435 tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
1436 GFP_KERNEL);
1437 if (!tc) {
7c3df132
SK		 1438 ql_log(ql_log_warn, vha, 0x00c1,
1439 "Unable to allocate (%d KB) for EFT.\n",
1440 EFT_SIZE / 1024);
436a7b11
AV		 1441 goto cont_alloc;
1442 }
1443
1444 memset(tc, 0, EFT_SIZE);
e315cd28 1445 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
436a7b11 1446 if (rval) {
7c3df132
SK		 1447 ql_log(ql_log_warn, vha, 0x00c2,
1448 "Unable to initialize EFT (%d).\n", rval);
436a7b11
AV		 1449 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
1450 tc_dma);
1451 goto cont_alloc;
1452 }
cfb0919c 1453 ql_dbg(ql_dbg_init, vha, 0x00c3,
7c3df132 1454 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
436a7b11
AV		 1455
1456 eft_size = EFT_SIZE;
1457 ha->eft_dma = tc_dma;
1458 ha->eft = tc;
d4e3e04d 1459 }
a7a167bf 1460cont_alloc:
73208dfd
AC		 1461 req_q_size = req->length * sizeof(request_t);
1462 rsp_q_size = rsp->length * sizeof(response_t);
a7a167bf
AV		 1463
1464 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
2afa19a9 1465 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
bb99de67
AV		 1466 ha->chain_offset = dump_size;
1467 dump_size += mq_size + fce_size;
d4e3e04d
AV		 1468
1469 ha->fw_dump = vmalloc(dump_size);
a7a167bf 1470 if (!ha->fw_dump) {
7c3df132
SK		 1471 ql_log(ql_log_warn, vha, 0x00c4,
1472 "Unable to allocate (%d KB) for firmware dump.\n",
1473 dump_size / 1024);
a7a167bf 1474
e30d1756
MI		 1475 if (ha->fce) {
1476 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
1477 ha->fce_dma);
1478 ha->fce = NULL;
1479 ha->fce_dma = 0;
1480 }
1481
a7a167bf
AV		 1482 if (ha->eft) {
1483 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
1484 ha->eft_dma);
1485 ha->eft = NULL;
1486 ha->eft_dma = 0;
1487 }
1488 return;
1489 }
cfb0919c 1490 ql_dbg(ql_dbg_init, vha, 0x00c5,
7c3df132 1491 "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
a7a167bf
AV		 1492
1493 ha->fw_dump_len = dump_size;
1494 ha->fw_dump->signature[0] = 'Q';
1495 ha->fw_dump->signature[1] = 'L';
1496 ha->fw_dump->signature[2] = 'G';
1497 ha->fw_dump->signature[3] = 'C';
1498 ha->fw_dump->version = __constant_htonl(1);
1499
1500 ha->fw_dump->fixed_size = htonl(fixed_size);
1501 ha->fw_dump->mem_size = htonl(mem_size);
1502 ha->fw_dump->req_q_size = htonl(req_q_size);
1503 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
1504
1505 ha->fw_dump->eft_size = htonl(eft_size);
1506 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
1507 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
1508
1509 ha->fw_dump->header_size =
1510 htonl(offsetof(struct qla2xxx_fw_dump, isp));
0107109e
AV		 1511}
1512
18e7555a
AV		 1513static int
1514qla81xx_mpi_sync(scsi_qla_host_t *vha)
1515{
1516#define MPS_MASK 0xe0
1517 int rval;
1518 uint16_t dc;
1519 uint32_t dw;
18e7555a
AV		 1520
1521 if (!IS_QLA81XX(vha->hw))
1522 return QLA_SUCCESS;
1523
1524 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
1525 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1526 ql_log(ql_log_warn, vha, 0x0105,
1527 "Unable to acquire semaphore.\n");
18e7555a
AV		 1528 goto done;
1529 }
1530
1531 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
1532 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
1533 if (rval != QLA_SUCCESS) {
7c3df132 1534 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
18e7555a
AV		 1535 goto done_release;
1536 }
1537
1538 dc &= MPS_MASK;
1539 if (dc == (dw & MPS_MASK))
1540 goto done_release;
1541
1542 dw &= ~MPS_MASK;
1543 dw |= dc;
1544 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
1545 if (rval != QLA_SUCCESS) {
7c3df132 1546 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
18e7555a
AV		 1547 }
1548
1549done_release:
1550 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
1551 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1552 ql_log(ql_log_warn, vha, 0x006d,
1553 "Unable to release semaphore.\n");
18e7555a
AV		 1554 }
1555
1556done:
1557 return rval;
1558}
1559
8d93f550
CD		 1560int
1561qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
1562{
1563 /* Don't try to reallocate the array */
1564 if (req->outstanding_cmds)
1565 return QLA_SUCCESS;
1566
1567 if (!IS_FWI2_CAPABLE(ha) || (ha->mqiobase &&
1568 (ql2xmultique_tag || ql2xmaxqueues > 1)))
1569 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
1570 else {
1571 if (ha->fw_xcb_count <= ha->fw_iocb_count)
1572 req->num_outstanding_cmds = ha->fw_xcb_count;
1573 else
1574 req->num_outstanding_cmds = ha->fw_iocb_count;
1575 }
1576
1577 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1578 req->num_outstanding_cmds, GFP_KERNEL);
1579
1580 if (!req->outstanding_cmds) {
1581 /*
1582 * Try to allocate a minimal size just so we can get through
1583 * initialization.
1584 */
1585 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
1586 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1587 req->num_outstanding_cmds, GFP_KERNEL);
1588
1589 if (!req->outstanding_cmds) {
1590 ql_log(ql_log_fatal, NULL, 0x0126,
1591 "Failed to allocate memory for "
1592 "outstanding_cmds for req_que %p.\n", req);
1593 req->num_outstanding_cmds = 0;
1594 return QLA_FUNCTION_FAILED;
1595 }
1596 }
1597
1598 return QLA_SUCCESS;
1599}
1600
1da177e4
LT		 1601/**
1602 * qla2x00_setup_chip() - Load and start RISC firmware.
1603 * @ha: HA context
1604 *
1605 * Returns 0 on success.
1606 */
1607static int
e315cd28 1608qla2x00_setup_chip(scsi_qla_host_t *vha)
1da177e4 1609{
0107109e
AV		 1610 int rval;
1611 uint32_t srisc_address = 0;
e315cd28 1612 struct qla_hw_data *ha = vha->hw;
3db0652e
AV		 1613 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1614 unsigned long flags;
dda772e8 1615 uint16_t fw_major_version;
3db0652e 1616
a9083016
GM		 1617 if (IS_QLA82XX(ha)) {
1618 rval = ha->isp_ops->load_risc(vha, &srisc_address);
14e303d9
AV		 1619 if (rval == QLA_SUCCESS) {
1620 qla2x00_stop_firmware(vha);
a9083016 1621 goto enable_82xx_npiv;
14e303d9 1622 } else
b963752f 1623 goto failed;
a9083016
GM		 1624 }
1625
3db0652e
AV		 1626 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1627 /* Disable SRAM, Instruction RAM and GP RAM parity. */
1628 spin_lock_irqsave(&ha->hardware_lock, flags);
1629 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
1630 RD_REG_WORD(&reg->hccr);
1631 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1632 }
1da177e4 1633
18e7555a
AV		 1634 qla81xx_mpi_sync(vha);
1635
1da177e4 1636 /* Load firmware sequences */
e315cd28 1637 rval = ha->isp_ops->load_risc(vha, &srisc_address);
0107109e 1638 if (rval == QLA_SUCCESS) {
7c3df132
SK		 1639 ql_dbg(ql_dbg_init, vha, 0x00c9,
1640 "Verifying Checksum of loaded RISC code.\n");
1da177e4 1641
e315cd28 1642 rval = qla2x00_verify_checksum(vha, srisc_address);
1da177e4
LT		 1643 if (rval == QLA_SUCCESS) {
1644 /* Start firmware execution. */
7c3df132
SK		 1645 ql_dbg(ql_dbg_init, vha, 0x00ca,
1646 "Starting firmware.\n");
1da177e4 1647
e315cd28 1648 rval = qla2x00_execute_fw(vha, srisc_address);
1da177e4 1649 /* Retrieve firmware information. */
dda772e8 1650 if (rval == QLA_SUCCESS) {
a9083016 1651enable_82xx_npiv:
dda772e8 1652 fw_major_version = ha->fw_major_version;
3173167f
GM		 1653 if (IS_QLA82XX(ha))
1654 qla82xx_check_md_needed(vha);
6246b8a1
GM		 1655 else
1656 rval = qla2x00_get_fw_version(vha);
ca9e9c3e
AV		 1657 if (rval != QLA_SUCCESS)
1658 goto failed;
2c3dfe3f 1659 ha->flags.npiv_supported = 0;
e315cd28 1660 if (IS_QLA2XXX_MIDTYPE(ha) &&
946fb891 1661 (ha->fw_attributes & BIT_2)) {
2c3dfe3f 1662 ha->flags.npiv_supported = 1;
4d0ea247
SJ		 1663 if ((!ha->max_npiv_vports) ||
1664 ((ha->max_npiv_vports + 1) %
eb66dc60 1665 MIN_MULTI_ID_FABRIC))
4d0ea247 1666 ha->max_npiv_vports =
eb66dc60 1667 MIN_MULTI_ID_FABRIC - 1;
4d0ea247 1668 }
24a08138 1669 qla2x00_get_resource_cnts(vha, NULL,
8d93f550 1670 &ha->fw_xcb_count, NULL, &ha->fw_iocb_count,
f3a0a77e 1671 &ha->max_npiv_vports, NULL);
d743de66 1672
8d93f550
CD		 1673 /*
1674 * Allocate the array of outstanding commands
1675 * now that we know the firmware resources.
1676 */
1677 rval = qla2x00_alloc_outstanding_cmds(ha,
1678 vha->req);
1679 if (rval != QLA_SUCCESS)
1680 goto failed;
1681
be5ea3cf
SK		 1682 if (!fw_major_version && ql2xallocfwdump
1683 && !IS_QLA82XX(ha))
08de2844 1684 qla2x00_alloc_fw_dump(vha);
1da177e4
LT		 1685 }
1686 } else {
7c3df132
SK		 1687 ql_log(ql_log_fatal, vha, 0x00cd,
1688 "ISP Firmware failed checksum.\n");
1689 goto failed;
1da177e4 1690 }
c74d88a4
AV		 1691 } else
1692 goto failed;
1da177e4 1693
3db0652e
AV		 1694 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1695 /* Enable proper parity. */
1696 spin_lock_irqsave(&ha->hardware_lock, flags);
1697 if (IS_QLA2300(ha))
1698 /* SRAM parity */
1699 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
1700 else
1701 /* SRAM, Instruction RAM and GP RAM parity */
1702 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
1703 RD_REG_WORD(&reg->hccr);
1704 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1705 }
1706
6246b8a1
GM		 1707 if (IS_QLA83XX(ha))
1708 goto skip_fac_check;
1709
1d2874de
JC		 1710 if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1711 uint32_t size;
1712
1713 rval = qla81xx_fac_get_sector_size(vha, &size);
1714 if (rval == QLA_SUCCESS) {
1715 ha->flags.fac_supported = 1;
1716 ha->fdt_block_size = size << 2;
1717 } else {
7c3df132 1718 ql_log(ql_log_warn, vha, 0x00ce,
1d2874de
JC		 1719 "Unsupported FAC firmware (%d.%02d.%02d).\n",
1720 ha->fw_major_version, ha->fw_minor_version,
1721 ha->fw_subminor_version);
6246b8a1
GM		 1722skip_fac_check:
1723 if (IS_QLA83XX(ha)) {
1724 ha->flags.fac_supported = 0;
1725 rval = QLA_SUCCESS;
1726 }
1d2874de
JC		 1727 }
1728 }
ca9e9c3e 1729failed:
1da177e4 1730 if (rval) {
7c3df132
SK		 1731 ql_log(ql_log_fatal, vha, 0x00cf,
1732 "Setup chip ****FAILED****.\n");
1da177e4
LT		 1733 }
1734
1735 return (rval);
1736}
1737
1738/**
1739 * qla2x00_init_response_q_entries() - Initializes response queue entries.
1740 * @ha: HA context
1741 *
1742 * Beginning of request ring has initialization control block already built
1743 * by nvram config routine.
1744 *
1745 * Returns 0 on success.
1746 */
73208dfd
AC		 1747void
1748qla2x00_init_response_q_entries(struct rsp_que *rsp)
1da177e4
LT		 1749{
1750 uint16_t cnt;
1751 response_t *pkt;
1752
2afa19a9
AC		 1753 rsp->ring_ptr = rsp->ring;
1754 rsp->ring_index = 0;
1755 rsp->status_srb = NULL;
e315cd28
AC		 1756 pkt = rsp->ring_ptr;
1757 for (cnt = 0; cnt < rsp->length; cnt++) {
1da177e4
LT		 1758 pkt->signature = RESPONSE_PROCESSED;
1759 pkt++;
1760 }
1da177e4
LT		 1761}
1762
1763/**
1764 * qla2x00_update_fw_options() - Read and process firmware options.
1765 * @ha: HA context
1766 *
1767 * Returns 0 on success.
1768 */
abbd8870 1769void
e315cd28 1770qla2x00_update_fw_options(scsi_qla_host_t *vha)
1da177e4
LT		 1771{
1772 uint16_t swing, emphasis, tx_sens, rx_sens;
e315cd28 1773 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 1774
1775 memset(ha->fw_options, 0, sizeof(ha->fw_options));
e315cd28 1776 qla2x00_get_fw_options(vha, ha->fw_options);
1da177e4
LT		 1777
1778 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1779 return;
1780
1781 /* Serial Link options. */
7c3df132
SK		 1782 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
1783 "Serial link options.\n");
1784 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
1785 (uint8_t *)&ha->fw_seriallink_options,
1786 sizeof(ha->fw_seriallink_options));
1da177e4
LT		 1787
1788 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1789 if (ha->fw_seriallink_options[3] & BIT_2) {
1790 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
1791
1792 /* 1G settings */
1793 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
1794 emphasis = (ha->fw_seriallink_options[2] &
1795 (BIT_4 | BIT_3)) >> 3;
1796 tx_sens = ha->fw_seriallink_options[0] &
fa2a1ce5 1797 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1798 rx_sens = (ha->fw_seriallink_options[0] &
1799 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1800 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
1801 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1802 if (rx_sens == 0x0)
1803 rx_sens = 0x3;
1804 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
1805 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1806 ha->fw_options[10] |= BIT_5 |
1807 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1808 (tx_sens & (BIT_1 | BIT_0));
1809
1810 /* 2G settings */
1811 swing = (ha->fw_seriallink_options[2] &
1812 (BIT_7 | BIT_6 | BIT_5)) >> 5;
1813 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
1814 tx_sens = ha->fw_seriallink_options[1] &
fa2a1ce5 1815 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1816 rx_sens = (ha->fw_seriallink_options[1] &
1817 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1818 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
1819 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1820 if (rx_sens == 0x0)
1821 rx_sens = 0x3;
1822 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
1823 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1824 ha->fw_options[11] |= BIT_5 |
1825 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1826 (tx_sens & (BIT_1 | BIT_0));
1827 }
1828
1829 /* FCP2 options. */
1830 /* Return command IOCBs without waiting for an ABTS to complete. */
1831 ha->fw_options[3] |= BIT_13;
1832
1833 /* LED scheme. */
1834 if (ha->flags.enable_led_scheme)
1835 ha->fw_options[2] |= BIT_12;
1836
48c02fde 1837 /* Detect ISP6312. */
1838 if (IS_QLA6312(ha))
1839 ha->fw_options[2] |= BIT_13;
1840
1da177e4 1841 /* Update firmware options. */
e315cd28 1842 qla2x00_set_fw_options(vha, ha->fw_options);
1da177e4
LT		 1843}
1844
0107109e 1845void
e315cd28 1846qla24xx_update_fw_options(scsi_qla_host_t *vha)
0107109e
AV		 1847{
1848 int rval;
e315cd28 1849 struct qla_hw_data *ha = vha->hw;
0107109e 1850
a9083016
GM		 1851 if (IS_QLA82XX(ha))
1852 return;
1853
0107109e 1854 /* Update Serial Link options. */
f94097ed 1855 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
0107109e
AV		 1856 return;
1857
e315cd28 1858 rval = qla2x00_set_serdes_params(vha,
f94097ed 1859 le16_to_cpu(ha->fw_seriallink_options24[1]),
1860 le16_to_cpu(ha->fw_seriallink_options24[2]),
1861 le16_to_cpu(ha->fw_seriallink_options24[3]));
0107109e 1862 if (rval != QLA_SUCCESS) {
7c3df132 1863 ql_log(ql_log_warn, vha, 0x0104,
0107109e
AV		 1864 "Unable to update Serial Link options (%x).\n", rval);
1865 }
1866}
1867
abbd8870 1868void
e315cd28 1869qla2x00_config_rings(struct scsi_qla_host *vha)
abbd8870 1870{
e315cd28 1871 struct qla_hw_data *ha = vha->hw;
3d71644c 1872 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
73208dfd
AC		 1873 struct req_que *req = ha->req_q_map[0];
1874 struct rsp_que *rsp = ha->rsp_q_map[0];
abbd8870
AV		 1875
1876 /* Setup ring parameters in initialization control block. */
1877 ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0);
1878 ha->init_cb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 1879 ha->init_cb->request_q_length = cpu_to_le16(req->length);
1880 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
1881 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1882 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1883 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1884 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
abbd8870
AV		 1885
1886 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
1887 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
1888 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
1889 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
1890 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
1891}
1892
0107109e 1893void
e315cd28 1894qla24xx_config_rings(struct scsi_qla_host *vha)
0107109e 1895{
e315cd28 1896 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 1897 device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0);
1898 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
1899 struct qla_msix_entry *msix;
0107109e 1900 struct init_cb_24xx *icb;
73208dfd
AC		 1901 uint16_t rid = 0;
1902 struct req_que *req = ha->req_q_map[0];
1903 struct rsp_que *rsp = ha->rsp_q_map[0];
0107109e 1904
6246b8a1 1905 /* Setup ring parameters in initialization control block. */
0107109e
AV		 1906 icb = (struct init_cb_24xx *)ha->init_cb;
1907 icb->request_q_outpointer = __constant_cpu_to_le16(0);
1908 icb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 1909 icb->request_q_length = cpu_to_le16(req->length);
1910 icb->response_q_length = cpu_to_le16(rsp->length);
1911 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1912 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1913 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1914 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
0107109e 1915
2d70c103
NB		 1916 /* Setup ATIO queue dma pointers for target mode */
1917 icb->atio_q_inpointer = __constant_cpu_to_le16(0);
1918 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
1919 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
1920 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
1921
6246b8a1 1922 if (ha->mqenable || IS_QLA83XX(ha)) {
73208dfd
AC		 1923 icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS);
1924 icb->rid = __constant_cpu_to_le16(rid);
1925 if (ha->flags.msix_enabled) {
1926 msix = &ha->msix_entries[1];
7c3df132
SK		 1927 ql_dbg(ql_dbg_init, vha, 0x00fd,
1928 "Registering vector 0x%x for base que.\n",
1929 msix->entry);
73208dfd
AC		 1930 icb->msix = cpu_to_le16(msix->entry);
1931 }
1932 /* Use alternate PCI bus number */
1933 if (MSB(rid))
1934 icb->firmware_options_2 |=
1935 __constant_cpu_to_le32(BIT_19);
1936 /* Use alternate PCI devfn */
1937 if (LSB(rid))
1938 icb->firmware_options_2 |=
1939 __constant_cpu_to_le32(BIT_18);
1940
3155754a 1941 /* Use Disable MSIX Handshake mode for capable adapters */
6246b8a1
GM		 1942 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
1943 (ha->flags.msix_enabled)) {
3155754a
AC		 1944 icb->firmware_options_2 &=
1945 __constant_cpu_to_le32(~BIT_22);
1946 ha->flags.disable_msix_handshake = 1;
7c3df132
SK		 1947 ql_dbg(ql_dbg_init, vha, 0x00fe,
1948 "MSIX Handshake Disable Mode turned on.\n");
3155754a
AC		 1949 } else {
1950 icb->firmware_options_2 |=
1951 __constant_cpu_to_le32(BIT_22);
1952 }
73208dfd 1953 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_23);
73208dfd
AC		 1954
1955 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
1956 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
1957 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
1958 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
1959 } else {
1960 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
1961 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
1962 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
1963 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
1964 }
aa230bc5 1965 qlt_24xx_config_rings(vha);
2d70c103 1966
73208dfd
AC		 1967 /* PCI posting */
1968 RD_REG_DWORD(&ioreg->hccr);
0107109e
AV		 1969}
1970
1da177e4
LT		 1971/**
1972 * qla2x00_init_rings() - Initializes firmware.
1973 * @ha: HA context
1974 *
1975 * Beginning of request ring has initialization control block already built
1976 * by nvram config routine.
1977 *
1978 * Returns 0 on success.
1979 */
1980static int
e315cd28 1981qla2x00_init_rings(scsi_qla_host_t *vha)
1da177e4
LT		 1982{
1983 int rval;
1984 unsigned long flags = 0;
29bdccbe 1985 int cnt, que;
e315cd28 1986 struct qla_hw_data *ha = vha->hw;
29bdccbe
AC		 1987 struct req_que *req;
1988 struct rsp_que *rsp;
2c3dfe3f
SJ		 1989 struct mid_init_cb_24xx *mid_init_cb =
1990 (struct mid_init_cb_24xx *) ha->init_cb;
1da177e4
LT		 1991
1992 spin_lock_irqsave(&ha->hardware_lock, flags);
1993
1994 /* Clear outstanding commands array. */
2afa19a9 1995 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe
AC		 1996 req = ha->req_q_map[que];
1997 if (!req)
1998 continue;
8d93f550 1999 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
29bdccbe 2000 req->outstanding_cmds[cnt] = NULL;
1da177e4 2001
2afa19a9 2002 req->current_outstanding_cmd = 1;
1da177e4 2003
29bdccbe
AC		 2004 /* Initialize firmware. */
2005 req->ring_ptr = req->ring;
2006 req->ring_index = 0;
2007 req->cnt = req->length;
2008 }
1da177e4 2009
2afa19a9 2010 for (que = 0; que < ha->max_rsp_queues; que++) {
29bdccbe
AC		 2011 rsp = ha->rsp_q_map[que];
2012 if (!rsp)
2013 continue;
29bdccbe
AC		 2014 /* Initialize response queue entries */
2015 qla2x00_init_response_q_entries(rsp);
2016 }
1da177e4 2017
2d70c103
NB		 2018 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
2019 ha->tgt.atio_ring_index = 0;
2020 /* Initialize ATIO queue entries */
2021 qlt_init_atio_q_entries(vha);
2022
e315cd28 2023 ha->isp_ops->config_rings(vha);
1da177e4
LT		 2024
2025 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2026
2027 /* Update any ISP specific firmware options before initialization. */
e315cd28 2028 ha->isp_ops->update_fw_options(vha);
1da177e4 2029
7c3df132 2030 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
2c3dfe3f 2031
605aa2bc 2032 if (ha->flags.npiv_supported) {
45980cc2 2033 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
605aa2bc 2034 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
c48339de 2035 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
605aa2bc
LC		 2036 }
2037
24a08138
AV		 2038 if (IS_FWI2_CAPABLE(ha)) {
2039 mid_init_cb->options = __constant_cpu_to_le16(BIT_1);
2040 mid_init_cb->init_cb.execution_throttle =
2041 cpu_to_le16(ha->fw_xcb_count);
2042 }
2c3dfe3f 2043
e315cd28 2044 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
1da177e4 2045 if (rval) {
7c3df132
SK		 2046 ql_log(ql_log_fatal, vha, 0x00d2,
2047 "Init Firmware **** FAILED ****.\n");
1da177e4 2048 } else {
7c3df132
SK		 2049 ql_dbg(ql_dbg_init, vha, 0x00d3,
2050 "Init Firmware -- success.\n");
1da177e4
LT		 2051 }
2052
2053 return (rval);
2054}
2055
2056/**
2057 * qla2x00_fw_ready() - Waits for firmware ready.
2058 * @ha: HA context
2059 *
2060 * Returns 0 on success.
2061 */
2062static int
e315cd28 2063qla2x00_fw_ready(scsi_qla_host_t *vha)
1da177e4
LT		 2064{
2065 int rval;
4d4df193 2066 unsigned long wtime, mtime, cs84xx_time;
1da177e4
LT		 2067 uint16_t min_wait; /* Minimum wait time if loop is down */
2068 uint16_t wait_time; /* Wait time if loop is coming ready */
656e8912 2069 uint16_t state[5];
e315cd28 2070 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2071
2072 rval = QLA_SUCCESS;
2073
2074 /* 20 seconds for loop down. */
fa2a1ce5 2075 min_wait = 20;
1da177e4
LT		 2076
2077 /*
2078 * Firmware should take at most one RATOV to login, plus 5 seconds for
2079 * our own processing.
2080 */
2081 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
2082 wait_time = min_wait;
2083 }
2084
2085 /* Min wait time if loop down */
2086 mtime = jiffies + (min_wait * HZ);
2087
2088 /* wait time before firmware ready */
2089 wtime = jiffies + (wait_time * HZ);
2090
2091 /* Wait for ISP to finish LIP */
e315cd28 2092 if (!vha->flags.init_done)
7c3df132
SK		 2093 ql_log(ql_log_info, vha, 0x801e,
2094 "Waiting for LIP to complete.\n");
1da177e4
LT		 2095
2096 do {
5b939038 2097 memset(state, -1, sizeof(state));
e315cd28 2098 rval = qla2x00_get_firmware_state(vha, state);
1da177e4 2099 if (rval == QLA_SUCCESS) {
4d4df193 2100 if (state[0] < FSTATE_LOSS_OF_SYNC) {
e315cd28 2101 vha->device_flags &= ~DFLG_NO_CABLE;
1da177e4 2102 }
4d4df193 2103 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
7c3df132
SK		 2104 ql_dbg(ql_dbg_taskm, vha, 0x801f,
2105 "fw_state=%x 84xx=%x.\n", state[0],
2106 state[2]);
4d4df193
HK		 2107 if ((state[2] & FSTATE_LOGGED_IN) &&
2108 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
7c3df132
SK		 2109 ql_dbg(ql_dbg_taskm, vha, 0x8028,
2110 "Sending verify iocb.\n");
4d4df193
HK		 2111
2112 cs84xx_time = jiffies;
e315cd28 2113 rval = qla84xx_init_chip(vha);
7c3df132
SK		 2114 if (rval != QLA_SUCCESS) {
2115 ql_log(ql_log_warn,
cfb0919c 2116 vha, 0x8007,
7c3df132 2117 "Init chip failed.\n");
4d4df193 2118 break;
7c3df132 2119 }
4d4df193
HK		 2120
2121 /* Add time taken to initialize. */
2122 cs84xx_time = jiffies - cs84xx_time;
2123 wtime += cs84xx_time;
2124 mtime += cs84xx_time;
cfb0919c 2125 ql_dbg(ql_dbg_taskm, vha, 0x8008,
7c3df132
SK		 2126 "Increasing wait time by %ld. "
2127 "New time %ld.\n", cs84xx_time,
2128 wtime);
4d4df193
HK		 2129 }
2130 } else if (state[0] == FSTATE_READY) {
7c3df132
SK		 2131 ql_dbg(ql_dbg_taskm, vha, 0x8037,
2132 "F/W Ready - OK.\n");
1da177e4 2133
e315cd28 2134 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1da177e4
LT		 2135 &ha->login_timeout, &ha->r_a_tov);
2136
2137 rval = QLA_SUCCESS;
2138 break;
2139 }
2140
2141 rval = QLA_FUNCTION_FAILED;
2142
e315cd28 2143 if (atomic_read(&vha->loop_down_timer) &&
4d4df193 2144 state[0] != FSTATE_READY) {
1da177e4 2145 /* Loop down. Timeout on min_wait for states
fa2a1ce5
AV		 2146 * other than Wait for Login.
2147 */
1da177e4 2148 if (time_after_eq(jiffies, mtime)) {
7c3df132 2149 ql_log(ql_log_info, vha, 0x8038,
1da177e4
LT		 2150 "Cable is unplugged...\n");
2151
e315cd28 2152 vha->device_flags |= DFLG_NO_CABLE;
1da177e4
LT		 2153 break;
2154 }
2155 }
2156 } else {
2157 /* Mailbox cmd failed. Timeout on min_wait. */
cdbb0a4f 2158 if (time_after_eq(jiffies, mtime) ||
7190575f 2159 ha->flags.isp82xx_fw_hung)
1da177e4
LT		 2160 break;
2161 }
2162
2163 if (time_after_eq(jiffies, wtime))
2164 break;
2165
2166 /* Delay for a while */
2167 msleep(500);
1da177e4
LT		 2168 } while (1);
2169
7c3df132
SK		 2170 ql_dbg(ql_dbg_taskm, vha, 0x803a,
2171 "fw_state=%x (%x, %x, %x, %x) " "curr time=%lx.\n", state[0],
2172 state[1], state[2], state[3], state[4], jiffies);
1da177e4 2173
cfb0919c 2174 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132
SK		 2175 ql_log(ql_log_warn, vha, 0x803b,
2176 "Firmware ready **** FAILED ****.\n");
1da177e4
LT		 2177 }
2178
2179 return (rval);
2180}
2181
2182/*
2183* qla2x00_configure_hba
2184* Setup adapter context.
2185*
2186* Input:
2187* ha = adapter state pointer.
2188*
2189* Returns:
2190* 0 = success
2191*
2192* Context:
2193* Kernel context.
2194*/
2195static int
e315cd28 2196qla2x00_configure_hba(scsi_qla_host_t *vha)
1da177e4
LT		 2197{
2198 int rval;
2199 uint16_t loop_id;
2200 uint16_t topo;
2c3dfe3f 2201 uint16_t sw_cap;
1da177e4
LT		 2202 uint8_t al_pa;
2203 uint8_t area;
2204 uint8_t domain;
2205 char connect_type[22];
e315cd28 2206 struct qla_hw_data *ha = vha->hw;
f24b5cb8 2207 unsigned long flags;
61e1b269 2208 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 2209
2210 /* Get host addresses. */
e315cd28 2211 rval = qla2x00_get_adapter_id(vha,
2c3dfe3f 2212 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
1da177e4 2213 if (rval != QLA_SUCCESS) {
e315cd28 2214 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
6246b8a1 2215 IS_CNA_CAPABLE(ha) ||
33135aa2 2216 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
7c3df132
SK		 2217 ql_dbg(ql_dbg_disc, vha, 0x2008,
2218 "Loop is in a transition state.\n");
33135aa2 2219 } else {
7c3df132
SK		 2220 ql_log(ql_log_warn, vha, 0x2009,
2221 "Unable to get host loop ID.\n");
61e1b269
JC		 2222 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
2223 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
2224 ql_log(ql_log_warn, vha, 0x1151,
2225 "Doing link init.\n");
2226 if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
2227 return rval;
2228 }
e315cd28 2229 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
33135aa2 2230 }
1da177e4
LT		 2231 return (rval);
2232 }
2233
2234 if (topo == 4) {
7c3df132
SK		 2235 ql_log(ql_log_info, vha, 0x200a,
2236 "Cannot get topology - retrying.\n");
1da177e4
LT		 2237 return (QLA_FUNCTION_FAILED);
2238 }
2239
e315cd28 2240 vha->loop_id = loop_id;
1da177e4
LT		 2241
2242 /* initialize */
2243 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
2244 ha->operating_mode = LOOP;
2c3dfe3f 2245 ha->switch_cap = 0;
1da177e4
LT		 2246
2247 switch (topo) {
2248 case 0:
7c3df132 2249 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
1da177e4
LT		 2250 ha->current_topology = ISP_CFG_NL;
2251 strcpy(connect_type, "(Loop)");
2252 break;
2253
2254 case 1:
7c3df132 2255 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2c3dfe3f 2256 ha->switch_cap = sw_cap;
1da177e4
LT		 2257 ha->current_topology = ISP_CFG_FL;
2258 strcpy(connect_type, "(FL_Port)");
2259 break;
2260
2261 case 2:
7c3df132 2262 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
1da177e4
LT		 2263 ha->operating_mode = P2P;
2264 ha->current_topology = ISP_CFG_N;
2265 strcpy(connect_type, "(N_Port-to-N_Port)");
2266 break;
2267
2268 case 3:
7c3df132 2269 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2c3dfe3f 2270 ha->switch_cap = sw_cap;
1da177e4
LT		 2271 ha->operating_mode = P2P;
2272 ha->current_topology = ISP_CFG_F;
2273 strcpy(connect_type, "(F_Port)");
2274 break;
2275
2276 default:
7c3df132
SK		 2277 ql_dbg(ql_dbg_disc, vha, 0x200f,
2278 "HBA in unknown topology %x, using NL.\n", topo);
1da177e4
LT		 2279 ha->current_topology = ISP_CFG_NL;
2280 strcpy(connect_type, "(Loop)");
2281 break;
2282 }
2283
2284 /* Save Host port and loop ID. */
2285 /* byte order - Big Endian */
e315cd28
AC		 2286 vha->d_id.b.domain = domain;
2287 vha->d_id.b.area = area;
2288 vha->d_id.b.al_pa = al_pa;
1da177e4 2289
f24b5cb8 2290 spin_lock_irqsave(&ha->vport_slock, flags);
2d70c103 2291 qlt_update_vp_map(vha, SET_AL_PA);
f24b5cb8 2292 spin_unlock_irqrestore(&ha->vport_slock, flags);
2d70c103 2293
e315cd28 2294 if (!vha->flags.init_done)
7c3df132
SK		 2295 ql_log(ql_log_info, vha, 0x2010,
2296 "Topology - %s, Host Loop address 0x%x.\n",
e315cd28 2297 connect_type, vha->loop_id);
1da177e4
LT		 2298
2299 if (rval) {
7c3df132
SK		 2300 ql_log(ql_log_warn, vha, 0x2011,
2301 "%s FAILED\n", __func__);
1da177e4 2302 } else {
7c3df132
SK		 2303 ql_dbg(ql_dbg_disc, vha, 0x2012,
2304 "%s success\n", __func__);
1da177e4
LT		 2305 }
2306
2307 return(rval);
2308}
2309
a9083016 2310inline void
e315cd28
AC		 2311qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
2312 char *def)
9bb9fcf2
AV		 2313{
2314 char *st, *en;
2315 uint16_t index;
e315cd28 2316 struct qla_hw_data *ha = vha->hw;
ab671149 2317 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
6246b8a1 2318 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
9bb9fcf2
AV		 2319
2320 if (memcmp(model, BINZERO, len) != 0) {
2321 strncpy(ha->model_number, model, len);
2322 st = en = ha->model_number;
2323 en += len - 1;
2324 while (en > st) {
2325 if (*en != 0x20 && *en != 0x00)
2326 break;
2327 *en-- = '\0';
2328 }
2329
2330 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2331 if (use_tbl &&
2332 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 2333 index < QLA_MODEL_NAMES)
1ee27146
JC		 2334 strncpy(ha->model_desc,
2335 qla2x00_model_name[index * 2 + 1],
2336 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2337 } else {
2338 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2339 if (use_tbl &&
2340 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2
AV		 2341 index < QLA_MODEL_NAMES) {
2342 strcpy(ha->model_number,
2343 qla2x00_model_name[index * 2]);
1ee27146
JC		 2344 strncpy(ha->model_desc,
2345 qla2x00_model_name[index * 2 + 1],
2346 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2347 } else {
2348 strcpy(ha->model_number, def);
2349 }
2350 }
1ee27146 2351 if (IS_FWI2_CAPABLE(ha))
e315cd28 2352 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
1ee27146 2353 sizeof(ha->model_desc));
9bb9fcf2
AV		 2354}
2355
4e08df3f
DM		 2356/* On sparc systems, obtain port and node WWN from firmware
2357 * properties.
2358 */
e315cd28 2359static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4e08df3f
DM		 2360{
2361#ifdef CONFIG_SPARC
e315cd28 2362 struct qla_hw_data *ha = vha->hw;
4e08df3f 2363 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 2364 struct device_node *dp = pci_device_to_OF_node(pdev);
2365 const u8 *val;
4e08df3f
DM		 2366 int len;
2367
2368 val = of_get_property(dp, "port-wwn", &len);
2369 if (val && len >= WWN_SIZE)
2370 memcpy(nv->port_name, val, WWN_SIZE);
2371
2372 val = of_get_property(dp, "node-wwn", &len);
2373 if (val && len >= WWN_SIZE)
2374 memcpy(nv->node_name, val, WWN_SIZE);
2375#endif
2376}
2377
1da177e4
LT		 2378/*
2379* NVRAM configuration for ISP 2xxx
2380*
2381* Input:
2382* ha = adapter block pointer.
2383*
2384* Output:
2385* initialization control block in response_ring
2386* host adapters parameters in host adapter block
2387*
2388* Returns:
2389* 0 = success.
2390*/
abbd8870 2391int
e315cd28 2392qla2x00_nvram_config(scsi_qla_host_t *vha)
1da177e4 2393{
4e08df3f 2394 int rval;
0107109e
AV		 2395 uint8_t chksum = 0;
2396 uint16_t cnt;
2397 uint8_t *dptr1, *dptr2;
e315cd28 2398 struct qla_hw_data *ha = vha->hw;
0107109e 2399 init_cb_t *icb = ha->init_cb;
281afe19
SJ		 2400 nvram_t *nv = ha->nvram;
2401 uint8_t *ptr = ha->nvram;
3d71644c 2402 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2403
4e08df3f
DM		 2404 rval = QLA_SUCCESS;
2405
1da177e4 2406 /* Determine NVRAM starting address. */
0107109e 2407 ha->nvram_size = sizeof(nvram_t);
1da177e4
LT		 2408 ha->nvram_base = 0;
2409 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
2410 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
2411 ha->nvram_base = 0x80;
2412
2413 /* Get NVRAM data and calculate checksum. */
e315cd28 2414 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
0107109e
AV		 2415 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
2416 chksum += *ptr++;
1da177e4 2417
7c3df132
SK		 2418 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
2419 "Contents of NVRAM.\n");
2420 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
2421 (uint8_t *)nv, ha->nvram_size);
1da177e4
LT		 2422
2423 /* Bad NVRAM data, set defaults parameters. */
2424 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
2425 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
2426 /* Reset NVRAM data. */
7c3df132 2427 ql_log(ql_log_warn, vha, 0x0064,
9e336520 2428 "Inconsistent NVRAM "
7c3df132
SK		 2429 "detected: checksum=0x%x id=%c version=0x%x.\n",
2430 chksum, nv->id[0], nv->nvram_version);
2431 ql_log(ql_log_warn, vha, 0x0065,
2432 "Falling back to "
2433 "functioning (yet invalid -- WWPN) defaults.\n");
4e08df3f
DM		 2434
2435 /*
2436 * Set default initialization control block.
2437 */
2438 memset(nv, 0, ha->nvram_size);
2439 nv->parameter_block_version = ICB_VERSION;
2440
2441 if (IS_QLA23XX(ha)) {
2442 nv->firmware_options[0] = BIT_2 | BIT_1;
2443 nv->firmware_options[1] = BIT_7 | BIT_5;
2444 nv->add_firmware_options[0] = BIT_5;
2445 nv->add_firmware_options[1] = BIT_5 | BIT_4;
2446 nv->frame_payload_size = __constant_cpu_to_le16(2048);
2447 nv->special_options[1] = BIT_7;
2448 } else if (IS_QLA2200(ha)) {
2449 nv->firmware_options[0] = BIT_2 | BIT_1;
2450 nv->firmware_options[1] = BIT_7 | BIT_5;
2451 nv->add_firmware_options[0] = BIT_5;
2452 nv->add_firmware_options[1] = BIT_5 | BIT_4;
2453 nv->frame_payload_size = __constant_cpu_to_le16(1024);
2454 } else if (IS_QLA2100(ha)) {
2455 nv->firmware_options[0] = BIT_3 | BIT_1;
2456 nv->firmware_options[1] = BIT_5;
2457 nv->frame_payload_size = __constant_cpu_to_le16(1024);
2458 }
2459
2460 nv->max_iocb_allocation = __constant_cpu_to_le16(256);
2461 nv->execution_throttle = __constant_cpu_to_le16(16);
2462 nv->retry_count = 8;
2463 nv->retry_delay = 1;
2464
2465 nv->port_name[0] = 33;
2466 nv->port_name[3] = 224;
2467 nv->port_name[4] = 139;
2468
e315cd28 2469 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 2470
2471 nv->login_timeout = 4;
2472
2473 /*
2474 * Set default host adapter parameters
2475 */
2476 nv->host_p[1] = BIT_2;
2477 nv->reset_delay = 5;
2478 nv->port_down_retry_count = 8;
2479 nv->max_luns_per_target = __constant_cpu_to_le16(8);
2480 nv->link_down_timeout = 60;
2481
2482 rval = 1;
1da177e4
LT		 2483 }
2484
2485#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
2486 /*
2487 * The SN2 does not provide BIOS emulation which means you can't change
2488 * potentially bogus BIOS settings. Force the use of default settings
2489 * for link rate and frame size. Hope that the rest of the settings
2490 * are valid.
2491 */
2492 if (ia64_platform_is("sn2")) {
2493 nv->frame_payload_size = __constant_cpu_to_le16(2048);
2494 if (IS_QLA23XX(ha))
2495 nv->special_options[1] = BIT_7;
2496 }
2497#endif
2498
2499 /* Reset Initialization control block */
0107109e 2500 memset(icb, 0, ha->init_cb_size);
1da177e4
LT		 2501
2502 /*
2503 * Setup driver NVRAM options.
2504 */
2505 nv->firmware_options[0] |= (BIT_6 | BIT_1);
2506 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
2507 nv->firmware_options[1] |= (BIT_5 | BIT_0);
2508 nv->firmware_options[1] &= ~BIT_4;
2509
2510 if (IS_QLA23XX(ha)) {
2511 nv->firmware_options[0] |= BIT_2;
2512 nv->firmware_options[0] &= ~BIT_3;
2d70c103 2513 nv->special_options[0] &= ~BIT_6;
0107109e 2514 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
1da177e4
LT		 2515
2516 if (IS_QLA2300(ha)) {
2517 if (ha->fb_rev == FPM_2310) {
2518 strcpy(ha->model_number, "QLA2310");
2519 } else {
2520 strcpy(ha->model_number, "QLA2300");
2521 }
2522 } else {
e315cd28 2523 qla2x00_set_model_info(vha, nv->model_number,
9bb9fcf2 2524 sizeof(nv->model_number), "QLA23xx");
1da177e4
LT		 2525 }
2526 } else if (IS_QLA2200(ha)) {
2527 nv->firmware_options[0] |= BIT_2;
2528 /*
2529 * 'Point-to-point preferred, else loop' is not a safe
2530 * connection mode setting.
2531 */
2532 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
2533 (BIT_5 | BIT_4)) {
2534 /* Force 'loop preferred, else point-to-point'. */
2535 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
2536 nv->add_firmware_options[0] |= BIT_5;
2537 }
2538 strcpy(ha->model_number, "QLA22xx");
2539 } else /*if (IS_QLA2100(ha))*/ {
2540 strcpy(ha->model_number, "QLA2100");
2541 }
2542
2543 /*
2544 * Copy over NVRAM RISC parameter block to initialization control block.
2545 */
2546 dptr1 = (uint8_t *)icb;
2547 dptr2 = (uint8_t *)&nv->parameter_block_version;
2548 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
2549 while (cnt--)
2550 *dptr1++ = *dptr2++;
2551
2552 /* Copy 2nd half. */
2553 dptr1 = (uint8_t *)icb->add_firmware_options;
2554 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
2555 while (cnt--)
2556 *dptr1++ = *dptr2++;
2557
5341e868
AV		 2558 /* Use alternate WWN? */
2559 if (nv->host_p[1] & BIT_7) {
2560 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
2561 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
2562 }
2563
1da177e4
LT		 2564 /* Prepare nodename */
2565 if ((icb->firmware_options[1] & BIT_6) == 0) {
2566 /*
2567 * Firmware will apply the following mask if the nodename was
2568 * not provided.
2569 */
2570 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
2571 icb->node_name[0] &= 0xF0;
2572 }
2573
2574 /*
2575 * Set host adapter parameters.
2576 */
3ce8866c
SK		 2577
2578 /*
2579 * BIT_7 in the host-parameters section allows for modification to
2580 * internal driver logging.
2581 */
0181944f 2582 if (nv->host_p[0] & BIT_7)
cfb0919c 2583 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1da177e4
LT		 2584 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
2585 /* Always load RISC code on non ISP2[12]00 chips. */
2586 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
2587 ha->flags.disable_risc_code_load = 0;
2588 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
2589 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
2590 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
06c22bd1 2591 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
d4c760c2 2592 ha->flags.disable_serdes = 0;
1da177e4
LT		 2593
2594 ha->operating_mode =
2595 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
2596
2597 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
2598 sizeof(ha->fw_seriallink_options));
2599
2600 /* save HBA serial number */
2601 ha->serial0 = icb->port_name[5];
2602 ha->serial1 = icb->port_name[6];
2603 ha->serial2 = icb->port_name[7];
e315cd28
AC		 2604 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
2605 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
1da177e4
LT		 2606
2607 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
2608
2609 ha->retry_count = nv->retry_count;
2610
2611 /* Set minimum login_timeout to 4 seconds. */
5b91490e 2612 if (nv->login_timeout != ql2xlogintimeout)
1da177e4
LT		 2613 nv->login_timeout = ql2xlogintimeout;
2614 if (nv->login_timeout < 4)
2615 nv->login_timeout = 4;
2616 ha->login_timeout = nv->login_timeout;
2617 icb->login_timeout = nv->login_timeout;
2618
00a537b8
AV		 2619 /* Set minimum RATOV to 100 tenths of a second. */
2620 ha->r_a_tov = 100;
1da177e4 2621
1da177e4
LT		 2622 ha->loop_reset_delay = nv->reset_delay;
2623
1da177e4
LT		 2624 /* Link Down Timeout = 0:
2625 *
2626 * When Port Down timer expires we will start returning
2627 * I/O's to OS with "DID_NO_CONNECT".
2628 *
2629 * Link Down Timeout != 0:
2630 *
2631 * The driver waits for the link to come up after link down
2632 * before returning I/Os to OS with "DID_NO_CONNECT".
fa2a1ce5 2633 */
1da177e4
LT		 2634 if (nv->link_down_timeout == 0) {
2635 ha->loop_down_abort_time =
354d6b21 2636 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
1da177e4
LT		 2637 } else {
2638 ha->link_down_timeout = nv->link_down_timeout;
2639 ha->loop_down_abort_time =
2640 (LOOP_DOWN_TIME - ha->link_down_timeout);
fa2a1ce5 2641 }
1da177e4 2642
1da177e4
LT		 2643 /*
2644 * Need enough time to try and get the port back.
2645 */
2646 ha->port_down_retry_count = nv->port_down_retry_count;
2647 if (qlport_down_retry)
2648 ha->port_down_retry_count = qlport_down_retry;
2649 /* Set login_retry_count */
2650 ha->login_retry_count = nv->retry_count;
2651 if (ha->port_down_retry_count == nv->port_down_retry_count &&
2652 ha->port_down_retry_count > 3)
2653 ha->login_retry_count = ha->port_down_retry_count;
2654 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
2655 ha->login_retry_count = ha->port_down_retry_count;
2656 if (ql2xloginretrycount)
2657 ha->login_retry_count = ql2xloginretrycount;
2658
1da177e4
LT		 2659 icb->lun_enables = __constant_cpu_to_le16(0);
2660 icb->command_resource_count = 0;
2661 icb->immediate_notify_resource_count = 0;
2662 icb->timeout = __constant_cpu_to_le16(0);
2663
2664 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
2665 /* Enable RIO */
2666 icb->firmware_options[0] &= ~BIT_3;
2667 icb->add_firmware_options[0] &=
2668 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
2669 icb->add_firmware_options[0] |= BIT_2;
2670 icb->response_accumulation_timer = 3;
2671 icb->interrupt_delay_timer = 5;
2672
e315cd28 2673 vha->flags.process_response_queue = 1;
1da177e4 2674 } else {
4fdfefe5 2675 /* Enable ZIO. */
e315cd28 2676 if (!vha->flags.init_done) {
4fdfefe5
AV		 2677 ha->zio_mode = icb->add_firmware_options[0] &
2678 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
2679 ha->zio_timer = icb->interrupt_delay_timer ?
2680 icb->interrupt_delay_timer: 2;
2681 }
1da177e4
LT		 2682 icb->add_firmware_options[0] &=
2683 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
e315cd28 2684 vha->flags.process_response_queue = 0;
4fdfefe5 2685 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d 2686 ha->zio_mode = QLA_ZIO_MODE_6;
2687
7c3df132 2688 ql_log(ql_log_info, vha, 0x0068,
4fdfefe5
AV		 2689 "ZIO mode %d enabled; timer delay (%d us).\n",
2690 ha->zio_mode, ha->zio_timer * 100);
1da177e4 2691
4fdfefe5
AV		 2692 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
2693 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
e315cd28 2694 vha->flags.process_response_queue = 1;
1da177e4
LT		 2695 }
2696 }
2697
4e08df3f 2698 if (rval) {
7c3df132
SK		 2699 ql_log(ql_log_warn, vha, 0x0069,
2700 "NVRAM configuration failed.\n");
4e08df3f
DM		 2701 }
2702 return (rval);
1da177e4
LT		 2703}
2704
19a7b4ae
JSEC		 2705static void
2706qla2x00_rport_del(void *data)
2707{
2708 fc_port_t *fcport = data;
d97994dc 2709 struct fc_rport *rport;
2d70c103 2710 scsi_qla_host_t *vha = fcport->vha;
044d78e1 2711 unsigned long flags;
d97994dc 2712
044d78e1 2713 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
ac280b67 2714 rport = fcport->drport ? fcport->drport: fcport->rport;
d97994dc 2715 fcport->drport = NULL;
044d78e1 2716 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
2d70c103 2717 if (rport) {
d97994dc 2718 fc_remote_port_delete(rport);
2d70c103
NB		 2719 /*
2720 * Release the target mode FC NEXUS in qla_target.c code
2721 * if target mod is enabled.
2722 */
2723 qlt_fc_port_deleted(vha, fcport);
2724 }
19a7b4ae
JSEC		 2725}
2726
1da177e4
LT		 2727/**
2728 * qla2x00_alloc_fcport() - Allocate a generic fcport.
2729 * @ha: HA context
2730 * @flags: allocation flags
2731 *
2732 * Returns a pointer to the allocated fcport, or NULL, if none available.
2733 */
9a069e19 2734fc_port_t *
e315cd28 2735qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
1da177e4
LT		 2736{
2737 fc_port_t *fcport;
2738
bbfbbbc1
MK		 2739 fcport = kzalloc(sizeof(fc_port_t), flags);
2740 if (!fcport)
2741 return NULL;
1da177e4
LT		 2742
2743 /* Setup fcport template structure. */
e315cd28 2744 fcport->vha = vha;
1da177e4
LT		 2745 fcport->port_type = FCT_UNKNOWN;
2746 fcport->loop_id = FC_NO_LOOP_ID;
ec426e10 2747 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
ad3e0eda 2748 fcport->supported_classes = FC_COS_UNSPECIFIED;
1da177e4 2749
bbfbbbc1 2750 return fcport;
1da177e4
LT		 2751}
2752
2753/*
2754 * qla2x00_configure_loop
2755 * Updates Fibre Channel Device Database with what is actually on loop.
2756 *
2757 * Input:
2758 * ha = adapter block pointer.
2759 *
2760 * Returns:
2761 * 0 = success.
2762 * 1 = error.
2763 * 2 = database was full and device was not configured.
2764 */
2765static int
e315cd28 2766qla2x00_configure_loop(scsi_qla_host_t *vha)
1da177e4
LT		 2767{
2768 int rval;
2769 unsigned long flags, save_flags;
e315cd28 2770 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2771 rval = QLA_SUCCESS;
2772
2773 /* Get Initiator ID */
e315cd28
AC		 2774 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
2775 rval = qla2x00_configure_hba(vha);
1da177e4 2776 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2777 ql_dbg(ql_dbg_disc, vha, 0x2013,
2778 "Unable to configure HBA.\n");
1da177e4
LT		 2779 return (rval);
2780 }
2781 }
2782
e315cd28 2783 save_flags = flags = vha->dpc_flags;
7c3df132
SK		 2784 ql_dbg(ql_dbg_disc, vha, 0x2014,
2785 "Configure loop -- dpc flags = 0x%lx.\n", flags);
1da177e4
LT		 2786
2787 /*
2788 * If we have both an RSCN and PORT UPDATE pending then handle them
2789 * both at the same time.
2790 */
e315cd28
AC		 2791 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2792 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
1da177e4 2793
3064ff39
MH		 2794 qla2x00_get_data_rate(vha);
2795
1da177e4
LT		 2796 /* Determine what we need to do */
2797 if (ha->current_topology == ISP_CFG_FL &&
2798 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2799
1da177e4
LT		 2800 set_bit(RSCN_UPDATE, &flags);
2801
2802 } else if (ha->current_topology == ISP_CFG_F &&
2803 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2804
1da177e4
LT		 2805 set_bit(RSCN_UPDATE, &flags);
2806 clear_bit(LOCAL_LOOP_UPDATE, &flags);
21333b48
AV		 2807
2808 } else if (ha->current_topology == ISP_CFG_N) {
2809 clear_bit(RSCN_UPDATE, &flags);
1da177e4 2810
e315cd28 2811 } else if (!vha->flags.online ||
1da177e4
LT		 2812 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
2813
1da177e4
LT		 2814 set_bit(RSCN_UPDATE, &flags);
2815 set_bit(LOCAL_LOOP_UPDATE, &flags);
2816 }
2817
2818 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
7c3df132
SK		 2819 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
2820 ql_dbg(ql_dbg_disc, vha, 0x2015,
2821 "Loop resync needed, failing.\n");
1da177e4 2822 rval = QLA_FUNCTION_FAILED;
642ef983 2823 } else
e315cd28 2824 rval = qla2x00_configure_local_loop(vha);
1da177e4
LT		 2825 }
2826
2827 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
7c3df132
SK		 2828 if (LOOP_TRANSITION(vha)) {
2829 ql_dbg(ql_dbg_disc, vha, 0x201e,
2830 "Needs RSCN update and loop transition.\n");
1da177e4 2831 rval = QLA_FUNCTION_FAILED;
7c3df132 2832 }
e315cd28
AC		 2833 else
2834 rval = qla2x00_configure_fabric(vha);
1da177e4
LT		 2835 }
2836
2837 if (rval == QLA_SUCCESS) {
e315cd28
AC		 2838 if (atomic_read(&vha->loop_down_timer) ||
2839 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4
LT		 2840 rval = QLA_FUNCTION_FAILED;
2841 } else {
e315cd28 2842 atomic_set(&vha->loop_state, LOOP_READY);
7c3df132
SK		 2843 ql_dbg(ql_dbg_disc, vha, 0x2069,
2844 "LOOP READY.\n");
1da177e4
LT		 2845 }
2846 }
2847
2848 if (rval) {
7c3df132
SK		 2849 ql_dbg(ql_dbg_disc, vha, 0x206a,
2850 "%s *** FAILED ***.\n", __func__);
1da177e4 2851 } else {
7c3df132
SK		 2852 ql_dbg(ql_dbg_disc, vha, 0x206b,
2853 "%s: exiting normally.\n", __func__);
1da177e4
LT		 2854 }
2855
cc3ef7bc 2856 /* Restore state if a resync event occurred during processing */
e315cd28 2857 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4 2858 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
e315cd28 2859 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
f4658b6c 2860 if (test_bit(RSCN_UPDATE, &save_flags)) {
e315cd28 2861 set_bit(RSCN_UPDATE, &vha->dpc_flags);
f4658b6c 2862 }
1da177e4
LT		 2863 }
2864
2865 return (rval);
2866}
2867
2868
2869
2870/*
2871 * qla2x00_configure_local_loop
2872 * Updates Fibre Channel Device Database with local loop devices.
2873 *
2874 * Input:
2875 * ha = adapter block pointer.
2876 *
2877 * Returns:
2878 * 0 = success.
2879 */
2880static int
e315cd28 2881qla2x00_configure_local_loop(scsi_qla_host_t *vha)
1da177e4
LT		 2882{
2883 int rval, rval2;
2884 int found_devs;
2885 int found;
2886 fc_port_t *fcport, *new_fcport;
2887
2888 uint16_t index;
2889 uint16_t entries;
2890 char *id_iter;
2891 uint16_t loop_id;
2892 uint8_t domain, area, al_pa;
e315cd28 2893 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2894
2895 found_devs = 0;
2896 new_fcport = NULL;
642ef983 2897 entries = MAX_FIBRE_DEVICES_LOOP;
1da177e4 2898
1da177e4 2899 /* Get list of logged in devices. */
642ef983 2900 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
e315cd28 2901 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
1da177e4
LT		 2902 &entries);
2903 if (rval != QLA_SUCCESS)
2904 goto cleanup_allocation;
2905
7c3df132
SK		 2906 ql_dbg(ql_dbg_disc, vha, 0x2017,
2907 "Entries in ID list (%d).\n", entries);
2908 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
2909 (uint8_t *)ha->gid_list,
2910 entries * sizeof(struct gid_list_info));
1da177e4
LT		 2911
2912 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 2913 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 2914 if (new_fcport == NULL) {
7c3df132
SK		 2915 ql_log(ql_log_warn, vha, 0x2018,
2916 "Memory allocation failed for fcport.\n");
1da177e4
LT		 2917 rval = QLA_MEMORY_ALLOC_FAILED;
2918 goto cleanup_allocation;
2919 }
2920 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
2921
2922 /*
2923 * Mark local devices that were present with FCF_DEVICE_LOST for now.
2924 */
e315cd28 2925 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 2926 if (atomic_read(&fcport->state) == FCS_ONLINE &&
2927 fcport->port_type != FCT_BROADCAST &&
2928 (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
2929
7c3df132
SK		 2930 ql_dbg(ql_dbg_disc, vha, 0x2019,
2931 "Marking port lost loop_id=0x%04x.\n",
2932 fcport->loop_id);
1da177e4 2933
ec426e10 2934 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 2935 }
2936 }
2937
2938 /* Add devices to port list. */
2939 id_iter = (char *)ha->gid_list;
2940 for (index = 0; index < entries; index++) {
2941 domain = ((struct gid_list_info *)id_iter)->domain;
2942 area = ((struct gid_list_info *)id_iter)->area;
2943 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
abbd8870 2944 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1da177e4
LT		 2945 loop_id = (uint16_t)
2946 ((struct gid_list_info *)id_iter)->loop_id_2100;
abbd8870 2947 else
1da177e4
LT		 2948 loop_id = le16_to_cpu(
2949 ((struct gid_list_info *)id_iter)->loop_id);
abbd8870 2950 id_iter += ha->gid_list_info_size;
1da177e4
LT		 2951
2952 /* Bypass reserved domain fields. */
2953 if ((domain & 0xf0) == 0xf0)
2954 continue;
2955
2956 /* Bypass if not same domain and area of adapter. */
f7d289f6 2957 if (area && domain &&
e315cd28 2958 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
1da177e4
LT		 2959 continue;
2960
2961 /* Bypass invalid local loop ID. */
2962 if (loop_id > LAST_LOCAL_LOOP_ID)
2963 continue;
2964
370d550e
AE		 2965 memset(new_fcport, 0, sizeof(fc_port_t));
2966
1da177e4
LT		 2967 /* Fill in member data. */
2968 new_fcport->d_id.b.domain = domain;
2969 new_fcport->d_id.b.area = area;
2970 new_fcport->d_id.b.al_pa = al_pa;
2971 new_fcport->loop_id = loop_id;
e315cd28 2972 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
1da177e4 2973 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 2974 ql_dbg(ql_dbg_disc, vha, 0x201a,
2975 "Failed to retrieve fcport information "
2976 "-- get_port_database=%x, loop_id=0x%04x.\n",
2977 rval2, new_fcport->loop_id);
2978 ql_dbg(ql_dbg_disc, vha, 0x201b,
2979 "Scheduling resync.\n");
e315cd28 2980 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 2981 continue;
2982 }
2983
2984 /* Check for matching device in port list. */
2985 found = 0;
2986 fcport = NULL;
e315cd28 2987 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 2988 if (memcmp(new_fcport->port_name, fcport->port_name,
2989 WWN_SIZE))
2990 continue;
2991
ddb9b126 2992 fcport->flags &= ~FCF_FABRIC_DEVICE;
1da177e4
LT		 2993 fcport->loop_id = new_fcport->loop_id;
2994 fcport->port_type = new_fcport->port_type;
2995 fcport->d_id.b24 = new_fcport->d_id.b24;
2996 memcpy(fcport->node_name, new_fcport->node_name,
2997 WWN_SIZE);
2998
2999 found++;
3000 break;
3001 }
3002
3003 if (!found) {
3004 /* New device, add to fcports list. */
e315cd28 3005 list_add_tail(&new_fcport->list, &vha->vp_fcports);
1da177e4
LT		 3006
3007 /* Allocate a new replacement fcport. */
3008 fcport = new_fcport;
e315cd28 3009 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3010 if (new_fcport == NULL) {
7c3df132
SK		 3011 ql_log(ql_log_warn, vha, 0x201c,
3012 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3013 rval = QLA_MEMORY_ALLOC_FAILED;
3014 goto cleanup_allocation;
3015 }
3016 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
3017 }
3018
d8b45213 3019 /* Base iIDMA settings on HBA port speed. */
a3cbdfad 3020 fcport->fp_speed = ha->link_data_rate;
d8b45213 3021
e315cd28 3022 qla2x00_update_fcport(vha, fcport);
1da177e4
LT		 3023
3024 found_devs++;
3025 }
3026
3027cleanup_allocation:
c9475cb0 3028 kfree(new_fcport);
1da177e4
LT		 3029
3030 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3031 ql_dbg(ql_dbg_disc, vha, 0x201d,
3032 "Configure local loop error exit: rval=%x.\n", rval);
1da177e4
LT		 3033 }
3034
1da177e4
LT		 3035 return (rval);
3036}
3037
d8b45213 3038static void
e315cd28 3039qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
d8b45213 3040{
d8b45213 3041 int rval;
1bb39548 3042 uint16_t mb[4];
e315cd28 3043 struct qla_hw_data *ha = vha->hw;
d8b45213 3044
c76f2c01 3045 if (!IS_IIDMA_CAPABLE(ha))
d8b45213
AV		 3046 return;
3047
c9afb9a2
GM		 3048 if (atomic_read(&fcport->state) != FCS_ONLINE)
3049 return;
3050
39bd9622
AV		 3051 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
3052 fcport->fp_speed > ha->link_data_rate)
d8b45213
AV		 3053 return;
3054
e315cd28 3055 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
a3cbdfad 3056 mb);
d8b45213 3057 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3058 ql_dbg(ql_dbg_disc, vha, 0x2004,
3059 "Unable to adjust iIDMA "
3060 "%02x%02x%02x%02x%02x%02x%02x%02x -- %04x %x %04x "
3061 "%04x.\n", fcport->port_name[0], fcport->port_name[1],
d8b45213
AV		 3062 fcport->port_name[2], fcport->port_name[3],
3063 fcport->port_name[4], fcport->port_name[5],
3064 fcport->port_name[6], fcport->port_name[7], rval,
7c3df132 3065 fcport->fp_speed, mb[0], mb[1]);
d8b45213 3066 } else {
7c3df132
SK		 3067 ql_dbg(ql_dbg_disc, vha, 0x2005,
3068 "iIDMA adjusted to %s GB/s "
d0297c9a
JC		 3069 "on %02x%02x%02x%02x%02x%02x%02x%02x.\n",
3070 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
7c3df132
SK		 3071 fcport->port_name[0], fcport->port_name[1],
3072 fcport->port_name[2], fcport->port_name[3],
3073 fcport->port_name[4], fcport->port_name[5],
3074 fcport->port_name[6], fcport->port_name[7]);
d8b45213
AV		 3075 }
3076}
3077
23be331d 3078static void
e315cd28 3079qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
8482e118 3080{
3081 struct fc_rport_identifiers rport_ids;
bdf79621 3082 struct fc_rport *rport;
044d78e1 3083 unsigned long flags;
8482e118 3084
ac280b67 3085 qla2x00_rport_del(fcport);
8482e118 3086
f8b02a85
AV		 3087 rport_ids.node_name = wwn_to_u64(fcport->node_name);
3088 rport_ids.port_name = wwn_to_u64(fcport->port_name);
8482e118 3089 rport_ids.port_id = fcport->d_id.b.domain << 16 |
3090 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
77d74143 3091 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
e315cd28 3092 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
77d74143 3093 if (!rport) {
7c3df132
SK		 3094 ql_log(ql_log_warn, vha, 0x2006,
3095 "Unable to allocate fc remote port.\n");
77d74143
AV		 3096 return;
3097 }
2d70c103
NB		 3098 /*
3099 * Create target mode FC NEXUS in qla_target.c if target mode is
3100 * enabled..
3101 */
3102 qlt_fc_port_added(vha, fcport);
3103
044d78e1 3104 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
19a7b4ae 3105 *((fc_port_t **)rport->dd_data) = fcport;
044d78e1 3106 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
d97994dc 3107
ad3e0eda 3108 rport->supported_classes = fcport->supported_classes;
77d74143 3109
8482e118 3110 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
3111 if (fcport->port_type == FCT_INITIATOR)
3112 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
3113 if (fcport->port_type == FCT_TARGET)
3114 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
77d74143 3115 fc_remote_port_rolechg(rport, rport_ids.roles);
1da177e4
LT		 3116}
3117
23be331d
AB		 3118/*
3119 * qla2x00_update_fcport
3120 * Updates device on list.
3121 *
3122 * Input:
3123 * ha = adapter block pointer.
3124 * fcport = port structure pointer.
3125 *
3126 * Return:
3127 * 0 - Success
3128 * BIT_0 - error
3129 *
3130 * Context:
3131 * Kernel context.
3132 */
3133void
e315cd28 3134qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
23be331d 3135{
e315cd28 3136 fcport->vha = vha;
23be331d 3137 fcport->login_retry = 0;
5ff1d584 3138 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
23be331d 3139
1f93da52 3140 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
e315cd28 3141 qla2x00_iidma_fcport(vha, fcport);
21090cbe 3142 qla24xx_update_fcport_fcp_prio(vha, fcport);
e315cd28 3143 qla2x00_reg_remote_port(vha, fcport);
23be331d
AB		 3144}
3145
1da177e4
LT		 3146/*
3147 * qla2x00_configure_fabric
3148 * Setup SNS devices with loop ID's.
3149 *
3150 * Input:
3151 * ha = adapter block pointer.
3152 *
3153 * Returns:
3154 * 0 = success.
3155 * BIT_0 = error
3156 */
3157static int
e315cd28 3158qla2x00_configure_fabric(scsi_qla_host_t *vha)
1da177e4 3159{
b3b02e6e 3160 int rval;
e452ceb6 3161 fc_port_t *fcport, *fcptemp;
1da177e4
LT		 3162 uint16_t next_loopid;
3163 uint16_t mb[MAILBOX_REGISTER_COUNT];
0107109e 3164 uint16_t loop_id;
1da177e4 3165 LIST_HEAD(new_fcports);
e315cd28
AC		 3166 struct qla_hw_data *ha = vha->hw;
3167 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3168
3169 /* If FL port exists, then SNS is present */
e428924c 3170 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3171 loop_id = NPH_F_PORT;
3172 else
3173 loop_id = SNS_FL_PORT;
e315cd28 3174 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
1da177e4 3175 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3176 ql_dbg(ql_dbg_disc, vha, 0x201f,
3177 "MBX_GET_PORT_NAME failed, No FL Port.\n");
1da177e4 3178
e315cd28 3179 vha->device_flags &= ~SWITCH_FOUND;
1da177e4
LT		 3180 return (QLA_SUCCESS);
3181 }
e315cd28 3182 vha->device_flags |= SWITCH_FOUND;
1da177e4 3183
1da177e4 3184 do {
cca5335c
AV		 3185 /* FDMI support. */
3186 if (ql2xfdmienable &&
e315cd28
AC		 3187 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
3188 qla2x00_fdmi_register(vha);
cca5335c 3189
1da177e4 3190 /* Ensure we are logged into the SNS. */
e428924c 3191 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3192 loop_id = NPH_SNS;
3193 else
3194 loop_id = SIMPLE_NAME_SERVER;
0b91d116
CD		 3195 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
3196 0xfc, mb, BIT_1|BIT_0);
3197 if (rval != QLA_SUCCESS) {
3198 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
e452ceb6 3199 return rval;
0b91d116 3200 }
1da177e4 3201 if (mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 3202 ql_dbg(ql_dbg_disc, vha, 0x2042,
3203 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
3204 "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
3205 mb[2], mb[6], mb[7]);
1da177e4
LT		 3206 return (QLA_SUCCESS);
3207 }
3208
e315cd28
AC		 3209 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
3210 if (qla2x00_rft_id(vha)) {
1da177e4 3211 /* EMPTY */
7c3df132
SK		 3212 ql_dbg(ql_dbg_disc, vha, 0x2045,
3213 "Register FC-4 TYPE failed.\n");
1da177e4 3214 }
e315cd28 3215 if (qla2x00_rff_id(vha)) {
1da177e4 3216 /* EMPTY */
7c3df132
SK		 3217 ql_dbg(ql_dbg_disc, vha, 0x2049,
3218 "Register FC-4 Features failed.\n");
1da177e4 3219 }
e315cd28 3220 if (qla2x00_rnn_id(vha)) {
1da177e4 3221 /* EMPTY */
7c3df132
SK		 3222 ql_dbg(ql_dbg_disc, vha, 0x204f,
3223 "Register Node Name failed.\n");
e315cd28 3224 } else if (qla2x00_rsnn_nn(vha)) {
1da177e4 3225 /* EMPTY */
7c3df132
SK		 3226 ql_dbg(ql_dbg_disc, vha, 0x2053,
3227 "Register Symobilic Node Name failed.\n");
1da177e4
LT		 3228 }
3229 }
3230
827210ba
JC		 3231#define QLA_FCPORT_SCAN 1
3232#define QLA_FCPORT_FOUND 2
3233
3234 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3235 fcport->scan_state = QLA_FCPORT_SCAN;
3236 }
3237
e315cd28 3238 rval = qla2x00_find_all_fabric_devs(vha, &new_fcports);
1da177e4
LT		 3239 if (rval != QLA_SUCCESS)
3240 break;
3241
e452ceb6
JC		 3242 /*
3243 * Logout all previous fabric devices marked lost, except
3244 * FCP2 devices.
3245 */
e315cd28
AC		 3246 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3247 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1da177e4
LT		 3248 break;
3249
3250 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
3251 continue;
3252
827210ba 3253 if (fcport->scan_state == QLA_FCPORT_SCAN &&
b3b02e6e 3254 atomic_read(&fcport->state) == FCS_ONLINE) {
e315cd28 3255 qla2x00_mark_device_lost(vha, fcport,
d97994dc 3256 ql2xplogiabsentdevice, 0);
1da177e4 3257 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3258 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
1da177e4
LT		 3259 fcport->port_type != FCT_INITIATOR &&
3260 fcport->port_type != FCT_BROADCAST) {
e315cd28 3261 ha->isp_ops->fabric_logout(vha,
1c7c6357
AV		 3262 fcport->loop_id,
3263 fcport->d_id.b.domain,
3264 fcport->d_id.b.area,
3265 fcport->d_id.b.al_pa);
e452ceb6 3266 fcport->loop_id = FC_NO_LOOP_ID;
1da177e4
LT		 3267 }
3268 }
e452ceb6 3269 }
1da177e4 3270
e452ceb6
JC		 3271 /* Starting free loop ID. */
3272 next_loopid = ha->min_external_loopid;
3273
3274 /*
3275 * Scan through our port list and login entries that need to be
3276 * logged in.
3277 */
3278 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3279 if (atomic_read(&vha->loop_down_timer) ||
3280 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3281 break;
3282
3283 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
3284 (fcport->flags & FCF_LOGIN_NEEDED) == 0)
3285 continue;
3286
3287 if (fcport->loop_id == FC_NO_LOOP_ID) {
3288 fcport->loop_id = next_loopid;
3289 rval = qla2x00_find_new_loop_id(
3290 base_vha, fcport);
3291 if (rval != QLA_SUCCESS) {
3292 /* Ran out of IDs to use */
3293 break;
1da177e4
LT		 3294 }
3295 }
e452ceb6
JC		 3296 /* Login and update database */
3297 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
3298 }
3299
3300 /* Exit if out of loop IDs. */
3301 if (rval != QLA_SUCCESS) {
3302 break;
3303 }
3304
3305 /*
3306 * Login and add the new devices to our port list.
3307 */
3308 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
3309 if (atomic_read(&vha->loop_down_timer) ||
3310 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3311 break;
3312
3313 /* Find a new loop ID to use. */
3314 fcport->loop_id = next_loopid;
3315 rval = qla2x00_find_new_loop_id(base_vha, fcport);
3316 if (rval != QLA_SUCCESS) {
3317 /* Ran out of IDs to use */
3318 break;
3319 }
1da177e4 3320
bdf79621 3321 /* Login and update database */
e315cd28 3322 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
e452ceb6
JC		 3323
3324 list_move_tail(&fcport->list, &vha->vp_fcports);
1da177e4
LT		 3325 }
3326 } while (0);
3327
e452ceb6
JC		 3328 /* Free all new device structures not processed. */
3329 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
3330 list_del(&fcport->list);
3331 kfree(fcport);
3332 }
3333
1da177e4 3334 if (rval) {
7c3df132
SK		 3335 ql_dbg(ql_dbg_disc, vha, 0x2068,
3336 "Configure fabric error exit rval=%d.\n", rval);
1da177e4
LT		 3337 }
3338
3339 return (rval);
3340}
3341
1da177e4
LT		 3342/*
3343 * qla2x00_find_all_fabric_devs
3344 *
3345 * Input:
3346 * ha = adapter block pointer.
3347 * dev = database device entry pointer.
3348 *
3349 * Returns:
3350 * 0 = success.
3351 *
3352 * Context:
3353 * Kernel context.
3354 */
3355static int
e315cd28
AC		 3356qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
3357 struct list_head *new_fcports)
1da177e4
LT		 3358{
3359 int rval;
3360 uint16_t loop_id;
3361 fc_port_t *fcport, *new_fcport, *fcptemp;
3362 int found;
3363
3364 sw_info_t *swl;
3365 int swl_idx;
3366 int first_dev, last_dev;
1516ef44 3367 port_id_t wrap = {}, nxt_d_id;
e315cd28 3368 struct qla_hw_data *ha = vha->hw;
bb4cf5b7 3369 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3370
3371 rval = QLA_SUCCESS;
3372
3373 /* Try GID_PT to get device list, else GAN. */
7a67735b 3374 if (!ha->swl)
642ef983 3375 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
7a67735b
AV		 3376 GFP_KERNEL);
3377 swl = ha->swl;
bbfbbbc1 3378 if (!swl) {
1da177e4 3379 /*EMPTY*/
7c3df132
SK		 3380 ql_dbg(ql_dbg_disc, vha, 0x2054,
3381 "GID_PT allocations failed, fallback on GA_NXT.\n");
1da177e4 3382 } else {
642ef983 3383 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
e315cd28 3384 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
1da177e4 3385 swl = NULL;
e315cd28 3386 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3387 swl = NULL;
e315cd28 3388 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3389 swl = NULL;
e5896bd5 3390 } else if (ql2xiidmaenable &&
e315cd28
AC		 3391 qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) {
3392 qla2x00_gpsc(vha, swl);
1da177e4 3393 }
e8c72ba5
CD		 3394
3395 /* If other queries succeeded probe for FC-4 type */
3396 if (swl)
3397 qla2x00_gff_id(vha, swl);
1da177e4
LT		 3398 }
3399 swl_idx = 0;
3400
3401 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 3402 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3403 if (new_fcport == NULL) {
7c3df132
SK		 3404 ql_log(ql_log_warn, vha, 0x205e,
3405 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3406 return (QLA_MEMORY_ALLOC_FAILED);
3407 }
3408 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
1da177e4
LT		 3409 /* Set start port ID scan at adapter ID. */
3410 first_dev = 1;
3411 last_dev = 0;
3412
3413 /* Starting free loop ID. */
e315cd28
AC		 3414 loop_id = ha->min_external_loopid;
3415 for (; loop_id <= ha->max_loop_id; loop_id++) {
3416 if (qla2x00_is_reserved_id(vha, loop_id))
1da177e4
LT		 3417 continue;
3418
3a6478df
GM		 3419 if (ha->current_topology == ISP_CFG_FL &&
3420 (atomic_read(&vha->loop_down_timer) ||
3421 LOOP_TRANSITION(vha))) {
bb2d52b2
AV		 3422 atomic_set(&vha->loop_down_timer, 0);
3423 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
3424 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1da177e4 3425 break;
bb2d52b2 3426 }
1da177e4
LT		 3427
3428 if (swl != NULL) {
3429 if (last_dev) {
3430 wrap.b24 = new_fcport->d_id.b24;
3431 } else {
3432 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
3433 memcpy(new_fcport->node_name,
3434 swl[swl_idx].node_name, WWN_SIZE);
3435 memcpy(new_fcport->port_name,
3436 swl[swl_idx].port_name, WWN_SIZE);
d8b45213
AV		 3437 memcpy(new_fcport->fabric_port_name,
3438 swl[swl_idx].fabric_port_name, WWN_SIZE);
3439 new_fcport->fp_speed = swl[swl_idx].fp_speed;
e8c72ba5 3440 new_fcport->fc4_type = swl[swl_idx].fc4_type;
1da177e4
LT		 3441
3442 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
3443 last_dev = 1;
3444 }
3445 swl_idx++;
3446 }
3447 } else {
3448 /* Send GA_NXT to the switch */
e315cd28 3449 rval = qla2x00_ga_nxt(vha, new_fcport);
1da177e4 3450 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3451 ql_log(ql_log_warn, vha, 0x2064,
3452 "SNS scan failed -- assuming "
3453 "zero-entry result.\n");
1da177e4
LT		 3454 list_for_each_entry_safe(fcport, fcptemp,
3455 new_fcports, list) {
3456 list_del(&fcport->list);
3457 kfree(fcport);
3458 }
3459 rval = QLA_SUCCESS;
3460 break;
3461 }
3462 }
3463
3464 /* If wrap on switch device list, exit. */
3465 if (first_dev) {
3466 wrap.b24 = new_fcport->d_id.b24;
3467 first_dev = 0;
3468 } else if (new_fcport->d_id.b24 == wrap.b24) {
7c3df132
SK		 3469 ql_dbg(ql_dbg_disc, vha, 0x2065,
3470 "Device wrap (%02x%02x%02x).\n",
3471 new_fcport->d_id.b.domain,
3472 new_fcport->d_id.b.area,
3473 new_fcport->d_id.b.al_pa);
1da177e4
LT		 3474 break;
3475 }
3476
2c3dfe3f 3477 /* Bypass if same physical adapter. */
e315cd28 3478 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
1da177e4
LT		 3479 continue;
3480
2c3dfe3f 3481 /* Bypass virtual ports of the same host. */
bb4cf5b7
CD		 3482 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24))
3483 continue;
2c3dfe3f 3484
f7d289f6
AV		 3485 /* Bypass if same domain and area of adapter. */
3486 if (((new_fcport->d_id.b24 & 0xffff00) ==
e315cd28 3487 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
f7d289f6
AV		 3488 ISP_CFG_FL)
3489 continue;
3490
1da177e4
LT		 3491 /* Bypass reserved domain fields. */
3492 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
3493 continue;
3494
e8c72ba5 3495 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
4da26e16
CD		 3496 if (ql2xgffidenable &&
3497 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
3498 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
e8c72ba5
CD		 3499 continue;
3500
1da177e4
LT		 3501 /* Locate matching device in database. */
3502 found = 0;
e315cd28 3503 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3504 if (memcmp(new_fcport->port_name, fcport->port_name,
3505 WWN_SIZE))
3506 continue;
3507
827210ba 3508 fcport->scan_state = QLA_FCPORT_FOUND;
b3b02e6e 3509
1da177e4
LT		 3510 found++;
3511
d8b45213
AV		 3512 /* Update port state. */
3513 memcpy(fcport->fabric_port_name,
3514 new_fcport->fabric_port_name, WWN_SIZE);
3515 fcport->fp_speed = new_fcport->fp_speed;
3516
1da177e4
LT		 3517 /*
3518 * If address the same and state FCS_ONLINE, nothing
3519 * changed.
3520 */
3521 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
3522 atomic_read(&fcport->state) == FCS_ONLINE) {
3523 break;
3524 }
3525
3526 /*
3527 * If device was not a fabric device before.
3528 */
3529 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3530 fcport->d_id.b24 = new_fcport->d_id.b24;
5f16b331 3531 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3532 fcport->flags |= (FCF_FABRIC_DEVICE |
3533 FCF_LOGIN_NEEDED);
1da177e4
LT		 3534 break;
3535 }
3536
3537 /*
3538 * Port ID changed or device was marked to be updated;
3539 * Log it out if still logged in and mark it for
3540 * relogin later.
3541 */
3542 fcport->d_id.b24 = new_fcport->d_id.b24;
3543 fcport->flags |= FCF_LOGIN_NEEDED;
3544 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3545 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
0eba25df 3546 (fcport->flags & FCF_ASYNC_SENT) == 0 &&
1da177e4
LT		 3547 fcport->port_type != FCT_INITIATOR &&
3548 fcport->port_type != FCT_BROADCAST) {
e315cd28 3549 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3550 fcport->d_id.b.domain, fcport->d_id.b.area,
3551 fcport->d_id.b.al_pa);
5f16b331 3552 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3553 }
3554
3555 break;
3556 }
3557
3558 if (found)
3559 continue;
1da177e4
LT		 3560 /* If device was not in our fcports list, then add it. */
3561 list_add_tail(&new_fcport->list, new_fcports);
3562
3563 /* Allocate a new replacement fcport. */
3564 nxt_d_id.b24 = new_fcport->d_id.b24;
e315cd28 3565 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3566 if (new_fcport == NULL) {
7c3df132
SK		 3567 ql_log(ql_log_warn, vha, 0x2066,
3568 "Memory allocation failed for fcport.\n");
1da177e4
LT		 3569 return (QLA_MEMORY_ALLOC_FAILED);
3570 }
3571 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
3572 new_fcport->d_id.b24 = nxt_d_id.b24;
3573 }
3574
c9475cb0 3575 kfree(new_fcport);
1da177e4 3576
1da177e4
LT		 3577 return (rval);
3578}
3579
3580/*
3581 * qla2x00_find_new_loop_id
3582 * Scan through our port list and find a new usable loop ID.
3583 *
3584 * Input:
3585 * ha: adapter state pointer.
3586 * dev: port structure pointer.
3587 *
3588 * Returns:
3589 * qla2x00 local function return status code.
3590 *
3591 * Context:
3592 * Kernel context.
3593 */
03bcfb57 3594int
e315cd28 3595qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
1da177e4
LT		 3596{
3597 int rval;
e315cd28 3598 struct qla_hw_data *ha = vha->hw;
feafb7b1 3599 unsigned long flags = 0;
1da177e4
LT		 3600
3601 rval = QLA_SUCCESS;
3602
5f16b331 3603 spin_lock_irqsave(&ha->vport_slock, flags);
1da177e4 3604
5f16b331
CD		 3605 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
3606 LOOPID_MAP_SIZE);
3607 if (dev->loop_id >= LOOPID_MAP_SIZE ||
3608 qla2x00_is_reserved_id(vha, dev->loop_id)) {
3609 dev->loop_id = FC_NO_LOOP_ID;
3610 rval = QLA_FUNCTION_FAILED;
3611 } else
3612 set_bit(dev->loop_id, ha->loop_id_map);
1da177e4 3613
5f16b331 3614 spin_unlock_irqrestore(&ha->vport_slock, flags);
1da177e4 3615
5f16b331
CD		 3616 if (rval == QLA_SUCCESS)
3617 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
3618 "Assigning new loopid=%x, portid=%x.\n",
3619 dev->loop_id, dev->d_id.b24);
3620 else
3621 ql_log(ql_log_warn, dev->vha, 0x2087,
3622 "No loop_id's available, portid=%x.\n",
3623 dev->d_id.b24);
1da177e4
LT		 3624
3625 return (rval);
3626}
3627
1da177e4
LT		 3628/*
3629 * qla2x00_fabric_dev_login
3630 * Login fabric target device and update FC port database.
3631 *
3632 * Input:
3633 * ha: adapter state pointer.
3634 * fcport: port structure list pointer.
3635 * next_loopid: contains value of a new loop ID that can be used
3636 * by the next login attempt.
3637 *
3638 * Returns:
3639 * qla2x00 local function return status code.
3640 *
3641 * Context:
3642 * Kernel context.
3643 */
3644static int
e315cd28 3645qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3646 uint16_t *next_loopid)
3647{
3648 int rval;
3649 int retry;
0107109e 3650 uint8_t opts;
e315cd28 3651 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3652
3653 rval = QLA_SUCCESS;
3654 retry = 0;
3655
ac280b67 3656 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584
AV		 3657 if (fcport->flags & FCF_ASYNC_SENT)
3658 return rval;
3659 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 3660 rval = qla2x00_post_async_login_work(vha, fcport, NULL);
3661 if (!rval)
3662 return rval;
3663 }
3664
5ff1d584 3665 fcport->flags &= ~FCF_ASYNC_SENT;
e315cd28 3666 rval = qla2x00_fabric_login(vha, fcport, next_loopid);
1da177e4 3667 if (rval == QLA_SUCCESS) {
f08b7251 3668 /* Send an ADISC to FCP2 devices.*/
0107109e 3669 opts = 0;
f08b7251 3670 if (fcport->flags & FCF_FCP2_DEVICE)
0107109e 3671 opts |= BIT_1;
e315cd28 3672 rval = qla2x00_get_port_database(vha, fcport, opts);
1da177e4 3673 if (rval != QLA_SUCCESS) {
e315cd28 3674 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3675 fcport->d_id.b.domain, fcport->d_id.b.area,
3676 fcport->d_id.b.al_pa);
e315cd28 3677 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4 3678 } else {
e315cd28 3679 qla2x00_update_fcport(vha, fcport);
1da177e4 3680 }
0b91d116
CD		 3681 } else {
3682 /* Retry Login. */
3683 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3684 }
3685
3686 return (rval);
3687}
3688
3689/*
3690 * qla2x00_fabric_login
3691 * Issue fabric login command.
3692 *
3693 * Input:
3694 * ha = adapter block pointer.
3695 * device = pointer to FC device type structure.
3696 *
3697 * Returns:
3698 * 0 - Login successfully
3699 * 1 - Login failed
3700 * 2 - Initiator device
3701 * 3 - Fatal error
3702 */
3703int
e315cd28 3704qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3705 uint16_t *next_loopid)
3706{
3707 int rval;
3708 int retry;
3709 uint16_t tmp_loopid;
3710 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 3711 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3712
3713 retry = 0;
3714 tmp_loopid = 0;
3715
3716 for (;;) {
7c3df132
SK		 3717 ql_dbg(ql_dbg_disc, vha, 0x2000,
3718 "Trying Fabric Login w/loop id 0x%04x for port "
3719 "%02x%02x%02x.\n",
3720 fcport->loop_id, fcport->d_id.b.domain,
3721 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3722
3723 /* Login fcport on switch. */
0b91d116 3724 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
1da177e4
LT		 3725 fcport->d_id.b.domain, fcport->d_id.b.area,
3726 fcport->d_id.b.al_pa, mb, BIT_0);
0b91d116
CD		 3727 if (rval != QLA_SUCCESS) {
3728 return rval;
3729 }
1da177e4
LT		 3730 if (mb[0] == MBS_PORT_ID_USED) {
3731 /*
3732 * Device has another loop ID. The firmware team
0107109e
AV		 3733 * recommends the driver perform an implicit login with
3734 * the specified ID again. The ID we just used is save
3735 * here so we return with an ID that can be tried by
3736 * the next login.
1da177e4
LT		 3737 */
3738 retry++;
3739 tmp_loopid = fcport->loop_id;
3740 fcport->loop_id = mb[1];
3741
7c3df132
SK		 3742 ql_dbg(ql_dbg_disc, vha, 0x2001,
3743 "Fabric Login: port in use - next loop "
3744 "id=0x%04x, port id= %02x%02x%02x.\n",
1da177e4 3745 fcport->loop_id, fcport->d_id.b.domain,
7c3df132 3746 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3747
3748 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
3749 /*
3750 * Login succeeded.
3751 */
3752 if (retry) {
3753 /* A retry occurred before. */
3754 *next_loopid = tmp_loopid;
3755 } else {
3756 /*
3757 * No retry occurred before. Just increment the
3758 * ID value for next login.
3759 */
3760 *next_loopid = (fcport->loop_id + 1);
3761 }
3762
3763 if (mb[1] & BIT_0) {
3764 fcport->port_type = FCT_INITIATOR;
3765 } else {
3766 fcport->port_type = FCT_TARGET;
3767 if (mb[1] & BIT_1) {
8474f3a0 3768 fcport->flags |= FCF_FCP2_DEVICE;
1da177e4
LT		 3769 }
3770 }
3771
ad3e0eda
AV		 3772 if (mb[10] & BIT_0)
3773 fcport->supported_classes |= FC_COS_CLASS2;
3774 if (mb[10] & BIT_1)
3775 fcport->supported_classes |= FC_COS_CLASS3;
3776
2d70c103
NB		 3777 if (IS_FWI2_CAPABLE(ha)) {
3778 if (mb[10] & BIT_7)
3779 fcport->flags |=
3780 FCF_CONF_COMP_SUPPORTED;
3781 }
3782
1da177e4
LT		 3783 rval = QLA_SUCCESS;
3784 break;
3785 } else if (mb[0] == MBS_LOOP_ID_USED) {
3786 /*
3787 * Loop ID already used, try next loop ID.
3788 */
3789 fcport->loop_id++;
e315cd28 3790 rval = qla2x00_find_new_loop_id(vha, fcport);
1da177e4
LT		 3791 if (rval != QLA_SUCCESS) {
3792 /* Ran out of loop IDs to use */
3793 break;
3794 }
3795 } else if (mb[0] == MBS_COMMAND_ERROR) {
3796 /*
3797 * Firmware possibly timed out during login. If NO
3798 * retries are left to do then the device is declared
3799 * dead.
3800 */
3801 *next_loopid = fcport->loop_id;
e315cd28 3802 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3803 fcport->d_id.b.domain, fcport->d_id.b.area,
3804 fcport->d_id.b.al_pa);
e315cd28 3805 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3806
3807 rval = 1;
3808 break;
3809 } else {
3810 /*
3811 * unrecoverable / not handled error
3812 */
7c3df132
SK		 3813 ql_dbg(ql_dbg_disc, vha, 0x2002,
3814 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
3815 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
3816 fcport->d_id.b.area, fcport->d_id.b.al_pa,
3817 fcport->loop_id, jiffies);
1da177e4
LT		 3818
3819 *next_loopid = fcport->loop_id;
e315cd28 3820 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3821 fcport->d_id.b.domain, fcport->d_id.b.area,
3822 fcport->d_id.b.al_pa);
5f16b331 3823 qla2x00_clear_loop_id(fcport);
0eedfcf0 3824 fcport->login_retry = 0;
1da177e4
LT		 3825
3826 rval = 3;
3827 break;
3828 }
3829 }
3830
3831 return (rval);
3832}
3833
3834/*
3835 * qla2x00_local_device_login
3836 * Issue local device login command.
3837 *
3838 * Input:
3839 * ha = adapter block pointer.
3840 * loop_id = loop id of device to login to.
3841 *
3842 * Returns (Where's the #define!!!!):
3843 * 0 - Login successfully
3844 * 1 - Login failed
3845 * 3 - Fatal error
3846 */
3847int
e315cd28 3848qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
1da177e4
LT		 3849{
3850 int rval;
3851 uint16_t mb[MAILBOX_REGISTER_COUNT];
3852
3853 memset(mb, 0, sizeof(mb));
e315cd28 3854 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
1da177e4
LT		 3855 if (rval == QLA_SUCCESS) {
3856 /* Interrogate mailbox registers for any errors */
3857 if (mb[0] == MBS_COMMAND_ERROR)
3858 rval = 1;
3859 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
3860 /* device not in PCB table */
3861 rval = 3;
3862 }
3863
3864 return (rval);
3865}
3866
3867/*
3868 * qla2x00_loop_resync
3869 * Resync with fibre channel devices.
3870 *
3871 * Input:
3872 * ha = adapter block pointer.
3873 *
3874 * Returns:
3875 * 0 = success
3876 */
3877int
e315cd28 3878qla2x00_loop_resync(scsi_qla_host_t *vha)
1da177e4 3879{
73208dfd 3880 int rval = QLA_SUCCESS;
1da177e4 3881 uint32_t wait_time;
67c2e93a
AC		 3882 struct req_que *req;
3883 struct rsp_que *rsp;
3884
7163ea81 3885 if (vha->hw->flags.cpu_affinity_enabled)
67c2e93a
AC		 3886 req = vha->hw->req_q_map[0];
3887 else
3888 req = vha->req;
3889 rsp = req->rsp;
1da177e4 3890
e315cd28
AC		 3891 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
3892 if (vha->flags.online) {
3893 if (!(rval = qla2x00_fw_ready(vha))) {
1da177e4
LT		 3894 /* Wait at most MAX_TARGET RSCNs for a stable link. */
3895 wait_time = 256;
3896 do {
0107109e 3897 /* Issue a marker after FW becomes ready. */
73208dfd
AC		 3898 qla2x00_marker(vha, req, rsp, 0, 0,
3899 MK_SYNC_ALL);
e315cd28 3900 vha->marker_needed = 0;
1da177e4
LT		 3901
3902 /* Remap devices on Loop. */
e315cd28 3903 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4 3904
e315cd28 3905 qla2x00_configure_loop(vha);
1da177e4 3906 wait_time--;
e315cd28
AC		 3907 } while (!atomic_read(&vha->loop_down_timer) &&
3908 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
3909 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
3910 &vha->dpc_flags)));
1da177e4 3911 }
1da177e4
LT		 3912 }
3913
e315cd28 3914 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
1da177e4 3915 return (QLA_FUNCTION_FAILED);
1da177e4 3916
e315cd28 3917 if (rval)
7c3df132
SK		 3918 ql_dbg(ql_dbg_disc, vha, 0x206c,
3919 "%s *** FAILED ***.\n", __func__);
1da177e4
LT		 3920
3921 return (rval);
3922}
3923
579d12b5
SK		 3924/*
3925* qla2x00_perform_loop_resync
3926* Description: This function will set the appropriate flags and call
3927* qla2x00_loop_resync. If successful loop will be resynced
3928* Arguments : scsi_qla_host_t pointer
3929* returm : Success or Failure
3930*/
3931
3932int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
3933{
3934 int32_t rval = 0;
3935
3936 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
3937 /*Configure the flags so that resync happens properly*/
3938 atomic_set(&ha->loop_down_timer, 0);
3939 if (!(ha->device_flags & DFLG_NO_CABLE)) {
3940 atomic_set(&ha->loop_state, LOOP_UP);
3941 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
3942 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
3943 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
3944
3945 rval = qla2x00_loop_resync(ha);
3946 } else
3947 atomic_set(&ha->loop_state, LOOP_DEAD);
3948
3949 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
3950 }
3951
3952 return rval;
3953}
3954
d97994dc 3955void
67becc00 3956qla2x00_update_fcports(scsi_qla_host_t *base_vha)
d97994dc 3957{
3958 fc_port_t *fcport;
feafb7b1
AE		 3959 struct scsi_qla_host *vha;
3960 struct qla_hw_data *ha = base_vha->hw;
3961 unsigned long flags;
d97994dc 3962
feafb7b1 3963 spin_lock_irqsave(&ha->vport_slock, flags);
d97994dc 3964 /* Go with deferred removal of rport references. */
feafb7b1
AE		 3965 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
3966 atomic_inc(&vha->vref_count);
3967 list_for_each_entry(fcport, &vha->vp_fcports, list) {
8ae598d0 3968 if (fcport->drport &&
feafb7b1
AE		 3969 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
3970 spin_unlock_irqrestore(&ha->vport_slock, flags);
3971
67becc00 3972 qla2x00_rport_del(fcport);
feafb7b1
AE		 3973
3974 spin_lock_irqsave(&ha->vport_slock, flags);
3975 }
3976 }
3977 atomic_dec(&vha->vref_count);
3978 }
3979 spin_unlock_irqrestore(&ha->vport_slock, flags);
d97994dc 3980}
3981
7d613ac6
SV		 3982/* Assumes idc_lock always held on entry */
3983void
3984qla83xx_reset_ownership(scsi_qla_host_t *vha)
3985{
3986 struct qla_hw_data *ha = vha->hw;
3987 uint32_t drv_presence, drv_presence_mask;
3988 uint32_t dev_part_info1, dev_part_info2, class_type;
3989 uint32_t class_type_mask = 0x3;
3990 uint16_t fcoe_other_function = 0xffff, i;
3991
3992 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
3993
3994 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
3995 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
3996 for (i = 0; i < 8; i++) {
3997 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
3998 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
3999 (i != ha->portnum)) {
4000 fcoe_other_function = i;
4001 break;
4002 }
4003 }
4004 if (fcoe_other_function == 0xffff) {
4005 for (i = 0; i < 8; i++) {
4006 class_type = ((dev_part_info2 >> (i * 4)) &
4007 class_type_mask);
4008 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
4009 ((i + 8) != ha->portnum)) {
4010 fcoe_other_function = i + 8;
4011 break;
4012 }
4013 }
4014 }
4015 /*
4016 * Prepare drv-presence mask based on fcoe functions present.
4017 * However consider only valid physical fcoe function numbers (0-15).
4018 */
4019 drv_presence_mask = ~((1 << (ha->portnum)) |
4020 ((fcoe_other_function == 0xffff) ?
4021 0 : (1 << (fcoe_other_function))));
4022
4023 /* We are the reset owner iff:
4024 * - No other protocol drivers present.
4025 * - This is the lowest among fcoe functions. */
4026 if (!(drv_presence & drv_presence_mask) &&
4027 (ha->portnum < fcoe_other_function)) {
4028 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
4029 "This host is Reset owner.\n");
4030 ha->flags.nic_core_reset_owner = 1;
4031 }
4032}
4033
fa492630 4034static int
7d613ac6
SV		 4035__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
4036{
4037 int rval = QLA_SUCCESS;
4038 struct qla_hw_data *ha = vha->hw;
4039 uint32_t drv_ack;
4040
4041 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4042 if (rval == QLA_SUCCESS) {
4043 drv_ack |= (1 << ha->portnum);
4044 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4045 }
4046
4047 return rval;
4048}
4049
fa492630 4050static int
7d613ac6
SV		 4051__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
4052{
4053 int rval = QLA_SUCCESS;
4054 struct qla_hw_data *ha = vha->hw;
4055 uint32_t drv_ack;
4056
4057 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4058 if (rval == QLA_SUCCESS) {
4059 drv_ack &= ~(1 << ha->portnum);
4060 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4061 }
4062
4063 return rval;
4064}
4065
fa492630 4066static const char *
7d613ac6
SV		 4067qla83xx_dev_state_to_string(uint32_t dev_state)
4068{
4069 switch (dev_state) {
4070 case QLA8XXX_DEV_COLD:
4071 return "COLD/RE-INIT";
4072 case QLA8XXX_DEV_INITIALIZING:
4073 return "INITIALIZING";
4074 case QLA8XXX_DEV_READY:
4075 return "READY";
4076 case QLA8XXX_DEV_NEED_RESET:
4077 return "NEED RESET";
4078 case QLA8XXX_DEV_NEED_QUIESCENT:
4079 return "NEED QUIESCENT";
4080 case QLA8XXX_DEV_FAILED:
4081 return "FAILED";
4082 case QLA8XXX_DEV_QUIESCENT:
4083 return "QUIESCENT";
4084 default:
4085 return "Unknown";
4086 }
4087}
4088
4089/* Assumes idc-lock always held on entry */
4090void
4091qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
4092{
4093 struct qla_hw_data *ha = vha->hw;
4094 uint32_t idc_audit_reg = 0, duration_secs = 0;
4095
4096 switch (audit_type) {
4097 case IDC_AUDIT_TIMESTAMP:
4098 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
4099 idc_audit_reg = (ha->portnum) |
4100 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
4101 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4102 break;
4103
4104 case IDC_AUDIT_COMPLETION:
4105 duration_secs = ((jiffies_to_msecs(jiffies) -
4106 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
4107 idc_audit_reg = (ha->portnum) |
4108 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
4109 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4110 break;
4111
4112 default:
4113 ql_log(ql_log_warn, vha, 0xb078,
4114 "Invalid audit type specified.\n");
4115 break;
4116 }
4117}
4118
4119/* Assumes idc_lock always held on entry */
fa492630 4120static int
7d613ac6
SV		 4121qla83xx_initiating_reset(scsi_qla_host_t *vha)
4122{
4123 struct qla_hw_data *ha = vha->hw;
4124 uint32_t idc_control, dev_state;
4125
4126 __qla83xx_get_idc_control(vha, &idc_control);
4127 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
4128 ql_log(ql_log_info, vha, 0xb080,
4129 "NIC Core reset has been disabled. idc-control=0x%x\n",
4130 idc_control);
4131 return QLA_FUNCTION_FAILED;
4132 }
4133
4134 /* Set NEED-RESET iff in READY state and we are the reset-owner */
4135 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4136 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
4137 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
4138 QLA8XXX_DEV_NEED_RESET);
4139 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
4140 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
4141 } else {
4142 const char *state = qla83xx_dev_state_to_string(dev_state);
4143 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
4144
4145 /* SV: XXX: Is timeout required here? */
4146 /* Wait for IDC state change READY -> NEED_RESET */
4147 while (dev_state == QLA8XXX_DEV_READY) {
4148 qla83xx_idc_unlock(vha, 0);
4149 msleep(200);
4150 qla83xx_idc_lock(vha, 0);
4151 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4152 }
4153 }
4154
4155 /* Send IDC ack by writing to drv-ack register */
4156 __qla83xx_set_drv_ack(vha);
4157
4158 return QLA_SUCCESS;
4159}
4160
4161int
4162__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
4163{
4164 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4165}
4166
7d613ac6
SV		 4167int
4168__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
4169{
4170 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4171}
4172
fa492630 4173static int
7d613ac6
SV		 4174qla83xx_check_driver_presence(scsi_qla_host_t *vha)
4175{
4176 uint32_t drv_presence = 0;
4177 struct qla_hw_data *ha = vha->hw;
4178
4179 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4180 if (drv_presence & (1 << ha->portnum))
4181 return QLA_SUCCESS;
4182 else
4183 return QLA_TEST_FAILED;
4184}
4185
4186int
4187qla83xx_nic_core_reset(scsi_qla_host_t *vha)
4188{
4189 int rval = QLA_SUCCESS;
4190 struct qla_hw_data *ha = vha->hw;
4191
4192 ql_dbg(ql_dbg_p3p, vha, 0xb058,
4193 "Entered %s().\n", __func__);
4194
4195 if (vha->device_flags & DFLG_DEV_FAILED) {
4196 ql_log(ql_log_warn, vha, 0xb059,
4197 "Device in unrecoverable FAILED state.\n");
4198 return QLA_FUNCTION_FAILED;
4199 }
4200
4201 qla83xx_idc_lock(vha, 0);
4202
4203 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
4204 ql_log(ql_log_warn, vha, 0xb05a,
4205 "Function=0x%x has been removed from IDC participation.\n",
4206 ha->portnum);
4207 rval = QLA_FUNCTION_FAILED;
4208 goto exit;
4209 }
4210
4211 qla83xx_reset_ownership(vha);
4212
4213 rval = qla83xx_initiating_reset(vha);
4214
4215 /*
4216 * Perform reset if we are the reset-owner,
4217 * else wait till IDC state changes to READY/FAILED.
4218 */
4219 if (rval == QLA_SUCCESS) {
4220 rval = qla83xx_idc_state_handler(vha);
4221
4222 if (rval == QLA_SUCCESS)
4223 ha->flags.nic_core_hung = 0;
4224 __qla83xx_clear_drv_ack(vha);
4225 }
4226
4227exit:
4228 qla83xx_idc_unlock(vha, 0);
4229
4230 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
4231
4232 return rval;
4233}
4234
81178772
SK		 4235int
4236qla2xxx_mctp_dump(scsi_qla_host_t *vha)
4237{
4238 struct qla_hw_data *ha = vha->hw;
4239 int rval = QLA_FUNCTION_FAILED;
4240
4241 if (!IS_MCTP_CAPABLE(ha)) {
4242 /* This message can be removed from the final version */
4243 ql_log(ql_log_info, vha, 0x506d,
4244 "This board is not MCTP capable\n");
4245 return rval;
4246 }
4247
4248 if (!ha->mctp_dump) {
4249 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
4250 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
4251
4252 if (!ha->mctp_dump) {
4253 ql_log(ql_log_warn, vha, 0x506e,
4254 "Failed to allocate memory for mctp dump\n");
4255 return rval;
4256 }
4257 }
4258
4259#define MCTP_DUMP_STR_ADDR 0x00000000
4260 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
4261 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
4262 if (rval != QLA_SUCCESS) {
4263 ql_log(ql_log_warn, vha, 0x506f,
4264 "Failed to capture mctp dump\n");
4265 } else {
4266 ql_log(ql_log_info, vha, 0x5070,
4267 "Mctp dump capture for host (%ld/%p).\n",
4268 vha->host_no, ha->mctp_dump);
4269 ha->mctp_dumped = 1;
4270 }
4271
409ee0fe 4272 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
81178772
SK		 4273 ha->flags.nic_core_reset_hdlr_active = 1;
4274 rval = qla83xx_restart_nic_firmware(vha);
4275 if (rval)
4276 /* NIC Core reset failed. */
4277 ql_log(ql_log_warn, vha, 0x5071,
4278 "Failed to restart nic firmware\n");
4279 else
4280 ql_dbg(ql_dbg_p3p, vha, 0xb084,
4281 "Restarted NIC firmware successfully.\n");
4282 ha->flags.nic_core_reset_hdlr_active = 0;
4283 }
4284
4285 return rval;
4286
4287}
4288
579d12b5 4289/*
8fcd6b8b 4290* qla2x00_quiesce_io
579d12b5
SK		 4291* Description: This function will block the new I/Os
4292* Its not aborting any I/Os as context
4293* is not destroyed during quiescence
4294* Arguments: scsi_qla_host_t
4295* return : void
4296*/
4297void
8fcd6b8b 4298qla2x00_quiesce_io(scsi_qla_host_t *vha)
579d12b5
SK		 4299{
4300 struct qla_hw_data *ha = vha->hw;
4301 struct scsi_qla_host *vp;
4302
8fcd6b8b
CD		 4303 ql_dbg(ql_dbg_dpc, vha, 0x401d,
4304 "Quiescing I/O - ha=%p.\n", ha);
579d12b5
SK		 4305
4306 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
4307 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4308 atomic_set(&vha->loop_state, LOOP_DOWN);
4309 qla2x00_mark_all_devices_lost(vha, 0);
4310 list_for_each_entry(vp, &ha->vp_list, list)
8fcd6b8b 4311 qla2x00_mark_all_devices_lost(vp, 0);
579d12b5
SK		 4312 } else {
4313 if (!atomic_read(&vha->loop_down_timer))
4314 atomic_set(&vha->loop_down_timer,
4315 LOOP_DOWN_TIME);
4316 }
4317 /* Wait for pending cmds to complete */
4318 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
4319}
4320
a9083016
GM		 4321void
4322qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
4323{
4324 struct qla_hw_data *ha = vha->hw;
579d12b5 4325 struct scsi_qla_host *vp;
feafb7b1 4326 unsigned long flags;
6aef87be 4327 fc_port_t *fcport;
a9083016 4328
e46ef004
SK		 4329 /* For ISP82XX, driver waits for completion of the commands.
4330 * online flag should be set.
4331 */
4332 if (!IS_QLA82XX(ha))
4333 vha->flags.online = 0;
a9083016
GM		 4334 ha->flags.chip_reset_done = 0;
4335 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2be21fa2 4336 vha->qla_stats.total_isp_aborts++;
a9083016 4337
7c3df132
SK		 4338 ql_log(ql_log_info, vha, 0x00af,
4339 "Performing ISP error recovery - ha=%p.\n", ha);
a9083016 4340
e46ef004
SK		 4341 /* For ISP82XX, reset_chip is just disabling interrupts.
4342 * Driver waits for the completion of the commands.
4343 * the interrupts need to be enabled.
4344 */
a9083016
GM		 4345 if (!IS_QLA82XX(ha))
4346 ha->isp_ops->reset_chip(vha);
4347
4348 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
4349 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4350 atomic_set(&vha->loop_state, LOOP_DOWN);
4351 qla2x00_mark_all_devices_lost(vha, 0);
feafb7b1
AE		 4352
4353 spin_lock_irqsave(&ha->vport_slock, flags);
579d12b5 4354 list_for_each_entry(vp, &ha->vp_list, list) {
feafb7b1
AE		 4355 atomic_inc(&vp->vref_count);
4356 spin_unlock_irqrestore(&ha->vport_slock, flags);
4357
a9083016 4358 qla2x00_mark_all_devices_lost(vp, 0);
feafb7b1
AE		 4359
4360 spin_lock_irqsave(&ha->vport_slock, flags);
4361 atomic_dec(&vp->vref_count);
4362 }
4363 spin_unlock_irqrestore(&ha->vport_slock, flags);
a9083016
GM		 4364 } else {
4365 if (!atomic_read(&vha->loop_down_timer))
4366 atomic_set(&vha->loop_down_timer,
4367 LOOP_DOWN_TIME);
4368 }
4369
6aef87be
AV		 4370 /* Clear all async request states across all VPs. */
4371 list_for_each_entry(fcport, &vha->vp_fcports, list)
4372 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4373 spin_lock_irqsave(&ha->vport_slock, flags);
4374 list_for_each_entry(vp, &ha->vp_list, list) {
4375 atomic_inc(&vp->vref_count);
4376 spin_unlock_irqrestore(&ha->vport_slock, flags);
4377
4378 list_for_each_entry(fcport, &vp->vp_fcports, list)
4379 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4380
4381 spin_lock_irqsave(&ha->vport_slock, flags);
4382 atomic_dec(&vp->vref_count);
4383 }
4384 spin_unlock_irqrestore(&ha->vport_slock, flags);
4385
bddd2d65
LC		 4386 if (!ha->flags.eeh_busy) {
4387 /* Make sure for ISP 82XX IO DMA is complete */
4388 if (IS_QLA82XX(ha)) {
7190575f 4389 qla82xx_chip_reset_cleanup(vha);
7c3df132
SK		 4390 ql_log(ql_log_info, vha, 0x00b4,
4391 "Done chip reset cleanup.\n");
a9083016 4392
e46ef004
SK		 4393 /* Done waiting for pending commands.
4394 * Reset the online flag.
4395 */
4396 vha->flags.online = 0;
4d78c973 4397 }
a9083016 4398
bddd2d65
LC		 4399 /* Requeue all commands in outstanding command list. */
4400 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
4401 }
a9083016
GM		 4402}
4403
1da177e4
LT		 4404/*
4405* qla2x00_abort_isp
4406* Resets ISP and aborts all outstanding commands.
4407*
4408* Input:
4409* ha = adapter block pointer.
4410*
4411* Returns:
4412* 0 = success
4413*/
4414int
e315cd28 4415qla2x00_abort_isp(scsi_qla_host_t *vha)
1da177e4 4416{
476e8978 4417 int rval;
1da177e4 4418 uint8_t status = 0;
e315cd28
AC		 4419 struct qla_hw_data *ha = vha->hw;
4420 struct scsi_qla_host *vp;
73208dfd 4421 struct req_que *req = ha->req_q_map[0];
feafb7b1 4422 unsigned long flags;
1da177e4 4423
e315cd28 4424 if (vha->flags.online) {
a9083016 4425 qla2x00_abort_isp_cleanup(vha);
1da177e4 4426
a6171297
SV		 4427 if (IS_QLA8031(ha)) {
4428 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
4429 "Clearing fcoe driver presence.\n");
4430 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
4431 ql_dbg(ql_dbg_p3p, vha, 0xb073,
4432 "Error while clearing DRV-Presence.\n");
4433 }
4434
85880801
AV		 4435 if (unlikely(pci_channel_offline(ha->pdev) &&
4436 ha->flags.pci_channel_io_perm_failure)) {
4437 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4438 status = 0;
4439 return status;
4440 }
4441
73208dfd 4442 ha->isp_ops->get_flash_version(vha, req->ring);
30c47662 4443
e315cd28 4444 ha->isp_ops->nvram_config(vha);
1da177e4 4445
e315cd28
AC		 4446 if (!qla2x00_restart_isp(vha)) {
4447 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4 4448
e315cd28 4449 if (!atomic_read(&vha->loop_down_timer)) {
1da177e4
LT		 4450 /*
4451 * Issue marker command only when we are going
4452 * to start the I/O .
4453 */
e315cd28 4454 vha->marker_needed = 1;
1da177e4
LT		 4455 }
4456
e315cd28 4457 vha->flags.online = 1;
1da177e4 4458
fd34f556 4459 ha->isp_ops->enable_intrs(ha);
1da177e4 4460
fa2a1ce5 4461 ha->isp_abort_cnt = 0;
e315cd28 4462 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
476e8978 4463
6246b8a1
GM		 4464 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
4465 qla2x00_get_fw_version(vha);
df613b96
AV		 4466 if (ha->fce) {
4467 ha->flags.fce_enabled = 1;
4468 memset(ha->fce, 0,
4469 fce_calc_size(ha->fce_bufs));
e315cd28 4470 rval = qla2x00_enable_fce_trace(vha,
df613b96
AV		 4471 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
4472 &ha->fce_bufs);
4473 if (rval) {
7c3df132 4474 ql_log(ql_log_warn, vha, 0x8033,
df613b96
AV		 4475 "Unable to reinitialize FCE "
4476 "(%d).\n", rval);
4477 ha->flags.fce_enabled = 0;
4478 }
4479 }
436a7b11
AV		 4480
4481 if (ha->eft) {
4482 memset(ha->eft, 0, EFT_SIZE);
e315cd28 4483 rval = qla2x00_enable_eft_trace(vha,
436a7b11
AV		 4484 ha->eft_dma, EFT_NUM_BUFFERS);
4485 if (rval) {
7c3df132 4486 ql_log(ql_log_warn, vha, 0x8034,
436a7b11
AV		 4487 "Unable to reinitialize EFT "
4488 "(%d).\n", rval);
4489 }
4490 }
1da177e4 4491 } else { /* failed the ISP abort */
e315cd28
AC		 4492 vha->flags.online = 1;
4493 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
1da177e4 4494 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 4495 ql_log(ql_log_fatal, vha, 0x8035,
4496 "ISP error recover failed - "
4497 "board disabled.\n");
fa2a1ce5 4498 /*
1da177e4
LT		 4499 * The next call disables the board
4500 * completely.
4501 */
e315cd28
AC		 4502 ha->isp_ops->reset_adapter(vha);
4503 vha->flags.online = 0;
1da177e4 4504 clear_bit(ISP_ABORT_RETRY,
e315cd28 4505 &vha->dpc_flags);
1da177e4
LT		 4506 status = 0;
4507 } else { /* schedule another ISP abort */
4508 ha->isp_abort_cnt--;
7c3df132
SK		 4509 ql_dbg(ql_dbg_taskm, vha, 0x8020,
4510 "ISP abort - retry remaining %d.\n",
4511 ha->isp_abort_cnt);
1da177e4
LT		 4512 status = 1;
4513 }
4514 } else {
4515 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 4516 ql_dbg(ql_dbg_taskm, vha, 0x8021,
4517 "ISP error recovery - retrying (%d) "
4518 "more times.\n", ha->isp_abort_cnt);
e315cd28 4519 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1da177e4
LT		 4520 status = 1;
4521 }
4522 }
fa2a1ce5 4523
1da177e4
LT		 4524 }
4525
e315cd28 4526 if (!status) {
7c3df132 4527 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
feafb7b1
AE		 4528
4529 spin_lock_irqsave(&ha->vport_slock, flags);
4530 list_for_each_entry(vp, &ha->vp_list, list) {
4531 if (vp->vp_idx) {
4532 atomic_inc(&vp->vref_count);
4533 spin_unlock_irqrestore(&ha->vport_slock, flags);
4534
e315cd28 4535 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 4536
4537 spin_lock_irqsave(&ha->vport_slock, flags);
4538 atomic_dec(&vp->vref_count);
4539 }
e315cd28 4540 }
feafb7b1
AE		 4541 spin_unlock_irqrestore(&ha->vport_slock, flags);
4542
7d613ac6
SV		 4543 if (IS_QLA8031(ha)) {
4544 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
4545 "Setting back fcoe driver presence.\n");
4546 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
4547 ql_dbg(ql_dbg_p3p, vha, 0xb074,
4548 "Error while setting DRV-Presence.\n");
4549 }
e315cd28 4550 } else {
d8424f68
JP		 4551 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
4552 __func__);
1da177e4
LT		 4553 }
4554
4555 return(status);
4556}
4557
4558/*
4559* qla2x00_restart_isp
4560* restarts the ISP after a reset
4561*
4562* Input:
4563* ha = adapter block pointer.
4564*
4565* Returns:
4566* 0 = success
4567*/
4568static int
e315cd28 4569qla2x00_restart_isp(scsi_qla_host_t *vha)
1da177e4 4570{
c6b2fca8 4571 int status = 0;
1da177e4 4572 uint32_t wait_time;
e315cd28 4573 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 4574 struct req_que *req = ha->req_q_map[0];
4575 struct rsp_que *rsp = ha->rsp_q_map[0];
2d70c103 4576 unsigned long flags;
1da177e4
LT		 4577
4578 /* If firmware needs to be loaded */
e315cd28
AC		 4579 if (qla2x00_isp_firmware(vha)) {
4580 vha->flags.online = 0;
4581 status = ha->isp_ops->chip_diag(vha);
4582 if (!status)
4583 status = qla2x00_setup_chip(vha);
1da177e4
LT		 4584 }
4585
e315cd28
AC		 4586 if (!status && !(status = qla2x00_init_rings(vha))) {
4587 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
2533cf67 4588 ha->flags.chip_reset_done = 1;
73208dfd
AC		 4589 /* Initialize the queues in use */
4590 qla25xx_init_queues(ha);
4591
e315cd28
AC		 4592 status = qla2x00_fw_ready(vha);
4593 if (!status) {
7c3df132
SK		 4594 ql_dbg(ql_dbg_taskm, vha, 0x8031,
4595 "Start configure loop status = %d.\n", status);
0107109e
AV		 4596
4597 /* Issue a marker after FW becomes ready. */
73208dfd 4598 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
0107109e 4599
e315cd28 4600 vha->flags.online = 1;
2d70c103
NB		 4601
4602 /*
4603 * Process any ATIO queue entries that came in
4604 * while we weren't online.
4605 */
4606 spin_lock_irqsave(&ha->hardware_lock, flags);
4607 if (qla_tgt_mode_enabled(vha))
4608 qlt_24xx_process_atio_queue(vha);
4609 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4610
1da177e4
LT		 4611 /* Wait at most MAX_TARGET RSCNs for a stable link. */
4612 wait_time = 256;
4613 do {
e315cd28
AC		 4614 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
4615 qla2x00_configure_loop(vha);
1da177e4 4616 wait_time--;
e315cd28
AC		 4617 } while (!atomic_read(&vha->loop_down_timer) &&
4618 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
4619 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
4620 &vha->dpc_flags)));
1da177e4
LT		 4621 }
4622
4623 /* if no cable then assume it's good */
e315cd28 4624 if ((vha->device_flags & DFLG_NO_CABLE))
1da177e4
LT		 4625 status = 0;
4626
7c3df132
SK		 4627 ql_dbg(ql_dbg_taskm, vha, 0x8032,
4628 "Configure loop done, status = 0x%x.\n", status);
1da177e4
LT		 4629 }
4630 return (status);
4631}
4632
73208dfd
AC		 4633static int
4634qla25xx_init_queues(struct qla_hw_data *ha)
4635{
4636 struct rsp_que *rsp = NULL;
4637 struct req_que *req = NULL;
4638 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
4639 int ret = -1;
4640 int i;
4641
2afa19a9 4642 for (i = 1; i < ha->max_rsp_queues; i++) {
73208dfd
AC		 4643 rsp = ha->rsp_q_map[i];
4644 if (rsp) {
4645 rsp->options &= ~BIT_0;
618a7523 4646 ret = qla25xx_init_rsp_que(base_vha, rsp);
73208dfd 4647 if (ret != QLA_SUCCESS)
7c3df132
SK		 4648 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
4649 "%s Rsp que: %d init failed.\n",
4650 __func__, rsp->id);
73208dfd 4651 else
7c3df132
SK		 4652 ql_dbg(ql_dbg_init, base_vha, 0x0100,
4653 "%s Rsp que: %d inited.\n",
4654 __func__, rsp->id);
73208dfd 4655 }
2afa19a9
AC		 4656 }
4657 for (i = 1; i < ha->max_req_queues; i++) {
73208dfd
AC		 4658 req = ha->req_q_map[i];
4659 if (req) {
29bdccbe 4660 /* Clear outstanding commands array. */
73208dfd 4661 req->options &= ~BIT_0;
618a7523 4662 ret = qla25xx_init_req_que(base_vha, req);
73208dfd 4663 if (ret != QLA_SUCCESS)
7c3df132
SK		 4664 ql_dbg(ql_dbg_init, base_vha, 0x0101,
4665 "%s Req que: %d init failed.\n",
4666 __func__, req->id);
73208dfd 4667 else
7c3df132
SK		 4668 ql_dbg(ql_dbg_init, base_vha, 0x0102,
4669 "%s Req que: %d inited.\n",
4670 __func__, req->id);
73208dfd
AC		 4671 }
4672 }
4673 return ret;
4674}
4675
1da177e4
LT		 4676/*
4677* qla2x00_reset_adapter
4678* Reset adapter.
4679*
4680* Input:
4681* ha = adapter block pointer.
4682*/
abbd8870 4683void
e315cd28 4684qla2x00_reset_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 4685{
4686 unsigned long flags = 0;
e315cd28 4687 struct qla_hw_data *ha = vha->hw;
3d71644c 4688 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 4689
e315cd28 4690 vha->flags.online = 0;
fd34f556 4691 ha->isp_ops->disable_intrs(ha);
1da177e4 4692
1da177e4
LT		 4693 spin_lock_irqsave(&ha->hardware_lock, flags);
4694 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
4695 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4696 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
4697 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4698 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4699}
0107109e
AV		 4700
4701void
e315cd28 4702qla24xx_reset_adapter(scsi_qla_host_t *vha)
0107109e
AV		 4703{
4704 unsigned long flags = 0;
e315cd28 4705 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 4706 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
4707
a9083016
GM		 4708 if (IS_QLA82XX(ha))
4709 return;
4710
e315cd28 4711 vha->flags.online = 0;
fd34f556 4712 ha->isp_ops->disable_intrs(ha);
0107109e
AV		 4713
4714 spin_lock_irqsave(&ha->hardware_lock, flags);
4715 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
4716 RD_REG_DWORD(&reg->hccr);
4717 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
4718 RD_REG_DWORD(&reg->hccr);
4719 spin_unlock_irqrestore(&ha->hardware_lock, flags);
09ff36d3
AV		 4720
4721 if (IS_NOPOLLING_TYPE(ha))
4722 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 4723}
4724
4e08df3f
DM		 4725/* On sparc systems, obtain port and node WWN from firmware
4726 * properties.
4727 */
e315cd28
AC		 4728static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
4729 struct nvram_24xx *nv)
4e08df3f
DM		 4730{
4731#ifdef CONFIG_SPARC
e315cd28 4732 struct qla_hw_data *ha = vha->hw;
4e08df3f 4733 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 4734 struct device_node *dp = pci_device_to_OF_node(pdev);
4735 const u8 *val;
4e08df3f
DM		 4736 int len;
4737
4738 val = of_get_property(dp, "port-wwn", &len);
4739 if (val && len >= WWN_SIZE)
4740 memcpy(nv->port_name, val, WWN_SIZE);
4741
4742 val = of_get_property(dp, "node-wwn", &len);
4743 if (val && len >= WWN_SIZE)
4744 memcpy(nv->node_name, val, WWN_SIZE);
4745#endif
4746}
4747
0107109e 4748int
e315cd28 4749qla24xx_nvram_config(scsi_qla_host_t *vha)
0107109e 4750{
4e08df3f 4751 int rval;
0107109e
AV		 4752 struct init_cb_24xx *icb;
4753 struct nvram_24xx *nv;
4754 uint32_t *dptr;
4755 uint8_t *dptr1, *dptr2;
4756 uint32_t chksum;
4757 uint16_t cnt;
e315cd28 4758 struct qla_hw_data *ha = vha->hw;
0107109e 4759
4e08df3f 4760 rval = QLA_SUCCESS;
0107109e 4761 icb = (struct init_cb_24xx *)ha->init_cb;
281afe19 4762 nv = ha->nvram;
0107109e
AV		 4763
4764 /* Determine NVRAM starting address. */
e5b68a61
AC		 4765 if (ha->flags.port0) {
4766 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
4767 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
4768 } else {
0107109e 4769 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
6f641790 4770 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
4771 }
e5b68a61
AC		 4772 ha->nvram_size = sizeof(struct nvram_24xx);
4773 ha->vpd_size = FA_NVRAM_VPD_SIZE;
a9083016
GM		 4774 if (IS_QLA82XX(ha))
4775 ha->vpd_size = FA_VPD_SIZE_82XX;
0107109e 4776
281afe19
SJ		 4777 /* Get VPD data into cache */
4778 ha->vpd = ha->nvram + VPD_OFFSET;
e315cd28 4779 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
281afe19
SJ		 4780 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
4781
4782 /* Get NVRAM data into cache and calculate checksum. */
0107109e 4783 dptr = (uint32_t *)nv;
e315cd28 4784 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
0107109e
AV		 4785 ha->nvram_size);
4786 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
4787 chksum += le32_to_cpu(*dptr++);
4788
7c3df132
SK		 4789 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
4790 "Contents of NVRAM\n");
4791 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
4792 (uint8_t *)nv, ha->nvram_size);
0107109e
AV		 4793
4794 /* Bad NVRAM data, set defaults parameters. */
4795 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
4796 || nv->id[3] != ' ' ||
4797 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
4798 /* Reset NVRAM data. */
7c3df132 4799 ql_log(ql_log_warn, vha, 0x006b,
9e336520 4800 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132
SK		 4801 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
4802 ql_log(ql_log_warn, vha, 0x006c,
4803 "Falling back to functioning (yet invalid -- WWPN) "
4804 "defaults.\n");
4e08df3f
DM		 4805
4806 /*
4807 * Set default initialization control block.
4808 */
4809 memset(nv, 0, ha->nvram_size);
4810 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
4811 nv->version = __constant_cpu_to_le16(ICB_VERSION);
4812 nv->frame_payload_size = __constant_cpu_to_le16(2048);
4813 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4814 nv->exchange_count = __constant_cpu_to_le16(0);
4815 nv->hard_address = __constant_cpu_to_le16(124);
4816 nv->port_name[0] = 0x21;
e5b68a61 4817 nv->port_name[1] = 0x00 + ha->port_no;
4e08df3f
DM		 4818 nv->port_name[2] = 0x00;
4819 nv->port_name[3] = 0xe0;
4820 nv->port_name[4] = 0x8b;
4821 nv->port_name[5] = 0x1c;
4822 nv->port_name[6] = 0x55;
4823 nv->port_name[7] = 0x86;
4824 nv->node_name[0] = 0x20;
4825 nv->node_name[1] = 0x00;
4826 nv->node_name[2] = 0x00;
4827 nv->node_name[3] = 0xe0;
4828 nv->node_name[4] = 0x8b;
4829 nv->node_name[5] = 0x1c;
4830 nv->node_name[6] = 0x55;
4831 nv->node_name[7] = 0x86;
e315cd28 4832 qla24xx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 4833 nv->login_retry_count = __constant_cpu_to_le16(8);
4834 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
4835 nv->login_timeout = __constant_cpu_to_le16(0);
4836 nv->firmware_options_1 =
4837 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
4838 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
4839 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
4840 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
4841 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
4842 nv->efi_parameters = __constant_cpu_to_le32(0);
4843 nv->reset_delay = 5;
4844 nv->max_luns_per_target = __constant_cpu_to_le16(128);
4845 nv->port_down_retry_count = __constant_cpu_to_le16(30);
4846 nv->link_down_timeout = __constant_cpu_to_le16(30);
4847
4848 rval = 1;
0107109e
AV		 4849 }
4850
2d70c103
NB		 4851 if (!qla_ini_mode_enabled(vha)) {
4852 /* Don't enable full login after initial LIP */
4853 nv->firmware_options_1 &= __constant_cpu_to_le32(~BIT_13);
4854 /* Don't enable LIP full login for initiator */
4855 nv->host_p &= __constant_cpu_to_le32(~BIT_10);
4856 }
4857
4858 qlt_24xx_config_nvram_stage1(vha, nv);
4859
0107109e 4860 /* Reset Initialization control block */
e315cd28 4861 memset(icb, 0, ha->init_cb_size);
0107109e
AV		 4862
4863 /* Copy 1st segment. */
4864 dptr1 = (uint8_t *)icb;
4865 dptr2 = (uint8_t *)&nv->version;
4866 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
4867 while (cnt--)
4868 *dptr1++ = *dptr2++;
4869
4870 icb->login_retry_count = nv->login_retry_count;
3ea66e28 4871 icb->link_down_on_nos = nv->link_down_on_nos;
0107109e
AV		 4872
4873 /* Copy 2nd segment. */
4874 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
4875 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
4876 cnt = (uint8_t *)&icb->reserved_3 -
4877 (uint8_t *)&icb->interrupt_delay_timer;
4878 while (cnt--)
4879 *dptr1++ = *dptr2++;
4880
4881 /*
4882 * Setup driver NVRAM options.
4883 */
e315cd28 4884 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9bb9fcf2 4885 "QLA2462");
0107109e 4886
2d70c103
NB		 4887 qlt_24xx_config_nvram_stage2(vha, icb);
4888
5341e868 4889 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
2d70c103 4890 /* Use alternate WWN? */
5341e868
AV		 4891 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
4892 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
4893 }
4894
0107109e 4895 /* Prepare nodename */
fd0e7e4d 4896 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
0107109e
AV		 4897 /*
4898 * Firmware will apply the following mask if the nodename was
4899 * not provided.
4900 */
4901 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
4902 icb->node_name[0] &= 0xF0;
4903 }
4904
4905 /* Set host adapter parameters. */
4906 ha->flags.disable_risc_code_load = 0;
0c8c39af
AV		 4907 ha->flags.enable_lip_reset = 0;
4908 ha->flags.enable_lip_full_login =
4909 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
4910 ha->flags.enable_target_reset =
4911 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
0107109e 4912 ha->flags.enable_led_scheme = 0;
d4c760c2 4913 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
0107109e 4914
fd0e7e4d
AV		 4915 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
4916 (BIT_6 | BIT_5 | BIT_4)) >> 4;
0107109e
AV		 4917
4918 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
4919 sizeof(ha->fw_seriallink_options24));
4920
4921 /* save HBA serial number */
4922 ha->serial0 = icb->port_name[5];
4923 ha->serial1 = icb->port_name[6];
4924 ha->serial2 = icb->port_name[7];
e315cd28
AC		 4925 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
4926 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
0107109e 4927
bc8fb3cb 4928 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4929
0107109e
AV		 4930 ha->retry_count = le16_to_cpu(nv->login_retry_count);
4931
4932 /* Set minimum login_timeout to 4 seconds. */
4933 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
4934 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
4935 if (le16_to_cpu(nv->login_timeout) < 4)
4936 nv->login_timeout = __constant_cpu_to_le16(4);
4937 ha->login_timeout = le16_to_cpu(nv->login_timeout);
c6852c4c 4938 icb->login_timeout = nv->login_timeout;
0107109e 4939
00a537b8
AV		 4940 /* Set minimum RATOV to 100 tenths of a second. */
4941 ha->r_a_tov = 100;
0107109e
AV		 4942
4943 ha->loop_reset_delay = nv->reset_delay;
4944
4945 /* Link Down Timeout = 0:
4946 *
4947 * When Port Down timer expires we will start returning
4948 * I/O's to OS with "DID_NO_CONNECT".
4949 *
4950 * Link Down Timeout != 0:
4951 *
4952 * The driver waits for the link to come up after link down
4953 * before returning I/Os to OS with "DID_NO_CONNECT".
4954 */
4955 if (le16_to_cpu(nv->link_down_timeout) == 0) {
4956 ha->loop_down_abort_time =
4957 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
4958 } else {
4959 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
4960 ha->loop_down_abort_time =
4961 (LOOP_DOWN_TIME - ha->link_down_timeout);
4962 }
4963
4964 /* Need enough time to try and get the port back. */
4965 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
4966 if (qlport_down_retry)
4967 ha->port_down_retry_count = qlport_down_retry;
4968
4969 /* Set login_retry_count */
4970 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
4971 if (ha->port_down_retry_count ==
4972 le16_to_cpu(nv->port_down_retry_count) &&
4973 ha->port_down_retry_count > 3)
4974 ha->login_retry_count = ha->port_down_retry_count;
4975 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
4976 ha->login_retry_count = ha->port_down_retry_count;
4977 if (ql2xloginretrycount)
4978 ha->login_retry_count = ql2xloginretrycount;
4979
4fdfefe5 4980 /* Enable ZIO. */
e315cd28 4981 if (!vha->flags.init_done) {
4fdfefe5
AV		 4982 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
4983 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
4984 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
4985 le16_to_cpu(icb->interrupt_delay_timer): 2;
4986 }
4987 icb->firmware_options_2 &= __constant_cpu_to_le32(
4988 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
e315cd28 4989 vha->flags.process_response_queue = 0;
4fdfefe5 4990 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d 4991 ha->zio_mode = QLA_ZIO_MODE_6;
4992
7c3df132 4993 ql_log(ql_log_info, vha, 0x006f,
4fdfefe5
AV		 4994 "ZIO mode %d enabled; timer delay (%d us).\n",
4995 ha->zio_mode, ha->zio_timer * 100);
4996
4997 icb->firmware_options_2 |= cpu_to_le32(
4998 (uint32_t)ha->zio_mode);
4999 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
e315cd28 5000 vha->flags.process_response_queue = 1;
4fdfefe5
AV		 5001 }
5002
4e08df3f 5003 if (rval) {
7c3df132
SK		 5004 ql_log(ql_log_warn, vha, 0x0070,
5005 "NVRAM configuration failed.\n");
4e08df3f
DM		 5006 }
5007 return (rval);
0107109e
AV		 5008}
5009
413975a0 5010static int
cbc8eb67
AV		 5011qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
5012 uint32_t faddr)
d1c61909 5013{
73208dfd 5014 int rval = QLA_SUCCESS;
d1c61909 5015 int segments, fragment;
d1c61909
AV		 5016 uint32_t *dcode, dlen;
5017 uint32_t risc_addr;
5018 uint32_t risc_size;
5019 uint32_t i;
e315cd28 5020 struct qla_hw_data *ha = vha->hw;
73208dfd 5021 struct req_que *req = ha->req_q_map[0];
eaac30be 5022
7c3df132 5023 ql_dbg(ql_dbg_init, vha, 0x008b,
cfb0919c 5024 "FW: Loading firmware from flash (%x).\n", faddr);
eaac30be 5025
d1c61909
AV		 5026 rval = QLA_SUCCESS;
5027
5028 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5029 dcode = (uint32_t *)req->ring;
d1c61909
AV		 5030 *srisc_addr = 0;
5031
5032 /* Validate firmware image by checking version. */
e315cd28 5033 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
d1c61909
AV		 5034 for (i = 0; i < 4; i++)
5035 dcode[i] = be32_to_cpu(dcode[i]);
5036 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5037 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5038 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5039 dcode[3] == 0)) {
7c3df132
SK		 5040 ql_log(ql_log_fatal, vha, 0x008c,
5041 "Unable to verify the integrity of flash firmware "
5042 "image.\n");
5043 ql_log(ql_log_fatal, vha, 0x008d,
5044 "Firmware data: %08x %08x %08x %08x.\n",
5045 dcode[0], dcode[1], dcode[2], dcode[3]);
d1c61909
AV		 5046
5047 return QLA_FUNCTION_FAILED;
5048 }
5049
5050 while (segments && rval == QLA_SUCCESS) {
5051 /* Read segment's load information. */
e315cd28 5052 qla24xx_read_flash_data(vha, dcode, faddr, 4);
d1c61909
AV		 5053
5054 risc_addr = be32_to_cpu(dcode[2]);
5055 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5056 risc_size = be32_to_cpu(dcode[3]);
5057
5058 fragment = 0;
5059 while (risc_size > 0 && rval == QLA_SUCCESS) {
5060 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5061 if (dlen > risc_size)
5062 dlen = risc_size;
5063
7c3df132
SK		 5064 ql_dbg(ql_dbg_init, vha, 0x008e,
5065 "Loading risc segment@ risc addr %x "
5066 "number of dwords 0x%x offset 0x%x.\n",
5067 risc_addr, dlen, faddr);
d1c61909 5068
e315cd28 5069 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
d1c61909
AV		 5070 for (i = 0; i < dlen; i++)
5071 dcode[i] = swab32(dcode[i]);
5072
73208dfd 5073 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
d1c61909
AV		 5074 dlen);
5075 if (rval) {
7c3df132
SK		 5076 ql_log(ql_log_fatal, vha, 0x008f,
5077 "Failed to load segment %d of firmware.\n",
5078 fragment);
d1c61909
AV		 5079 break;
5080 }
5081
5082 faddr += dlen;
5083 risc_addr += dlen;
5084 risc_size -= dlen;
5085 fragment++;
5086 }
5087
5088 /* Next segment. */
5089 segments--;
5090 }
5091
5092 return rval;
5093}
5094
e9454a88 5095#define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
d1c61909 5096
0107109e 5097int
e315cd28 5098qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5433383e
AV		 5099{
5100 int rval;
5101 int i, fragment;
5102 uint16_t *wcode, *fwcode;
5103 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
5104 struct fw_blob *blob;
e315cd28 5105 struct qla_hw_data *ha = vha->hw;
73208dfd 5106 struct req_que *req = ha->req_q_map[0];
5433383e
AV		 5107
5108 /* Load firmware blob. */
e315cd28 5109 blob = qla2x00_request_firmware(vha);
5433383e 5110 if (!blob) {
7c3df132
SK		 5111 ql_log(ql_log_info, vha, 0x0083,
5112 "Fimware image unavailable.\n");
5113 ql_log(ql_log_info, vha, 0x0084,
5114 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5433383e
AV		 5115 return QLA_FUNCTION_FAILED;
5116 }
5117
5118 rval = QLA_SUCCESS;
5119
73208dfd 5120 wcode = (uint16_t *)req->ring;
5433383e
AV		 5121 *srisc_addr = 0;
5122 fwcode = (uint16_t *)blob->fw->data;
5123 fwclen = 0;
5124
5125 /* Validate firmware image by checking version. */
5126 if (blob->fw->size < 8 * sizeof(uint16_t)) {
7c3df132
SK		 5127 ql_log(ql_log_fatal, vha, 0x0085,
5128 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e
AV		 5129 blob->fw->size);
5130 goto fail_fw_integrity;
5131 }
5132 for (i = 0; i < 4; i++)
5133 wcode[i] = be16_to_cpu(fwcode[i + 4]);
5134 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
5135 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
5136 wcode[2] == 0 && wcode[3] == 0)) {
7c3df132
SK		 5137 ql_log(ql_log_fatal, vha, 0x0086,
5138 "Unable to verify integrity of firmware image.\n");
5139 ql_log(ql_log_fatal, vha, 0x0087,
5140 "Firmware data: %04x %04x %04x %04x.\n",
5141 wcode[0], wcode[1], wcode[2], wcode[3]);
5433383e
AV		 5142 goto fail_fw_integrity;
5143 }
5144
5145 seg = blob->segs;
5146 while (*seg && rval == QLA_SUCCESS) {
5147 risc_addr = *seg;
5148 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
5149 risc_size = be16_to_cpu(fwcode[3]);
5150
5151 /* Validate firmware image size. */
5152 fwclen += risc_size * sizeof(uint16_t);
5153 if (blob->fw->size < fwclen) {
7c3df132 5154 ql_log(ql_log_fatal, vha, 0x0088,
5433383e 5155 "Unable to verify integrity of firmware image "
7c3df132 5156 "(%Zd).\n", blob->fw->size);
5433383e
AV		 5157 goto fail_fw_integrity;
5158 }
5159
5160 fragment = 0;
5161 while (risc_size > 0 && rval == QLA_SUCCESS) {
5162 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
5163 if (wlen > risc_size)
5164 wlen = risc_size;
7c3df132
SK		 5165 ql_dbg(ql_dbg_init, vha, 0x0089,
5166 "Loading risc segment@ risc addr %x number of "
5167 "words 0x%x.\n", risc_addr, wlen);
5433383e
AV		 5168
5169 for (i = 0; i < wlen; i++)
5170 wcode[i] = swab16(fwcode[i]);
5171
73208dfd 5172 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5433383e
AV		 5173 wlen);
5174 if (rval) {
7c3df132
SK		 5175 ql_log(ql_log_fatal, vha, 0x008a,
5176 "Failed to load segment %d of firmware.\n",
5177 fragment);
5433383e
AV		 5178 break;
5179 }
5180
5181 fwcode += wlen;
5182 risc_addr += wlen;
5183 risc_size -= wlen;
5184 fragment++;
5185 }
5186
5187 /* Next segment. */
5188 seg++;
5189 }
5190 return rval;
5191
5192fail_fw_integrity:
5193 return QLA_FUNCTION_FAILED;
5194}
5195
eaac30be
AV		 5196static int
5197qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
0107109e
AV		 5198{
5199 int rval;
5200 int segments, fragment;
5201 uint32_t *dcode, dlen;
5202 uint32_t risc_addr;
5203 uint32_t risc_size;
5204 uint32_t i;
5433383e 5205 struct fw_blob *blob;
0107109e 5206 uint32_t *fwcode, fwclen;
e315cd28 5207 struct qla_hw_data *ha = vha->hw;
73208dfd 5208 struct req_que *req = ha->req_q_map[0];
0107109e 5209
5433383e 5210 /* Load firmware blob. */
e315cd28 5211 blob = qla2x00_request_firmware(vha);
5433383e 5212 if (!blob) {
7c3df132
SK		 5213 ql_log(ql_log_warn, vha, 0x0090,
5214 "Fimware image unavailable.\n");
5215 ql_log(ql_log_warn, vha, 0x0091,
5216 "Firmware images can be retrieved from: "
5217 QLA_FW_URL ".\n");
d1c61909 5218
eaac30be 5219 return QLA_FUNCTION_FAILED;
0107109e
AV		 5220 }
5221
cfb0919c
CD		 5222 ql_dbg(ql_dbg_init, vha, 0x0092,
5223 "FW: Loading via request-firmware.\n");
eaac30be 5224
0107109e
AV		 5225 rval = QLA_SUCCESS;
5226
5227 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5228 dcode = (uint32_t *)req->ring;
0107109e 5229 *srisc_addr = 0;
5433383e 5230 fwcode = (uint32_t *)blob->fw->data;
0107109e
AV		 5231 fwclen = 0;
5232
5233 /* Validate firmware image by checking version. */
5433383e 5234 if (blob->fw->size < 8 * sizeof(uint32_t)) {
7c3df132
SK		 5235 ql_log(ql_log_fatal, vha, 0x0093,
5236 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e 5237 blob->fw->size);
0107109e
AV		 5238 goto fail_fw_integrity;
5239 }
5240 for (i = 0; i < 4; i++)
5241 dcode[i] = be32_to_cpu(fwcode[i + 4]);
5242 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5243 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5244 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5245 dcode[3] == 0)) {
7c3df132
SK		 5246 ql_log(ql_log_fatal, vha, 0x0094,
5247 "Unable to verify integrity of firmware image (%Zd).\n",
5248 blob->fw->size);
5249 ql_log(ql_log_fatal, vha, 0x0095,
5250 "Firmware data: %08x %08x %08x %08x.\n",
5251 dcode[0], dcode[1], dcode[2], dcode[3]);
0107109e
AV		 5252 goto fail_fw_integrity;
5253 }
5254
5255 while (segments && rval == QLA_SUCCESS) {
5256 risc_addr = be32_to_cpu(fwcode[2]);
5257 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5258 risc_size = be32_to_cpu(fwcode[3]);
5259
5260 /* Validate firmware image size. */
5261 fwclen += risc_size * sizeof(uint32_t);
5433383e 5262 if (blob->fw->size < fwclen) {
7c3df132 5263 ql_log(ql_log_fatal, vha, 0x0096,
5433383e 5264 "Unable to verify integrity of firmware image "
7c3df132 5265 "(%Zd).\n", blob->fw->size);
5433383e 5266
0107109e
AV		 5267 goto fail_fw_integrity;
5268 }
5269
5270 fragment = 0;
5271 while (risc_size > 0 && rval == QLA_SUCCESS) {
5272 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5273 if (dlen > risc_size)
5274 dlen = risc_size;
5275
7c3df132
SK		 5276 ql_dbg(ql_dbg_init, vha, 0x0097,
5277 "Loading risc segment@ risc addr %x "
5278 "number of dwords 0x%x.\n", risc_addr, dlen);
0107109e
AV		 5279
5280 for (i = 0; i < dlen; i++)
5281 dcode[i] = swab32(fwcode[i]);
5282
73208dfd 5283 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
590f98e5 5284 dlen);
0107109e 5285 if (rval) {
7c3df132
SK		 5286 ql_log(ql_log_fatal, vha, 0x0098,
5287 "Failed to load segment %d of firmware.\n",
5288 fragment);
0107109e
AV		 5289 break;
5290 }
5291
5292 fwcode += dlen;
5293 risc_addr += dlen;
5294 risc_size -= dlen;
5295 fragment++;
5296 }
5297
5298 /* Next segment. */
5299 segments--;
5300 }
0107109e
AV		 5301 return rval;
5302
5303fail_fw_integrity:
0107109e 5304 return QLA_FUNCTION_FAILED;
0107109e 5305}
18c6c127 5306
eaac30be
AV		 5307int
5308qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5309{
5310 int rval;
5311
e337d907
AV		 5312 if (ql2xfwloadbin == 1)
5313 return qla81xx_load_risc(vha, srisc_addr);
5314
eaac30be
AV		 5315 /*
5316 * FW Load priority:
5317 * 1) Firmware via request-firmware interface (.bin file).
5318 * 2) Firmware residing in flash.
5319 */
5320 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5321 if (rval == QLA_SUCCESS)
5322 return rval;
5323
cbc8eb67
AV		 5324 return qla24xx_load_risc_flash(vha, srisc_addr,
5325 vha->hw->flt_region_fw);
eaac30be
AV		 5326}
5327
5328int
5329qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5330{
5331 int rval;
cbc8eb67 5332 struct qla_hw_data *ha = vha->hw;
eaac30be 5333
e337d907 5334 if (ql2xfwloadbin == 2)
cbc8eb67 5335 goto try_blob_fw;
e337d907 5336
eaac30be
AV		 5337 /*
5338 * FW Load priority:
5339 * 1) Firmware residing in flash.
5340 * 2) Firmware via request-firmware interface (.bin file).
cbc8eb67 5341 * 3) Golden-Firmware residing in flash -- limited operation.
eaac30be 5342 */
cbc8eb67 5343 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
eaac30be
AV		 5344 if (rval == QLA_SUCCESS)
5345 return rval;
5346
cbc8eb67
AV		 5347try_blob_fw:
5348 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5349 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
5350 return rval;
5351
7c3df132
SK		 5352 ql_log(ql_log_info, vha, 0x0099,
5353 "Attempting to fallback to golden firmware.\n");
cbc8eb67
AV		 5354 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
5355 if (rval != QLA_SUCCESS)
5356 return rval;
5357
7c3df132 5358 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
cbc8eb67 5359 ha->flags.running_gold_fw = 1;
cbc8eb67 5360 return rval;
eaac30be
AV		 5361}
5362
18c6c127 5363void
e315cd28 5364qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
18c6c127
AV		 5365{
5366 int ret, retries;
e315cd28 5367 struct qla_hw_data *ha = vha->hw;
18c6c127 5368
85880801
AV		 5369 if (ha->flags.pci_channel_io_perm_failure)
5370 return;
e428924c 5371 if (!IS_FWI2_CAPABLE(ha))
18c6c127 5372 return;
75edf81d
AV		 5373 if (!ha->fw_major_version)
5374 return;
18c6c127 5375
e315cd28 5376 ret = qla2x00_stop_firmware(vha);
7c7f1f29 5377 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
b469a7cb 5378 ret != QLA_INVALID_COMMAND && retries ; retries--) {
e315cd28
AC		 5379 ha->isp_ops->reset_chip(vha);
5380 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
18c6c127 5381 continue;
e315cd28 5382 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
18c6c127 5383 continue;
7c3df132
SK		 5384 ql_log(ql_log_info, vha, 0x8015,
5385 "Attempting retry of stop-firmware command.\n");
e315cd28 5386 ret = qla2x00_stop_firmware(vha);
18c6c127
AV		 5387 }
5388}
2c3dfe3f
SJ		 5389
5390int
e315cd28 5391qla24xx_configure_vhba(scsi_qla_host_t *vha)
2c3dfe3f
SJ		 5392{
5393 int rval = QLA_SUCCESS;
0b91d116 5394 int rval2;
2c3dfe3f 5395 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28
AC		 5396 struct qla_hw_data *ha = vha->hw;
5397 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
67c2e93a
AC		 5398 struct req_que *req;
5399 struct rsp_que *rsp;
2c3dfe3f 5400
e315cd28 5401 if (!vha->vp_idx)
2c3dfe3f
SJ		 5402 return -EINVAL;
5403
e315cd28 5404 rval = qla2x00_fw_ready(base_vha);
7163ea81 5405 if (ha->flags.cpu_affinity_enabled)
67c2e93a
AC		 5406 req = ha->req_q_map[0];
5407 else
5408 req = vha->req;
5409 rsp = req->rsp;
5410
2c3dfe3f 5411 if (rval == QLA_SUCCESS) {
e315cd28 5412 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
73208dfd 5413 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
2c3dfe3f
SJ		 5414 }
5415
e315cd28 5416 vha->flags.management_server_logged_in = 0;
2c3dfe3f
SJ		 5417
5418 /* Login to SNS first */
0b91d116
CD		 5419 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
5420 BIT_1);
5421 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
5422 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
5423 ql_dbg(ql_dbg_init, vha, 0x0120,
5424 "Failed SNS login: loop_id=%x, rval2=%d\n",
5425 NPH_SNS, rval2);
5426 else
5427 ql_dbg(ql_dbg_init, vha, 0x0103,
5428 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
5429 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
5430 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
2c3dfe3f
SJ		 5431 return (QLA_FUNCTION_FAILED);
5432 }
5433
e315cd28
AC		 5434 atomic_set(&vha->loop_down_timer, 0);
5435 atomic_set(&vha->loop_state, LOOP_UP);
5436 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5437 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5438 rval = qla2x00_loop_resync(base_vha);
2c3dfe3f
SJ		 5439
5440 return rval;
5441}
4d4df193
HK		 5442
5443/* 84XX Support **************************************************************/
5444
5445static LIST_HEAD(qla_cs84xx_list);
5446static DEFINE_MUTEX(qla_cs84xx_mutex);
5447
5448static struct qla_chip_state_84xx *
e315cd28 5449qla84xx_get_chip(struct scsi_qla_host *vha)
4d4df193
HK		 5450{
5451 struct qla_chip_state_84xx *cs84xx;
e315cd28 5452 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5453
5454 mutex_lock(&qla_cs84xx_mutex);
5455
5456 /* Find any shared 84xx chip. */
5457 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
5458 if (cs84xx->bus == ha->pdev->bus) {
5459 kref_get(&cs84xx->kref);
5460 goto done;
5461 }
5462 }
5463
5464 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
5465 if (!cs84xx)
5466 goto done;
5467
5468 kref_init(&cs84xx->kref);
5469 spin_lock_init(&cs84xx->access_lock);
5470 mutex_init(&cs84xx->fw_update_mutex);
5471 cs84xx->bus = ha->pdev->bus;
5472
5473 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
5474done:
5475 mutex_unlock(&qla_cs84xx_mutex);
5476 return cs84xx;
5477}
5478
5479static void
5480__qla84xx_chip_release(struct kref *kref)
5481{
5482 struct qla_chip_state_84xx *cs84xx =
5483 container_of(kref, struct qla_chip_state_84xx, kref);
5484
5485 mutex_lock(&qla_cs84xx_mutex);
5486 list_del(&cs84xx->list);
5487 mutex_unlock(&qla_cs84xx_mutex);
5488 kfree(cs84xx);
5489}
5490
5491void
e315cd28 5492qla84xx_put_chip(struct scsi_qla_host *vha)
4d4df193 5493{
e315cd28 5494 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5495 if (ha->cs84xx)
5496 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
5497}
5498
5499static int
e315cd28 5500qla84xx_init_chip(scsi_qla_host_t *vha)
4d4df193
HK		 5501{
5502 int rval;
5503 uint16_t status[2];
e315cd28 5504 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5505
5506 mutex_lock(&ha->cs84xx->fw_update_mutex);
5507
e315cd28 5508 rval = qla84xx_verify_chip(vha, status);
4d4df193
HK		 5509
5510 mutex_unlock(&ha->cs84xx->fw_update_mutex);
5511
5512 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
5513 QLA_SUCCESS;
5514}
3a03eb79
AV		 5515
5516/* 81XX Support **************************************************************/
5517
5518int
5519qla81xx_nvram_config(scsi_qla_host_t *vha)
5520{
5521 int rval;
5522 struct init_cb_81xx *icb;
5523 struct nvram_81xx *nv;
5524 uint32_t *dptr;
5525 uint8_t *dptr1, *dptr2;
5526 uint32_t chksum;
5527 uint16_t cnt;
5528 struct qla_hw_data *ha = vha->hw;
5529
5530 rval = QLA_SUCCESS;
5531 icb = (struct init_cb_81xx *)ha->init_cb;
5532 nv = ha->nvram;
5533
5534 /* Determine NVRAM starting address. */
5535 ha->nvram_size = sizeof(struct nvram_81xx);
3a03eb79 5536 ha->vpd_size = FA_NVRAM_VPD_SIZE;
3a03eb79
AV		 5537
5538 /* Get VPD data into cache */
5539 ha->vpd = ha->nvram + VPD_OFFSET;
3d79038f
AV		 5540 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
5541 ha->vpd_size);
3a03eb79
AV		 5542
5543 /* Get NVRAM data into cache and calculate checksum. */
3d79038f 5544 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
3a03eb79 5545 ha->nvram_size);
3d79038f 5546 dptr = (uint32_t *)nv;
3a03eb79
AV		 5547 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
5548 chksum += le32_to_cpu(*dptr++);
5549
7c3df132
SK		 5550 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
5551 "Contents of NVRAM:\n");
5552 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
5553 (uint8_t *)nv, ha->nvram_size);
3a03eb79
AV		 5554
5555 /* Bad NVRAM data, set defaults parameters. */
5556 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
5557 || nv->id[3] != ' ' ||
5558 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
5559 /* Reset NVRAM data. */
7c3df132 5560 ql_log(ql_log_info, vha, 0x0073,
9e336520 5561 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132 5562 "version=0x%x.\n", chksum, nv->id[0],
3a03eb79 5563 le16_to_cpu(nv->nvram_version));
7c3df132
SK		 5564 ql_log(ql_log_info, vha, 0x0074,
5565 "Falling back to functioning (yet invalid -- WWPN) "
5566 "defaults.\n");
3a03eb79
AV		 5567
5568 /*
5569 * Set default initialization control block.
5570 */
5571 memset(nv, 0, ha->nvram_size);
5572 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
5573 nv->version = __constant_cpu_to_le16(ICB_VERSION);
5574 nv->frame_payload_size = __constant_cpu_to_le16(2048);
5575 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5576 nv->exchange_count = __constant_cpu_to_le16(0);
5577 nv->port_name[0] = 0x21;
e5b68a61 5578 nv->port_name[1] = 0x00 + ha->port_no;
3a03eb79
AV		 5579 nv->port_name[2] = 0x00;
5580 nv->port_name[3] = 0xe0;
5581 nv->port_name[4] = 0x8b;
5582 nv->port_name[5] = 0x1c;
5583 nv->port_name[6] = 0x55;
5584 nv->port_name[7] = 0x86;
5585 nv->node_name[0] = 0x20;
5586 nv->node_name[1] = 0x00;
5587 nv->node_name[2] = 0x00;
5588 nv->node_name[3] = 0xe0;
5589 nv->node_name[4] = 0x8b;
5590 nv->node_name[5] = 0x1c;
5591 nv->node_name[6] = 0x55;
5592 nv->node_name[7] = 0x86;
5593 nv->login_retry_count = __constant_cpu_to_le16(8);
5594 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
5595 nv->login_timeout = __constant_cpu_to_le16(0);
5596 nv->firmware_options_1 =
5597 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
5598 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
5599 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
5600 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
5601 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
5602 nv->efi_parameters = __constant_cpu_to_le32(0);
5603 nv->reset_delay = 5;
5604 nv->max_luns_per_target = __constant_cpu_to_le16(128);
5605 nv->port_down_retry_count = __constant_cpu_to_le16(30);
6246b8a1 5606 nv->link_down_timeout = __constant_cpu_to_le16(180);
eeebcc92 5607 nv->enode_mac[0] = 0x00;
6246b8a1
GM		 5608 nv->enode_mac[1] = 0xC0;
5609 nv->enode_mac[2] = 0xDD;
3a03eb79
AV		 5610 nv->enode_mac[3] = 0x04;
5611 nv->enode_mac[4] = 0x05;
e5b68a61 5612 nv->enode_mac[5] = 0x06 + ha->port_no;
3a03eb79
AV		 5613
5614 rval = 1;
5615 }
5616
9e522cd8
AE		 5617 if (IS_T10_PI_CAPABLE(ha))
5618 nv->frame_payload_size &= ~7;
5619
aa230bc5
AE		 5620 qlt_81xx_config_nvram_stage1(vha, nv);
5621
3a03eb79 5622 /* Reset Initialization control block */
773120e4 5623 memset(icb, 0, ha->init_cb_size);
3a03eb79
AV		 5624
5625 /* Copy 1st segment. */
5626 dptr1 = (uint8_t *)icb;
5627 dptr2 = (uint8_t *)&nv->version;
5628 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
5629 while (cnt--)
5630 *dptr1++ = *dptr2++;
5631
5632 icb->login_retry_count = nv->login_retry_count;
5633
5634 /* Copy 2nd segment. */
5635 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
5636 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
5637 cnt = (uint8_t *)&icb->reserved_5 -
5638 (uint8_t *)&icb->interrupt_delay_timer;
5639 while (cnt--)
5640 *dptr1++ = *dptr2++;
5641
5642 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
5643 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
5644 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
69e5f1ea
AV		 5645 icb->enode_mac[0] = 0x00;
5646 icb->enode_mac[1] = 0xC0;
5647 icb->enode_mac[2] = 0xDD;
3a03eb79
AV		 5648 icb->enode_mac[3] = 0x04;
5649 icb->enode_mac[4] = 0x05;
e5b68a61 5650 icb->enode_mac[5] = 0x06 + ha->port_no;
3a03eb79
AV		 5651 }
5652
b64b0e8f
AV		 5653 /* Use extended-initialization control block. */
5654 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
5655
3a03eb79
AV		 5656 /*
5657 * Setup driver NVRAM options.
5658 */
5659 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
a9083016 5660 "QLE8XXX");
3a03eb79 5661
aa230bc5
AE		 5662 qlt_81xx_config_nvram_stage2(vha, icb);
5663
3a03eb79
AV		 5664 /* Use alternate WWN? */
5665 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
5666 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
5667 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
5668 }
5669
5670 /* Prepare nodename */
5671 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
5672 /*
5673 * Firmware will apply the following mask if the nodename was
5674 * not provided.
5675 */
5676 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
5677 icb->node_name[0] &= 0xF0;
5678 }
5679
5680 /* Set host adapter parameters. */
5681 ha->flags.disable_risc_code_load = 0;
5682 ha->flags.enable_lip_reset = 0;
5683 ha->flags.enable_lip_full_login =
5684 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
5685 ha->flags.enable_target_reset =
5686 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
5687 ha->flags.enable_led_scheme = 0;
5688 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
5689
5690 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
5691 (BIT_6 | BIT_5 | BIT_4)) >> 4;
5692
5693 /* save HBA serial number */
5694 ha->serial0 = icb->port_name[5];
5695 ha->serial1 = icb->port_name[6];
5696 ha->serial2 = icb->port_name[7];
5697 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
5698 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
5699
5700 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5701
5702 ha->retry_count = le16_to_cpu(nv->login_retry_count);
5703
5704 /* Set minimum login_timeout to 4 seconds. */
5705 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
5706 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
5707 if (le16_to_cpu(nv->login_timeout) < 4)
5708 nv->login_timeout = __constant_cpu_to_le16(4);
5709 ha->login_timeout = le16_to_cpu(nv->login_timeout);
5710 icb->login_timeout = nv->login_timeout;
5711
5712 /* Set minimum RATOV to 100 tenths of a second. */
5713 ha->r_a_tov = 100;
5714
5715 ha->loop_reset_delay = nv->reset_delay;
5716
5717 /* Link Down Timeout = 0:
5718 *
5719 * When Port Down timer expires we will start returning
5720 * I/O's to OS with "DID_NO_CONNECT".
5721 *
5722 * Link Down Timeout != 0:
5723 *
5724 * The driver waits for the link to come up after link down
5725 * before returning I/Os to OS with "DID_NO_CONNECT".
5726 */
5727 if (le16_to_cpu(nv->link_down_timeout) == 0) {
5728 ha->loop_down_abort_time =
5729 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
5730 } else {
5731 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
5732 ha->loop_down_abort_time =
5733 (LOOP_DOWN_TIME - ha->link_down_timeout);
5734 }
5735
5736 /* Need enough time to try and get the port back. */
5737 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
5738 if (qlport_down_retry)
5739 ha->port_down_retry_count = qlport_down_retry;
5740
5741 /* Set login_retry_count */
5742 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
5743 if (ha->port_down_retry_count ==
5744 le16_to_cpu(nv->port_down_retry_count) &&
5745 ha->port_down_retry_count > 3)
5746 ha->login_retry_count = ha->port_down_retry_count;
5747 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
5748 ha->login_retry_count = ha->port_down_retry_count;
5749 if (ql2xloginretrycount)
5750 ha->login_retry_count = ql2xloginretrycount;
5751
6246b8a1
GM		 5752 /* if not running MSI-X we need handshaking on interrupts */
5753 if (!vha->hw->flags.msix_enabled && IS_QLA83XX(ha))
5754 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_22);
5755
3a03eb79
AV		 5756 /* Enable ZIO. */
5757 if (!vha->flags.init_done) {
5758 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
5759 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
5760 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
5761 le16_to_cpu(icb->interrupt_delay_timer): 2;
5762 }
5763 icb->firmware_options_2 &= __constant_cpu_to_le32(
5764 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
5765 vha->flags.process_response_queue = 0;
5766 if (ha->zio_mode != QLA_ZIO_DISABLED) {
5767 ha->zio_mode = QLA_ZIO_MODE_6;
5768
7c3df132 5769 ql_log(ql_log_info, vha, 0x0075,
3a03eb79 5770 "ZIO mode %d enabled; timer delay (%d us).\n",
7c3df132
SK		 5771 ha->zio_mode,
5772 ha->zio_timer * 100);
3a03eb79
AV		 5773
5774 icb->firmware_options_2 |= cpu_to_le32(
5775 (uint32_t)ha->zio_mode);
5776 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
5777 vha->flags.process_response_queue = 1;
5778 }
5779
5780 if (rval) {
7c3df132
SK		 5781 ql_log(ql_log_warn, vha, 0x0076,
5782 "NVRAM configuration failed.\n");
3a03eb79
AV		 5783 }
5784 return (rval);
5785}
5786
a9083016
GM		 5787int
5788qla82xx_restart_isp(scsi_qla_host_t *vha)
5789{
5790 int status, rval;
5791 uint32_t wait_time;
5792 struct qla_hw_data *ha = vha->hw;
5793 struct req_que *req = ha->req_q_map[0];
5794 struct rsp_que *rsp = ha->rsp_q_map[0];
5795 struct scsi_qla_host *vp;
feafb7b1 5796 unsigned long flags;
a9083016
GM		 5797
5798 status = qla2x00_init_rings(vha);
5799 if (!status) {
5800 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5801 ha->flags.chip_reset_done = 1;
5802
5803 status = qla2x00_fw_ready(vha);
5804 if (!status) {
7c3df132
SK		 5805 ql_log(ql_log_info, vha, 0x803c,
5806 "Start configure loop, status =%d.\n", status);
a9083016
GM		 5807
5808 /* Issue a marker after FW becomes ready. */
5809 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
5810
5811 vha->flags.online = 1;
5812 /* Wait at most MAX_TARGET RSCNs for a stable link. */
5813 wait_time = 256;
5814 do {
5815 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5816 qla2x00_configure_loop(vha);
5817 wait_time--;
5818 } while (!atomic_read(&vha->loop_down_timer) &&
5819 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) &&
5820 wait_time &&
5821 (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)));
5822 }
5823
5824 /* if no cable then assume it's good */
5825 if ((vha->device_flags & DFLG_NO_CABLE))
5826 status = 0;
5827
cfb0919c 5828 ql_log(ql_log_info, vha, 0x8000,
7c3df132 5829 "Configure loop done, status = 0x%x.\n", status);
a9083016
GM		 5830 }
5831
5832 if (!status) {
5833 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5834
5835 if (!atomic_read(&vha->loop_down_timer)) {
5836 /*
5837 * Issue marker command only when we are going
5838 * to start the I/O .
5839 */
5840 vha->marker_needed = 1;
5841 }
5842
5843 vha->flags.online = 1;
5844
5845 ha->isp_ops->enable_intrs(ha);
5846
5847 ha->isp_abort_cnt = 0;
5848 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
5849
53296788 5850 /* Update the firmware version */
3173167f 5851 status = qla82xx_check_md_needed(vha);
53296788 5852
a9083016
GM		 5853 if (ha->fce) {
5854 ha->flags.fce_enabled = 1;
5855 memset(ha->fce, 0,
5856 fce_calc_size(ha->fce_bufs));
5857 rval = qla2x00_enable_fce_trace(vha,
5858 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
5859 &ha->fce_bufs);
5860 if (rval) {
cfb0919c 5861 ql_log(ql_log_warn, vha, 0x8001,
7c3df132
SK		 5862 "Unable to reinitialize FCE (%d).\n",
5863 rval);
a9083016
GM		 5864 ha->flags.fce_enabled = 0;
5865 }
5866 }
5867
5868 if (ha->eft) {
5869 memset(ha->eft, 0, EFT_SIZE);
5870 rval = qla2x00_enable_eft_trace(vha,
5871 ha->eft_dma, EFT_NUM_BUFFERS);
5872 if (rval) {
cfb0919c 5873 ql_log(ql_log_warn, vha, 0x8010,
7c3df132
SK		 5874 "Unable to reinitialize EFT (%d).\n",
5875 rval);
a9083016
GM		 5876 }
5877 }
a9083016
GM		 5878 }
5879
5880 if (!status) {
cfb0919c 5881 ql_dbg(ql_dbg_taskm, vha, 0x8011,
7c3df132 5882 "qla82xx_restart_isp succeeded.\n");
feafb7b1
AE		 5883
5884 spin_lock_irqsave(&ha->vport_slock, flags);
5885 list_for_each_entry(vp, &ha->vp_list, list) {
5886 if (vp->vp_idx) {
5887 atomic_inc(&vp->vref_count);
5888 spin_unlock_irqrestore(&ha->vport_slock, flags);
5889
a9083016 5890 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 5891
5892 spin_lock_irqsave(&ha->vport_slock, flags);
5893 atomic_dec(&vp->vref_count);
5894 }
a9083016 5895 }
feafb7b1
AE		 5896 spin_unlock_irqrestore(&ha->vport_slock, flags);
5897
a9083016 5898 } else {
cfb0919c 5899 ql_log(ql_log_warn, vha, 0x8016,
7c3df132 5900 "qla82xx_restart_isp **** FAILED ****.\n");
a9083016
GM		 5901 }
5902
5903 return status;
5904}
5905
3a03eb79 5906void
ae97c91e 5907qla81xx_update_fw_options(scsi_qla_host_t *vha)
3a03eb79 5908{
ae97c91e
AV		 5909 struct qla_hw_data *ha = vha->hw;
5910
5911 if (!ql2xetsenable)
5912 return;
5913
5914 /* Enable ETS Burst. */
5915 memset(ha->fw_options, 0, sizeof(ha->fw_options));
5916 ha->fw_options[2] |= BIT_9;
5917 qla2x00_set_fw_options(vha, ha->fw_options);
3a03eb79 5918}
09ff701a
SR		 5919
5920/*
5921 * qla24xx_get_fcp_prio
5922 * Gets the fcp cmd priority value for the logged in port.
5923 * Looks for a match of the port descriptors within
5924 * each of the fcp prio config entries. If a match is found,
5925 * the tag (priority) value is returned.
5926 *
5927 * Input:
21090cbe 5928 * vha = scsi host structure pointer.
09ff701a
SR		 5929 * fcport = port structure pointer.
5930 *
5931 * Return:
6c452a45 5932 * non-zero (if found)
f28a0a96 5933 * -1 (if not found)
09ff701a
SR		 5934 *
5935 * Context:
5936 * Kernel context
5937 */
f28a0a96 5938static int
09ff701a
SR		 5939qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
5940{
5941 int i, entries;
5942 uint8_t pid_match, wwn_match;
f28a0a96 5943 int priority;
09ff701a
SR		 5944 uint32_t pid1, pid2;
5945 uint64_t wwn1, wwn2;
5946 struct qla_fcp_prio_entry *pri_entry;
5947 struct qla_hw_data *ha = vha->hw;
5948
5949 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
f28a0a96 5950 return -1;
09ff701a 5951
f28a0a96 5952 priority = -1;
09ff701a
SR		 5953 entries = ha->fcp_prio_cfg->num_entries;
5954 pri_entry = &ha->fcp_prio_cfg->entry[0];
5955
5956 for (i = 0; i < entries; i++) {
5957 pid_match = wwn_match = 0;
5958
5959 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
5960 pri_entry++;
5961 continue;
5962 }
5963
5964 /* check source pid for a match */
5965 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
5966 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
5967 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
5968 if (pid1 == INVALID_PORT_ID)
5969 pid_match++;
5970 else if (pid1 == pid2)
5971 pid_match++;
5972 }
5973
5974 /* check destination pid for a match */
5975 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
5976 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
5977 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
5978 if (pid1 == INVALID_PORT_ID)
5979 pid_match++;
5980 else if (pid1 == pid2)
5981 pid_match++;
5982 }
5983
5984 /* check source WWN for a match */
5985 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
5986 wwn1 = wwn_to_u64(vha->port_name);
5987 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
5988 if (wwn2 == (uint64_t)-1)
5989 wwn_match++;
5990 else if (wwn1 == wwn2)
5991 wwn_match++;
5992 }
5993
5994 /* check destination WWN for a match */
5995 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
5996 wwn1 = wwn_to_u64(fcport->port_name);
5997 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
5998 if (wwn2 == (uint64_t)-1)
5999 wwn_match++;
6000 else if (wwn1 == wwn2)
6001 wwn_match++;
6002 }
6003
6004 if (pid_match == 2 || wwn_match == 2) {
6005 /* Found a matching entry */
6006 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
6007 priority = pri_entry->tag;
6008 break;
6009 }
6010
6011 pri_entry++;
6012 }
6013
6014 return priority;
6015}
6016
6017/*
6018 * qla24xx_update_fcport_fcp_prio
6019 * Activates fcp priority for the logged in fc port
6020 *
6021 * Input:
21090cbe 6022 * vha = scsi host structure pointer.
09ff701a
SR		 6023 * fcp = port structure pointer.
6024 *
6025 * Return:
6026 * QLA_SUCCESS or QLA_FUNCTION_FAILED
6027 *
6028 * Context:
6029 * Kernel context.
6030 */
6031int
21090cbe 6032qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
09ff701a
SR		 6033{
6034 int ret;
f28a0a96 6035 int priority;
09ff701a
SR		 6036 uint16_t mb[5];
6037
21090cbe
MI		 6038 if (fcport->port_type != FCT_TARGET ||
6039 fcport->loop_id == FC_NO_LOOP_ID)
09ff701a
SR		 6040 return QLA_FUNCTION_FAILED;
6041
21090cbe 6042 priority = qla24xx_get_fcp_prio(vha, fcport);
f28a0a96
AV		 6043 if (priority < 0)
6044 return QLA_FUNCTION_FAILED;
6045
a00f6296
SK		 6046 if (IS_QLA82XX(vha->hw)) {
6047 fcport->fcp_prio = priority & 0xf;
6048 return QLA_SUCCESS;
6049 }
6050
21090cbe 6051 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
cfb0919c
CD		 6052 if (ret == QLA_SUCCESS) {
6053 if (fcport->fcp_prio != priority)
6054 ql_dbg(ql_dbg_user, vha, 0x709e,
6055 "Updated FCP_CMND priority - value=%d loop_id=%d "
6056 "port_id=%02x%02x%02x.\n", priority,
6057 fcport->loop_id, fcport->d_id.b.domain,
6058 fcport->d_id.b.area, fcport->d_id.b.al_pa);
a00f6296 6059 fcport->fcp_prio = priority & 0xf;
cfb0919c 6060 } else
7c3df132 6061 ql_dbg(ql_dbg_user, vha, 0x704f,
cfb0919c
CD		 6062 "Unable to update FCP_CMND priority - ret=0x%x for "
6063 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
6064 fcport->d_id.b.domain, fcport->d_id.b.area,
6065 fcport->d_id.b.al_pa);
09ff701a
SR		 6066 return ret;
6067}
6068
6069/*
6070 * qla24xx_update_all_fcp_prio
6071 * Activates fcp priority for all the logged in ports
6072 *
6073 * Input:
6074 * ha = adapter block pointer.
6075 *
6076 * Return:
6077 * QLA_SUCCESS or QLA_FUNCTION_FAILED
6078 *
6079 * Context:
6080 * Kernel context.
6081 */
6082int
6083qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
6084{
6085 int ret;
6086 fc_port_t *fcport;
6087
6088 ret = QLA_FUNCTION_FAILED;
6089 /* We need to set priority for all logged in ports */
6090 list_for_each_entry(fcport, &vha->vp_fcports, list)
6091 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
6092
6093 return ret;
6094}
Linux kernel - Deliverables
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