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qla2xxx: Let DPORT be enabled purely by nvram.
[deliverable/linux.git] / drivers / scsi / qla2xxx / qla_init.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
73208dfd 8#include "qla_gbl.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/slab.h>
0107109e 12#include <linux/vmalloc.h>
1da177e4
LT		 13
14#include "qla_devtbl.h"
15
4e08df3f
DM		 16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
4e08df3f
DM		 18#endif
19
2d70c103
NB		 20#include <target/target_core_base.h>
21#include "qla_target.h"
22
1da177e4
LT		 23/*
24* QLogic ISP2x00 Hardware Support Function Prototypes.
25*/
1da177e4 26static int qla2x00_isp_firmware(scsi_qla_host_t *);
1da177e4 27static int qla2x00_setup_chip(scsi_qla_host_t *);
1da177e4
LT		 28static int qla2x00_fw_ready(scsi_qla_host_t *);
29static int qla2x00_configure_hba(scsi_qla_host_t *);
1da177e4
LT		 30static int qla2x00_configure_loop(scsi_qla_host_t *);
31static int qla2x00_configure_local_loop(scsi_qla_host_t *);
1da177e4
LT		 32static int qla2x00_configure_fabric(scsi_qla_host_t *);
33static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *);
1da177e4
LT		 34static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
35 uint16_t *);
1da177e4
LT		 36
37static int qla2x00_restart_isp(scsi_qla_host_t *);
1da177e4 38
4d4df193
HK		 39static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
40static int qla84xx_init_chip(scsi_qla_host_t *);
73208dfd 41static int qla25xx_init_queues(struct qla_hw_data *);
4d4df193 42
ac280b67
AV		 43/* SRB Extensions ---------------------------------------------------------- */
44
9ba56b95
GM		 45void
46qla2x00_sp_timeout(unsigned long __data)
ac280b67
AV		 47{
48 srb_t *sp = (srb_t *)__data;
4916392b 49 struct srb_iocb *iocb;
ac280b67
AV		 50 fc_port_t *fcport = sp->fcport;
51 struct qla_hw_data *ha = fcport->vha->hw;
52 struct req_que *req;
53 unsigned long flags;
54
55 spin_lock_irqsave(&ha->hardware_lock, flags);
56 req = ha->req_q_map[0];
57 req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 58 iocb = &sp->u.iocb_cmd;
4916392b 59 iocb->timeout(sp);
9ba56b95 60 sp->free(fcport->vha, sp);
6ac52608 61 spin_unlock_irqrestore(&ha->hardware_lock, flags);
ac280b67
AV		 62}
63
9ba56b95
GM		 64void
65qla2x00_sp_free(void *data, void *ptr)
ac280b67 66{
9ba56b95
GM		 67 srb_t *sp = (srb_t *)ptr;
68 struct srb_iocb *iocb = &sp->u.iocb_cmd;
69 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
ac280b67 70
4d97cc53 71 del_timer(&iocb->timer);
b00ee7d7 72 qla2x00_rel_sp(vha, sp);
ac280b67
AV		 73}
74
ac280b67
AV		 75/* Asynchronous Login/Logout Routines -------------------------------------- */
76
a9b6f722 77unsigned long
5b91490e
AV		 78qla2x00_get_async_timeout(struct scsi_qla_host *vha)
79{
80 unsigned long tmo;
81 struct qla_hw_data *ha = vha->hw;
82
83 /* Firmware should use switch negotiated r_a_tov for timeout. */
84 tmo = ha->r_a_tov / 10 * 2;
8ae6d9c7
GM		 85 if (IS_QLAFX00(ha)) {
86 tmo = FX00_DEF_RATOV * 2;
87 } else if (!IS_FWI2_CAPABLE(ha)) {
5b91490e
AV		 88 /*
89 * Except for earlier ISPs where the timeout is seeded from the
90 * initialization control block.
91 */
92 tmo = ha->login_timeout;
93 }
94 return tmo;
95}
ac280b67
AV		 96
97static void
9ba56b95 98qla2x00_async_iocb_timeout(void *data)
ac280b67 99{
9ba56b95 100 srb_t *sp = (srb_t *)data;
ac280b67 101 fc_port_t *fcport = sp->fcport;
ac280b67 102
7c3df132 103 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
cfb0919c 104 "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n",
9ba56b95 105 sp->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area,
7c3df132 106 fcport->d_id.b.al_pa);
ac280b67 107
5ff1d584 108 fcport->flags &= ~FCF_ASYNC_SENT;
9ba56b95
GM		 109 if (sp->type == SRB_LOGIN_CMD) {
110 struct srb_iocb *lio = &sp->u.iocb_cmd;
ac280b67 111 qla2x00_post_async_logout_work(fcport->vha, fcport, NULL);
6ac52608
AV		 112 /* Retry as needed. */
113 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
114 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
115 QLA_LOGIO_LOGIN_RETRIED : 0;
116 qla2x00_post_async_login_done_work(fcport->vha, fcport,
117 lio->u.logio.data);
a6ca8878
AP		 118 } else if (sp->type == SRB_LOGOUT_CMD) {
119 qlt_logo_completion_handler(fcport, QLA_FUNCTION_TIMEOUT);
6ac52608 120 }
ac280b67
AV		 121}
122
99b0bec7 123static void
9ba56b95 124qla2x00_async_login_sp_done(void *data, void *ptr, int res)
99b0bec7 125{
9ba56b95
GM		 126 srb_t *sp = (srb_t *)ptr;
127 struct srb_iocb *lio = &sp->u.iocb_cmd;
128 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
129
130 if (!test_bit(UNLOADING, &vha->dpc_flags))
131 qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport,
132 lio->u.logio.data);
133 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 134}
135
ac280b67
AV		 136int
137qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
138 uint16_t *data)
139{
ac280b67 140 srb_t *sp;
4916392b 141 struct srb_iocb *lio;
ac280b67
AV		 142 int rval;
143
144 rval = QLA_FUNCTION_FAILED;
9ba56b95 145 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 146 if (!sp)
147 goto done;
148
9ba56b95
GM		 149 sp->type = SRB_LOGIN_CMD;
150 sp->name = "login";
151 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
152
153 lio = &sp->u.iocb_cmd;
3822263e 154 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 155 sp->done = qla2x00_async_login_sp_done;
4916392b 156 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
ac280b67 157 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 158 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
ac280b67 159 rval = qla2x00_start_sp(sp);
080c9517
CD		 160 if (rval != QLA_SUCCESS) {
161 fcport->flags &= ~FCF_ASYNC_SENT;
162 fcport->flags |= FCF_LOGIN_NEEDED;
163 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
ac280b67 164 goto done_free_sp;
080c9517 165 }
ac280b67 166
7c3df132 167 ql_dbg(ql_dbg_disc, vha, 0x2072,
cfb0919c
CD		 168 "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x "
169 "retries=%d.\n", sp->handle, fcport->loop_id,
170 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
171 fcport->login_retry);
ac280b67
AV		 172 return rval;
173
174done_free_sp:
9ba56b95 175 sp->free(fcport->vha, sp);
ac280b67
AV		 176done:
177 return rval;
178}
179
99b0bec7 180static void
9ba56b95 181qla2x00_async_logout_sp_done(void *data, void *ptr, int res)
99b0bec7 182{
9ba56b95
GM		 183 srb_t *sp = (srb_t *)ptr;
184 struct srb_iocb *lio = &sp->u.iocb_cmd;
185 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
186
187 if (!test_bit(UNLOADING, &vha->dpc_flags))
188 qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport,
189 lio->u.logio.data);
190 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 191}
192
ac280b67
AV		 193int
194qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
195{
ac280b67 196 srb_t *sp;
4916392b 197 struct srb_iocb *lio;
ac280b67
AV		 198 int rval;
199
200 rval = QLA_FUNCTION_FAILED;
9ba56b95 201 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 202 if (!sp)
203 goto done;
204
9ba56b95
GM		 205 sp->type = SRB_LOGOUT_CMD;
206 sp->name = "logout";
207 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
208
209 lio = &sp->u.iocb_cmd;
3822263e 210 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 211 sp->done = qla2x00_async_logout_sp_done;
ac280b67
AV		 212 rval = qla2x00_start_sp(sp);
213 if (rval != QLA_SUCCESS)
214 goto done_free_sp;
215
7c3df132 216 ql_dbg(ql_dbg_disc, vha, 0x2070,
cfb0919c
CD		 217 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
218 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
219 fcport->d_id.b.area, fcport->d_id.b.al_pa);
ac280b67
AV		 220 return rval;
221
222done_free_sp:
9ba56b95 223 sp->free(fcport->vha, sp);
ac280b67
AV		 224done:
225 return rval;
226}
227
5ff1d584 228static void
9ba56b95 229qla2x00_async_adisc_sp_done(void *data, void *ptr, int res)
5ff1d584 230{
9ba56b95
GM		 231 srb_t *sp = (srb_t *)ptr;
232 struct srb_iocb *lio = &sp->u.iocb_cmd;
233 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
234
235 if (!test_bit(UNLOADING, &vha->dpc_flags))
236 qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport,
237 lio->u.logio.data);
238 sp->free(sp->fcport->vha, sp);
5ff1d584
AV		 239}
240
241int
242qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
243 uint16_t *data)
244{
5ff1d584 245 srb_t *sp;
4916392b 246 struct srb_iocb *lio;
5ff1d584
AV		 247 int rval;
248
249 rval = QLA_FUNCTION_FAILED;
9ba56b95 250 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
5ff1d584
AV		 251 if (!sp)
252 goto done;
253
9ba56b95
GM		 254 sp->type = SRB_ADISC_CMD;
255 sp->name = "adisc";
256 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
257
258 lio = &sp->u.iocb_cmd;
3822263e 259 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 260 sp->done = qla2x00_async_adisc_sp_done;
5ff1d584 261 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 262 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
5ff1d584
AV		 263 rval = qla2x00_start_sp(sp);
264 if (rval != QLA_SUCCESS)
265 goto done_free_sp;
266
7c3df132 267 ql_dbg(ql_dbg_disc, vha, 0x206f,
cfb0919c
CD		 268 "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
269 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
270 fcport->d_id.b.area, fcport->d_id.b.al_pa);
5ff1d584
AV		 271 return rval;
272
273done_free_sp:
9ba56b95 274 sp->free(fcport->vha, sp);
5ff1d584
AV		 275done:
276 return rval;
277}
278
3822263e 279static void
faef62d1 280qla2x00_tmf_iocb_timeout(void *data)
3822263e 281{
faef62d1
AB		 282 srb_t *sp = (srb_t *)data;
283 struct srb_iocb *tmf = &sp->u.iocb_cmd;
3822263e 284
faef62d1
AB		 285 tmf->u.tmf.comp_status = CS_TIMEOUT;
286 complete(&tmf->u.tmf.comp);
287}
9ba56b95 288
faef62d1
AB		 289static void
290qla2x00_tmf_sp_done(void *data, void *ptr, int res)
291{
292 srb_t *sp = (srb_t *)ptr;
293 struct srb_iocb *tmf = &sp->u.iocb_cmd;
294 complete(&tmf->u.tmf.comp);
3822263e
MI		 295}
296
297int
faef62d1 298qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun,
3822263e
MI		 299 uint32_t tag)
300{
301 struct scsi_qla_host *vha = fcport->vha;
faef62d1 302 struct srb_iocb *tm_iocb;
3822263e 303 srb_t *sp;
faef62d1 304 int rval = QLA_FUNCTION_FAILED;
3822263e 305
9ba56b95 306 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
3822263e
MI		 307 if (!sp)
308 goto done;
309
faef62d1 310 tm_iocb = &sp->u.iocb_cmd;
9ba56b95
GM		 311 sp->type = SRB_TM_CMD;
312 sp->name = "tmf";
faef62d1
AB		 313 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
314 tm_iocb->u.tmf.flags = flags;
315 tm_iocb->u.tmf.lun = lun;
316 tm_iocb->u.tmf.data = tag;
317 sp->done = qla2x00_tmf_sp_done;
318 tm_iocb->timeout = qla2x00_tmf_iocb_timeout;
319 init_completion(&tm_iocb->u.tmf.comp);
3822263e
MI		 320
321 rval = qla2x00_start_sp(sp);
322 if (rval != QLA_SUCCESS)
323 goto done_free_sp;
324
7c3df132 325 ql_dbg(ql_dbg_taskm, vha, 0x802f,
cfb0919c
CD		 326 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
327 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
328 fcport->d_id.b.area, fcport->d_id.b.al_pa);
faef62d1
AB		 329
330 wait_for_completion(&tm_iocb->u.tmf.comp);
331
332 rval = tm_iocb->u.tmf.comp_status == CS_COMPLETE ?
333 QLA_SUCCESS : QLA_FUNCTION_FAILED;
334
335 if ((rval != QLA_SUCCESS) || tm_iocb->u.tmf.data) {
336 ql_dbg(ql_dbg_taskm, vha, 0x8030,
337 "TM IOCB failed (%x).\n", rval);
338 }
339
340 if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) {
341 flags = tm_iocb->u.tmf.flags;
342 lun = (uint16_t)tm_iocb->u.tmf.lun;
343
344 /* Issue Marker IOCB */
345 qla2x00_marker(vha, vha->hw->req_q_map[0],
346 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
347 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
348 }
3822263e
MI		 349
350done_free_sp:
faef62d1 351 sp->free(vha, sp);
3822263e
MI		 352done:
353 return rval;
354}
355
4440e46d
AB		 356static void
357qla24xx_abort_iocb_timeout(void *data)
358{
359 srb_t *sp = (srb_t *)data;
360 struct srb_iocb *abt = &sp->u.iocb_cmd;
361
362 abt->u.abt.comp_status = CS_TIMEOUT;
363 complete(&abt->u.abt.comp);
364}
365
366static void
367qla24xx_abort_sp_done(void *data, void *ptr, int res)
368{
369 srb_t *sp = (srb_t *)ptr;
370 struct srb_iocb *abt = &sp->u.iocb_cmd;
371
372 complete(&abt->u.abt.comp);
373}
374
375static int
376qla24xx_async_abort_cmd(srb_t *cmd_sp)
377{
378 scsi_qla_host_t *vha = cmd_sp->fcport->vha;
379 fc_port_t *fcport = cmd_sp->fcport;
380 struct srb_iocb *abt_iocb;
381 srb_t *sp;
382 int rval = QLA_FUNCTION_FAILED;
383
384 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
385 if (!sp)
386 goto done;
387
388 abt_iocb = &sp->u.iocb_cmd;
389 sp->type = SRB_ABT_CMD;
390 sp->name = "abort";
391 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
392 abt_iocb->u.abt.cmd_hndl = cmd_sp->handle;
393 sp->done = qla24xx_abort_sp_done;
394 abt_iocb->timeout = qla24xx_abort_iocb_timeout;
395 init_completion(&abt_iocb->u.abt.comp);
396
397 rval = qla2x00_start_sp(sp);
398 if (rval != QLA_SUCCESS)
399 goto done_free_sp;
400
401 ql_dbg(ql_dbg_async, vha, 0x507c,
402 "Abort command issued - hdl=%x, target_id=%x\n",
403 cmd_sp->handle, fcport->tgt_id);
404
405 wait_for_completion(&abt_iocb->u.abt.comp);
406
407 rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ?
408 QLA_SUCCESS : QLA_FUNCTION_FAILED;
409
410done_free_sp:
411 sp->free(vha, sp);
412done:
413 return rval;
414}
415
416int
417qla24xx_async_abort_command(srb_t *sp)
418{
419 unsigned long flags = 0;
420
421 uint32_t handle;
422 fc_port_t *fcport = sp->fcport;
423 struct scsi_qla_host *vha = fcport->vha;
424 struct qla_hw_data *ha = vha->hw;
425 struct req_que *req = vha->req;
426
427 spin_lock_irqsave(&ha->hardware_lock, flags);
428 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
429 if (req->outstanding_cmds[handle] == sp)
430 break;
431 }
432 spin_unlock_irqrestore(&ha->hardware_lock, flags);
433 if (handle == req->num_outstanding_cmds) {
434 /* Command not found. */
435 return QLA_FUNCTION_FAILED;
436 }
437 if (sp->type == SRB_FXIOCB_DCMD)
438 return qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
439 FXDISC_ABORT_IOCTL);
440
441 return qla24xx_async_abort_cmd(sp);
442}
443
4916392b 444void
ac280b67
AV		 445qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport,
446 uint16_t *data)
447{
448 int rval;
ac280b67
AV		 449
450 switch (data[0]) {
451 case MBS_COMMAND_COMPLETE:
a4f92a32
AV		 452 /*
453 * Driver must validate login state - If PRLI not complete,
454 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
455 * requests.
456 */
457 rval = qla2x00_get_port_database(vha, fcport, 0);
0eba25df
AE		 458 if (rval == QLA_NOT_LOGGED_IN) {
459 fcport->flags &= ~FCF_ASYNC_SENT;
460 fcport->flags |= FCF_LOGIN_NEEDED;
461 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
462 break;
463 }
464
a4f92a32
AV		 465 if (rval != QLA_SUCCESS) {
466 qla2x00_post_async_logout_work(vha, fcport, NULL);
467 qla2x00_post_async_login_work(vha, fcport, NULL);
468 break;
469 }
99b0bec7 470 if (fcport->flags & FCF_FCP2_DEVICE) {
5ff1d584
AV		 471 qla2x00_post_async_adisc_work(vha, fcport, data);
472 break;
99b0bec7
AV		 473 }
474 qla2x00_update_fcport(vha, fcport);
ac280b67
AV		 475 break;
476 case MBS_COMMAND_ERROR:
5ff1d584 477 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 478 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
479 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
480 else
80d79440 481 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 482 break;
483 case MBS_PORT_ID_USED:
484 fcport->loop_id = data[1];
6ac52608 485 qla2x00_post_async_logout_work(vha, fcport, NULL);
ac280b67
AV		 486 qla2x00_post_async_login_work(vha, fcport, NULL);
487 break;
488 case MBS_LOOP_ID_USED:
489 fcport->loop_id++;
490 rval = qla2x00_find_new_loop_id(vha, fcport);
491 if (rval != QLA_SUCCESS) {
5ff1d584 492 fcport->flags &= ~FCF_ASYNC_SENT;
80d79440 493 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 494 break;
495 }
496 qla2x00_post_async_login_work(vha, fcport, NULL);
497 break;
498 }
4916392b 499 return;
ac280b67
AV		 500}
501
4916392b 502void
ac280b67
AV		 503qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
504 uint16_t *data)
505{
a6ca8878
AP		 506 /* Don't re-login in target mode */
507 if (!fcport->tgt_session)
508 qla2x00_mark_device_lost(vha, fcport, 1, 0);
509 qlt_logo_completion_handler(fcport, data[0]);
4916392b 510 return;
ac280b67
AV		 511}
512
4916392b 513void
5ff1d584
AV		 514qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
515 uint16_t *data)
516{
517 if (data[0] == MBS_COMMAND_COMPLETE) {
518 qla2x00_update_fcport(vha, fcport);
519
4916392b 520 return;
5ff1d584
AV		 521 }
522
523 /* Retry login. */
524 fcport->flags &= ~FCF_ASYNC_SENT;
525 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
526 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
527 else
80d79440 528 qla2x00_mark_device_lost(vha, fcport, 1, 0);
5ff1d584 529
4916392b 530 return;
5ff1d584
AV		 531}
532
1da177e4
LT		 533/****************************************************************************/
534/* QLogic ISP2x00 Hardware Support Functions. */
535/****************************************************************************/
536
fa492630 537static int
7d613ac6
SV		 538qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
539{
540 int rval = QLA_SUCCESS;
541 struct qla_hw_data *ha = vha->hw;
542 uint32_t idc_major_ver, idc_minor_ver;
711aa7f7 543 uint16_t config[4];
7d613ac6
SV		 544
545 qla83xx_idc_lock(vha, 0);
546
547 /* SV: TODO: Assign initialization timeout from
548 * flash-info / other param
549 */
550 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
551 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
552
553 /* Set our fcoe function presence */
554 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
555 ql_dbg(ql_dbg_p3p, vha, 0xb077,
556 "Error while setting DRV-Presence.\n");
557 rval = QLA_FUNCTION_FAILED;
558 goto exit;
559 }
560
561 /* Decide the reset ownership */
562 qla83xx_reset_ownership(vha);
563
564 /*
565 * On first protocol driver load:
566 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
567 * register.
568 * Others: Check compatibility with current IDC Major version.
569 */
570 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
571 if (ha->flags.nic_core_reset_owner) {
572 /* Set IDC Major version */
573 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
574 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
575
576 /* Clearing IDC-Lock-Recovery register */
577 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
578 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
579 /*
580 * Clear further IDC participation if we are not compatible with
581 * the current IDC Major Version.
582 */
583 ql_log(ql_log_warn, vha, 0xb07d,
584 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
585 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
586 __qla83xx_clear_drv_presence(vha);
587 rval = QLA_FUNCTION_FAILED;
588 goto exit;
589 }
590 /* Each function sets its supported Minor version. */
591 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
592 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
593 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
594
711aa7f7
SK		 595 if (ha->flags.nic_core_reset_owner) {
596 memset(config, 0, sizeof(config));
597 if (!qla81xx_get_port_config(vha, config))
598 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
599 QLA8XXX_DEV_READY);
600 }
601
7d613ac6
SV		 602 rval = qla83xx_idc_state_handler(vha);
603
604exit:
605 qla83xx_idc_unlock(vha, 0);
606
607 return rval;
608}
609
1da177e4
LT		 610/*
611* qla2x00_initialize_adapter
612* Initialize board.
613*
614* Input:
615* ha = adapter block pointer.
616*
617* Returns:
618* 0 = success
619*/
620int
e315cd28 621qla2x00_initialize_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 622{
623 int rval;
e315cd28 624 struct qla_hw_data *ha = vha->hw;
73208dfd 625 struct req_que *req = ha->req_q_map[0];
2533cf67 626
fc90adaf
JC		 627 memset(&vha->qla_stats, 0, sizeof(vha->qla_stats));
628 memset(&vha->fc_host_stat, 0, sizeof(vha->fc_host_stat));
629
1da177e4 630 /* Clear adapter flags. */
e315cd28 631 vha->flags.online = 0;
2533cf67 632 ha->flags.chip_reset_done = 0;
e315cd28 633 vha->flags.reset_active = 0;
85880801
AV		 634 ha->flags.pci_channel_io_perm_failure = 0;
635 ha->flags.eeh_busy = 0;
fabbb8df 636 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64();
e315cd28
AC		 637 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
638 atomic_set(&vha->loop_state, LOOP_DOWN);
639 vha->device_flags = DFLG_NO_CABLE;
640 vha->dpc_flags = 0;
641 vha->flags.management_server_logged_in = 0;
642 vha->marker_needed = 0;
1da177e4
LT		 643 ha->isp_abort_cnt = 0;
644 ha->beacon_blink_led = 0;
645
73208dfd
AC		 646 set_bit(0, ha->req_qid_map);
647 set_bit(0, ha->rsp_qid_map);
648
cfb0919c 649 ql_dbg(ql_dbg_init, vha, 0x0040,
7c3df132 650 "Configuring PCI space...\n");
e315cd28 651 rval = ha->isp_ops->pci_config(vha);
1da177e4 652 if (rval) {
7c3df132
SK		 653 ql_log(ql_log_warn, vha, 0x0044,
654 "Unable to configure PCI space.\n");
1da177e4
LT		 655 return (rval);
656 }
657
e315cd28 658 ha->isp_ops->reset_chip(vha);
1da177e4 659
e315cd28 660 rval = qla2xxx_get_flash_info(vha);
c00d8994 661 if (rval) {
7c3df132
SK		 662 ql_log(ql_log_fatal, vha, 0x004f,
663 "Unable to validate FLASH data.\n");
7ec0effd
AD		 664 return rval;
665 }
666
667 if (IS_QLA8044(ha)) {
668 qla8044_read_reset_template(vha);
669
670 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0.
671 * If DONRESET_BIT0 is set, drivers should not set dev_state
672 * to NEED_RESET. But if NEED_RESET is set, drivers should
673 * should honor the reset. */
674 if (ql2xdontresethba == 1)
675 qla8044_set_idc_dontreset(vha);
c00d8994
AV		 676 }
677
73208dfd 678 ha->isp_ops->get_flash_version(vha, req->ring);
cfb0919c 679 ql_dbg(ql_dbg_init, vha, 0x0061,
7c3df132 680 "Configure NVRAM parameters...\n");
0107109e 681
e315cd28 682 ha->isp_ops->nvram_config(vha);
1da177e4 683
d4c760c2
AV		 684 if (ha->flags.disable_serdes) {
685 /* Mask HBA via NVRAM settings? */
7c3df132 686 ql_log(ql_log_info, vha, 0x0077,
7b833558 687 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name);
d4c760c2
AV		 688 return QLA_FUNCTION_FAILED;
689 }
690
cfb0919c 691 ql_dbg(ql_dbg_init, vha, 0x0078,
7c3df132 692 "Verifying loaded RISC code...\n");
1da177e4 693
e315cd28
AC		 694 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
695 rval = ha->isp_ops->chip_diag(vha);
d19044c3
AV		 696 if (rval)
697 return (rval);
e315cd28 698 rval = qla2x00_setup_chip(vha);
d19044c3
AV		 699 if (rval)
700 return (rval);
1da177e4 701 }
a9083016 702
4d4df193 703 if (IS_QLA84XX(ha)) {
e315cd28 704 ha->cs84xx = qla84xx_get_chip(vha);
4d4df193 705 if (!ha->cs84xx) {
7c3df132 706 ql_log(ql_log_warn, vha, 0x00d0,
4d4df193
HK		 707 "Unable to configure ISP84XX.\n");
708 return QLA_FUNCTION_FAILED;
709 }
710 }
2d70c103
NB		 711
712 if (qla_ini_mode_enabled(vha))
713 rval = qla2x00_init_rings(vha);
714
2533cf67 715 ha->flags.chip_reset_done = 1;
1da177e4 716
9a069e19 717 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
6c452a45 718 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
9a069e19
GM		 719 rval = qla84xx_init_chip(vha);
720 if (rval != QLA_SUCCESS) {
7c3df132
SK		 721 ql_log(ql_log_warn, vha, 0x00d4,
722 "Unable to initialize ISP84XX.\n");
8d2b21db 723 qla84xx_put_chip(vha);
9a069e19
GM		 724 }
725 }
726
7d613ac6
SV		 727 /* Load the NIC Core f/w if we are the first protocol driver. */
728 if (IS_QLA8031(ha)) {
729 rval = qla83xx_nic_core_fw_load(vha);
730 if (rval)
731 ql_log(ql_log_warn, vha, 0x0124,
732 "Error in initializing NIC Core f/w.\n");
733 }
734
2f0f3f4f
MI		 735 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
736 qla24xx_read_fcp_prio_cfg(vha);
09ff701a 737
c46e65c7
JC		 738 if (IS_P3P_TYPE(ha))
739 qla82xx_set_driver_version(vha, QLA2XXX_VERSION);
740 else
741 qla25xx_set_driver_version(vha, QLA2XXX_VERSION);
742
1da177e4
LT		 743 return (rval);
744}
745
746/**
abbd8870 747 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
1da177e4
LT		 748 * @ha: HA context
749 *
750 * Returns 0 on success.
751 */
abbd8870 752int
e315cd28 753qla2100_pci_config(scsi_qla_host_t *vha)
1da177e4 754{
a157b101 755 uint16_t w;
abbd8870 756 unsigned long flags;
e315cd28 757 struct qla_hw_data *ha = vha->hw;
3d71644c 758 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 759
1da177e4 760 pci_set_master(ha->pdev);
af6177d8 761 pci_try_set_mwi(ha->pdev);
1da177e4 762
1da177e4 763 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 764 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
abbd8870
AV		 765 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
766
737faece 767 pci_disable_rom(ha->pdev);
1da177e4
LT		 768
769 /* Get PCI bus information. */
770 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 771 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
1da177e4
LT		 772 spin_unlock_irqrestore(&ha->hardware_lock, flags);
773
abbd8870
AV		 774 return QLA_SUCCESS;
775}
1da177e4 776
abbd8870
AV		 777/**
778 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
779 * @ha: HA context
780 *
781 * Returns 0 on success.
782 */
783int
e315cd28 784qla2300_pci_config(scsi_qla_host_t *vha)
abbd8870 785{
a157b101 786 uint16_t w;
abbd8870
AV		 787 unsigned long flags = 0;
788 uint32_t cnt;
e315cd28 789 struct qla_hw_data *ha = vha->hw;
3d71644c 790 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 791
abbd8870 792 pci_set_master(ha->pdev);
af6177d8 793 pci_try_set_mwi(ha->pdev);
1da177e4 794
abbd8870 795 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 796 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1da177e4 797
abbd8870
AV		 798 if (IS_QLA2322(ha) || IS_QLA6322(ha))
799 w &= ~PCI_COMMAND_INTX_DISABLE;
a157b101 800 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1da177e4 801
abbd8870
AV		 802 /*
803 * If this is a 2300 card and not 2312, reset the
804 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
805 * the 2310 also reports itself as a 2300 so we need to get the
806 * fb revision level -- a 6 indicates it really is a 2300 and
807 * not a 2310.
808 */
809 if (IS_QLA2300(ha)) {
810 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 811
abbd8870 812 /* Pause RISC. */
3d71644c 813 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
abbd8870 814 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 815 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
abbd8870 816 break;
1da177e4 817
abbd8870
AV		 818 udelay(10);
819 }
1da177e4 820
abbd8870 821 /* Select FPM registers. */
3d71644c
AV		 822 WRT_REG_WORD(&reg->ctrl_status, 0x20);
823 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 824
825 /* Get the fb rev level */
3d71644c 826 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
abbd8870
AV		 827
828 if (ha->fb_rev == FPM_2300)
a157b101 829 pci_clear_mwi(ha->pdev);
abbd8870
AV		 830
831 /* Deselect FPM registers. */
3d71644c
AV		 832 WRT_REG_WORD(&reg->ctrl_status, 0x0);
833 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 834
835 /* Release RISC module. */
3d71644c 836 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
abbd8870 837 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 838 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
abbd8870
AV		 839 break;
840
841 udelay(10);
1da177e4 842 }
1da177e4 843
abbd8870
AV		 844 spin_unlock_irqrestore(&ha->hardware_lock, flags);
845 }
1da177e4 846
abbd8870
AV		 847 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
848
737faece 849 pci_disable_rom(ha->pdev);
1da177e4 850
abbd8870
AV		 851 /* Get PCI bus information. */
852 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 853 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 854 spin_unlock_irqrestore(&ha->hardware_lock, flags);
855
856 return QLA_SUCCESS;
1da177e4
LT		 857}
858
0107109e
AV		 859/**
860 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
861 * @ha: HA context
862 *
863 * Returns 0 on success.
864 */
865int
e315cd28 866qla24xx_pci_config(scsi_qla_host_t *vha)
0107109e 867{
a157b101 868 uint16_t w;
0107109e 869 unsigned long flags = 0;
e315cd28 870 struct qla_hw_data *ha = vha->hw;
0107109e 871 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
0107109e
AV		 872
873 pci_set_master(ha->pdev);
af6177d8 874 pci_try_set_mwi(ha->pdev);
0107109e
AV		 875
876 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 877 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
0107109e
AV		 878 w &= ~PCI_COMMAND_INTX_DISABLE;
879 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
880
881 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
882
883 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
f85ec187
AV		 884 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
885 pcix_set_mmrbc(ha->pdev, 2048);
0107109e
AV		 886
887 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 888 if (pci_is_pcie(ha->pdev))
5ffd3a52 889 pcie_set_readrq(ha->pdev, 4096);
0107109e 890
737faece 891 pci_disable_rom(ha->pdev);
0107109e 892
44c10138 893 ha->chip_revision = ha->pdev->revision;
a8488abe 894
0107109e
AV		 895 /* Get PCI bus information. */
896 spin_lock_irqsave(&ha->hardware_lock, flags);
897 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
898 spin_unlock_irqrestore(&ha->hardware_lock, flags);
899
900 return QLA_SUCCESS;
901}
902
c3a2f0df
AV		 903/**
904 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
905 * @ha: HA context
906 *
907 * Returns 0 on success.
908 */
909int
e315cd28 910qla25xx_pci_config(scsi_qla_host_t *vha)
c3a2f0df
AV		 911{
912 uint16_t w;
e315cd28 913 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 914
915 pci_set_master(ha->pdev);
916 pci_try_set_mwi(ha->pdev);
917
918 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
919 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
920 w &= ~PCI_COMMAND_INTX_DISABLE;
921 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
922
923 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 924 if (pci_is_pcie(ha->pdev))
5ffd3a52 925 pcie_set_readrq(ha->pdev, 4096);
c3a2f0df 926
737faece 927 pci_disable_rom(ha->pdev);
c3a2f0df
AV		 928
929 ha->chip_revision = ha->pdev->revision;
930
931 return QLA_SUCCESS;
932}
933
1da177e4
LT		 934/**
935 * qla2x00_isp_firmware() - Choose firmware image.
936 * @ha: HA context
937 *
938 * Returns 0 on success.
939 */
940static int
e315cd28 941qla2x00_isp_firmware(scsi_qla_host_t *vha)
1da177e4
LT		 942{
943 int rval;
42e421b1
AV		 944 uint16_t loop_id, topo, sw_cap;
945 uint8_t domain, area, al_pa;
e315cd28 946 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 947
948 /* Assume loading risc code */
fa2a1ce5 949 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 950
951 if (ha->flags.disable_risc_code_load) {
7c3df132 952 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
1da177e4
LT		 953
954 /* Verify checksum of loaded RISC code. */
e315cd28 955 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
42e421b1
AV		 956 if (rval == QLA_SUCCESS) {
957 /* And, verify we are not in ROM code. */
e315cd28 958 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
42e421b1
AV		 959 &area, &domain, &topo, &sw_cap);
960 }
1da177e4
LT		 961 }
962
7c3df132
SK		 963 if (rval)
964 ql_dbg(ql_dbg_init, vha, 0x007a,
965 "**** Load RISC code ****.\n");
1da177e4
LT		 966
967 return (rval);
968}
969
970/**
971 * qla2x00_reset_chip() - Reset ISP chip.
972 * @ha: HA context
973 *
974 * Returns 0 on success.
975 */
abbd8870 976void
e315cd28 977qla2x00_reset_chip(scsi_qla_host_t *vha)
1da177e4
LT		 978{
979 unsigned long flags = 0;
e315cd28 980 struct qla_hw_data *ha = vha->hw;
3d71644c 981 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 982 uint32_t cnt;
1da177e4
LT		 983 uint16_t cmd;
984
85880801
AV		 985 if (unlikely(pci_channel_offline(ha->pdev)))
986 return;
987
fd34f556 988 ha->isp_ops->disable_intrs(ha);
1da177e4
LT		 989
990 spin_lock_irqsave(&ha->hardware_lock, flags);
991
992 /* Turn off master enable */
993 cmd = 0;
994 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
995 cmd &= ~PCI_COMMAND_MASTER;
996 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
997
998 if (!IS_QLA2100(ha)) {
999 /* Pause RISC. */
1000 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1001 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
1002 for (cnt = 0; cnt < 30000; cnt++) {
1003 if ((RD_REG_WORD(&reg->hccr) &
1004 HCCR_RISC_PAUSE) != 0)
1005 break;
1006 udelay(100);
1007 }
1008 } else {
1009 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1010 udelay(10);
1011 }
1012
1013 /* Select FPM registers. */
1014 WRT_REG_WORD(&reg->ctrl_status, 0x20);
1015 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1016
1017 /* FPM Soft Reset. */
1018 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
1019 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
1020
1021 /* Toggle Fpm Reset. */
1022 if (!IS_QLA2200(ha)) {
1023 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
1024 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
1025 }
1026
1027 /* Select frame buffer registers. */
1028 WRT_REG_WORD(&reg->ctrl_status, 0x10);
1029 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1030
1031 /* Reset frame buffer FIFOs. */
1032 if (IS_QLA2200(ha)) {
1033 WRT_FB_CMD_REG(ha, reg, 0xa000);
1034 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
1035 } else {
1036 WRT_FB_CMD_REG(ha, reg, 0x00fc);
1037
1038 /* Read back fb_cmd until zero or 3 seconds max */
1039 for (cnt = 0; cnt < 3000; cnt++) {
1040 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
1041 break;
1042 udelay(100);
1043 }
1044 }
1045
1046 /* Select RISC module registers. */
1047 WRT_REG_WORD(&reg->ctrl_status, 0);
1048 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1049
1050 /* Reset RISC processor. */
1051 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1052 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1053
1054 /* Release RISC processor. */
1055 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1056 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1057 }
1058
1059 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
1060 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
1061
1062 /* Reset ISP chip. */
1063 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1064
1065 /* Wait for RISC to recover from reset. */
1066 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1067 /*
1068 * It is necessary to for a delay here since the card doesn't
1069 * respond to PCI reads during a reset. On some architectures
1070 * this will result in an MCA.
1071 */
1072 udelay(20);
1073 for (cnt = 30000; cnt; cnt--) {
1074 if ((RD_REG_WORD(&reg->ctrl_status) &
1075 CSR_ISP_SOFT_RESET) == 0)
1076 break;
1077 udelay(100);
1078 }
1079 } else
1080 udelay(10);
1081
1082 /* Reset RISC processor. */
1083 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1084
1085 WRT_REG_WORD(&reg->semaphore, 0);
1086
1087 /* Release RISC processor. */
1088 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1089 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1090
1091 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1092 for (cnt = 0; cnt < 30000; cnt++) {
ffb39f03 1093 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1da177e4 1094 break;
1da177e4
LT		 1095
1096 udelay(100);
1097 }
1098 } else
1099 udelay(100);
1100
1101 /* Turn on master enable */
1102 cmd |= PCI_COMMAND_MASTER;
1103 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
1104
1105 /* Disable RISC pause on FPM parity error. */
1106 if (!IS_QLA2100(ha)) {
1107 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
1108 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1109 }
1110
1111 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1112}
1113
b1d46989
MI		 1114/**
1115 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
1116 *
1117 * Returns 0 on success.
1118 */
fa492630 1119static int
b1d46989
MI		 1120qla81xx_reset_mpi(scsi_qla_host_t *vha)
1121{
1122 uint16_t mb[4] = {0x1010, 0, 1, 0};
1123
6246b8a1
GM		 1124 if (!IS_QLA81XX(vha->hw))
1125 return QLA_SUCCESS;
1126
b1d46989
MI		 1127 return qla81xx_write_mpi_register(vha, mb);
1128}
1129
0107109e 1130/**
88c26663 1131 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
0107109e
AV		 1132 * @ha: HA context
1133 *
1134 * Returns 0 on success.
1135 */
d14e72fb 1136static inline int
e315cd28 1137qla24xx_reset_risc(scsi_qla_host_t *vha)
0107109e
AV		 1138{
1139 unsigned long flags = 0;
e315cd28 1140 struct qla_hw_data *ha = vha->hw;
0107109e 1141 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
52c82823 1142 uint32_t cnt;
335a1cc9 1143 uint16_t wd;
b1d46989 1144 static int abts_cnt; /* ISP abort retry counts */
d14e72fb 1145 int rval = QLA_SUCCESS;
0107109e 1146
0107109e
AV		 1147 spin_lock_irqsave(&ha->hardware_lock, flags);
1148
1149 /* Reset RISC. */
1150 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1151 for (cnt = 0; cnt < 30000; cnt++) {
1152 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
1153 break;
1154
1155 udelay(10);
1156 }
1157
d14e72fb
HM		 1158 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE))
1159 set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags);
1160
1161 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017e,
1162 "HCCR: 0x%x, Control Status %x, DMA active status:0x%x\n",
1163 RD_REG_DWORD(&reg->hccr),
1164 RD_REG_DWORD(&reg->ctrl_status),
1165 (RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE));
1166
0107109e
AV		 1167 WRT_REG_DWORD(&reg->ctrl_status,
1168 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335a1cc9 1169 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
88c26663 1170
335a1cc9 1171 udelay(100);
d14e72fb 1172
88c26663 1173 /* Wait for firmware to complete NVRAM accesses. */
52c82823 1174 RD_REG_WORD(&reg->mailbox0);
d14e72fb
HM		 1175 for (cnt = 10000; RD_REG_WORD(&reg->mailbox0) != 0 &&
1176 rval == QLA_SUCCESS; cnt--) {
88c26663 1177 barrier();
d14e72fb
HM		 1178 if (cnt)
1179 udelay(5);
1180 else
1181 rval = QLA_FUNCTION_TIMEOUT;
88c26663
AV		 1182 }
1183
d14e72fb
HM		 1184 if (rval == QLA_SUCCESS)
1185 set_bit(ISP_MBX_RDY, &ha->fw_dump_cap_flags);
1186
1187 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017f,
1188 "HCCR: 0x%x, MailBox0 Status 0x%x\n",
1189 RD_REG_DWORD(&reg->hccr),
1190 RD_REG_DWORD(&reg->mailbox0));
1191
335a1cc9 1192 /* Wait for soft-reset to complete. */
52c82823 1193 RD_REG_DWORD(&reg->ctrl_status);
d14e72fb 1194 for (cnt = 0; cnt < 6000000; cnt++) {
0107109e 1195 barrier();
d14e72fb
HM		 1196 if ((RD_REG_DWORD(&reg->ctrl_status) &
1197 CSRX_ISP_SOFT_RESET) == 0)
1198 break;
1199
1200 udelay(5);
0107109e 1201 }
d14e72fb
HM		 1202 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))
1203 set_bit(ISP_SOFT_RESET_CMPL, &ha->fw_dump_cap_flags);
1204
1205 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015d,
1206 "HCCR: 0x%x, Soft Reset status: 0x%x\n",
1207 RD_REG_DWORD(&reg->hccr),
1208 RD_REG_DWORD(&reg->ctrl_status));
0107109e 1209
b1d46989
MI		 1210 /* If required, do an MPI FW reset now */
1211 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
1212 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
1213 if (++abts_cnt < 5) {
1214 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1215 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
1216 } else {
1217 /*
1218 * We exhausted the ISP abort retries. We have to
1219 * set the board offline.
1220 */
1221 abts_cnt = 0;
1222 vha->flags.online = 0;
1223 }
1224 }
1225 }
1226
0107109e
AV		 1227 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
1228 RD_REG_DWORD(&reg->hccr);
1229
1230 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
1231 RD_REG_DWORD(&reg->hccr);
1232
1233 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
1234 RD_REG_DWORD(&reg->hccr);
1235
52c82823 1236 RD_REG_WORD(&reg->mailbox0);
d14e72fb
HM		 1237 for (cnt = 6000000; RD_REG_WORD(&reg->mailbox0) != 0 &&
1238 rval == QLA_SUCCESS; cnt--) {
0107109e 1239 barrier();
d14e72fb
HM		 1240 if (cnt)
1241 udelay(5);
1242 else
1243 rval = QLA_FUNCTION_TIMEOUT;
0107109e 1244 }
d14e72fb
HM		 1245 if (rval == QLA_SUCCESS)
1246 set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
1247
1248 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015e,
1249 "Host Risc 0x%x, mailbox0 0x%x\n",
1250 RD_REG_DWORD(&reg->hccr),
1251 RD_REG_WORD(&reg->mailbox0));
0107109e
AV		 1252
1253 spin_unlock_irqrestore(&ha->hardware_lock, flags);
124f85e6 1254
d14e72fb
HM		 1255 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015f,
1256 "Driver in %s mode\n",
1257 IS_NOPOLLING_TYPE(ha) ? "Interrupt" : "Polling");
1258
124f85e6
AV		 1259 if (IS_NOPOLLING_TYPE(ha))
1260 ha->isp_ops->enable_intrs(ha);
d14e72fb
HM		 1261
1262 return rval;
0107109e
AV		 1263}
1264
4ea2c9c7
JC		 1265static void
1266qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
1267{
1268 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1269
1270 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1271 *data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);
1272
1273}
1274
1275static void
1276qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
1277{
1278 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1279
1280 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1281 WRT_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
1282}
1283
1284static void
1285qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
1286{
4ea2c9c7
JC		 1287 uint32_t wd32 = 0;
1288 uint delta_msec = 100;
1289 uint elapsed_msec = 0;
1290 uint timeout_msec;
1291 ulong n;
1292
cc790764
JC		 1293 if (vha->hw->pdev->subsystem_device != 0x0175 &&
1294 vha->hw->pdev->subsystem_device != 0x0240)
4ea2c9c7
JC		 1295 return;
1296
8dd7e3a5
JC		 1297 WRT_REG_DWORD(&vha->hw->iobase->isp24.hccr, HCCRX_SET_RISC_PAUSE);
1298 udelay(100);
1299
4ea2c9c7
JC		 1300attempt:
1301 timeout_msec = TIMEOUT_SEMAPHORE;
1302 n = timeout_msec / delta_msec;
1303 while (n--) {
1304 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
1305 qla25xx_read_risc_sema_reg(vha, &wd32);
1306 if (wd32 & RISC_SEMAPHORE)
1307 break;
1308 msleep(delta_msec);
1309 elapsed_msec += delta_msec;
1310 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1311 goto force;
1312 }
1313
1314 if (!(wd32 & RISC_SEMAPHORE))
1315 goto force;
1316
1317 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1318 goto acquired;
1319
1320 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
1321 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
1322 n = timeout_msec / delta_msec;
1323 while (n--) {
1324 qla25xx_read_risc_sema_reg(vha, &wd32);
1325 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1326 break;
1327 msleep(delta_msec);
1328 elapsed_msec += delta_msec;
1329 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1330 goto force;
1331 }
1332
1333 if (wd32 & RISC_SEMAPHORE_FORCE)
1334 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
1335
1336 goto attempt;
1337
1338force:
1339 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
1340
1341acquired:
1342 return;
1343}
1344
88c26663
AV		 1345/**
1346 * qla24xx_reset_chip() - Reset ISP24xx chip.
1347 * @ha: HA context
1348 *
1349 * Returns 0 on success.
1350 */
1351void
e315cd28 1352qla24xx_reset_chip(scsi_qla_host_t *vha)
88c26663 1353{
e315cd28 1354 struct qla_hw_data *ha = vha->hw;
85880801
AV		 1355
1356 if (pci_channel_offline(ha->pdev) &&
1357 ha->flags.pci_channel_io_perm_failure) {
1358 return;
1359 }
1360
fd34f556 1361 ha->isp_ops->disable_intrs(ha);
88c26663 1362
4ea2c9c7
JC		 1363 qla25xx_manipulate_risc_semaphore(vha);
1364
88c26663 1365 /* Perform RISC reset. */
e315cd28 1366 qla24xx_reset_risc(vha);
88c26663
AV		 1367}
1368
1da177e4
LT		 1369/**
1370 * qla2x00_chip_diag() - Test chip for proper operation.
1371 * @ha: HA context
1372 *
1373 * Returns 0 on success.
1374 */
abbd8870 1375int
e315cd28 1376qla2x00_chip_diag(scsi_qla_host_t *vha)
1da177e4
LT		 1377{
1378 int rval;
e315cd28 1379 struct qla_hw_data *ha = vha->hw;
3d71644c 1380 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 1381 unsigned long flags = 0;
1382 uint16_t data;
1383 uint32_t cnt;
1384 uint16_t mb[5];
73208dfd 1385 struct req_que *req = ha->req_q_map[0];
1da177e4
LT		 1386
1387 /* Assume a failed state */
1388 rval = QLA_FUNCTION_FAILED;
1389
7c3df132
SK		 1390 ql_dbg(ql_dbg_init, vha, 0x007b,
1391 "Testing device at %lx.\n", (u_long)&reg->flash_address);
1da177e4
LT		 1392
1393 spin_lock_irqsave(&ha->hardware_lock, flags);
1394
1395 /* Reset ISP chip. */
1396 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1397
1398 /*
1399 * We need to have a delay here since the card will not respond while
1400 * in reset causing an MCA on some architectures.
1401 */
1402 udelay(20);
1403 data = qla2x00_debounce_register(&reg->ctrl_status);
1404 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
1405 udelay(5);
1406 data = RD_REG_WORD(&reg->ctrl_status);
1407 barrier();
1408 }
1409
1410 if (!cnt)
1411 goto chip_diag_failed;
1412
7c3df132
SK		 1413 ql_dbg(ql_dbg_init, vha, 0x007c,
1414 "Reset register cleared by chip reset.\n");
1da177e4
LT		 1415
1416 /* Reset RISC processor. */
1417 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1418 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1419
1420 /* Workaround for QLA2312 PCI parity error */
1421 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1422 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
1423 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
1424 udelay(5);
1425 data = RD_MAILBOX_REG(ha, reg, 0);
fa2a1ce5 1426 barrier();
1da177e4
LT		 1427 }
1428 } else
1429 udelay(10);
1430
1431 if (!cnt)
1432 goto chip_diag_failed;
1433
1434 /* Check product ID of chip */
7c3df132 1435 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
1da177e4
LT		 1436
1437 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
1438 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
1439 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
1440 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
1441 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
1442 mb[3] != PROD_ID_3) {
7c3df132
SK		 1443 ql_log(ql_log_warn, vha, 0x0062,
1444 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
1445 mb[1], mb[2], mb[3]);
1da177e4
LT		 1446
1447 goto chip_diag_failed;
1448 }
1449 ha->product_id[0] = mb[1];
1450 ha->product_id[1] = mb[2];
1451 ha->product_id[2] = mb[3];
1452 ha->product_id[3] = mb[4];
1453
1454 /* Adjust fw RISC transfer size */
73208dfd 1455 if (req->length > 1024)
1da177e4
LT		 1456 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
1457 else
1458 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
73208dfd 1459 req->length;
1da177e4
LT		 1460
1461 if (IS_QLA2200(ha) &&
1462 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
1463 /* Limit firmware transfer size with a 2200A */
7c3df132 1464 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1da177e4 1465
ea5b6382 1466 ha->device_type |= DT_ISP2200A;
1da177e4
LT		 1467 ha->fw_transfer_size = 128;
1468 }
1469
1470 /* Wrap Incoming Mailboxes Test. */
1471 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1472
7c3df132 1473 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
e315cd28 1474 rval = qla2x00_mbx_reg_test(vha);
7c3df132
SK		 1475 if (rval)
1476 ql_log(ql_log_warn, vha, 0x0080,
1477 "Failed mailbox send register test.\n");
1478 else
1da177e4
LT		 1479 /* Flag a successful rval */
1480 rval = QLA_SUCCESS;
1da177e4
LT		 1481 spin_lock_irqsave(&ha->hardware_lock, flags);
1482
1483chip_diag_failed:
1484 if (rval)
7c3df132
SK		 1485 ql_log(ql_log_info, vha, 0x0081,
1486 "Chip diagnostics **** FAILED ****.\n");
1da177e4
LT		 1487
1488 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1489
1490 return (rval);
1491}
1492
0107109e
AV		 1493/**
1494 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
1495 * @ha: HA context
1496 *
1497 * Returns 0 on success.
1498 */
1499int
e315cd28 1500qla24xx_chip_diag(scsi_qla_host_t *vha)
0107109e
AV		 1501{
1502 int rval;
e315cd28 1503 struct qla_hw_data *ha = vha->hw;
73208dfd 1504 struct req_que *req = ha->req_q_map[0];
0107109e 1505
7ec0effd 1506 if (IS_P3P_TYPE(ha))
a9083016
GM		 1507 return QLA_SUCCESS;
1508
73208dfd 1509 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
0107109e 1510
e315cd28 1511 rval = qla2x00_mbx_reg_test(vha);
0107109e 1512 if (rval) {
7c3df132
SK		 1513 ql_log(ql_log_warn, vha, 0x0082,
1514 "Failed mailbox send register test.\n");
0107109e
AV		 1515 } else {
1516 /* Flag a successful rval */
1517 rval = QLA_SUCCESS;
1518 }
1519
1520 return rval;
1521}
1522
a7a167bf 1523void
e315cd28 1524qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
0107109e 1525{
a7a167bf
AV		 1526 int rval;
1527 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
73208dfd 1528 eft_size, fce_size, mq_size;
df613b96
AV		 1529 dma_addr_t tc_dma;
1530 void *tc;
e315cd28 1531 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 1532 struct req_que *req = ha->req_q_map[0];
1533 struct rsp_que *rsp = ha->rsp_q_map[0];
a7a167bf
AV		 1534
1535 if (ha->fw_dump) {
7c3df132
SK		 1536 ql_dbg(ql_dbg_init, vha, 0x00bd,
1537 "Firmware dump already allocated.\n");
a7a167bf
AV		 1538 return;
1539 }
d4e3e04d 1540
0107109e 1541 ha->fw_dumped = 0;
61f098dd 1542 ha->fw_dump_cap_flags = 0;
f73cb695
CD		 1543 dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
1544 req_q_size = rsp_q_size = 0;
1545
1546 if (IS_QLA27XX(ha))
1547 goto try_fce;
1548
d4e3e04d 1549 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
a7a167bf 1550 fixed_size = sizeof(struct qla2100_fw_dump);
d4e3e04d 1551 } else if (IS_QLA23XX(ha)) {
a7a167bf
AV		 1552 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
1553 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
1554 sizeof(uint16_t);
e428924c 1555 } else if (IS_FWI2_CAPABLE(ha)) {
b20f02e1 1556 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1
GM		 1557 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
1558 else if (IS_QLA81XX(ha))
3a03eb79
AV		 1559 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
1560 else if (IS_QLA25XX(ha))
1561 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
1562 else
1563 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
f73cb695 1564
a7a167bf
AV		 1565 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
1566 sizeof(uint32_t);
050c9bb1 1567 if (ha->mqenable) {
b20f02e1 1568 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
6246b8a1 1569 mq_size = sizeof(struct qla2xxx_mq_chain);
050c9bb1
GM		 1570 /*
1571 * Allocate maximum buffer size for all queues.
1572 * Resizing must be done at end-of-dump processing.
1573 */
1574 mq_size += ha->max_req_queues *
1575 (req->length * sizeof(request_t));
1576 mq_size += ha->max_rsp_queues *
1577 (rsp->length * sizeof(response_t));
1578 }
00876ae8 1579 if (ha->tgt.atio_ring)
2d70c103 1580 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
df613b96 1581 /* Allocate memory for Fibre Channel Event Buffer. */
f73cb695
CD		 1582 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
1583 !IS_QLA27XX(ha))
436a7b11 1584 goto try_eft;
df613b96 1585
f73cb695
CD		 1586try_fce:
1587 if (ha->fce)
1588 dma_free_coherent(&ha->pdev->dev,
1589 FCE_SIZE, ha->fce, ha->fce_dma);
1590
1591 /* Allocate memory for Fibre Channel Event Buffer. */
0ea85b50
JP		 1592 tc = dma_zalloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
1593 GFP_KERNEL);
df613b96 1594 if (!tc) {
7c3df132
SK		 1595 ql_log(ql_log_warn, vha, 0x00be,
1596 "Unable to allocate (%d KB) for FCE.\n",
1597 FCE_SIZE / 1024);
17d98630 1598 goto try_eft;
df613b96
AV		 1599 }
1600
e315cd28 1601 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
df613b96
AV		 1602 ha->fce_mb, &ha->fce_bufs);
1603 if (rval) {
7c3df132
SK		 1604 ql_log(ql_log_warn, vha, 0x00bf,
1605 "Unable to initialize FCE (%d).\n", rval);
df613b96
AV		 1606 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
1607 tc_dma);
1608 ha->flags.fce_enabled = 0;
17d98630 1609 goto try_eft;
df613b96 1610 }
cfb0919c 1611 ql_dbg(ql_dbg_init, vha, 0x00c0,
7c3df132 1612 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
df613b96 1613
7d9dade3 1614 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
df613b96
AV		 1615 ha->flags.fce_enabled = 1;
1616 ha->fce_dma = tc_dma;
1617 ha->fce = tc;
f73cb695 1618
436a7b11 1619try_eft:
f73cb695
CD		 1620 if (ha->eft)
1621 dma_free_coherent(&ha->pdev->dev,
1622 EFT_SIZE, ha->eft, ha->eft_dma);
1623
436a7b11 1624 /* Allocate memory for Extended Trace Buffer. */
0ea85b50
JP		 1625 tc = dma_zalloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
1626 GFP_KERNEL);
436a7b11 1627 if (!tc) {
7c3df132
SK		 1628 ql_log(ql_log_warn, vha, 0x00c1,
1629 "Unable to allocate (%d KB) for EFT.\n",
1630 EFT_SIZE / 1024);
436a7b11
AV		 1631 goto cont_alloc;
1632 }
1633
e315cd28 1634 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
436a7b11 1635 if (rval) {
7c3df132
SK		 1636 ql_log(ql_log_warn, vha, 0x00c2,
1637 "Unable to initialize EFT (%d).\n", rval);
436a7b11
AV		 1638 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
1639 tc_dma);
1640 goto cont_alloc;
1641 }
cfb0919c 1642 ql_dbg(ql_dbg_init, vha, 0x00c3,
7c3df132 1643 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
436a7b11
AV		 1644
1645 eft_size = EFT_SIZE;
1646 ha->eft_dma = tc_dma;
1647 ha->eft = tc;
d4e3e04d 1648 }
f73cb695 1649
a7a167bf 1650cont_alloc:
f73cb695
CD		 1651 if (IS_QLA27XX(ha)) {
1652 if (!ha->fw_dump_template) {
1653 ql_log(ql_log_warn, vha, 0x00ba,
1654 "Failed missing fwdump template\n");
1655 return;
1656 }
1657 dump_size = qla27xx_fwdt_calculate_dump_size(vha);
1658 ql_dbg(ql_dbg_init, vha, 0x00fa,
1659 "-> allocating fwdump (%x bytes)...\n", dump_size);
1660 goto allocate;
1661 }
1662
73208dfd
AC		 1663 req_q_size = req->length * sizeof(request_t);
1664 rsp_q_size = rsp->length * sizeof(response_t);
a7a167bf 1665 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
2afa19a9 1666 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
bb99de67
AV		 1667 ha->chain_offset = dump_size;
1668 dump_size += mq_size + fce_size;
d4e3e04d 1669
f73cb695 1670allocate:
d4e3e04d 1671 ha->fw_dump = vmalloc(dump_size);
a7a167bf 1672 if (!ha->fw_dump) {
7c3df132
SK		 1673 ql_log(ql_log_warn, vha, 0x00c4,
1674 "Unable to allocate (%d KB) for firmware dump.\n",
1675 dump_size / 1024);
a7a167bf 1676
e30d1756
MI		 1677 if (ha->fce) {
1678 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
1679 ha->fce_dma);
1680 ha->fce = NULL;
1681 ha->fce_dma = 0;
1682 }
1683
a7a167bf
AV		 1684 if (ha->eft) {
1685 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
1686 ha->eft_dma);
1687 ha->eft = NULL;
1688 ha->eft_dma = 0;
1689 }
1690 return;
1691 }
f73cb695 1692 ha->fw_dump_len = dump_size;
cfb0919c 1693 ql_dbg(ql_dbg_init, vha, 0x00c5,
7c3df132 1694 "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
a7a167bf 1695
f73cb695
CD		 1696 if (IS_QLA27XX(ha))
1697 return;
1698
a7a167bf
AV		 1699 ha->fw_dump->signature[0] = 'Q';
1700 ha->fw_dump->signature[1] = 'L';
1701 ha->fw_dump->signature[2] = 'G';
1702 ha->fw_dump->signature[3] = 'C';
ad950360 1703 ha->fw_dump->version = htonl(1);
a7a167bf
AV		 1704
1705 ha->fw_dump->fixed_size = htonl(fixed_size);
1706 ha->fw_dump->mem_size = htonl(mem_size);
1707 ha->fw_dump->req_q_size = htonl(req_q_size);
1708 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
1709
1710 ha->fw_dump->eft_size = htonl(eft_size);
1711 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
1712 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
1713
1714 ha->fw_dump->header_size =
1715 htonl(offsetof(struct qla2xxx_fw_dump, isp));
0107109e
AV		 1716}
1717
18e7555a
AV		 1718static int
1719qla81xx_mpi_sync(scsi_qla_host_t *vha)
1720{
1721#define MPS_MASK 0xe0
1722 int rval;
1723 uint16_t dc;
1724 uint32_t dw;
18e7555a
AV		 1725
1726 if (!IS_QLA81XX(vha->hw))
1727 return QLA_SUCCESS;
1728
1729 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
1730 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1731 ql_log(ql_log_warn, vha, 0x0105,
1732 "Unable to acquire semaphore.\n");
18e7555a
AV		 1733 goto done;
1734 }
1735
1736 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
1737 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
1738 if (rval != QLA_SUCCESS) {
7c3df132 1739 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
18e7555a
AV		 1740 goto done_release;
1741 }
1742
1743 dc &= MPS_MASK;
1744 if (dc == (dw & MPS_MASK))
1745 goto done_release;
1746
1747 dw &= ~MPS_MASK;
1748 dw |= dc;
1749 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
1750 if (rval != QLA_SUCCESS) {
7c3df132 1751 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
18e7555a
AV		 1752 }
1753
1754done_release:
1755 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
1756 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1757 ql_log(ql_log_warn, vha, 0x006d,
1758 "Unable to release semaphore.\n");
18e7555a
AV		 1759 }
1760
1761done:
1762 return rval;
1763}
1764
8d93f550
CD		 1765int
1766qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
1767{
1768 /* Don't try to reallocate the array */
1769 if (req->outstanding_cmds)
1770 return QLA_SUCCESS;
1771
1772 if (!IS_FWI2_CAPABLE(ha) || (ha->mqiobase &&
1773 (ql2xmultique_tag || ql2xmaxqueues > 1)))
1774 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
1775 else {
03e8c680
QT		 1776 if (ha->cur_fw_xcb_count <= ha->cur_fw_iocb_count)
1777 req->num_outstanding_cmds = ha->cur_fw_xcb_count;
8d93f550 1778 else
03e8c680 1779 req->num_outstanding_cmds = ha->cur_fw_iocb_count;
8d93f550
CD		 1780 }
1781
1782 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1783 req->num_outstanding_cmds, GFP_KERNEL);
1784
1785 if (!req->outstanding_cmds) {
1786 /*
1787 * Try to allocate a minimal size just so we can get through
1788 * initialization.
1789 */
1790 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
1791 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1792 req->num_outstanding_cmds, GFP_KERNEL);
1793
1794 if (!req->outstanding_cmds) {
1795 ql_log(ql_log_fatal, NULL, 0x0126,
1796 "Failed to allocate memory for "
1797 "outstanding_cmds for req_que %p.\n", req);
1798 req->num_outstanding_cmds = 0;
1799 return QLA_FUNCTION_FAILED;
1800 }
1801 }
1802
1803 return QLA_SUCCESS;
1804}
1805
1da177e4
LT		 1806/**
1807 * qla2x00_setup_chip() - Load and start RISC firmware.
1808 * @ha: HA context
1809 *
1810 * Returns 0 on success.
1811 */
1812static int
e315cd28 1813qla2x00_setup_chip(scsi_qla_host_t *vha)
1da177e4 1814{
0107109e
AV		 1815 int rval;
1816 uint32_t srisc_address = 0;
e315cd28 1817 struct qla_hw_data *ha = vha->hw;
3db0652e
AV		 1818 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1819 unsigned long flags;
dda772e8 1820 uint16_t fw_major_version;
3db0652e 1821
7ec0effd 1822 if (IS_P3P_TYPE(ha)) {
a9083016 1823 rval = ha->isp_ops->load_risc(vha, &srisc_address);
14e303d9
AV		 1824 if (rval == QLA_SUCCESS) {
1825 qla2x00_stop_firmware(vha);
a9083016 1826 goto enable_82xx_npiv;
14e303d9 1827 } else
b963752f 1828 goto failed;
a9083016
GM		 1829 }
1830
3db0652e
AV		 1831 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1832 /* Disable SRAM, Instruction RAM and GP RAM parity. */
1833 spin_lock_irqsave(&ha->hardware_lock, flags);
1834 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
1835 RD_REG_WORD(&reg->hccr);
1836 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1837 }
1da177e4 1838
18e7555a
AV		 1839 qla81xx_mpi_sync(vha);
1840
1da177e4 1841 /* Load firmware sequences */
e315cd28 1842 rval = ha->isp_ops->load_risc(vha, &srisc_address);
0107109e 1843 if (rval == QLA_SUCCESS) {
7c3df132
SK		 1844 ql_dbg(ql_dbg_init, vha, 0x00c9,
1845 "Verifying Checksum of loaded RISC code.\n");
1da177e4 1846
e315cd28 1847 rval = qla2x00_verify_checksum(vha, srisc_address);
1da177e4
LT		 1848 if (rval == QLA_SUCCESS) {
1849 /* Start firmware execution. */
7c3df132
SK		 1850 ql_dbg(ql_dbg_init, vha, 0x00ca,
1851 "Starting firmware.\n");
1da177e4 1852
b0d6cabd
HM		 1853 if (ql2xexlogins)
1854 ha->flags.exlogins_enabled = 1;
1855
2f56a7f1
HM		 1856 if (ql2xexchoffld)
1857 ha->flags.exchoffld_enabled = 1;
1858
e315cd28 1859 rval = qla2x00_execute_fw(vha, srisc_address);
1da177e4 1860 /* Retrieve firmware information. */
dda772e8 1861 if (rval == QLA_SUCCESS) {
b0d6cabd
HM		 1862 rval = qla2x00_set_exlogins_buffer(vha);
1863 if (rval != QLA_SUCCESS)
1864 goto failed;
1865
2f56a7f1
HM		 1866 rval = qla2x00_set_exchoffld_buffer(vha);
1867 if (rval != QLA_SUCCESS)
1868 goto failed;
1869
a9083016 1870enable_82xx_npiv:
dda772e8 1871 fw_major_version = ha->fw_major_version;
7ec0effd 1872 if (IS_P3P_TYPE(ha))
3173167f 1873 qla82xx_check_md_needed(vha);
6246b8a1
GM		 1874 else
1875 rval = qla2x00_get_fw_version(vha);
ca9e9c3e
AV		 1876 if (rval != QLA_SUCCESS)
1877 goto failed;
2c3dfe3f 1878 ha->flags.npiv_supported = 0;
e315cd28 1879 if (IS_QLA2XXX_MIDTYPE(ha) &&
946fb891 1880 (ha->fw_attributes & BIT_2)) {
2c3dfe3f 1881 ha->flags.npiv_supported = 1;
4d0ea247
SJ		 1882 if ((!ha->max_npiv_vports) ||
1883 ((ha->max_npiv_vports + 1) %
eb66dc60 1884 MIN_MULTI_ID_FABRIC))
4d0ea247 1885 ha->max_npiv_vports =
eb66dc60 1886 MIN_MULTI_ID_FABRIC - 1;
4d0ea247 1887 }
03e8c680 1888 qla2x00_get_resource_cnts(vha);
d743de66 1889
8d93f550
CD		 1890 /*
1891 * Allocate the array of outstanding commands
1892 * now that we know the firmware resources.
1893 */
1894 rval = qla2x00_alloc_outstanding_cmds(ha,
1895 vha->req);
1896 if (rval != QLA_SUCCESS)
1897 goto failed;
1898
be5ea3cf 1899 if (!fw_major_version && ql2xallocfwdump
7ec0effd 1900 && !(IS_P3P_TYPE(ha)))
08de2844 1901 qla2x00_alloc_fw_dump(vha);
3b6e5b9d
CD		 1902 } else {
1903 goto failed;
1da177e4
LT		 1904 }
1905 } else {
7c3df132
SK		 1906 ql_log(ql_log_fatal, vha, 0x00cd,
1907 "ISP Firmware failed checksum.\n");
1908 goto failed;
1da177e4 1909 }
c74d88a4
AV		 1910 } else
1911 goto failed;
1da177e4 1912
3db0652e
AV		 1913 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1914 /* Enable proper parity. */
1915 spin_lock_irqsave(&ha->hardware_lock, flags);
1916 if (IS_QLA2300(ha))
1917 /* SRAM parity */
1918 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
1919 else
1920 /* SRAM, Instruction RAM and GP RAM parity */
1921 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
1922 RD_REG_WORD(&reg->hccr);
1923 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1924 }
1925
f3982d89
CD		 1926 if (IS_QLA27XX(ha))
1927 ha->flags.fac_supported = 1;
1928 else if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1d2874de
JC		 1929 uint32_t size;
1930
1931 rval = qla81xx_fac_get_sector_size(vha, &size);
1932 if (rval == QLA_SUCCESS) {
1933 ha->flags.fac_supported = 1;
1934 ha->fdt_block_size = size << 2;
1935 } else {
7c3df132 1936 ql_log(ql_log_warn, vha, 0x00ce,
1d2874de
JC		 1937 "Unsupported FAC firmware (%d.%02d.%02d).\n",
1938 ha->fw_major_version, ha->fw_minor_version,
1939 ha->fw_subminor_version);
1ca60e3b 1940
f73cb695 1941 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
6246b8a1
GM		 1942 ha->flags.fac_supported = 0;
1943 rval = QLA_SUCCESS;
1944 }
1d2874de
JC		 1945 }
1946 }
ca9e9c3e 1947failed:
1da177e4 1948 if (rval) {
7c3df132
SK		 1949 ql_log(ql_log_fatal, vha, 0x00cf,
1950 "Setup chip ****FAILED****.\n");
1da177e4
LT		 1951 }
1952
1953 return (rval);
1954}
1955
1956/**
1957 * qla2x00_init_response_q_entries() - Initializes response queue entries.
1958 * @ha: HA context
1959 *
1960 * Beginning of request ring has initialization control block already built
1961 * by nvram config routine.
1962 *
1963 * Returns 0 on success.
1964 */
73208dfd
AC		 1965void
1966qla2x00_init_response_q_entries(struct rsp_que *rsp)
1da177e4
LT		 1967{
1968 uint16_t cnt;
1969 response_t *pkt;
1970
2afa19a9
AC		 1971 rsp->ring_ptr = rsp->ring;
1972 rsp->ring_index = 0;
1973 rsp->status_srb = NULL;
e315cd28
AC		 1974 pkt = rsp->ring_ptr;
1975 for (cnt = 0; cnt < rsp->length; cnt++) {
1da177e4
LT		 1976 pkt->signature = RESPONSE_PROCESSED;
1977 pkt++;
1978 }
1da177e4
LT		 1979}
1980
1981/**
1982 * qla2x00_update_fw_options() - Read and process firmware options.
1983 * @ha: HA context
1984 *
1985 * Returns 0 on success.
1986 */
abbd8870 1987void
e315cd28 1988qla2x00_update_fw_options(scsi_qla_host_t *vha)
1da177e4
LT		 1989{
1990 uint16_t swing, emphasis, tx_sens, rx_sens;
e315cd28 1991 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 1992
1993 memset(ha->fw_options, 0, sizeof(ha->fw_options));
e315cd28 1994 qla2x00_get_fw_options(vha, ha->fw_options);
1da177e4
LT		 1995
1996 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1997 return;
1998
1999 /* Serial Link options. */
7c3df132
SK		 2000 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
2001 "Serial link options.\n");
2002 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
2003 (uint8_t *)&ha->fw_seriallink_options,
2004 sizeof(ha->fw_seriallink_options));
1da177e4
LT		 2005
2006 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
2007 if (ha->fw_seriallink_options[3] & BIT_2) {
2008 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
2009
2010 /* 1G settings */
2011 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
2012 emphasis = (ha->fw_seriallink_options[2] &
2013 (BIT_4 | BIT_3)) >> 3;
2014 tx_sens = ha->fw_seriallink_options[0] &
fa2a1ce5 2015 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 2016 rx_sens = (ha->fw_seriallink_options[0] &
2017 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
2018 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
2019 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
2020 if (rx_sens == 0x0)
2021 rx_sens = 0x3;
2022 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
2023 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
2024 ha->fw_options[10] |= BIT_5 |
2025 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
2026 (tx_sens & (BIT_1 | BIT_0));
2027
2028 /* 2G settings */
2029 swing = (ha->fw_seriallink_options[2] &
2030 (BIT_7 | BIT_6 | BIT_5)) >> 5;
2031 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
2032 tx_sens = ha->fw_seriallink_options[1] &
fa2a1ce5 2033 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 2034 rx_sens = (ha->fw_seriallink_options[1] &
2035 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
2036 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
2037 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
2038 if (rx_sens == 0x0)
2039 rx_sens = 0x3;
2040 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
2041 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
2042 ha->fw_options[11] |= BIT_5 |
2043 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
2044 (tx_sens & (BIT_1 | BIT_0));
2045 }
2046
2047 /* FCP2 options. */
2048 /* Return command IOCBs without waiting for an ABTS to complete. */
2049 ha->fw_options[3] |= BIT_13;
2050
2051 /* LED scheme. */
2052 if (ha->flags.enable_led_scheme)
2053 ha->fw_options[2] |= BIT_12;
2054
48c02fde 2055 /* Detect ISP6312. */
2056 if (IS_QLA6312(ha))
2057 ha->fw_options[2] |= BIT_13;
2058
088d09d4
GM		 2059 /* Set Retry FLOGI in case of P2P connection */
2060 if (ha->operating_mode == P2P) {
2061 ha->fw_options[2] |= BIT_3;
2062 ql_dbg(ql_dbg_disc, vha, 0x2100,
2063 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
2064 __func__, ha->fw_options[2]);
2065 }
2066
1da177e4 2067 /* Update firmware options. */
e315cd28 2068 qla2x00_set_fw_options(vha, ha->fw_options);
1da177e4
LT		 2069}
2070
0107109e 2071void
e315cd28 2072qla24xx_update_fw_options(scsi_qla_host_t *vha)
0107109e
AV		 2073{
2074 int rval;
e315cd28 2075 struct qla_hw_data *ha = vha->hw;
0107109e 2076
7ec0effd 2077 if (IS_P3P_TYPE(ha))
a9083016
GM		 2078 return;
2079
f198cafa
HM		 2080 /* Hold status IOCBs until ABTS response received. */
2081 if (ql2xfwholdabts)
2082 ha->fw_options[3] |= BIT_12;
2083
088d09d4
GM		 2084 /* Set Retry FLOGI in case of P2P connection */
2085 if (ha->operating_mode == P2P) {
2086 ha->fw_options[2] |= BIT_3;
2087 ql_dbg(ql_dbg_disc, vha, 0x2101,
2088 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
2089 __func__, ha->fw_options[2]);
2090 }
2091
0107109e 2092 /* Update Serial Link options. */
f94097ed 2093 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
0107109e
AV		 2094 return;
2095
e315cd28 2096 rval = qla2x00_set_serdes_params(vha,
f94097ed 2097 le16_to_cpu(ha->fw_seriallink_options24[1]),
2098 le16_to_cpu(ha->fw_seriallink_options24[2]),
2099 le16_to_cpu(ha->fw_seriallink_options24[3]));
0107109e 2100 if (rval != QLA_SUCCESS) {
7c3df132 2101 ql_log(ql_log_warn, vha, 0x0104,
0107109e
AV		 2102 "Unable to update Serial Link options (%x).\n", rval);
2103 }
2104}
2105
abbd8870 2106void
e315cd28 2107qla2x00_config_rings(struct scsi_qla_host *vha)
abbd8870 2108{
e315cd28 2109 struct qla_hw_data *ha = vha->hw;
3d71644c 2110 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
73208dfd
AC		 2111 struct req_que *req = ha->req_q_map[0];
2112 struct rsp_que *rsp = ha->rsp_q_map[0];
abbd8870
AV		 2113
2114 /* Setup ring parameters in initialization control block. */
ad950360
BVA		 2115 ha->init_cb->request_q_outpointer = cpu_to_le16(0);
2116 ha->init_cb->response_q_inpointer = cpu_to_le16(0);
e315cd28
AC		 2117 ha->init_cb->request_q_length = cpu_to_le16(req->length);
2118 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
2119 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
2120 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
2121 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
2122 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
abbd8870
AV		 2123
2124 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
2125 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
2126 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
2127 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
2128 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
2129}
2130
0107109e 2131void
e315cd28 2132qla24xx_config_rings(struct scsi_qla_host *vha)
0107109e 2133{
e315cd28 2134 struct qla_hw_data *ha = vha->hw;
118e2ef9 2135 device_reg_t *reg = ISP_QUE_REG(ha, 0);
73208dfd
AC		 2136 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
2137 struct qla_msix_entry *msix;
0107109e 2138 struct init_cb_24xx *icb;
73208dfd
AC		 2139 uint16_t rid = 0;
2140 struct req_que *req = ha->req_q_map[0];
2141 struct rsp_que *rsp = ha->rsp_q_map[0];
0107109e 2142
6246b8a1 2143 /* Setup ring parameters in initialization control block. */
0107109e 2144 icb = (struct init_cb_24xx *)ha->init_cb;
ad950360
BVA		 2145 icb->request_q_outpointer = cpu_to_le16(0);
2146 icb->response_q_inpointer = cpu_to_le16(0);
e315cd28
AC		 2147 icb->request_q_length = cpu_to_le16(req->length);
2148 icb->response_q_length = cpu_to_le16(rsp->length);
2149 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
2150 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
2151 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
2152 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
0107109e 2153
2d70c103 2154 /* Setup ATIO queue dma pointers for target mode */
ad950360 2155 icb->atio_q_inpointer = cpu_to_le16(0);
2d70c103
NB		 2156 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
2157 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
2158 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
2159
7c6300e3 2160 if (IS_SHADOW_REG_CAPABLE(ha))
ad950360 2161 icb->firmware_options_2 |= cpu_to_le32(BIT_30|BIT_29);
7c6300e3 2162
f73cb695 2163 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
ad950360
BVA		 2164 icb->qos = cpu_to_le16(QLA_DEFAULT_QUE_QOS);
2165 icb->rid = cpu_to_le16(rid);
73208dfd
AC		 2166 if (ha->flags.msix_enabled) {
2167 msix = &ha->msix_entries[1];
7c3df132
SK		 2168 ql_dbg(ql_dbg_init, vha, 0x00fd,
2169 "Registering vector 0x%x for base que.\n",
2170 msix->entry);
73208dfd
AC		 2171 icb->msix = cpu_to_le16(msix->entry);
2172 }
2173 /* Use alternate PCI bus number */
2174 if (MSB(rid))
ad950360 2175 icb->firmware_options_2 |= cpu_to_le32(BIT_19);
73208dfd
AC		 2176 /* Use alternate PCI devfn */
2177 if (LSB(rid))
ad950360 2178 icb->firmware_options_2 |= cpu_to_le32(BIT_18);
73208dfd 2179
3155754a 2180 /* Use Disable MSIX Handshake mode for capable adapters */
6246b8a1
GM		 2181 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
2182 (ha->flags.msix_enabled)) {
ad950360 2183 icb->firmware_options_2 &= cpu_to_le32(~BIT_22);
3155754a 2184 ha->flags.disable_msix_handshake = 1;
7c3df132
SK		 2185 ql_dbg(ql_dbg_init, vha, 0x00fe,
2186 "MSIX Handshake Disable Mode turned on.\n");
3155754a 2187 } else {
ad950360 2188 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
3155754a 2189 }
ad950360 2190 icb->firmware_options_2 |= cpu_to_le32(BIT_23);
73208dfd
AC		 2191
2192 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
2193 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
2194 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
2195 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
2196 } else {
2197 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
2198 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
2199 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
2200 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
2201 }
aa230bc5 2202 qlt_24xx_config_rings(vha);
2d70c103 2203
73208dfd
AC		 2204 /* PCI posting */
2205 RD_REG_DWORD(&ioreg->hccr);
0107109e
AV		 2206}
2207
1da177e4
LT		 2208/**
2209 * qla2x00_init_rings() - Initializes firmware.
2210 * @ha: HA context
2211 *
2212 * Beginning of request ring has initialization control block already built
2213 * by nvram config routine.
2214 *
2215 * Returns 0 on success.
2216 */
8ae6d9c7 2217int
e315cd28 2218qla2x00_init_rings(scsi_qla_host_t *vha)
1da177e4
LT		 2219{
2220 int rval;
2221 unsigned long flags = 0;
29bdccbe 2222 int cnt, que;
e315cd28 2223 struct qla_hw_data *ha = vha->hw;
29bdccbe
AC		 2224 struct req_que *req;
2225 struct rsp_que *rsp;
2c3dfe3f
SJ		 2226 struct mid_init_cb_24xx *mid_init_cb =
2227 (struct mid_init_cb_24xx *) ha->init_cb;
1da177e4
LT		 2228
2229 spin_lock_irqsave(&ha->hardware_lock, flags);
2230
2231 /* Clear outstanding commands array. */
2afa19a9 2232 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 2233 req = ha->req_q_map[que];
cb43285f 2234 if (!req || !test_bit(que, ha->req_qid_map))
29bdccbe 2235 continue;
7c6300e3
JC		 2236 req->out_ptr = (void *)(req->ring + req->length);
2237 *req->out_ptr = 0;
8d93f550 2238 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
29bdccbe 2239 req->outstanding_cmds[cnt] = NULL;
1da177e4 2240
2afa19a9 2241 req->current_outstanding_cmd = 1;
1da177e4 2242
29bdccbe
AC		 2243 /* Initialize firmware. */
2244 req->ring_ptr = req->ring;
2245 req->ring_index = 0;
2246 req->cnt = req->length;
2247 }
1da177e4 2248
2afa19a9 2249 for (que = 0; que < ha->max_rsp_queues; que++) {
29bdccbe 2250 rsp = ha->rsp_q_map[que];
cb43285f 2251 if (!rsp || !test_bit(que, ha->rsp_qid_map))
29bdccbe 2252 continue;
7c6300e3
JC		 2253 rsp->in_ptr = (void *)(rsp->ring + rsp->length);
2254 *rsp->in_ptr = 0;
29bdccbe 2255 /* Initialize response queue entries */
8ae6d9c7
GM		 2256 if (IS_QLAFX00(ha))
2257 qlafx00_init_response_q_entries(rsp);
2258 else
2259 qla2x00_init_response_q_entries(rsp);
29bdccbe 2260 }
1da177e4 2261
2d70c103
NB		 2262 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
2263 ha->tgt.atio_ring_index = 0;
2264 /* Initialize ATIO queue entries */
2265 qlt_init_atio_q_entries(vha);
2266
e315cd28 2267 ha->isp_ops->config_rings(vha);
1da177e4
LT		 2268
2269 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2270
8ae6d9c7
GM		 2271 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
2272
2273 if (IS_QLAFX00(ha)) {
2274 rval = qlafx00_init_firmware(vha, ha->init_cb_size);
2275 goto next_check;
2276 }
2277
1da177e4 2278 /* Update any ISP specific firmware options before initialization. */
e315cd28 2279 ha->isp_ops->update_fw_options(vha);
1da177e4 2280
605aa2bc 2281 if (ha->flags.npiv_supported) {
45980cc2 2282 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
605aa2bc 2283 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
c48339de 2284 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
605aa2bc
LC		 2285 }
2286
24a08138 2287 if (IS_FWI2_CAPABLE(ha)) {
ad950360 2288 mid_init_cb->options = cpu_to_le16(BIT_1);
24a08138 2289 mid_init_cb->init_cb.execution_throttle =
03e8c680 2290 cpu_to_le16(ha->cur_fw_xcb_count);
40f3862b
JC		 2291 ha->flags.dport_enabled =
2292 (mid_init_cb->init_cb.firmware_options_1 & BIT_7) != 0;
2293 ql_dbg(ql_dbg_init, vha, 0x0191, "DPORT Support: %s.\n",
2294 (ha->flags.dport_enabled) ? "enabled" : "disabled");
2295 /* FA-WWPN Status */
2486c627 2296 ha->flags.fawwpn_enabled =
40f3862b 2297 (mid_init_cb->init_cb.firmware_options_1 & BIT_6) != 0;
2486c627
HM		 2298 ql_dbg(ql_dbg_init, vha, 0x0141, "FA-WWPN Support: %s.\n",
2299 (ha->flags.fawwpn_enabled) ? "enabled" : "disabled");
24a08138 2300 }
2c3dfe3f 2301
e315cd28 2302 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
8ae6d9c7 2303next_check:
1da177e4 2304 if (rval) {
7c3df132
SK		 2305 ql_log(ql_log_fatal, vha, 0x00d2,
2306 "Init Firmware **** FAILED ****.\n");
1da177e4 2307 } else {
7c3df132
SK		 2308 ql_dbg(ql_dbg_init, vha, 0x00d3,
2309 "Init Firmware -- success.\n");
1da177e4
LT		 2310 }
2311
2312 return (rval);
2313}
2314
2315/**
2316 * qla2x00_fw_ready() - Waits for firmware ready.
2317 * @ha: HA context
2318 *
2319 * Returns 0 on success.
2320 */
2321static int
e315cd28 2322qla2x00_fw_ready(scsi_qla_host_t *vha)
1da177e4
LT		 2323{
2324 int rval;
4d4df193 2325 unsigned long wtime, mtime, cs84xx_time;
1da177e4
LT		 2326 uint16_t min_wait; /* Minimum wait time if loop is down */
2327 uint16_t wait_time; /* Wait time if loop is coming ready */
b5a340dd 2328 uint16_t state[6];
e315cd28 2329 struct qla_hw_data *ha = vha->hw;
1da177e4 2330
8ae6d9c7
GM		 2331 if (IS_QLAFX00(vha->hw))
2332 return qlafx00_fw_ready(vha);
2333
1da177e4
LT		 2334 rval = QLA_SUCCESS;
2335
33461491
CD		 2336 /* Time to wait for loop down */
2337 if (IS_P3P_TYPE(ha))
2338 min_wait = 30;
2339 else
2340 min_wait = 20;
1da177e4
LT		 2341
2342 /*
2343 * Firmware should take at most one RATOV to login, plus 5 seconds for
2344 * our own processing.
2345 */
2346 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
2347 wait_time = min_wait;
2348 }
2349
2350 /* Min wait time if loop down */
2351 mtime = jiffies + (min_wait * HZ);
2352
2353 /* wait time before firmware ready */
2354 wtime = jiffies + (wait_time * HZ);
2355
2356 /* Wait for ISP to finish LIP */
e315cd28 2357 if (!vha->flags.init_done)
7c3df132
SK		 2358 ql_log(ql_log_info, vha, 0x801e,
2359 "Waiting for LIP to complete.\n");
1da177e4
LT		 2360
2361 do {
5b939038 2362 memset(state, -1, sizeof(state));
e315cd28 2363 rval = qla2x00_get_firmware_state(vha, state);
1da177e4 2364 if (rval == QLA_SUCCESS) {
4d4df193 2365 if (state[0] < FSTATE_LOSS_OF_SYNC) {
e315cd28 2366 vha->device_flags &= ~DFLG_NO_CABLE;
1da177e4 2367 }
4d4df193 2368 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
7c3df132
SK		 2369 ql_dbg(ql_dbg_taskm, vha, 0x801f,
2370 "fw_state=%x 84xx=%x.\n", state[0],
2371 state[2]);
4d4df193
HK		 2372 if ((state[2] & FSTATE_LOGGED_IN) &&
2373 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
7c3df132
SK		 2374 ql_dbg(ql_dbg_taskm, vha, 0x8028,
2375 "Sending verify iocb.\n");
4d4df193
HK		 2376
2377 cs84xx_time = jiffies;
e315cd28 2378 rval = qla84xx_init_chip(vha);
7c3df132
SK		 2379 if (rval != QLA_SUCCESS) {
2380 ql_log(ql_log_warn,
cfb0919c 2381 vha, 0x8007,
7c3df132 2382 "Init chip failed.\n");
4d4df193 2383 break;
7c3df132 2384 }
4d4df193
HK		 2385
2386 /* Add time taken to initialize. */
2387 cs84xx_time = jiffies - cs84xx_time;
2388 wtime += cs84xx_time;
2389 mtime += cs84xx_time;
cfb0919c 2390 ql_dbg(ql_dbg_taskm, vha, 0x8008,
7c3df132
SK		 2391 "Increasing wait time by %ld. "
2392 "New time %ld.\n", cs84xx_time,
2393 wtime);
4d4df193
HK		 2394 }
2395 } else if (state[0] == FSTATE_READY) {
7c3df132
SK		 2396 ql_dbg(ql_dbg_taskm, vha, 0x8037,
2397 "F/W Ready - OK.\n");
1da177e4 2398
e315cd28 2399 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1da177e4
LT		 2400 &ha->login_timeout, &ha->r_a_tov);
2401
2402 rval = QLA_SUCCESS;
2403 break;
2404 }
2405
2406 rval = QLA_FUNCTION_FAILED;
2407
e315cd28 2408 if (atomic_read(&vha->loop_down_timer) &&
4d4df193 2409 state[0] != FSTATE_READY) {
1da177e4 2410 /* Loop down. Timeout on min_wait for states
fa2a1ce5
AV		 2411 * other than Wait for Login.
2412 */
1da177e4 2413 if (time_after_eq(jiffies, mtime)) {
7c3df132 2414 ql_log(ql_log_info, vha, 0x8038,
1da177e4
LT		 2415 "Cable is unplugged...\n");
2416
e315cd28 2417 vha->device_flags |= DFLG_NO_CABLE;
1da177e4
LT		 2418 break;
2419 }
2420 }
2421 } else {
2422 /* Mailbox cmd failed. Timeout on min_wait. */
cdbb0a4f 2423 if (time_after_eq(jiffies, mtime) ||
7190575f 2424 ha->flags.isp82xx_fw_hung)
1da177e4
LT		 2425 break;
2426 }
2427
2428 if (time_after_eq(jiffies, wtime))
2429 break;
2430
2431 /* Delay for a while */
2432 msleep(500);
1da177e4
LT		 2433 } while (1);
2434
7c3df132 2435 ql_dbg(ql_dbg_taskm, vha, 0x803a,
b5a340dd
JC		 2436 "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0],
2437 state[1], state[2], state[3], state[4], state[5], jiffies);
1da177e4 2438
cfb0919c 2439 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132
SK		 2440 ql_log(ql_log_warn, vha, 0x803b,
2441 "Firmware ready **** FAILED ****.\n");
1da177e4
LT		 2442 }
2443
2444 return (rval);
2445}
2446
2447/*
2448* qla2x00_configure_hba
2449* Setup adapter context.
2450*
2451* Input:
2452* ha = adapter state pointer.
2453*
2454* Returns:
2455* 0 = success
2456*
2457* Context:
2458* Kernel context.
2459*/
2460static int
e315cd28 2461qla2x00_configure_hba(scsi_qla_host_t *vha)
1da177e4
LT		 2462{
2463 int rval;
2464 uint16_t loop_id;
2465 uint16_t topo;
2c3dfe3f 2466 uint16_t sw_cap;
1da177e4
LT		 2467 uint8_t al_pa;
2468 uint8_t area;
2469 uint8_t domain;
2470 char connect_type[22];
e315cd28 2471 struct qla_hw_data *ha = vha->hw;
f24b5cb8 2472 unsigned long flags;
61e1b269 2473 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 2474
2475 /* Get host addresses. */
e315cd28 2476 rval = qla2x00_get_adapter_id(vha,
2c3dfe3f 2477 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
1da177e4 2478 if (rval != QLA_SUCCESS) {
e315cd28 2479 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
6246b8a1 2480 IS_CNA_CAPABLE(ha) ||
33135aa2 2481 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
7c3df132
SK		 2482 ql_dbg(ql_dbg_disc, vha, 0x2008,
2483 "Loop is in a transition state.\n");
33135aa2 2484 } else {
7c3df132
SK		 2485 ql_log(ql_log_warn, vha, 0x2009,
2486 "Unable to get host loop ID.\n");
61e1b269
JC		 2487 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
2488 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
2489 ql_log(ql_log_warn, vha, 0x1151,
2490 "Doing link init.\n");
2491 if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
2492 return rval;
2493 }
e315cd28 2494 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
33135aa2 2495 }
1da177e4
LT		 2496 return (rval);
2497 }
2498
2499 if (topo == 4) {
7c3df132
SK		 2500 ql_log(ql_log_info, vha, 0x200a,
2501 "Cannot get topology - retrying.\n");
1da177e4
LT		 2502 return (QLA_FUNCTION_FAILED);
2503 }
2504
e315cd28 2505 vha->loop_id = loop_id;
1da177e4
LT		 2506
2507 /* initialize */
2508 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
2509 ha->operating_mode = LOOP;
2c3dfe3f 2510 ha->switch_cap = 0;
1da177e4
LT		 2511
2512 switch (topo) {
2513 case 0:
7c3df132 2514 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
1da177e4
LT		 2515 ha->current_topology = ISP_CFG_NL;
2516 strcpy(connect_type, "(Loop)");
2517 break;
2518
2519 case 1:
7c3df132 2520 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2c3dfe3f 2521 ha->switch_cap = sw_cap;
1da177e4
LT		 2522 ha->current_topology = ISP_CFG_FL;
2523 strcpy(connect_type, "(FL_Port)");
2524 break;
2525
2526 case 2:
7c3df132 2527 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
1da177e4
LT		 2528 ha->operating_mode = P2P;
2529 ha->current_topology = ISP_CFG_N;
2530 strcpy(connect_type, "(N_Port-to-N_Port)");
2531 break;
2532
2533 case 3:
7c3df132 2534 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2c3dfe3f 2535 ha->switch_cap = sw_cap;
1da177e4
LT		 2536 ha->operating_mode = P2P;
2537 ha->current_topology = ISP_CFG_F;
2538 strcpy(connect_type, "(F_Port)");
2539 break;
2540
2541 default:
7c3df132
SK		 2542 ql_dbg(ql_dbg_disc, vha, 0x200f,
2543 "HBA in unknown topology %x, using NL.\n", topo);
1da177e4
LT		 2544 ha->current_topology = ISP_CFG_NL;
2545 strcpy(connect_type, "(Loop)");
2546 break;
2547 }
2548
2549 /* Save Host port and loop ID. */
2550 /* byte order - Big Endian */
e315cd28
AC		 2551 vha->d_id.b.domain = domain;
2552 vha->d_id.b.area = area;
2553 vha->d_id.b.al_pa = al_pa;
1da177e4 2554
f24b5cb8 2555 spin_lock_irqsave(&ha->vport_slock, flags);
2d70c103 2556 qlt_update_vp_map(vha, SET_AL_PA);
f24b5cb8 2557 spin_unlock_irqrestore(&ha->vport_slock, flags);
2d70c103 2558
e315cd28 2559 if (!vha->flags.init_done)
7c3df132
SK		 2560 ql_log(ql_log_info, vha, 0x2010,
2561 "Topology - %s, Host Loop address 0x%x.\n",
e315cd28 2562 connect_type, vha->loop_id);
1da177e4 2563
1da177e4
LT		 2564 return(rval);
2565}
2566
a9083016 2567inline void
e315cd28
AC		 2568qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
2569 char *def)
9bb9fcf2
AV		 2570{
2571 char *st, *en;
2572 uint16_t index;
e315cd28 2573 struct qla_hw_data *ha = vha->hw;
ab671149 2574 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
6246b8a1 2575 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
9bb9fcf2
AV		 2576
2577 if (memcmp(model, BINZERO, len) != 0) {
2578 strncpy(ha->model_number, model, len);
2579 st = en = ha->model_number;
2580 en += len - 1;
2581 while (en > st) {
2582 if (*en != 0x20 && *en != 0x00)
2583 break;
2584 *en-- = '\0';
2585 }
2586
2587 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2588 if (use_tbl &&
2589 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 2590 index < QLA_MODEL_NAMES)
1ee27146
JC		 2591 strncpy(ha->model_desc,
2592 qla2x00_model_name[index * 2 + 1],
2593 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2594 } else {
2595 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2596 if (use_tbl &&
2597 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2
AV		 2598 index < QLA_MODEL_NAMES) {
2599 strcpy(ha->model_number,
2600 qla2x00_model_name[index * 2]);
1ee27146
JC		 2601 strncpy(ha->model_desc,
2602 qla2x00_model_name[index * 2 + 1],
2603 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2604 } else {
2605 strcpy(ha->model_number, def);
2606 }
2607 }
1ee27146 2608 if (IS_FWI2_CAPABLE(ha))
e315cd28 2609 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
1ee27146 2610 sizeof(ha->model_desc));
9bb9fcf2
AV		 2611}
2612
4e08df3f
DM		 2613/* On sparc systems, obtain port and node WWN from firmware
2614 * properties.
2615 */
e315cd28 2616static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4e08df3f
DM		 2617{
2618#ifdef CONFIG_SPARC
e315cd28 2619 struct qla_hw_data *ha = vha->hw;
4e08df3f 2620 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 2621 struct device_node *dp = pci_device_to_OF_node(pdev);
2622 const u8 *val;
4e08df3f
DM		 2623 int len;
2624
2625 val = of_get_property(dp, "port-wwn", &len);
2626 if (val && len >= WWN_SIZE)
2627 memcpy(nv->port_name, val, WWN_SIZE);
2628
2629 val = of_get_property(dp, "node-wwn", &len);
2630 if (val && len >= WWN_SIZE)
2631 memcpy(nv->node_name, val, WWN_SIZE);
2632#endif
2633}
2634
1da177e4
LT		 2635/*
2636* NVRAM configuration for ISP 2xxx
2637*
2638* Input:
2639* ha = adapter block pointer.
2640*
2641* Output:
2642* initialization control block in response_ring
2643* host adapters parameters in host adapter block
2644*
2645* Returns:
2646* 0 = success.
2647*/
abbd8870 2648int
e315cd28 2649qla2x00_nvram_config(scsi_qla_host_t *vha)
1da177e4 2650{
4e08df3f 2651 int rval;
0107109e
AV		 2652 uint8_t chksum = 0;
2653 uint16_t cnt;
2654 uint8_t *dptr1, *dptr2;
e315cd28 2655 struct qla_hw_data *ha = vha->hw;
0107109e 2656 init_cb_t *icb = ha->init_cb;
281afe19
SJ		 2657 nvram_t *nv = ha->nvram;
2658 uint8_t *ptr = ha->nvram;
3d71644c 2659 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2660
4e08df3f
DM		 2661 rval = QLA_SUCCESS;
2662
1da177e4 2663 /* Determine NVRAM starting address. */
0107109e 2664 ha->nvram_size = sizeof(nvram_t);
1da177e4
LT		 2665 ha->nvram_base = 0;
2666 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
2667 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
2668 ha->nvram_base = 0x80;
2669
2670 /* Get NVRAM data and calculate checksum. */
e315cd28 2671 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
0107109e
AV		 2672 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
2673 chksum += *ptr++;
1da177e4 2674
7c3df132
SK		 2675 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
2676 "Contents of NVRAM.\n");
2677 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
2678 (uint8_t *)nv, ha->nvram_size);
1da177e4
LT		 2679
2680 /* Bad NVRAM data, set defaults parameters. */
2681 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
2682 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
2683 /* Reset NVRAM data. */
7c3df132 2684 ql_log(ql_log_warn, vha, 0x0064,
9e336520 2685 "Inconsistent NVRAM "
7c3df132
SK		 2686 "detected: checksum=0x%x id=%c version=0x%x.\n",
2687 chksum, nv->id[0], nv->nvram_version);
2688 ql_log(ql_log_warn, vha, 0x0065,
2689 "Falling back to "
2690 "functioning (yet invalid -- WWPN) defaults.\n");
4e08df3f
DM		 2691
2692 /*
2693 * Set default initialization control block.
2694 */
2695 memset(nv, 0, ha->nvram_size);
2696 nv->parameter_block_version = ICB_VERSION;
2697
2698 if (IS_QLA23XX(ha)) {
2699 nv->firmware_options[0] = BIT_2 | BIT_1;
2700 nv->firmware_options[1] = BIT_7 | BIT_5;
2701 nv->add_firmware_options[0] = BIT_5;
2702 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 2703 nv->frame_payload_size = 2048;
4e08df3f
DM		 2704 nv->special_options[1] = BIT_7;
2705 } else if (IS_QLA2200(ha)) {
2706 nv->firmware_options[0] = BIT_2 | BIT_1;
2707 nv->firmware_options[1] = BIT_7 | BIT_5;
2708 nv->add_firmware_options[0] = BIT_5;
2709 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 2710 nv->frame_payload_size = 1024;
4e08df3f
DM		 2711 } else if (IS_QLA2100(ha)) {
2712 nv->firmware_options[0] = BIT_3 | BIT_1;
2713 nv->firmware_options[1] = BIT_5;
98aee70d 2714 nv->frame_payload_size = 1024;
4e08df3f
DM		 2715 }
2716
ad950360
BVA		 2717 nv->max_iocb_allocation = cpu_to_le16(256);
2718 nv->execution_throttle = cpu_to_le16(16);
4e08df3f
DM		 2719 nv->retry_count = 8;
2720 nv->retry_delay = 1;
2721
2722 nv->port_name[0] = 33;
2723 nv->port_name[3] = 224;
2724 nv->port_name[4] = 139;
2725
e315cd28 2726 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 2727
2728 nv->login_timeout = 4;
2729
2730 /*
2731 * Set default host adapter parameters
2732 */
2733 nv->host_p[1] = BIT_2;
2734 nv->reset_delay = 5;
2735 nv->port_down_retry_count = 8;
ad950360 2736 nv->max_luns_per_target = cpu_to_le16(8);
4e08df3f
DM		 2737 nv->link_down_timeout = 60;
2738
2739 rval = 1;
1da177e4
LT		 2740 }
2741
2742#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
2743 /*
2744 * The SN2 does not provide BIOS emulation which means you can't change
2745 * potentially bogus BIOS settings. Force the use of default settings
2746 * for link rate and frame size. Hope that the rest of the settings
2747 * are valid.
2748 */
2749 if (ia64_platform_is("sn2")) {
98aee70d 2750 nv->frame_payload_size = 2048;
1da177e4
LT		 2751 if (IS_QLA23XX(ha))
2752 nv->special_options[1] = BIT_7;
2753 }
2754#endif
2755
2756 /* Reset Initialization control block */
0107109e 2757 memset(icb, 0, ha->init_cb_size);
1da177e4
LT		 2758
2759 /*
2760 * Setup driver NVRAM options.
2761 */
2762 nv->firmware_options[0] |= (BIT_6 | BIT_1);
2763 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
2764 nv->firmware_options[1] |= (BIT_5 | BIT_0);
2765 nv->firmware_options[1] &= ~BIT_4;
2766
2767 if (IS_QLA23XX(ha)) {
2768 nv->firmware_options[0] |= BIT_2;
2769 nv->firmware_options[0] &= ~BIT_3;
2d70c103 2770 nv->special_options[0] &= ~BIT_6;
0107109e 2771 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
1da177e4
LT		 2772
2773 if (IS_QLA2300(ha)) {
2774 if (ha->fb_rev == FPM_2310) {
2775 strcpy(ha->model_number, "QLA2310");
2776 } else {
2777 strcpy(ha->model_number, "QLA2300");
2778 }
2779 } else {
e315cd28 2780 qla2x00_set_model_info(vha, nv->model_number,
9bb9fcf2 2781 sizeof(nv->model_number), "QLA23xx");
1da177e4
LT		 2782 }
2783 } else if (IS_QLA2200(ha)) {
2784 nv->firmware_options[0] |= BIT_2;
2785 /*
2786 * 'Point-to-point preferred, else loop' is not a safe
2787 * connection mode setting.
2788 */
2789 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
2790 (BIT_5 | BIT_4)) {
2791 /* Force 'loop preferred, else point-to-point'. */
2792 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
2793 nv->add_firmware_options[0] |= BIT_5;
2794 }
2795 strcpy(ha->model_number, "QLA22xx");
2796 } else /*if (IS_QLA2100(ha))*/ {
2797 strcpy(ha->model_number, "QLA2100");
2798 }
2799
2800 /*
2801 * Copy over NVRAM RISC parameter block to initialization control block.
2802 */
2803 dptr1 = (uint8_t *)icb;
2804 dptr2 = (uint8_t *)&nv->parameter_block_version;
2805 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
2806 while (cnt--)
2807 *dptr1++ = *dptr2++;
2808
2809 /* Copy 2nd half. */
2810 dptr1 = (uint8_t *)icb->add_firmware_options;
2811 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
2812 while (cnt--)
2813 *dptr1++ = *dptr2++;
2814
5341e868
AV		 2815 /* Use alternate WWN? */
2816 if (nv->host_p[1] & BIT_7) {
2817 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
2818 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
2819 }
2820
1da177e4
LT		 2821 /* Prepare nodename */
2822 if ((icb->firmware_options[1] & BIT_6) == 0) {
2823 /*
2824 * Firmware will apply the following mask if the nodename was
2825 * not provided.
2826 */
2827 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
2828 icb->node_name[0] &= 0xF0;
2829 }
2830
2831 /*
2832 * Set host adapter parameters.
2833 */
3ce8866c
SK		 2834
2835 /*
2836 * BIT_7 in the host-parameters section allows for modification to
2837 * internal driver logging.
2838 */
0181944f 2839 if (nv->host_p[0] & BIT_7)
cfb0919c 2840 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1da177e4
LT		 2841 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
2842 /* Always load RISC code on non ISP2[12]00 chips. */
2843 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
2844 ha->flags.disable_risc_code_load = 0;
2845 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
2846 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
2847 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
06c22bd1 2848 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
d4c760c2 2849 ha->flags.disable_serdes = 0;
1da177e4
LT		 2850
2851 ha->operating_mode =
2852 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
2853
2854 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
2855 sizeof(ha->fw_seriallink_options));
2856
2857 /* save HBA serial number */
2858 ha->serial0 = icb->port_name[5];
2859 ha->serial1 = icb->port_name[6];
2860 ha->serial2 = icb->port_name[7];
e315cd28
AC		 2861 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
2862 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
1da177e4 2863
ad950360 2864 icb->execution_throttle = cpu_to_le16(0xFFFF);
1da177e4
LT		 2865
2866 ha->retry_count = nv->retry_count;
2867
2868 /* Set minimum login_timeout to 4 seconds. */
5b91490e 2869 if (nv->login_timeout != ql2xlogintimeout)
1da177e4
LT		 2870 nv->login_timeout = ql2xlogintimeout;
2871 if (nv->login_timeout < 4)
2872 nv->login_timeout = 4;
2873 ha->login_timeout = nv->login_timeout;
1da177e4 2874
00a537b8
AV		 2875 /* Set minimum RATOV to 100 tenths of a second. */
2876 ha->r_a_tov = 100;
1da177e4 2877
1da177e4
LT		 2878 ha->loop_reset_delay = nv->reset_delay;
2879
1da177e4
LT		 2880 /* Link Down Timeout = 0:
2881 *
2882 * When Port Down timer expires we will start returning
2883 * I/O's to OS with "DID_NO_CONNECT".
2884 *
2885 * Link Down Timeout != 0:
2886 *
2887 * The driver waits for the link to come up after link down
2888 * before returning I/Os to OS with "DID_NO_CONNECT".
fa2a1ce5 2889 */
1da177e4
LT		 2890 if (nv->link_down_timeout == 0) {
2891 ha->loop_down_abort_time =
354d6b21 2892 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
1da177e4
LT		 2893 } else {
2894 ha->link_down_timeout = nv->link_down_timeout;
2895 ha->loop_down_abort_time =
2896 (LOOP_DOWN_TIME - ha->link_down_timeout);
fa2a1ce5 2897 }
1da177e4 2898
1da177e4
LT		 2899 /*
2900 * Need enough time to try and get the port back.
2901 */
2902 ha->port_down_retry_count = nv->port_down_retry_count;
2903 if (qlport_down_retry)
2904 ha->port_down_retry_count = qlport_down_retry;
2905 /* Set login_retry_count */
2906 ha->login_retry_count = nv->retry_count;
2907 if (ha->port_down_retry_count == nv->port_down_retry_count &&
2908 ha->port_down_retry_count > 3)
2909 ha->login_retry_count = ha->port_down_retry_count;
2910 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
2911 ha->login_retry_count = ha->port_down_retry_count;
2912 if (ql2xloginretrycount)
2913 ha->login_retry_count = ql2xloginretrycount;
2914
ad950360 2915 icb->lun_enables = cpu_to_le16(0);
1da177e4
LT		 2916 icb->command_resource_count = 0;
2917 icb->immediate_notify_resource_count = 0;
ad950360 2918 icb->timeout = cpu_to_le16(0);
1da177e4
LT		 2919
2920 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
2921 /* Enable RIO */
2922 icb->firmware_options[0] &= ~BIT_3;
2923 icb->add_firmware_options[0] &=
2924 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
2925 icb->add_firmware_options[0] |= BIT_2;
2926 icb->response_accumulation_timer = 3;
2927 icb->interrupt_delay_timer = 5;
2928
e315cd28 2929 vha->flags.process_response_queue = 1;
1da177e4 2930 } else {
4fdfefe5 2931 /* Enable ZIO. */
e315cd28 2932 if (!vha->flags.init_done) {
4fdfefe5
AV		 2933 ha->zio_mode = icb->add_firmware_options[0] &
2934 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
2935 ha->zio_timer = icb->interrupt_delay_timer ?
2936 icb->interrupt_delay_timer: 2;
2937 }
1da177e4
LT		 2938 icb->add_firmware_options[0] &=
2939 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
e315cd28 2940 vha->flags.process_response_queue = 0;
4fdfefe5 2941 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d 2942 ha->zio_mode = QLA_ZIO_MODE_6;
2943
7c3df132 2944 ql_log(ql_log_info, vha, 0x0068,
4fdfefe5
AV		 2945 "ZIO mode %d enabled; timer delay (%d us).\n",
2946 ha->zio_mode, ha->zio_timer * 100);
1da177e4 2947
4fdfefe5
AV		 2948 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
2949 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
e315cd28 2950 vha->flags.process_response_queue = 1;
1da177e4
LT		 2951 }
2952 }
2953
4e08df3f 2954 if (rval) {
7c3df132
SK		 2955 ql_log(ql_log_warn, vha, 0x0069,
2956 "NVRAM configuration failed.\n");
4e08df3f
DM		 2957 }
2958 return (rval);
1da177e4
LT		 2959}
2960
19a7b4ae
JSEC		 2961static void
2962qla2x00_rport_del(void *data)
2963{
2964 fc_port_t *fcport = data;
d97994dc 2965 struct fc_rport *rport;
044d78e1 2966 unsigned long flags;
d97994dc 2967
044d78e1 2968 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
ac280b67 2969 rport = fcport->drport ? fcport->drport: fcport->rport;
d97994dc 2970 fcport->drport = NULL;
044d78e1 2971 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
df673274 2972 if (rport)
d97994dc 2973 fc_remote_port_delete(rport);
19a7b4ae
JSEC		 2974}
2975
1da177e4
LT		 2976/**
2977 * qla2x00_alloc_fcport() - Allocate a generic fcport.
2978 * @ha: HA context
2979 * @flags: allocation flags
2980 *
2981 * Returns a pointer to the allocated fcport, or NULL, if none available.
2982 */
9a069e19 2983fc_port_t *
e315cd28 2984qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
1da177e4
LT		 2985{
2986 fc_port_t *fcport;
2987
bbfbbbc1
MK		 2988 fcport = kzalloc(sizeof(fc_port_t), flags);
2989 if (!fcport)
2990 return NULL;
1da177e4
LT		 2991
2992 /* Setup fcport template structure. */
e315cd28 2993 fcport->vha = vha;
1da177e4
LT		 2994 fcport->port_type = FCT_UNKNOWN;
2995 fcport->loop_id = FC_NO_LOOP_ID;
ec426e10 2996 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
ad3e0eda 2997 fcport->supported_classes = FC_COS_UNSPECIFIED;
1da177e4 2998
bbfbbbc1 2999 return fcport;
1da177e4
LT		 3000}
3001
3002/*
3003 * qla2x00_configure_loop
3004 * Updates Fibre Channel Device Database with what is actually on loop.
3005 *
3006 * Input:
3007 * ha = adapter block pointer.
3008 *
3009 * Returns:
3010 * 0 = success.
3011 * 1 = error.
3012 * 2 = database was full and device was not configured.
3013 */
3014static int
e315cd28 3015qla2x00_configure_loop(scsi_qla_host_t *vha)
1da177e4
LT		 3016{
3017 int rval;
3018 unsigned long flags, save_flags;
e315cd28 3019 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3020 rval = QLA_SUCCESS;
3021
3022 /* Get Initiator ID */
e315cd28
AC		 3023 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
3024 rval = qla2x00_configure_hba(vha);
1da177e4 3025 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3026 ql_dbg(ql_dbg_disc, vha, 0x2013,
3027 "Unable to configure HBA.\n");
1da177e4
LT		 3028 return (rval);
3029 }
3030 }
3031
e315cd28 3032 save_flags = flags = vha->dpc_flags;
7c3df132
SK		 3033 ql_dbg(ql_dbg_disc, vha, 0x2014,
3034 "Configure loop -- dpc flags = 0x%lx.\n", flags);
1da177e4
LT		 3035
3036 /*
3037 * If we have both an RSCN and PORT UPDATE pending then handle them
3038 * both at the same time.
3039 */
e315cd28
AC		 3040 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
3041 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
1da177e4 3042
3064ff39
MH		 3043 qla2x00_get_data_rate(vha);
3044
1da177e4
LT		 3045 /* Determine what we need to do */
3046 if (ha->current_topology == ISP_CFG_FL &&
3047 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
3048
1da177e4
LT		 3049 set_bit(RSCN_UPDATE, &flags);
3050
3051 } else if (ha->current_topology == ISP_CFG_F &&
3052 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
3053
1da177e4
LT		 3054 set_bit(RSCN_UPDATE, &flags);
3055 clear_bit(LOCAL_LOOP_UPDATE, &flags);
21333b48
AV		 3056
3057 } else if (ha->current_topology == ISP_CFG_N) {
3058 clear_bit(RSCN_UPDATE, &flags);
1da177e4 3059
e315cd28 3060 } else if (!vha->flags.online ||
1da177e4
LT		 3061 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
3062
1da177e4
LT		 3063 set_bit(RSCN_UPDATE, &flags);
3064 set_bit(LOCAL_LOOP_UPDATE, &flags);
3065 }
3066
3067 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
7c3df132
SK		 3068 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
3069 ql_dbg(ql_dbg_disc, vha, 0x2015,
3070 "Loop resync needed, failing.\n");
1da177e4 3071 rval = QLA_FUNCTION_FAILED;
642ef983 3072 } else
e315cd28 3073 rval = qla2x00_configure_local_loop(vha);
1da177e4
LT		 3074 }
3075
3076 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
7c3df132
SK		 3077 if (LOOP_TRANSITION(vha)) {
3078 ql_dbg(ql_dbg_disc, vha, 0x201e,
3079 "Needs RSCN update and loop transition.\n");
1da177e4 3080 rval = QLA_FUNCTION_FAILED;
7c3df132 3081 }
e315cd28
AC		 3082 else
3083 rval = qla2x00_configure_fabric(vha);
1da177e4
LT		 3084 }
3085
3086 if (rval == QLA_SUCCESS) {
e315cd28
AC		 3087 if (atomic_read(&vha->loop_down_timer) ||
3088 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4
LT		 3089 rval = QLA_FUNCTION_FAILED;
3090 } else {
e315cd28 3091 atomic_set(&vha->loop_state, LOOP_READY);
7c3df132
SK		 3092 ql_dbg(ql_dbg_disc, vha, 0x2069,
3093 "LOOP READY.\n");
3bb67df5
DKU		 3094
3095 /*
3096 * Process any ATIO queue entries that came in
3097 * while we weren't online.
3098 */
3099 if (qla_tgt_mode_enabled(vha)) {
3100 if (IS_QLA27XX(ha) || IS_QLA83XX(ha)) {
3101 spin_lock_irqsave(&ha->tgt.atio_lock,
3102 flags);
3103 qlt_24xx_process_atio_queue(vha, 0);
3104 spin_unlock_irqrestore(
3105 &ha->tgt.atio_lock, flags);
3106 } else {
3107 spin_lock_irqsave(&ha->hardware_lock,
3108 flags);
3109 qlt_24xx_process_atio_queue(vha, 1);
3110 spin_unlock_irqrestore(
3111 &ha->hardware_lock, flags);
3112 }
3113 }
1da177e4
LT		 3114 }
3115 }
3116
3117 if (rval) {
7c3df132
SK		 3118 ql_dbg(ql_dbg_disc, vha, 0x206a,
3119 "%s *** FAILED ***.\n", __func__);
1da177e4 3120 } else {
7c3df132
SK		 3121 ql_dbg(ql_dbg_disc, vha, 0x206b,
3122 "%s: exiting normally.\n", __func__);
1da177e4
LT		 3123 }
3124
cc3ef7bc 3125 /* Restore state if a resync event occurred during processing */
e315cd28 3126 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4 3127 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
e315cd28 3128 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
f4658b6c 3129 if (test_bit(RSCN_UPDATE, &save_flags)) {
e315cd28 3130 set_bit(RSCN_UPDATE, &vha->dpc_flags);
f4658b6c 3131 }
1da177e4
LT		 3132 }
3133
3134 return (rval);
3135}
3136
3137
3138
3139/*
3140 * qla2x00_configure_local_loop
3141 * Updates Fibre Channel Device Database with local loop devices.
3142 *
3143 * Input:
3144 * ha = adapter block pointer.
3145 *
3146 * Returns:
3147 * 0 = success.
3148 */
3149static int
e315cd28 3150qla2x00_configure_local_loop(scsi_qla_host_t *vha)
1da177e4
LT		 3151{
3152 int rval, rval2;
3153 int found_devs;
3154 int found;
3155 fc_port_t *fcport, *new_fcport;
3156
3157 uint16_t index;
3158 uint16_t entries;
3159 char *id_iter;
3160 uint16_t loop_id;
3161 uint8_t domain, area, al_pa;
e315cd28 3162 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3163
3164 found_devs = 0;
3165 new_fcport = NULL;
642ef983 3166 entries = MAX_FIBRE_DEVICES_LOOP;
1da177e4 3167
1da177e4 3168 /* Get list of logged in devices. */
642ef983 3169 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
e315cd28 3170 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
1da177e4
LT		 3171 &entries);
3172 if (rval != QLA_SUCCESS)
3173 goto cleanup_allocation;
3174
7c3df132
SK		 3175 ql_dbg(ql_dbg_disc, vha, 0x2017,
3176 "Entries in ID list (%d).\n", entries);
3177 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
3178 (uint8_t *)ha->gid_list,
3179 entries * sizeof(struct gid_list_info));
1da177e4
LT		 3180
3181 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 3182 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3183 if (new_fcport == NULL) {
7c3df132
SK		 3184 ql_log(ql_log_warn, vha, 0x2018,
3185 "Memory allocation failed for fcport.\n");
1da177e4
LT		 3186 rval = QLA_MEMORY_ALLOC_FAILED;
3187 goto cleanup_allocation;
3188 }
3189 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
3190
3191 /*
3192 * Mark local devices that were present with FCF_DEVICE_LOST for now.
3193 */
e315cd28 3194 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3195 if (atomic_read(&fcport->state) == FCS_ONLINE &&
3196 fcport->port_type != FCT_BROADCAST &&
3197 (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3198
7c3df132
SK		 3199 ql_dbg(ql_dbg_disc, vha, 0x2019,
3200 "Marking port lost loop_id=0x%04x.\n",
3201 fcport->loop_id);
1da177e4 3202
ec426e10 3203 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3204 }
3205 }
3206
3207 /* Add devices to port list. */
3208 id_iter = (char *)ha->gid_list;
3209 for (index = 0; index < entries; index++) {
3210 domain = ((struct gid_list_info *)id_iter)->domain;
3211 area = ((struct gid_list_info *)id_iter)->area;
3212 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
abbd8870 3213 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1da177e4
LT		 3214 loop_id = (uint16_t)
3215 ((struct gid_list_info *)id_iter)->loop_id_2100;
abbd8870 3216 else
1da177e4
LT		 3217 loop_id = le16_to_cpu(
3218 ((struct gid_list_info *)id_iter)->loop_id);
abbd8870 3219 id_iter += ha->gid_list_info_size;
1da177e4
LT		 3220
3221 /* Bypass reserved domain fields. */
3222 if ((domain & 0xf0) == 0xf0)
3223 continue;
3224
3225 /* Bypass if not same domain and area of adapter. */
f7d289f6 3226 if (area && domain &&
e315cd28 3227 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
1da177e4
LT		 3228 continue;
3229
3230 /* Bypass invalid local loop ID. */
3231 if (loop_id > LAST_LOCAL_LOOP_ID)
3232 continue;
3233
370d550e
AE		 3234 memset(new_fcport, 0, sizeof(fc_port_t));
3235
1da177e4
LT		 3236 /* Fill in member data. */
3237 new_fcport->d_id.b.domain = domain;
3238 new_fcport->d_id.b.area = area;
3239 new_fcport->d_id.b.al_pa = al_pa;
3240 new_fcport->loop_id = loop_id;
e315cd28 3241 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
1da177e4 3242 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 3243 ql_dbg(ql_dbg_disc, vha, 0x201a,
3244 "Failed to retrieve fcport information "
3245 "-- get_port_database=%x, loop_id=0x%04x.\n",
3246 rval2, new_fcport->loop_id);
3247 ql_dbg(ql_dbg_disc, vha, 0x201b,
3248 "Scheduling resync.\n");
e315cd28 3249 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 3250 continue;
3251 }
3252
3253 /* Check for matching device in port list. */
3254 found = 0;
3255 fcport = NULL;
e315cd28 3256 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3257 if (memcmp(new_fcport->port_name, fcport->port_name,
3258 WWN_SIZE))
3259 continue;
3260
ddb9b126 3261 fcport->flags &= ~FCF_FABRIC_DEVICE;
1da177e4
LT		 3262 fcport->loop_id = new_fcport->loop_id;
3263 fcport->port_type = new_fcport->port_type;
3264 fcport->d_id.b24 = new_fcport->d_id.b24;
3265 memcpy(fcport->node_name, new_fcport->node_name,
3266 WWN_SIZE);
3267
3268 found++;
3269 break;
3270 }
3271
3272 if (!found) {
3273 /* New device, add to fcports list. */
e315cd28 3274 list_add_tail(&new_fcport->list, &vha->vp_fcports);
1da177e4
LT		 3275
3276 /* Allocate a new replacement fcport. */
3277 fcport = new_fcport;
e315cd28 3278 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3279 if (new_fcport == NULL) {
7c3df132
SK		 3280 ql_log(ql_log_warn, vha, 0x201c,
3281 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3282 rval = QLA_MEMORY_ALLOC_FAILED;
3283 goto cleanup_allocation;
3284 }
3285 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
3286 }
3287
d8b45213 3288 /* Base iIDMA settings on HBA port speed. */
a3cbdfad 3289 fcport->fp_speed = ha->link_data_rate;
d8b45213 3290
e315cd28 3291 qla2x00_update_fcport(vha, fcport);
1da177e4
LT		 3292
3293 found_devs++;
3294 }
3295
3296cleanup_allocation:
c9475cb0 3297 kfree(new_fcport);
1da177e4
LT		 3298
3299 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3300 ql_dbg(ql_dbg_disc, vha, 0x201d,
3301 "Configure local loop error exit: rval=%x.\n", rval);
1da177e4
LT		 3302 }
3303
1da177e4
LT		 3304 return (rval);
3305}
3306
d8b45213 3307static void
e315cd28 3308qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
d8b45213 3309{
d8b45213 3310 int rval;
93f2bd67 3311 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 3312 struct qla_hw_data *ha = vha->hw;
d8b45213 3313
c76f2c01 3314 if (!IS_IIDMA_CAPABLE(ha))
d8b45213
AV		 3315 return;
3316
c9afb9a2
GM		 3317 if (atomic_read(&fcport->state) != FCS_ONLINE)
3318 return;
3319
39bd9622
AV		 3320 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
3321 fcport->fp_speed > ha->link_data_rate)
d8b45213
AV		 3322 return;
3323
e315cd28 3324 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
a3cbdfad 3325 mb);
d8b45213 3326 if (rval != QLA_SUCCESS) {
7c3df132 3327 ql_dbg(ql_dbg_disc, vha, 0x2004,
7b833558
OK		 3328 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n",
3329 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]);
d8b45213 3330 } else {
7c3df132 3331 ql_dbg(ql_dbg_disc, vha, 0x2005,
7b833558 3332 "iIDMA adjusted to %s GB/s on %8phN.\n",
d0297c9a 3333 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
7b833558 3334 fcport->port_name);
d8b45213
AV		 3335 }
3336}
3337
23be331d 3338static void
e315cd28 3339qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
8482e118 3340{
3341 struct fc_rport_identifiers rport_ids;
bdf79621 3342 struct fc_rport *rport;
044d78e1 3343 unsigned long flags;
8482e118 3344
f8b02a85
AV		 3345 rport_ids.node_name = wwn_to_u64(fcport->node_name);
3346 rport_ids.port_name = wwn_to_u64(fcport->port_name);
8482e118 3347 rport_ids.port_id = fcport->d_id.b.domain << 16 |
3348 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
77d74143 3349 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
e315cd28 3350 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
77d74143 3351 if (!rport) {
7c3df132
SK		 3352 ql_log(ql_log_warn, vha, 0x2006,
3353 "Unable to allocate fc remote port.\n");
77d74143
AV		 3354 return;
3355 }
2d70c103
NB		 3356 /*
3357 * Create target mode FC NEXUS in qla_target.c if target mode is
3358 * enabled..
3359 */
ba9f6f64 3360
2d70c103
NB		 3361 qlt_fc_port_added(vha, fcport);
3362
044d78e1 3363 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
19a7b4ae 3364 *((fc_port_t **)rport->dd_data) = fcport;
044d78e1 3365 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
d97994dc 3366
ad3e0eda 3367 rport->supported_classes = fcport->supported_classes;
77d74143 3368
8482e118 3369 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
3370 if (fcport->port_type == FCT_INITIATOR)
3371 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
3372 if (fcport->port_type == FCT_TARGET)
3373 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
77d74143 3374 fc_remote_port_rolechg(rport, rport_ids.roles);
1da177e4
LT		 3375}
3376
23be331d
AB		 3377/*
3378 * qla2x00_update_fcport
3379 * Updates device on list.
3380 *
3381 * Input:
3382 * ha = adapter block pointer.
3383 * fcport = port structure pointer.
3384 *
3385 * Return:
3386 * 0 - Success
3387 * BIT_0 - error
3388 *
3389 * Context:
3390 * Kernel context.
3391 */
3392void
e315cd28 3393qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
23be331d 3394{
e315cd28 3395 fcport->vha = vha;
8ae6d9c7
GM		 3396
3397 if (IS_QLAFX00(vha->hw)) {
3398 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
d20ed91b 3399 goto reg_port;
8ae6d9c7 3400 }
23be331d 3401 fcport->login_retry = 0;
5ff1d584 3402 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
23be331d 3403
1f93da52 3404 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
e315cd28 3405 qla2x00_iidma_fcport(vha, fcport);
21090cbe 3406 qla24xx_update_fcport_fcp_prio(vha, fcport);
d20ed91b
AP		 3407
3408reg_port:
3409 if (qla_ini_mode_enabled(vha))
3410 qla2x00_reg_remote_port(vha, fcport);
3411 else {
3412 /*
3413 * Create target mode FC NEXUS in qla_target.c
3414 */
3415 qlt_fc_port_added(vha, fcport);
3416 }
23be331d
AB		 3417}
3418
1da177e4
LT		 3419/*
3420 * qla2x00_configure_fabric
3421 * Setup SNS devices with loop ID's.
3422 *
3423 * Input:
3424 * ha = adapter block pointer.
3425 *
3426 * Returns:
3427 * 0 = success.
3428 * BIT_0 = error
3429 */
3430static int
e315cd28 3431qla2x00_configure_fabric(scsi_qla_host_t *vha)
1da177e4 3432{
b3b02e6e 3433 int rval;
e452ceb6 3434 fc_port_t *fcport, *fcptemp;
1da177e4
LT		 3435 uint16_t next_loopid;
3436 uint16_t mb[MAILBOX_REGISTER_COUNT];
0107109e 3437 uint16_t loop_id;
1da177e4 3438 LIST_HEAD(new_fcports);
e315cd28
AC		 3439 struct qla_hw_data *ha = vha->hw;
3440 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
df673274 3441 int discovery_gen;
1da177e4
LT		 3442
3443 /* If FL port exists, then SNS is present */
e428924c 3444 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3445 loop_id = NPH_F_PORT;
3446 else
3447 loop_id = SNS_FL_PORT;
e315cd28 3448 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
1da177e4 3449 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3450 ql_dbg(ql_dbg_disc, vha, 0x201f,
3451 "MBX_GET_PORT_NAME failed, No FL Port.\n");
1da177e4 3452
e315cd28 3453 vha->device_flags &= ~SWITCH_FOUND;
1da177e4
LT		 3454 return (QLA_SUCCESS);
3455 }
e315cd28 3456 vha->device_flags |= SWITCH_FOUND;
1da177e4 3457
1da177e4 3458 do {
cca5335c
AV		 3459 /* FDMI support. */
3460 if (ql2xfdmienable &&
e315cd28
AC		 3461 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
3462 qla2x00_fdmi_register(vha);
cca5335c 3463
1da177e4 3464 /* Ensure we are logged into the SNS. */
e428924c 3465 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3466 loop_id = NPH_SNS;
3467 else
3468 loop_id = SIMPLE_NAME_SERVER;
0b91d116
CD		 3469 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
3470 0xfc, mb, BIT_1|BIT_0);
3471 if (rval != QLA_SUCCESS) {
3472 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
e452ceb6 3473 return rval;
0b91d116 3474 }
1da177e4 3475 if (mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 3476 ql_dbg(ql_dbg_disc, vha, 0x2042,
3477 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
3478 "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
3479 mb[2], mb[6], mb[7]);
1da177e4
LT		 3480 return (QLA_SUCCESS);
3481 }
3482
e315cd28
AC		 3483 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
3484 if (qla2x00_rft_id(vha)) {
1da177e4 3485 /* EMPTY */
7c3df132
SK		 3486 ql_dbg(ql_dbg_disc, vha, 0x2045,
3487 "Register FC-4 TYPE failed.\n");
1da177e4 3488 }
e315cd28 3489 if (qla2x00_rff_id(vha)) {
1da177e4 3490 /* EMPTY */
7c3df132
SK		 3491 ql_dbg(ql_dbg_disc, vha, 0x2049,
3492 "Register FC-4 Features failed.\n");
1da177e4 3493 }
e315cd28 3494 if (qla2x00_rnn_id(vha)) {
1da177e4 3495 /* EMPTY */
7c3df132
SK		 3496 ql_dbg(ql_dbg_disc, vha, 0x204f,
3497 "Register Node Name failed.\n");
e315cd28 3498 } else if (qla2x00_rsnn_nn(vha)) {
1da177e4 3499 /* EMPTY */
7c3df132
SK		 3500 ql_dbg(ql_dbg_disc, vha, 0x2053,
3501 "Register Symobilic Node Name failed.\n");
1da177e4
LT		 3502 }
3503 }
3504
827210ba
JC		 3505#define QLA_FCPORT_SCAN 1
3506#define QLA_FCPORT_FOUND 2
3507
3508 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3509 fcport->scan_state = QLA_FCPORT_SCAN;
3510 }
3511
df673274
AP		 3512 /* Mark the time right before querying FW for connected ports.
3513 * This process is long, asynchronous and by the time it's done,
3514 * collected information might not be accurate anymore. E.g.
3515 * disconnected port might have re-connected and a brand new
3516 * session has been created. In this case session's generation
3517 * will be newer than discovery_gen. */
3518 qlt_do_generation_tick(vha, &discovery_gen);
3519
e315cd28 3520 rval = qla2x00_find_all_fabric_devs(vha, &new_fcports);
1da177e4
LT		 3521 if (rval != QLA_SUCCESS)
3522 break;
3523
e452ceb6
JC		 3524 /*
3525 * Logout all previous fabric devices marked lost, except
3526 * FCP2 devices.
3527 */
e315cd28
AC		 3528 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3529 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1da177e4
LT		 3530 break;
3531
3532 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
3533 continue;
3534
b2032fd5
RD		 3535 if (fcport->scan_state == QLA_FCPORT_SCAN) {
3536 if (qla_ini_mode_enabled(base_vha) &&
3537 atomic_read(&fcport->state) == FCS_ONLINE) {
3538 qla2x00_mark_device_lost(vha, fcport,
3539 ql2xplogiabsentdevice, 0);
3540 if (fcport->loop_id != FC_NO_LOOP_ID &&
3541 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
3542 fcport->port_type != FCT_INITIATOR &&
3543 fcport->port_type != FCT_BROADCAST) {
3544 ha->isp_ops->fabric_logout(vha,
3545 fcport->loop_id,
3546 fcport->d_id.b.domain,
3547 fcport->d_id.b.area,
3548 fcport->d_id.b.al_pa);
3549 qla2x00_clear_loop_id(fcport);
3550 }
3551 } else if (!qla_ini_mode_enabled(base_vha)) {
3552 /*
3553 * In target mode, explicitly kill
3554 * sessions and log out of devices
3555 * that are gone, so that we don't
3556 * end up with an initiator using the
3557 * wrong ACL (if the fabric recycles
3558 * an FC address and we have a stale
3559 * session around) and so that we don't
3560 * report initiators that are no longer
3561 * on the fabric.
3562 */
3563 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf077,
3564 "port gone, logging out/killing session: "
3565 "%8phC state 0x%x flags 0x%x fc4_type 0x%x "
3566 "scan_state %d\n",
3567 fcport->port_name,
3568 atomic_read(&fcport->state),
3569 fcport->flags, fcport->fc4_type,
3570 fcport->scan_state);
df673274
AP		 3571 qlt_fc_port_deleted(vha, fcport,
3572 discovery_gen);
1da177e4
LT		 3573 }
3574 }
e452ceb6 3575 }
1da177e4 3576
e452ceb6
JC		 3577 /* Starting free loop ID. */
3578 next_loopid = ha->min_external_loopid;
3579
3580 /*
3581 * Scan through our port list and login entries that need to be
3582 * logged in.
3583 */
3584 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3585 if (atomic_read(&vha->loop_down_timer) ||
3586 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3587 break;
3588
3589 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
3590 (fcport->flags & FCF_LOGIN_NEEDED) == 0)
3591 continue;
3592
b2032fd5
RD		 3593 /*
3594 * If we're not an initiator, skip looking for devices
3595 * and logging in. There's no reason for us to do it,
3596 * and it seems to actively cause problems in target
3597 * mode if we race with the initiator logging into us
3598 * (we might get the "port ID used" status back from
3599 * our login command and log out the initiator, which
3600 * seems to cause havoc).
3601 */
3602 if (!qla_ini_mode_enabled(base_vha)) {
3603 if (fcport->scan_state == QLA_FCPORT_FOUND) {
3604 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf078,
3605 "port %8phC state 0x%x flags 0x%x fc4_type 0x%x "
3606 "scan_state %d (initiator mode disabled; skipping "
3607 "login)\n", fcport->port_name,
3608 atomic_read(&fcport->state),
3609 fcport->flags, fcport->fc4_type,
3610 fcport->scan_state);
3611 }
3612 continue;
3613 }
3614
e452ceb6
JC		 3615 if (fcport->loop_id == FC_NO_LOOP_ID) {
3616 fcport->loop_id = next_loopid;
3617 rval = qla2x00_find_new_loop_id(
3618 base_vha, fcport);
3619 if (rval != QLA_SUCCESS) {
3620 /* Ran out of IDs to use */
3621 break;
1da177e4
LT		 3622 }
3623 }
e452ceb6
JC		 3624 /* Login and update database */
3625 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
3626 }
3627
3628 /* Exit if out of loop IDs. */
3629 if (rval != QLA_SUCCESS) {
3630 break;
3631 }
3632
3633 /*
3634 * Login and add the new devices to our port list.
3635 */
3636 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
3637 if (atomic_read(&vha->loop_down_timer) ||
3638 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3639 break;
3640
b2032fd5
RD		 3641 /*
3642 * If we're not an initiator, skip looking for devices
3643 * and logging in. There's no reason for us to do it,
3644 * and it seems to actively cause problems in target
3645 * mode if we race with the initiator logging into us
3646 * (we might get the "port ID used" status back from
3647 * our login command and log out the initiator, which
3648 * seems to cause havoc).
3649 */
3650 if (qla_ini_mode_enabled(base_vha)) {
3651 /* Find a new loop ID to use. */
3652 fcport->loop_id = next_loopid;
3653 rval = qla2x00_find_new_loop_id(base_vha,
3654 fcport);
3655 if (rval != QLA_SUCCESS) {
3656 /* Ran out of IDs to use */
3657 break;
3658 }
1da177e4 3659
b2032fd5
RD		 3660 /* Login and update database */
3661 qla2x00_fabric_dev_login(vha, fcport,
3662 &next_loopid);
3663 } else {
3664 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf079,
3665 "new port %8phC state 0x%x flags 0x%x fc4_type "
3666 "0x%x scan_state %d (initiator mode disabled; "
3667 "skipping login)\n",
3668 fcport->port_name,
3669 atomic_read(&fcport->state),
3670 fcport->flags, fcport->fc4_type,
3671 fcport->scan_state);
3672 }
e452ceb6
JC		 3673
3674 list_move_tail(&fcport->list, &vha->vp_fcports);
1da177e4
LT		 3675 }
3676 } while (0);
3677
e452ceb6
JC		 3678 /* Free all new device structures not processed. */
3679 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
3680 list_del(&fcport->list);
3681 kfree(fcport);
3682 }
3683
1da177e4 3684 if (rval) {
7c3df132
SK		 3685 ql_dbg(ql_dbg_disc, vha, 0x2068,
3686 "Configure fabric error exit rval=%d.\n", rval);
1da177e4
LT		 3687 }
3688
3689 return (rval);
3690}
3691
1da177e4
LT		 3692/*
3693 * qla2x00_find_all_fabric_devs
3694 *
3695 * Input:
3696 * ha = adapter block pointer.
3697 * dev = database device entry pointer.
3698 *
3699 * Returns:
3700 * 0 = success.
3701 *
3702 * Context:
3703 * Kernel context.
3704 */
3705static int
e315cd28
AC		 3706qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
3707 struct list_head *new_fcports)
1da177e4
LT		 3708{
3709 int rval;
3710 uint16_t loop_id;
3711 fc_port_t *fcport, *new_fcport, *fcptemp;
3712 int found;
3713
3714 sw_info_t *swl;
3715 int swl_idx;
3716 int first_dev, last_dev;
1516ef44 3717 port_id_t wrap = {}, nxt_d_id;
e315cd28 3718 struct qla_hw_data *ha = vha->hw;
bb4cf5b7 3719 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3720
3721 rval = QLA_SUCCESS;
3722
3723 /* Try GID_PT to get device list, else GAN. */
7a67735b 3724 if (!ha->swl)
642ef983 3725 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
7a67735b
AV		 3726 GFP_KERNEL);
3727 swl = ha->swl;
bbfbbbc1 3728 if (!swl) {
1da177e4 3729 /*EMPTY*/
7c3df132
SK		 3730 ql_dbg(ql_dbg_disc, vha, 0x2054,
3731 "GID_PT allocations failed, fallback on GA_NXT.\n");
1da177e4 3732 } else {
642ef983 3733 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
e315cd28 3734 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
1da177e4 3735 swl = NULL;
e315cd28 3736 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3737 swl = NULL;
e315cd28 3738 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3739 swl = NULL;
e5896bd5 3740 } else if (ql2xiidmaenable &&
e315cd28
AC		 3741 qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) {
3742 qla2x00_gpsc(vha, swl);
1da177e4 3743 }
e8c72ba5
CD		 3744
3745 /* If other queries succeeded probe for FC-4 type */
3746 if (swl)
3747 qla2x00_gff_id(vha, swl);
1da177e4
LT		 3748 }
3749 swl_idx = 0;
3750
3751 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 3752 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3753 if (new_fcport == NULL) {
7c3df132
SK		 3754 ql_log(ql_log_warn, vha, 0x205e,
3755 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3756 return (QLA_MEMORY_ALLOC_FAILED);
3757 }
3758 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
1da177e4
LT		 3759 /* Set start port ID scan at adapter ID. */
3760 first_dev = 1;
3761 last_dev = 0;
3762
3763 /* Starting free loop ID. */
e315cd28
AC		 3764 loop_id = ha->min_external_loopid;
3765 for (; loop_id <= ha->max_loop_id; loop_id++) {
3766 if (qla2x00_is_reserved_id(vha, loop_id))
1da177e4
LT		 3767 continue;
3768
3a6478df
GM		 3769 if (ha->current_topology == ISP_CFG_FL &&
3770 (atomic_read(&vha->loop_down_timer) ||
3771 LOOP_TRANSITION(vha))) {
bb2d52b2
AV		 3772 atomic_set(&vha->loop_down_timer, 0);
3773 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
3774 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1da177e4 3775 break;
bb2d52b2 3776 }
1da177e4
LT		 3777
3778 if (swl != NULL) {
3779 if (last_dev) {
3780 wrap.b24 = new_fcport->d_id.b24;
3781 } else {
3782 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
3783 memcpy(new_fcport->node_name,
3784 swl[swl_idx].node_name, WWN_SIZE);
3785 memcpy(new_fcport->port_name,
3786 swl[swl_idx].port_name, WWN_SIZE);
d8b45213
AV		 3787 memcpy(new_fcport->fabric_port_name,
3788 swl[swl_idx].fabric_port_name, WWN_SIZE);
3789 new_fcport->fp_speed = swl[swl_idx].fp_speed;
e8c72ba5 3790 new_fcport->fc4_type = swl[swl_idx].fc4_type;
1da177e4
LT		 3791
3792 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
3793 last_dev = 1;
3794 }
3795 swl_idx++;
3796 }
3797 } else {
3798 /* Send GA_NXT to the switch */
e315cd28 3799 rval = qla2x00_ga_nxt(vha, new_fcport);
1da177e4 3800 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3801 ql_log(ql_log_warn, vha, 0x2064,
3802 "SNS scan failed -- assuming "
3803 "zero-entry result.\n");
1da177e4
LT		 3804 list_for_each_entry_safe(fcport, fcptemp,
3805 new_fcports, list) {
3806 list_del(&fcport->list);
3807 kfree(fcport);
3808 }
3809 rval = QLA_SUCCESS;
3810 break;
3811 }
3812 }
3813
3814 /* If wrap on switch device list, exit. */
3815 if (first_dev) {
3816 wrap.b24 = new_fcport->d_id.b24;
3817 first_dev = 0;
3818 } else if (new_fcport->d_id.b24 == wrap.b24) {
7c3df132
SK		 3819 ql_dbg(ql_dbg_disc, vha, 0x2065,
3820 "Device wrap (%02x%02x%02x).\n",
3821 new_fcport->d_id.b.domain,
3822 new_fcport->d_id.b.area,
3823 new_fcport->d_id.b.al_pa);
1da177e4
LT		 3824 break;
3825 }
3826
2c3dfe3f 3827 /* Bypass if same physical adapter. */
e315cd28 3828 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
1da177e4
LT		 3829 continue;
3830
2c3dfe3f 3831 /* Bypass virtual ports of the same host. */
bb4cf5b7
CD		 3832 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24))
3833 continue;
2c3dfe3f 3834
f7d289f6
AV		 3835 /* Bypass if same domain and area of adapter. */
3836 if (((new_fcport->d_id.b24 & 0xffff00) ==
e315cd28 3837 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
f7d289f6
AV		 3838 ISP_CFG_FL)
3839 continue;
3840
1da177e4
LT		 3841 /* Bypass reserved domain fields. */
3842 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
3843 continue;
3844
e8c72ba5 3845 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
4da26e16
CD		 3846 if (ql2xgffidenable &&
3847 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
3848 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
e8c72ba5
CD		 3849 continue;
3850
1da177e4
LT		 3851 /* Locate matching device in database. */
3852 found = 0;
e315cd28 3853 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3854 if (memcmp(new_fcport->port_name, fcport->port_name,
3855 WWN_SIZE))
3856 continue;
3857
827210ba 3858 fcport->scan_state = QLA_FCPORT_FOUND;
b3b02e6e 3859
1da177e4
LT		 3860 found++;
3861
d8b45213
AV		 3862 /* Update port state. */
3863 memcpy(fcport->fabric_port_name,
3864 new_fcport->fabric_port_name, WWN_SIZE);
3865 fcport->fp_speed = new_fcport->fp_speed;
3866
1da177e4 3867 /*
b2032fd5
RD		 3868 * If address the same and state FCS_ONLINE
3869 * (or in target mode), nothing changed.
1da177e4
LT		 3870 */
3871 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
b2032fd5
RD		 3872 (atomic_read(&fcport->state) == FCS_ONLINE ||
3873 !qla_ini_mode_enabled(base_vha))) {
1da177e4
LT		 3874 break;
3875 }
3876
3877 /*
3878 * If device was not a fabric device before.
3879 */
3880 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3881 fcport->d_id.b24 = new_fcport->d_id.b24;
5f16b331 3882 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3883 fcport->flags |= (FCF_FABRIC_DEVICE |
3884 FCF_LOGIN_NEEDED);
1da177e4
LT		 3885 break;
3886 }
3887
3888 /*
3889 * Port ID changed or device was marked to be updated;
3890 * Log it out if still logged in and mark it for
3891 * relogin later.
3892 */
b2032fd5
RD		 3893 if (!qla_ini_mode_enabled(base_vha)) {
3894 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf080,
3895 "port changed FC ID, %8phC"
3896 " old %x:%x:%x (loop_id 0x%04x)-> new %x:%x:%x\n",
3897 fcport->port_name,
3898 fcport->d_id.b.domain,
3899 fcport->d_id.b.area,
3900 fcport->d_id.b.al_pa,
3901 fcport->loop_id,
3902 new_fcport->d_id.b.domain,
3903 new_fcport->d_id.b.area,
3904 new_fcport->d_id.b.al_pa);
3905 fcport->d_id.b24 = new_fcport->d_id.b24;
3906 break;
3907 }
3908
1da177e4
LT		 3909 fcport->d_id.b24 = new_fcport->d_id.b24;
3910 fcport->flags |= FCF_LOGIN_NEEDED;
3911 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3912 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
0eba25df 3913 (fcport->flags & FCF_ASYNC_SENT) == 0 &&
1da177e4
LT		 3914 fcport->port_type != FCT_INITIATOR &&
3915 fcport->port_type != FCT_BROADCAST) {
e315cd28 3916 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3917 fcport->d_id.b.domain, fcport->d_id.b.area,
3918 fcport->d_id.b.al_pa);
5f16b331 3919 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3920 }
3921
3922 break;
3923 }
3924
3925 if (found)
3926 continue;
1da177e4 3927 /* If device was not in our fcports list, then add it. */
b2032fd5 3928 new_fcport->scan_state = QLA_FCPORT_FOUND;
1da177e4
LT		 3929 list_add_tail(&new_fcport->list, new_fcports);
3930
3931 /* Allocate a new replacement fcport. */
3932 nxt_d_id.b24 = new_fcport->d_id.b24;
e315cd28 3933 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3934 if (new_fcport == NULL) {
7c3df132
SK		 3935 ql_log(ql_log_warn, vha, 0x2066,
3936 "Memory allocation failed for fcport.\n");
1da177e4
LT		 3937 return (QLA_MEMORY_ALLOC_FAILED);
3938 }
3939 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
3940 new_fcport->d_id.b24 = nxt_d_id.b24;
3941 }
3942
c9475cb0 3943 kfree(new_fcport);
1da177e4 3944
1da177e4
LT		 3945 return (rval);
3946}
3947
3948/*
3949 * qla2x00_find_new_loop_id
3950 * Scan through our port list and find a new usable loop ID.
3951 *
3952 * Input:
3953 * ha: adapter state pointer.
3954 * dev: port structure pointer.
3955 *
3956 * Returns:
3957 * qla2x00 local function return status code.
3958 *
3959 * Context:
3960 * Kernel context.
3961 */
03bcfb57 3962int
e315cd28 3963qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
1da177e4
LT		 3964{
3965 int rval;
e315cd28 3966 struct qla_hw_data *ha = vha->hw;
feafb7b1 3967 unsigned long flags = 0;
1da177e4
LT		 3968
3969 rval = QLA_SUCCESS;
3970
5f16b331 3971 spin_lock_irqsave(&ha->vport_slock, flags);
1da177e4 3972
5f16b331
CD		 3973 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
3974 LOOPID_MAP_SIZE);
3975 if (dev->loop_id >= LOOPID_MAP_SIZE ||
3976 qla2x00_is_reserved_id(vha, dev->loop_id)) {
3977 dev->loop_id = FC_NO_LOOP_ID;
3978 rval = QLA_FUNCTION_FAILED;
3979 } else
3980 set_bit(dev->loop_id, ha->loop_id_map);
1da177e4 3981
5f16b331 3982 spin_unlock_irqrestore(&ha->vport_slock, flags);
1da177e4 3983
5f16b331
CD		 3984 if (rval == QLA_SUCCESS)
3985 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
3986 "Assigning new loopid=%x, portid=%x.\n",
3987 dev->loop_id, dev->d_id.b24);
3988 else
3989 ql_log(ql_log_warn, dev->vha, 0x2087,
3990 "No loop_id's available, portid=%x.\n",
3991 dev->d_id.b24);
1da177e4
LT		 3992
3993 return (rval);
3994}
3995
1da177e4
LT		 3996/*
3997 * qla2x00_fabric_dev_login
3998 * Login fabric target device and update FC port database.
3999 *
4000 * Input:
4001 * ha: adapter state pointer.
4002 * fcport: port structure list pointer.
4003 * next_loopid: contains value of a new loop ID that can be used
4004 * by the next login attempt.
4005 *
4006 * Returns:
4007 * qla2x00 local function return status code.
4008 *
4009 * Context:
4010 * Kernel context.
4011 */
4012static int
e315cd28 4013qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 4014 uint16_t *next_loopid)
4015{
4016 int rval;
0107109e 4017 uint8_t opts;
e315cd28 4018 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 4019
4020 rval = QLA_SUCCESS;
1da177e4 4021
ac280b67 4022 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584
AV		 4023 if (fcport->flags & FCF_ASYNC_SENT)
4024 return rval;
4025 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 4026 rval = qla2x00_post_async_login_work(vha, fcport, NULL);
4027 if (!rval)
4028 return rval;
4029 }
4030
5ff1d584 4031 fcport->flags &= ~FCF_ASYNC_SENT;
e315cd28 4032 rval = qla2x00_fabric_login(vha, fcport, next_loopid);
1da177e4 4033 if (rval == QLA_SUCCESS) {
f08b7251 4034 /* Send an ADISC to FCP2 devices.*/
0107109e 4035 opts = 0;
f08b7251 4036 if (fcport->flags & FCF_FCP2_DEVICE)
0107109e 4037 opts |= BIT_1;
e315cd28 4038 rval = qla2x00_get_port_database(vha, fcport, opts);
1da177e4 4039 if (rval != QLA_SUCCESS) {
e315cd28 4040 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 4041 fcport->d_id.b.domain, fcport->d_id.b.area,
4042 fcport->d_id.b.al_pa);
e315cd28 4043 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4 4044 } else {
e315cd28 4045 qla2x00_update_fcport(vha, fcport);
1da177e4 4046 }
0b91d116
CD		 4047 } else {
4048 /* Retry Login. */
4049 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 4050 }
4051
4052 return (rval);
4053}
4054
4055/*
4056 * qla2x00_fabric_login
4057 * Issue fabric login command.
4058 *
4059 * Input:
4060 * ha = adapter block pointer.
4061 * device = pointer to FC device type structure.
4062 *
4063 * Returns:
4064 * 0 - Login successfully
4065 * 1 - Login failed
4066 * 2 - Initiator device
4067 * 3 - Fatal error
4068 */
4069int
e315cd28 4070qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 4071 uint16_t *next_loopid)
4072{
4073 int rval;
4074 int retry;
4075 uint16_t tmp_loopid;
4076 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 4077 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 4078
4079 retry = 0;
4080 tmp_loopid = 0;
4081
4082 for (;;) {
7c3df132
SK		 4083 ql_dbg(ql_dbg_disc, vha, 0x2000,
4084 "Trying Fabric Login w/loop id 0x%04x for port "
4085 "%02x%02x%02x.\n",
4086 fcport->loop_id, fcport->d_id.b.domain,
4087 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 4088
4089 /* Login fcport on switch. */
0b91d116 4090 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
1da177e4
LT		 4091 fcport->d_id.b.domain, fcport->d_id.b.area,
4092 fcport->d_id.b.al_pa, mb, BIT_0);
0b91d116
CD		 4093 if (rval != QLA_SUCCESS) {
4094 return rval;
4095 }
1da177e4
LT		 4096 if (mb[0] == MBS_PORT_ID_USED) {
4097 /*
4098 * Device has another loop ID. The firmware team
0107109e
AV		 4099 * recommends the driver perform an implicit login with
4100 * the specified ID again. The ID we just used is save
4101 * here so we return with an ID that can be tried by
4102 * the next login.
1da177e4
LT		 4103 */
4104 retry++;
4105 tmp_loopid = fcport->loop_id;
4106 fcport->loop_id = mb[1];
4107
7c3df132
SK		 4108 ql_dbg(ql_dbg_disc, vha, 0x2001,
4109 "Fabric Login: port in use - next loop "
4110 "id=0x%04x, port id= %02x%02x%02x.\n",
1da177e4 4111 fcport->loop_id, fcport->d_id.b.domain,
7c3df132 4112 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 4113
4114 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
4115 /*
4116 * Login succeeded.
4117 */
4118 if (retry) {
4119 /* A retry occurred before. */
4120 *next_loopid = tmp_loopid;
4121 } else {
4122 /*
4123 * No retry occurred before. Just increment the
4124 * ID value for next login.
4125 */
4126 *next_loopid = (fcport->loop_id + 1);
4127 }
4128
4129 if (mb[1] & BIT_0) {
4130 fcport->port_type = FCT_INITIATOR;
4131 } else {
4132 fcport->port_type = FCT_TARGET;
4133 if (mb[1] & BIT_1) {
8474f3a0 4134 fcport->flags |= FCF_FCP2_DEVICE;
1da177e4
LT		 4135 }
4136 }
4137
ad3e0eda
AV		 4138 if (mb[10] & BIT_0)
4139 fcport->supported_classes |= FC_COS_CLASS2;
4140 if (mb[10] & BIT_1)
4141 fcport->supported_classes |= FC_COS_CLASS3;
4142
2d70c103
NB		 4143 if (IS_FWI2_CAPABLE(ha)) {
4144 if (mb[10] & BIT_7)
4145 fcport->flags |=
4146 FCF_CONF_COMP_SUPPORTED;
4147 }
4148
1da177e4
LT		 4149 rval = QLA_SUCCESS;
4150 break;
4151 } else if (mb[0] == MBS_LOOP_ID_USED) {
4152 /*
4153 * Loop ID already used, try next loop ID.
4154 */
4155 fcport->loop_id++;
e315cd28 4156 rval = qla2x00_find_new_loop_id(vha, fcport);
1da177e4
LT		 4157 if (rval != QLA_SUCCESS) {
4158 /* Ran out of loop IDs to use */
4159 break;
4160 }
4161 } else if (mb[0] == MBS_COMMAND_ERROR) {
4162 /*
4163 * Firmware possibly timed out during login. If NO
4164 * retries are left to do then the device is declared
4165 * dead.
4166 */
4167 *next_loopid = fcport->loop_id;
e315cd28 4168 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 4169 fcport->d_id.b.domain, fcport->d_id.b.area,
4170 fcport->d_id.b.al_pa);
e315cd28 4171 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 4172
4173 rval = 1;
4174 break;
4175 } else {
4176 /*
4177 * unrecoverable / not handled error
4178 */
7c3df132
SK		 4179 ql_dbg(ql_dbg_disc, vha, 0x2002,
4180 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
4181 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
4182 fcport->d_id.b.area, fcport->d_id.b.al_pa,
4183 fcport->loop_id, jiffies);
1da177e4
LT		 4184
4185 *next_loopid = fcport->loop_id;
e315cd28 4186 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 4187 fcport->d_id.b.domain, fcport->d_id.b.area,
4188 fcport->d_id.b.al_pa);
5f16b331 4189 qla2x00_clear_loop_id(fcport);
0eedfcf0 4190 fcport->login_retry = 0;
1da177e4
LT		 4191
4192 rval = 3;
4193 break;
4194 }
4195 }
4196
4197 return (rval);
4198}
4199
4200/*
4201 * qla2x00_local_device_login
4202 * Issue local device login command.
4203 *
4204 * Input:
4205 * ha = adapter block pointer.
4206 * loop_id = loop id of device to login to.
4207 *
4208 * Returns (Where's the #define!!!!):
4209 * 0 - Login successfully
4210 * 1 - Login failed
4211 * 3 - Fatal error
4212 */
4213int
e315cd28 4214qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
1da177e4
LT		 4215{
4216 int rval;
4217 uint16_t mb[MAILBOX_REGISTER_COUNT];
4218
4219 memset(mb, 0, sizeof(mb));
e315cd28 4220 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
1da177e4
LT		 4221 if (rval == QLA_SUCCESS) {
4222 /* Interrogate mailbox registers for any errors */
4223 if (mb[0] == MBS_COMMAND_ERROR)
4224 rval = 1;
4225 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
4226 /* device not in PCB table */
4227 rval = 3;
4228 }
4229
4230 return (rval);
4231}
4232
4233/*
4234 * qla2x00_loop_resync
4235 * Resync with fibre channel devices.
4236 *
4237 * Input:
4238 * ha = adapter block pointer.
4239 *
4240 * Returns:
4241 * 0 = success
4242 */
4243int
e315cd28 4244qla2x00_loop_resync(scsi_qla_host_t *vha)
1da177e4 4245{
73208dfd 4246 int rval = QLA_SUCCESS;
1da177e4 4247 uint32_t wait_time;
67c2e93a
AC		 4248 struct req_que *req;
4249 struct rsp_que *rsp;
4250
7163ea81 4251 if (vha->hw->flags.cpu_affinity_enabled)
67c2e93a
AC		 4252 req = vha->hw->req_q_map[0];
4253 else
4254 req = vha->req;
4255 rsp = req->rsp;
1da177e4 4256
e315cd28
AC		 4257 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4258 if (vha->flags.online) {
4259 if (!(rval = qla2x00_fw_ready(vha))) {
1da177e4
LT		 4260 /* Wait at most MAX_TARGET RSCNs for a stable link. */
4261 wait_time = 256;
4262 do {
8ae6d9c7
GM		 4263 if (!IS_QLAFX00(vha->hw)) {
4264 /*
4265 * Issue a marker after FW becomes
4266 * ready.
4267 */
4268 qla2x00_marker(vha, req, rsp, 0, 0,
4269 MK_SYNC_ALL);
4270 vha->marker_needed = 0;
4271 }
1da177e4
LT		 4272
4273 /* Remap devices on Loop. */
e315cd28 4274 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4 4275
8ae6d9c7
GM		 4276 if (IS_QLAFX00(vha->hw))
4277 qlafx00_configure_devices(vha);
4278 else
4279 qla2x00_configure_loop(vha);
4280
1da177e4 4281 wait_time--;
e315cd28
AC		 4282 } while (!atomic_read(&vha->loop_down_timer) &&
4283 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
4284 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
4285 &vha->dpc_flags)));
1da177e4 4286 }
1da177e4
LT		 4287 }
4288
e315cd28 4289 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
1da177e4 4290 return (QLA_FUNCTION_FAILED);
1da177e4 4291
e315cd28 4292 if (rval)
7c3df132
SK		 4293 ql_dbg(ql_dbg_disc, vha, 0x206c,
4294 "%s *** FAILED ***.\n", __func__);
1da177e4
LT		 4295
4296 return (rval);
4297}
4298
579d12b5
SK		 4299/*
4300* qla2x00_perform_loop_resync
4301* Description: This function will set the appropriate flags and call
4302* qla2x00_loop_resync. If successful loop will be resynced
4303* Arguments : scsi_qla_host_t pointer
4304* returm : Success or Failure
4305*/
4306
4307int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
4308{
4309 int32_t rval = 0;
4310
4311 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
4312 /*Configure the flags so that resync happens properly*/
4313 atomic_set(&ha->loop_down_timer, 0);
4314 if (!(ha->device_flags & DFLG_NO_CABLE)) {
4315 atomic_set(&ha->loop_state, LOOP_UP);
4316 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
4317 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
4318 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
4319
4320 rval = qla2x00_loop_resync(ha);
4321 } else
4322 atomic_set(&ha->loop_state, LOOP_DEAD);
4323
4324 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
4325 }
4326
4327 return rval;
4328}
4329
d97994dc 4330void
67becc00 4331qla2x00_update_fcports(scsi_qla_host_t *base_vha)
d97994dc 4332{
4333 fc_port_t *fcport;
feafb7b1
AE		 4334 struct scsi_qla_host *vha;
4335 struct qla_hw_data *ha = base_vha->hw;
4336 unsigned long flags;
d97994dc 4337
feafb7b1 4338 spin_lock_irqsave(&ha->vport_slock, flags);
d97994dc 4339 /* Go with deferred removal of rport references. */
feafb7b1
AE		 4340 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
4341 atomic_inc(&vha->vref_count);
4342 list_for_each_entry(fcport, &vha->vp_fcports, list) {
8ae598d0 4343 if (fcport->drport &&
feafb7b1
AE		 4344 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
4345 spin_unlock_irqrestore(&ha->vport_slock, flags);
67becc00 4346 qla2x00_rport_del(fcport);
df673274
AP		 4347
4348 /*
4349 * Release the target mode FC NEXUS in
4350 * qla_target.c, if target mod is enabled.
4351 */
4352 qlt_fc_port_deleted(vha, fcport,
4353 base_vha->total_fcport_update_gen);
4354
feafb7b1
AE		 4355 spin_lock_irqsave(&ha->vport_slock, flags);
4356 }
4357 }
4358 atomic_dec(&vha->vref_count);
4359 }
4360 spin_unlock_irqrestore(&ha->vport_slock, flags);
d97994dc 4361}
4362
7d613ac6
SV		 4363/* Assumes idc_lock always held on entry */
4364void
4365qla83xx_reset_ownership(scsi_qla_host_t *vha)
4366{
4367 struct qla_hw_data *ha = vha->hw;
4368 uint32_t drv_presence, drv_presence_mask;
4369 uint32_t dev_part_info1, dev_part_info2, class_type;
4370 uint32_t class_type_mask = 0x3;
4371 uint16_t fcoe_other_function = 0xffff, i;
4372
7ec0effd
AD		 4373 if (IS_QLA8044(ha)) {
4374 drv_presence = qla8044_rd_direct(vha,
4375 QLA8044_CRB_DRV_ACTIVE_INDEX);
4376 dev_part_info1 = qla8044_rd_direct(vha,
4377 QLA8044_CRB_DEV_PART_INFO_INDEX);
4378 dev_part_info2 = qla8044_rd_direct(vha,
4379 QLA8044_CRB_DEV_PART_INFO2);
4380 } else {
4381 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4382 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
4383 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
4384 }
7d613ac6
SV		 4385 for (i = 0; i < 8; i++) {
4386 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
4387 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
4388 (i != ha->portnum)) {
4389 fcoe_other_function = i;
4390 break;
4391 }
4392 }
4393 if (fcoe_other_function == 0xffff) {
4394 for (i = 0; i < 8; i++) {
4395 class_type = ((dev_part_info2 >> (i * 4)) &
4396 class_type_mask);
4397 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
4398 ((i + 8) != ha->portnum)) {
4399 fcoe_other_function = i + 8;
4400 break;
4401 }
4402 }
4403 }
4404 /*
4405 * Prepare drv-presence mask based on fcoe functions present.
4406 * However consider only valid physical fcoe function numbers (0-15).
4407 */
4408 drv_presence_mask = ~((1 << (ha->portnum)) |
4409 ((fcoe_other_function == 0xffff) ?
4410 0 : (1 << (fcoe_other_function))));
4411
4412 /* We are the reset owner iff:
4413 * - No other protocol drivers present.
4414 * - This is the lowest among fcoe functions. */
4415 if (!(drv_presence & drv_presence_mask) &&
4416 (ha->portnum < fcoe_other_function)) {
4417 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
4418 "This host is Reset owner.\n");
4419 ha->flags.nic_core_reset_owner = 1;
4420 }
4421}
4422
fa492630 4423static int
7d613ac6
SV		 4424__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
4425{
4426 int rval = QLA_SUCCESS;
4427 struct qla_hw_data *ha = vha->hw;
4428 uint32_t drv_ack;
4429
4430 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4431 if (rval == QLA_SUCCESS) {
4432 drv_ack |= (1 << ha->portnum);
4433 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4434 }
4435
4436 return rval;
4437}
4438
fa492630 4439static int
7d613ac6
SV		 4440__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
4441{
4442 int rval = QLA_SUCCESS;
4443 struct qla_hw_data *ha = vha->hw;
4444 uint32_t drv_ack;
4445
4446 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4447 if (rval == QLA_SUCCESS) {
4448 drv_ack &= ~(1 << ha->portnum);
4449 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4450 }
4451
4452 return rval;
4453}
4454
fa492630 4455static const char *
7d613ac6
SV		 4456qla83xx_dev_state_to_string(uint32_t dev_state)
4457{
4458 switch (dev_state) {
4459 case QLA8XXX_DEV_COLD:
4460 return "COLD/RE-INIT";
4461 case QLA8XXX_DEV_INITIALIZING:
4462 return "INITIALIZING";
4463 case QLA8XXX_DEV_READY:
4464 return "READY";
4465 case QLA8XXX_DEV_NEED_RESET:
4466 return "NEED RESET";
4467 case QLA8XXX_DEV_NEED_QUIESCENT:
4468 return "NEED QUIESCENT";
4469 case QLA8XXX_DEV_FAILED:
4470 return "FAILED";
4471 case QLA8XXX_DEV_QUIESCENT:
4472 return "QUIESCENT";
4473 default:
4474 return "Unknown";
4475 }
4476}
4477
4478/* Assumes idc-lock always held on entry */
4479void
4480qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
4481{
4482 struct qla_hw_data *ha = vha->hw;
4483 uint32_t idc_audit_reg = 0, duration_secs = 0;
4484
4485 switch (audit_type) {
4486 case IDC_AUDIT_TIMESTAMP:
4487 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
4488 idc_audit_reg = (ha->portnum) |
4489 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
4490 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4491 break;
4492
4493 case IDC_AUDIT_COMPLETION:
4494 duration_secs = ((jiffies_to_msecs(jiffies) -
4495 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
4496 idc_audit_reg = (ha->portnum) |
4497 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
4498 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4499 break;
4500
4501 default:
4502 ql_log(ql_log_warn, vha, 0xb078,
4503 "Invalid audit type specified.\n");
4504 break;
4505 }
4506}
4507
4508/* Assumes idc_lock always held on entry */
fa492630 4509static int
7d613ac6
SV		 4510qla83xx_initiating_reset(scsi_qla_host_t *vha)
4511{
4512 struct qla_hw_data *ha = vha->hw;
4513 uint32_t idc_control, dev_state;
4514
4515 __qla83xx_get_idc_control(vha, &idc_control);
4516 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
4517 ql_log(ql_log_info, vha, 0xb080,
4518 "NIC Core reset has been disabled. idc-control=0x%x\n",
4519 idc_control);
4520 return QLA_FUNCTION_FAILED;
4521 }
4522
4523 /* Set NEED-RESET iff in READY state and we are the reset-owner */
4524 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4525 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
4526 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
4527 QLA8XXX_DEV_NEED_RESET);
4528 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
4529 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
4530 } else {
4531 const char *state = qla83xx_dev_state_to_string(dev_state);
4532 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
4533
4534 /* SV: XXX: Is timeout required here? */
4535 /* Wait for IDC state change READY -> NEED_RESET */
4536 while (dev_state == QLA8XXX_DEV_READY) {
4537 qla83xx_idc_unlock(vha, 0);
4538 msleep(200);
4539 qla83xx_idc_lock(vha, 0);
4540 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4541 }
4542 }
4543
4544 /* Send IDC ack by writing to drv-ack register */
4545 __qla83xx_set_drv_ack(vha);
4546
4547 return QLA_SUCCESS;
4548}
4549
4550int
4551__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
4552{
4553 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4554}
4555
7d613ac6
SV		 4556int
4557__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
4558{
4559 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4560}
4561
fa492630 4562static int
7d613ac6
SV		 4563qla83xx_check_driver_presence(scsi_qla_host_t *vha)
4564{
4565 uint32_t drv_presence = 0;
4566 struct qla_hw_data *ha = vha->hw;
4567
4568 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4569 if (drv_presence & (1 << ha->portnum))
4570 return QLA_SUCCESS;
4571 else
4572 return QLA_TEST_FAILED;
4573}
4574
4575int
4576qla83xx_nic_core_reset(scsi_qla_host_t *vha)
4577{
4578 int rval = QLA_SUCCESS;
4579 struct qla_hw_data *ha = vha->hw;
4580
4581 ql_dbg(ql_dbg_p3p, vha, 0xb058,
4582 "Entered %s().\n", __func__);
4583
4584 if (vha->device_flags & DFLG_DEV_FAILED) {
4585 ql_log(ql_log_warn, vha, 0xb059,
4586 "Device in unrecoverable FAILED state.\n");
4587 return QLA_FUNCTION_FAILED;
4588 }
4589
4590 qla83xx_idc_lock(vha, 0);
4591
4592 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
4593 ql_log(ql_log_warn, vha, 0xb05a,
4594 "Function=0x%x has been removed from IDC participation.\n",
4595 ha->portnum);
4596 rval = QLA_FUNCTION_FAILED;
4597 goto exit;
4598 }
4599
4600 qla83xx_reset_ownership(vha);
4601
4602 rval = qla83xx_initiating_reset(vha);
4603
4604 /*
4605 * Perform reset if we are the reset-owner,
4606 * else wait till IDC state changes to READY/FAILED.
4607 */
4608 if (rval == QLA_SUCCESS) {
4609 rval = qla83xx_idc_state_handler(vha);
4610
4611 if (rval == QLA_SUCCESS)
4612 ha->flags.nic_core_hung = 0;
4613 __qla83xx_clear_drv_ack(vha);
4614 }
4615
4616exit:
4617 qla83xx_idc_unlock(vha, 0);
4618
4619 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
4620
4621 return rval;
4622}
4623
81178772
SK		 4624int
4625qla2xxx_mctp_dump(scsi_qla_host_t *vha)
4626{
4627 struct qla_hw_data *ha = vha->hw;
4628 int rval = QLA_FUNCTION_FAILED;
4629
4630 if (!IS_MCTP_CAPABLE(ha)) {
4631 /* This message can be removed from the final version */
4632 ql_log(ql_log_info, vha, 0x506d,
4633 "This board is not MCTP capable\n");
4634 return rval;
4635 }
4636
4637 if (!ha->mctp_dump) {
4638 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
4639 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
4640
4641 if (!ha->mctp_dump) {
4642 ql_log(ql_log_warn, vha, 0x506e,
4643 "Failed to allocate memory for mctp dump\n");
4644 return rval;
4645 }
4646 }
4647
4648#define MCTP_DUMP_STR_ADDR 0x00000000
4649 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
4650 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
4651 if (rval != QLA_SUCCESS) {
4652 ql_log(ql_log_warn, vha, 0x506f,
4653 "Failed to capture mctp dump\n");
4654 } else {
4655 ql_log(ql_log_info, vha, 0x5070,
4656 "Mctp dump capture for host (%ld/%p).\n",
4657 vha->host_no, ha->mctp_dump);
4658 ha->mctp_dumped = 1;
4659 }
4660
409ee0fe 4661 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
81178772
SK		 4662 ha->flags.nic_core_reset_hdlr_active = 1;
4663 rval = qla83xx_restart_nic_firmware(vha);
4664 if (rval)
4665 /* NIC Core reset failed. */
4666 ql_log(ql_log_warn, vha, 0x5071,
4667 "Failed to restart nic firmware\n");
4668 else
4669 ql_dbg(ql_dbg_p3p, vha, 0xb084,
4670 "Restarted NIC firmware successfully.\n");
4671 ha->flags.nic_core_reset_hdlr_active = 0;
4672 }
4673
4674 return rval;
4675
4676}
4677
579d12b5 4678/*
8fcd6b8b 4679* qla2x00_quiesce_io
579d12b5
SK		 4680* Description: This function will block the new I/Os
4681* Its not aborting any I/Os as context
4682* is not destroyed during quiescence
4683* Arguments: scsi_qla_host_t
4684* return : void
4685*/
4686void
8fcd6b8b 4687qla2x00_quiesce_io(scsi_qla_host_t *vha)
579d12b5
SK		 4688{
4689 struct qla_hw_data *ha = vha->hw;
4690 struct scsi_qla_host *vp;
4691
8fcd6b8b
CD		 4692 ql_dbg(ql_dbg_dpc, vha, 0x401d,
4693 "Quiescing I/O - ha=%p.\n", ha);
579d12b5
SK		 4694
4695 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
4696 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4697 atomic_set(&vha->loop_state, LOOP_DOWN);
4698 qla2x00_mark_all_devices_lost(vha, 0);
4699 list_for_each_entry(vp, &ha->vp_list, list)
8fcd6b8b 4700 qla2x00_mark_all_devices_lost(vp, 0);
579d12b5
SK		 4701 } else {
4702 if (!atomic_read(&vha->loop_down_timer))
4703 atomic_set(&vha->loop_down_timer,
4704 LOOP_DOWN_TIME);
4705 }
4706 /* Wait for pending cmds to complete */
4707 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
4708}
4709
a9083016
GM		 4710void
4711qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
4712{
4713 struct qla_hw_data *ha = vha->hw;
579d12b5 4714 struct scsi_qla_host *vp;
feafb7b1 4715 unsigned long flags;
6aef87be 4716 fc_port_t *fcport;
a9083016 4717
e46ef004
SK		 4718 /* For ISP82XX, driver waits for completion of the commands.
4719 * online flag should be set.
4720 */
7ec0effd 4721 if (!(IS_P3P_TYPE(ha)))
e46ef004 4722 vha->flags.online = 0;
a9083016
GM		 4723 ha->flags.chip_reset_done = 0;
4724 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2be21fa2 4725 vha->qla_stats.total_isp_aborts++;
a9083016 4726
7c3df132
SK		 4727 ql_log(ql_log_info, vha, 0x00af,
4728 "Performing ISP error recovery - ha=%p.\n", ha);
a9083016 4729
e46ef004
SK		 4730 /* For ISP82XX, reset_chip is just disabling interrupts.
4731 * Driver waits for the completion of the commands.
4732 * the interrupts need to be enabled.
4733 */
7ec0effd 4734 if (!(IS_P3P_TYPE(ha)))
a9083016
GM		 4735 ha->isp_ops->reset_chip(vha);
4736
4737 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
4738 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4739 atomic_set(&vha->loop_state, LOOP_DOWN);
4740 qla2x00_mark_all_devices_lost(vha, 0);
feafb7b1
AE		 4741
4742 spin_lock_irqsave(&ha->vport_slock, flags);
579d12b5 4743 list_for_each_entry(vp, &ha->vp_list, list) {
feafb7b1
AE		 4744 atomic_inc(&vp->vref_count);
4745 spin_unlock_irqrestore(&ha->vport_slock, flags);
4746
a9083016 4747 qla2x00_mark_all_devices_lost(vp, 0);
feafb7b1
AE		 4748
4749 spin_lock_irqsave(&ha->vport_slock, flags);
4750 atomic_dec(&vp->vref_count);
4751 }
4752 spin_unlock_irqrestore(&ha->vport_slock, flags);
a9083016
GM		 4753 } else {
4754 if (!atomic_read(&vha->loop_down_timer))
4755 atomic_set(&vha->loop_down_timer,
4756 LOOP_DOWN_TIME);
4757 }
4758
6aef87be
AV		 4759 /* Clear all async request states across all VPs. */
4760 list_for_each_entry(fcport, &vha->vp_fcports, list)
4761 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4762 spin_lock_irqsave(&ha->vport_slock, flags);
4763 list_for_each_entry(vp, &ha->vp_list, list) {
4764 atomic_inc(&vp->vref_count);
4765 spin_unlock_irqrestore(&ha->vport_slock, flags);
4766
4767 list_for_each_entry(fcport, &vp->vp_fcports, list)
4768 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4769
4770 spin_lock_irqsave(&ha->vport_slock, flags);
4771 atomic_dec(&vp->vref_count);
4772 }
4773 spin_unlock_irqrestore(&ha->vport_slock, flags);
4774
bddd2d65
LC		 4775 if (!ha->flags.eeh_busy) {
4776 /* Make sure for ISP 82XX IO DMA is complete */
7ec0effd 4777 if (IS_P3P_TYPE(ha)) {
7190575f 4778 qla82xx_chip_reset_cleanup(vha);
7c3df132
SK		 4779 ql_log(ql_log_info, vha, 0x00b4,
4780 "Done chip reset cleanup.\n");
a9083016 4781
e46ef004
SK		 4782 /* Done waiting for pending commands.
4783 * Reset the online flag.
4784 */
4785 vha->flags.online = 0;
4d78c973 4786 }
a9083016 4787
bddd2d65
LC		 4788 /* Requeue all commands in outstanding command list. */
4789 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
4790 }
b6a029e1
AE		 4791
4792 ha->chip_reset++;
4793 /* memory barrier */
4794 wmb();
a9083016
GM		 4795}
4796
1da177e4
LT		 4797/*
4798* qla2x00_abort_isp
4799* Resets ISP and aborts all outstanding commands.
4800*
4801* Input:
4802* ha = adapter block pointer.
4803*
4804* Returns:
4805* 0 = success
4806*/
4807int
e315cd28 4808qla2x00_abort_isp(scsi_qla_host_t *vha)
1da177e4 4809{
476e8978 4810 int rval;
1da177e4 4811 uint8_t status = 0;
e315cd28
AC		 4812 struct qla_hw_data *ha = vha->hw;
4813 struct scsi_qla_host *vp;
73208dfd 4814 struct req_que *req = ha->req_q_map[0];
feafb7b1 4815 unsigned long flags;
1da177e4 4816
e315cd28 4817 if (vha->flags.online) {
a9083016 4818 qla2x00_abort_isp_cleanup(vha);
1da177e4 4819
a6171297
SV		 4820 if (IS_QLA8031(ha)) {
4821 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
4822 "Clearing fcoe driver presence.\n");
4823 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
4824 ql_dbg(ql_dbg_p3p, vha, 0xb073,
4825 "Error while clearing DRV-Presence.\n");
4826 }
4827
85880801
AV		 4828 if (unlikely(pci_channel_offline(ha->pdev) &&
4829 ha->flags.pci_channel_io_perm_failure)) {
4830 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4831 status = 0;
4832 return status;
4833 }
4834
73208dfd 4835 ha->isp_ops->get_flash_version(vha, req->ring);
30c47662 4836
e315cd28 4837 ha->isp_ops->nvram_config(vha);
1da177e4 4838
e315cd28
AC		 4839 if (!qla2x00_restart_isp(vha)) {
4840 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4 4841
e315cd28 4842 if (!atomic_read(&vha->loop_down_timer)) {
1da177e4
LT		 4843 /*
4844 * Issue marker command only when we are going
4845 * to start the I/O .
4846 */
e315cd28 4847 vha->marker_needed = 1;
1da177e4
LT		 4848 }
4849
e315cd28 4850 vha->flags.online = 1;
1da177e4 4851
fd34f556 4852 ha->isp_ops->enable_intrs(ha);
1da177e4 4853
fa2a1ce5 4854 ha->isp_abort_cnt = 0;
e315cd28 4855 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
476e8978 4856
6246b8a1
GM		 4857 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
4858 qla2x00_get_fw_version(vha);
df613b96
AV		 4859 if (ha->fce) {
4860 ha->flags.fce_enabled = 1;
4861 memset(ha->fce, 0,
4862 fce_calc_size(ha->fce_bufs));
e315cd28 4863 rval = qla2x00_enable_fce_trace(vha,
df613b96
AV		 4864 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
4865 &ha->fce_bufs);
4866 if (rval) {
7c3df132 4867 ql_log(ql_log_warn, vha, 0x8033,
df613b96
AV		 4868 "Unable to reinitialize FCE "
4869 "(%d).\n", rval);
4870 ha->flags.fce_enabled = 0;
4871 }
4872 }
436a7b11
AV		 4873
4874 if (ha->eft) {
4875 memset(ha->eft, 0, EFT_SIZE);
e315cd28 4876 rval = qla2x00_enable_eft_trace(vha,
436a7b11
AV		 4877 ha->eft_dma, EFT_NUM_BUFFERS);
4878 if (rval) {
7c3df132 4879 ql_log(ql_log_warn, vha, 0x8034,
436a7b11
AV		 4880 "Unable to reinitialize EFT "
4881 "(%d).\n", rval);
4882 }
4883 }
1da177e4 4884 } else { /* failed the ISP abort */
e315cd28
AC		 4885 vha->flags.online = 1;
4886 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
1da177e4 4887 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 4888 ql_log(ql_log_fatal, vha, 0x8035,
4889 "ISP error recover failed - "
4890 "board disabled.\n");
fa2a1ce5 4891 /*
1da177e4
LT		 4892 * The next call disables the board
4893 * completely.
4894 */
e315cd28
AC		 4895 ha->isp_ops->reset_adapter(vha);
4896 vha->flags.online = 0;
1da177e4 4897 clear_bit(ISP_ABORT_RETRY,
e315cd28 4898 &vha->dpc_flags);
1da177e4
LT		 4899 status = 0;
4900 } else { /* schedule another ISP abort */
4901 ha->isp_abort_cnt--;
7c3df132
SK		 4902 ql_dbg(ql_dbg_taskm, vha, 0x8020,
4903 "ISP abort - retry remaining %d.\n",
4904 ha->isp_abort_cnt);
1da177e4
LT		 4905 status = 1;
4906 }
4907 } else {
4908 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 4909 ql_dbg(ql_dbg_taskm, vha, 0x8021,
4910 "ISP error recovery - retrying (%d) "
4911 "more times.\n", ha->isp_abort_cnt);
e315cd28 4912 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1da177e4
LT		 4913 status = 1;
4914 }
4915 }
fa2a1ce5 4916
1da177e4
LT		 4917 }
4918
e315cd28 4919 if (!status) {
7c3df132 4920 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
feafb7b1
AE		 4921
4922 spin_lock_irqsave(&ha->vport_slock, flags);
4923 list_for_each_entry(vp, &ha->vp_list, list) {
4924 if (vp->vp_idx) {
4925 atomic_inc(&vp->vref_count);
4926 spin_unlock_irqrestore(&ha->vport_slock, flags);
4927
e315cd28 4928 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 4929
4930 spin_lock_irqsave(&ha->vport_slock, flags);
4931 atomic_dec(&vp->vref_count);
4932 }
e315cd28 4933 }
feafb7b1
AE		 4934 spin_unlock_irqrestore(&ha->vport_slock, flags);
4935
7d613ac6
SV		 4936 if (IS_QLA8031(ha)) {
4937 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
4938 "Setting back fcoe driver presence.\n");
4939 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
4940 ql_dbg(ql_dbg_p3p, vha, 0xb074,
4941 "Error while setting DRV-Presence.\n");
4942 }
e315cd28 4943 } else {
d8424f68
JP		 4944 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
4945 __func__);
1da177e4
LT		 4946 }
4947
4948 return(status);
4949}
4950
4951/*
4952* qla2x00_restart_isp
4953* restarts the ISP after a reset
4954*
4955* Input:
4956* ha = adapter block pointer.
4957*
4958* Returns:
4959* 0 = success
4960*/
4961static int
e315cd28 4962qla2x00_restart_isp(scsi_qla_host_t *vha)
1da177e4 4963{
c6b2fca8 4964 int status = 0;
e315cd28 4965 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 4966 struct req_que *req = ha->req_q_map[0];
4967 struct rsp_que *rsp = ha->rsp_q_map[0];
1da177e4
LT		 4968
4969 /* If firmware needs to be loaded */
e315cd28
AC		 4970 if (qla2x00_isp_firmware(vha)) {
4971 vha->flags.online = 0;
4972 status = ha->isp_ops->chip_diag(vha);
4973 if (!status)
4974 status = qla2x00_setup_chip(vha);
1da177e4
LT		 4975 }
4976
e315cd28
AC		 4977 if (!status && !(status = qla2x00_init_rings(vha))) {
4978 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
2533cf67 4979 ha->flags.chip_reset_done = 1;
7108b76e 4980
73208dfd
AC		 4981 /* Initialize the queues in use */
4982 qla25xx_init_queues(ha);
4983
e315cd28
AC		 4984 status = qla2x00_fw_ready(vha);
4985 if (!status) {
0107109e 4986 /* Issue a marker after FW becomes ready. */
73208dfd 4987 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
0107109e 4988
7108b76e 4989 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 4990 }
4991
4992 /* if no cable then assume it's good */
e315cd28 4993 if ((vha->device_flags & DFLG_NO_CABLE))
1da177e4 4994 status = 0;
1da177e4
LT		 4995 }
4996 return (status);
4997}
4998
73208dfd
AC		 4999static int
5000qla25xx_init_queues(struct qla_hw_data *ha)
5001{
5002 struct rsp_que *rsp = NULL;
5003 struct req_que *req = NULL;
5004 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
5005 int ret = -1;
5006 int i;
5007
2afa19a9 5008 for (i = 1; i < ha->max_rsp_queues; i++) {
73208dfd 5009 rsp = ha->rsp_q_map[i];
cb43285f 5010 if (rsp && test_bit(i, ha->rsp_qid_map)) {
73208dfd 5011 rsp->options &= ~BIT_0;
618a7523 5012 ret = qla25xx_init_rsp_que(base_vha, rsp);
73208dfd 5013 if (ret != QLA_SUCCESS)
7c3df132
SK		 5014 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
5015 "%s Rsp que: %d init failed.\n",
5016 __func__, rsp->id);
73208dfd 5017 else
7c3df132
SK		 5018 ql_dbg(ql_dbg_init, base_vha, 0x0100,
5019 "%s Rsp que: %d inited.\n",
5020 __func__, rsp->id);
73208dfd 5021 }
2afa19a9
AC		 5022 }
5023 for (i = 1; i < ha->max_req_queues; i++) {
73208dfd 5024 req = ha->req_q_map[i];
cb43285f
QT		 5025 if (req && test_bit(i, ha->req_qid_map)) {
5026 /* Clear outstanding commands array. */
73208dfd 5027 req->options &= ~BIT_0;
618a7523 5028 ret = qla25xx_init_req_que(base_vha, req);
73208dfd 5029 if (ret != QLA_SUCCESS)
7c3df132
SK		 5030 ql_dbg(ql_dbg_init, base_vha, 0x0101,
5031 "%s Req que: %d init failed.\n",
5032 __func__, req->id);
73208dfd 5033 else
7c3df132
SK		 5034 ql_dbg(ql_dbg_init, base_vha, 0x0102,
5035 "%s Req que: %d inited.\n",
5036 __func__, req->id);
73208dfd
AC		 5037 }
5038 }
5039 return ret;
5040}
5041
1da177e4
LT		 5042/*
5043* qla2x00_reset_adapter
5044* Reset adapter.
5045*
5046* Input:
5047* ha = adapter block pointer.
5048*/
abbd8870 5049void
e315cd28 5050qla2x00_reset_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 5051{
5052 unsigned long flags = 0;
e315cd28 5053 struct qla_hw_data *ha = vha->hw;
3d71644c 5054 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 5055
e315cd28 5056 vha->flags.online = 0;
fd34f556 5057 ha->isp_ops->disable_intrs(ha);
1da177e4 5058
1da177e4
LT		 5059 spin_lock_irqsave(&ha->hardware_lock, flags);
5060 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
5061 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
5062 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
5063 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
5064 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5065}
0107109e
AV		 5066
5067void
e315cd28 5068qla24xx_reset_adapter(scsi_qla_host_t *vha)
0107109e
AV		 5069{
5070 unsigned long flags = 0;
e315cd28 5071 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 5072 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
5073
7ec0effd 5074 if (IS_P3P_TYPE(ha))
a9083016
GM		 5075 return;
5076
e315cd28 5077 vha->flags.online = 0;
fd34f556 5078 ha->isp_ops->disable_intrs(ha);
0107109e
AV		 5079
5080 spin_lock_irqsave(&ha->hardware_lock, flags);
5081 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
5082 RD_REG_DWORD(&reg->hccr);
5083 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
5084 RD_REG_DWORD(&reg->hccr);
5085 spin_unlock_irqrestore(&ha->hardware_lock, flags);
09ff36d3
AV		 5086
5087 if (IS_NOPOLLING_TYPE(ha))
5088 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 5089}
5090
4e08df3f
DM		 5091/* On sparc systems, obtain port and node WWN from firmware
5092 * properties.
5093 */
e315cd28
AC		 5094static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
5095 struct nvram_24xx *nv)
4e08df3f
DM		 5096{
5097#ifdef CONFIG_SPARC
e315cd28 5098 struct qla_hw_data *ha = vha->hw;
4e08df3f 5099 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 5100 struct device_node *dp = pci_device_to_OF_node(pdev);
5101 const u8 *val;
4e08df3f
DM		 5102 int len;
5103
5104 val = of_get_property(dp, "port-wwn", &len);
5105 if (val && len >= WWN_SIZE)
5106 memcpy(nv->port_name, val, WWN_SIZE);
5107
5108 val = of_get_property(dp, "node-wwn", &len);
5109 if (val && len >= WWN_SIZE)
5110 memcpy(nv->node_name, val, WWN_SIZE);
5111#endif
5112}
5113
0107109e 5114int
e315cd28 5115qla24xx_nvram_config(scsi_qla_host_t *vha)
0107109e 5116{
4e08df3f 5117 int rval;
0107109e
AV		 5118 struct init_cb_24xx *icb;
5119 struct nvram_24xx *nv;
5120 uint32_t *dptr;
5121 uint8_t *dptr1, *dptr2;
5122 uint32_t chksum;
5123 uint16_t cnt;
e315cd28 5124 struct qla_hw_data *ha = vha->hw;
0107109e 5125
4e08df3f 5126 rval = QLA_SUCCESS;
0107109e 5127 icb = (struct init_cb_24xx *)ha->init_cb;
281afe19 5128 nv = ha->nvram;
0107109e
AV		 5129
5130 /* Determine NVRAM starting address. */
f73cb695 5131 if (ha->port_no == 0) {
e5b68a61
AC		 5132 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
5133 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
5134 } else {
0107109e 5135 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
6f641790 5136 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
5137 }
f73cb695 5138
e5b68a61
AC		 5139 ha->nvram_size = sizeof(struct nvram_24xx);
5140 ha->vpd_size = FA_NVRAM_VPD_SIZE;
0107109e 5141
281afe19
SJ		 5142 /* Get VPD data into cache */
5143 ha->vpd = ha->nvram + VPD_OFFSET;
e315cd28 5144 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
281afe19
SJ		 5145 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
5146
5147 /* Get NVRAM data into cache and calculate checksum. */
0107109e 5148 dptr = (uint32_t *)nv;
e315cd28 5149 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
0107109e 5150 ha->nvram_size);
da08ef5c
JC		 5151 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
5152 chksum += le32_to_cpu(*dptr);
0107109e 5153
7c3df132
SK		 5154 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
5155 "Contents of NVRAM\n");
5156 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
5157 (uint8_t *)nv, ha->nvram_size);
0107109e
AV		 5158
5159 /* Bad NVRAM data, set defaults parameters. */
5160 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
5161 || nv->id[3] != ' ' ||
ad950360 5162 nv->nvram_version < cpu_to_le16(ICB_VERSION)) {
0107109e 5163 /* Reset NVRAM data. */
7c3df132 5164 ql_log(ql_log_warn, vha, 0x006b,
9e336520 5165 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132
SK		 5166 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
5167 ql_log(ql_log_warn, vha, 0x006c,
5168 "Falling back to functioning (yet invalid -- WWPN) "
5169 "defaults.\n");
4e08df3f
DM		 5170
5171 /*
5172 * Set default initialization control block.
5173 */
5174 memset(nv, 0, ha->nvram_size);
ad950360
BVA		 5175 nv->nvram_version = cpu_to_le16(ICB_VERSION);
5176 nv->version = cpu_to_le16(ICB_VERSION);
98aee70d 5177 nv->frame_payload_size = 2048;
ad950360
BVA		 5178 nv->execution_throttle = cpu_to_le16(0xFFFF);
5179 nv->exchange_count = cpu_to_le16(0);
5180 nv->hard_address = cpu_to_le16(124);
4e08df3f 5181 nv->port_name[0] = 0x21;
f73cb695 5182 nv->port_name[1] = 0x00 + ha->port_no + 1;
4e08df3f
DM		 5183 nv->port_name[2] = 0x00;
5184 nv->port_name[3] = 0xe0;
5185 nv->port_name[4] = 0x8b;
5186 nv->port_name[5] = 0x1c;
5187 nv->port_name[6] = 0x55;
5188 nv->port_name[7] = 0x86;
5189 nv->node_name[0] = 0x20;
5190 nv->node_name[1] = 0x00;
5191 nv->node_name[2] = 0x00;
5192 nv->node_name[3] = 0xe0;
5193 nv->node_name[4] = 0x8b;
5194 nv->node_name[5] = 0x1c;
5195 nv->node_name[6] = 0x55;
5196 nv->node_name[7] = 0x86;
e315cd28 5197 qla24xx_nvram_wwn_from_ofw(vha, nv);
ad950360
BVA		 5198 nv->login_retry_count = cpu_to_le16(8);
5199 nv->interrupt_delay_timer = cpu_to_le16(0);
5200 nv->login_timeout = cpu_to_le16(0);
4e08df3f 5201 nv->firmware_options_1 =
ad950360
BVA		 5202 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
5203 nv->firmware_options_2 = cpu_to_le32(2 << 4);
5204 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
5205 nv->firmware_options_3 = cpu_to_le32(2 << 13);
5206 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
5207 nv->efi_parameters = cpu_to_le32(0);
4e08df3f 5208 nv->reset_delay = 5;
ad950360
BVA		 5209 nv->max_luns_per_target = cpu_to_le16(128);
5210 nv->port_down_retry_count = cpu_to_le16(30);
5211 nv->link_down_timeout = cpu_to_le16(30);
4e08df3f
DM		 5212
5213 rval = 1;
0107109e
AV		 5214 }
5215
2d70c103
NB		 5216 if (!qla_ini_mode_enabled(vha)) {
5217 /* Don't enable full login after initial LIP */
ad950360 5218 nv->firmware_options_1 &= cpu_to_le32(~BIT_13);
2d70c103 5219 /* Don't enable LIP full login for initiator */
ad950360 5220 nv->host_p &= cpu_to_le32(~BIT_10);
2d70c103
NB		 5221 }
5222
5223 qlt_24xx_config_nvram_stage1(vha, nv);
5224
0107109e 5225 /* Reset Initialization control block */
e315cd28 5226 memset(icb, 0, ha->init_cb_size);
0107109e
AV		 5227
5228 /* Copy 1st segment. */
5229 dptr1 = (uint8_t *)icb;
5230 dptr2 = (uint8_t *)&nv->version;
5231 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
5232 while (cnt--)
5233 *dptr1++ = *dptr2++;
5234
5235 icb->login_retry_count = nv->login_retry_count;
3ea66e28 5236 icb->link_down_on_nos = nv->link_down_on_nos;
0107109e
AV		 5237
5238 /* Copy 2nd segment. */
5239 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
5240 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
5241 cnt = (uint8_t *)&icb->reserved_3 -
5242 (uint8_t *)&icb->interrupt_delay_timer;
5243 while (cnt--)
5244 *dptr1++ = *dptr2++;
5245
5246 /*
5247 * Setup driver NVRAM options.
5248 */
e315cd28 5249 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9bb9fcf2 5250 "QLA2462");
0107109e 5251
2d70c103
NB		 5252 qlt_24xx_config_nvram_stage2(vha, icb);
5253
ad950360 5254 if (nv->host_p & cpu_to_le32(BIT_15)) {
2d70c103 5255 /* Use alternate WWN? */
5341e868
AV		 5256 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
5257 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
5258 }
5259
0107109e 5260 /* Prepare nodename */
ad950360 5261 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
0107109e
AV		 5262 /*
5263 * Firmware will apply the following mask if the nodename was
5264 * not provided.
5265 */
5266 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
5267 icb->node_name[0] &= 0xF0;
5268 }
5269
5270 /* Set host adapter parameters. */
5271 ha->flags.disable_risc_code_load = 0;
0c8c39af
AV		 5272 ha->flags.enable_lip_reset = 0;
5273 ha->flags.enable_lip_full_login =
5274 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
5275 ha->flags.enable_target_reset =
5276 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
0107109e 5277 ha->flags.enable_led_scheme = 0;
d4c760c2 5278 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
0107109e 5279
fd0e7e4d
AV		 5280 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
5281 (BIT_6 | BIT_5 | BIT_4)) >> 4;
0107109e
AV		 5282
5283 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
5284 sizeof(ha->fw_seriallink_options24));
5285
5286 /* save HBA serial number */
5287 ha->serial0 = icb->port_name[5];
5288 ha->serial1 = icb->port_name[6];
5289 ha->serial2 = icb->port_name[7];
e315cd28
AC		 5290 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
5291 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
0107109e 5292
ad950360 5293 icb->execution_throttle = cpu_to_le16(0xFFFF);
bc8fb3cb 5294
0107109e
AV		 5295 ha->retry_count = le16_to_cpu(nv->login_retry_count);
5296
5297 /* Set minimum login_timeout to 4 seconds. */
5298 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
5299 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
5300 if (le16_to_cpu(nv->login_timeout) < 4)
ad950360 5301 nv->login_timeout = cpu_to_le16(4);
0107109e 5302 ha->login_timeout = le16_to_cpu(nv->login_timeout);
0107109e 5303
00a537b8
AV		 5304 /* Set minimum RATOV to 100 tenths of a second. */
5305 ha->r_a_tov = 100;
0107109e
AV		 5306
5307 ha->loop_reset_delay = nv->reset_delay;
5308
5309 /* Link Down Timeout = 0:
5310 *
5311 * When Port Down timer expires we will start returning
5312 * I/O's to OS with "DID_NO_CONNECT".
5313 *
5314 * Link Down Timeout != 0:
5315 *
5316 * The driver waits for the link to come up after link down
5317 * before returning I/Os to OS with "DID_NO_CONNECT".
5318 */
5319 if (le16_to_cpu(nv->link_down_timeout) == 0) {
5320 ha->loop_down_abort_time =
5321 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
5322 } else {
5323 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
5324 ha->loop_down_abort_time =
5325 (LOOP_DOWN_TIME - ha->link_down_timeout);
5326 }
5327
5328 /* Need enough time to try and get the port back. */
5329 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
5330 if (qlport_down_retry)
5331 ha->port_down_retry_count = qlport_down_retry;
5332
5333 /* Set login_retry_count */
5334 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
5335 if (ha->port_down_retry_count ==
5336 le16_to_cpu(nv->port_down_retry_count) &&
5337 ha->port_down_retry_count > 3)
5338 ha->login_retry_count = ha->port_down_retry_count;
5339 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
5340 ha->login_retry_count = ha->port_down_retry_count;
5341 if (ql2xloginretrycount)
5342 ha->login_retry_count = ql2xloginretrycount;
5343
4fdfefe5 5344 /* Enable ZIO. */
e315cd28 5345 if (!vha->flags.init_done) {
4fdfefe5
AV		 5346 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
5347 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
5348 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
5349 le16_to_cpu(icb->interrupt_delay_timer): 2;
5350 }
ad950360 5351 icb->firmware_options_2 &= cpu_to_le32(
4fdfefe5 5352 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
e315cd28 5353 vha->flags.process_response_queue = 0;
4fdfefe5 5354 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d 5355 ha->zio_mode = QLA_ZIO_MODE_6;
5356
7c3df132 5357 ql_log(ql_log_info, vha, 0x006f,
4fdfefe5
AV		 5358 "ZIO mode %d enabled; timer delay (%d us).\n",
5359 ha->zio_mode, ha->zio_timer * 100);
5360
5361 icb->firmware_options_2 |= cpu_to_le32(
5362 (uint32_t)ha->zio_mode);
5363 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
e315cd28 5364 vha->flags.process_response_queue = 1;
4fdfefe5
AV		 5365 }
5366
4e08df3f 5367 if (rval) {
7c3df132
SK		 5368 ql_log(ql_log_warn, vha, 0x0070,
5369 "NVRAM configuration failed.\n");
4e08df3f
DM		 5370 }
5371 return (rval);
0107109e
AV		 5372}
5373
4243c115
SC		 5374uint8_t qla27xx_find_valid_image(struct scsi_qla_host *vha)
5375{
5376 struct qla27xx_image_status pri_image_status, sec_image_status;
5377 uint8_t valid_pri_image, valid_sec_image;
5378 uint32_t *wptr;
5379 uint32_t cnt, chksum, size;
5380 struct qla_hw_data *ha = vha->hw;
5381
5382 valid_pri_image = valid_sec_image = 1;
5383 ha->active_image = 0;
5384 size = sizeof(struct qla27xx_image_status) / sizeof(uint32_t);
5385
5386 if (!ha->flt_region_img_status_pri) {
5387 valid_pri_image = 0;
5388 goto check_sec_image;
5389 }
5390
5391 qla24xx_read_flash_data(vha, (uint32_t *)(&pri_image_status),
5392 ha->flt_region_img_status_pri, size);
5393
5394 if (pri_image_status.signature != QLA27XX_IMG_STATUS_SIGN) {
5395 ql_dbg(ql_dbg_init, vha, 0x018b,
5396 "Primary image signature (0x%x) not valid\n",
5397 pri_image_status.signature);
5398 valid_pri_image = 0;
5399 goto check_sec_image;
5400 }
5401
5402 wptr = (uint32_t *)(&pri_image_status);
5403 cnt = size;
5404
da08ef5c
JC		 5405 for (chksum = 0; cnt--; wptr++)
5406 chksum += le32_to_cpu(*wptr);
4243c115
SC		 5407 if (chksum) {
5408 ql_dbg(ql_dbg_init, vha, 0x018c,
5409 "Checksum validation failed for primary image (0x%x)\n",
5410 chksum);
5411 valid_pri_image = 0;
5412 }
5413
5414check_sec_image:
5415 if (!ha->flt_region_img_status_sec) {
5416 valid_sec_image = 0;
5417 goto check_valid_image;
5418 }
5419
5420 qla24xx_read_flash_data(vha, (uint32_t *)(&sec_image_status),
5421 ha->flt_region_img_status_sec, size);
5422
5423 if (sec_image_status.signature != QLA27XX_IMG_STATUS_SIGN) {
5424 ql_dbg(ql_dbg_init, vha, 0x018d,
5425 "Secondary image signature(0x%x) not valid\n",
5426 sec_image_status.signature);
5427 valid_sec_image = 0;
5428 goto check_valid_image;
5429 }
5430
5431 wptr = (uint32_t *)(&sec_image_status);
5432 cnt = size;
da08ef5c
JC		 5433 for (chksum = 0; cnt--; wptr++)
5434 chksum += le32_to_cpu(*wptr);
4243c115
SC		 5435 if (chksum) {
5436 ql_dbg(ql_dbg_init, vha, 0x018e,
5437 "Checksum validation failed for secondary image (0x%x)\n",
5438 chksum);
5439 valid_sec_image = 0;
5440 }
5441
5442check_valid_image:
5443 if (valid_pri_image && (pri_image_status.image_status_mask & 0x1))
5444 ha->active_image = QLA27XX_PRIMARY_IMAGE;
5445 if (valid_sec_image && (sec_image_status.image_status_mask & 0x1)) {
5446 if (!ha->active_image ||
5447 pri_image_status.generation_number <
5448 sec_image_status.generation_number)
5449 ha->active_image = QLA27XX_SECONDARY_IMAGE;
5450 }
5451
5452 ql_dbg(ql_dbg_init, vha, 0x018f, "%s image\n",
5453 ha->active_image == 0 ? "default bootld and fw" :
5454 ha->active_image == 1 ? "primary" :
5455 ha->active_image == 2 ? "secondary" :
5456 "Invalid");
5457
5458 return ha->active_image;
5459}
5460
413975a0 5461static int
cbc8eb67
AV		 5462qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
5463 uint32_t faddr)
d1c61909 5464{
73208dfd 5465 int rval = QLA_SUCCESS;
d1c61909 5466 int segments, fragment;
d1c61909
AV		 5467 uint32_t *dcode, dlen;
5468 uint32_t risc_addr;
5469 uint32_t risc_size;
5470 uint32_t i;
e315cd28 5471 struct qla_hw_data *ha = vha->hw;
73208dfd 5472 struct req_que *req = ha->req_q_map[0];
eaac30be 5473
7c3df132 5474 ql_dbg(ql_dbg_init, vha, 0x008b,
cfb0919c 5475 "FW: Loading firmware from flash (%x).\n", faddr);
eaac30be 5476
d1c61909
AV		 5477 rval = QLA_SUCCESS;
5478
5479 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5480 dcode = (uint32_t *)req->ring;
d1c61909
AV		 5481 *srisc_addr = 0;
5482
4243c115
SC		 5483 if (IS_QLA27XX(ha) &&
5484 qla27xx_find_valid_image(vha) == QLA27XX_SECONDARY_IMAGE)
5485 faddr = ha->flt_region_fw_sec;
5486
d1c61909 5487 /* Validate firmware image by checking version. */
e315cd28 5488 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
d1c61909
AV		 5489 for (i = 0; i < 4; i++)
5490 dcode[i] = be32_to_cpu(dcode[i]);
5491 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5492 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5493 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5494 dcode[3] == 0)) {
7c3df132
SK		 5495 ql_log(ql_log_fatal, vha, 0x008c,
5496 "Unable to verify the integrity of flash firmware "
5497 "image.\n");
5498 ql_log(ql_log_fatal, vha, 0x008d,
5499 "Firmware data: %08x %08x %08x %08x.\n",
5500 dcode[0], dcode[1], dcode[2], dcode[3]);
d1c61909
AV		 5501
5502 return QLA_FUNCTION_FAILED;
5503 }
5504
5505 while (segments && rval == QLA_SUCCESS) {
5506 /* Read segment's load information. */
e315cd28 5507 qla24xx_read_flash_data(vha, dcode, faddr, 4);
d1c61909
AV		 5508
5509 risc_addr = be32_to_cpu(dcode[2]);
5510 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5511 risc_size = be32_to_cpu(dcode[3]);
5512
5513 fragment = 0;
5514 while (risc_size > 0 && rval == QLA_SUCCESS) {
5515 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5516 if (dlen > risc_size)
5517 dlen = risc_size;
5518
7c3df132
SK		 5519 ql_dbg(ql_dbg_init, vha, 0x008e,
5520 "Loading risc segment@ risc addr %x "
5521 "number of dwords 0x%x offset 0x%x.\n",
5522 risc_addr, dlen, faddr);
d1c61909 5523
e315cd28 5524 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
d1c61909
AV		 5525 for (i = 0; i < dlen; i++)
5526 dcode[i] = swab32(dcode[i]);
5527
73208dfd 5528 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
d1c61909
AV		 5529 dlen);
5530 if (rval) {
7c3df132
SK		 5531 ql_log(ql_log_fatal, vha, 0x008f,
5532 "Failed to load segment %d of firmware.\n",
5533 fragment);
f261f7af 5534 return QLA_FUNCTION_FAILED;
d1c61909
AV		 5535 }
5536
5537 faddr += dlen;
5538 risc_addr += dlen;
5539 risc_size -= dlen;
5540 fragment++;
5541 }
5542
5543 /* Next segment. */
5544 segments--;
5545 }
5546
f73cb695
CD		 5547 if (!IS_QLA27XX(ha))
5548 return rval;
5549
5550 if (ha->fw_dump_template)
5551 vfree(ha->fw_dump_template);
5552 ha->fw_dump_template = NULL;
5553 ha->fw_dump_template_len = 0;
5554
5555 ql_dbg(ql_dbg_init, vha, 0x0161,
5556 "Loading fwdump template from %x\n", faddr);
5557 qla24xx_read_flash_data(vha, dcode, faddr, 7);
5558 risc_size = be32_to_cpu(dcode[2]);
5559 ql_dbg(ql_dbg_init, vha, 0x0162,
5560 "-> array size %x dwords\n", risc_size);
5561 if (risc_size == 0 || risc_size == ~0)
5562 goto default_template;
5563
5564 dlen = (risc_size - 8) * sizeof(*dcode);
5565 ql_dbg(ql_dbg_init, vha, 0x0163,
5566 "-> template allocating %x bytes...\n", dlen);
5567 ha->fw_dump_template = vmalloc(dlen);
5568 if (!ha->fw_dump_template) {
5569 ql_log(ql_log_warn, vha, 0x0164,
5570 "Failed fwdump template allocate %x bytes.\n", risc_size);
5571 goto default_template;
5572 }
5573
5574 faddr += 7;
5575 risc_size -= 8;
5576 dcode = ha->fw_dump_template;
5577 qla24xx_read_flash_data(vha, dcode, faddr, risc_size);
5578 for (i = 0; i < risc_size; i++)
5579 dcode[i] = le32_to_cpu(dcode[i]);
5580
5581 if (!qla27xx_fwdt_template_valid(dcode)) {
5582 ql_log(ql_log_warn, vha, 0x0165,
5583 "Failed fwdump template validate\n");
5584 goto default_template;
5585 }
5586
5587 dlen = qla27xx_fwdt_template_size(dcode);
5588 ql_dbg(ql_dbg_init, vha, 0x0166,
5589 "-> template size %x bytes\n", dlen);
5590 if (dlen > risc_size * sizeof(*dcode)) {
5591 ql_log(ql_log_warn, vha, 0x0167,
97ea702b
CD		 5592 "Failed fwdump template exceeds array by %x bytes\n",
5593 (uint32_t)(dlen - risc_size * sizeof(*dcode)));
f73cb695
CD		 5594 goto default_template;
5595 }
5596 ha->fw_dump_template_len = dlen;
5597 return rval;
5598
5599default_template:
5600 ql_log(ql_log_warn, vha, 0x0168, "Using default fwdump template\n");
5601 if (ha->fw_dump_template)
5602 vfree(ha->fw_dump_template);
5603 ha->fw_dump_template = NULL;
5604 ha->fw_dump_template_len = 0;
5605
5606 dlen = qla27xx_fwdt_template_default_size();
5607 ql_dbg(ql_dbg_init, vha, 0x0169,
5608 "-> template allocating %x bytes...\n", dlen);
5609 ha->fw_dump_template = vmalloc(dlen);
5610 if (!ha->fw_dump_template) {
5611 ql_log(ql_log_warn, vha, 0x016a,
5612 "Failed fwdump template allocate %x bytes.\n", risc_size);
5613 goto failed_template;
5614 }
5615
5616 dcode = ha->fw_dump_template;
5617 risc_size = dlen / sizeof(*dcode);
5618 memcpy(dcode, qla27xx_fwdt_template_default(), dlen);
5619 for (i = 0; i < risc_size; i++)
5620 dcode[i] = be32_to_cpu(dcode[i]);
5621
5622 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
5623 ql_log(ql_log_warn, vha, 0x016b,
5624 "Failed fwdump template validate\n");
5625 goto failed_template;
5626 }
5627
5628 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
5629 ql_dbg(ql_dbg_init, vha, 0x016c,
5630 "-> template size %x bytes\n", dlen);
5631 ha->fw_dump_template_len = dlen;
5632 return rval;
5633
5634failed_template:
5635 ql_log(ql_log_warn, vha, 0x016d, "Failed default fwdump template\n");
5636 if (ha->fw_dump_template)
5637 vfree(ha->fw_dump_template);
5638 ha->fw_dump_template = NULL;
5639 ha->fw_dump_template_len = 0;
d1c61909
AV		 5640 return rval;
5641}
5642
e9454a88 5643#define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
d1c61909 5644
0107109e 5645int
e315cd28 5646qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5433383e
AV		 5647{
5648 int rval;
5649 int i, fragment;
5650 uint16_t *wcode, *fwcode;
5651 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
5652 struct fw_blob *blob;
e315cd28 5653 struct qla_hw_data *ha = vha->hw;
73208dfd 5654 struct req_que *req = ha->req_q_map[0];
5433383e
AV		 5655
5656 /* Load firmware blob. */
e315cd28 5657 blob = qla2x00_request_firmware(vha);
5433383e 5658 if (!blob) {
7c3df132 5659 ql_log(ql_log_info, vha, 0x0083,
94bcf830 5660 "Firmware image unavailable.\n");
7c3df132
SK		 5661 ql_log(ql_log_info, vha, 0x0084,
5662 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5433383e
AV		 5663 return QLA_FUNCTION_FAILED;
5664 }
5665
5666 rval = QLA_SUCCESS;
5667
73208dfd 5668 wcode = (uint16_t *)req->ring;
5433383e
AV		 5669 *srisc_addr = 0;
5670 fwcode = (uint16_t *)blob->fw->data;
5671 fwclen = 0;
5672
5673 /* Validate firmware image by checking version. */
5674 if (blob->fw->size < 8 * sizeof(uint16_t)) {
7c3df132
SK		 5675 ql_log(ql_log_fatal, vha, 0x0085,
5676 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e
AV		 5677 blob->fw->size);
5678 goto fail_fw_integrity;
5679 }
5680 for (i = 0; i < 4; i++)
5681 wcode[i] = be16_to_cpu(fwcode[i + 4]);
5682 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
5683 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
5684 wcode[2] == 0 && wcode[3] == 0)) {
7c3df132
SK		 5685 ql_log(ql_log_fatal, vha, 0x0086,
5686 "Unable to verify integrity of firmware image.\n");
5687 ql_log(ql_log_fatal, vha, 0x0087,
5688 "Firmware data: %04x %04x %04x %04x.\n",
5689 wcode[0], wcode[1], wcode[2], wcode[3]);
5433383e
AV		 5690 goto fail_fw_integrity;
5691 }
5692
5693 seg = blob->segs;
5694 while (*seg && rval == QLA_SUCCESS) {
5695 risc_addr = *seg;
5696 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
5697 risc_size = be16_to_cpu(fwcode[3]);
5698
5699 /* Validate firmware image size. */
5700 fwclen += risc_size * sizeof(uint16_t);
5701 if (blob->fw->size < fwclen) {
7c3df132 5702 ql_log(ql_log_fatal, vha, 0x0088,
5433383e 5703 "Unable to verify integrity of firmware image "
7c3df132 5704 "(%Zd).\n", blob->fw->size);
5433383e
AV		 5705 goto fail_fw_integrity;
5706 }
5707
5708 fragment = 0;
5709 while (risc_size > 0 && rval == QLA_SUCCESS) {
5710 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
5711 if (wlen > risc_size)
5712 wlen = risc_size;
7c3df132
SK		 5713 ql_dbg(ql_dbg_init, vha, 0x0089,
5714 "Loading risc segment@ risc addr %x number of "
5715 "words 0x%x.\n", risc_addr, wlen);
5433383e
AV		 5716
5717 for (i = 0; i < wlen; i++)
5718 wcode[i] = swab16(fwcode[i]);
5719
73208dfd 5720 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5433383e
AV		 5721 wlen);
5722 if (rval) {
7c3df132
SK		 5723 ql_log(ql_log_fatal, vha, 0x008a,
5724 "Failed to load segment %d of firmware.\n",
5725 fragment);
5433383e
AV		 5726 break;
5727 }
5728
5729 fwcode += wlen;
5730 risc_addr += wlen;
5731 risc_size -= wlen;
5732 fragment++;
5733 }
5734
5735 /* Next segment. */
5736 seg++;
5737 }
5738 return rval;
5739
5740fail_fw_integrity:
5741 return QLA_FUNCTION_FAILED;
5742}
5743
eaac30be
AV		 5744static int
5745qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
0107109e
AV		 5746{
5747 int rval;
5748 int segments, fragment;
5749 uint32_t *dcode, dlen;
5750 uint32_t risc_addr;
5751 uint32_t risc_size;
5752 uint32_t i;
5433383e 5753 struct fw_blob *blob;
f73cb695
CD		 5754 const uint32_t *fwcode;
5755 uint32_t fwclen;
e315cd28 5756 struct qla_hw_data *ha = vha->hw;
73208dfd 5757 struct req_que *req = ha->req_q_map[0];
0107109e 5758
5433383e 5759 /* Load firmware blob. */
e315cd28 5760 blob = qla2x00_request_firmware(vha);
5433383e 5761 if (!blob) {
7c3df132 5762 ql_log(ql_log_warn, vha, 0x0090,
94bcf830 5763 "Firmware image unavailable.\n");
7c3df132
SK		 5764 ql_log(ql_log_warn, vha, 0x0091,
5765 "Firmware images can be retrieved from: "
5766 QLA_FW_URL ".\n");
d1c61909 5767
eaac30be 5768 return QLA_FUNCTION_FAILED;
0107109e
AV		 5769 }
5770
cfb0919c
CD		 5771 ql_dbg(ql_dbg_init, vha, 0x0092,
5772 "FW: Loading via request-firmware.\n");
eaac30be 5773
0107109e
AV		 5774 rval = QLA_SUCCESS;
5775
5776 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5777 dcode = (uint32_t *)req->ring;
0107109e 5778 *srisc_addr = 0;
5433383e 5779 fwcode = (uint32_t *)blob->fw->data;
0107109e
AV		 5780 fwclen = 0;
5781
5782 /* Validate firmware image by checking version. */
5433383e 5783 if (blob->fw->size < 8 * sizeof(uint32_t)) {
7c3df132
SK		 5784 ql_log(ql_log_fatal, vha, 0x0093,
5785 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e 5786 blob->fw->size);
f73cb695 5787 return QLA_FUNCTION_FAILED;
0107109e
AV		 5788 }
5789 for (i = 0; i < 4; i++)
5790 dcode[i] = be32_to_cpu(fwcode[i + 4]);
5791 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5792 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5793 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5794 dcode[3] == 0)) {
7c3df132
SK		 5795 ql_log(ql_log_fatal, vha, 0x0094,
5796 "Unable to verify integrity of firmware image (%Zd).\n",
5797 blob->fw->size);
5798 ql_log(ql_log_fatal, vha, 0x0095,
5799 "Firmware data: %08x %08x %08x %08x.\n",
5800 dcode[0], dcode[1], dcode[2], dcode[3]);
f73cb695 5801 return QLA_FUNCTION_FAILED;
0107109e
AV		 5802 }
5803
5804 while (segments && rval == QLA_SUCCESS) {
5805 risc_addr = be32_to_cpu(fwcode[2]);
5806 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5807 risc_size = be32_to_cpu(fwcode[3]);
5808
5809 /* Validate firmware image size. */
5810 fwclen += risc_size * sizeof(uint32_t);
5433383e 5811 if (blob->fw->size < fwclen) {
7c3df132 5812 ql_log(ql_log_fatal, vha, 0x0096,
5433383e 5813 "Unable to verify integrity of firmware image "
7c3df132 5814 "(%Zd).\n", blob->fw->size);
f73cb695 5815 return QLA_FUNCTION_FAILED;
0107109e
AV		 5816 }
5817
5818 fragment = 0;
5819 while (risc_size > 0 && rval == QLA_SUCCESS) {
5820 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5821 if (dlen > risc_size)
5822 dlen = risc_size;
5823
7c3df132
SK		 5824 ql_dbg(ql_dbg_init, vha, 0x0097,
5825 "Loading risc segment@ risc addr %x "
5826 "number of dwords 0x%x.\n", risc_addr, dlen);
0107109e
AV		 5827
5828 for (i = 0; i < dlen; i++)
5829 dcode[i] = swab32(fwcode[i]);
5830
73208dfd 5831 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
590f98e5 5832 dlen);
0107109e 5833 if (rval) {
7c3df132
SK		 5834 ql_log(ql_log_fatal, vha, 0x0098,
5835 "Failed to load segment %d of firmware.\n",
5836 fragment);
f261f7af 5837 return QLA_FUNCTION_FAILED;
0107109e
AV		 5838 }
5839
5840 fwcode += dlen;
5841 risc_addr += dlen;
5842 risc_size -= dlen;
5843 fragment++;
5844 }
5845
5846 /* Next segment. */
5847 segments--;
5848 }
f73cb695
CD		 5849
5850 if (!IS_QLA27XX(ha))
5851 return rval;
5852
5853 if (ha->fw_dump_template)
5854 vfree(ha->fw_dump_template);
5855 ha->fw_dump_template = NULL;
5856 ha->fw_dump_template_len = 0;
5857
5858 ql_dbg(ql_dbg_init, vha, 0x171,
97ea702b
CD		 5859 "Loading fwdump template from %x\n",
5860 (uint32_t)((void *)fwcode - (void *)blob->fw->data));
f73cb695
CD		 5861 risc_size = be32_to_cpu(fwcode[2]);
5862 ql_dbg(ql_dbg_init, vha, 0x172,
5863 "-> array size %x dwords\n", risc_size);
5864 if (risc_size == 0 || risc_size == ~0)
5865 goto default_template;
5866
5867 dlen = (risc_size - 8) * sizeof(*fwcode);
5868 ql_dbg(ql_dbg_init, vha, 0x0173,
5869 "-> template allocating %x bytes...\n", dlen);
5870 ha->fw_dump_template = vmalloc(dlen);
5871 if (!ha->fw_dump_template) {
5872 ql_log(ql_log_warn, vha, 0x0174,
5873 "Failed fwdump template allocate %x bytes.\n", risc_size);
5874 goto default_template;
5875 }
5876
5877 fwcode += 7;
5878 risc_size -= 8;
5879 dcode = ha->fw_dump_template;
5880 for (i = 0; i < risc_size; i++)
5881 dcode[i] = le32_to_cpu(fwcode[i]);
5882
5883 if (!qla27xx_fwdt_template_valid(dcode)) {
5884 ql_log(ql_log_warn, vha, 0x0175,
5885 "Failed fwdump template validate\n");
5886 goto default_template;
5887 }
5888
5889 dlen = qla27xx_fwdt_template_size(dcode);
5890 ql_dbg(ql_dbg_init, vha, 0x0176,
5891 "-> template size %x bytes\n", dlen);
5892 if (dlen > risc_size * sizeof(*fwcode)) {
5893 ql_log(ql_log_warn, vha, 0x0177,
97ea702b
CD		 5894 "Failed fwdump template exceeds array by %x bytes\n",
5895 (uint32_t)(dlen - risc_size * sizeof(*fwcode)));
f73cb695
CD		 5896 goto default_template;
5897 }
5898 ha->fw_dump_template_len = dlen;
0107109e
AV		 5899 return rval;
5900
f73cb695
CD		 5901default_template:
5902 ql_log(ql_log_warn, vha, 0x0178, "Using default fwdump template\n");
5903 if (ha->fw_dump_template)
5904 vfree(ha->fw_dump_template);
5905 ha->fw_dump_template = NULL;
5906 ha->fw_dump_template_len = 0;
5907
5908 dlen = qla27xx_fwdt_template_default_size();
5909 ql_dbg(ql_dbg_init, vha, 0x0179,
5910 "-> template allocating %x bytes...\n", dlen);
5911 ha->fw_dump_template = vmalloc(dlen);
5912 if (!ha->fw_dump_template) {
5913 ql_log(ql_log_warn, vha, 0x017a,
5914 "Failed fwdump template allocate %x bytes.\n", risc_size);
5915 goto failed_template;
5916 }
5917
5918 dcode = ha->fw_dump_template;
5919 risc_size = dlen / sizeof(*fwcode);
5920 fwcode = qla27xx_fwdt_template_default();
5921 for (i = 0; i < risc_size; i++)
5922 dcode[i] = be32_to_cpu(fwcode[i]);
5923
5924 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
5925 ql_log(ql_log_warn, vha, 0x017b,
5926 "Failed fwdump template validate\n");
5927 goto failed_template;
5928 }
5929
5930 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
5931 ql_dbg(ql_dbg_init, vha, 0x017c,
5932 "-> template size %x bytes\n", dlen);
5933 ha->fw_dump_template_len = dlen;
5934 return rval;
5935
5936failed_template:
5937 ql_log(ql_log_warn, vha, 0x017d, "Failed default fwdump template\n");
5938 if (ha->fw_dump_template)
5939 vfree(ha->fw_dump_template);
5940 ha->fw_dump_template = NULL;
5941 ha->fw_dump_template_len = 0;
5942 return rval;
0107109e 5943}
18c6c127 5944
eaac30be
AV		 5945int
5946qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5947{
5948 int rval;
5949
e337d907
AV		 5950 if (ql2xfwloadbin == 1)
5951 return qla81xx_load_risc(vha, srisc_addr);
5952
eaac30be
AV		 5953 /*
5954 * FW Load priority:
5955 * 1) Firmware via request-firmware interface (.bin file).
5956 * 2) Firmware residing in flash.
5957 */
5958 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5959 if (rval == QLA_SUCCESS)
5960 return rval;
5961
cbc8eb67
AV		 5962 return qla24xx_load_risc_flash(vha, srisc_addr,
5963 vha->hw->flt_region_fw);
eaac30be
AV		 5964}
5965
5966int
5967qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5968{
5969 int rval;
cbc8eb67 5970 struct qla_hw_data *ha = vha->hw;
eaac30be 5971
e337d907 5972 if (ql2xfwloadbin == 2)
cbc8eb67 5973 goto try_blob_fw;
e337d907 5974
eaac30be
AV		 5975 /*
5976 * FW Load priority:
5977 * 1) Firmware residing in flash.
5978 * 2) Firmware via request-firmware interface (.bin file).
cbc8eb67 5979 * 3) Golden-Firmware residing in flash -- limited operation.
eaac30be 5980 */
cbc8eb67 5981 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
eaac30be
AV		 5982 if (rval == QLA_SUCCESS)
5983 return rval;
5984
cbc8eb67
AV		 5985try_blob_fw:
5986 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5987 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
5988 return rval;
5989
7c3df132
SK		 5990 ql_log(ql_log_info, vha, 0x0099,
5991 "Attempting to fallback to golden firmware.\n");
cbc8eb67
AV		 5992 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
5993 if (rval != QLA_SUCCESS)
5994 return rval;
5995
7c3df132 5996 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
cbc8eb67 5997 ha->flags.running_gold_fw = 1;
cbc8eb67 5998 return rval;
eaac30be
AV		 5999}
6000
18c6c127 6001void
e315cd28 6002qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
18c6c127
AV		 6003{
6004 int ret, retries;
e315cd28 6005 struct qla_hw_data *ha = vha->hw;
18c6c127 6006
85880801
AV		 6007 if (ha->flags.pci_channel_io_perm_failure)
6008 return;
e428924c 6009 if (!IS_FWI2_CAPABLE(ha))
18c6c127 6010 return;
75edf81d
AV		 6011 if (!ha->fw_major_version)
6012 return;
18c6c127 6013
e315cd28 6014 ret = qla2x00_stop_firmware(vha);
7c7f1f29 6015 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
b469a7cb 6016 ret != QLA_INVALID_COMMAND && retries ; retries--) {
e315cd28
AC		 6017 ha->isp_ops->reset_chip(vha);
6018 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
18c6c127 6019 continue;
e315cd28 6020 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
18c6c127 6021 continue;
7c3df132
SK		 6022 ql_log(ql_log_info, vha, 0x8015,
6023 "Attempting retry of stop-firmware command.\n");
e315cd28 6024 ret = qla2x00_stop_firmware(vha);
18c6c127
AV		 6025 }
6026}
2c3dfe3f
SJ		 6027
6028int
e315cd28 6029qla24xx_configure_vhba(scsi_qla_host_t *vha)
2c3dfe3f
SJ		 6030{
6031 int rval = QLA_SUCCESS;
0b91d116 6032 int rval2;
2c3dfe3f 6033 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28
AC		 6034 struct qla_hw_data *ha = vha->hw;
6035 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
67c2e93a
AC		 6036 struct req_que *req;
6037 struct rsp_que *rsp;
2c3dfe3f 6038
e315cd28 6039 if (!vha->vp_idx)
2c3dfe3f
SJ		 6040 return -EINVAL;
6041
e315cd28 6042 rval = qla2x00_fw_ready(base_vha);
7163ea81 6043 if (ha->flags.cpu_affinity_enabled)
67c2e93a
AC		 6044 req = ha->req_q_map[0];
6045 else
6046 req = vha->req;
6047 rsp = req->rsp;
6048
2c3dfe3f 6049 if (rval == QLA_SUCCESS) {
e315cd28 6050 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
73208dfd 6051 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
2c3dfe3f
SJ		 6052 }
6053
e315cd28 6054 vha->flags.management_server_logged_in = 0;
2c3dfe3f
SJ		 6055
6056 /* Login to SNS first */
0b91d116
CD		 6057 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
6058 BIT_1);
6059 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
6060 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
6061 ql_dbg(ql_dbg_init, vha, 0x0120,
6062 "Failed SNS login: loop_id=%x, rval2=%d\n",
6063 NPH_SNS, rval2);
6064 else
6065 ql_dbg(ql_dbg_init, vha, 0x0103,
6066 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
6067 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
6068 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
2c3dfe3f
SJ		 6069 return (QLA_FUNCTION_FAILED);
6070 }
6071
e315cd28
AC		 6072 atomic_set(&vha->loop_down_timer, 0);
6073 atomic_set(&vha->loop_state, LOOP_UP);
6074 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
6075 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
6076 rval = qla2x00_loop_resync(base_vha);
2c3dfe3f
SJ		 6077
6078 return rval;
6079}
4d4df193
HK		 6080
6081/* 84XX Support **************************************************************/
6082
6083static LIST_HEAD(qla_cs84xx_list);
6084static DEFINE_MUTEX(qla_cs84xx_mutex);
6085
6086static struct qla_chip_state_84xx *
e315cd28 6087qla84xx_get_chip(struct scsi_qla_host *vha)
4d4df193
HK		 6088{
6089 struct qla_chip_state_84xx *cs84xx;
e315cd28 6090 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 6091
6092 mutex_lock(&qla_cs84xx_mutex);
6093
6094 /* Find any shared 84xx chip. */
6095 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
6096 if (cs84xx->bus == ha->pdev->bus) {
6097 kref_get(&cs84xx->kref);
6098 goto done;
6099 }
6100 }
6101
6102 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
6103 if (!cs84xx)
6104 goto done;
6105
6106 kref_init(&cs84xx->kref);
6107 spin_lock_init(&cs84xx->access_lock);
6108 mutex_init(&cs84xx->fw_update_mutex);
6109 cs84xx->bus = ha->pdev->bus;
6110
6111 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
6112done:
6113 mutex_unlock(&qla_cs84xx_mutex);
6114 return cs84xx;
6115}
6116
6117static void
6118__qla84xx_chip_release(struct kref *kref)
6119{
6120 struct qla_chip_state_84xx *cs84xx =
6121 container_of(kref, struct qla_chip_state_84xx, kref);
6122
6123 mutex_lock(&qla_cs84xx_mutex);
6124 list_del(&cs84xx->list);
6125 mutex_unlock(&qla_cs84xx_mutex);
6126 kfree(cs84xx);
6127}
6128
6129void
e315cd28 6130qla84xx_put_chip(struct scsi_qla_host *vha)
4d4df193 6131{
e315cd28 6132 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 6133 if (ha->cs84xx)
6134 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
6135}
6136
6137static int
e315cd28 6138qla84xx_init_chip(scsi_qla_host_t *vha)
4d4df193
HK		 6139{
6140 int rval;
6141 uint16_t status[2];
e315cd28 6142 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 6143
6144 mutex_lock(&ha->cs84xx->fw_update_mutex);
6145
e315cd28 6146 rval = qla84xx_verify_chip(vha, status);
4d4df193
HK		 6147
6148 mutex_unlock(&ha->cs84xx->fw_update_mutex);
6149
6150 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
6151 QLA_SUCCESS;
6152}
3a03eb79
AV		 6153
6154/* 81XX Support **************************************************************/
6155
6156int
6157qla81xx_nvram_config(scsi_qla_host_t *vha)
6158{
6159 int rval;
6160 struct init_cb_81xx *icb;
6161 struct nvram_81xx *nv;
6162 uint32_t *dptr;
6163 uint8_t *dptr1, *dptr2;
6164 uint32_t chksum;
6165 uint16_t cnt;
6166 struct qla_hw_data *ha = vha->hw;
6167
6168 rval = QLA_SUCCESS;
6169 icb = (struct init_cb_81xx *)ha->init_cb;
6170 nv = ha->nvram;
6171
6172 /* Determine NVRAM starting address. */
6173 ha->nvram_size = sizeof(struct nvram_81xx);
3a03eb79 6174 ha->vpd_size = FA_NVRAM_VPD_SIZE;
7ec0effd
AD		 6175 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
6176 ha->vpd_size = FA_VPD_SIZE_82XX;
3a03eb79
AV		 6177
6178 /* Get VPD data into cache */
6179 ha->vpd = ha->nvram + VPD_OFFSET;
3d79038f
AV		 6180 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
6181 ha->vpd_size);
3a03eb79
AV		 6182
6183 /* Get NVRAM data into cache and calculate checksum. */
3d79038f 6184 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
3a03eb79 6185 ha->nvram_size);
3d79038f 6186 dptr = (uint32_t *)nv;
da08ef5c
JC		 6187 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
6188 chksum += le32_to_cpu(*dptr);
3a03eb79 6189
7c3df132
SK		 6190 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
6191 "Contents of NVRAM:\n");
6192 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
6193 (uint8_t *)nv, ha->nvram_size);
3a03eb79
AV		 6194
6195 /* Bad NVRAM data, set defaults parameters. */
6196 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
6197 || nv->id[3] != ' ' ||
ad950360 6198 nv->nvram_version < cpu_to_le16(ICB_VERSION)) {
3a03eb79 6199 /* Reset NVRAM data. */
7c3df132 6200 ql_log(ql_log_info, vha, 0x0073,
9e336520 6201 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132 6202 "version=0x%x.\n", chksum, nv->id[0],
3a03eb79 6203 le16_to_cpu(nv->nvram_version));
7c3df132
SK		 6204 ql_log(ql_log_info, vha, 0x0074,
6205 "Falling back to functioning (yet invalid -- WWPN) "
6206 "defaults.\n");
3a03eb79
AV		 6207
6208 /*
6209 * Set default initialization control block.
6210 */
6211 memset(nv, 0, ha->nvram_size);
ad950360
BVA		 6212 nv->nvram_version = cpu_to_le16(ICB_VERSION);
6213 nv->version = cpu_to_le16(ICB_VERSION);
98aee70d 6214 nv->frame_payload_size = 2048;
ad950360
BVA		 6215 nv->execution_throttle = cpu_to_le16(0xFFFF);
6216 nv->exchange_count = cpu_to_le16(0);
3a03eb79 6217 nv->port_name[0] = 0x21;
f73cb695 6218 nv->port_name[1] = 0x00 + ha->port_no + 1;
3a03eb79
AV		 6219 nv->port_name[2] = 0x00;
6220 nv->port_name[3] = 0xe0;
6221 nv->port_name[4] = 0x8b;
6222 nv->port_name[5] = 0x1c;
6223 nv->port_name[6] = 0x55;
6224 nv->port_name[7] = 0x86;
6225 nv->node_name[0] = 0x20;
6226 nv->node_name[1] = 0x00;
6227 nv->node_name[2] = 0x00;
6228 nv->node_name[3] = 0xe0;
6229 nv->node_name[4] = 0x8b;
6230 nv->node_name[5] = 0x1c;
6231 nv->node_name[6] = 0x55;
6232 nv->node_name[7] = 0x86;
ad950360
BVA		 6233 nv->login_retry_count = cpu_to_le16(8);
6234 nv->interrupt_delay_timer = cpu_to_le16(0);
6235 nv->login_timeout = cpu_to_le16(0);
3a03eb79 6236 nv->firmware_options_1 =
ad950360
BVA		 6237 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
6238 nv->firmware_options_2 = cpu_to_le32(2 << 4);
6239 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
6240 nv->firmware_options_3 = cpu_to_le32(2 << 13);
6241 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
6242 nv->efi_parameters = cpu_to_le32(0);
3a03eb79 6243 nv->reset_delay = 5;
ad950360
BVA		 6244 nv->max_luns_per_target = cpu_to_le16(128);
6245 nv->port_down_retry_count = cpu_to_le16(30);
6246 nv->link_down_timeout = cpu_to_le16(180);
eeebcc92 6247 nv->enode_mac[0] = 0x00;
6246b8a1
GM		 6248 nv->enode_mac[1] = 0xC0;
6249 nv->enode_mac[2] = 0xDD;
3a03eb79
AV		 6250 nv->enode_mac[3] = 0x04;
6251 nv->enode_mac[4] = 0x05;
f73cb695 6252 nv->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 6253
6254 rval = 1;
6255 }
6256
9e522cd8
AE		 6257 if (IS_T10_PI_CAPABLE(ha))
6258 nv->frame_payload_size &= ~7;
6259
aa230bc5
AE		 6260 qlt_81xx_config_nvram_stage1(vha, nv);
6261
3a03eb79 6262 /* Reset Initialization control block */
773120e4 6263 memset(icb, 0, ha->init_cb_size);
3a03eb79
AV		 6264
6265 /* Copy 1st segment. */
6266 dptr1 = (uint8_t *)icb;
6267 dptr2 = (uint8_t *)&nv->version;
6268 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
6269 while (cnt--)
6270 *dptr1++ = *dptr2++;
6271
6272 icb->login_retry_count = nv->login_retry_count;
6273
6274 /* Copy 2nd segment. */
6275 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
6276 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
6277 cnt = (uint8_t *)&icb->reserved_5 -
6278 (uint8_t *)&icb->interrupt_delay_timer;
6279 while (cnt--)
6280 *dptr1++ = *dptr2++;
6281
6282 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
6283 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
6284 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
69e5f1ea
AV		 6285 icb->enode_mac[0] = 0x00;
6286 icb->enode_mac[1] = 0xC0;
6287 icb->enode_mac[2] = 0xDD;
3a03eb79
AV		 6288 icb->enode_mac[3] = 0x04;
6289 icb->enode_mac[4] = 0x05;
f73cb695 6290 icb->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 6291 }
6292
b64b0e8f
AV		 6293 /* Use extended-initialization control block. */
6294 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
6295
3a03eb79
AV		 6296 /*
6297 * Setup driver NVRAM options.
6298 */
6299 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
a9083016 6300 "QLE8XXX");
3a03eb79 6301
aa230bc5
AE		 6302 qlt_81xx_config_nvram_stage2(vha, icb);
6303
3a03eb79 6304 /* Use alternate WWN? */
ad950360 6305 if (nv->host_p & cpu_to_le32(BIT_15)) {
3a03eb79
AV		 6306 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
6307 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
6308 }
6309
6310 /* Prepare nodename */
ad950360 6311 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
3a03eb79
AV		 6312 /*
6313 * Firmware will apply the following mask if the nodename was
6314 * not provided.
6315 */
6316 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
6317 icb->node_name[0] &= 0xF0;
6318 }
6319
6320 /* Set host adapter parameters. */
6321 ha->flags.disable_risc_code_load = 0;
6322 ha->flags.enable_lip_reset = 0;
6323 ha->flags.enable_lip_full_login =
6324 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
6325 ha->flags.enable_target_reset =
6326 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
6327 ha->flags.enable_led_scheme = 0;
6328 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
6329
6330 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
6331 (BIT_6 | BIT_5 | BIT_4)) >> 4;
6332
6333 /* save HBA serial number */
6334 ha->serial0 = icb->port_name[5];
6335 ha->serial1 = icb->port_name[6];
6336 ha->serial2 = icb->port_name[7];
6337 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
6338 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
6339
ad950360 6340 icb->execution_throttle = cpu_to_le16(0xFFFF);
3a03eb79
AV		 6341
6342 ha->retry_count = le16_to_cpu(nv->login_retry_count);
6343
6344 /* Set minimum login_timeout to 4 seconds. */
6345 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
6346 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
6347 if (le16_to_cpu(nv->login_timeout) < 4)
ad950360 6348 nv->login_timeout = cpu_to_le16(4);
3a03eb79 6349 ha->login_timeout = le16_to_cpu(nv->login_timeout);
3a03eb79
AV		 6350
6351 /* Set minimum RATOV to 100 tenths of a second. */
6352 ha->r_a_tov = 100;
6353
6354 ha->loop_reset_delay = nv->reset_delay;
6355
6356 /* Link Down Timeout = 0:
6357 *
7ec0effd 6358 * When Port Down timer expires we will start returning
3a03eb79
AV		 6359 * I/O's to OS with "DID_NO_CONNECT".
6360 *
6361 * Link Down Timeout != 0:
6362 *
6363 * The driver waits for the link to come up after link down
6364 * before returning I/Os to OS with "DID_NO_CONNECT".
6365 */
6366 if (le16_to_cpu(nv->link_down_timeout) == 0) {
6367 ha->loop_down_abort_time =
6368 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
6369 } else {
6370 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
6371 ha->loop_down_abort_time =
6372 (LOOP_DOWN_TIME - ha->link_down_timeout);
6373 }
6374
6375 /* Need enough time to try and get the port back. */
6376 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
6377 if (qlport_down_retry)
6378 ha->port_down_retry_count = qlport_down_retry;
6379
6380 /* Set login_retry_count */
6381 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
6382 if (ha->port_down_retry_count ==
6383 le16_to_cpu(nv->port_down_retry_count) &&
6384 ha->port_down_retry_count > 3)
6385 ha->login_retry_count = ha->port_down_retry_count;
6386 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
6387 ha->login_retry_count = ha->port_down_retry_count;
6388 if (ql2xloginretrycount)
6389 ha->login_retry_count = ql2xloginretrycount;
6390
6246b8a1 6391 /* if not running MSI-X we need handshaking on interrupts */
f73cb695 6392 if (!vha->hw->flags.msix_enabled && (IS_QLA83XX(ha) || IS_QLA27XX(ha)))
ad950360 6393 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
6246b8a1 6394
3a03eb79
AV		 6395 /* Enable ZIO. */
6396 if (!vha->flags.init_done) {
6397 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
6398 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
6399 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
6400 le16_to_cpu(icb->interrupt_delay_timer): 2;
6401 }
ad950360 6402 icb->firmware_options_2 &= cpu_to_le32(
3a03eb79
AV		 6403 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
6404 vha->flags.process_response_queue = 0;
6405 if (ha->zio_mode != QLA_ZIO_DISABLED) {
6406 ha->zio_mode = QLA_ZIO_MODE_6;
6407
7c3df132 6408 ql_log(ql_log_info, vha, 0x0075,
3a03eb79 6409 "ZIO mode %d enabled; timer delay (%d us).\n",
7c3df132
SK		 6410 ha->zio_mode,
6411 ha->zio_timer * 100);
3a03eb79
AV		 6412
6413 icb->firmware_options_2 |= cpu_to_le32(
6414 (uint32_t)ha->zio_mode);
6415 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
6416 vha->flags.process_response_queue = 1;
6417 }
6418
6419 if (rval) {
7c3df132
SK		 6420 ql_log(ql_log_warn, vha, 0x0076,
6421 "NVRAM configuration failed.\n");
3a03eb79
AV		 6422 }
6423 return (rval);
6424}
6425
a9083016
GM		 6426int
6427qla82xx_restart_isp(scsi_qla_host_t *vha)
6428{
6429 int status, rval;
a9083016
GM		 6430 struct qla_hw_data *ha = vha->hw;
6431 struct req_que *req = ha->req_q_map[0];
6432 struct rsp_que *rsp = ha->rsp_q_map[0];
6433 struct scsi_qla_host *vp;
feafb7b1 6434 unsigned long flags;
a9083016
GM		 6435
6436 status = qla2x00_init_rings(vha);
6437 if (!status) {
6438 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
6439 ha->flags.chip_reset_done = 1;
6440
6441 status = qla2x00_fw_ready(vha);
6442 if (!status) {
a9083016
GM		 6443 /* Issue a marker after FW becomes ready. */
6444 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
a9083016 6445 vha->flags.online = 1;
7108b76e 6446 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
a9083016
GM		 6447 }
6448
6449 /* if no cable then assume it's good */
6450 if ((vha->device_flags & DFLG_NO_CABLE))
6451 status = 0;
a9083016
GM		 6452 }
6453
6454 if (!status) {
6455 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
6456
6457 if (!atomic_read(&vha->loop_down_timer)) {
6458 /*
6459 * Issue marker command only when we are going
6460 * to start the I/O .
6461 */
6462 vha->marker_needed = 1;
6463 }
6464
a9083016
GM		 6465 ha->isp_ops->enable_intrs(ha);
6466
6467 ha->isp_abort_cnt = 0;
6468 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
6469
53296788 6470 /* Update the firmware version */
3173167f 6471 status = qla82xx_check_md_needed(vha);
53296788 6472
a9083016
GM		 6473 if (ha->fce) {
6474 ha->flags.fce_enabled = 1;
6475 memset(ha->fce, 0,
6476 fce_calc_size(ha->fce_bufs));
6477 rval = qla2x00_enable_fce_trace(vha,
6478 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
6479 &ha->fce_bufs);
6480 if (rval) {
cfb0919c 6481 ql_log(ql_log_warn, vha, 0x8001,
7c3df132
SK		 6482 "Unable to reinitialize FCE (%d).\n",
6483 rval);
a9083016
GM		 6484 ha->flags.fce_enabled = 0;
6485 }
6486 }
6487
6488 if (ha->eft) {
6489 memset(ha->eft, 0, EFT_SIZE);
6490 rval = qla2x00_enable_eft_trace(vha,
6491 ha->eft_dma, EFT_NUM_BUFFERS);
6492 if (rval) {
cfb0919c 6493 ql_log(ql_log_warn, vha, 0x8010,
7c3df132
SK		 6494 "Unable to reinitialize EFT (%d).\n",
6495 rval);
a9083016
GM		 6496 }
6497 }
a9083016
GM		 6498 }
6499
6500 if (!status) {
cfb0919c 6501 ql_dbg(ql_dbg_taskm, vha, 0x8011,
7c3df132 6502 "qla82xx_restart_isp succeeded.\n");
feafb7b1
AE		 6503
6504 spin_lock_irqsave(&ha->vport_slock, flags);
6505 list_for_each_entry(vp, &ha->vp_list, list) {
6506 if (vp->vp_idx) {
6507 atomic_inc(&vp->vref_count);
6508 spin_unlock_irqrestore(&ha->vport_slock, flags);
6509
a9083016 6510 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 6511
6512 spin_lock_irqsave(&ha->vport_slock, flags);
6513 atomic_dec(&vp->vref_count);
6514 }
a9083016 6515 }
feafb7b1
AE		 6516 spin_unlock_irqrestore(&ha->vport_slock, flags);
6517
a9083016 6518 } else {
cfb0919c 6519 ql_log(ql_log_warn, vha, 0x8016,
7c3df132 6520 "qla82xx_restart_isp **** FAILED ****.\n");
a9083016
GM		 6521 }
6522
6523 return status;
6524}
6525
3a03eb79 6526void
ae97c91e 6527qla81xx_update_fw_options(scsi_qla_host_t *vha)
3a03eb79 6528{
ae97c91e
AV		 6529 struct qla_hw_data *ha = vha->hw;
6530
f198cafa
HM		 6531 /* Hold status IOCBs until ABTS response received. */
6532 if (ql2xfwholdabts)
6533 ha->fw_options[3] |= BIT_12;
6534
088d09d4
GM		 6535 /* Set Retry FLOGI in case of P2P connection */
6536 if (ha->operating_mode == P2P) {
6537 ha->fw_options[2] |= BIT_3;
6538 ql_dbg(ql_dbg_disc, vha, 0x2103,
6539 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
6540 __func__, ha->fw_options[2]);
6541 }
6542
ae97c91e 6543 if (!ql2xetsenable)
f198cafa 6544 goto out;
ae97c91e
AV		 6545
6546 /* Enable ETS Burst. */
6547 memset(ha->fw_options, 0, sizeof(ha->fw_options));
6548 ha->fw_options[2] |= BIT_9;
f198cafa 6549out:
ae97c91e 6550 qla2x00_set_fw_options(vha, ha->fw_options);
3a03eb79 6551}
09ff701a
SR		 6552
6553/*
6554 * qla24xx_get_fcp_prio
6555 * Gets the fcp cmd priority value for the logged in port.
6556 * Looks for a match of the port descriptors within
6557 * each of the fcp prio config entries. If a match is found,
6558 * the tag (priority) value is returned.
6559 *
6560 * Input:
21090cbe 6561 * vha = scsi host structure pointer.
09ff701a
SR		 6562 * fcport = port structure pointer.
6563 *
6564 * Return:
6c452a45 6565 * non-zero (if found)
f28a0a96 6566 * -1 (if not found)
09ff701a
SR		 6567 *
6568 * Context:
6569 * Kernel context
6570 */
f28a0a96 6571static int
09ff701a
SR		 6572qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
6573{
6574 int i, entries;
6575 uint8_t pid_match, wwn_match;
f28a0a96 6576 int priority;
09ff701a
SR		 6577 uint32_t pid1, pid2;
6578 uint64_t wwn1, wwn2;
6579 struct qla_fcp_prio_entry *pri_entry;
6580 struct qla_hw_data *ha = vha->hw;
6581
6582 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
f28a0a96 6583 return -1;
09ff701a 6584
f28a0a96 6585 priority = -1;
09ff701a
SR		 6586 entries = ha->fcp_prio_cfg->num_entries;
6587 pri_entry = &ha->fcp_prio_cfg->entry[0];
6588
6589 for (i = 0; i < entries; i++) {
6590 pid_match = wwn_match = 0;
6591
6592 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
6593 pri_entry++;
6594 continue;
6595 }
6596
6597 /* check source pid for a match */
6598 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
6599 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
6600 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
6601 if (pid1 == INVALID_PORT_ID)
6602 pid_match++;
6603 else if (pid1 == pid2)
6604 pid_match++;
6605 }
6606
6607 /* check destination pid for a match */
6608 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
6609 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
6610 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
6611 if (pid1 == INVALID_PORT_ID)
6612 pid_match++;
6613 else if (pid1 == pid2)
6614 pid_match++;
6615 }
6616
6617 /* check source WWN for a match */
6618 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
6619 wwn1 = wwn_to_u64(vha->port_name);
6620 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
6621 if (wwn2 == (uint64_t)-1)
6622 wwn_match++;
6623 else if (wwn1 == wwn2)
6624 wwn_match++;
6625 }
6626
6627 /* check destination WWN for a match */
6628 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
6629 wwn1 = wwn_to_u64(fcport->port_name);
6630 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
6631 if (wwn2 == (uint64_t)-1)
6632 wwn_match++;
6633 else if (wwn1 == wwn2)
6634 wwn_match++;
6635 }
6636
6637 if (pid_match == 2 || wwn_match == 2) {
6638 /* Found a matching entry */
6639 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
6640 priority = pri_entry->tag;
6641 break;
6642 }
6643
6644 pri_entry++;
6645 }
6646
6647 return priority;
6648}
6649
6650/*
6651 * qla24xx_update_fcport_fcp_prio
6652 * Activates fcp priority for the logged in fc port
6653 *
6654 * Input:
21090cbe 6655 * vha = scsi host structure pointer.
09ff701a
SR		 6656 * fcp = port structure pointer.
6657 *
6658 * Return:
6659 * QLA_SUCCESS or QLA_FUNCTION_FAILED
6660 *
6661 * Context:
6662 * Kernel context.
6663 */
6664int
21090cbe 6665qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
09ff701a
SR		 6666{
6667 int ret;
f28a0a96 6668 int priority;
09ff701a
SR		 6669 uint16_t mb[5];
6670
21090cbe
MI		 6671 if (fcport->port_type != FCT_TARGET ||
6672 fcport->loop_id == FC_NO_LOOP_ID)
09ff701a
SR		 6673 return QLA_FUNCTION_FAILED;
6674
21090cbe 6675 priority = qla24xx_get_fcp_prio(vha, fcport);
f28a0a96
AV		 6676 if (priority < 0)
6677 return QLA_FUNCTION_FAILED;
6678
7ec0effd 6679 if (IS_P3P_TYPE(vha->hw)) {
a00f6296
SK		 6680 fcport->fcp_prio = priority & 0xf;
6681 return QLA_SUCCESS;
6682 }
6683
21090cbe 6684 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
cfb0919c
CD		 6685 if (ret == QLA_SUCCESS) {
6686 if (fcport->fcp_prio != priority)
6687 ql_dbg(ql_dbg_user, vha, 0x709e,
6688 "Updated FCP_CMND priority - value=%d loop_id=%d "
6689 "port_id=%02x%02x%02x.\n", priority,
6690 fcport->loop_id, fcport->d_id.b.domain,
6691 fcport->d_id.b.area, fcport->d_id.b.al_pa);
a00f6296 6692 fcport->fcp_prio = priority & 0xf;
cfb0919c 6693 } else
7c3df132 6694 ql_dbg(ql_dbg_user, vha, 0x704f,
cfb0919c
CD		 6695 "Unable to update FCP_CMND priority - ret=0x%x for "
6696 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
6697 fcport->d_id.b.domain, fcport->d_id.b.area,
6698 fcport->d_id.b.al_pa);
09ff701a
SR		 6699 return ret;
6700}
6701
6702/*
6703 * qla24xx_update_all_fcp_prio
6704 * Activates fcp priority for all the logged in ports
6705 *
6706 * Input:
6707 * ha = adapter block pointer.
6708 *
6709 * Return:
6710 * QLA_SUCCESS or QLA_FUNCTION_FAILED
6711 *
6712 * Context:
6713 * Kernel context.
6714 */
6715int
6716qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
6717{
6718 int ret;
6719 fc_port_t *fcport;
6720
6721 ret = QLA_FUNCTION_FAILED;
6722 /* We need to set priority for all logged in ports */
6723 list_for_each_entry(fcport, &vha->vp_fcports, list)
6724 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
6725
6726 return ret;
6727}
Linux kernel - Deliverables
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