projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
qla2xxx: Declaration error cause stack corruption.
[deliverable/linux.git] / drivers / scsi / qla2xxx / qla_init.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
73208dfd 8#include "qla_gbl.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/slab.h>
0107109e 12#include <linux/vmalloc.h>
1da177e4
LT		 13
14#include "qla_devtbl.h"
15
4e08df3f
DM		 16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
4e08df3f
DM		 18#endif
19
2d70c103
NB		 20#include <target/target_core_base.h>
21#include "qla_target.h"
22
1da177e4
LT		 23/*
24* QLogic ISP2x00 Hardware Support Function Prototypes.
25*/
1da177e4 26static int qla2x00_isp_firmware(scsi_qla_host_t *);
1da177e4 27static int qla2x00_setup_chip(scsi_qla_host_t *);
1da177e4
LT		 28static int qla2x00_fw_ready(scsi_qla_host_t *);
29static int qla2x00_configure_hba(scsi_qla_host_t *);
1da177e4
LT		 30static int qla2x00_configure_loop(scsi_qla_host_t *);
31static int qla2x00_configure_local_loop(scsi_qla_host_t *);
1da177e4
LT		 32static int qla2x00_configure_fabric(scsi_qla_host_t *);
33static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *);
1da177e4
LT		 34static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
35 uint16_t *);
1da177e4
LT		 36
37static int qla2x00_restart_isp(scsi_qla_host_t *);
1da177e4 38
4d4df193
HK		 39static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
40static int qla84xx_init_chip(scsi_qla_host_t *);
73208dfd 41static int qla25xx_init_queues(struct qla_hw_data *);
4d4df193 42
ac280b67
AV		 43/* SRB Extensions ---------------------------------------------------------- */
44
9ba56b95
GM		 45void
46qla2x00_sp_timeout(unsigned long __data)
ac280b67
AV		 47{
48 srb_t *sp = (srb_t *)__data;
4916392b 49 struct srb_iocb *iocb;
ac280b67
AV		 50 fc_port_t *fcport = sp->fcport;
51 struct qla_hw_data *ha = fcport->vha->hw;
52 struct req_que *req;
53 unsigned long flags;
54
55 spin_lock_irqsave(&ha->hardware_lock, flags);
56 req = ha->req_q_map[0];
57 req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 58 iocb = &sp->u.iocb_cmd;
4916392b 59 iocb->timeout(sp);
9ba56b95 60 sp->free(fcport->vha, sp);
6ac52608 61 spin_unlock_irqrestore(&ha->hardware_lock, flags);
ac280b67
AV		 62}
63
9ba56b95
GM		 64void
65qla2x00_sp_free(void *data, void *ptr)
ac280b67 66{
9ba56b95
GM		 67 srb_t *sp = (srb_t *)ptr;
68 struct srb_iocb *iocb = &sp->u.iocb_cmd;
69 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
ac280b67 70
4d97cc53 71 del_timer(&iocb->timer);
b00ee7d7 72 qla2x00_rel_sp(vha, sp);
ac280b67
AV		 73}
74
ac280b67
AV		 75/* Asynchronous Login/Logout Routines -------------------------------------- */
76
a9b6f722 77unsigned long
5b91490e
AV		 78qla2x00_get_async_timeout(struct scsi_qla_host *vha)
79{
80 unsigned long tmo;
81 struct qla_hw_data *ha = vha->hw;
82
83 /* Firmware should use switch negotiated r_a_tov for timeout. */
84 tmo = ha->r_a_tov / 10 * 2;
8ae6d9c7
GM		 85 if (IS_QLAFX00(ha)) {
86 tmo = FX00_DEF_RATOV * 2;
87 } else if (!IS_FWI2_CAPABLE(ha)) {
5b91490e
AV		 88 /*
89 * Except for earlier ISPs where the timeout is seeded from the
90 * initialization control block.
91 */
92 tmo = ha->login_timeout;
93 }
94 return tmo;
95}
ac280b67
AV		 96
97static void
9ba56b95 98qla2x00_async_iocb_timeout(void *data)
ac280b67 99{
9ba56b95 100 srb_t *sp = (srb_t *)data;
ac280b67 101 fc_port_t *fcport = sp->fcport;
ac280b67 102
7c3df132 103 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
cfb0919c 104 "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n",
9ba56b95 105 sp->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area,
7c3df132 106 fcport->d_id.b.al_pa);
ac280b67 107
5ff1d584 108 fcport->flags &= ~FCF_ASYNC_SENT;
9ba56b95
GM		 109 if (sp->type == SRB_LOGIN_CMD) {
110 struct srb_iocb *lio = &sp->u.iocb_cmd;
ac280b67 111 qla2x00_post_async_logout_work(fcport->vha, fcport, NULL);
6ac52608
AV		 112 /* Retry as needed. */
113 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
114 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
115 QLA_LOGIO_LOGIN_RETRIED : 0;
116 qla2x00_post_async_login_done_work(fcport->vha, fcport,
117 lio->u.logio.data);
118 }
ac280b67
AV		 119}
120
99b0bec7 121static void
9ba56b95 122qla2x00_async_login_sp_done(void *data, void *ptr, int res)
99b0bec7 123{
9ba56b95
GM		 124 srb_t *sp = (srb_t *)ptr;
125 struct srb_iocb *lio = &sp->u.iocb_cmd;
126 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
127
128 if (!test_bit(UNLOADING, &vha->dpc_flags))
129 qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport,
130 lio->u.logio.data);
131 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 132}
133
ac280b67
AV		 134int
135qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
136 uint16_t *data)
137{
ac280b67 138 srb_t *sp;
4916392b 139 struct srb_iocb *lio;
ac280b67
AV		 140 int rval;
141
142 rval = QLA_FUNCTION_FAILED;
9ba56b95 143 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 144 if (!sp)
145 goto done;
146
9ba56b95
GM		 147 sp->type = SRB_LOGIN_CMD;
148 sp->name = "login";
149 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
150
151 lio = &sp->u.iocb_cmd;
3822263e 152 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 153 sp->done = qla2x00_async_login_sp_done;
4916392b 154 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
ac280b67 155 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 156 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
ac280b67
AV		 157 rval = qla2x00_start_sp(sp);
158 if (rval != QLA_SUCCESS)
159 goto done_free_sp;
160
7c3df132 161 ql_dbg(ql_dbg_disc, vha, 0x2072,
cfb0919c
CD		 162 "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x "
163 "retries=%d.\n", sp->handle, fcport->loop_id,
164 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
165 fcport->login_retry);
ac280b67
AV		 166 return rval;
167
168done_free_sp:
9ba56b95 169 sp->free(fcport->vha, sp);
ac280b67
AV		 170done:
171 return rval;
172}
173
99b0bec7 174static void
9ba56b95 175qla2x00_async_logout_sp_done(void *data, void *ptr, int res)
99b0bec7 176{
9ba56b95
GM		 177 srb_t *sp = (srb_t *)ptr;
178 struct srb_iocb *lio = &sp->u.iocb_cmd;
179 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
180
181 if (!test_bit(UNLOADING, &vha->dpc_flags))
182 qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport,
183 lio->u.logio.data);
184 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 185}
186
ac280b67
AV		 187int
188qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
189{
ac280b67 190 srb_t *sp;
4916392b 191 struct srb_iocb *lio;
ac280b67
AV		 192 int rval;
193
194 rval = QLA_FUNCTION_FAILED;
9ba56b95 195 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 196 if (!sp)
197 goto done;
198
9ba56b95
GM		 199 sp->type = SRB_LOGOUT_CMD;
200 sp->name = "logout";
201 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
202
203 lio = &sp->u.iocb_cmd;
3822263e 204 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 205 sp->done = qla2x00_async_logout_sp_done;
ac280b67
AV		 206 rval = qla2x00_start_sp(sp);
207 if (rval != QLA_SUCCESS)
208 goto done_free_sp;
209
7c3df132 210 ql_dbg(ql_dbg_disc, vha, 0x2070,
cfb0919c
CD		 211 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
212 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
213 fcport->d_id.b.area, fcport->d_id.b.al_pa);
ac280b67
AV		 214 return rval;
215
216done_free_sp:
9ba56b95 217 sp->free(fcport->vha, sp);
ac280b67
AV		 218done:
219 return rval;
220}
221
5ff1d584 222static void
9ba56b95 223qla2x00_async_adisc_sp_done(void *data, void *ptr, int res)
5ff1d584 224{
9ba56b95
GM		 225 srb_t *sp = (srb_t *)ptr;
226 struct srb_iocb *lio = &sp->u.iocb_cmd;
227 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
228
229 if (!test_bit(UNLOADING, &vha->dpc_flags))
230 qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport,
231 lio->u.logio.data);
232 sp->free(sp->fcport->vha, sp);
5ff1d584
AV		 233}
234
235int
236qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
237 uint16_t *data)
238{
5ff1d584 239 srb_t *sp;
4916392b 240 struct srb_iocb *lio;
5ff1d584
AV		 241 int rval;
242
243 rval = QLA_FUNCTION_FAILED;
9ba56b95 244 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
5ff1d584
AV		 245 if (!sp)
246 goto done;
247
9ba56b95
GM		 248 sp->type = SRB_ADISC_CMD;
249 sp->name = "adisc";
250 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
251
252 lio = &sp->u.iocb_cmd;
3822263e 253 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 254 sp->done = qla2x00_async_adisc_sp_done;
5ff1d584 255 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 256 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
5ff1d584
AV		 257 rval = qla2x00_start_sp(sp);
258 if (rval != QLA_SUCCESS)
259 goto done_free_sp;
260
7c3df132 261 ql_dbg(ql_dbg_disc, vha, 0x206f,
cfb0919c
CD		 262 "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
263 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
264 fcport->d_id.b.area, fcport->d_id.b.al_pa);
5ff1d584
AV		 265 return rval;
266
267done_free_sp:
9ba56b95 268 sp->free(fcport->vha, sp);
5ff1d584
AV		 269done:
270 return rval;
271}
272
3822263e 273static void
faef62d1 274qla2x00_tmf_iocb_timeout(void *data)
3822263e 275{
faef62d1
AB		 276 srb_t *sp = (srb_t *)data;
277 struct srb_iocb *tmf = &sp->u.iocb_cmd;
3822263e 278
faef62d1
AB		 279 tmf->u.tmf.comp_status = CS_TIMEOUT;
280 complete(&tmf->u.tmf.comp);
281}
9ba56b95 282
faef62d1
AB		 283static void
284qla2x00_tmf_sp_done(void *data, void *ptr, int res)
285{
286 srb_t *sp = (srb_t *)ptr;
287 struct srb_iocb *tmf = &sp->u.iocb_cmd;
288 complete(&tmf->u.tmf.comp);
3822263e
MI		 289}
290
291int
faef62d1 292qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun,
3822263e
MI		 293 uint32_t tag)
294{
295 struct scsi_qla_host *vha = fcport->vha;
faef62d1 296 struct srb_iocb *tm_iocb;
3822263e 297 srb_t *sp;
faef62d1 298 int rval = QLA_FUNCTION_FAILED;
3822263e 299
9ba56b95 300 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
3822263e
MI		 301 if (!sp)
302 goto done;
303
faef62d1 304 tm_iocb = &sp->u.iocb_cmd;
9ba56b95
GM		 305 sp->type = SRB_TM_CMD;
306 sp->name = "tmf";
faef62d1
AB		 307 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
308 tm_iocb->u.tmf.flags = flags;
309 tm_iocb->u.tmf.lun = lun;
310 tm_iocb->u.tmf.data = tag;
311 sp->done = qla2x00_tmf_sp_done;
312 tm_iocb->timeout = qla2x00_tmf_iocb_timeout;
313 init_completion(&tm_iocb->u.tmf.comp);
3822263e
MI		 314
315 rval = qla2x00_start_sp(sp);
316 if (rval != QLA_SUCCESS)
317 goto done_free_sp;
318
7c3df132 319 ql_dbg(ql_dbg_taskm, vha, 0x802f,
cfb0919c
CD		 320 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
321 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
322 fcport->d_id.b.area, fcport->d_id.b.al_pa);
faef62d1
AB		 323
324 wait_for_completion(&tm_iocb->u.tmf.comp);
325
326 rval = tm_iocb->u.tmf.comp_status == CS_COMPLETE ?
327 QLA_SUCCESS : QLA_FUNCTION_FAILED;
328
329 if ((rval != QLA_SUCCESS) || tm_iocb->u.tmf.data) {
330 ql_dbg(ql_dbg_taskm, vha, 0x8030,
331 "TM IOCB failed (%x).\n", rval);
332 }
333
334 if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) {
335 flags = tm_iocb->u.tmf.flags;
336 lun = (uint16_t)tm_iocb->u.tmf.lun;
337
338 /* Issue Marker IOCB */
339 qla2x00_marker(vha, vha->hw->req_q_map[0],
340 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
341 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
342 }
3822263e
MI		 343
344done_free_sp:
faef62d1 345 sp->free(vha, sp);
3822263e
MI		 346done:
347 return rval;
348}
349
4440e46d
AB		 350static void
351qla24xx_abort_iocb_timeout(void *data)
352{
353 srb_t *sp = (srb_t *)data;
354 struct srb_iocb *abt = &sp->u.iocb_cmd;
355
356 abt->u.abt.comp_status = CS_TIMEOUT;
357 complete(&abt->u.abt.comp);
358}
359
360static void
361qla24xx_abort_sp_done(void *data, void *ptr, int res)
362{
363 srb_t *sp = (srb_t *)ptr;
364 struct srb_iocb *abt = &sp->u.iocb_cmd;
365
366 complete(&abt->u.abt.comp);
367}
368
369static int
370qla24xx_async_abort_cmd(srb_t *cmd_sp)
371{
372 scsi_qla_host_t *vha = cmd_sp->fcport->vha;
373 fc_port_t *fcport = cmd_sp->fcport;
374 struct srb_iocb *abt_iocb;
375 srb_t *sp;
376 int rval = QLA_FUNCTION_FAILED;
377
378 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
379 if (!sp)
380 goto done;
381
382 abt_iocb = &sp->u.iocb_cmd;
383 sp->type = SRB_ABT_CMD;
384 sp->name = "abort";
385 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
386 abt_iocb->u.abt.cmd_hndl = cmd_sp->handle;
387 sp->done = qla24xx_abort_sp_done;
388 abt_iocb->timeout = qla24xx_abort_iocb_timeout;
389 init_completion(&abt_iocb->u.abt.comp);
390
391 rval = qla2x00_start_sp(sp);
392 if (rval != QLA_SUCCESS)
393 goto done_free_sp;
394
395 ql_dbg(ql_dbg_async, vha, 0x507c,
396 "Abort command issued - hdl=%x, target_id=%x\n",
397 cmd_sp->handle, fcport->tgt_id);
398
399 wait_for_completion(&abt_iocb->u.abt.comp);
400
401 rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ?
402 QLA_SUCCESS : QLA_FUNCTION_FAILED;
403
404done_free_sp:
405 sp->free(vha, sp);
406done:
407 return rval;
408}
409
410int
411qla24xx_async_abort_command(srb_t *sp)
412{
413 unsigned long flags = 0;
414
415 uint32_t handle;
416 fc_port_t *fcport = sp->fcport;
417 struct scsi_qla_host *vha = fcport->vha;
418 struct qla_hw_data *ha = vha->hw;
419 struct req_que *req = vha->req;
420
421 spin_lock_irqsave(&ha->hardware_lock, flags);
422 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
423 if (req->outstanding_cmds[handle] == sp)
424 break;
425 }
426 spin_unlock_irqrestore(&ha->hardware_lock, flags);
427 if (handle == req->num_outstanding_cmds) {
428 /* Command not found. */
429 return QLA_FUNCTION_FAILED;
430 }
431 if (sp->type == SRB_FXIOCB_DCMD)
432 return qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
433 FXDISC_ABORT_IOCTL);
434
435 return qla24xx_async_abort_cmd(sp);
436}
437
4916392b 438void
ac280b67
AV		 439qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport,
440 uint16_t *data)
441{
442 int rval;
ac280b67
AV		 443
444 switch (data[0]) {
445 case MBS_COMMAND_COMPLETE:
a4f92a32
AV		 446 /*
447 * Driver must validate login state - If PRLI not complete,
448 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
449 * requests.
450 */
451 rval = qla2x00_get_port_database(vha, fcport, 0);
0eba25df
AE		 452 if (rval == QLA_NOT_LOGGED_IN) {
453 fcport->flags &= ~FCF_ASYNC_SENT;
454 fcport->flags |= FCF_LOGIN_NEEDED;
455 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
456 break;
457 }
458
a4f92a32
AV		 459 if (rval != QLA_SUCCESS) {
460 qla2x00_post_async_logout_work(vha, fcport, NULL);
461 qla2x00_post_async_login_work(vha, fcport, NULL);
462 break;
463 }
99b0bec7 464 if (fcport->flags & FCF_FCP2_DEVICE) {
5ff1d584
AV		 465 qla2x00_post_async_adisc_work(vha, fcport, data);
466 break;
99b0bec7
AV		 467 }
468 qla2x00_update_fcport(vha, fcport);
ac280b67
AV		 469 break;
470 case MBS_COMMAND_ERROR:
5ff1d584 471 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 472 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
473 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
474 else
80d79440 475 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 476 break;
477 case MBS_PORT_ID_USED:
478 fcport->loop_id = data[1];
6ac52608 479 qla2x00_post_async_logout_work(vha, fcport, NULL);
ac280b67
AV		 480 qla2x00_post_async_login_work(vha, fcport, NULL);
481 break;
482 case MBS_LOOP_ID_USED:
483 fcport->loop_id++;
484 rval = qla2x00_find_new_loop_id(vha, fcport);
485 if (rval != QLA_SUCCESS) {
5ff1d584 486 fcport->flags &= ~FCF_ASYNC_SENT;
80d79440 487 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 488 break;
489 }
490 qla2x00_post_async_login_work(vha, fcport, NULL);
491 break;
492 }
4916392b 493 return;
ac280b67
AV		 494}
495
4916392b 496void
ac280b67
AV		 497qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
498 uint16_t *data)
499{
500 qla2x00_mark_device_lost(vha, fcport, 1, 0);
4916392b 501 return;
ac280b67
AV		 502}
503
4916392b 504void
5ff1d584
AV		 505qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
506 uint16_t *data)
507{
508 if (data[0] == MBS_COMMAND_COMPLETE) {
509 qla2x00_update_fcport(vha, fcport);
510
4916392b 511 return;
5ff1d584
AV		 512 }
513
514 /* Retry login. */
515 fcport->flags &= ~FCF_ASYNC_SENT;
516 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
517 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
518 else
80d79440 519 qla2x00_mark_device_lost(vha, fcport, 1, 0);
5ff1d584 520
4916392b 521 return;
5ff1d584
AV		 522}
523
1da177e4
LT		 524/****************************************************************************/
525/* QLogic ISP2x00 Hardware Support Functions. */
526/****************************************************************************/
527
fa492630 528static int
7d613ac6
SV		 529qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
530{
531 int rval = QLA_SUCCESS;
532 struct qla_hw_data *ha = vha->hw;
533 uint32_t idc_major_ver, idc_minor_ver;
711aa7f7 534 uint16_t config[4];
7d613ac6
SV		 535
536 qla83xx_idc_lock(vha, 0);
537
538 /* SV: TODO: Assign initialization timeout from
539 * flash-info / other param
540 */
541 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
542 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
543
544 /* Set our fcoe function presence */
545 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
546 ql_dbg(ql_dbg_p3p, vha, 0xb077,
547 "Error while setting DRV-Presence.\n");
548 rval = QLA_FUNCTION_FAILED;
549 goto exit;
550 }
551
552 /* Decide the reset ownership */
553 qla83xx_reset_ownership(vha);
554
555 /*
556 * On first protocol driver load:
557 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
558 * register.
559 * Others: Check compatibility with current IDC Major version.
560 */
561 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
562 if (ha->flags.nic_core_reset_owner) {
563 /* Set IDC Major version */
564 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
565 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
566
567 /* Clearing IDC-Lock-Recovery register */
568 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
569 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
570 /*
571 * Clear further IDC participation if we are not compatible with
572 * the current IDC Major Version.
573 */
574 ql_log(ql_log_warn, vha, 0xb07d,
575 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
576 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
577 __qla83xx_clear_drv_presence(vha);
578 rval = QLA_FUNCTION_FAILED;
579 goto exit;
580 }
581 /* Each function sets its supported Minor version. */
582 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
583 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
584 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
585
711aa7f7
SK		 586 if (ha->flags.nic_core_reset_owner) {
587 memset(config, 0, sizeof(config));
588 if (!qla81xx_get_port_config(vha, config))
589 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
590 QLA8XXX_DEV_READY);
591 }
592
7d613ac6
SV		 593 rval = qla83xx_idc_state_handler(vha);
594
595exit:
596 qla83xx_idc_unlock(vha, 0);
597
598 return rval;
599}
600
1da177e4
LT		 601/*
602* qla2x00_initialize_adapter
603* Initialize board.
604*
605* Input:
606* ha = adapter block pointer.
607*
608* Returns:
609* 0 = success
610*/
611int
e315cd28 612qla2x00_initialize_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 613{
614 int rval;
e315cd28 615 struct qla_hw_data *ha = vha->hw;
73208dfd 616 struct req_que *req = ha->req_q_map[0];
2533cf67 617
1da177e4 618 /* Clear adapter flags. */
e315cd28 619 vha->flags.online = 0;
2533cf67 620 ha->flags.chip_reset_done = 0;
e315cd28 621 vha->flags.reset_active = 0;
85880801
AV		 622 ha->flags.pci_channel_io_perm_failure = 0;
623 ha->flags.eeh_busy = 0;
fabbb8df 624 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64();
e315cd28
AC		 625 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
626 atomic_set(&vha->loop_state, LOOP_DOWN);
627 vha->device_flags = DFLG_NO_CABLE;
628 vha->dpc_flags = 0;
629 vha->flags.management_server_logged_in = 0;
630 vha->marker_needed = 0;
1da177e4
LT		 631 ha->isp_abort_cnt = 0;
632 ha->beacon_blink_led = 0;
633
73208dfd
AC		 634 set_bit(0, ha->req_qid_map);
635 set_bit(0, ha->rsp_qid_map);
636
cfb0919c 637 ql_dbg(ql_dbg_init, vha, 0x0040,
7c3df132 638 "Configuring PCI space...\n");
e315cd28 639 rval = ha->isp_ops->pci_config(vha);
1da177e4 640 if (rval) {
7c3df132
SK		 641 ql_log(ql_log_warn, vha, 0x0044,
642 "Unable to configure PCI space.\n");
1da177e4
LT		 643 return (rval);
644 }
645
e315cd28 646 ha->isp_ops->reset_chip(vha);
1da177e4 647
e315cd28 648 rval = qla2xxx_get_flash_info(vha);
c00d8994 649 if (rval) {
7c3df132
SK		 650 ql_log(ql_log_fatal, vha, 0x004f,
651 "Unable to validate FLASH data.\n");
7ec0effd
AD		 652 return rval;
653 }
654
655 if (IS_QLA8044(ha)) {
656 qla8044_read_reset_template(vha);
657
658 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0.
659 * If DONRESET_BIT0 is set, drivers should not set dev_state
660 * to NEED_RESET. But if NEED_RESET is set, drivers should
661 * should honor the reset. */
662 if (ql2xdontresethba == 1)
663 qla8044_set_idc_dontreset(vha);
c00d8994
AV		 664 }
665
73208dfd 666 ha->isp_ops->get_flash_version(vha, req->ring);
cfb0919c 667 ql_dbg(ql_dbg_init, vha, 0x0061,
7c3df132 668 "Configure NVRAM parameters...\n");
0107109e 669
e315cd28 670 ha->isp_ops->nvram_config(vha);
1da177e4 671
d4c760c2
AV		 672 if (ha->flags.disable_serdes) {
673 /* Mask HBA via NVRAM settings? */
7c3df132 674 ql_log(ql_log_info, vha, 0x0077,
7b833558 675 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name);
d4c760c2
AV		 676 return QLA_FUNCTION_FAILED;
677 }
678
cfb0919c 679 ql_dbg(ql_dbg_init, vha, 0x0078,
7c3df132 680 "Verifying loaded RISC code...\n");
1da177e4 681
e315cd28
AC		 682 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
683 rval = ha->isp_ops->chip_diag(vha);
d19044c3
AV		 684 if (rval)
685 return (rval);
e315cd28 686 rval = qla2x00_setup_chip(vha);
d19044c3
AV		 687 if (rval)
688 return (rval);
1da177e4 689 }
a9083016 690
4d4df193 691 if (IS_QLA84XX(ha)) {
e315cd28 692 ha->cs84xx = qla84xx_get_chip(vha);
4d4df193 693 if (!ha->cs84xx) {
7c3df132 694 ql_log(ql_log_warn, vha, 0x00d0,
4d4df193
HK		 695 "Unable to configure ISP84XX.\n");
696 return QLA_FUNCTION_FAILED;
697 }
698 }
2d70c103
NB		 699
700 if (qla_ini_mode_enabled(vha))
701 rval = qla2x00_init_rings(vha);
702
2533cf67 703 ha->flags.chip_reset_done = 1;
1da177e4 704
9a069e19 705 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
6c452a45 706 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
9a069e19
GM		 707 rval = qla84xx_init_chip(vha);
708 if (rval != QLA_SUCCESS) {
7c3df132
SK		 709 ql_log(ql_log_warn, vha, 0x00d4,
710 "Unable to initialize ISP84XX.\n");
9a069e19
GM		 711 qla84xx_put_chip(vha);
712 }
713 }
714
7d613ac6
SV		 715 /* Load the NIC Core f/w if we are the first protocol driver. */
716 if (IS_QLA8031(ha)) {
717 rval = qla83xx_nic_core_fw_load(vha);
718 if (rval)
719 ql_log(ql_log_warn, vha, 0x0124,
720 "Error in initializing NIC Core f/w.\n");
721 }
722
2f0f3f4f
MI		 723 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
724 qla24xx_read_fcp_prio_cfg(vha);
09ff701a 725
c46e65c7
JC		 726 if (IS_P3P_TYPE(ha))
727 qla82xx_set_driver_version(vha, QLA2XXX_VERSION);
728 else
729 qla25xx_set_driver_version(vha, QLA2XXX_VERSION);
730
1da177e4
LT		 731 return (rval);
732}
733
734/**
abbd8870 735 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
1da177e4
LT		 736 * @ha: HA context
737 *
738 * Returns 0 on success.
739 */
abbd8870 740int
e315cd28 741qla2100_pci_config(scsi_qla_host_t *vha)
1da177e4 742{
a157b101 743 uint16_t w;
abbd8870 744 unsigned long flags;
e315cd28 745 struct qla_hw_data *ha = vha->hw;
3d71644c 746 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 747
1da177e4 748 pci_set_master(ha->pdev);
af6177d8 749 pci_try_set_mwi(ha->pdev);
1da177e4 750
1da177e4 751 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 752 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
abbd8870
AV		 753 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
754
737faece 755 pci_disable_rom(ha->pdev);
1da177e4
LT		 756
757 /* Get PCI bus information. */
758 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 759 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
1da177e4
LT		 760 spin_unlock_irqrestore(&ha->hardware_lock, flags);
761
abbd8870
AV		 762 return QLA_SUCCESS;
763}
1da177e4 764
abbd8870
AV		 765/**
766 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
767 * @ha: HA context
768 *
769 * Returns 0 on success.
770 */
771int
e315cd28 772qla2300_pci_config(scsi_qla_host_t *vha)
abbd8870 773{
a157b101 774 uint16_t w;
abbd8870
AV		 775 unsigned long flags = 0;
776 uint32_t cnt;
e315cd28 777 struct qla_hw_data *ha = vha->hw;
3d71644c 778 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 779
abbd8870 780 pci_set_master(ha->pdev);
af6177d8 781 pci_try_set_mwi(ha->pdev);
1da177e4 782
abbd8870 783 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 784 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1da177e4 785
abbd8870
AV		 786 if (IS_QLA2322(ha) || IS_QLA6322(ha))
787 w &= ~PCI_COMMAND_INTX_DISABLE;
a157b101 788 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1da177e4 789
abbd8870
AV		 790 /*
791 * If this is a 2300 card and not 2312, reset the
792 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
793 * the 2310 also reports itself as a 2300 so we need to get the
794 * fb revision level -- a 6 indicates it really is a 2300 and
795 * not a 2310.
796 */
797 if (IS_QLA2300(ha)) {
798 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 799
abbd8870 800 /* Pause RISC. */
3d71644c 801 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
abbd8870 802 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 803 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
abbd8870 804 break;
1da177e4 805
abbd8870
AV		 806 udelay(10);
807 }
1da177e4 808
abbd8870 809 /* Select FPM registers. */
3d71644c
AV		 810 WRT_REG_WORD(&reg->ctrl_status, 0x20);
811 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 812
813 /* Get the fb rev level */
3d71644c 814 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
abbd8870
AV		 815
816 if (ha->fb_rev == FPM_2300)
a157b101 817 pci_clear_mwi(ha->pdev);
abbd8870
AV		 818
819 /* Deselect FPM registers. */
3d71644c
AV		 820 WRT_REG_WORD(&reg->ctrl_status, 0x0);
821 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 822
823 /* Release RISC module. */
3d71644c 824 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
abbd8870 825 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 826 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
abbd8870
AV		 827 break;
828
829 udelay(10);
1da177e4 830 }
1da177e4 831
abbd8870
AV		 832 spin_unlock_irqrestore(&ha->hardware_lock, flags);
833 }
1da177e4 834
abbd8870
AV		 835 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
836
737faece 837 pci_disable_rom(ha->pdev);
1da177e4 838
abbd8870
AV		 839 /* Get PCI bus information. */
840 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 841 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 842 spin_unlock_irqrestore(&ha->hardware_lock, flags);
843
844 return QLA_SUCCESS;
1da177e4
LT		 845}
846
0107109e
AV		 847/**
848 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
849 * @ha: HA context
850 *
851 * Returns 0 on success.
852 */
853int
e315cd28 854qla24xx_pci_config(scsi_qla_host_t *vha)
0107109e 855{
a157b101 856 uint16_t w;
0107109e 857 unsigned long flags = 0;
e315cd28 858 struct qla_hw_data *ha = vha->hw;
0107109e 859 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
0107109e
AV		 860
861 pci_set_master(ha->pdev);
af6177d8 862 pci_try_set_mwi(ha->pdev);
0107109e
AV		 863
864 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 865 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
0107109e
AV		 866 w &= ~PCI_COMMAND_INTX_DISABLE;
867 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
868
869 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
870
871 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
f85ec187
AV		 872 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
873 pcix_set_mmrbc(ha->pdev, 2048);
0107109e
AV		 874
875 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 876 if (pci_is_pcie(ha->pdev))
5ffd3a52 877 pcie_set_readrq(ha->pdev, 4096);
0107109e 878
737faece 879 pci_disable_rom(ha->pdev);
0107109e 880
44c10138 881 ha->chip_revision = ha->pdev->revision;
a8488abe 882
0107109e
AV		 883 /* Get PCI bus information. */
884 spin_lock_irqsave(&ha->hardware_lock, flags);
885 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
886 spin_unlock_irqrestore(&ha->hardware_lock, flags);
887
888 return QLA_SUCCESS;
889}
890
c3a2f0df
AV		 891/**
892 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
893 * @ha: HA context
894 *
895 * Returns 0 on success.
896 */
897int
e315cd28 898qla25xx_pci_config(scsi_qla_host_t *vha)
c3a2f0df
AV		 899{
900 uint16_t w;
e315cd28 901 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 902
903 pci_set_master(ha->pdev);
904 pci_try_set_mwi(ha->pdev);
905
906 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
907 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
908 w &= ~PCI_COMMAND_INTX_DISABLE;
909 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
910
911 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 912 if (pci_is_pcie(ha->pdev))
5ffd3a52 913 pcie_set_readrq(ha->pdev, 4096);
c3a2f0df 914
737faece 915 pci_disable_rom(ha->pdev);
c3a2f0df
AV		 916
917 ha->chip_revision = ha->pdev->revision;
918
919 return QLA_SUCCESS;
920}
921
1da177e4
LT		 922/**
923 * qla2x00_isp_firmware() - Choose firmware image.
924 * @ha: HA context
925 *
926 * Returns 0 on success.
927 */
928static int
e315cd28 929qla2x00_isp_firmware(scsi_qla_host_t *vha)
1da177e4
LT		 930{
931 int rval;
42e421b1
AV		 932 uint16_t loop_id, topo, sw_cap;
933 uint8_t domain, area, al_pa;
e315cd28 934 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 935
936 /* Assume loading risc code */
fa2a1ce5 937 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 938
939 if (ha->flags.disable_risc_code_load) {
7c3df132 940 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
1da177e4
LT		 941
942 /* Verify checksum of loaded RISC code. */
e315cd28 943 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
42e421b1
AV		 944 if (rval == QLA_SUCCESS) {
945 /* And, verify we are not in ROM code. */
e315cd28 946 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
42e421b1
AV		 947 &area, &domain, &topo, &sw_cap);
948 }
1da177e4
LT		 949 }
950
7c3df132
SK		 951 if (rval)
952 ql_dbg(ql_dbg_init, vha, 0x007a,
953 "**** Load RISC code ****.\n");
1da177e4
LT		 954
955 return (rval);
956}
957
958/**
959 * qla2x00_reset_chip() - Reset ISP chip.
960 * @ha: HA context
961 *
962 * Returns 0 on success.
963 */
abbd8870 964void
e315cd28 965qla2x00_reset_chip(scsi_qla_host_t *vha)
1da177e4
LT		 966{
967 unsigned long flags = 0;
e315cd28 968 struct qla_hw_data *ha = vha->hw;
3d71644c 969 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 970 uint32_t cnt;
1da177e4
LT		 971 uint16_t cmd;
972
85880801
AV		 973 if (unlikely(pci_channel_offline(ha->pdev)))
974 return;
975
fd34f556 976 ha->isp_ops->disable_intrs(ha);
1da177e4
LT		 977
978 spin_lock_irqsave(&ha->hardware_lock, flags);
979
980 /* Turn off master enable */
981 cmd = 0;
982 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
983 cmd &= ~PCI_COMMAND_MASTER;
984 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
985
986 if (!IS_QLA2100(ha)) {
987 /* Pause RISC. */
988 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
989 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
990 for (cnt = 0; cnt < 30000; cnt++) {
991 if ((RD_REG_WORD(&reg->hccr) &
992 HCCR_RISC_PAUSE) != 0)
993 break;
994 udelay(100);
995 }
996 } else {
997 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
998 udelay(10);
999 }
1000
1001 /* Select FPM registers. */
1002 WRT_REG_WORD(&reg->ctrl_status, 0x20);
1003 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1004
1005 /* FPM Soft Reset. */
1006 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
1007 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
1008
1009 /* Toggle Fpm Reset. */
1010 if (!IS_QLA2200(ha)) {
1011 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
1012 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
1013 }
1014
1015 /* Select frame buffer registers. */
1016 WRT_REG_WORD(&reg->ctrl_status, 0x10);
1017 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1018
1019 /* Reset frame buffer FIFOs. */
1020 if (IS_QLA2200(ha)) {
1021 WRT_FB_CMD_REG(ha, reg, 0xa000);
1022 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
1023 } else {
1024 WRT_FB_CMD_REG(ha, reg, 0x00fc);
1025
1026 /* Read back fb_cmd until zero or 3 seconds max */
1027 for (cnt = 0; cnt < 3000; cnt++) {
1028 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
1029 break;
1030 udelay(100);
1031 }
1032 }
1033
1034 /* Select RISC module registers. */
1035 WRT_REG_WORD(&reg->ctrl_status, 0);
1036 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1037
1038 /* Reset RISC processor. */
1039 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1040 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1041
1042 /* Release RISC processor. */
1043 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1044 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1045 }
1046
1047 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
1048 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
1049
1050 /* Reset ISP chip. */
1051 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1052
1053 /* Wait for RISC to recover from reset. */
1054 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1055 /*
1056 * It is necessary to for a delay here since the card doesn't
1057 * respond to PCI reads during a reset. On some architectures
1058 * this will result in an MCA.
1059 */
1060 udelay(20);
1061 for (cnt = 30000; cnt; cnt--) {
1062 if ((RD_REG_WORD(&reg->ctrl_status) &
1063 CSR_ISP_SOFT_RESET) == 0)
1064 break;
1065 udelay(100);
1066 }
1067 } else
1068 udelay(10);
1069
1070 /* Reset RISC processor. */
1071 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1072
1073 WRT_REG_WORD(&reg->semaphore, 0);
1074
1075 /* Release RISC processor. */
1076 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1077 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1078
1079 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1080 for (cnt = 0; cnt < 30000; cnt++) {
ffb39f03 1081 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1da177e4 1082 break;
1da177e4
LT		 1083
1084 udelay(100);
1085 }
1086 } else
1087 udelay(100);
1088
1089 /* Turn on master enable */
1090 cmd |= PCI_COMMAND_MASTER;
1091 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
1092
1093 /* Disable RISC pause on FPM parity error. */
1094 if (!IS_QLA2100(ha)) {
1095 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
1096 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
1097 }
1098
1099 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1100}
1101
b1d46989
MI		 1102/**
1103 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
1104 *
1105 * Returns 0 on success.
1106 */
fa492630 1107static int
b1d46989
MI		 1108qla81xx_reset_mpi(scsi_qla_host_t *vha)
1109{
1110 uint16_t mb[4] = {0x1010, 0, 1, 0};
1111
6246b8a1
GM		 1112 if (!IS_QLA81XX(vha->hw))
1113 return QLA_SUCCESS;
1114
b1d46989
MI		 1115 return qla81xx_write_mpi_register(vha, mb);
1116}
1117
0107109e 1118/**
88c26663 1119 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
0107109e
AV		 1120 * @ha: HA context
1121 *
1122 * Returns 0 on success.
1123 */
88c26663 1124static inline void
e315cd28 1125qla24xx_reset_risc(scsi_qla_host_t *vha)
0107109e
AV		 1126{
1127 unsigned long flags = 0;
e315cd28 1128 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 1129 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1130 uint32_t cnt, d2;
335a1cc9 1131 uint16_t wd;
b1d46989 1132 static int abts_cnt; /* ISP abort retry counts */
0107109e 1133
0107109e
AV		 1134 spin_lock_irqsave(&ha->hardware_lock, flags);
1135
1136 /* Reset RISC. */
1137 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1138 for (cnt = 0; cnt < 30000; cnt++) {
1139 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
1140 break;
1141
1142 udelay(10);
1143 }
1144
1145 WRT_REG_DWORD(&reg->ctrl_status,
1146 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335a1cc9 1147 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
88c26663 1148
335a1cc9 1149 udelay(100);
88c26663 1150 /* Wait for firmware to complete NVRAM accesses. */
88c26663
AV		 1151 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1152 for (cnt = 10000 ; cnt && d2; cnt--) {
1153 udelay(5);
1154 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1155 barrier();
1156 }
1157
335a1cc9 1158 /* Wait for soft-reset to complete. */
0107109e
AV		 1159 d2 = RD_REG_DWORD(&reg->ctrl_status);
1160 for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) {
1161 udelay(5);
1162 d2 = RD_REG_DWORD(&reg->ctrl_status);
1163 barrier();
1164 }
1165
b1d46989
MI		 1166 /* If required, do an MPI FW reset now */
1167 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
1168 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
1169 if (++abts_cnt < 5) {
1170 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1171 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
1172 } else {
1173 /*
1174 * We exhausted the ISP abort retries. We have to
1175 * set the board offline.
1176 */
1177 abts_cnt = 0;
1178 vha->flags.online = 0;
1179 }
1180 }
1181 }
1182
0107109e
AV		 1183 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
1184 RD_REG_DWORD(&reg->hccr);
1185
1186 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
1187 RD_REG_DWORD(&reg->hccr);
1188
1189 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
1190 RD_REG_DWORD(&reg->hccr);
1191
1192 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1193 for (cnt = 6000000 ; cnt && d2; cnt--) {
1194 udelay(5);
1195 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1196 barrier();
1197 }
1198
1199 spin_unlock_irqrestore(&ha->hardware_lock, flags);
124f85e6
AV		 1200
1201 if (IS_NOPOLLING_TYPE(ha))
1202 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 1203}
1204
4ea2c9c7
JC		 1205static void
1206qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
1207{
1208 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1209
1210 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1211 *data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);
1212
1213}
1214
1215static void
1216qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
1217{
1218 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1219
1220 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1221 WRT_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
1222}
1223
1224static void
1225qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
1226{
1227 struct qla_hw_data *ha = vha->hw;
1228 uint32_t wd32 = 0;
1229 uint delta_msec = 100;
1230 uint elapsed_msec = 0;
1231 uint timeout_msec;
1232 ulong n;
1233
1234 if (!IS_QLA25XX(ha) && !IS_QLA2031(ha))
1235 return;
1236
1237attempt:
1238 timeout_msec = TIMEOUT_SEMAPHORE;
1239 n = timeout_msec / delta_msec;
1240 while (n--) {
1241 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
1242 qla25xx_read_risc_sema_reg(vha, &wd32);
1243 if (wd32 & RISC_SEMAPHORE)
1244 break;
1245 msleep(delta_msec);
1246 elapsed_msec += delta_msec;
1247 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1248 goto force;
1249 }
1250
1251 if (!(wd32 & RISC_SEMAPHORE))
1252 goto force;
1253
1254 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1255 goto acquired;
1256
1257 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
1258 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
1259 n = timeout_msec / delta_msec;
1260 while (n--) {
1261 qla25xx_read_risc_sema_reg(vha, &wd32);
1262 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1263 break;
1264 msleep(delta_msec);
1265 elapsed_msec += delta_msec;
1266 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1267 goto force;
1268 }
1269
1270 if (wd32 & RISC_SEMAPHORE_FORCE)
1271 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
1272
1273 goto attempt;
1274
1275force:
1276 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
1277
1278acquired:
1279 return;
1280}
1281
88c26663
AV		 1282/**
1283 * qla24xx_reset_chip() - Reset ISP24xx chip.
1284 * @ha: HA context
1285 *
1286 * Returns 0 on success.
1287 */
1288void
e315cd28 1289qla24xx_reset_chip(scsi_qla_host_t *vha)
88c26663 1290{
e315cd28 1291 struct qla_hw_data *ha = vha->hw;
85880801
AV		 1292
1293 if (pci_channel_offline(ha->pdev) &&
1294 ha->flags.pci_channel_io_perm_failure) {
1295 return;
1296 }
1297
fd34f556 1298 ha->isp_ops->disable_intrs(ha);
88c26663 1299
4ea2c9c7
JC		 1300 qla25xx_manipulate_risc_semaphore(vha);
1301
88c26663 1302 /* Perform RISC reset. */
e315cd28 1303 qla24xx_reset_risc(vha);
88c26663
AV		 1304}
1305
1da177e4
LT		 1306/**
1307 * qla2x00_chip_diag() - Test chip for proper operation.
1308 * @ha: HA context
1309 *
1310 * Returns 0 on success.
1311 */
abbd8870 1312int
e315cd28 1313qla2x00_chip_diag(scsi_qla_host_t *vha)
1da177e4
LT		 1314{
1315 int rval;
e315cd28 1316 struct qla_hw_data *ha = vha->hw;
3d71644c 1317 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 1318 unsigned long flags = 0;
1319 uint16_t data;
1320 uint32_t cnt;
1321 uint16_t mb[5];
73208dfd 1322 struct req_que *req = ha->req_q_map[0];
1da177e4
LT		 1323
1324 /* Assume a failed state */
1325 rval = QLA_FUNCTION_FAILED;
1326
7c3df132
SK		 1327 ql_dbg(ql_dbg_init, vha, 0x007b,
1328 "Testing device at %lx.\n", (u_long)&reg->flash_address);
1da177e4
LT		 1329
1330 spin_lock_irqsave(&ha->hardware_lock, flags);
1331
1332 /* Reset ISP chip. */
1333 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1334
1335 /*
1336 * We need to have a delay here since the card will not respond while
1337 * in reset causing an MCA on some architectures.
1338 */
1339 udelay(20);
1340 data = qla2x00_debounce_register(&reg->ctrl_status);
1341 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
1342 udelay(5);
1343 data = RD_REG_WORD(&reg->ctrl_status);
1344 barrier();
1345 }
1346
1347 if (!cnt)
1348 goto chip_diag_failed;
1349
7c3df132
SK		 1350 ql_dbg(ql_dbg_init, vha, 0x007c,
1351 "Reset register cleared by chip reset.\n");
1da177e4
LT		 1352
1353 /* Reset RISC processor. */
1354 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1355 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1356
1357 /* Workaround for QLA2312 PCI parity error */
1358 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1359 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
1360 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
1361 udelay(5);
1362 data = RD_MAILBOX_REG(ha, reg, 0);
fa2a1ce5 1363 barrier();
1da177e4
LT		 1364 }
1365 } else
1366 udelay(10);
1367
1368 if (!cnt)
1369 goto chip_diag_failed;
1370
1371 /* Check product ID of chip */
7c3df132 1372 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
1da177e4
LT		 1373
1374 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
1375 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
1376 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
1377 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
1378 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
1379 mb[3] != PROD_ID_3) {
7c3df132
SK		 1380 ql_log(ql_log_warn, vha, 0x0062,
1381 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
1382 mb[1], mb[2], mb[3]);
1da177e4
LT		 1383
1384 goto chip_diag_failed;
1385 }
1386 ha->product_id[0] = mb[1];
1387 ha->product_id[1] = mb[2];
1388 ha->product_id[2] = mb[3];
1389 ha->product_id[3] = mb[4];
1390
1391 /* Adjust fw RISC transfer size */
73208dfd 1392 if (req->length > 1024)
1da177e4
LT		 1393 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
1394 else
1395 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
73208dfd 1396 req->length;
1da177e4
LT		 1397
1398 if (IS_QLA2200(ha) &&
1399 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
1400 /* Limit firmware transfer size with a 2200A */
7c3df132 1401 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1da177e4 1402
ea5b6382 1403 ha->device_type |= DT_ISP2200A;
1da177e4
LT		 1404 ha->fw_transfer_size = 128;
1405 }
1406
1407 /* Wrap Incoming Mailboxes Test. */
1408 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1409
7c3df132 1410 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
e315cd28 1411 rval = qla2x00_mbx_reg_test(vha);
7c3df132
SK		 1412 if (rval)
1413 ql_log(ql_log_warn, vha, 0x0080,
1414 "Failed mailbox send register test.\n");
1415 else
1da177e4
LT		 1416 /* Flag a successful rval */
1417 rval = QLA_SUCCESS;
1da177e4
LT		 1418 spin_lock_irqsave(&ha->hardware_lock, flags);
1419
1420chip_diag_failed:
1421 if (rval)
7c3df132
SK		 1422 ql_log(ql_log_info, vha, 0x0081,
1423 "Chip diagnostics **** FAILED ****.\n");
1da177e4
LT		 1424
1425 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1426
1427 return (rval);
1428}
1429
0107109e
AV		 1430/**
1431 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
1432 * @ha: HA context
1433 *
1434 * Returns 0 on success.
1435 */
1436int
e315cd28 1437qla24xx_chip_diag(scsi_qla_host_t *vha)
0107109e
AV		 1438{
1439 int rval;
e315cd28 1440 struct qla_hw_data *ha = vha->hw;
73208dfd 1441 struct req_que *req = ha->req_q_map[0];
0107109e 1442
7ec0effd 1443 if (IS_P3P_TYPE(ha))
a9083016
GM		 1444 return QLA_SUCCESS;
1445
73208dfd 1446 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
0107109e 1447
e315cd28 1448 rval = qla2x00_mbx_reg_test(vha);
0107109e 1449 if (rval) {
7c3df132
SK		 1450 ql_log(ql_log_warn, vha, 0x0082,
1451 "Failed mailbox send register test.\n");
0107109e
AV		 1452 } else {
1453 /* Flag a successful rval */
1454 rval = QLA_SUCCESS;
1455 }
1456
1457 return rval;
1458}
1459
a7a167bf 1460void
e315cd28 1461qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
0107109e 1462{
a7a167bf
AV		 1463 int rval;
1464 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
73208dfd 1465 eft_size, fce_size, mq_size;
df613b96
AV		 1466 dma_addr_t tc_dma;
1467 void *tc;
e315cd28 1468 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 1469 struct req_que *req = ha->req_q_map[0];
1470 struct rsp_que *rsp = ha->rsp_q_map[0];
a7a167bf
AV		 1471
1472 if (ha->fw_dump) {
7c3df132
SK		 1473 ql_dbg(ql_dbg_init, vha, 0x00bd,
1474 "Firmware dump already allocated.\n");
a7a167bf
AV		 1475 return;
1476 }
d4e3e04d 1477
0107109e 1478 ha->fw_dumped = 0;
61f098dd 1479 ha->fw_dump_cap_flags = 0;
f73cb695
CD		 1480 dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
1481 req_q_size = rsp_q_size = 0;
1482
1483 if (IS_QLA27XX(ha))
1484 goto try_fce;
1485
d4e3e04d 1486 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
a7a167bf 1487 fixed_size = sizeof(struct qla2100_fw_dump);
d4e3e04d 1488 } else if (IS_QLA23XX(ha)) {
a7a167bf
AV		 1489 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
1490 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
1491 sizeof(uint16_t);
e428924c 1492 } else if (IS_FWI2_CAPABLE(ha)) {
6246b8a1
GM		 1493 if (IS_QLA83XX(ha))
1494 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
1495 else if (IS_QLA81XX(ha))
3a03eb79
AV		 1496 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
1497 else if (IS_QLA25XX(ha))
1498 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
1499 else
1500 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
f73cb695 1501
a7a167bf
AV		 1502 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
1503 sizeof(uint32_t);
050c9bb1 1504 if (ha->mqenable) {
6246b8a1
GM		 1505 if (!IS_QLA83XX(ha))
1506 mq_size = sizeof(struct qla2xxx_mq_chain);
050c9bb1
GM		 1507 /*
1508 * Allocate maximum buffer size for all queues.
1509 * Resizing must be done at end-of-dump processing.
1510 */
1511 mq_size += ha->max_req_queues *
1512 (req->length * sizeof(request_t));
1513 mq_size += ha->max_rsp_queues *
1514 (rsp->length * sizeof(response_t));
1515 }
00876ae8 1516 if (ha->tgt.atio_ring)
2d70c103 1517 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
df613b96 1518 /* Allocate memory for Fibre Channel Event Buffer. */
f73cb695
CD		 1519 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
1520 !IS_QLA27XX(ha))
436a7b11 1521 goto try_eft;
df613b96 1522
f73cb695
CD		 1523try_fce:
1524 if (ha->fce)
1525 dma_free_coherent(&ha->pdev->dev,
1526 FCE_SIZE, ha->fce, ha->fce_dma);
1527
1528 /* Allocate memory for Fibre Channel Event Buffer. */
0ea85b50
JP		 1529 tc = dma_zalloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
1530 GFP_KERNEL);
df613b96 1531 if (!tc) {
7c3df132
SK		 1532 ql_log(ql_log_warn, vha, 0x00be,
1533 "Unable to allocate (%d KB) for FCE.\n",
1534 FCE_SIZE / 1024);
17d98630 1535 goto try_eft;
df613b96
AV		 1536 }
1537
e315cd28 1538 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
df613b96
AV		 1539 ha->fce_mb, &ha->fce_bufs);
1540 if (rval) {
7c3df132
SK		 1541 ql_log(ql_log_warn, vha, 0x00bf,
1542 "Unable to initialize FCE (%d).\n", rval);
df613b96
AV		 1543 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
1544 tc_dma);
1545 ha->flags.fce_enabled = 0;
17d98630 1546 goto try_eft;
df613b96 1547 }
cfb0919c 1548 ql_dbg(ql_dbg_init, vha, 0x00c0,
7c3df132 1549 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
df613b96 1550
7d9dade3 1551 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
df613b96
AV		 1552 ha->flags.fce_enabled = 1;
1553 ha->fce_dma = tc_dma;
1554 ha->fce = tc;
f73cb695 1555
436a7b11 1556try_eft:
f73cb695
CD		 1557 if (ha->eft)
1558 dma_free_coherent(&ha->pdev->dev,
1559 EFT_SIZE, ha->eft, ha->eft_dma);
1560
436a7b11 1561 /* Allocate memory for Extended Trace Buffer. */
0ea85b50
JP		 1562 tc = dma_zalloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
1563 GFP_KERNEL);
436a7b11 1564 if (!tc) {
7c3df132
SK		 1565 ql_log(ql_log_warn, vha, 0x00c1,
1566 "Unable to allocate (%d KB) for EFT.\n",
1567 EFT_SIZE / 1024);
436a7b11
AV		 1568 goto cont_alloc;
1569 }
1570
e315cd28 1571 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
436a7b11 1572 if (rval) {
7c3df132
SK		 1573 ql_log(ql_log_warn, vha, 0x00c2,
1574 "Unable to initialize EFT (%d).\n", rval);
436a7b11
AV		 1575 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
1576 tc_dma);
1577 goto cont_alloc;
1578 }
cfb0919c 1579 ql_dbg(ql_dbg_init, vha, 0x00c3,
7c3df132 1580 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
436a7b11
AV		 1581
1582 eft_size = EFT_SIZE;
1583 ha->eft_dma = tc_dma;
1584 ha->eft = tc;
d4e3e04d 1585 }
f73cb695 1586
a7a167bf 1587cont_alloc:
f73cb695
CD		 1588 if (IS_QLA27XX(ha)) {
1589 if (!ha->fw_dump_template) {
1590 ql_log(ql_log_warn, vha, 0x00ba,
1591 "Failed missing fwdump template\n");
1592 return;
1593 }
1594 dump_size = qla27xx_fwdt_calculate_dump_size(vha);
1595 ql_dbg(ql_dbg_init, vha, 0x00fa,
1596 "-> allocating fwdump (%x bytes)...\n", dump_size);
1597 goto allocate;
1598 }
1599
73208dfd
AC		 1600 req_q_size = req->length * sizeof(request_t);
1601 rsp_q_size = rsp->length * sizeof(response_t);
a7a167bf 1602 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
2afa19a9 1603 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
bb99de67
AV		 1604 ha->chain_offset = dump_size;
1605 dump_size += mq_size + fce_size;
d4e3e04d 1606
f73cb695 1607allocate:
d4e3e04d 1608 ha->fw_dump = vmalloc(dump_size);
a7a167bf 1609 if (!ha->fw_dump) {
7c3df132
SK		 1610 ql_log(ql_log_warn, vha, 0x00c4,
1611 "Unable to allocate (%d KB) for firmware dump.\n",
1612 dump_size / 1024);
a7a167bf 1613
e30d1756
MI		 1614 if (ha->fce) {
1615 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
1616 ha->fce_dma);
1617 ha->fce = NULL;
1618 ha->fce_dma = 0;
1619 }
1620
a7a167bf
AV		 1621 if (ha->eft) {
1622 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
1623 ha->eft_dma);
1624 ha->eft = NULL;
1625 ha->eft_dma = 0;
1626 }
1627 return;
1628 }
f73cb695 1629 ha->fw_dump_len = dump_size;
cfb0919c 1630 ql_dbg(ql_dbg_init, vha, 0x00c5,
7c3df132 1631 "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
a7a167bf 1632
f73cb695
CD		 1633 if (IS_QLA27XX(ha))
1634 return;
1635
a7a167bf
AV		 1636 ha->fw_dump->signature[0] = 'Q';
1637 ha->fw_dump->signature[1] = 'L';
1638 ha->fw_dump->signature[2] = 'G';
1639 ha->fw_dump->signature[3] = 'C';
1640 ha->fw_dump->version = __constant_htonl(1);
1641
1642 ha->fw_dump->fixed_size = htonl(fixed_size);
1643 ha->fw_dump->mem_size = htonl(mem_size);
1644 ha->fw_dump->req_q_size = htonl(req_q_size);
1645 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
1646
1647 ha->fw_dump->eft_size = htonl(eft_size);
1648 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
1649 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
1650
1651 ha->fw_dump->header_size =
1652 htonl(offsetof(struct qla2xxx_fw_dump, isp));
0107109e
AV		 1653}
1654
18e7555a
AV		 1655static int
1656qla81xx_mpi_sync(scsi_qla_host_t *vha)
1657{
1658#define MPS_MASK 0xe0
1659 int rval;
1660 uint16_t dc;
1661 uint32_t dw;
18e7555a
AV		 1662
1663 if (!IS_QLA81XX(vha->hw))
1664 return QLA_SUCCESS;
1665
1666 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
1667 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1668 ql_log(ql_log_warn, vha, 0x0105,
1669 "Unable to acquire semaphore.\n");
18e7555a
AV		 1670 goto done;
1671 }
1672
1673 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
1674 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
1675 if (rval != QLA_SUCCESS) {
7c3df132 1676 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
18e7555a
AV		 1677 goto done_release;
1678 }
1679
1680 dc &= MPS_MASK;
1681 if (dc == (dw & MPS_MASK))
1682 goto done_release;
1683
1684 dw &= ~MPS_MASK;
1685 dw |= dc;
1686 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
1687 if (rval != QLA_SUCCESS) {
7c3df132 1688 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
18e7555a
AV		 1689 }
1690
1691done_release:
1692 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
1693 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1694 ql_log(ql_log_warn, vha, 0x006d,
1695 "Unable to release semaphore.\n");
18e7555a
AV		 1696 }
1697
1698done:
1699 return rval;
1700}
1701
8d93f550
CD		 1702int
1703qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
1704{
1705 /* Don't try to reallocate the array */
1706 if (req->outstanding_cmds)
1707 return QLA_SUCCESS;
1708
1709 if (!IS_FWI2_CAPABLE(ha) || (ha->mqiobase &&
1710 (ql2xmultique_tag || ql2xmaxqueues > 1)))
1711 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
1712 else {
1713 if (ha->fw_xcb_count <= ha->fw_iocb_count)
1714 req->num_outstanding_cmds = ha->fw_xcb_count;
1715 else
1716 req->num_outstanding_cmds = ha->fw_iocb_count;
1717 }
1718
1719 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1720 req->num_outstanding_cmds, GFP_KERNEL);
1721
1722 if (!req->outstanding_cmds) {
1723 /*
1724 * Try to allocate a minimal size just so we can get through
1725 * initialization.
1726 */
1727 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
1728 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1729 req->num_outstanding_cmds, GFP_KERNEL);
1730
1731 if (!req->outstanding_cmds) {
1732 ql_log(ql_log_fatal, NULL, 0x0126,
1733 "Failed to allocate memory for "
1734 "outstanding_cmds for req_que %p.\n", req);
1735 req->num_outstanding_cmds = 0;
1736 return QLA_FUNCTION_FAILED;
1737 }
1738 }
1739
1740 return QLA_SUCCESS;
1741}
1742
1da177e4
LT		 1743/**
1744 * qla2x00_setup_chip() - Load and start RISC firmware.
1745 * @ha: HA context
1746 *
1747 * Returns 0 on success.
1748 */
1749static int
e315cd28 1750qla2x00_setup_chip(scsi_qla_host_t *vha)
1da177e4 1751{
0107109e
AV		 1752 int rval;
1753 uint32_t srisc_address = 0;
e315cd28 1754 struct qla_hw_data *ha = vha->hw;
3db0652e
AV		 1755 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1756 unsigned long flags;
dda772e8 1757 uint16_t fw_major_version;
3db0652e 1758
7ec0effd 1759 if (IS_P3P_TYPE(ha)) {
a9083016 1760 rval = ha->isp_ops->load_risc(vha, &srisc_address);
14e303d9
AV		 1761 if (rval == QLA_SUCCESS) {
1762 qla2x00_stop_firmware(vha);
a9083016 1763 goto enable_82xx_npiv;
14e303d9 1764 } else
b963752f 1765 goto failed;
a9083016
GM		 1766 }
1767
3db0652e
AV		 1768 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1769 /* Disable SRAM, Instruction RAM and GP RAM parity. */
1770 spin_lock_irqsave(&ha->hardware_lock, flags);
1771 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
1772 RD_REG_WORD(&reg->hccr);
1773 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1774 }
1da177e4 1775
18e7555a
AV		 1776 qla81xx_mpi_sync(vha);
1777
1da177e4 1778 /* Load firmware sequences */
e315cd28 1779 rval = ha->isp_ops->load_risc(vha, &srisc_address);
0107109e 1780 if (rval == QLA_SUCCESS) {
7c3df132
SK		 1781 ql_dbg(ql_dbg_init, vha, 0x00c9,
1782 "Verifying Checksum of loaded RISC code.\n");
1da177e4 1783
e315cd28 1784 rval = qla2x00_verify_checksum(vha, srisc_address);
1da177e4
LT		 1785 if (rval == QLA_SUCCESS) {
1786 /* Start firmware execution. */
7c3df132
SK		 1787 ql_dbg(ql_dbg_init, vha, 0x00ca,
1788 "Starting firmware.\n");
1da177e4 1789
e315cd28 1790 rval = qla2x00_execute_fw(vha, srisc_address);
1da177e4 1791 /* Retrieve firmware information. */
dda772e8 1792 if (rval == QLA_SUCCESS) {
a9083016 1793enable_82xx_npiv:
dda772e8 1794 fw_major_version = ha->fw_major_version;
7ec0effd 1795 if (IS_P3P_TYPE(ha))
3173167f 1796 qla82xx_check_md_needed(vha);
6246b8a1
GM		 1797 else
1798 rval = qla2x00_get_fw_version(vha);
ca9e9c3e
AV		 1799 if (rval != QLA_SUCCESS)
1800 goto failed;
2c3dfe3f 1801 ha->flags.npiv_supported = 0;
e315cd28 1802 if (IS_QLA2XXX_MIDTYPE(ha) &&
946fb891 1803 (ha->fw_attributes & BIT_2)) {
2c3dfe3f 1804 ha->flags.npiv_supported = 1;
4d0ea247
SJ		 1805 if ((!ha->max_npiv_vports) ||
1806 ((ha->max_npiv_vports + 1) %
eb66dc60 1807 MIN_MULTI_ID_FABRIC))
4d0ea247 1808 ha->max_npiv_vports =
eb66dc60 1809 MIN_MULTI_ID_FABRIC - 1;
4d0ea247 1810 }
24a08138 1811 qla2x00_get_resource_cnts(vha, NULL,
8d93f550 1812 &ha->fw_xcb_count, NULL, &ha->fw_iocb_count,
f3a0a77e 1813 &ha->max_npiv_vports, NULL);
d743de66 1814
8d93f550
CD		 1815 /*
1816 * Allocate the array of outstanding commands
1817 * now that we know the firmware resources.
1818 */
1819 rval = qla2x00_alloc_outstanding_cmds(ha,
1820 vha->req);
1821 if (rval != QLA_SUCCESS)
1822 goto failed;
1823
be5ea3cf 1824 if (!fw_major_version && ql2xallocfwdump
7ec0effd 1825 && !(IS_P3P_TYPE(ha)))
08de2844 1826 qla2x00_alloc_fw_dump(vha);
3b6e5b9d
CD		 1827 } else {
1828 goto failed;
1da177e4
LT		 1829 }
1830 } else {
7c3df132
SK		 1831 ql_log(ql_log_fatal, vha, 0x00cd,
1832 "ISP Firmware failed checksum.\n");
1833 goto failed;
1da177e4 1834 }
c74d88a4
AV		 1835 } else
1836 goto failed;
1da177e4 1837
3db0652e
AV		 1838 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1839 /* Enable proper parity. */
1840 spin_lock_irqsave(&ha->hardware_lock, flags);
1841 if (IS_QLA2300(ha))
1842 /* SRAM parity */
1843 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
1844 else
1845 /* SRAM, Instruction RAM and GP RAM parity */
1846 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
1847 RD_REG_WORD(&reg->hccr);
1848 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1849 }
1850
1d2874de
JC		 1851 if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1852 uint32_t size;
1853
1854 rval = qla81xx_fac_get_sector_size(vha, &size);
1855 if (rval == QLA_SUCCESS) {
1856 ha->flags.fac_supported = 1;
1857 ha->fdt_block_size = size << 2;
1858 } else {
7c3df132 1859 ql_log(ql_log_warn, vha, 0x00ce,
1d2874de
JC		 1860 "Unsupported FAC firmware (%d.%02d.%02d).\n",
1861 ha->fw_major_version, ha->fw_minor_version,
1862 ha->fw_subminor_version);
1ca60e3b 1863
f73cb695 1864 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
6246b8a1
GM		 1865 ha->flags.fac_supported = 0;
1866 rval = QLA_SUCCESS;
1867 }
1d2874de
JC		 1868 }
1869 }
ca9e9c3e 1870failed:
1da177e4 1871 if (rval) {
7c3df132
SK		 1872 ql_log(ql_log_fatal, vha, 0x00cf,
1873 "Setup chip ****FAILED****.\n");
1da177e4
LT		 1874 }
1875
1876 return (rval);
1877}
1878
1879/**
1880 * qla2x00_init_response_q_entries() - Initializes response queue entries.
1881 * @ha: HA context
1882 *
1883 * Beginning of request ring has initialization control block already built
1884 * by nvram config routine.
1885 *
1886 * Returns 0 on success.
1887 */
73208dfd
AC		 1888void
1889qla2x00_init_response_q_entries(struct rsp_que *rsp)
1da177e4
LT		 1890{
1891 uint16_t cnt;
1892 response_t *pkt;
1893
2afa19a9
AC		 1894 rsp->ring_ptr = rsp->ring;
1895 rsp->ring_index = 0;
1896 rsp->status_srb = NULL;
e315cd28
AC		 1897 pkt = rsp->ring_ptr;
1898 for (cnt = 0; cnt < rsp->length; cnt++) {
1da177e4
LT		 1899 pkt->signature = RESPONSE_PROCESSED;
1900 pkt++;
1901 }
1da177e4
LT		 1902}
1903
1904/**
1905 * qla2x00_update_fw_options() - Read and process firmware options.
1906 * @ha: HA context
1907 *
1908 * Returns 0 on success.
1909 */
abbd8870 1910void
e315cd28 1911qla2x00_update_fw_options(scsi_qla_host_t *vha)
1da177e4
LT		 1912{
1913 uint16_t swing, emphasis, tx_sens, rx_sens;
e315cd28 1914 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 1915
1916 memset(ha->fw_options, 0, sizeof(ha->fw_options));
e315cd28 1917 qla2x00_get_fw_options(vha, ha->fw_options);
1da177e4
LT		 1918
1919 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1920 return;
1921
1922 /* Serial Link options. */
7c3df132
SK		 1923 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
1924 "Serial link options.\n");
1925 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
1926 (uint8_t *)&ha->fw_seriallink_options,
1927 sizeof(ha->fw_seriallink_options));
1da177e4
LT		 1928
1929 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1930 if (ha->fw_seriallink_options[3] & BIT_2) {
1931 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
1932
1933 /* 1G settings */
1934 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
1935 emphasis = (ha->fw_seriallink_options[2] &
1936 (BIT_4 | BIT_3)) >> 3;
1937 tx_sens = ha->fw_seriallink_options[0] &
fa2a1ce5 1938 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1939 rx_sens = (ha->fw_seriallink_options[0] &
1940 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1941 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
1942 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1943 if (rx_sens == 0x0)
1944 rx_sens = 0x3;
1945 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
1946 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1947 ha->fw_options[10] |= BIT_5 |
1948 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1949 (tx_sens & (BIT_1 | BIT_0));
1950
1951 /* 2G settings */
1952 swing = (ha->fw_seriallink_options[2] &
1953 (BIT_7 | BIT_6 | BIT_5)) >> 5;
1954 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
1955 tx_sens = ha->fw_seriallink_options[1] &
fa2a1ce5 1956 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1957 rx_sens = (ha->fw_seriallink_options[1] &
1958 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1959 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
1960 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1961 if (rx_sens == 0x0)
1962 rx_sens = 0x3;
1963 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
1964 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1965 ha->fw_options[11] |= BIT_5 |
1966 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1967 (tx_sens & (BIT_1 | BIT_0));
1968 }
1969
1970 /* FCP2 options. */
1971 /* Return command IOCBs without waiting for an ABTS to complete. */
1972 ha->fw_options[3] |= BIT_13;
1973
1974 /* LED scheme. */
1975 if (ha->flags.enable_led_scheme)
1976 ha->fw_options[2] |= BIT_12;
1977
48c02fde 1978 /* Detect ISP6312. */
1979 if (IS_QLA6312(ha))
1980 ha->fw_options[2] |= BIT_13;
1981
1da177e4 1982 /* Update firmware options. */
e315cd28 1983 qla2x00_set_fw_options(vha, ha->fw_options);
1da177e4
LT		 1984}
1985
0107109e 1986void
e315cd28 1987qla24xx_update_fw_options(scsi_qla_host_t *vha)
0107109e
AV		 1988{
1989 int rval;
e315cd28 1990 struct qla_hw_data *ha = vha->hw;
0107109e 1991
7ec0effd 1992 if (IS_P3P_TYPE(ha))
a9083016
GM		 1993 return;
1994
0107109e 1995 /* Update Serial Link options. */
f94097ed 1996 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
0107109e
AV		 1997 return;
1998
e315cd28 1999 rval = qla2x00_set_serdes_params(vha,
f94097ed 2000 le16_to_cpu(ha->fw_seriallink_options24[1]),
2001 le16_to_cpu(ha->fw_seriallink_options24[2]),
2002 le16_to_cpu(ha->fw_seriallink_options24[3]));
0107109e 2003 if (rval != QLA_SUCCESS) {
7c3df132 2004 ql_log(ql_log_warn, vha, 0x0104,
0107109e
AV		 2005 "Unable to update Serial Link options (%x).\n", rval);
2006 }
2007}
2008
abbd8870 2009void
e315cd28 2010qla2x00_config_rings(struct scsi_qla_host *vha)
abbd8870 2011{
e315cd28 2012 struct qla_hw_data *ha = vha->hw;
3d71644c 2013 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
73208dfd
AC		 2014 struct req_que *req = ha->req_q_map[0];
2015 struct rsp_que *rsp = ha->rsp_q_map[0];
abbd8870
AV		 2016
2017 /* Setup ring parameters in initialization control block. */
2018 ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0);
2019 ha->init_cb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 2020 ha->init_cb->request_q_length = cpu_to_le16(req->length);
2021 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
2022 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
2023 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
2024 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
2025 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
abbd8870
AV		 2026
2027 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
2028 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
2029 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
2030 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
2031 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
2032}
2033
0107109e 2034void
e315cd28 2035qla24xx_config_rings(struct scsi_qla_host *vha)
0107109e 2036{
e315cd28 2037 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 2038 device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0);
2039 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
2040 struct qla_msix_entry *msix;
0107109e 2041 struct init_cb_24xx *icb;
73208dfd
AC		 2042 uint16_t rid = 0;
2043 struct req_que *req = ha->req_q_map[0];
2044 struct rsp_que *rsp = ha->rsp_q_map[0];
0107109e 2045
6246b8a1 2046 /* Setup ring parameters in initialization control block. */
0107109e
AV		 2047 icb = (struct init_cb_24xx *)ha->init_cb;
2048 icb->request_q_outpointer = __constant_cpu_to_le16(0);
2049 icb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 2050 icb->request_q_length = cpu_to_le16(req->length);
2051 icb->response_q_length = cpu_to_le16(rsp->length);
2052 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
2053 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
2054 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
2055 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
0107109e 2056
2d70c103
NB		 2057 /* Setup ATIO queue dma pointers for target mode */
2058 icb->atio_q_inpointer = __constant_cpu_to_le16(0);
2059 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
2060 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
2061 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
2062
7c6300e3
JC		 2063 if (IS_SHADOW_REG_CAPABLE(ha))
2064 icb->firmware_options_2 |=
2065 __constant_cpu_to_le32(BIT_30|BIT_29);
2066
f73cb695 2067 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
73208dfd
AC		 2068 icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS);
2069 icb->rid = __constant_cpu_to_le16(rid);
2070 if (ha->flags.msix_enabled) {
2071 msix = &ha->msix_entries[1];
7c3df132
SK		 2072 ql_dbg(ql_dbg_init, vha, 0x00fd,
2073 "Registering vector 0x%x for base que.\n",
2074 msix->entry);
73208dfd
AC		 2075 icb->msix = cpu_to_le16(msix->entry);
2076 }
2077 /* Use alternate PCI bus number */
2078 if (MSB(rid))
2079 icb->firmware_options_2 |=
2080 __constant_cpu_to_le32(BIT_19);
2081 /* Use alternate PCI devfn */
2082 if (LSB(rid))
2083 icb->firmware_options_2 |=
2084 __constant_cpu_to_le32(BIT_18);
2085
3155754a 2086 /* Use Disable MSIX Handshake mode for capable adapters */
6246b8a1
GM		 2087 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
2088 (ha->flags.msix_enabled)) {
3155754a
AC		 2089 icb->firmware_options_2 &=
2090 __constant_cpu_to_le32(~BIT_22);
2091 ha->flags.disable_msix_handshake = 1;
7c3df132
SK		 2092 ql_dbg(ql_dbg_init, vha, 0x00fe,
2093 "MSIX Handshake Disable Mode turned on.\n");
3155754a
AC		 2094 } else {
2095 icb->firmware_options_2 |=
2096 __constant_cpu_to_le32(BIT_22);
2097 }
73208dfd 2098 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_23);
73208dfd
AC		 2099
2100 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
2101 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
2102 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
2103 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
2104 } else {
2105 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
2106 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
2107 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
2108 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
2109 }
aa230bc5 2110 qlt_24xx_config_rings(vha);
2d70c103 2111
73208dfd
AC		 2112 /* PCI posting */
2113 RD_REG_DWORD(&ioreg->hccr);
0107109e
AV		 2114}
2115
1da177e4
LT		 2116/**
2117 * qla2x00_init_rings() - Initializes firmware.
2118 * @ha: HA context
2119 *
2120 * Beginning of request ring has initialization control block already built
2121 * by nvram config routine.
2122 *
2123 * Returns 0 on success.
2124 */
8ae6d9c7 2125int
e315cd28 2126qla2x00_init_rings(scsi_qla_host_t *vha)
1da177e4
LT		 2127{
2128 int rval;
2129 unsigned long flags = 0;
29bdccbe 2130 int cnt, que;
e315cd28 2131 struct qla_hw_data *ha = vha->hw;
29bdccbe
AC		 2132 struct req_que *req;
2133 struct rsp_que *rsp;
2c3dfe3f
SJ		 2134 struct mid_init_cb_24xx *mid_init_cb =
2135 (struct mid_init_cb_24xx *) ha->init_cb;
1da177e4
LT		 2136
2137 spin_lock_irqsave(&ha->hardware_lock, flags);
2138
2139 /* Clear outstanding commands array. */
2afa19a9 2140 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe
AC		 2141 req = ha->req_q_map[que];
2142 if (!req)
2143 continue;
7c6300e3
JC		 2144 req->out_ptr = (void *)(req->ring + req->length);
2145 *req->out_ptr = 0;
8d93f550 2146 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
29bdccbe 2147 req->outstanding_cmds[cnt] = NULL;
1da177e4 2148
2afa19a9 2149 req->current_outstanding_cmd = 1;
1da177e4 2150
29bdccbe
AC		 2151 /* Initialize firmware. */
2152 req->ring_ptr = req->ring;
2153 req->ring_index = 0;
2154 req->cnt = req->length;
2155 }
1da177e4 2156
2afa19a9 2157 for (que = 0; que < ha->max_rsp_queues; que++) {
29bdccbe
AC		 2158 rsp = ha->rsp_q_map[que];
2159 if (!rsp)
2160 continue;
7c6300e3
JC		 2161 rsp->in_ptr = (void *)(rsp->ring + rsp->length);
2162 *rsp->in_ptr = 0;
29bdccbe 2163 /* Initialize response queue entries */
8ae6d9c7
GM		 2164 if (IS_QLAFX00(ha))
2165 qlafx00_init_response_q_entries(rsp);
2166 else
2167 qla2x00_init_response_q_entries(rsp);
29bdccbe 2168 }
1da177e4 2169
2d70c103
NB		 2170 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
2171 ha->tgt.atio_ring_index = 0;
2172 /* Initialize ATIO queue entries */
2173 qlt_init_atio_q_entries(vha);
2174
e315cd28 2175 ha->isp_ops->config_rings(vha);
1da177e4
LT		 2176
2177 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2178
8ae6d9c7
GM		 2179 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
2180
2181 if (IS_QLAFX00(ha)) {
2182 rval = qlafx00_init_firmware(vha, ha->init_cb_size);
2183 goto next_check;
2184 }
2185
1da177e4 2186 /* Update any ISP specific firmware options before initialization. */
e315cd28 2187 ha->isp_ops->update_fw_options(vha);
1da177e4 2188
605aa2bc 2189 if (ha->flags.npiv_supported) {
45980cc2 2190 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
605aa2bc 2191 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
c48339de 2192 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
605aa2bc
LC		 2193 }
2194
24a08138
AV		 2195 if (IS_FWI2_CAPABLE(ha)) {
2196 mid_init_cb->options = __constant_cpu_to_le16(BIT_1);
2197 mid_init_cb->init_cb.execution_throttle =
2198 cpu_to_le16(ha->fw_xcb_count);
2199 }
2c3dfe3f 2200
e315cd28 2201 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
8ae6d9c7 2202next_check:
1da177e4 2203 if (rval) {
7c3df132
SK		 2204 ql_log(ql_log_fatal, vha, 0x00d2,
2205 "Init Firmware **** FAILED ****.\n");
1da177e4 2206 } else {
7c3df132
SK		 2207 ql_dbg(ql_dbg_init, vha, 0x00d3,
2208 "Init Firmware -- success.\n");
1da177e4
LT		 2209 }
2210
2211 return (rval);
2212}
2213
2214/**
2215 * qla2x00_fw_ready() - Waits for firmware ready.
2216 * @ha: HA context
2217 *
2218 * Returns 0 on success.
2219 */
2220static int
e315cd28 2221qla2x00_fw_ready(scsi_qla_host_t *vha)
1da177e4
LT		 2222{
2223 int rval;
4d4df193 2224 unsigned long wtime, mtime, cs84xx_time;
1da177e4
LT		 2225 uint16_t min_wait; /* Minimum wait time if loop is down */
2226 uint16_t wait_time; /* Wait time if loop is coming ready */
b5a340dd 2227 uint16_t state[6];
e315cd28 2228 struct qla_hw_data *ha = vha->hw;
1da177e4 2229
8ae6d9c7
GM		 2230 if (IS_QLAFX00(vha->hw))
2231 return qlafx00_fw_ready(vha);
2232
1da177e4
LT		 2233 rval = QLA_SUCCESS;
2234
2235 /* 20 seconds for loop down. */
fa2a1ce5 2236 min_wait = 20;
1da177e4
LT		 2237
2238 /*
2239 * Firmware should take at most one RATOV to login, plus 5 seconds for
2240 * our own processing.
2241 */
2242 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
2243 wait_time = min_wait;
2244 }
2245
2246 /* Min wait time if loop down */
2247 mtime = jiffies + (min_wait * HZ);
2248
2249 /* wait time before firmware ready */
2250 wtime = jiffies + (wait_time * HZ);
2251
2252 /* Wait for ISP to finish LIP */
e315cd28 2253 if (!vha->flags.init_done)
7c3df132
SK		 2254 ql_log(ql_log_info, vha, 0x801e,
2255 "Waiting for LIP to complete.\n");
1da177e4
LT		 2256
2257 do {
5b939038 2258 memset(state, -1, sizeof(state));
e315cd28 2259 rval = qla2x00_get_firmware_state(vha, state);
1da177e4 2260 if (rval == QLA_SUCCESS) {
4d4df193 2261 if (state[0] < FSTATE_LOSS_OF_SYNC) {
e315cd28 2262 vha->device_flags &= ~DFLG_NO_CABLE;
1da177e4 2263 }
4d4df193 2264 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
7c3df132
SK		 2265 ql_dbg(ql_dbg_taskm, vha, 0x801f,
2266 "fw_state=%x 84xx=%x.\n", state[0],
2267 state[2]);
4d4df193
HK		 2268 if ((state[2] & FSTATE_LOGGED_IN) &&
2269 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
7c3df132
SK		 2270 ql_dbg(ql_dbg_taskm, vha, 0x8028,
2271 "Sending verify iocb.\n");
4d4df193
HK		 2272
2273 cs84xx_time = jiffies;
e315cd28 2274 rval = qla84xx_init_chip(vha);
7c3df132
SK		 2275 if (rval != QLA_SUCCESS) {
2276 ql_log(ql_log_warn,
cfb0919c 2277 vha, 0x8007,
7c3df132 2278 "Init chip failed.\n");
4d4df193 2279 break;
7c3df132 2280 }
4d4df193
HK		 2281
2282 /* Add time taken to initialize. */
2283 cs84xx_time = jiffies - cs84xx_time;
2284 wtime += cs84xx_time;
2285 mtime += cs84xx_time;
cfb0919c 2286 ql_dbg(ql_dbg_taskm, vha, 0x8008,
7c3df132
SK		 2287 "Increasing wait time by %ld. "
2288 "New time %ld.\n", cs84xx_time,
2289 wtime);
4d4df193
HK		 2290 }
2291 } else if (state[0] == FSTATE_READY) {
7c3df132
SK		 2292 ql_dbg(ql_dbg_taskm, vha, 0x8037,
2293 "F/W Ready - OK.\n");
1da177e4 2294
e315cd28 2295 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1da177e4
LT		 2296 &ha->login_timeout, &ha->r_a_tov);
2297
2298 rval = QLA_SUCCESS;
2299 break;
2300 }
2301
2302 rval = QLA_FUNCTION_FAILED;
2303
e315cd28 2304 if (atomic_read(&vha->loop_down_timer) &&
4d4df193 2305 state[0] != FSTATE_READY) {
1da177e4 2306 /* Loop down. Timeout on min_wait for states
fa2a1ce5
AV		 2307 * other than Wait for Login.
2308 */
1da177e4 2309 if (time_after_eq(jiffies, mtime)) {
7c3df132 2310 ql_log(ql_log_info, vha, 0x8038,
1da177e4
LT		 2311 "Cable is unplugged...\n");
2312
e315cd28 2313 vha->device_flags |= DFLG_NO_CABLE;
1da177e4
LT		 2314 break;
2315 }
2316 }
2317 } else {
2318 /* Mailbox cmd failed. Timeout on min_wait. */
cdbb0a4f 2319 if (time_after_eq(jiffies, mtime) ||
7190575f 2320 ha->flags.isp82xx_fw_hung)
1da177e4
LT		 2321 break;
2322 }
2323
2324 if (time_after_eq(jiffies, wtime))
2325 break;
2326
2327 /* Delay for a while */
2328 msleep(500);
1da177e4
LT		 2329 } while (1);
2330
7c3df132 2331 ql_dbg(ql_dbg_taskm, vha, 0x803a,
b5a340dd
JC		 2332 "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0],
2333 state[1], state[2], state[3], state[4], state[5], jiffies);
1da177e4 2334
cfb0919c 2335 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132
SK		 2336 ql_log(ql_log_warn, vha, 0x803b,
2337 "Firmware ready **** FAILED ****.\n");
1da177e4
LT		 2338 }
2339
2340 return (rval);
2341}
2342
2343/*
2344* qla2x00_configure_hba
2345* Setup adapter context.
2346*
2347* Input:
2348* ha = adapter state pointer.
2349*
2350* Returns:
2351* 0 = success
2352*
2353* Context:
2354* Kernel context.
2355*/
2356static int
e315cd28 2357qla2x00_configure_hba(scsi_qla_host_t *vha)
1da177e4
LT		 2358{
2359 int rval;
2360 uint16_t loop_id;
2361 uint16_t topo;
2c3dfe3f 2362 uint16_t sw_cap;
1da177e4
LT		 2363 uint8_t al_pa;
2364 uint8_t area;
2365 uint8_t domain;
2366 char connect_type[22];
e315cd28 2367 struct qla_hw_data *ha = vha->hw;
f24b5cb8 2368 unsigned long flags;
61e1b269 2369 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 2370
2371 /* Get host addresses. */
e315cd28 2372 rval = qla2x00_get_adapter_id(vha,
2c3dfe3f 2373 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
1da177e4 2374 if (rval != QLA_SUCCESS) {
e315cd28 2375 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
6246b8a1 2376 IS_CNA_CAPABLE(ha) ||
33135aa2 2377 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
7c3df132
SK		 2378 ql_dbg(ql_dbg_disc, vha, 0x2008,
2379 "Loop is in a transition state.\n");
33135aa2 2380 } else {
7c3df132
SK		 2381 ql_log(ql_log_warn, vha, 0x2009,
2382 "Unable to get host loop ID.\n");
61e1b269
JC		 2383 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
2384 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
2385 ql_log(ql_log_warn, vha, 0x1151,
2386 "Doing link init.\n");
2387 if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
2388 return rval;
2389 }
e315cd28 2390 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
33135aa2 2391 }
1da177e4
LT		 2392 return (rval);
2393 }
2394
2395 if (topo == 4) {
7c3df132
SK		 2396 ql_log(ql_log_info, vha, 0x200a,
2397 "Cannot get topology - retrying.\n");
1da177e4
LT		 2398 return (QLA_FUNCTION_FAILED);
2399 }
2400
e315cd28 2401 vha->loop_id = loop_id;
1da177e4
LT		 2402
2403 /* initialize */
2404 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
2405 ha->operating_mode = LOOP;
2c3dfe3f 2406 ha->switch_cap = 0;
1da177e4
LT		 2407
2408 switch (topo) {
2409 case 0:
7c3df132 2410 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
1da177e4
LT		 2411 ha->current_topology = ISP_CFG_NL;
2412 strcpy(connect_type, "(Loop)");
2413 break;
2414
2415 case 1:
7c3df132 2416 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2c3dfe3f 2417 ha->switch_cap = sw_cap;
1da177e4
LT		 2418 ha->current_topology = ISP_CFG_FL;
2419 strcpy(connect_type, "(FL_Port)");
2420 break;
2421
2422 case 2:
7c3df132 2423 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
1da177e4
LT		 2424 ha->operating_mode = P2P;
2425 ha->current_topology = ISP_CFG_N;
2426 strcpy(connect_type, "(N_Port-to-N_Port)");
2427 break;
2428
2429 case 3:
7c3df132 2430 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2c3dfe3f 2431 ha->switch_cap = sw_cap;
1da177e4
LT		 2432 ha->operating_mode = P2P;
2433 ha->current_topology = ISP_CFG_F;
2434 strcpy(connect_type, "(F_Port)");
2435 break;
2436
2437 default:
7c3df132
SK		 2438 ql_dbg(ql_dbg_disc, vha, 0x200f,
2439 "HBA in unknown topology %x, using NL.\n", topo);
1da177e4
LT		 2440 ha->current_topology = ISP_CFG_NL;
2441 strcpy(connect_type, "(Loop)");
2442 break;
2443 }
2444
2445 /* Save Host port and loop ID. */
2446 /* byte order - Big Endian */
e315cd28
AC		 2447 vha->d_id.b.domain = domain;
2448 vha->d_id.b.area = area;
2449 vha->d_id.b.al_pa = al_pa;
1da177e4 2450
f24b5cb8 2451 spin_lock_irqsave(&ha->vport_slock, flags);
2d70c103 2452 qlt_update_vp_map(vha, SET_AL_PA);
f24b5cb8 2453 spin_unlock_irqrestore(&ha->vport_slock, flags);
2d70c103 2454
e315cd28 2455 if (!vha->flags.init_done)
7c3df132
SK		 2456 ql_log(ql_log_info, vha, 0x2010,
2457 "Topology - %s, Host Loop address 0x%x.\n",
e315cd28 2458 connect_type, vha->loop_id);
1da177e4 2459
1da177e4
LT		 2460 return(rval);
2461}
2462
a9083016 2463inline void
e315cd28
AC		 2464qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
2465 char *def)
9bb9fcf2
AV		 2466{
2467 char *st, *en;
2468 uint16_t index;
e315cd28 2469 struct qla_hw_data *ha = vha->hw;
ab671149 2470 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
6246b8a1 2471 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
9bb9fcf2
AV		 2472
2473 if (memcmp(model, BINZERO, len) != 0) {
2474 strncpy(ha->model_number, model, len);
2475 st = en = ha->model_number;
2476 en += len - 1;
2477 while (en > st) {
2478 if (*en != 0x20 && *en != 0x00)
2479 break;
2480 *en-- = '\0';
2481 }
2482
2483 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2484 if (use_tbl &&
2485 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 2486 index < QLA_MODEL_NAMES)
1ee27146
JC		 2487 strncpy(ha->model_desc,
2488 qla2x00_model_name[index * 2 + 1],
2489 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2490 } else {
2491 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2492 if (use_tbl &&
2493 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2
AV		 2494 index < QLA_MODEL_NAMES) {
2495 strcpy(ha->model_number,
2496 qla2x00_model_name[index * 2]);
1ee27146
JC		 2497 strncpy(ha->model_desc,
2498 qla2x00_model_name[index * 2 + 1],
2499 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2500 } else {
2501 strcpy(ha->model_number, def);
2502 }
2503 }
1ee27146 2504 if (IS_FWI2_CAPABLE(ha))
e315cd28 2505 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
1ee27146 2506 sizeof(ha->model_desc));
9bb9fcf2
AV		 2507}
2508
4e08df3f
DM		 2509/* On sparc systems, obtain port and node WWN from firmware
2510 * properties.
2511 */
e315cd28 2512static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4e08df3f
DM		 2513{
2514#ifdef CONFIG_SPARC
e315cd28 2515 struct qla_hw_data *ha = vha->hw;
4e08df3f 2516 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 2517 struct device_node *dp = pci_device_to_OF_node(pdev);
2518 const u8 *val;
4e08df3f
DM		 2519 int len;
2520
2521 val = of_get_property(dp, "port-wwn", &len);
2522 if (val && len >= WWN_SIZE)
2523 memcpy(nv->port_name, val, WWN_SIZE);
2524
2525 val = of_get_property(dp, "node-wwn", &len);
2526 if (val && len >= WWN_SIZE)
2527 memcpy(nv->node_name, val, WWN_SIZE);
2528#endif
2529}
2530
1da177e4
LT		 2531/*
2532* NVRAM configuration for ISP 2xxx
2533*
2534* Input:
2535* ha = adapter block pointer.
2536*
2537* Output:
2538* initialization control block in response_ring
2539* host adapters parameters in host adapter block
2540*
2541* Returns:
2542* 0 = success.
2543*/
abbd8870 2544int
e315cd28 2545qla2x00_nvram_config(scsi_qla_host_t *vha)
1da177e4 2546{
4e08df3f 2547 int rval;
0107109e
AV		 2548 uint8_t chksum = 0;
2549 uint16_t cnt;
2550 uint8_t *dptr1, *dptr2;
e315cd28 2551 struct qla_hw_data *ha = vha->hw;
0107109e 2552 init_cb_t *icb = ha->init_cb;
281afe19
SJ		 2553 nvram_t *nv = ha->nvram;
2554 uint8_t *ptr = ha->nvram;
3d71644c 2555 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2556
4e08df3f
DM		 2557 rval = QLA_SUCCESS;
2558
1da177e4 2559 /* Determine NVRAM starting address. */
0107109e 2560 ha->nvram_size = sizeof(nvram_t);
1da177e4
LT		 2561 ha->nvram_base = 0;
2562 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
2563 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
2564 ha->nvram_base = 0x80;
2565
2566 /* Get NVRAM data and calculate checksum. */
e315cd28 2567 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
0107109e
AV		 2568 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
2569 chksum += *ptr++;
1da177e4 2570
7c3df132
SK		 2571 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
2572 "Contents of NVRAM.\n");
2573 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
2574 (uint8_t *)nv, ha->nvram_size);
1da177e4
LT		 2575
2576 /* Bad NVRAM data, set defaults parameters. */
2577 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
2578 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
2579 /* Reset NVRAM data. */
7c3df132 2580 ql_log(ql_log_warn, vha, 0x0064,
9e336520 2581 "Inconsistent NVRAM "
7c3df132
SK		 2582 "detected: checksum=0x%x id=%c version=0x%x.\n",
2583 chksum, nv->id[0], nv->nvram_version);
2584 ql_log(ql_log_warn, vha, 0x0065,
2585 "Falling back to "
2586 "functioning (yet invalid -- WWPN) defaults.\n");
4e08df3f
DM		 2587
2588 /*
2589 * Set default initialization control block.
2590 */
2591 memset(nv, 0, ha->nvram_size);
2592 nv->parameter_block_version = ICB_VERSION;
2593
2594 if (IS_QLA23XX(ha)) {
2595 nv->firmware_options[0] = BIT_2 | BIT_1;
2596 nv->firmware_options[1] = BIT_7 | BIT_5;
2597 nv->add_firmware_options[0] = BIT_5;
2598 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 2599 nv->frame_payload_size = 2048;
4e08df3f
DM		 2600 nv->special_options[1] = BIT_7;
2601 } else if (IS_QLA2200(ha)) {
2602 nv->firmware_options[0] = BIT_2 | BIT_1;
2603 nv->firmware_options[1] = BIT_7 | BIT_5;
2604 nv->add_firmware_options[0] = BIT_5;
2605 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 2606 nv->frame_payload_size = 1024;
4e08df3f
DM		 2607 } else if (IS_QLA2100(ha)) {
2608 nv->firmware_options[0] = BIT_3 | BIT_1;
2609 nv->firmware_options[1] = BIT_5;
98aee70d 2610 nv->frame_payload_size = 1024;
4e08df3f
DM		 2611 }
2612
2613 nv->max_iocb_allocation = __constant_cpu_to_le16(256);
2614 nv->execution_throttle = __constant_cpu_to_le16(16);
2615 nv->retry_count = 8;
2616 nv->retry_delay = 1;
2617
2618 nv->port_name[0] = 33;
2619 nv->port_name[3] = 224;
2620 nv->port_name[4] = 139;
2621
e315cd28 2622 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 2623
2624 nv->login_timeout = 4;
2625
2626 /*
2627 * Set default host adapter parameters
2628 */
2629 nv->host_p[1] = BIT_2;
2630 nv->reset_delay = 5;
2631 nv->port_down_retry_count = 8;
2632 nv->max_luns_per_target = __constant_cpu_to_le16(8);
2633 nv->link_down_timeout = 60;
2634
2635 rval = 1;
1da177e4
LT		 2636 }
2637
2638#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
2639 /*
2640 * The SN2 does not provide BIOS emulation which means you can't change
2641 * potentially bogus BIOS settings. Force the use of default settings
2642 * for link rate and frame size. Hope that the rest of the settings
2643 * are valid.
2644 */
2645 if (ia64_platform_is("sn2")) {
98aee70d 2646 nv->frame_payload_size = 2048;
1da177e4
LT		 2647 if (IS_QLA23XX(ha))
2648 nv->special_options[1] = BIT_7;
2649 }
2650#endif
2651
2652 /* Reset Initialization control block */
0107109e 2653 memset(icb, 0, ha->init_cb_size);
1da177e4
LT		 2654
2655 /*
2656 * Setup driver NVRAM options.
2657 */
2658 nv->firmware_options[0] |= (BIT_6 | BIT_1);
2659 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
2660 nv->firmware_options[1] |= (BIT_5 | BIT_0);
2661 nv->firmware_options[1] &= ~BIT_4;
2662
2663 if (IS_QLA23XX(ha)) {
2664 nv->firmware_options[0] |= BIT_2;
2665 nv->firmware_options[0] &= ~BIT_3;
2d70c103 2666 nv->special_options[0] &= ~BIT_6;
0107109e 2667 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
1da177e4
LT		 2668
2669 if (IS_QLA2300(ha)) {
2670 if (ha->fb_rev == FPM_2310) {
2671 strcpy(ha->model_number, "QLA2310");
2672 } else {
2673 strcpy(ha->model_number, "QLA2300");
2674 }
2675 } else {
e315cd28 2676 qla2x00_set_model_info(vha, nv->model_number,
9bb9fcf2 2677 sizeof(nv->model_number), "QLA23xx");
1da177e4
LT		 2678 }
2679 } else if (IS_QLA2200(ha)) {
2680 nv->firmware_options[0] |= BIT_2;
2681 /*
2682 * 'Point-to-point preferred, else loop' is not a safe
2683 * connection mode setting.
2684 */
2685 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
2686 (BIT_5 | BIT_4)) {
2687 /* Force 'loop preferred, else point-to-point'. */
2688 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
2689 nv->add_firmware_options[0] |= BIT_5;
2690 }
2691 strcpy(ha->model_number, "QLA22xx");
2692 } else /*if (IS_QLA2100(ha))*/ {
2693 strcpy(ha->model_number, "QLA2100");
2694 }
2695
2696 /*
2697 * Copy over NVRAM RISC parameter block to initialization control block.
2698 */
2699 dptr1 = (uint8_t *)icb;
2700 dptr2 = (uint8_t *)&nv->parameter_block_version;
2701 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
2702 while (cnt--)
2703 *dptr1++ = *dptr2++;
2704
2705 /* Copy 2nd half. */
2706 dptr1 = (uint8_t *)icb->add_firmware_options;
2707 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
2708 while (cnt--)
2709 *dptr1++ = *dptr2++;
2710
5341e868
AV		 2711 /* Use alternate WWN? */
2712 if (nv->host_p[1] & BIT_7) {
2713 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
2714 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
2715 }
2716
1da177e4
LT		 2717 /* Prepare nodename */
2718 if ((icb->firmware_options[1] & BIT_6) == 0) {
2719 /*
2720 * Firmware will apply the following mask if the nodename was
2721 * not provided.
2722 */
2723 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
2724 icb->node_name[0] &= 0xF0;
2725 }
2726
2727 /*
2728 * Set host adapter parameters.
2729 */
3ce8866c
SK		 2730
2731 /*
2732 * BIT_7 in the host-parameters section allows for modification to
2733 * internal driver logging.
2734 */
0181944f 2735 if (nv->host_p[0] & BIT_7)
cfb0919c 2736 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1da177e4
LT		 2737 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
2738 /* Always load RISC code on non ISP2[12]00 chips. */
2739 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
2740 ha->flags.disable_risc_code_load = 0;
2741 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
2742 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
2743 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
06c22bd1 2744 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
d4c760c2 2745 ha->flags.disable_serdes = 0;
1da177e4
LT		 2746
2747 ha->operating_mode =
2748 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
2749
2750 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
2751 sizeof(ha->fw_seriallink_options));
2752
2753 /* save HBA serial number */
2754 ha->serial0 = icb->port_name[5];
2755 ha->serial1 = icb->port_name[6];
2756 ha->serial2 = icb->port_name[7];
e315cd28
AC		 2757 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
2758 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
1da177e4
LT		 2759
2760 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
2761
2762 ha->retry_count = nv->retry_count;
2763
2764 /* Set minimum login_timeout to 4 seconds. */
5b91490e 2765 if (nv->login_timeout != ql2xlogintimeout)
1da177e4
LT		 2766 nv->login_timeout = ql2xlogintimeout;
2767 if (nv->login_timeout < 4)
2768 nv->login_timeout = 4;
2769 ha->login_timeout = nv->login_timeout;
2770 icb->login_timeout = nv->login_timeout;
2771
00a537b8
AV		 2772 /* Set minimum RATOV to 100 tenths of a second. */
2773 ha->r_a_tov = 100;
1da177e4 2774
1da177e4
LT		 2775 ha->loop_reset_delay = nv->reset_delay;
2776
1da177e4
LT		 2777 /* Link Down Timeout = 0:
2778 *
2779 * When Port Down timer expires we will start returning
2780 * I/O's to OS with "DID_NO_CONNECT".
2781 *
2782 * Link Down Timeout != 0:
2783 *
2784 * The driver waits for the link to come up after link down
2785 * before returning I/Os to OS with "DID_NO_CONNECT".
fa2a1ce5 2786 */
1da177e4
LT		 2787 if (nv->link_down_timeout == 0) {
2788 ha->loop_down_abort_time =
354d6b21 2789 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
1da177e4
LT		 2790 } else {
2791 ha->link_down_timeout = nv->link_down_timeout;
2792 ha->loop_down_abort_time =
2793 (LOOP_DOWN_TIME - ha->link_down_timeout);
fa2a1ce5 2794 }
1da177e4 2795
1da177e4
LT		 2796 /*
2797 * Need enough time to try and get the port back.
2798 */
2799 ha->port_down_retry_count = nv->port_down_retry_count;
2800 if (qlport_down_retry)
2801 ha->port_down_retry_count = qlport_down_retry;
2802 /* Set login_retry_count */
2803 ha->login_retry_count = nv->retry_count;
2804 if (ha->port_down_retry_count == nv->port_down_retry_count &&
2805 ha->port_down_retry_count > 3)
2806 ha->login_retry_count = ha->port_down_retry_count;
2807 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
2808 ha->login_retry_count = ha->port_down_retry_count;
2809 if (ql2xloginretrycount)
2810 ha->login_retry_count = ql2xloginretrycount;
2811
1da177e4
LT		 2812 icb->lun_enables = __constant_cpu_to_le16(0);
2813 icb->command_resource_count = 0;
2814 icb->immediate_notify_resource_count = 0;
2815 icb->timeout = __constant_cpu_to_le16(0);
2816
2817 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
2818 /* Enable RIO */
2819 icb->firmware_options[0] &= ~BIT_3;
2820 icb->add_firmware_options[0] &=
2821 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
2822 icb->add_firmware_options[0] |= BIT_2;
2823 icb->response_accumulation_timer = 3;
2824 icb->interrupt_delay_timer = 5;
2825
e315cd28 2826 vha->flags.process_response_queue = 1;
1da177e4 2827 } else {
4fdfefe5 2828 /* Enable ZIO. */
e315cd28 2829 if (!vha->flags.init_done) {
4fdfefe5
AV		 2830 ha->zio_mode = icb->add_firmware_options[0] &
2831 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
2832 ha->zio_timer = icb->interrupt_delay_timer ?
2833 icb->interrupt_delay_timer: 2;
2834 }
1da177e4
LT		 2835 icb->add_firmware_options[0] &=
2836 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
e315cd28 2837 vha->flags.process_response_queue = 0;
4fdfefe5 2838 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d 2839 ha->zio_mode = QLA_ZIO_MODE_6;
2840
7c3df132 2841 ql_log(ql_log_info, vha, 0x0068,
4fdfefe5
AV		 2842 "ZIO mode %d enabled; timer delay (%d us).\n",
2843 ha->zio_mode, ha->zio_timer * 100);
1da177e4 2844
4fdfefe5
AV		 2845 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
2846 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
e315cd28 2847 vha->flags.process_response_queue = 1;
1da177e4
LT		 2848 }
2849 }
2850
4e08df3f 2851 if (rval) {
7c3df132
SK		 2852 ql_log(ql_log_warn, vha, 0x0069,
2853 "NVRAM configuration failed.\n");
4e08df3f
DM		 2854 }
2855 return (rval);
1da177e4
LT		 2856}
2857
19a7b4ae
JSEC		 2858static void
2859qla2x00_rport_del(void *data)
2860{
2861 fc_port_t *fcport = data;
d97994dc 2862 struct fc_rport *rport;
2d70c103 2863 scsi_qla_host_t *vha = fcport->vha;
044d78e1 2864 unsigned long flags;
d97994dc 2865
044d78e1 2866 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
ac280b67 2867 rport = fcport->drport ? fcport->drport: fcport->rport;
d97994dc 2868 fcport->drport = NULL;
044d78e1 2869 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
2d70c103 2870 if (rport) {
d97994dc 2871 fc_remote_port_delete(rport);
2d70c103
NB		 2872 /*
2873 * Release the target mode FC NEXUS in qla_target.c code
2874 * if target mod is enabled.
2875 */
2876 qlt_fc_port_deleted(vha, fcport);
2877 }
19a7b4ae
JSEC		 2878}
2879
1da177e4
LT		 2880/**
2881 * qla2x00_alloc_fcport() - Allocate a generic fcport.
2882 * @ha: HA context
2883 * @flags: allocation flags
2884 *
2885 * Returns a pointer to the allocated fcport, or NULL, if none available.
2886 */
9a069e19 2887fc_port_t *
e315cd28 2888qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
1da177e4
LT		 2889{
2890 fc_port_t *fcport;
2891
bbfbbbc1
MK		 2892 fcport = kzalloc(sizeof(fc_port_t), flags);
2893 if (!fcport)
2894 return NULL;
1da177e4
LT		 2895
2896 /* Setup fcport template structure. */
e315cd28 2897 fcport->vha = vha;
1da177e4
LT		 2898 fcport->port_type = FCT_UNKNOWN;
2899 fcport->loop_id = FC_NO_LOOP_ID;
ec426e10 2900 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
ad3e0eda 2901 fcport->supported_classes = FC_COS_UNSPECIFIED;
1da177e4 2902
bbfbbbc1 2903 return fcport;
1da177e4
LT		 2904}
2905
2906/*
2907 * qla2x00_configure_loop
2908 * Updates Fibre Channel Device Database with what is actually on loop.
2909 *
2910 * Input:
2911 * ha = adapter block pointer.
2912 *
2913 * Returns:
2914 * 0 = success.
2915 * 1 = error.
2916 * 2 = database was full and device was not configured.
2917 */
2918static int
e315cd28 2919qla2x00_configure_loop(scsi_qla_host_t *vha)
1da177e4
LT		 2920{
2921 int rval;
2922 unsigned long flags, save_flags;
e315cd28 2923 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2924 rval = QLA_SUCCESS;
2925
2926 /* Get Initiator ID */
e315cd28
AC		 2927 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
2928 rval = qla2x00_configure_hba(vha);
1da177e4 2929 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2930 ql_dbg(ql_dbg_disc, vha, 0x2013,
2931 "Unable to configure HBA.\n");
1da177e4
LT		 2932 return (rval);
2933 }
2934 }
2935
e315cd28 2936 save_flags = flags = vha->dpc_flags;
7c3df132
SK		 2937 ql_dbg(ql_dbg_disc, vha, 0x2014,
2938 "Configure loop -- dpc flags = 0x%lx.\n", flags);
1da177e4
LT		 2939
2940 /*
2941 * If we have both an RSCN and PORT UPDATE pending then handle them
2942 * both at the same time.
2943 */
e315cd28
AC		 2944 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2945 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
1da177e4 2946
3064ff39
MH		 2947 qla2x00_get_data_rate(vha);
2948
1da177e4
LT		 2949 /* Determine what we need to do */
2950 if (ha->current_topology == ISP_CFG_FL &&
2951 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2952
1da177e4
LT		 2953 set_bit(RSCN_UPDATE, &flags);
2954
2955 } else if (ha->current_topology == ISP_CFG_F &&
2956 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2957
1da177e4
LT		 2958 set_bit(RSCN_UPDATE, &flags);
2959 clear_bit(LOCAL_LOOP_UPDATE, &flags);
21333b48
AV		 2960
2961 } else if (ha->current_topology == ISP_CFG_N) {
2962 clear_bit(RSCN_UPDATE, &flags);
1da177e4 2963
e315cd28 2964 } else if (!vha->flags.online ||
1da177e4
LT		 2965 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
2966
1da177e4
LT		 2967 set_bit(RSCN_UPDATE, &flags);
2968 set_bit(LOCAL_LOOP_UPDATE, &flags);
2969 }
2970
2971 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
7c3df132
SK		 2972 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
2973 ql_dbg(ql_dbg_disc, vha, 0x2015,
2974 "Loop resync needed, failing.\n");
1da177e4 2975 rval = QLA_FUNCTION_FAILED;
642ef983 2976 } else
e315cd28 2977 rval = qla2x00_configure_local_loop(vha);
1da177e4
LT		 2978 }
2979
2980 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
7c3df132
SK		 2981 if (LOOP_TRANSITION(vha)) {
2982 ql_dbg(ql_dbg_disc, vha, 0x201e,
2983 "Needs RSCN update and loop transition.\n");
1da177e4 2984 rval = QLA_FUNCTION_FAILED;
7c3df132 2985 }
e315cd28
AC		 2986 else
2987 rval = qla2x00_configure_fabric(vha);
1da177e4
LT		 2988 }
2989
2990 if (rval == QLA_SUCCESS) {
e315cd28
AC		 2991 if (atomic_read(&vha->loop_down_timer) ||
2992 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4
LT		 2993 rval = QLA_FUNCTION_FAILED;
2994 } else {
e315cd28 2995 atomic_set(&vha->loop_state, LOOP_READY);
7c3df132
SK		 2996 ql_dbg(ql_dbg_disc, vha, 0x2069,
2997 "LOOP READY.\n");
1da177e4
LT		 2998 }
2999 }
3000
3001 if (rval) {
7c3df132
SK		 3002 ql_dbg(ql_dbg_disc, vha, 0x206a,
3003 "%s *** FAILED ***.\n", __func__);
1da177e4 3004 } else {
7c3df132
SK		 3005 ql_dbg(ql_dbg_disc, vha, 0x206b,
3006 "%s: exiting normally.\n", __func__);
1da177e4
LT		 3007 }
3008
cc3ef7bc 3009 /* Restore state if a resync event occurred during processing */
e315cd28 3010 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4 3011 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
e315cd28 3012 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
f4658b6c 3013 if (test_bit(RSCN_UPDATE, &save_flags)) {
e315cd28 3014 set_bit(RSCN_UPDATE, &vha->dpc_flags);
f4658b6c 3015 }
1da177e4
LT		 3016 }
3017
3018 return (rval);
3019}
3020
3021
3022
3023/*
3024 * qla2x00_configure_local_loop
3025 * Updates Fibre Channel Device Database with local loop devices.
3026 *
3027 * Input:
3028 * ha = adapter block pointer.
3029 *
3030 * Returns:
3031 * 0 = success.
3032 */
3033static int
e315cd28 3034qla2x00_configure_local_loop(scsi_qla_host_t *vha)
1da177e4
LT		 3035{
3036 int rval, rval2;
3037 int found_devs;
3038 int found;
3039 fc_port_t *fcport, *new_fcport;
3040
3041 uint16_t index;
3042 uint16_t entries;
3043 char *id_iter;
3044 uint16_t loop_id;
3045 uint8_t domain, area, al_pa;
e315cd28 3046 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3047
3048 found_devs = 0;
3049 new_fcport = NULL;
642ef983 3050 entries = MAX_FIBRE_DEVICES_LOOP;
1da177e4 3051
1da177e4 3052 /* Get list of logged in devices. */
642ef983 3053 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
e315cd28 3054 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
1da177e4
LT		 3055 &entries);
3056 if (rval != QLA_SUCCESS)
3057 goto cleanup_allocation;
3058
7c3df132
SK		 3059 ql_dbg(ql_dbg_disc, vha, 0x2017,
3060 "Entries in ID list (%d).\n", entries);
3061 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
3062 (uint8_t *)ha->gid_list,
3063 entries * sizeof(struct gid_list_info));
1da177e4
LT		 3064
3065 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 3066 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3067 if (new_fcport == NULL) {
7c3df132
SK		 3068 ql_log(ql_log_warn, vha, 0x2018,
3069 "Memory allocation failed for fcport.\n");
1da177e4
LT		 3070 rval = QLA_MEMORY_ALLOC_FAILED;
3071 goto cleanup_allocation;
3072 }
3073 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
3074
3075 /*
3076 * Mark local devices that were present with FCF_DEVICE_LOST for now.
3077 */
e315cd28 3078 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3079 if (atomic_read(&fcport->state) == FCS_ONLINE &&
3080 fcport->port_type != FCT_BROADCAST &&
3081 (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3082
7c3df132
SK		 3083 ql_dbg(ql_dbg_disc, vha, 0x2019,
3084 "Marking port lost loop_id=0x%04x.\n",
3085 fcport->loop_id);
1da177e4 3086
ec426e10 3087 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3088 }
3089 }
3090
3091 /* Add devices to port list. */
3092 id_iter = (char *)ha->gid_list;
3093 for (index = 0; index < entries; index++) {
3094 domain = ((struct gid_list_info *)id_iter)->domain;
3095 area = ((struct gid_list_info *)id_iter)->area;
3096 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
abbd8870 3097 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1da177e4
LT		 3098 loop_id = (uint16_t)
3099 ((struct gid_list_info *)id_iter)->loop_id_2100;
abbd8870 3100 else
1da177e4
LT		 3101 loop_id = le16_to_cpu(
3102 ((struct gid_list_info *)id_iter)->loop_id);
abbd8870 3103 id_iter += ha->gid_list_info_size;
1da177e4
LT		 3104
3105 /* Bypass reserved domain fields. */
3106 if ((domain & 0xf0) == 0xf0)
3107 continue;
3108
3109 /* Bypass if not same domain and area of adapter. */
f7d289f6 3110 if (area && domain &&
e315cd28 3111 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
1da177e4
LT		 3112 continue;
3113
3114 /* Bypass invalid local loop ID. */
3115 if (loop_id > LAST_LOCAL_LOOP_ID)
3116 continue;
3117
370d550e
AE		 3118 memset(new_fcport, 0, sizeof(fc_port_t));
3119
1da177e4
LT		 3120 /* Fill in member data. */
3121 new_fcport->d_id.b.domain = domain;
3122 new_fcport->d_id.b.area = area;
3123 new_fcport->d_id.b.al_pa = al_pa;
3124 new_fcport->loop_id = loop_id;
e315cd28 3125 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
1da177e4 3126 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 3127 ql_dbg(ql_dbg_disc, vha, 0x201a,
3128 "Failed to retrieve fcport information "
3129 "-- get_port_database=%x, loop_id=0x%04x.\n",
3130 rval2, new_fcport->loop_id);
3131 ql_dbg(ql_dbg_disc, vha, 0x201b,
3132 "Scheduling resync.\n");
e315cd28 3133 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 3134 continue;
3135 }
3136
3137 /* Check for matching device in port list. */
3138 found = 0;
3139 fcport = NULL;
e315cd28 3140 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3141 if (memcmp(new_fcport->port_name, fcport->port_name,
3142 WWN_SIZE))
3143 continue;
3144
ddb9b126 3145 fcport->flags &= ~FCF_FABRIC_DEVICE;
1da177e4
LT		 3146 fcport->loop_id = new_fcport->loop_id;
3147 fcport->port_type = new_fcport->port_type;
3148 fcport->d_id.b24 = new_fcport->d_id.b24;
3149 memcpy(fcport->node_name, new_fcport->node_name,
3150 WWN_SIZE);
3151
3152 found++;
3153 break;
3154 }
3155
3156 if (!found) {
3157 /* New device, add to fcports list. */
e315cd28 3158 list_add_tail(&new_fcport->list, &vha->vp_fcports);
1da177e4
LT		 3159
3160 /* Allocate a new replacement fcport. */
3161 fcport = new_fcport;
e315cd28 3162 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3163 if (new_fcport == NULL) {
7c3df132
SK		 3164 ql_log(ql_log_warn, vha, 0x201c,
3165 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3166 rval = QLA_MEMORY_ALLOC_FAILED;
3167 goto cleanup_allocation;
3168 }
3169 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
3170 }
3171
d8b45213 3172 /* Base iIDMA settings on HBA port speed. */
a3cbdfad 3173 fcport->fp_speed = ha->link_data_rate;
d8b45213 3174
e315cd28 3175 qla2x00_update_fcport(vha, fcport);
1da177e4
LT		 3176
3177 found_devs++;
3178 }
3179
3180cleanup_allocation:
c9475cb0 3181 kfree(new_fcport);
1da177e4
LT		 3182
3183 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3184 ql_dbg(ql_dbg_disc, vha, 0x201d,
3185 "Configure local loop error exit: rval=%x.\n", rval);
1da177e4
LT		 3186 }
3187
1da177e4
LT		 3188 return (rval);
3189}
3190
d8b45213 3191static void
e315cd28 3192qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
d8b45213 3193{
d8b45213 3194 int rval;
93f2bd67 3195 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 3196 struct qla_hw_data *ha = vha->hw;
d8b45213 3197
c76f2c01 3198 if (!IS_IIDMA_CAPABLE(ha))
d8b45213
AV		 3199 return;
3200
c9afb9a2
GM		 3201 if (atomic_read(&fcport->state) != FCS_ONLINE)
3202 return;
3203
39bd9622
AV		 3204 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
3205 fcport->fp_speed > ha->link_data_rate)
d8b45213
AV		 3206 return;
3207
e315cd28 3208 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
a3cbdfad 3209 mb);
d8b45213 3210 if (rval != QLA_SUCCESS) {
7c3df132 3211 ql_dbg(ql_dbg_disc, vha, 0x2004,
7b833558
OK		 3212 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n",
3213 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]);
d8b45213 3214 } else {
7c3df132 3215 ql_dbg(ql_dbg_disc, vha, 0x2005,
7b833558 3216 "iIDMA adjusted to %s GB/s on %8phN.\n",
d0297c9a 3217 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
7b833558 3218 fcport->port_name);
d8b45213
AV		 3219 }
3220}
3221
23be331d 3222static void
e315cd28 3223qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
8482e118 3224{
3225 struct fc_rport_identifiers rport_ids;
bdf79621 3226 struct fc_rport *rport;
044d78e1 3227 unsigned long flags;
8482e118 3228
ac280b67 3229 qla2x00_rport_del(fcport);
8482e118 3230
f8b02a85
AV		 3231 rport_ids.node_name = wwn_to_u64(fcport->node_name);
3232 rport_ids.port_name = wwn_to_u64(fcport->port_name);
8482e118 3233 rport_ids.port_id = fcport->d_id.b.domain << 16 |
3234 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
77d74143 3235 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
e315cd28 3236 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
77d74143 3237 if (!rport) {
7c3df132
SK		 3238 ql_log(ql_log_warn, vha, 0x2006,
3239 "Unable to allocate fc remote port.\n");
77d74143
AV		 3240 return;
3241 }
2d70c103
NB		 3242 /*
3243 * Create target mode FC NEXUS in qla_target.c if target mode is
3244 * enabled..
3245 */
3246 qlt_fc_port_added(vha, fcport);
3247
044d78e1 3248 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
19a7b4ae 3249 *((fc_port_t **)rport->dd_data) = fcport;
044d78e1 3250 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
d97994dc 3251
ad3e0eda 3252 rport->supported_classes = fcport->supported_classes;
77d74143 3253
8482e118 3254 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
3255 if (fcport->port_type == FCT_INITIATOR)
3256 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
3257 if (fcport->port_type == FCT_TARGET)
3258 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
77d74143 3259 fc_remote_port_rolechg(rport, rport_ids.roles);
1da177e4
LT		 3260}
3261
23be331d
AB		 3262/*
3263 * qla2x00_update_fcport
3264 * Updates device on list.
3265 *
3266 * Input:
3267 * ha = adapter block pointer.
3268 * fcport = port structure pointer.
3269 *
3270 * Return:
3271 * 0 - Success
3272 * BIT_0 - error
3273 *
3274 * Context:
3275 * Kernel context.
3276 */
3277void
e315cd28 3278qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
23be331d 3279{
e315cd28 3280 fcport->vha = vha;
8ae6d9c7
GM		 3281
3282 if (IS_QLAFX00(vha->hw)) {
3283 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
3284 qla2x00_reg_remote_port(vha, fcport);
3285 return;
3286 }
23be331d 3287 fcport->login_retry = 0;
5ff1d584 3288 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
23be331d 3289
1f93da52 3290 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
e315cd28 3291 qla2x00_iidma_fcport(vha, fcport);
21090cbe 3292 qla24xx_update_fcport_fcp_prio(vha, fcport);
e315cd28 3293 qla2x00_reg_remote_port(vha, fcport);
23be331d
AB		 3294}
3295
1da177e4
LT		 3296/*
3297 * qla2x00_configure_fabric
3298 * Setup SNS devices with loop ID's.
3299 *
3300 * Input:
3301 * ha = adapter block pointer.
3302 *
3303 * Returns:
3304 * 0 = success.
3305 * BIT_0 = error
3306 */
3307static int
e315cd28 3308qla2x00_configure_fabric(scsi_qla_host_t *vha)
1da177e4 3309{
b3b02e6e 3310 int rval;
e452ceb6 3311 fc_port_t *fcport, *fcptemp;
1da177e4
LT		 3312 uint16_t next_loopid;
3313 uint16_t mb[MAILBOX_REGISTER_COUNT];
0107109e 3314 uint16_t loop_id;
1da177e4 3315 LIST_HEAD(new_fcports);
e315cd28
AC		 3316 struct qla_hw_data *ha = vha->hw;
3317 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3318
3319 /* If FL port exists, then SNS is present */
e428924c 3320 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3321 loop_id = NPH_F_PORT;
3322 else
3323 loop_id = SNS_FL_PORT;
e315cd28 3324 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
1da177e4 3325 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3326 ql_dbg(ql_dbg_disc, vha, 0x201f,
3327 "MBX_GET_PORT_NAME failed, No FL Port.\n");
1da177e4 3328
e315cd28 3329 vha->device_flags &= ~SWITCH_FOUND;
1da177e4
LT		 3330 return (QLA_SUCCESS);
3331 }
e315cd28 3332 vha->device_flags |= SWITCH_FOUND;
1da177e4 3333
1da177e4 3334 do {
cca5335c
AV		 3335 /* FDMI support. */
3336 if (ql2xfdmienable &&
e315cd28
AC		 3337 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
3338 qla2x00_fdmi_register(vha);
cca5335c 3339
1da177e4 3340 /* Ensure we are logged into the SNS. */
e428924c 3341 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3342 loop_id = NPH_SNS;
3343 else
3344 loop_id = SIMPLE_NAME_SERVER;
0b91d116
CD		 3345 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
3346 0xfc, mb, BIT_1|BIT_0);
3347 if (rval != QLA_SUCCESS) {
3348 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
e452ceb6 3349 return rval;
0b91d116 3350 }
1da177e4 3351 if (mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 3352 ql_dbg(ql_dbg_disc, vha, 0x2042,
3353 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
3354 "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
3355 mb[2], mb[6], mb[7]);
1da177e4
LT		 3356 return (QLA_SUCCESS);
3357 }
3358
e315cd28
AC		 3359 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
3360 if (qla2x00_rft_id(vha)) {
1da177e4 3361 /* EMPTY */
7c3df132
SK		 3362 ql_dbg(ql_dbg_disc, vha, 0x2045,
3363 "Register FC-4 TYPE failed.\n");
1da177e4 3364 }
e315cd28 3365 if (qla2x00_rff_id(vha)) {
1da177e4 3366 /* EMPTY */
7c3df132
SK		 3367 ql_dbg(ql_dbg_disc, vha, 0x2049,
3368 "Register FC-4 Features failed.\n");
1da177e4 3369 }
e315cd28 3370 if (qla2x00_rnn_id(vha)) {
1da177e4 3371 /* EMPTY */
7c3df132
SK		 3372 ql_dbg(ql_dbg_disc, vha, 0x204f,
3373 "Register Node Name failed.\n");
e315cd28 3374 } else if (qla2x00_rsnn_nn(vha)) {
1da177e4 3375 /* EMPTY */
7c3df132
SK		 3376 ql_dbg(ql_dbg_disc, vha, 0x2053,
3377 "Register Symobilic Node Name failed.\n");
1da177e4
LT		 3378 }
3379 }
3380
827210ba
JC		 3381#define QLA_FCPORT_SCAN 1
3382#define QLA_FCPORT_FOUND 2
3383
3384 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3385 fcport->scan_state = QLA_FCPORT_SCAN;
3386 }
3387
e315cd28 3388 rval = qla2x00_find_all_fabric_devs(vha, &new_fcports);
1da177e4
LT		 3389 if (rval != QLA_SUCCESS)
3390 break;
3391
e452ceb6
JC		 3392 /*
3393 * Logout all previous fabric devices marked lost, except
3394 * FCP2 devices.
3395 */
e315cd28
AC		 3396 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3397 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1da177e4
LT		 3398 break;
3399
3400 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
3401 continue;
3402
827210ba 3403 if (fcport->scan_state == QLA_FCPORT_SCAN &&
b3b02e6e 3404 atomic_read(&fcport->state) == FCS_ONLINE) {
e315cd28 3405 qla2x00_mark_device_lost(vha, fcport,
d97994dc 3406 ql2xplogiabsentdevice, 0);
1da177e4 3407 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3408 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
1da177e4
LT		 3409 fcport->port_type != FCT_INITIATOR &&
3410 fcport->port_type != FCT_BROADCAST) {
e315cd28 3411 ha->isp_ops->fabric_logout(vha,
1c7c6357
AV		 3412 fcport->loop_id,
3413 fcport->d_id.b.domain,
3414 fcport->d_id.b.area,
3415 fcport->d_id.b.al_pa);
1a5c69bf 3416 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3417 }
3418 }
e452ceb6 3419 }
1da177e4 3420
e452ceb6
JC		 3421 /* Starting free loop ID. */
3422 next_loopid = ha->min_external_loopid;
3423
3424 /*
3425 * Scan through our port list and login entries that need to be
3426 * logged in.
3427 */
3428 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3429 if (atomic_read(&vha->loop_down_timer) ||
3430 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3431 break;
3432
3433 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
3434 (fcport->flags & FCF_LOGIN_NEEDED) == 0)
3435 continue;
3436
3437 if (fcport->loop_id == FC_NO_LOOP_ID) {
3438 fcport->loop_id = next_loopid;
3439 rval = qla2x00_find_new_loop_id(
3440 base_vha, fcport);
3441 if (rval != QLA_SUCCESS) {
3442 /* Ran out of IDs to use */
3443 break;
1da177e4
LT		 3444 }
3445 }
e452ceb6
JC		 3446 /* Login and update database */
3447 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
3448 }
3449
3450 /* Exit if out of loop IDs. */
3451 if (rval != QLA_SUCCESS) {
3452 break;
3453 }
3454
3455 /*
3456 * Login and add the new devices to our port list.
3457 */
3458 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
3459 if (atomic_read(&vha->loop_down_timer) ||
3460 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3461 break;
3462
3463 /* Find a new loop ID to use. */
3464 fcport->loop_id = next_loopid;
3465 rval = qla2x00_find_new_loop_id(base_vha, fcport);
3466 if (rval != QLA_SUCCESS) {
3467 /* Ran out of IDs to use */
3468 break;
3469 }
1da177e4 3470
bdf79621 3471 /* Login and update database */
e315cd28 3472 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
e452ceb6
JC		 3473
3474 list_move_tail(&fcport->list, &vha->vp_fcports);
1da177e4
LT		 3475 }
3476 } while (0);
3477
e452ceb6
JC		 3478 /* Free all new device structures not processed. */
3479 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
3480 list_del(&fcport->list);
3481 kfree(fcport);
3482 }
3483
1da177e4 3484 if (rval) {
7c3df132
SK		 3485 ql_dbg(ql_dbg_disc, vha, 0x2068,
3486 "Configure fabric error exit rval=%d.\n", rval);
1da177e4
LT		 3487 }
3488
3489 return (rval);
3490}
3491
1da177e4
LT		 3492/*
3493 * qla2x00_find_all_fabric_devs
3494 *
3495 * Input:
3496 * ha = adapter block pointer.
3497 * dev = database device entry pointer.
3498 *
3499 * Returns:
3500 * 0 = success.
3501 *
3502 * Context:
3503 * Kernel context.
3504 */
3505static int
e315cd28
AC		 3506qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
3507 struct list_head *new_fcports)
1da177e4
LT		 3508{
3509 int rval;
3510 uint16_t loop_id;
3511 fc_port_t *fcport, *new_fcport, *fcptemp;
3512 int found;
3513
3514 sw_info_t *swl;
3515 int swl_idx;
3516 int first_dev, last_dev;
1516ef44 3517 port_id_t wrap = {}, nxt_d_id;
e315cd28 3518 struct qla_hw_data *ha = vha->hw;
bb4cf5b7 3519 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3520
3521 rval = QLA_SUCCESS;
3522
3523 /* Try GID_PT to get device list, else GAN. */
7a67735b 3524 if (!ha->swl)
642ef983 3525 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
7a67735b
AV		 3526 GFP_KERNEL);
3527 swl = ha->swl;
bbfbbbc1 3528 if (!swl) {
1da177e4 3529 /*EMPTY*/
7c3df132
SK		 3530 ql_dbg(ql_dbg_disc, vha, 0x2054,
3531 "GID_PT allocations failed, fallback on GA_NXT.\n");
1da177e4 3532 } else {
642ef983 3533 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
e315cd28 3534 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
1da177e4 3535 swl = NULL;
e315cd28 3536 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3537 swl = NULL;
e315cd28 3538 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3539 swl = NULL;
e5896bd5 3540 } else if (ql2xiidmaenable &&
e315cd28
AC		 3541 qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) {
3542 qla2x00_gpsc(vha, swl);
1da177e4 3543 }
e8c72ba5
CD		 3544
3545 /* If other queries succeeded probe for FC-4 type */
3546 if (swl)
3547 qla2x00_gff_id(vha, swl);
1da177e4
LT		 3548 }
3549 swl_idx = 0;
3550
3551 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 3552 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3553 if (new_fcport == NULL) {
7c3df132
SK		 3554 ql_log(ql_log_warn, vha, 0x205e,
3555 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3556 return (QLA_MEMORY_ALLOC_FAILED);
3557 }
3558 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
1da177e4
LT		 3559 /* Set start port ID scan at adapter ID. */
3560 first_dev = 1;
3561 last_dev = 0;
3562
3563 /* Starting free loop ID. */
e315cd28
AC		 3564 loop_id = ha->min_external_loopid;
3565 for (; loop_id <= ha->max_loop_id; loop_id++) {
3566 if (qla2x00_is_reserved_id(vha, loop_id))
1da177e4
LT		 3567 continue;
3568
3a6478df
GM		 3569 if (ha->current_topology == ISP_CFG_FL &&
3570 (atomic_read(&vha->loop_down_timer) ||
3571 LOOP_TRANSITION(vha))) {
bb2d52b2
AV		 3572 atomic_set(&vha->loop_down_timer, 0);
3573 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
3574 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1da177e4 3575 break;
bb2d52b2 3576 }
1da177e4
LT		 3577
3578 if (swl != NULL) {
3579 if (last_dev) {
3580 wrap.b24 = new_fcport->d_id.b24;
3581 } else {
3582 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
3583 memcpy(new_fcport->node_name,
3584 swl[swl_idx].node_name, WWN_SIZE);
3585 memcpy(new_fcport->port_name,
3586 swl[swl_idx].port_name, WWN_SIZE);
d8b45213
AV		 3587 memcpy(new_fcport->fabric_port_name,
3588 swl[swl_idx].fabric_port_name, WWN_SIZE);
3589 new_fcport->fp_speed = swl[swl_idx].fp_speed;
e8c72ba5 3590 new_fcport->fc4_type = swl[swl_idx].fc4_type;
1da177e4
LT		 3591
3592 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
3593 last_dev = 1;
3594 }
3595 swl_idx++;
3596 }
3597 } else {
3598 /* Send GA_NXT to the switch */
e315cd28 3599 rval = qla2x00_ga_nxt(vha, new_fcport);
1da177e4 3600 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3601 ql_log(ql_log_warn, vha, 0x2064,
3602 "SNS scan failed -- assuming "
3603 "zero-entry result.\n");
1da177e4
LT		 3604 list_for_each_entry_safe(fcport, fcptemp,
3605 new_fcports, list) {
3606 list_del(&fcport->list);
3607 kfree(fcport);
3608 }
3609 rval = QLA_SUCCESS;
3610 break;
3611 }
3612 }
3613
3614 /* If wrap on switch device list, exit. */
3615 if (first_dev) {
3616 wrap.b24 = new_fcport->d_id.b24;
3617 first_dev = 0;
3618 } else if (new_fcport->d_id.b24 == wrap.b24) {
7c3df132
SK		 3619 ql_dbg(ql_dbg_disc, vha, 0x2065,
3620 "Device wrap (%02x%02x%02x).\n",
3621 new_fcport->d_id.b.domain,
3622 new_fcport->d_id.b.area,
3623 new_fcport->d_id.b.al_pa);
1da177e4
LT		 3624 break;
3625 }
3626
2c3dfe3f 3627 /* Bypass if same physical adapter. */
e315cd28 3628 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
1da177e4
LT		 3629 continue;
3630
2c3dfe3f 3631 /* Bypass virtual ports of the same host. */
bb4cf5b7
CD		 3632 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24))
3633 continue;
2c3dfe3f 3634
f7d289f6
AV		 3635 /* Bypass if same domain and area of adapter. */
3636 if (((new_fcport->d_id.b24 & 0xffff00) ==
e315cd28 3637 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
f7d289f6
AV		 3638 ISP_CFG_FL)
3639 continue;
3640
1da177e4
LT		 3641 /* Bypass reserved domain fields. */
3642 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
3643 continue;
3644
e8c72ba5 3645 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
4da26e16
CD		 3646 if (ql2xgffidenable &&
3647 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
3648 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
e8c72ba5
CD		 3649 continue;
3650
1da177e4
LT		 3651 /* Locate matching device in database. */
3652 found = 0;
e315cd28 3653 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3654 if (memcmp(new_fcport->port_name, fcport->port_name,
3655 WWN_SIZE))
3656 continue;
3657
827210ba 3658 fcport->scan_state = QLA_FCPORT_FOUND;
b3b02e6e 3659
1da177e4
LT		 3660 found++;
3661
d8b45213
AV		 3662 /* Update port state. */
3663 memcpy(fcport->fabric_port_name,
3664 new_fcport->fabric_port_name, WWN_SIZE);
3665 fcport->fp_speed = new_fcport->fp_speed;
3666
1da177e4
LT		 3667 /*
3668 * If address the same and state FCS_ONLINE, nothing
3669 * changed.
3670 */
3671 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
3672 atomic_read(&fcport->state) == FCS_ONLINE) {
3673 break;
3674 }
3675
3676 /*
3677 * If device was not a fabric device before.
3678 */
3679 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3680 fcport->d_id.b24 = new_fcport->d_id.b24;
5f16b331 3681 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3682 fcport->flags |= (FCF_FABRIC_DEVICE |
3683 FCF_LOGIN_NEEDED);
1da177e4
LT		 3684 break;
3685 }
3686
3687 /*
3688 * Port ID changed or device was marked to be updated;
3689 * Log it out if still logged in and mark it for
3690 * relogin later.
3691 */
3692 fcport->d_id.b24 = new_fcport->d_id.b24;
3693 fcport->flags |= FCF_LOGIN_NEEDED;
3694 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3695 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
0eba25df 3696 (fcport->flags & FCF_ASYNC_SENT) == 0 &&
1da177e4
LT		 3697 fcport->port_type != FCT_INITIATOR &&
3698 fcport->port_type != FCT_BROADCAST) {
e315cd28 3699 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3700 fcport->d_id.b.domain, fcport->d_id.b.area,
3701 fcport->d_id.b.al_pa);
5f16b331 3702 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3703 }
3704
3705 break;
3706 }
3707
3708 if (found)
3709 continue;
1da177e4
LT		 3710 /* If device was not in our fcports list, then add it. */
3711 list_add_tail(&new_fcport->list, new_fcports);
3712
3713 /* Allocate a new replacement fcport. */
3714 nxt_d_id.b24 = new_fcport->d_id.b24;
e315cd28 3715 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3716 if (new_fcport == NULL) {
7c3df132
SK		 3717 ql_log(ql_log_warn, vha, 0x2066,
3718 "Memory allocation failed for fcport.\n");
1da177e4
LT		 3719 return (QLA_MEMORY_ALLOC_FAILED);
3720 }
3721 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
3722 new_fcport->d_id.b24 = nxt_d_id.b24;
3723 }
3724
c9475cb0 3725 kfree(new_fcport);
1da177e4 3726
1da177e4
LT		 3727 return (rval);
3728}
3729
3730/*
3731 * qla2x00_find_new_loop_id
3732 * Scan through our port list and find a new usable loop ID.
3733 *
3734 * Input:
3735 * ha: adapter state pointer.
3736 * dev: port structure pointer.
3737 *
3738 * Returns:
3739 * qla2x00 local function return status code.
3740 *
3741 * Context:
3742 * Kernel context.
3743 */
03bcfb57 3744int
e315cd28 3745qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
1da177e4
LT		 3746{
3747 int rval;
e315cd28 3748 struct qla_hw_data *ha = vha->hw;
feafb7b1 3749 unsigned long flags = 0;
1da177e4
LT		 3750
3751 rval = QLA_SUCCESS;
3752
5f16b331 3753 spin_lock_irqsave(&ha->vport_slock, flags);
1da177e4 3754
5f16b331
CD		 3755 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
3756 LOOPID_MAP_SIZE);
3757 if (dev->loop_id >= LOOPID_MAP_SIZE ||
3758 qla2x00_is_reserved_id(vha, dev->loop_id)) {
3759 dev->loop_id = FC_NO_LOOP_ID;
3760 rval = QLA_FUNCTION_FAILED;
3761 } else
3762 set_bit(dev->loop_id, ha->loop_id_map);
1da177e4 3763
5f16b331 3764 spin_unlock_irqrestore(&ha->vport_slock, flags);
1da177e4 3765
5f16b331
CD		 3766 if (rval == QLA_SUCCESS)
3767 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
3768 "Assigning new loopid=%x, portid=%x.\n",
3769 dev->loop_id, dev->d_id.b24);
3770 else
3771 ql_log(ql_log_warn, dev->vha, 0x2087,
3772 "No loop_id's available, portid=%x.\n",
3773 dev->d_id.b24);
1da177e4
LT		 3774
3775 return (rval);
3776}
3777
1da177e4
LT		 3778/*
3779 * qla2x00_fabric_dev_login
3780 * Login fabric target device and update FC port database.
3781 *
3782 * Input:
3783 * ha: adapter state pointer.
3784 * fcport: port structure list pointer.
3785 * next_loopid: contains value of a new loop ID that can be used
3786 * by the next login attempt.
3787 *
3788 * Returns:
3789 * qla2x00 local function return status code.
3790 *
3791 * Context:
3792 * Kernel context.
3793 */
3794static int
e315cd28 3795qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3796 uint16_t *next_loopid)
3797{
3798 int rval;
3799 int retry;
0107109e 3800 uint8_t opts;
e315cd28 3801 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3802
3803 rval = QLA_SUCCESS;
3804 retry = 0;
3805
ac280b67 3806 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584
AV		 3807 if (fcport->flags & FCF_ASYNC_SENT)
3808 return rval;
3809 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 3810 rval = qla2x00_post_async_login_work(vha, fcport, NULL);
3811 if (!rval)
3812 return rval;
3813 }
3814
5ff1d584 3815 fcport->flags &= ~FCF_ASYNC_SENT;
e315cd28 3816 rval = qla2x00_fabric_login(vha, fcport, next_loopid);
1da177e4 3817 if (rval == QLA_SUCCESS) {
f08b7251 3818 /* Send an ADISC to FCP2 devices.*/
0107109e 3819 opts = 0;
f08b7251 3820 if (fcport->flags & FCF_FCP2_DEVICE)
0107109e 3821 opts |= BIT_1;
e315cd28 3822 rval = qla2x00_get_port_database(vha, fcport, opts);
1da177e4 3823 if (rval != QLA_SUCCESS) {
e315cd28 3824 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3825 fcport->d_id.b.domain, fcport->d_id.b.area,
3826 fcport->d_id.b.al_pa);
e315cd28 3827 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4 3828 } else {
e315cd28 3829 qla2x00_update_fcport(vha, fcport);
1da177e4 3830 }
0b91d116
CD		 3831 } else {
3832 /* Retry Login. */
3833 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3834 }
3835
3836 return (rval);
3837}
3838
3839/*
3840 * qla2x00_fabric_login
3841 * Issue fabric login command.
3842 *
3843 * Input:
3844 * ha = adapter block pointer.
3845 * device = pointer to FC device type structure.
3846 *
3847 * Returns:
3848 * 0 - Login successfully
3849 * 1 - Login failed
3850 * 2 - Initiator device
3851 * 3 - Fatal error
3852 */
3853int
e315cd28 3854qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3855 uint16_t *next_loopid)
3856{
3857 int rval;
3858 int retry;
3859 uint16_t tmp_loopid;
3860 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 3861 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3862
3863 retry = 0;
3864 tmp_loopid = 0;
3865
3866 for (;;) {
7c3df132
SK		 3867 ql_dbg(ql_dbg_disc, vha, 0x2000,
3868 "Trying Fabric Login w/loop id 0x%04x for port "
3869 "%02x%02x%02x.\n",
3870 fcport->loop_id, fcport->d_id.b.domain,
3871 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3872
3873 /* Login fcport on switch. */
0b91d116 3874 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
1da177e4
LT		 3875 fcport->d_id.b.domain, fcport->d_id.b.area,
3876 fcport->d_id.b.al_pa, mb, BIT_0);
0b91d116
CD		 3877 if (rval != QLA_SUCCESS) {
3878 return rval;
3879 }
1da177e4
LT		 3880 if (mb[0] == MBS_PORT_ID_USED) {
3881 /*
3882 * Device has another loop ID. The firmware team
0107109e
AV		 3883 * recommends the driver perform an implicit login with
3884 * the specified ID again. The ID we just used is save
3885 * here so we return with an ID that can be tried by
3886 * the next login.
1da177e4
LT		 3887 */
3888 retry++;
3889 tmp_loopid = fcport->loop_id;
3890 fcport->loop_id = mb[1];
3891
7c3df132
SK		 3892 ql_dbg(ql_dbg_disc, vha, 0x2001,
3893 "Fabric Login: port in use - next loop "
3894 "id=0x%04x, port id= %02x%02x%02x.\n",
1da177e4 3895 fcport->loop_id, fcport->d_id.b.domain,
7c3df132 3896 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3897
3898 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
3899 /*
3900 * Login succeeded.
3901 */
3902 if (retry) {
3903 /* A retry occurred before. */
3904 *next_loopid = tmp_loopid;
3905 } else {
3906 /*
3907 * No retry occurred before. Just increment the
3908 * ID value for next login.
3909 */
3910 *next_loopid = (fcport->loop_id + 1);
3911 }
3912
3913 if (mb[1] & BIT_0) {
3914 fcport->port_type = FCT_INITIATOR;
3915 } else {
3916 fcport->port_type = FCT_TARGET;
3917 if (mb[1] & BIT_1) {
8474f3a0 3918 fcport->flags |= FCF_FCP2_DEVICE;
1da177e4
LT		 3919 }
3920 }
3921
ad3e0eda
AV		 3922 if (mb[10] & BIT_0)
3923 fcport->supported_classes |= FC_COS_CLASS2;
3924 if (mb[10] & BIT_1)
3925 fcport->supported_classes |= FC_COS_CLASS3;
3926
2d70c103
NB		 3927 if (IS_FWI2_CAPABLE(ha)) {
3928 if (mb[10] & BIT_7)
3929 fcport->flags |=
3930 FCF_CONF_COMP_SUPPORTED;
3931 }
3932
1da177e4
LT		 3933 rval = QLA_SUCCESS;
3934 break;
3935 } else if (mb[0] == MBS_LOOP_ID_USED) {
3936 /*
3937 * Loop ID already used, try next loop ID.
3938 */
3939 fcport->loop_id++;
e315cd28 3940 rval = qla2x00_find_new_loop_id(vha, fcport);
1da177e4
LT		 3941 if (rval != QLA_SUCCESS) {
3942 /* Ran out of loop IDs to use */
3943 break;
3944 }
3945 } else if (mb[0] == MBS_COMMAND_ERROR) {
3946 /*
3947 * Firmware possibly timed out during login. If NO
3948 * retries are left to do then the device is declared
3949 * dead.
3950 */
3951 *next_loopid = fcport->loop_id;
e315cd28 3952 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3953 fcport->d_id.b.domain, fcport->d_id.b.area,
3954 fcport->d_id.b.al_pa);
e315cd28 3955 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3956
3957 rval = 1;
3958 break;
3959 } else {
3960 /*
3961 * unrecoverable / not handled error
3962 */
7c3df132
SK		 3963 ql_dbg(ql_dbg_disc, vha, 0x2002,
3964 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
3965 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
3966 fcport->d_id.b.area, fcport->d_id.b.al_pa,
3967 fcport->loop_id, jiffies);
1da177e4
LT		 3968
3969 *next_loopid = fcport->loop_id;
e315cd28 3970 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3971 fcport->d_id.b.domain, fcport->d_id.b.area,
3972 fcport->d_id.b.al_pa);
5f16b331 3973 qla2x00_clear_loop_id(fcport);
0eedfcf0 3974 fcport->login_retry = 0;
1da177e4
LT		 3975
3976 rval = 3;
3977 break;
3978 }
3979 }
3980
3981 return (rval);
3982}
3983
3984/*
3985 * qla2x00_local_device_login
3986 * Issue local device login command.
3987 *
3988 * Input:
3989 * ha = adapter block pointer.
3990 * loop_id = loop id of device to login to.
3991 *
3992 * Returns (Where's the #define!!!!):
3993 * 0 - Login successfully
3994 * 1 - Login failed
3995 * 3 - Fatal error
3996 */
3997int
e315cd28 3998qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
1da177e4
LT		 3999{
4000 int rval;
4001 uint16_t mb[MAILBOX_REGISTER_COUNT];
4002
4003 memset(mb, 0, sizeof(mb));
e315cd28 4004 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
1da177e4
LT		 4005 if (rval == QLA_SUCCESS) {
4006 /* Interrogate mailbox registers for any errors */
4007 if (mb[0] == MBS_COMMAND_ERROR)
4008 rval = 1;
4009 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
4010 /* device not in PCB table */
4011 rval = 3;
4012 }
4013
4014 return (rval);
4015}
4016
4017/*
4018 * qla2x00_loop_resync
4019 * Resync with fibre channel devices.
4020 *
4021 * Input:
4022 * ha = adapter block pointer.
4023 *
4024 * Returns:
4025 * 0 = success
4026 */
4027int
e315cd28 4028qla2x00_loop_resync(scsi_qla_host_t *vha)
1da177e4 4029{
73208dfd 4030 int rval = QLA_SUCCESS;
1da177e4 4031 uint32_t wait_time;
67c2e93a
AC		 4032 struct req_que *req;
4033 struct rsp_que *rsp;
4034
7163ea81 4035 if (vha->hw->flags.cpu_affinity_enabled)
67c2e93a
AC		 4036 req = vha->hw->req_q_map[0];
4037 else
4038 req = vha->req;
4039 rsp = req->rsp;
1da177e4 4040
e315cd28
AC		 4041 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4042 if (vha->flags.online) {
4043 if (!(rval = qla2x00_fw_ready(vha))) {
1da177e4
LT		 4044 /* Wait at most MAX_TARGET RSCNs for a stable link. */
4045 wait_time = 256;
4046 do {
8ae6d9c7
GM		 4047 if (!IS_QLAFX00(vha->hw)) {
4048 /*
4049 * Issue a marker after FW becomes
4050 * ready.
4051 */
4052 qla2x00_marker(vha, req, rsp, 0, 0,
4053 MK_SYNC_ALL);
4054 vha->marker_needed = 0;
4055 }
1da177e4
LT		 4056
4057 /* Remap devices on Loop. */
e315cd28 4058 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4 4059
8ae6d9c7
GM		 4060 if (IS_QLAFX00(vha->hw))
4061 qlafx00_configure_devices(vha);
4062 else
4063 qla2x00_configure_loop(vha);
4064
1da177e4 4065 wait_time--;
e315cd28
AC		 4066 } while (!atomic_read(&vha->loop_down_timer) &&
4067 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
4068 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
4069 &vha->dpc_flags)));
1da177e4 4070 }
1da177e4
LT		 4071 }
4072
e315cd28 4073 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
1da177e4 4074 return (QLA_FUNCTION_FAILED);
1da177e4 4075
e315cd28 4076 if (rval)
7c3df132
SK		 4077 ql_dbg(ql_dbg_disc, vha, 0x206c,
4078 "%s *** FAILED ***.\n", __func__);
1da177e4
LT		 4079
4080 return (rval);
4081}
4082
579d12b5
SK		 4083/*
4084* qla2x00_perform_loop_resync
4085* Description: This function will set the appropriate flags and call
4086* qla2x00_loop_resync. If successful loop will be resynced
4087* Arguments : scsi_qla_host_t pointer
4088* returm : Success or Failure
4089*/
4090
4091int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
4092{
4093 int32_t rval = 0;
4094
4095 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
4096 /*Configure the flags so that resync happens properly*/
4097 atomic_set(&ha->loop_down_timer, 0);
4098 if (!(ha->device_flags & DFLG_NO_CABLE)) {
4099 atomic_set(&ha->loop_state, LOOP_UP);
4100 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
4101 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
4102 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
4103
4104 rval = qla2x00_loop_resync(ha);
4105 } else
4106 atomic_set(&ha->loop_state, LOOP_DEAD);
4107
4108 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
4109 }
4110
4111 return rval;
4112}
4113
d97994dc 4114void
67becc00 4115qla2x00_update_fcports(scsi_qla_host_t *base_vha)
d97994dc 4116{
4117 fc_port_t *fcport;
feafb7b1
AE		 4118 struct scsi_qla_host *vha;
4119 struct qla_hw_data *ha = base_vha->hw;
4120 unsigned long flags;
d97994dc 4121
feafb7b1 4122 spin_lock_irqsave(&ha->vport_slock, flags);
d97994dc 4123 /* Go with deferred removal of rport references. */
feafb7b1
AE		 4124 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
4125 atomic_inc(&vha->vref_count);
4126 list_for_each_entry(fcport, &vha->vp_fcports, list) {
8ae598d0 4127 if (fcport->drport &&
feafb7b1
AE		 4128 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
4129 spin_unlock_irqrestore(&ha->vport_slock, flags);
67becc00 4130 qla2x00_rport_del(fcport);
feafb7b1
AE		 4131 spin_lock_irqsave(&ha->vport_slock, flags);
4132 }
4133 }
4134 atomic_dec(&vha->vref_count);
4135 }
4136 spin_unlock_irqrestore(&ha->vport_slock, flags);
d97994dc 4137}
4138
7d613ac6
SV		 4139/* Assumes idc_lock always held on entry */
4140void
4141qla83xx_reset_ownership(scsi_qla_host_t *vha)
4142{
4143 struct qla_hw_data *ha = vha->hw;
4144 uint32_t drv_presence, drv_presence_mask;
4145 uint32_t dev_part_info1, dev_part_info2, class_type;
4146 uint32_t class_type_mask = 0x3;
4147 uint16_t fcoe_other_function = 0xffff, i;
4148
7ec0effd
AD		 4149 if (IS_QLA8044(ha)) {
4150 drv_presence = qla8044_rd_direct(vha,
4151 QLA8044_CRB_DRV_ACTIVE_INDEX);
4152 dev_part_info1 = qla8044_rd_direct(vha,
4153 QLA8044_CRB_DEV_PART_INFO_INDEX);
4154 dev_part_info2 = qla8044_rd_direct(vha,
4155 QLA8044_CRB_DEV_PART_INFO2);
4156 } else {
4157 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4158 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
4159 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
4160 }
7d613ac6
SV		 4161 for (i = 0; i < 8; i++) {
4162 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
4163 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
4164 (i != ha->portnum)) {
4165 fcoe_other_function = i;
4166 break;
4167 }
4168 }
4169 if (fcoe_other_function == 0xffff) {
4170 for (i = 0; i < 8; i++) {
4171 class_type = ((dev_part_info2 >> (i * 4)) &
4172 class_type_mask);
4173 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
4174 ((i + 8) != ha->portnum)) {
4175 fcoe_other_function = i + 8;
4176 break;
4177 }
4178 }
4179 }
4180 /*
4181 * Prepare drv-presence mask based on fcoe functions present.
4182 * However consider only valid physical fcoe function numbers (0-15).
4183 */
4184 drv_presence_mask = ~((1 << (ha->portnum)) |
4185 ((fcoe_other_function == 0xffff) ?
4186 0 : (1 << (fcoe_other_function))));
4187
4188 /* We are the reset owner iff:
4189 * - No other protocol drivers present.
4190 * - This is the lowest among fcoe functions. */
4191 if (!(drv_presence & drv_presence_mask) &&
4192 (ha->portnum < fcoe_other_function)) {
4193 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
4194 "This host is Reset owner.\n");
4195 ha->flags.nic_core_reset_owner = 1;
4196 }
4197}
4198
fa492630 4199static int
7d613ac6
SV		 4200__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
4201{
4202 int rval = QLA_SUCCESS;
4203 struct qla_hw_data *ha = vha->hw;
4204 uint32_t drv_ack;
4205
4206 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4207 if (rval == QLA_SUCCESS) {
4208 drv_ack |= (1 << ha->portnum);
4209 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4210 }
4211
4212 return rval;
4213}
4214
fa492630 4215static int
7d613ac6
SV		 4216__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
4217{
4218 int rval = QLA_SUCCESS;
4219 struct qla_hw_data *ha = vha->hw;
4220 uint32_t drv_ack;
4221
4222 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4223 if (rval == QLA_SUCCESS) {
4224 drv_ack &= ~(1 << ha->portnum);
4225 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4226 }
4227
4228 return rval;
4229}
4230
fa492630 4231static const char *
7d613ac6
SV		 4232qla83xx_dev_state_to_string(uint32_t dev_state)
4233{
4234 switch (dev_state) {
4235 case QLA8XXX_DEV_COLD:
4236 return "COLD/RE-INIT";
4237 case QLA8XXX_DEV_INITIALIZING:
4238 return "INITIALIZING";
4239 case QLA8XXX_DEV_READY:
4240 return "READY";
4241 case QLA8XXX_DEV_NEED_RESET:
4242 return "NEED RESET";
4243 case QLA8XXX_DEV_NEED_QUIESCENT:
4244 return "NEED QUIESCENT";
4245 case QLA8XXX_DEV_FAILED:
4246 return "FAILED";
4247 case QLA8XXX_DEV_QUIESCENT:
4248 return "QUIESCENT";
4249 default:
4250 return "Unknown";
4251 }
4252}
4253
4254/* Assumes idc-lock always held on entry */
4255void
4256qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
4257{
4258 struct qla_hw_data *ha = vha->hw;
4259 uint32_t idc_audit_reg = 0, duration_secs = 0;
4260
4261 switch (audit_type) {
4262 case IDC_AUDIT_TIMESTAMP:
4263 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
4264 idc_audit_reg = (ha->portnum) |
4265 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
4266 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4267 break;
4268
4269 case IDC_AUDIT_COMPLETION:
4270 duration_secs = ((jiffies_to_msecs(jiffies) -
4271 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
4272 idc_audit_reg = (ha->portnum) |
4273 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
4274 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4275 break;
4276
4277 default:
4278 ql_log(ql_log_warn, vha, 0xb078,
4279 "Invalid audit type specified.\n");
4280 break;
4281 }
4282}
4283
4284/* Assumes idc_lock always held on entry */
fa492630 4285static int
7d613ac6
SV		 4286qla83xx_initiating_reset(scsi_qla_host_t *vha)
4287{
4288 struct qla_hw_data *ha = vha->hw;
4289 uint32_t idc_control, dev_state;
4290
4291 __qla83xx_get_idc_control(vha, &idc_control);
4292 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
4293 ql_log(ql_log_info, vha, 0xb080,
4294 "NIC Core reset has been disabled. idc-control=0x%x\n",
4295 idc_control);
4296 return QLA_FUNCTION_FAILED;
4297 }
4298
4299 /* Set NEED-RESET iff in READY state and we are the reset-owner */
4300 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4301 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
4302 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
4303 QLA8XXX_DEV_NEED_RESET);
4304 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
4305 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
4306 } else {
4307 const char *state = qla83xx_dev_state_to_string(dev_state);
4308 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
4309
4310 /* SV: XXX: Is timeout required here? */
4311 /* Wait for IDC state change READY -> NEED_RESET */
4312 while (dev_state == QLA8XXX_DEV_READY) {
4313 qla83xx_idc_unlock(vha, 0);
4314 msleep(200);
4315 qla83xx_idc_lock(vha, 0);
4316 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4317 }
4318 }
4319
4320 /* Send IDC ack by writing to drv-ack register */
4321 __qla83xx_set_drv_ack(vha);
4322
4323 return QLA_SUCCESS;
4324}
4325
4326int
4327__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
4328{
4329 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4330}
4331
7d613ac6
SV		 4332int
4333__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
4334{
4335 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4336}
4337
fa492630 4338static int
7d613ac6
SV		 4339qla83xx_check_driver_presence(scsi_qla_host_t *vha)
4340{
4341 uint32_t drv_presence = 0;
4342 struct qla_hw_data *ha = vha->hw;
4343
4344 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4345 if (drv_presence & (1 << ha->portnum))
4346 return QLA_SUCCESS;
4347 else
4348 return QLA_TEST_FAILED;
4349}
4350
4351int
4352qla83xx_nic_core_reset(scsi_qla_host_t *vha)
4353{
4354 int rval = QLA_SUCCESS;
4355 struct qla_hw_data *ha = vha->hw;
4356
4357 ql_dbg(ql_dbg_p3p, vha, 0xb058,
4358 "Entered %s().\n", __func__);
4359
4360 if (vha->device_flags & DFLG_DEV_FAILED) {
4361 ql_log(ql_log_warn, vha, 0xb059,
4362 "Device in unrecoverable FAILED state.\n");
4363 return QLA_FUNCTION_FAILED;
4364 }
4365
4366 qla83xx_idc_lock(vha, 0);
4367
4368 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
4369 ql_log(ql_log_warn, vha, 0xb05a,
4370 "Function=0x%x has been removed from IDC participation.\n",
4371 ha->portnum);
4372 rval = QLA_FUNCTION_FAILED;
4373 goto exit;
4374 }
4375
4376 qla83xx_reset_ownership(vha);
4377
4378 rval = qla83xx_initiating_reset(vha);
4379
4380 /*
4381 * Perform reset if we are the reset-owner,
4382 * else wait till IDC state changes to READY/FAILED.
4383 */
4384 if (rval == QLA_SUCCESS) {
4385 rval = qla83xx_idc_state_handler(vha);
4386
4387 if (rval == QLA_SUCCESS)
4388 ha->flags.nic_core_hung = 0;
4389 __qla83xx_clear_drv_ack(vha);
4390 }
4391
4392exit:
4393 qla83xx_idc_unlock(vha, 0);
4394
4395 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
4396
4397 return rval;
4398}
4399
81178772
SK		 4400int
4401qla2xxx_mctp_dump(scsi_qla_host_t *vha)
4402{
4403 struct qla_hw_data *ha = vha->hw;
4404 int rval = QLA_FUNCTION_FAILED;
4405
4406 if (!IS_MCTP_CAPABLE(ha)) {
4407 /* This message can be removed from the final version */
4408 ql_log(ql_log_info, vha, 0x506d,
4409 "This board is not MCTP capable\n");
4410 return rval;
4411 }
4412
4413 if (!ha->mctp_dump) {
4414 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
4415 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
4416
4417 if (!ha->mctp_dump) {
4418 ql_log(ql_log_warn, vha, 0x506e,
4419 "Failed to allocate memory for mctp dump\n");
4420 return rval;
4421 }
4422 }
4423
4424#define MCTP_DUMP_STR_ADDR 0x00000000
4425 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
4426 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
4427 if (rval != QLA_SUCCESS) {
4428 ql_log(ql_log_warn, vha, 0x506f,
4429 "Failed to capture mctp dump\n");
4430 } else {
4431 ql_log(ql_log_info, vha, 0x5070,
4432 "Mctp dump capture for host (%ld/%p).\n",
4433 vha->host_no, ha->mctp_dump);
4434 ha->mctp_dumped = 1;
4435 }
4436
409ee0fe 4437 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
81178772
SK		 4438 ha->flags.nic_core_reset_hdlr_active = 1;
4439 rval = qla83xx_restart_nic_firmware(vha);
4440 if (rval)
4441 /* NIC Core reset failed. */
4442 ql_log(ql_log_warn, vha, 0x5071,
4443 "Failed to restart nic firmware\n");
4444 else
4445 ql_dbg(ql_dbg_p3p, vha, 0xb084,
4446 "Restarted NIC firmware successfully.\n");
4447 ha->flags.nic_core_reset_hdlr_active = 0;
4448 }
4449
4450 return rval;
4451
4452}
4453
579d12b5 4454/*
8fcd6b8b 4455* qla2x00_quiesce_io
579d12b5
SK		 4456* Description: This function will block the new I/Os
4457* Its not aborting any I/Os as context
4458* is not destroyed during quiescence
4459* Arguments: scsi_qla_host_t
4460* return : void
4461*/
4462void
8fcd6b8b 4463qla2x00_quiesce_io(scsi_qla_host_t *vha)
579d12b5
SK		 4464{
4465 struct qla_hw_data *ha = vha->hw;
4466 struct scsi_qla_host *vp;
4467
8fcd6b8b
CD		 4468 ql_dbg(ql_dbg_dpc, vha, 0x401d,
4469 "Quiescing I/O - ha=%p.\n", ha);
579d12b5
SK		 4470
4471 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
4472 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4473 atomic_set(&vha->loop_state, LOOP_DOWN);
4474 qla2x00_mark_all_devices_lost(vha, 0);
4475 list_for_each_entry(vp, &ha->vp_list, list)
8fcd6b8b 4476 qla2x00_mark_all_devices_lost(vp, 0);
579d12b5
SK		 4477 } else {
4478 if (!atomic_read(&vha->loop_down_timer))
4479 atomic_set(&vha->loop_down_timer,
4480 LOOP_DOWN_TIME);
4481 }
4482 /* Wait for pending cmds to complete */
4483 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
4484}
4485
a9083016
GM		 4486void
4487qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
4488{
4489 struct qla_hw_data *ha = vha->hw;
579d12b5 4490 struct scsi_qla_host *vp;
feafb7b1 4491 unsigned long flags;
6aef87be 4492 fc_port_t *fcport;
a9083016 4493
e46ef004
SK		 4494 /* For ISP82XX, driver waits for completion of the commands.
4495 * online flag should be set.
4496 */
7ec0effd 4497 if (!(IS_P3P_TYPE(ha)))
e46ef004 4498 vha->flags.online = 0;
a9083016
GM		 4499 ha->flags.chip_reset_done = 0;
4500 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2be21fa2 4501 vha->qla_stats.total_isp_aborts++;
a9083016 4502
7c3df132
SK		 4503 ql_log(ql_log_info, vha, 0x00af,
4504 "Performing ISP error recovery - ha=%p.\n", ha);
a9083016 4505
e46ef004
SK		 4506 /* For ISP82XX, reset_chip is just disabling interrupts.
4507 * Driver waits for the completion of the commands.
4508 * the interrupts need to be enabled.
4509 */
7ec0effd 4510 if (!(IS_P3P_TYPE(ha)))
a9083016
GM		 4511 ha->isp_ops->reset_chip(vha);
4512
4513 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
4514 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4515 atomic_set(&vha->loop_state, LOOP_DOWN);
4516 qla2x00_mark_all_devices_lost(vha, 0);
feafb7b1
AE		 4517
4518 spin_lock_irqsave(&ha->vport_slock, flags);
579d12b5 4519 list_for_each_entry(vp, &ha->vp_list, list) {
feafb7b1
AE		 4520 atomic_inc(&vp->vref_count);
4521 spin_unlock_irqrestore(&ha->vport_slock, flags);
4522
a9083016 4523 qla2x00_mark_all_devices_lost(vp, 0);
feafb7b1
AE		 4524
4525 spin_lock_irqsave(&ha->vport_slock, flags);
4526 atomic_dec(&vp->vref_count);
4527 }
4528 spin_unlock_irqrestore(&ha->vport_slock, flags);
a9083016
GM		 4529 } else {
4530 if (!atomic_read(&vha->loop_down_timer))
4531 atomic_set(&vha->loop_down_timer,
4532 LOOP_DOWN_TIME);
4533 }
4534
6aef87be
AV		 4535 /* Clear all async request states across all VPs. */
4536 list_for_each_entry(fcport, &vha->vp_fcports, list)
4537 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4538 spin_lock_irqsave(&ha->vport_slock, flags);
4539 list_for_each_entry(vp, &ha->vp_list, list) {
4540 atomic_inc(&vp->vref_count);
4541 spin_unlock_irqrestore(&ha->vport_slock, flags);
4542
4543 list_for_each_entry(fcport, &vp->vp_fcports, list)
4544 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4545
4546 spin_lock_irqsave(&ha->vport_slock, flags);
4547 atomic_dec(&vp->vref_count);
4548 }
4549 spin_unlock_irqrestore(&ha->vport_slock, flags);
4550
bddd2d65
LC		 4551 if (!ha->flags.eeh_busy) {
4552 /* Make sure for ISP 82XX IO DMA is complete */
7ec0effd 4553 if (IS_P3P_TYPE(ha)) {
7190575f 4554 qla82xx_chip_reset_cleanup(vha);
7c3df132
SK		 4555 ql_log(ql_log_info, vha, 0x00b4,
4556 "Done chip reset cleanup.\n");
a9083016 4557
e46ef004
SK		 4558 /* Done waiting for pending commands.
4559 * Reset the online flag.
4560 */
4561 vha->flags.online = 0;
4d78c973 4562 }
a9083016 4563
bddd2d65
LC		 4564 /* Requeue all commands in outstanding command list. */
4565 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
4566 }
a9083016
GM		 4567}
4568
1da177e4
LT		 4569/*
4570* qla2x00_abort_isp
4571* Resets ISP and aborts all outstanding commands.
4572*
4573* Input:
4574* ha = adapter block pointer.
4575*
4576* Returns:
4577* 0 = success
4578*/
4579int
e315cd28 4580qla2x00_abort_isp(scsi_qla_host_t *vha)
1da177e4 4581{
476e8978 4582 int rval;
1da177e4 4583 uint8_t status = 0;
e315cd28
AC		 4584 struct qla_hw_data *ha = vha->hw;
4585 struct scsi_qla_host *vp;
73208dfd 4586 struct req_que *req = ha->req_q_map[0];
feafb7b1 4587 unsigned long flags;
1da177e4 4588
e315cd28 4589 if (vha->flags.online) {
a9083016 4590 qla2x00_abort_isp_cleanup(vha);
1da177e4 4591
a6171297
SV		 4592 if (IS_QLA8031(ha)) {
4593 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
4594 "Clearing fcoe driver presence.\n");
4595 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
4596 ql_dbg(ql_dbg_p3p, vha, 0xb073,
4597 "Error while clearing DRV-Presence.\n");
4598 }
4599
85880801
AV		 4600 if (unlikely(pci_channel_offline(ha->pdev) &&
4601 ha->flags.pci_channel_io_perm_failure)) {
4602 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4603 status = 0;
4604 return status;
4605 }
4606
73208dfd 4607 ha->isp_ops->get_flash_version(vha, req->ring);
30c47662 4608
e315cd28 4609 ha->isp_ops->nvram_config(vha);
1da177e4 4610
e315cd28
AC		 4611 if (!qla2x00_restart_isp(vha)) {
4612 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4 4613
e315cd28 4614 if (!atomic_read(&vha->loop_down_timer)) {
1da177e4
LT		 4615 /*
4616 * Issue marker command only when we are going
4617 * to start the I/O .
4618 */
e315cd28 4619 vha->marker_needed = 1;
1da177e4
LT		 4620 }
4621
e315cd28 4622 vha->flags.online = 1;
1da177e4 4623
fd34f556 4624 ha->isp_ops->enable_intrs(ha);
1da177e4 4625
fa2a1ce5 4626 ha->isp_abort_cnt = 0;
e315cd28 4627 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
476e8978 4628
6246b8a1
GM		 4629 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
4630 qla2x00_get_fw_version(vha);
df613b96
AV		 4631 if (ha->fce) {
4632 ha->flags.fce_enabled = 1;
4633 memset(ha->fce, 0,
4634 fce_calc_size(ha->fce_bufs));
e315cd28 4635 rval = qla2x00_enable_fce_trace(vha,
df613b96
AV		 4636 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
4637 &ha->fce_bufs);
4638 if (rval) {
7c3df132 4639 ql_log(ql_log_warn, vha, 0x8033,
df613b96
AV		 4640 "Unable to reinitialize FCE "
4641 "(%d).\n", rval);
4642 ha->flags.fce_enabled = 0;
4643 }
4644 }
436a7b11
AV		 4645
4646 if (ha->eft) {
4647 memset(ha->eft, 0, EFT_SIZE);
e315cd28 4648 rval = qla2x00_enable_eft_trace(vha,
436a7b11
AV		 4649 ha->eft_dma, EFT_NUM_BUFFERS);
4650 if (rval) {
7c3df132 4651 ql_log(ql_log_warn, vha, 0x8034,
436a7b11
AV		 4652 "Unable to reinitialize EFT "
4653 "(%d).\n", rval);
4654 }
4655 }
1da177e4 4656 } else { /* failed the ISP abort */
e315cd28
AC		 4657 vha->flags.online = 1;
4658 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
1da177e4 4659 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 4660 ql_log(ql_log_fatal, vha, 0x8035,
4661 "ISP error recover failed - "
4662 "board disabled.\n");
fa2a1ce5 4663 /*
1da177e4
LT		 4664 * The next call disables the board
4665 * completely.
4666 */
e315cd28
AC		 4667 ha->isp_ops->reset_adapter(vha);
4668 vha->flags.online = 0;
1da177e4 4669 clear_bit(ISP_ABORT_RETRY,
e315cd28 4670 &vha->dpc_flags);
1da177e4
LT		 4671 status = 0;
4672 } else { /* schedule another ISP abort */
4673 ha->isp_abort_cnt--;
7c3df132
SK		 4674 ql_dbg(ql_dbg_taskm, vha, 0x8020,
4675 "ISP abort - retry remaining %d.\n",
4676 ha->isp_abort_cnt);
1da177e4
LT		 4677 status = 1;
4678 }
4679 } else {
4680 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 4681 ql_dbg(ql_dbg_taskm, vha, 0x8021,
4682 "ISP error recovery - retrying (%d) "
4683 "more times.\n", ha->isp_abort_cnt);
e315cd28 4684 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1da177e4
LT		 4685 status = 1;
4686 }
4687 }
fa2a1ce5 4688
1da177e4
LT		 4689 }
4690
e315cd28 4691 if (!status) {
7c3df132 4692 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
feafb7b1
AE		 4693
4694 spin_lock_irqsave(&ha->vport_slock, flags);
4695 list_for_each_entry(vp, &ha->vp_list, list) {
4696 if (vp->vp_idx) {
4697 atomic_inc(&vp->vref_count);
4698 spin_unlock_irqrestore(&ha->vport_slock, flags);
4699
e315cd28 4700 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 4701
4702 spin_lock_irqsave(&ha->vport_slock, flags);
4703 atomic_dec(&vp->vref_count);
4704 }
e315cd28 4705 }
feafb7b1
AE		 4706 spin_unlock_irqrestore(&ha->vport_slock, flags);
4707
7d613ac6
SV		 4708 if (IS_QLA8031(ha)) {
4709 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
4710 "Setting back fcoe driver presence.\n");
4711 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
4712 ql_dbg(ql_dbg_p3p, vha, 0xb074,
4713 "Error while setting DRV-Presence.\n");
4714 }
e315cd28 4715 } else {
d8424f68
JP		 4716 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
4717 __func__);
1da177e4
LT		 4718 }
4719
4720 return(status);
4721}
4722
4723/*
4724* qla2x00_restart_isp
4725* restarts the ISP after a reset
4726*
4727* Input:
4728* ha = adapter block pointer.
4729*
4730* Returns:
4731* 0 = success
4732*/
4733static int
e315cd28 4734qla2x00_restart_isp(scsi_qla_host_t *vha)
1da177e4 4735{
c6b2fca8 4736 int status = 0;
e315cd28 4737 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 4738 struct req_que *req = ha->req_q_map[0];
4739 struct rsp_que *rsp = ha->rsp_q_map[0];
2d70c103 4740 unsigned long flags;
1da177e4
LT		 4741
4742 /* If firmware needs to be loaded */
e315cd28
AC		 4743 if (qla2x00_isp_firmware(vha)) {
4744 vha->flags.online = 0;
4745 status = ha->isp_ops->chip_diag(vha);
4746 if (!status)
4747 status = qla2x00_setup_chip(vha);
1da177e4
LT		 4748 }
4749
e315cd28
AC		 4750 if (!status && !(status = qla2x00_init_rings(vha))) {
4751 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
2533cf67 4752 ha->flags.chip_reset_done = 1;
7108b76e 4753
73208dfd
AC		 4754 /* Initialize the queues in use */
4755 qla25xx_init_queues(ha);
4756
e315cd28
AC		 4757 status = qla2x00_fw_ready(vha);
4758 if (!status) {
0107109e 4759 /* Issue a marker after FW becomes ready. */
73208dfd 4760 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
0107109e 4761
e315cd28 4762 vha->flags.online = 1;
2d70c103
NB		 4763
4764 /*
4765 * Process any ATIO queue entries that came in
4766 * while we weren't online.
4767 */
4768 spin_lock_irqsave(&ha->hardware_lock, flags);
4769 if (qla_tgt_mode_enabled(vha))
4770 qlt_24xx_process_atio_queue(vha);
4771 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4772
7108b76e 4773 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 4774 }
4775
4776 /* if no cable then assume it's good */
e315cd28 4777 if ((vha->device_flags & DFLG_NO_CABLE))
1da177e4 4778 status = 0;
1da177e4
LT		 4779 }
4780 return (status);
4781}
4782
73208dfd
AC		 4783static int
4784qla25xx_init_queues(struct qla_hw_data *ha)
4785{
4786 struct rsp_que *rsp = NULL;
4787 struct req_que *req = NULL;
4788 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
4789 int ret = -1;
4790 int i;
4791
2afa19a9 4792 for (i = 1; i < ha->max_rsp_queues; i++) {
73208dfd
AC		 4793 rsp = ha->rsp_q_map[i];
4794 if (rsp) {
4795 rsp->options &= ~BIT_0;
618a7523 4796 ret = qla25xx_init_rsp_que(base_vha, rsp);
73208dfd 4797 if (ret != QLA_SUCCESS)
7c3df132
SK		 4798 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
4799 "%s Rsp que: %d init failed.\n",
4800 __func__, rsp->id);
73208dfd 4801 else
7c3df132
SK		 4802 ql_dbg(ql_dbg_init, base_vha, 0x0100,
4803 "%s Rsp que: %d inited.\n",
4804 __func__, rsp->id);
73208dfd 4805 }
2afa19a9
AC		 4806 }
4807 for (i = 1; i < ha->max_req_queues; i++) {
73208dfd
AC		 4808 req = ha->req_q_map[i];
4809 if (req) {
29bdccbe 4810 /* Clear outstanding commands array. */
73208dfd 4811 req->options &= ~BIT_0;
618a7523 4812 ret = qla25xx_init_req_que(base_vha, req);
73208dfd 4813 if (ret != QLA_SUCCESS)
7c3df132
SK		 4814 ql_dbg(ql_dbg_init, base_vha, 0x0101,
4815 "%s Req que: %d init failed.\n",
4816 __func__, req->id);
73208dfd 4817 else
7c3df132
SK		 4818 ql_dbg(ql_dbg_init, base_vha, 0x0102,
4819 "%s Req que: %d inited.\n",
4820 __func__, req->id);
73208dfd
AC		 4821 }
4822 }
4823 return ret;
4824}
4825
1da177e4
LT		 4826/*
4827* qla2x00_reset_adapter
4828* Reset adapter.
4829*
4830* Input:
4831* ha = adapter block pointer.
4832*/
abbd8870 4833void
e315cd28 4834qla2x00_reset_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 4835{
4836 unsigned long flags = 0;
e315cd28 4837 struct qla_hw_data *ha = vha->hw;
3d71644c 4838 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 4839
e315cd28 4840 vha->flags.online = 0;
fd34f556 4841 ha->isp_ops->disable_intrs(ha);
1da177e4 4842
1da177e4
LT		 4843 spin_lock_irqsave(&ha->hardware_lock, flags);
4844 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
4845 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4846 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
4847 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4848 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4849}
0107109e
AV		 4850
4851void
e315cd28 4852qla24xx_reset_adapter(scsi_qla_host_t *vha)
0107109e
AV		 4853{
4854 unsigned long flags = 0;
e315cd28 4855 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 4856 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
4857
7ec0effd 4858 if (IS_P3P_TYPE(ha))
a9083016
GM		 4859 return;
4860
e315cd28 4861 vha->flags.online = 0;
fd34f556 4862 ha->isp_ops->disable_intrs(ha);
0107109e
AV		 4863
4864 spin_lock_irqsave(&ha->hardware_lock, flags);
4865 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
4866 RD_REG_DWORD(&reg->hccr);
4867 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
4868 RD_REG_DWORD(&reg->hccr);
4869 spin_unlock_irqrestore(&ha->hardware_lock, flags);
09ff36d3
AV		 4870
4871 if (IS_NOPOLLING_TYPE(ha))
4872 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 4873}
4874
4e08df3f
DM		 4875/* On sparc systems, obtain port and node WWN from firmware
4876 * properties.
4877 */
e315cd28
AC		 4878static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
4879 struct nvram_24xx *nv)
4e08df3f
DM		 4880{
4881#ifdef CONFIG_SPARC
e315cd28 4882 struct qla_hw_data *ha = vha->hw;
4e08df3f 4883 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 4884 struct device_node *dp = pci_device_to_OF_node(pdev);
4885 const u8 *val;
4e08df3f
DM		 4886 int len;
4887
4888 val = of_get_property(dp, "port-wwn", &len);
4889 if (val && len >= WWN_SIZE)
4890 memcpy(nv->port_name, val, WWN_SIZE);
4891
4892 val = of_get_property(dp, "node-wwn", &len);
4893 if (val && len >= WWN_SIZE)
4894 memcpy(nv->node_name, val, WWN_SIZE);
4895#endif
4896}
4897
0107109e 4898int
e315cd28 4899qla24xx_nvram_config(scsi_qla_host_t *vha)
0107109e 4900{
4e08df3f 4901 int rval;
0107109e
AV		 4902 struct init_cb_24xx *icb;
4903 struct nvram_24xx *nv;
4904 uint32_t *dptr;
4905 uint8_t *dptr1, *dptr2;
4906 uint32_t chksum;
4907 uint16_t cnt;
e315cd28 4908 struct qla_hw_data *ha = vha->hw;
0107109e 4909
4e08df3f 4910 rval = QLA_SUCCESS;
0107109e 4911 icb = (struct init_cb_24xx *)ha->init_cb;
281afe19 4912 nv = ha->nvram;
0107109e
AV		 4913
4914 /* Determine NVRAM starting address. */
f73cb695 4915 if (ha->port_no == 0) {
e5b68a61
AC		 4916 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
4917 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
4918 } else {
0107109e 4919 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
6f641790 4920 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
4921 }
f73cb695 4922
e5b68a61
AC		 4923 ha->nvram_size = sizeof(struct nvram_24xx);
4924 ha->vpd_size = FA_NVRAM_VPD_SIZE;
0107109e 4925
281afe19
SJ		 4926 /* Get VPD data into cache */
4927 ha->vpd = ha->nvram + VPD_OFFSET;
e315cd28 4928 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
281afe19
SJ		 4929 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
4930
4931 /* Get NVRAM data into cache and calculate checksum. */
0107109e 4932 dptr = (uint32_t *)nv;
e315cd28 4933 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
0107109e
AV		 4934 ha->nvram_size);
4935 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
4936 chksum += le32_to_cpu(*dptr++);
4937
7c3df132
SK		 4938 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
4939 "Contents of NVRAM\n");
4940 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
4941 (uint8_t *)nv, ha->nvram_size);
0107109e
AV		 4942
4943 /* Bad NVRAM data, set defaults parameters. */
4944 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
4945 || nv->id[3] != ' ' ||
4946 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
4947 /* Reset NVRAM data. */
7c3df132 4948 ql_log(ql_log_warn, vha, 0x006b,
9e336520 4949 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132
SK		 4950 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
4951 ql_log(ql_log_warn, vha, 0x006c,
4952 "Falling back to functioning (yet invalid -- WWPN) "
4953 "defaults.\n");
4e08df3f
DM		 4954
4955 /*
4956 * Set default initialization control block.
4957 */
4958 memset(nv, 0, ha->nvram_size);
4959 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
4960 nv->version = __constant_cpu_to_le16(ICB_VERSION);
98aee70d 4961 nv->frame_payload_size = 2048;
4e08df3f
DM		 4962 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4963 nv->exchange_count = __constant_cpu_to_le16(0);
4964 nv->hard_address = __constant_cpu_to_le16(124);
4965 nv->port_name[0] = 0x21;
f73cb695 4966 nv->port_name[1] = 0x00 + ha->port_no + 1;
4e08df3f
DM		 4967 nv->port_name[2] = 0x00;
4968 nv->port_name[3] = 0xe0;
4969 nv->port_name[4] = 0x8b;
4970 nv->port_name[5] = 0x1c;
4971 nv->port_name[6] = 0x55;
4972 nv->port_name[7] = 0x86;
4973 nv->node_name[0] = 0x20;
4974 nv->node_name[1] = 0x00;
4975 nv->node_name[2] = 0x00;
4976 nv->node_name[3] = 0xe0;
4977 nv->node_name[4] = 0x8b;
4978 nv->node_name[5] = 0x1c;
4979 nv->node_name[6] = 0x55;
4980 nv->node_name[7] = 0x86;
e315cd28 4981 qla24xx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 4982 nv->login_retry_count = __constant_cpu_to_le16(8);
4983 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
4984 nv->login_timeout = __constant_cpu_to_le16(0);
4985 nv->firmware_options_1 =
4986 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
4987 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
4988 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
4989 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
4990 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
4991 nv->efi_parameters = __constant_cpu_to_le32(0);
4992 nv->reset_delay = 5;
4993 nv->max_luns_per_target = __constant_cpu_to_le16(128);
4994 nv->port_down_retry_count = __constant_cpu_to_le16(30);
4995 nv->link_down_timeout = __constant_cpu_to_le16(30);
4996
4997 rval = 1;
0107109e
AV		 4998 }
4999
2d70c103
NB		 5000 if (!qla_ini_mode_enabled(vha)) {
5001 /* Don't enable full login after initial LIP */
5002 nv->firmware_options_1 &= __constant_cpu_to_le32(~BIT_13);
5003 /* Don't enable LIP full login for initiator */
5004 nv->host_p &= __constant_cpu_to_le32(~BIT_10);
5005 }
5006
5007 qlt_24xx_config_nvram_stage1(vha, nv);
5008
0107109e 5009 /* Reset Initialization control block */
e315cd28 5010 memset(icb, 0, ha->init_cb_size);
0107109e
AV		 5011
5012 /* Copy 1st segment. */
5013 dptr1 = (uint8_t *)icb;
5014 dptr2 = (uint8_t *)&nv->version;
5015 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
5016 while (cnt--)
5017 *dptr1++ = *dptr2++;
5018
5019 icb->login_retry_count = nv->login_retry_count;
3ea66e28 5020 icb->link_down_on_nos = nv->link_down_on_nos;
0107109e
AV		 5021
5022 /* Copy 2nd segment. */
5023 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
5024 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
5025 cnt = (uint8_t *)&icb->reserved_3 -
5026 (uint8_t *)&icb->interrupt_delay_timer;
5027 while (cnt--)
5028 *dptr1++ = *dptr2++;
5029
5030 /*
5031 * Setup driver NVRAM options.
5032 */
e315cd28 5033 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9bb9fcf2 5034 "QLA2462");
0107109e 5035
2d70c103
NB		 5036 qlt_24xx_config_nvram_stage2(vha, icb);
5037
5341e868 5038 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
2d70c103 5039 /* Use alternate WWN? */
5341e868
AV		 5040 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
5041 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
5042 }
5043
0107109e 5044 /* Prepare nodename */
fd0e7e4d 5045 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
0107109e
AV		 5046 /*
5047 * Firmware will apply the following mask if the nodename was
5048 * not provided.
5049 */
5050 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
5051 icb->node_name[0] &= 0xF0;
5052 }
5053
5054 /* Set host adapter parameters. */
5055 ha->flags.disable_risc_code_load = 0;
0c8c39af
AV		 5056 ha->flags.enable_lip_reset = 0;
5057 ha->flags.enable_lip_full_login =
5058 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
5059 ha->flags.enable_target_reset =
5060 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
0107109e 5061 ha->flags.enable_led_scheme = 0;
d4c760c2 5062 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
0107109e 5063
fd0e7e4d
AV		 5064 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
5065 (BIT_6 | BIT_5 | BIT_4)) >> 4;
0107109e
AV		 5066
5067 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
5068 sizeof(ha->fw_seriallink_options24));
5069
5070 /* save HBA serial number */
5071 ha->serial0 = icb->port_name[5];
5072 ha->serial1 = icb->port_name[6];
5073 ha->serial2 = icb->port_name[7];
e315cd28
AC		 5074 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
5075 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
0107109e 5076
bc8fb3cb 5077 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5078
0107109e
AV		 5079 ha->retry_count = le16_to_cpu(nv->login_retry_count);
5080
5081 /* Set minimum login_timeout to 4 seconds. */
5082 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
5083 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
5084 if (le16_to_cpu(nv->login_timeout) < 4)
5085 nv->login_timeout = __constant_cpu_to_le16(4);
5086 ha->login_timeout = le16_to_cpu(nv->login_timeout);
c6852c4c 5087 icb->login_timeout = nv->login_timeout;
0107109e 5088
00a537b8
AV		 5089 /* Set minimum RATOV to 100 tenths of a second. */
5090 ha->r_a_tov = 100;
0107109e
AV		 5091
5092 ha->loop_reset_delay = nv->reset_delay;
5093
5094 /* Link Down Timeout = 0:
5095 *
5096 * When Port Down timer expires we will start returning
5097 * I/O's to OS with "DID_NO_CONNECT".
5098 *
5099 * Link Down Timeout != 0:
5100 *
5101 * The driver waits for the link to come up after link down
5102 * before returning I/Os to OS with "DID_NO_CONNECT".
5103 */
5104 if (le16_to_cpu(nv->link_down_timeout) == 0) {
5105 ha->loop_down_abort_time =
5106 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
5107 } else {
5108 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
5109 ha->loop_down_abort_time =
5110 (LOOP_DOWN_TIME - ha->link_down_timeout);
5111 }
5112
5113 /* Need enough time to try and get the port back. */
5114 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
5115 if (qlport_down_retry)
5116 ha->port_down_retry_count = qlport_down_retry;
5117
5118 /* Set login_retry_count */
5119 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
5120 if (ha->port_down_retry_count ==
5121 le16_to_cpu(nv->port_down_retry_count) &&
5122 ha->port_down_retry_count > 3)
5123 ha->login_retry_count = ha->port_down_retry_count;
5124 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
5125 ha->login_retry_count = ha->port_down_retry_count;
5126 if (ql2xloginretrycount)
5127 ha->login_retry_count = ql2xloginretrycount;
5128
4fdfefe5 5129 /* Enable ZIO. */
e315cd28 5130 if (!vha->flags.init_done) {
4fdfefe5
AV		 5131 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
5132 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
5133 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
5134 le16_to_cpu(icb->interrupt_delay_timer): 2;
5135 }
5136 icb->firmware_options_2 &= __constant_cpu_to_le32(
5137 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
e315cd28 5138 vha->flags.process_response_queue = 0;
4fdfefe5 5139 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d 5140 ha->zio_mode = QLA_ZIO_MODE_6;
5141
7c3df132 5142 ql_log(ql_log_info, vha, 0x006f,
4fdfefe5
AV		 5143 "ZIO mode %d enabled; timer delay (%d us).\n",
5144 ha->zio_mode, ha->zio_timer * 100);
5145
5146 icb->firmware_options_2 |= cpu_to_le32(
5147 (uint32_t)ha->zio_mode);
5148 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
e315cd28 5149 vha->flags.process_response_queue = 1;
4fdfefe5
AV		 5150 }
5151
4e08df3f 5152 if (rval) {
7c3df132
SK		 5153 ql_log(ql_log_warn, vha, 0x0070,
5154 "NVRAM configuration failed.\n");
4e08df3f
DM		 5155 }
5156 return (rval);
0107109e
AV		 5157}
5158
413975a0 5159static int
cbc8eb67
AV		 5160qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
5161 uint32_t faddr)
d1c61909 5162{
73208dfd 5163 int rval = QLA_SUCCESS;
d1c61909 5164 int segments, fragment;
d1c61909
AV		 5165 uint32_t *dcode, dlen;
5166 uint32_t risc_addr;
5167 uint32_t risc_size;
5168 uint32_t i;
e315cd28 5169 struct qla_hw_data *ha = vha->hw;
73208dfd 5170 struct req_que *req = ha->req_q_map[0];
eaac30be 5171
7c3df132 5172 ql_dbg(ql_dbg_init, vha, 0x008b,
cfb0919c 5173 "FW: Loading firmware from flash (%x).\n", faddr);
eaac30be 5174
d1c61909
AV		 5175 rval = QLA_SUCCESS;
5176
5177 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5178 dcode = (uint32_t *)req->ring;
d1c61909
AV		 5179 *srisc_addr = 0;
5180
5181 /* Validate firmware image by checking version. */
e315cd28 5182 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
d1c61909
AV		 5183 for (i = 0; i < 4; i++)
5184 dcode[i] = be32_to_cpu(dcode[i]);
5185 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5186 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5187 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5188 dcode[3] == 0)) {
7c3df132
SK		 5189 ql_log(ql_log_fatal, vha, 0x008c,
5190 "Unable to verify the integrity of flash firmware "
5191 "image.\n");
5192 ql_log(ql_log_fatal, vha, 0x008d,
5193 "Firmware data: %08x %08x %08x %08x.\n",
5194 dcode[0], dcode[1], dcode[2], dcode[3]);
d1c61909
AV		 5195
5196 return QLA_FUNCTION_FAILED;
5197 }
5198
5199 while (segments && rval == QLA_SUCCESS) {
5200 /* Read segment's load information. */
e315cd28 5201 qla24xx_read_flash_data(vha, dcode, faddr, 4);
d1c61909
AV		 5202
5203 risc_addr = be32_to_cpu(dcode[2]);
5204 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5205 risc_size = be32_to_cpu(dcode[3]);
5206
5207 fragment = 0;
5208 while (risc_size > 0 && rval == QLA_SUCCESS) {
5209 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5210 if (dlen > risc_size)
5211 dlen = risc_size;
5212
7c3df132
SK		 5213 ql_dbg(ql_dbg_init, vha, 0x008e,
5214 "Loading risc segment@ risc addr %x "
5215 "number of dwords 0x%x offset 0x%x.\n",
5216 risc_addr, dlen, faddr);
d1c61909 5217
e315cd28 5218 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
d1c61909
AV		 5219 for (i = 0; i < dlen; i++)
5220 dcode[i] = swab32(dcode[i]);
5221
73208dfd 5222 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
d1c61909
AV		 5223 dlen);
5224 if (rval) {
7c3df132
SK		 5225 ql_log(ql_log_fatal, vha, 0x008f,
5226 "Failed to load segment %d of firmware.\n",
5227 fragment);
d1c61909
AV		 5228 break;
5229 }
5230
5231 faddr += dlen;
5232 risc_addr += dlen;
5233 risc_size -= dlen;
5234 fragment++;
5235 }
5236
5237 /* Next segment. */
5238 segments--;
5239 }
5240
f73cb695
CD		 5241 if (!IS_QLA27XX(ha))
5242 return rval;
5243
5244 if (ha->fw_dump_template)
5245 vfree(ha->fw_dump_template);
5246 ha->fw_dump_template = NULL;
5247 ha->fw_dump_template_len = 0;
5248
5249 ql_dbg(ql_dbg_init, vha, 0x0161,
5250 "Loading fwdump template from %x\n", faddr);
5251 qla24xx_read_flash_data(vha, dcode, faddr, 7);
5252 risc_size = be32_to_cpu(dcode[2]);
5253 ql_dbg(ql_dbg_init, vha, 0x0162,
5254 "-> array size %x dwords\n", risc_size);
5255 if (risc_size == 0 || risc_size == ~0)
5256 goto default_template;
5257
5258 dlen = (risc_size - 8) * sizeof(*dcode);
5259 ql_dbg(ql_dbg_init, vha, 0x0163,
5260 "-> template allocating %x bytes...\n", dlen);
5261 ha->fw_dump_template = vmalloc(dlen);
5262 if (!ha->fw_dump_template) {
5263 ql_log(ql_log_warn, vha, 0x0164,
5264 "Failed fwdump template allocate %x bytes.\n", risc_size);
5265 goto default_template;
5266 }
5267
5268 faddr += 7;
5269 risc_size -= 8;
5270 dcode = ha->fw_dump_template;
5271 qla24xx_read_flash_data(vha, dcode, faddr, risc_size);
5272 for (i = 0; i < risc_size; i++)
5273 dcode[i] = le32_to_cpu(dcode[i]);
5274
5275 if (!qla27xx_fwdt_template_valid(dcode)) {
5276 ql_log(ql_log_warn, vha, 0x0165,
5277 "Failed fwdump template validate\n");
5278 goto default_template;
5279 }
5280
5281 dlen = qla27xx_fwdt_template_size(dcode);
5282 ql_dbg(ql_dbg_init, vha, 0x0166,
5283 "-> template size %x bytes\n", dlen);
5284 if (dlen > risc_size * sizeof(*dcode)) {
5285 ql_log(ql_log_warn, vha, 0x0167,
97ea702b
CD		 5286 "Failed fwdump template exceeds array by %x bytes\n",
5287 (uint32_t)(dlen - risc_size * sizeof(*dcode)));
f73cb695
CD		 5288 goto default_template;
5289 }
5290 ha->fw_dump_template_len = dlen;
5291 return rval;
5292
5293default_template:
5294 ql_log(ql_log_warn, vha, 0x0168, "Using default fwdump template\n");
5295 if (ha->fw_dump_template)
5296 vfree(ha->fw_dump_template);
5297 ha->fw_dump_template = NULL;
5298 ha->fw_dump_template_len = 0;
5299
5300 dlen = qla27xx_fwdt_template_default_size();
5301 ql_dbg(ql_dbg_init, vha, 0x0169,
5302 "-> template allocating %x bytes...\n", dlen);
5303 ha->fw_dump_template = vmalloc(dlen);
5304 if (!ha->fw_dump_template) {
5305 ql_log(ql_log_warn, vha, 0x016a,
5306 "Failed fwdump template allocate %x bytes.\n", risc_size);
5307 goto failed_template;
5308 }
5309
5310 dcode = ha->fw_dump_template;
5311 risc_size = dlen / sizeof(*dcode);
5312 memcpy(dcode, qla27xx_fwdt_template_default(), dlen);
5313 for (i = 0; i < risc_size; i++)
5314 dcode[i] = be32_to_cpu(dcode[i]);
5315
5316 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
5317 ql_log(ql_log_warn, vha, 0x016b,
5318 "Failed fwdump template validate\n");
5319 goto failed_template;
5320 }
5321
5322 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
5323 ql_dbg(ql_dbg_init, vha, 0x016c,
5324 "-> template size %x bytes\n", dlen);
5325 ha->fw_dump_template_len = dlen;
5326 return rval;
5327
5328failed_template:
5329 ql_log(ql_log_warn, vha, 0x016d, "Failed default fwdump template\n");
5330 if (ha->fw_dump_template)
5331 vfree(ha->fw_dump_template);
5332 ha->fw_dump_template = NULL;
5333 ha->fw_dump_template_len = 0;
d1c61909
AV		 5334 return rval;
5335}
5336
e9454a88 5337#define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
d1c61909 5338
0107109e 5339int
e315cd28 5340qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5433383e
AV		 5341{
5342 int rval;
5343 int i, fragment;
5344 uint16_t *wcode, *fwcode;
5345 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
5346 struct fw_blob *blob;
e315cd28 5347 struct qla_hw_data *ha = vha->hw;
73208dfd 5348 struct req_que *req = ha->req_q_map[0];
5433383e
AV		 5349
5350 /* Load firmware blob. */
e315cd28 5351 blob = qla2x00_request_firmware(vha);
5433383e 5352 if (!blob) {
7c3df132
SK		 5353 ql_log(ql_log_info, vha, 0x0083,
5354 "Fimware image unavailable.\n");
5355 ql_log(ql_log_info, vha, 0x0084,
5356 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5433383e
AV		 5357 return QLA_FUNCTION_FAILED;
5358 }
5359
5360 rval = QLA_SUCCESS;
5361
73208dfd 5362 wcode = (uint16_t *)req->ring;
5433383e
AV		 5363 *srisc_addr = 0;
5364 fwcode = (uint16_t *)blob->fw->data;
5365 fwclen = 0;
5366
5367 /* Validate firmware image by checking version. */
5368 if (blob->fw->size < 8 * sizeof(uint16_t)) {
7c3df132
SK		 5369 ql_log(ql_log_fatal, vha, 0x0085,
5370 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e
AV		 5371 blob->fw->size);
5372 goto fail_fw_integrity;
5373 }
5374 for (i = 0; i < 4; i++)
5375 wcode[i] = be16_to_cpu(fwcode[i + 4]);
5376 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
5377 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
5378 wcode[2] == 0 && wcode[3] == 0)) {
7c3df132
SK		 5379 ql_log(ql_log_fatal, vha, 0x0086,
5380 "Unable to verify integrity of firmware image.\n");
5381 ql_log(ql_log_fatal, vha, 0x0087,
5382 "Firmware data: %04x %04x %04x %04x.\n",
5383 wcode[0], wcode[1], wcode[2], wcode[3]);
5433383e
AV		 5384 goto fail_fw_integrity;
5385 }
5386
5387 seg = blob->segs;
5388 while (*seg && rval == QLA_SUCCESS) {
5389 risc_addr = *seg;
5390 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
5391 risc_size = be16_to_cpu(fwcode[3]);
5392
5393 /* Validate firmware image size. */
5394 fwclen += risc_size * sizeof(uint16_t);
5395 if (blob->fw->size < fwclen) {
7c3df132 5396 ql_log(ql_log_fatal, vha, 0x0088,
5433383e 5397 "Unable to verify integrity of firmware image "
7c3df132 5398 "(%Zd).\n", blob->fw->size);
5433383e
AV		 5399 goto fail_fw_integrity;
5400 }
5401
5402 fragment = 0;
5403 while (risc_size > 0 && rval == QLA_SUCCESS) {
5404 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
5405 if (wlen > risc_size)
5406 wlen = risc_size;
7c3df132
SK		 5407 ql_dbg(ql_dbg_init, vha, 0x0089,
5408 "Loading risc segment@ risc addr %x number of "
5409 "words 0x%x.\n", risc_addr, wlen);
5433383e
AV		 5410
5411 for (i = 0; i < wlen; i++)
5412 wcode[i] = swab16(fwcode[i]);
5413
73208dfd 5414 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5433383e
AV		 5415 wlen);
5416 if (rval) {
7c3df132
SK		 5417 ql_log(ql_log_fatal, vha, 0x008a,
5418 "Failed to load segment %d of firmware.\n",
5419 fragment);
5433383e
AV		 5420 break;
5421 }
5422
5423 fwcode += wlen;
5424 risc_addr += wlen;
5425 risc_size -= wlen;
5426 fragment++;
5427 }
5428
5429 /* Next segment. */
5430 seg++;
5431 }
5432 return rval;
5433
5434fail_fw_integrity:
5435 return QLA_FUNCTION_FAILED;
5436}
5437
eaac30be
AV		 5438static int
5439qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
0107109e
AV		 5440{
5441 int rval;
5442 int segments, fragment;
5443 uint32_t *dcode, dlen;
5444 uint32_t risc_addr;
5445 uint32_t risc_size;
5446 uint32_t i;
5433383e 5447 struct fw_blob *blob;
f73cb695
CD		 5448 const uint32_t *fwcode;
5449 uint32_t fwclen;
e315cd28 5450 struct qla_hw_data *ha = vha->hw;
73208dfd 5451 struct req_que *req = ha->req_q_map[0];
0107109e 5452
5433383e 5453 /* Load firmware blob. */
e315cd28 5454 blob = qla2x00_request_firmware(vha);
5433383e 5455 if (!blob) {
7c3df132
SK		 5456 ql_log(ql_log_warn, vha, 0x0090,
5457 "Fimware image unavailable.\n");
5458 ql_log(ql_log_warn, vha, 0x0091,
5459 "Firmware images can be retrieved from: "
5460 QLA_FW_URL ".\n");
d1c61909 5461
eaac30be 5462 return QLA_FUNCTION_FAILED;
0107109e
AV		 5463 }
5464
cfb0919c
CD		 5465 ql_dbg(ql_dbg_init, vha, 0x0092,
5466 "FW: Loading via request-firmware.\n");
eaac30be 5467
0107109e
AV		 5468 rval = QLA_SUCCESS;
5469
5470 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5471 dcode = (uint32_t *)req->ring;
0107109e 5472 *srisc_addr = 0;
5433383e 5473 fwcode = (uint32_t *)blob->fw->data;
0107109e
AV		 5474 fwclen = 0;
5475
5476 /* Validate firmware image by checking version. */
5433383e 5477 if (blob->fw->size < 8 * sizeof(uint32_t)) {
7c3df132
SK		 5478 ql_log(ql_log_fatal, vha, 0x0093,
5479 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e 5480 blob->fw->size);
f73cb695 5481 return QLA_FUNCTION_FAILED;
0107109e
AV		 5482 }
5483 for (i = 0; i < 4; i++)
5484 dcode[i] = be32_to_cpu(fwcode[i + 4]);
5485 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5486 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5487 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5488 dcode[3] == 0)) {
7c3df132
SK		 5489 ql_log(ql_log_fatal, vha, 0x0094,
5490 "Unable to verify integrity of firmware image (%Zd).\n",
5491 blob->fw->size);
5492 ql_log(ql_log_fatal, vha, 0x0095,
5493 "Firmware data: %08x %08x %08x %08x.\n",
5494 dcode[0], dcode[1], dcode[2], dcode[3]);
f73cb695 5495 return QLA_FUNCTION_FAILED;
0107109e
AV		 5496 }
5497
5498 while (segments && rval == QLA_SUCCESS) {
5499 risc_addr = be32_to_cpu(fwcode[2]);
5500 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5501 risc_size = be32_to_cpu(fwcode[3]);
5502
5503 /* Validate firmware image size. */
5504 fwclen += risc_size * sizeof(uint32_t);
5433383e 5505 if (blob->fw->size < fwclen) {
7c3df132 5506 ql_log(ql_log_fatal, vha, 0x0096,
5433383e 5507 "Unable to verify integrity of firmware image "
7c3df132 5508 "(%Zd).\n", blob->fw->size);
f73cb695 5509 return QLA_FUNCTION_FAILED;
0107109e
AV		 5510 }
5511
5512 fragment = 0;
5513 while (risc_size > 0 && rval == QLA_SUCCESS) {
5514 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5515 if (dlen > risc_size)
5516 dlen = risc_size;
5517
7c3df132
SK		 5518 ql_dbg(ql_dbg_init, vha, 0x0097,
5519 "Loading risc segment@ risc addr %x "
5520 "number of dwords 0x%x.\n", risc_addr, dlen);
0107109e
AV		 5521
5522 for (i = 0; i < dlen; i++)
5523 dcode[i] = swab32(fwcode[i]);
5524
73208dfd 5525 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
590f98e5 5526 dlen);
0107109e 5527 if (rval) {
7c3df132
SK		 5528 ql_log(ql_log_fatal, vha, 0x0098,
5529 "Failed to load segment %d of firmware.\n",
5530 fragment);
0107109e
AV		 5531 break;
5532 }
5533
5534 fwcode += dlen;
5535 risc_addr += dlen;
5536 risc_size -= dlen;
5537 fragment++;
5538 }
5539
5540 /* Next segment. */
5541 segments--;
5542 }
f73cb695
CD		 5543
5544 if (!IS_QLA27XX(ha))
5545 return rval;
5546
5547 if (ha->fw_dump_template)
5548 vfree(ha->fw_dump_template);
5549 ha->fw_dump_template = NULL;
5550 ha->fw_dump_template_len = 0;
5551
5552 ql_dbg(ql_dbg_init, vha, 0x171,
97ea702b
CD		 5553 "Loading fwdump template from %x\n",
5554 (uint32_t)((void *)fwcode - (void *)blob->fw->data));
f73cb695
CD		 5555 risc_size = be32_to_cpu(fwcode[2]);
5556 ql_dbg(ql_dbg_init, vha, 0x172,
5557 "-> array size %x dwords\n", risc_size);
5558 if (risc_size == 0 || risc_size == ~0)
5559 goto default_template;
5560
5561 dlen = (risc_size - 8) * sizeof(*fwcode);
5562 ql_dbg(ql_dbg_init, vha, 0x0173,
5563 "-> template allocating %x bytes...\n", dlen);
5564 ha->fw_dump_template = vmalloc(dlen);
5565 if (!ha->fw_dump_template) {
5566 ql_log(ql_log_warn, vha, 0x0174,
5567 "Failed fwdump template allocate %x bytes.\n", risc_size);
5568 goto default_template;
5569 }
5570
5571 fwcode += 7;
5572 risc_size -= 8;
5573 dcode = ha->fw_dump_template;
5574 for (i = 0; i < risc_size; i++)
5575 dcode[i] = le32_to_cpu(fwcode[i]);
5576
5577 if (!qla27xx_fwdt_template_valid(dcode)) {
5578 ql_log(ql_log_warn, vha, 0x0175,
5579 "Failed fwdump template validate\n");
5580 goto default_template;
5581 }
5582
5583 dlen = qla27xx_fwdt_template_size(dcode);
5584 ql_dbg(ql_dbg_init, vha, 0x0176,
5585 "-> template size %x bytes\n", dlen);
5586 if (dlen > risc_size * sizeof(*fwcode)) {
5587 ql_log(ql_log_warn, vha, 0x0177,
97ea702b
CD		 5588 "Failed fwdump template exceeds array by %x bytes\n",
5589 (uint32_t)(dlen - risc_size * sizeof(*fwcode)));
f73cb695
CD		 5590 goto default_template;
5591 }
5592 ha->fw_dump_template_len = dlen;
0107109e
AV		 5593 return rval;
5594
f73cb695
CD		 5595default_template:
5596 ql_log(ql_log_warn, vha, 0x0178, "Using default fwdump template\n");
5597 if (ha->fw_dump_template)
5598 vfree(ha->fw_dump_template);
5599 ha->fw_dump_template = NULL;
5600 ha->fw_dump_template_len = 0;
5601
5602 dlen = qla27xx_fwdt_template_default_size();
5603 ql_dbg(ql_dbg_init, vha, 0x0179,
5604 "-> template allocating %x bytes...\n", dlen);
5605 ha->fw_dump_template = vmalloc(dlen);
5606 if (!ha->fw_dump_template) {
5607 ql_log(ql_log_warn, vha, 0x017a,
5608 "Failed fwdump template allocate %x bytes.\n", risc_size);
5609 goto failed_template;
5610 }
5611
5612 dcode = ha->fw_dump_template;
5613 risc_size = dlen / sizeof(*fwcode);
5614 fwcode = qla27xx_fwdt_template_default();
5615 for (i = 0; i < risc_size; i++)
5616 dcode[i] = be32_to_cpu(fwcode[i]);
5617
5618 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
5619 ql_log(ql_log_warn, vha, 0x017b,
5620 "Failed fwdump template validate\n");
5621 goto failed_template;
5622 }
5623
5624 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
5625 ql_dbg(ql_dbg_init, vha, 0x017c,
5626 "-> template size %x bytes\n", dlen);
5627 ha->fw_dump_template_len = dlen;
5628 return rval;
5629
5630failed_template:
5631 ql_log(ql_log_warn, vha, 0x017d, "Failed default fwdump template\n");
5632 if (ha->fw_dump_template)
5633 vfree(ha->fw_dump_template);
5634 ha->fw_dump_template = NULL;
5635 ha->fw_dump_template_len = 0;
5636 return rval;
0107109e 5637}
18c6c127 5638
eaac30be
AV		 5639int
5640qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5641{
5642 int rval;
5643
e337d907
AV		 5644 if (ql2xfwloadbin == 1)
5645 return qla81xx_load_risc(vha, srisc_addr);
5646
eaac30be
AV		 5647 /*
5648 * FW Load priority:
5649 * 1) Firmware via request-firmware interface (.bin file).
5650 * 2) Firmware residing in flash.
5651 */
5652 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5653 if (rval == QLA_SUCCESS)
5654 return rval;
5655
cbc8eb67
AV		 5656 return qla24xx_load_risc_flash(vha, srisc_addr,
5657 vha->hw->flt_region_fw);
eaac30be
AV		 5658}
5659
5660int
5661qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5662{
5663 int rval;
cbc8eb67 5664 struct qla_hw_data *ha = vha->hw;
eaac30be 5665
e337d907 5666 if (ql2xfwloadbin == 2)
cbc8eb67 5667 goto try_blob_fw;
e337d907 5668
eaac30be
AV		 5669 /*
5670 * FW Load priority:
5671 * 1) Firmware residing in flash.
5672 * 2) Firmware via request-firmware interface (.bin file).
cbc8eb67 5673 * 3) Golden-Firmware residing in flash -- limited operation.
eaac30be 5674 */
cbc8eb67 5675 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
eaac30be
AV		 5676 if (rval == QLA_SUCCESS)
5677 return rval;
5678
cbc8eb67
AV		 5679try_blob_fw:
5680 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5681 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
5682 return rval;
5683
7c3df132
SK		 5684 ql_log(ql_log_info, vha, 0x0099,
5685 "Attempting to fallback to golden firmware.\n");
cbc8eb67
AV		 5686 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
5687 if (rval != QLA_SUCCESS)
5688 return rval;
5689
7c3df132 5690 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
cbc8eb67 5691 ha->flags.running_gold_fw = 1;
cbc8eb67 5692 return rval;
eaac30be
AV		 5693}
5694
18c6c127 5695void
e315cd28 5696qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
18c6c127
AV		 5697{
5698 int ret, retries;
e315cd28 5699 struct qla_hw_data *ha = vha->hw;
18c6c127 5700
85880801
AV		 5701 if (ha->flags.pci_channel_io_perm_failure)
5702 return;
e428924c 5703 if (!IS_FWI2_CAPABLE(ha))
18c6c127 5704 return;
75edf81d
AV		 5705 if (!ha->fw_major_version)
5706 return;
18c6c127 5707
e315cd28 5708 ret = qla2x00_stop_firmware(vha);
7c7f1f29 5709 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
b469a7cb 5710 ret != QLA_INVALID_COMMAND && retries ; retries--) {
e315cd28
AC		 5711 ha->isp_ops->reset_chip(vha);
5712 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
18c6c127 5713 continue;
e315cd28 5714 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
18c6c127 5715 continue;
7c3df132
SK		 5716 ql_log(ql_log_info, vha, 0x8015,
5717 "Attempting retry of stop-firmware command.\n");
e315cd28 5718 ret = qla2x00_stop_firmware(vha);
18c6c127
AV		 5719 }
5720}
2c3dfe3f
SJ		 5721
5722int
e315cd28 5723qla24xx_configure_vhba(scsi_qla_host_t *vha)
2c3dfe3f
SJ		 5724{
5725 int rval = QLA_SUCCESS;
0b91d116 5726 int rval2;
2c3dfe3f 5727 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28
AC		 5728 struct qla_hw_data *ha = vha->hw;
5729 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
67c2e93a
AC		 5730 struct req_que *req;
5731 struct rsp_que *rsp;
2c3dfe3f 5732
e315cd28 5733 if (!vha->vp_idx)
2c3dfe3f
SJ		 5734 return -EINVAL;
5735
e315cd28 5736 rval = qla2x00_fw_ready(base_vha);
7163ea81 5737 if (ha->flags.cpu_affinity_enabled)
67c2e93a
AC		 5738 req = ha->req_q_map[0];
5739 else
5740 req = vha->req;
5741 rsp = req->rsp;
5742
2c3dfe3f 5743 if (rval == QLA_SUCCESS) {
e315cd28 5744 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
73208dfd 5745 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
2c3dfe3f
SJ		 5746 }
5747
e315cd28 5748 vha->flags.management_server_logged_in = 0;
2c3dfe3f
SJ		 5749
5750 /* Login to SNS first */
0b91d116
CD		 5751 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
5752 BIT_1);
5753 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
5754 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
5755 ql_dbg(ql_dbg_init, vha, 0x0120,
5756 "Failed SNS login: loop_id=%x, rval2=%d\n",
5757 NPH_SNS, rval2);
5758 else
5759 ql_dbg(ql_dbg_init, vha, 0x0103,
5760 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
5761 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
5762 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
2c3dfe3f
SJ		 5763 return (QLA_FUNCTION_FAILED);
5764 }
5765
e315cd28
AC		 5766 atomic_set(&vha->loop_down_timer, 0);
5767 atomic_set(&vha->loop_state, LOOP_UP);
5768 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5769 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5770 rval = qla2x00_loop_resync(base_vha);
2c3dfe3f
SJ		 5771
5772 return rval;
5773}
4d4df193
HK		 5774
5775/* 84XX Support **************************************************************/
5776
5777static LIST_HEAD(qla_cs84xx_list);
5778static DEFINE_MUTEX(qla_cs84xx_mutex);
5779
5780static struct qla_chip_state_84xx *
e315cd28 5781qla84xx_get_chip(struct scsi_qla_host *vha)
4d4df193
HK		 5782{
5783 struct qla_chip_state_84xx *cs84xx;
e315cd28 5784 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5785
5786 mutex_lock(&qla_cs84xx_mutex);
5787
5788 /* Find any shared 84xx chip. */
5789 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
5790 if (cs84xx->bus == ha->pdev->bus) {
5791 kref_get(&cs84xx->kref);
5792 goto done;
5793 }
5794 }
5795
5796 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
5797 if (!cs84xx)
5798 goto done;
5799
5800 kref_init(&cs84xx->kref);
5801 spin_lock_init(&cs84xx->access_lock);
5802 mutex_init(&cs84xx->fw_update_mutex);
5803 cs84xx->bus = ha->pdev->bus;
5804
5805 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
5806done:
5807 mutex_unlock(&qla_cs84xx_mutex);
5808 return cs84xx;
5809}
5810
5811static void
5812__qla84xx_chip_release(struct kref *kref)
5813{
5814 struct qla_chip_state_84xx *cs84xx =
5815 container_of(kref, struct qla_chip_state_84xx, kref);
5816
5817 mutex_lock(&qla_cs84xx_mutex);
5818 list_del(&cs84xx->list);
5819 mutex_unlock(&qla_cs84xx_mutex);
5820 kfree(cs84xx);
5821}
5822
5823void
e315cd28 5824qla84xx_put_chip(struct scsi_qla_host *vha)
4d4df193 5825{
e315cd28 5826 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5827 if (ha->cs84xx)
5828 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
5829}
5830
5831static int
e315cd28 5832qla84xx_init_chip(scsi_qla_host_t *vha)
4d4df193
HK		 5833{
5834 int rval;
5835 uint16_t status[2];
e315cd28 5836 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5837
5838 mutex_lock(&ha->cs84xx->fw_update_mutex);
5839
e315cd28 5840 rval = qla84xx_verify_chip(vha, status);
4d4df193
HK		 5841
5842 mutex_unlock(&ha->cs84xx->fw_update_mutex);
5843
5844 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
5845 QLA_SUCCESS;
5846}
3a03eb79
AV		 5847
5848/* 81XX Support **************************************************************/
5849
5850int
5851qla81xx_nvram_config(scsi_qla_host_t *vha)
5852{
5853 int rval;
5854 struct init_cb_81xx *icb;
5855 struct nvram_81xx *nv;
5856 uint32_t *dptr;
5857 uint8_t *dptr1, *dptr2;
5858 uint32_t chksum;
5859 uint16_t cnt;
5860 struct qla_hw_data *ha = vha->hw;
5861
5862 rval = QLA_SUCCESS;
5863 icb = (struct init_cb_81xx *)ha->init_cb;
5864 nv = ha->nvram;
5865
5866 /* Determine NVRAM starting address. */
5867 ha->nvram_size = sizeof(struct nvram_81xx);
3a03eb79 5868 ha->vpd_size = FA_NVRAM_VPD_SIZE;
7ec0effd
AD		 5869 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
5870 ha->vpd_size = FA_VPD_SIZE_82XX;
3a03eb79
AV		 5871
5872 /* Get VPD data into cache */
5873 ha->vpd = ha->nvram + VPD_OFFSET;
3d79038f
AV		 5874 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
5875 ha->vpd_size);
3a03eb79
AV		 5876
5877 /* Get NVRAM data into cache and calculate checksum. */
3d79038f 5878 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
3a03eb79 5879 ha->nvram_size);
3d79038f 5880 dptr = (uint32_t *)nv;
3a03eb79
AV		 5881 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
5882 chksum += le32_to_cpu(*dptr++);
5883
7c3df132
SK		 5884 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
5885 "Contents of NVRAM:\n");
5886 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
5887 (uint8_t *)nv, ha->nvram_size);
3a03eb79
AV		 5888
5889 /* Bad NVRAM data, set defaults parameters. */
5890 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
5891 || nv->id[3] != ' ' ||
5892 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
5893 /* Reset NVRAM data. */
7c3df132 5894 ql_log(ql_log_info, vha, 0x0073,
9e336520 5895 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132 5896 "version=0x%x.\n", chksum, nv->id[0],
3a03eb79 5897 le16_to_cpu(nv->nvram_version));
7c3df132
SK		 5898 ql_log(ql_log_info, vha, 0x0074,
5899 "Falling back to functioning (yet invalid -- WWPN) "
5900 "defaults.\n");
3a03eb79
AV		 5901
5902 /*
5903 * Set default initialization control block.
5904 */
5905 memset(nv, 0, ha->nvram_size);
5906 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
5907 nv->version = __constant_cpu_to_le16(ICB_VERSION);
98aee70d 5908 nv->frame_payload_size = 2048;
3a03eb79
AV		 5909 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5910 nv->exchange_count = __constant_cpu_to_le16(0);
5911 nv->port_name[0] = 0x21;
f73cb695 5912 nv->port_name[1] = 0x00 + ha->port_no + 1;
3a03eb79
AV		 5913 nv->port_name[2] = 0x00;
5914 nv->port_name[3] = 0xe0;
5915 nv->port_name[4] = 0x8b;
5916 nv->port_name[5] = 0x1c;
5917 nv->port_name[6] = 0x55;
5918 nv->port_name[7] = 0x86;
5919 nv->node_name[0] = 0x20;
5920 nv->node_name[1] = 0x00;
5921 nv->node_name[2] = 0x00;
5922 nv->node_name[3] = 0xe0;
5923 nv->node_name[4] = 0x8b;
5924 nv->node_name[5] = 0x1c;
5925 nv->node_name[6] = 0x55;
5926 nv->node_name[7] = 0x86;
5927 nv->login_retry_count = __constant_cpu_to_le16(8);
5928 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
5929 nv->login_timeout = __constant_cpu_to_le16(0);
5930 nv->firmware_options_1 =
5931 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
5932 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
5933 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
5934 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
5935 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
5936 nv->efi_parameters = __constant_cpu_to_le32(0);
5937 nv->reset_delay = 5;
5938 nv->max_luns_per_target = __constant_cpu_to_le16(128);
5939 nv->port_down_retry_count = __constant_cpu_to_le16(30);
6246b8a1 5940 nv->link_down_timeout = __constant_cpu_to_le16(180);
eeebcc92 5941 nv->enode_mac[0] = 0x00;
6246b8a1
GM		 5942 nv->enode_mac[1] = 0xC0;
5943 nv->enode_mac[2] = 0xDD;
3a03eb79
AV		 5944 nv->enode_mac[3] = 0x04;
5945 nv->enode_mac[4] = 0x05;
f73cb695 5946 nv->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 5947
5948 rval = 1;
5949 }
5950
9e522cd8
AE		 5951 if (IS_T10_PI_CAPABLE(ha))
5952 nv->frame_payload_size &= ~7;
5953
aa230bc5
AE		 5954 qlt_81xx_config_nvram_stage1(vha, nv);
5955
3a03eb79 5956 /* Reset Initialization control block */
773120e4 5957 memset(icb, 0, ha->init_cb_size);
3a03eb79
AV		 5958
5959 /* Copy 1st segment. */
5960 dptr1 = (uint8_t *)icb;
5961 dptr2 = (uint8_t *)&nv->version;
5962 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
5963 while (cnt--)
5964 *dptr1++ = *dptr2++;
5965
5966 icb->login_retry_count = nv->login_retry_count;
5967
5968 /* Copy 2nd segment. */
5969 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
5970 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
5971 cnt = (uint8_t *)&icb->reserved_5 -
5972 (uint8_t *)&icb->interrupt_delay_timer;
5973 while (cnt--)
5974 *dptr1++ = *dptr2++;
5975
5976 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
5977 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
5978 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
69e5f1ea
AV		 5979 icb->enode_mac[0] = 0x00;
5980 icb->enode_mac[1] = 0xC0;
5981 icb->enode_mac[2] = 0xDD;
3a03eb79
AV		 5982 icb->enode_mac[3] = 0x04;
5983 icb->enode_mac[4] = 0x05;
f73cb695 5984 icb->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 5985 }
5986
b64b0e8f
AV		 5987 /* Use extended-initialization control block. */
5988 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
5989
3a03eb79
AV		 5990 /*
5991 * Setup driver NVRAM options.
5992 */
5993 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
a9083016 5994 "QLE8XXX");
3a03eb79 5995
aa230bc5
AE		 5996 qlt_81xx_config_nvram_stage2(vha, icb);
5997
3a03eb79
AV		 5998 /* Use alternate WWN? */
5999 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
6000 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
6001 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
6002 }
6003
6004 /* Prepare nodename */
6005 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
6006 /*
6007 * Firmware will apply the following mask if the nodename was
6008 * not provided.
6009 */
6010 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
6011 icb->node_name[0] &= 0xF0;
6012 }
6013
6014 /* Set host adapter parameters. */
6015 ha->flags.disable_risc_code_load = 0;
6016 ha->flags.enable_lip_reset = 0;
6017 ha->flags.enable_lip_full_login =
6018 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
6019 ha->flags.enable_target_reset =
6020 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
6021 ha->flags.enable_led_scheme = 0;
6022 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
6023
6024 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
6025 (BIT_6 | BIT_5 | BIT_4)) >> 4;
6026
6027 /* save HBA serial number */
6028 ha->serial0 = icb->port_name[5];
6029 ha->serial1 = icb->port_name[6];
6030 ha->serial2 = icb->port_name[7];
6031 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
6032 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
6033
6034 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
6035
6036 ha->retry_count = le16_to_cpu(nv->login_retry_count);
6037
6038 /* Set minimum login_timeout to 4 seconds. */
6039 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
6040 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
6041 if (le16_to_cpu(nv->login_timeout) < 4)
6042 nv->login_timeout = __constant_cpu_to_le16(4);
6043 ha->login_timeout = le16_to_cpu(nv->login_timeout);
6044 icb->login_timeout = nv->login_timeout;
6045
6046 /* Set minimum RATOV to 100 tenths of a second. */
6047 ha->r_a_tov = 100;
6048
6049 ha->loop_reset_delay = nv->reset_delay;
6050
6051 /* Link Down Timeout = 0:
6052 *
7ec0effd 6053 * When Port Down timer expires we will start returning
3a03eb79
AV		 6054 * I/O's to OS with "DID_NO_CONNECT".
6055 *
6056 * Link Down Timeout != 0:
6057 *
6058 * The driver waits for the link to come up after link down
6059 * before returning I/Os to OS with "DID_NO_CONNECT".
6060 */
6061 if (le16_to_cpu(nv->link_down_timeout) == 0) {
6062 ha->loop_down_abort_time =
6063 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
6064 } else {
6065 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
6066 ha->loop_down_abort_time =
6067 (LOOP_DOWN_TIME - ha->link_down_timeout);
6068 }
6069
6070 /* Need enough time to try and get the port back. */
6071 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
6072 if (qlport_down_retry)
6073 ha->port_down_retry_count = qlport_down_retry;
6074
6075 /* Set login_retry_count */
6076 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
6077 if (ha->port_down_retry_count ==
6078 le16_to_cpu(nv->port_down_retry_count) &&
6079 ha->port_down_retry_count > 3)
6080 ha->login_retry_count = ha->port_down_retry_count;
6081 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
6082 ha->login_retry_count = ha->port_down_retry_count;
6083 if (ql2xloginretrycount)
6084 ha->login_retry_count = ql2xloginretrycount;
6085
6246b8a1 6086 /* if not running MSI-X we need handshaking on interrupts */
f73cb695 6087 if (!vha->hw->flags.msix_enabled && (IS_QLA83XX(ha) || IS_QLA27XX(ha)))
6246b8a1
GM		 6088 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_22);
6089
3a03eb79
AV		 6090 /* Enable ZIO. */
6091 if (!vha->flags.init_done) {
6092 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
6093 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
6094 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
6095 le16_to_cpu(icb->interrupt_delay_timer): 2;
6096 }
6097 icb->firmware_options_2 &= __constant_cpu_to_le32(
6098 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
6099 vha->flags.process_response_queue = 0;
6100 if (ha->zio_mode != QLA_ZIO_DISABLED) {
6101 ha->zio_mode = QLA_ZIO_MODE_6;
6102
7c3df132 6103 ql_log(ql_log_info, vha, 0x0075,
3a03eb79 6104 "ZIO mode %d enabled; timer delay (%d us).\n",
7c3df132
SK		 6105 ha->zio_mode,
6106 ha->zio_timer * 100);
3a03eb79
AV		 6107
6108 icb->firmware_options_2 |= cpu_to_le32(
6109 (uint32_t)ha->zio_mode);
6110 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
6111 vha->flags.process_response_queue = 1;
6112 }
6113
6114 if (rval) {
7c3df132
SK		 6115 ql_log(ql_log_warn, vha, 0x0076,
6116 "NVRAM configuration failed.\n");
3a03eb79
AV		 6117 }
6118 return (rval);
6119}
6120
a9083016
GM		 6121int
6122qla82xx_restart_isp(scsi_qla_host_t *vha)
6123{
6124 int status, rval;
a9083016
GM		 6125 struct qla_hw_data *ha = vha->hw;
6126 struct req_que *req = ha->req_q_map[0];
6127 struct rsp_que *rsp = ha->rsp_q_map[0];
6128 struct scsi_qla_host *vp;
feafb7b1 6129 unsigned long flags;
a9083016
GM		 6130
6131 status = qla2x00_init_rings(vha);
6132 if (!status) {
6133 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
6134 ha->flags.chip_reset_done = 1;
6135
6136 status = qla2x00_fw_ready(vha);
6137 if (!status) {
a9083016
GM		 6138 /* Issue a marker after FW becomes ready. */
6139 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
a9083016 6140 vha->flags.online = 1;
7108b76e 6141 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
a9083016
GM		 6142 }
6143
6144 /* if no cable then assume it's good */
6145 if ((vha->device_flags & DFLG_NO_CABLE))
6146 status = 0;
a9083016
GM		 6147 }
6148
6149 if (!status) {
6150 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
6151
6152 if (!atomic_read(&vha->loop_down_timer)) {
6153 /*
6154 * Issue marker command only when we are going
6155 * to start the I/O .
6156 */
6157 vha->marker_needed = 1;
6158 }
6159
a9083016
GM		 6160 ha->isp_ops->enable_intrs(ha);
6161
6162 ha->isp_abort_cnt = 0;
6163 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
6164
53296788 6165 /* Update the firmware version */
3173167f 6166 status = qla82xx_check_md_needed(vha);
53296788 6167
a9083016
GM		 6168 if (ha->fce) {
6169 ha->flags.fce_enabled = 1;
6170 memset(ha->fce, 0,
6171 fce_calc_size(ha->fce_bufs));
6172 rval = qla2x00_enable_fce_trace(vha,
6173 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
6174 &ha->fce_bufs);
6175 if (rval) {
cfb0919c 6176 ql_log(ql_log_warn, vha, 0x8001,
7c3df132
SK		 6177 "Unable to reinitialize FCE (%d).\n",
6178 rval);
a9083016
GM		 6179 ha->flags.fce_enabled = 0;
6180 }
6181 }
6182
6183 if (ha->eft) {
6184 memset(ha->eft, 0, EFT_SIZE);
6185 rval = qla2x00_enable_eft_trace(vha,
6186 ha->eft_dma, EFT_NUM_BUFFERS);
6187 if (rval) {
cfb0919c 6188 ql_log(ql_log_warn, vha, 0x8010,
7c3df132
SK		 6189 "Unable to reinitialize EFT (%d).\n",
6190 rval);
a9083016
GM		 6191 }
6192 }
a9083016
GM		 6193 }
6194
6195 if (!status) {
cfb0919c 6196 ql_dbg(ql_dbg_taskm, vha, 0x8011,
7c3df132 6197 "qla82xx_restart_isp succeeded.\n");
feafb7b1
AE		 6198
6199 spin_lock_irqsave(&ha->vport_slock, flags);
6200 list_for_each_entry(vp, &ha->vp_list, list) {
6201 if (vp->vp_idx) {
6202 atomic_inc(&vp->vref_count);
6203 spin_unlock_irqrestore(&ha->vport_slock, flags);
6204
a9083016 6205 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 6206
6207 spin_lock_irqsave(&ha->vport_slock, flags);
6208 atomic_dec(&vp->vref_count);
6209 }
a9083016 6210 }
feafb7b1
AE		 6211 spin_unlock_irqrestore(&ha->vport_slock, flags);
6212
a9083016 6213 } else {
cfb0919c 6214 ql_log(ql_log_warn, vha, 0x8016,
7c3df132 6215 "qla82xx_restart_isp **** FAILED ****.\n");
a9083016
GM		 6216 }
6217
6218 return status;
6219}
6220
3a03eb79 6221void
ae97c91e 6222qla81xx_update_fw_options(scsi_qla_host_t *vha)
3a03eb79 6223{
ae97c91e
AV		 6224 struct qla_hw_data *ha = vha->hw;
6225
6226 if (!ql2xetsenable)
6227 return;
6228
6229 /* Enable ETS Burst. */
6230 memset(ha->fw_options, 0, sizeof(ha->fw_options));
6231 ha->fw_options[2] |= BIT_9;
6232 qla2x00_set_fw_options(vha, ha->fw_options);
3a03eb79 6233}
09ff701a
SR		 6234
6235/*
6236 * qla24xx_get_fcp_prio
6237 * Gets the fcp cmd priority value for the logged in port.
6238 * Looks for a match of the port descriptors within
6239 * each of the fcp prio config entries. If a match is found,
6240 * the tag (priority) value is returned.
6241 *
6242 * Input:
21090cbe 6243 * vha = scsi host structure pointer.
09ff701a
SR		 6244 * fcport = port structure pointer.
6245 *
6246 * Return:
6c452a45 6247 * non-zero (if found)
f28a0a96 6248 * -1 (if not found)
09ff701a
SR		 6249 *
6250 * Context:
6251 * Kernel context
6252 */
f28a0a96 6253static int
09ff701a
SR		 6254qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
6255{
6256 int i, entries;
6257 uint8_t pid_match, wwn_match;
f28a0a96 6258 int priority;
09ff701a
SR		 6259 uint32_t pid1, pid2;
6260 uint64_t wwn1, wwn2;
6261 struct qla_fcp_prio_entry *pri_entry;
6262 struct qla_hw_data *ha = vha->hw;
6263
6264 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
f28a0a96 6265 return -1;
09ff701a 6266
f28a0a96 6267 priority = -1;
09ff701a
SR		 6268 entries = ha->fcp_prio_cfg->num_entries;
6269 pri_entry = &ha->fcp_prio_cfg->entry[0];
6270
6271 for (i = 0; i < entries; i++) {
6272 pid_match = wwn_match = 0;
6273
6274 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
6275 pri_entry++;
6276 continue;
6277 }
6278
6279 /* check source pid for a match */
6280 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
6281 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
6282 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
6283 if (pid1 == INVALID_PORT_ID)
6284 pid_match++;
6285 else if (pid1 == pid2)
6286 pid_match++;
6287 }
6288
6289 /* check destination pid for a match */
6290 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
6291 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
6292 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
6293 if (pid1 == INVALID_PORT_ID)
6294 pid_match++;
6295 else if (pid1 == pid2)
6296 pid_match++;
6297 }
6298
6299 /* check source WWN for a match */
6300 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
6301 wwn1 = wwn_to_u64(vha->port_name);
6302 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
6303 if (wwn2 == (uint64_t)-1)
6304 wwn_match++;
6305 else if (wwn1 == wwn2)
6306 wwn_match++;
6307 }
6308
6309 /* check destination WWN for a match */
6310 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
6311 wwn1 = wwn_to_u64(fcport->port_name);
6312 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
6313 if (wwn2 == (uint64_t)-1)
6314 wwn_match++;
6315 else if (wwn1 == wwn2)
6316 wwn_match++;
6317 }
6318
6319 if (pid_match == 2 || wwn_match == 2) {
6320 /* Found a matching entry */
6321 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
6322 priority = pri_entry->tag;
6323 break;
6324 }
6325
6326 pri_entry++;
6327 }
6328
6329 return priority;
6330}
6331
6332/*
6333 * qla24xx_update_fcport_fcp_prio
6334 * Activates fcp priority for the logged in fc port
6335 *
6336 * Input:
21090cbe 6337 * vha = scsi host structure pointer.
09ff701a
SR		 6338 * fcp = port structure pointer.
6339 *
6340 * Return:
6341 * QLA_SUCCESS or QLA_FUNCTION_FAILED
6342 *
6343 * Context:
6344 * Kernel context.
6345 */
6346int
21090cbe 6347qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
09ff701a
SR		 6348{
6349 int ret;
f28a0a96 6350 int priority;
09ff701a
SR		 6351 uint16_t mb[5];
6352
21090cbe
MI		 6353 if (fcport->port_type != FCT_TARGET ||
6354 fcport->loop_id == FC_NO_LOOP_ID)
09ff701a
SR		 6355 return QLA_FUNCTION_FAILED;
6356
21090cbe 6357 priority = qla24xx_get_fcp_prio(vha, fcport);
f28a0a96
AV		 6358 if (priority < 0)
6359 return QLA_FUNCTION_FAILED;
6360
7ec0effd 6361 if (IS_P3P_TYPE(vha->hw)) {
a00f6296
SK		 6362 fcport->fcp_prio = priority & 0xf;
6363 return QLA_SUCCESS;
6364 }
6365
21090cbe 6366 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
cfb0919c
CD		 6367 if (ret == QLA_SUCCESS) {
6368 if (fcport->fcp_prio != priority)
6369 ql_dbg(ql_dbg_user, vha, 0x709e,
6370 "Updated FCP_CMND priority - value=%d loop_id=%d "
6371 "port_id=%02x%02x%02x.\n", priority,
6372 fcport->loop_id, fcport->d_id.b.domain,
6373 fcport->d_id.b.area, fcport->d_id.b.al_pa);
a00f6296 6374 fcport->fcp_prio = priority & 0xf;
cfb0919c 6375 } else
7c3df132 6376 ql_dbg(ql_dbg_user, vha, 0x704f,
cfb0919c
CD		 6377 "Unable to update FCP_CMND priority - ret=0x%x for "
6378 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
6379 fcport->d_id.b.domain, fcport->d_id.b.area,
6380 fcport->d_id.b.al_pa);
09ff701a
SR		 6381 return ret;
6382}
6383
6384/*
6385 * qla24xx_update_all_fcp_prio
6386 * Activates fcp priority for all the logged in ports
6387 *
6388 * Input:
6389 * ha = adapter block pointer.
6390 *
6391 * Return:
6392 * QLA_SUCCESS or QLA_FUNCTION_FAILED
6393 *
6394 * Context:
6395 * Kernel context.
6396 */
6397int
6398qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
6399{
6400 int ret;
6401 fc_port_t *fcport;
6402
6403 ret = QLA_FUNCTION_FAILED;
6404 /* We need to set priority for all logged in ports */
6405 list_for_each_entry(fcport, &vha->vp_fcports, list)
6406 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
6407
6408 return ret;
6409}
Linux kernel - Deliverables
This page took 1.739035 seconds and 5 git commands to generate.