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[SCSI] qla2xxx: Wrong PCIe(2.5Gb/s x8) speed in the kerenel message for ISP82xx.
[deliverable/linux.git] / drivers / scsi / qla2xxx / qla_init.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
46152ceb 3 * Copyright (c) 2003-2012 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
73208dfd 8#include "qla_gbl.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/slab.h>
0107109e 12#include <linux/vmalloc.h>
1da177e4
LT		 13
14#include "qla_devtbl.h"
15
4e08df3f
DM		 16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
4e08df3f
DM		 18#endif
19
2d70c103
NB		 20#include <target/target_core_base.h>
21#include "qla_target.h"
22
1da177e4
LT		 23/*
24* QLogic ISP2x00 Hardware Support Function Prototypes.
25*/
1da177e4 26static int qla2x00_isp_firmware(scsi_qla_host_t *);
1da177e4 27static int qla2x00_setup_chip(scsi_qla_host_t *);
1da177e4
LT		 28static int qla2x00_init_rings(scsi_qla_host_t *);
29static int qla2x00_fw_ready(scsi_qla_host_t *);
30static int qla2x00_configure_hba(scsi_qla_host_t *);
1da177e4
LT		 31static int qla2x00_configure_loop(scsi_qla_host_t *);
32static int qla2x00_configure_local_loop(scsi_qla_host_t *);
1da177e4
LT		 33static int qla2x00_configure_fabric(scsi_qla_host_t *);
34static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *);
1da177e4
LT		 35static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
36 uint16_t *);
1da177e4
LT		 37
38static int qla2x00_restart_isp(scsi_qla_host_t *);
1da177e4 39
4d4df193
HK		 40static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
41static int qla84xx_init_chip(scsi_qla_host_t *);
73208dfd 42static int qla25xx_init_queues(struct qla_hw_data *);
4d4df193 43
ac280b67
AV		 44/* SRB Extensions ---------------------------------------------------------- */
45
9ba56b95
GM		 46void
47qla2x00_sp_timeout(unsigned long __data)
ac280b67
AV		 48{
49 srb_t *sp = (srb_t *)__data;
4916392b 50 struct srb_iocb *iocb;
ac280b67
AV		 51 fc_port_t *fcport = sp->fcport;
52 struct qla_hw_data *ha = fcport->vha->hw;
53 struct req_que *req;
54 unsigned long flags;
55
56 spin_lock_irqsave(&ha->hardware_lock, flags);
57 req = ha->req_q_map[0];
58 req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 59 iocb = &sp->u.iocb_cmd;
4916392b 60 iocb->timeout(sp);
9ba56b95 61 sp->free(fcport->vha, sp);
6ac52608 62 spin_unlock_irqrestore(&ha->hardware_lock, flags);
ac280b67
AV		 63}
64
9ba56b95
GM		 65void
66qla2x00_sp_free(void *data, void *ptr)
ac280b67 67{
9ba56b95
GM		 68 srb_t *sp = (srb_t *)ptr;
69 struct srb_iocb *iocb = &sp->u.iocb_cmd;
70 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
ac280b67 71
4d97cc53 72 del_timer(&iocb->timer);
9ba56b95 73 mempool_free(sp, vha->hw->srb_mempool);
feafb7b1
AE		 74
75 QLA_VHA_MARK_NOT_BUSY(vha);
ac280b67
AV		 76}
77
ac280b67
AV		 78/* Asynchronous Login/Logout Routines -------------------------------------- */
79
a9b6f722 80unsigned long
5b91490e
AV		 81qla2x00_get_async_timeout(struct scsi_qla_host *vha)
82{
83 unsigned long tmo;
84 struct qla_hw_data *ha = vha->hw;
85
86 /* Firmware should use switch negotiated r_a_tov for timeout. */
87 tmo = ha->r_a_tov / 10 * 2;
88 if (!IS_FWI2_CAPABLE(ha)) {
89 /*
90 * Except for earlier ISPs where the timeout is seeded from the
91 * initialization control block.
92 */
93 tmo = ha->login_timeout;
94 }
95 return tmo;
96}
ac280b67
AV		 97
98static void
9ba56b95 99qla2x00_async_iocb_timeout(void *data)
ac280b67 100{
9ba56b95 101 srb_t *sp = (srb_t *)data;
ac280b67 102 fc_port_t *fcport = sp->fcport;
ac280b67 103
7c3df132 104 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
cfb0919c 105 "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n",
9ba56b95 106 sp->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area,
7c3df132 107 fcport->d_id.b.al_pa);
ac280b67 108
5ff1d584 109 fcport->flags &= ~FCF_ASYNC_SENT;
9ba56b95
GM		 110 if (sp->type == SRB_LOGIN_CMD) {
111 struct srb_iocb *lio = &sp->u.iocb_cmd;
ac280b67 112 qla2x00_post_async_logout_work(fcport->vha, fcport, NULL);
6ac52608
AV		 113 /* Retry as needed. */
114 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
115 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
116 QLA_LOGIO_LOGIN_RETRIED : 0;
117 qla2x00_post_async_login_done_work(fcport->vha, fcport,
118 lio->u.logio.data);
119 }
ac280b67
AV		 120}
121
99b0bec7 122static void
9ba56b95 123qla2x00_async_login_sp_done(void *data, void *ptr, int res)
99b0bec7 124{
9ba56b95
GM		 125 srb_t *sp = (srb_t *)ptr;
126 struct srb_iocb *lio = &sp->u.iocb_cmd;
127 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
128
129 if (!test_bit(UNLOADING, &vha->dpc_flags))
130 qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport,
131 lio->u.logio.data);
132 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 133}
134
ac280b67
AV		 135int
136qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
137 uint16_t *data)
138{
ac280b67 139 srb_t *sp;
4916392b 140 struct srb_iocb *lio;
ac280b67
AV		 141 int rval;
142
143 rval = QLA_FUNCTION_FAILED;
9ba56b95 144 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 145 if (!sp)
146 goto done;
147
9ba56b95
GM		 148 sp->type = SRB_LOGIN_CMD;
149 sp->name = "login";
150 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
151
152 lio = &sp->u.iocb_cmd;
3822263e 153 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 154 sp->done = qla2x00_async_login_sp_done;
4916392b 155 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
ac280b67 156 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 157 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
ac280b67
AV		 158 rval = qla2x00_start_sp(sp);
159 if (rval != QLA_SUCCESS)
160 goto done_free_sp;
161
7c3df132 162 ql_dbg(ql_dbg_disc, vha, 0x2072,
cfb0919c
CD		 163 "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x "
164 "retries=%d.\n", sp->handle, fcport->loop_id,
165 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
166 fcport->login_retry);
ac280b67
AV		 167 return rval;
168
169done_free_sp:
9ba56b95 170 sp->free(fcport->vha, sp);
ac280b67
AV		 171done:
172 return rval;
173}
174
99b0bec7 175static void
9ba56b95 176qla2x00_async_logout_sp_done(void *data, void *ptr, int res)
99b0bec7 177{
9ba56b95
GM		 178 srb_t *sp = (srb_t *)ptr;
179 struct srb_iocb *lio = &sp->u.iocb_cmd;
180 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
181
182 if (!test_bit(UNLOADING, &vha->dpc_flags))
183 qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport,
184 lio->u.logio.data);
185 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 186}
187
ac280b67
AV		 188int
189qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
190{
ac280b67 191 srb_t *sp;
4916392b 192 struct srb_iocb *lio;
ac280b67
AV		 193 int rval;
194
195 rval = QLA_FUNCTION_FAILED;
9ba56b95 196 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 197 if (!sp)
198 goto done;
199
9ba56b95
GM		 200 sp->type = SRB_LOGOUT_CMD;
201 sp->name = "logout";
202 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
203
204 lio = &sp->u.iocb_cmd;
3822263e 205 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 206 sp->done = qla2x00_async_logout_sp_done;
ac280b67
AV		 207 rval = qla2x00_start_sp(sp);
208 if (rval != QLA_SUCCESS)
209 goto done_free_sp;
210
7c3df132 211 ql_dbg(ql_dbg_disc, vha, 0x2070,
cfb0919c
CD		 212 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
213 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
214 fcport->d_id.b.area, fcport->d_id.b.al_pa);
ac280b67
AV		 215 return rval;
216
217done_free_sp:
9ba56b95 218 sp->free(fcport->vha, sp);
ac280b67
AV		 219done:
220 return rval;
221}
222
5ff1d584 223static void
9ba56b95 224qla2x00_async_adisc_sp_done(void *data, void *ptr, int res)
5ff1d584 225{
9ba56b95
GM		 226 srb_t *sp = (srb_t *)ptr;
227 struct srb_iocb *lio = &sp->u.iocb_cmd;
228 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
229
230 if (!test_bit(UNLOADING, &vha->dpc_flags))
231 qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport,
232 lio->u.logio.data);
233 sp->free(sp->fcport->vha, sp);
5ff1d584
AV		 234}
235
236int
237qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
238 uint16_t *data)
239{
5ff1d584 240 srb_t *sp;
4916392b 241 struct srb_iocb *lio;
5ff1d584
AV		 242 int rval;
243
244 rval = QLA_FUNCTION_FAILED;
9ba56b95 245 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
5ff1d584
AV		 246 if (!sp)
247 goto done;
248
9ba56b95
GM		 249 sp->type = SRB_ADISC_CMD;
250 sp->name = "adisc";
251 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
252
253 lio = &sp->u.iocb_cmd;
3822263e 254 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 255 sp->done = qla2x00_async_adisc_sp_done;
5ff1d584 256 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 257 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
5ff1d584
AV		 258 rval = qla2x00_start_sp(sp);
259 if (rval != QLA_SUCCESS)
260 goto done_free_sp;
261
7c3df132 262 ql_dbg(ql_dbg_disc, vha, 0x206f,
cfb0919c
CD		 263 "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
264 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
265 fcport->d_id.b.area, fcport->d_id.b.al_pa);
5ff1d584
AV		 266 return rval;
267
268done_free_sp:
9ba56b95 269 sp->free(fcport->vha, sp);
5ff1d584
AV		 270done:
271 return rval;
272}
273
3822263e 274static void
9ba56b95 275qla2x00_async_tm_cmd_done(void *data, void *ptr, int res)
3822263e 276{
9ba56b95
GM		 277 srb_t *sp = (srb_t *)ptr;
278 struct srb_iocb *iocb = &sp->u.iocb_cmd;
279 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
280 uint32_t flags;
281 uint16_t lun;
282 int rval;
3822263e 283
9ba56b95
GM		 284 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
285 flags = iocb->u.tmf.flags;
286 lun = (uint16_t)iocb->u.tmf.lun;
287
288 /* Issue Marker IOCB */
289 rval = qla2x00_marker(vha, vha->hw->req_q_map[0],
290 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
291 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
292
293 if ((rval != QLA_SUCCESS) || iocb->u.tmf.data) {
294 ql_dbg(ql_dbg_taskm, vha, 0x8030,
295 "TM IOCB failed (%x).\n", rval);
296 }
297 }
298 sp->free(sp->fcport->vha, sp);
3822263e
MI		 299}
300
301int
9ba56b95 302qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t tm_flags, uint32_t lun,
3822263e
MI		 303 uint32_t tag)
304{
305 struct scsi_qla_host *vha = fcport->vha;
3822263e 306 srb_t *sp;
3822263e
MI		 307 struct srb_iocb *tcf;
308 int rval;
309
310 rval = QLA_FUNCTION_FAILED;
9ba56b95 311 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
3822263e
MI		 312 if (!sp)
313 goto done;
314
9ba56b95
GM		 315 sp->type = SRB_TM_CMD;
316 sp->name = "tmf";
317 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
318
319 tcf = &sp->u.iocb_cmd;
320 tcf->u.tmf.flags = tm_flags;
3822263e
MI		 321 tcf->u.tmf.lun = lun;
322 tcf->u.tmf.data = tag;
323 tcf->timeout = qla2x00_async_iocb_timeout;
9ba56b95 324 sp->done = qla2x00_async_tm_cmd_done;
3822263e
MI		 325
326 rval = qla2x00_start_sp(sp);
327 if (rval != QLA_SUCCESS)
328 goto done_free_sp;
329
7c3df132 330 ql_dbg(ql_dbg_taskm, vha, 0x802f,
cfb0919c
CD		 331 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
332 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
333 fcport->d_id.b.area, fcport->d_id.b.al_pa);
3822263e
MI		 334 return rval;
335
336done_free_sp:
9ba56b95 337 sp->free(fcport->vha, sp);
3822263e
MI		 338done:
339 return rval;
340}
341
4916392b 342void
ac280b67
AV		 343qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport,
344 uint16_t *data)
345{
346 int rval;
ac280b67
AV		 347
348 switch (data[0]) {
349 case MBS_COMMAND_COMPLETE:
a4f92a32
AV		 350 /*
351 * Driver must validate login state - If PRLI not complete,
352 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
353 * requests.
354 */
355 rval = qla2x00_get_port_database(vha, fcport, 0);
0eba25df
AE		 356 if (rval == QLA_NOT_LOGGED_IN) {
357 fcport->flags &= ~FCF_ASYNC_SENT;
358 fcport->flags |= FCF_LOGIN_NEEDED;
359 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
360 break;
361 }
362
a4f92a32
AV		 363 if (rval != QLA_SUCCESS) {
364 qla2x00_post_async_logout_work(vha, fcport, NULL);
365 qla2x00_post_async_login_work(vha, fcport, NULL);
366 break;
367 }
99b0bec7 368 if (fcport->flags & FCF_FCP2_DEVICE) {
5ff1d584
AV		 369 qla2x00_post_async_adisc_work(vha, fcport, data);
370 break;
99b0bec7
AV		 371 }
372 qla2x00_update_fcport(vha, fcport);
ac280b67
AV		 373 break;
374 case MBS_COMMAND_ERROR:
5ff1d584 375 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 376 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
377 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
378 else
80d79440 379 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 380 break;
381 case MBS_PORT_ID_USED:
382 fcport->loop_id = data[1];
6ac52608 383 qla2x00_post_async_logout_work(vha, fcport, NULL);
ac280b67
AV		 384 qla2x00_post_async_login_work(vha, fcport, NULL);
385 break;
386 case MBS_LOOP_ID_USED:
387 fcport->loop_id++;
388 rval = qla2x00_find_new_loop_id(vha, fcport);
389 if (rval != QLA_SUCCESS) {
5ff1d584 390 fcport->flags &= ~FCF_ASYNC_SENT;
80d79440 391 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 392 break;
393 }
394 qla2x00_post_async_login_work(vha, fcport, NULL);
395 break;
396 }
4916392b 397 return;
ac280b67
AV		 398}
399
4916392b 400void
ac280b67
AV		 401qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
402 uint16_t *data)
403{
404 qla2x00_mark_device_lost(vha, fcport, 1, 0);
4916392b 405 return;
ac280b67
AV		 406}
407
4916392b 408void
5ff1d584
AV		 409qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
410 uint16_t *data)
411{
412 if (data[0] == MBS_COMMAND_COMPLETE) {
413 qla2x00_update_fcport(vha, fcport);
414
4916392b 415 return;
5ff1d584
AV		 416 }
417
418 /* Retry login. */
419 fcport->flags &= ~FCF_ASYNC_SENT;
420 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
421 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
422 else
80d79440 423 qla2x00_mark_device_lost(vha, fcport, 1, 0);
5ff1d584 424
4916392b 425 return;
5ff1d584
AV		 426}
427
1da177e4
LT		 428/****************************************************************************/
429/* QLogic ISP2x00 Hardware Support Functions. */
430/****************************************************************************/
431
7d613ac6
SV		 432int
433qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
434{
435 int rval = QLA_SUCCESS;
436 struct qla_hw_data *ha = vha->hw;
437 uint32_t idc_major_ver, idc_minor_ver;
438
439 qla83xx_idc_lock(vha, 0);
440
441 /* SV: TODO: Assign initialization timeout from
442 * flash-info / other param
443 */
444 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
445 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
446
447 /* Set our fcoe function presence */
448 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
449 ql_dbg(ql_dbg_p3p, vha, 0xb077,
450 "Error while setting DRV-Presence.\n");
451 rval = QLA_FUNCTION_FAILED;
452 goto exit;
453 }
454
455 /* Decide the reset ownership */
456 qla83xx_reset_ownership(vha);
457
458 /*
459 * On first protocol driver load:
460 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
461 * register.
462 * Others: Check compatibility with current IDC Major version.
463 */
464 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
465 if (ha->flags.nic_core_reset_owner) {
466 /* Set IDC Major version */
467 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
468 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
469
470 /* Clearing IDC-Lock-Recovery register */
471 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
472 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
473 /*
474 * Clear further IDC participation if we are not compatible with
475 * the current IDC Major Version.
476 */
477 ql_log(ql_log_warn, vha, 0xb07d,
478 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
479 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
480 __qla83xx_clear_drv_presence(vha);
481 rval = QLA_FUNCTION_FAILED;
482 goto exit;
483 }
484 /* Each function sets its supported Minor version. */
485 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
486 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
487 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
488
489 rval = qla83xx_idc_state_handler(vha);
490
491exit:
492 qla83xx_idc_unlock(vha, 0);
493
494 return rval;
495}
496
1da177e4
LT		 497/*
498* qla2x00_initialize_adapter
499* Initialize board.
500*
501* Input:
502* ha = adapter block pointer.
503*
504* Returns:
505* 0 = success
506*/
507int
e315cd28 508qla2x00_initialize_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 509{
510 int rval;
e315cd28 511 struct qla_hw_data *ha = vha->hw;
73208dfd 512 struct req_que *req = ha->req_q_map[0];
2533cf67 513
1da177e4 514 /* Clear adapter flags. */
e315cd28 515 vha->flags.online = 0;
2533cf67 516 ha->flags.chip_reset_done = 0;
e315cd28 517 vha->flags.reset_active = 0;
85880801
AV		 518 ha->flags.pci_channel_io_perm_failure = 0;
519 ha->flags.eeh_busy = 0;
794a5691 520 ha->flags.thermal_supported = 1;
e315cd28
AC		 521 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
522 atomic_set(&vha->loop_state, LOOP_DOWN);
523 vha->device_flags = DFLG_NO_CABLE;
524 vha->dpc_flags = 0;
525 vha->flags.management_server_logged_in = 0;
526 vha->marker_needed = 0;
1da177e4
LT		 527 ha->isp_abort_cnt = 0;
528 ha->beacon_blink_led = 0;
529
73208dfd
AC		 530 set_bit(0, ha->req_qid_map);
531 set_bit(0, ha->rsp_qid_map);
532
cfb0919c 533 ql_dbg(ql_dbg_init, vha, 0x0040,
7c3df132 534 "Configuring PCI space...\n");
e315cd28 535 rval = ha->isp_ops->pci_config(vha);
1da177e4 536 if (rval) {
7c3df132
SK		 537 ql_log(ql_log_warn, vha, 0x0044,
538 "Unable to configure PCI space.\n");
1da177e4
LT		 539 return (rval);
540 }
541
e315cd28 542 ha->isp_ops->reset_chip(vha);
1da177e4 543
e315cd28 544 rval = qla2xxx_get_flash_info(vha);
c00d8994 545 if (rval) {
7c3df132
SK		 546 ql_log(ql_log_fatal, vha, 0x004f,
547 "Unable to validate FLASH data.\n");
c00d8994
AV		 548 return (rval);
549 }
550
73208dfd 551 ha->isp_ops->get_flash_version(vha, req->ring);
cfb0919c 552 ql_dbg(ql_dbg_init, vha, 0x0061,
7c3df132 553 "Configure NVRAM parameters...\n");
0107109e 554
e315cd28 555 ha->isp_ops->nvram_config(vha);
1da177e4 556
d4c760c2
AV		 557 if (ha->flags.disable_serdes) {
558 /* Mask HBA via NVRAM settings? */
7c3df132
SK		 559 ql_log(ql_log_info, vha, 0x0077,
560 "Masking HBA WWPN "
d4c760c2 561 "%02x%02x%02x%02x%02x%02x%02x%02x (via NVRAM).\n",
e315cd28
AC		 562 vha->port_name[0], vha->port_name[1],
563 vha->port_name[2], vha->port_name[3],
564 vha->port_name[4], vha->port_name[5],
565 vha->port_name[6], vha->port_name[7]);
d4c760c2
AV		 566 return QLA_FUNCTION_FAILED;
567 }
568
cfb0919c 569 ql_dbg(ql_dbg_init, vha, 0x0078,
7c3df132 570 "Verifying loaded RISC code...\n");
1da177e4 571
e315cd28
AC		 572 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
573 rval = ha->isp_ops->chip_diag(vha);
d19044c3
AV		 574 if (rval)
575 return (rval);
e315cd28 576 rval = qla2x00_setup_chip(vha);
d19044c3
AV		 577 if (rval)
578 return (rval);
1da177e4 579 }
a9083016 580
4d4df193 581 if (IS_QLA84XX(ha)) {
e315cd28 582 ha->cs84xx = qla84xx_get_chip(vha);
4d4df193 583 if (!ha->cs84xx) {
7c3df132 584 ql_log(ql_log_warn, vha, 0x00d0,
4d4df193
HK		 585 "Unable to configure ISP84XX.\n");
586 return QLA_FUNCTION_FAILED;
587 }
588 }
2d70c103
NB		 589
590 if (qla_ini_mode_enabled(vha))
591 rval = qla2x00_init_rings(vha);
592
2533cf67 593 ha->flags.chip_reset_done = 1;
1da177e4 594
9a069e19 595 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
6c452a45 596 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
9a069e19
GM		 597 rval = qla84xx_init_chip(vha);
598 if (rval != QLA_SUCCESS) {
7c3df132
SK		 599 ql_log(ql_log_warn, vha, 0x00d4,
600 "Unable to initialize ISP84XX.\n");
9a069e19
GM		 601 qla84xx_put_chip(vha);
602 }
603 }
604
7d613ac6
SV		 605 /* Load the NIC Core f/w if we are the first protocol driver. */
606 if (IS_QLA8031(ha)) {
607 rval = qla83xx_nic_core_fw_load(vha);
608 if (rval)
609 ql_log(ql_log_warn, vha, 0x0124,
610 "Error in initializing NIC Core f/w.\n");
611 }
612
2f0f3f4f
MI		 613 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
614 qla24xx_read_fcp_prio_cfg(vha);
09ff701a 615
1da177e4
LT		 616 return (rval);
617}
618
619/**
abbd8870 620 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
1da177e4
LT		 621 * @ha: HA context
622 *
623 * Returns 0 on success.
624 */
abbd8870 625int
e315cd28 626qla2100_pci_config(scsi_qla_host_t *vha)
1da177e4 627{
a157b101 628 uint16_t w;
abbd8870 629 unsigned long flags;
e315cd28 630 struct qla_hw_data *ha = vha->hw;
3d71644c 631 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 632
1da177e4 633 pci_set_master(ha->pdev);
af6177d8 634 pci_try_set_mwi(ha->pdev);
1da177e4 635
1da177e4 636 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 637 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
abbd8870
AV		 638 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
639
737faece 640 pci_disable_rom(ha->pdev);
1da177e4
LT		 641
642 /* Get PCI bus information. */
643 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 644 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
1da177e4
LT		 645 spin_unlock_irqrestore(&ha->hardware_lock, flags);
646
abbd8870
AV		 647 return QLA_SUCCESS;
648}
1da177e4 649
abbd8870
AV		 650/**
651 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
652 * @ha: HA context
653 *
654 * Returns 0 on success.
655 */
656int
e315cd28 657qla2300_pci_config(scsi_qla_host_t *vha)
abbd8870 658{
a157b101 659 uint16_t w;
abbd8870
AV		 660 unsigned long flags = 0;
661 uint32_t cnt;
e315cd28 662 struct qla_hw_data *ha = vha->hw;
3d71644c 663 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 664
abbd8870 665 pci_set_master(ha->pdev);
af6177d8 666 pci_try_set_mwi(ha->pdev);
1da177e4 667
abbd8870 668 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 669 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1da177e4 670
abbd8870
AV		 671 if (IS_QLA2322(ha) || IS_QLA6322(ha))
672 w &= ~PCI_COMMAND_INTX_DISABLE;
a157b101 673 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1da177e4 674
abbd8870
AV		 675 /*
676 * If this is a 2300 card and not 2312, reset the
677 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
678 * the 2310 also reports itself as a 2300 so we need to get the
679 * fb revision level -- a 6 indicates it really is a 2300 and
680 * not a 2310.
681 */
682 if (IS_QLA2300(ha)) {
683 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 684
abbd8870 685 /* Pause RISC. */
3d71644c 686 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
abbd8870 687 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 688 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
abbd8870 689 break;
1da177e4 690
abbd8870
AV		 691 udelay(10);
692 }
1da177e4 693
abbd8870 694 /* Select FPM registers. */
3d71644c
AV		 695 WRT_REG_WORD(&reg->ctrl_status, 0x20);
696 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 697
698 /* Get the fb rev level */
3d71644c 699 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
abbd8870
AV		 700
701 if (ha->fb_rev == FPM_2300)
a157b101 702 pci_clear_mwi(ha->pdev);
abbd8870
AV		 703
704 /* Deselect FPM registers. */
3d71644c
AV		 705 WRT_REG_WORD(&reg->ctrl_status, 0x0);
706 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 707
708 /* Release RISC module. */
3d71644c 709 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
abbd8870 710 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 711 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
abbd8870
AV		 712 break;
713
714 udelay(10);
1da177e4 715 }
1da177e4 716
abbd8870
AV		 717 spin_unlock_irqrestore(&ha->hardware_lock, flags);
718 }
1da177e4 719
abbd8870
AV		 720 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
721
737faece 722 pci_disable_rom(ha->pdev);
1da177e4 723
abbd8870
AV		 724 /* Get PCI bus information. */
725 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 726 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 727 spin_unlock_irqrestore(&ha->hardware_lock, flags);
728
729 return QLA_SUCCESS;
1da177e4
LT		 730}
731
0107109e
AV		 732/**
733 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
734 * @ha: HA context
735 *
736 * Returns 0 on success.
737 */
738int
e315cd28 739qla24xx_pci_config(scsi_qla_host_t *vha)
0107109e 740{
a157b101 741 uint16_t w;
0107109e 742 unsigned long flags = 0;
e315cd28 743 struct qla_hw_data *ha = vha->hw;
0107109e 744 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
0107109e
AV		 745
746 pci_set_master(ha->pdev);
af6177d8 747 pci_try_set_mwi(ha->pdev);
0107109e
AV		 748
749 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 750 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
0107109e
AV		 751 w &= ~PCI_COMMAND_INTX_DISABLE;
752 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
753
754 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
755
756 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
f85ec187
AV		 757 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
758 pcix_set_mmrbc(ha->pdev, 2048);
0107109e
AV		 759
760 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 761 if (pci_is_pcie(ha->pdev))
f85ec187 762 pcie_set_readrq(ha->pdev, 2048);
0107109e 763
737faece 764 pci_disable_rom(ha->pdev);
0107109e 765
44c10138 766 ha->chip_revision = ha->pdev->revision;
a8488abe 767
0107109e
AV		 768 /* Get PCI bus information. */
769 spin_lock_irqsave(&ha->hardware_lock, flags);
770 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
771 spin_unlock_irqrestore(&ha->hardware_lock, flags);
772
773 return QLA_SUCCESS;
774}
775
c3a2f0df
AV		 776/**
777 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
778 * @ha: HA context
779 *
780 * Returns 0 on success.
781 */
782int
e315cd28 783qla25xx_pci_config(scsi_qla_host_t *vha)
c3a2f0df
AV		 784{
785 uint16_t w;
e315cd28 786 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 787
788 pci_set_master(ha->pdev);
789 pci_try_set_mwi(ha->pdev);
790
791 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
792 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
793 w &= ~PCI_COMMAND_INTX_DISABLE;
794 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
795
796 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 797 if (pci_is_pcie(ha->pdev))
c3a2f0df
AV		 798 pcie_set_readrq(ha->pdev, 2048);
799
737faece 800 pci_disable_rom(ha->pdev);
c3a2f0df
AV		 801
802 ha->chip_revision = ha->pdev->revision;
803
804 return QLA_SUCCESS;
805}
806
1da177e4
LT		 807/**
808 * qla2x00_isp_firmware() - Choose firmware image.
809 * @ha: HA context
810 *
811 * Returns 0 on success.
812 */
813static int
e315cd28 814qla2x00_isp_firmware(scsi_qla_host_t *vha)
1da177e4
LT		 815{
816 int rval;
42e421b1
AV		 817 uint16_t loop_id, topo, sw_cap;
818 uint8_t domain, area, al_pa;
e315cd28 819 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 820
821 /* Assume loading risc code */
fa2a1ce5 822 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 823
824 if (ha->flags.disable_risc_code_load) {
7c3df132 825 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
1da177e4
LT		 826
827 /* Verify checksum of loaded RISC code. */
e315cd28 828 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
42e421b1
AV		 829 if (rval == QLA_SUCCESS) {
830 /* And, verify we are not in ROM code. */
e315cd28 831 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
42e421b1
AV		 832 &area, &domain, &topo, &sw_cap);
833 }
1da177e4
LT		 834 }
835
7c3df132
SK		 836 if (rval)
837 ql_dbg(ql_dbg_init, vha, 0x007a,
838 "**** Load RISC code ****.\n");
1da177e4
LT		 839
840 return (rval);
841}
842
843/**
844 * qla2x00_reset_chip() - Reset ISP chip.
845 * @ha: HA context
846 *
847 * Returns 0 on success.
848 */
abbd8870 849void
e315cd28 850qla2x00_reset_chip(scsi_qla_host_t *vha)
1da177e4
LT		 851{
852 unsigned long flags = 0;
e315cd28 853 struct qla_hw_data *ha = vha->hw;
3d71644c 854 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 855 uint32_t cnt;
1da177e4
LT		 856 uint16_t cmd;
857
85880801
AV		 858 if (unlikely(pci_channel_offline(ha->pdev)))
859 return;
860
fd34f556 861 ha->isp_ops->disable_intrs(ha);
1da177e4
LT		 862
863 spin_lock_irqsave(&ha->hardware_lock, flags);
864
865 /* Turn off master enable */
866 cmd = 0;
867 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
868 cmd &= ~PCI_COMMAND_MASTER;
869 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
870
871 if (!IS_QLA2100(ha)) {
872 /* Pause RISC. */
873 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
874 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
875 for (cnt = 0; cnt < 30000; cnt++) {
876 if ((RD_REG_WORD(&reg->hccr) &
877 HCCR_RISC_PAUSE) != 0)
878 break;
879 udelay(100);
880 }
881 } else {
882 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
883 udelay(10);
884 }
885
886 /* Select FPM registers. */
887 WRT_REG_WORD(&reg->ctrl_status, 0x20);
888 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
889
890 /* FPM Soft Reset. */
891 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
892 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
893
894 /* Toggle Fpm Reset. */
895 if (!IS_QLA2200(ha)) {
896 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
897 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
898 }
899
900 /* Select frame buffer registers. */
901 WRT_REG_WORD(&reg->ctrl_status, 0x10);
902 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
903
904 /* Reset frame buffer FIFOs. */
905 if (IS_QLA2200(ha)) {
906 WRT_FB_CMD_REG(ha, reg, 0xa000);
907 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
908 } else {
909 WRT_FB_CMD_REG(ha, reg, 0x00fc);
910
911 /* Read back fb_cmd until zero or 3 seconds max */
912 for (cnt = 0; cnt < 3000; cnt++) {
913 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
914 break;
915 udelay(100);
916 }
917 }
918
919 /* Select RISC module registers. */
920 WRT_REG_WORD(&reg->ctrl_status, 0);
921 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
922
923 /* Reset RISC processor. */
924 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
925 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
926
927 /* Release RISC processor. */
928 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
929 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
930 }
931
932 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
933 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
934
935 /* Reset ISP chip. */
936 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
937
938 /* Wait for RISC to recover from reset. */
939 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
940 /*
941 * It is necessary to for a delay here since the card doesn't
942 * respond to PCI reads during a reset. On some architectures
943 * this will result in an MCA.
944 */
945 udelay(20);
946 for (cnt = 30000; cnt; cnt--) {
947 if ((RD_REG_WORD(&reg->ctrl_status) &
948 CSR_ISP_SOFT_RESET) == 0)
949 break;
950 udelay(100);
951 }
952 } else
953 udelay(10);
954
955 /* Reset RISC processor. */
956 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
957
958 WRT_REG_WORD(&reg->semaphore, 0);
959
960 /* Release RISC processor. */
961 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
962 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
963
964 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
965 for (cnt = 0; cnt < 30000; cnt++) {
ffb39f03 966 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1da177e4 967 break;
1da177e4
LT		 968
969 udelay(100);
970 }
971 } else
972 udelay(100);
973
974 /* Turn on master enable */
975 cmd |= PCI_COMMAND_MASTER;
976 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
977
978 /* Disable RISC pause on FPM parity error. */
979 if (!IS_QLA2100(ha)) {
980 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
981 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
982 }
983
984 spin_unlock_irqrestore(&ha->hardware_lock, flags);
985}
986
b1d46989
MI		 987/**
988 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
989 *
990 * Returns 0 on success.
991 */
992int
993qla81xx_reset_mpi(scsi_qla_host_t *vha)
994{
995 uint16_t mb[4] = {0x1010, 0, 1, 0};
996
6246b8a1
GM		 997 if (!IS_QLA81XX(vha->hw))
998 return QLA_SUCCESS;
999
b1d46989
MI		 1000 return qla81xx_write_mpi_register(vha, mb);
1001}
1002
0107109e 1003/**
88c26663 1004 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
0107109e
AV		 1005 * @ha: HA context
1006 *
1007 * Returns 0 on success.
1008 */
88c26663 1009static inline void
e315cd28 1010qla24xx_reset_risc(scsi_qla_host_t *vha)
0107109e
AV		 1011{
1012 unsigned long flags = 0;
e315cd28 1013 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 1014 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1015 uint32_t cnt, d2;
335a1cc9 1016 uint16_t wd;
b1d46989 1017 static int abts_cnt; /* ISP abort retry counts */
0107109e 1018
0107109e
AV		 1019 spin_lock_irqsave(&ha->hardware_lock, flags);
1020
1021 /* Reset RISC. */
1022 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1023 for (cnt = 0; cnt < 30000; cnt++) {
1024 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
1025 break;
1026
1027 udelay(10);
1028 }
1029
1030 WRT_REG_DWORD(&reg->ctrl_status,
1031 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335a1cc9 1032 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
88c26663 1033
335a1cc9 1034 udelay(100);
88c26663 1035 /* Wait for firmware to complete NVRAM accesses. */
88c26663
AV		 1036 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1037 for (cnt = 10000 ; cnt && d2; cnt--) {
1038 udelay(5);
1039 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1040 barrier();
1041 }
1042
335a1cc9 1043 /* Wait for soft-reset to complete. */
0107109e
AV		 1044 d2 = RD_REG_DWORD(&reg->ctrl_status);
1045 for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) {
1046 udelay(5);
1047 d2 = RD_REG_DWORD(&reg->ctrl_status);
1048 barrier();
1049 }
1050
b1d46989
MI		 1051 /* If required, do an MPI FW reset now */
1052 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
1053 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
1054 if (++abts_cnt < 5) {
1055 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1056 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
1057 } else {
1058 /*
1059 * We exhausted the ISP abort retries. We have to
1060 * set the board offline.
1061 */
1062 abts_cnt = 0;
1063 vha->flags.online = 0;
1064 }
1065 }
1066 }
1067
0107109e
AV		 1068 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
1069 RD_REG_DWORD(&reg->hccr);
1070
1071 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
1072 RD_REG_DWORD(&reg->hccr);
1073
1074 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
1075 RD_REG_DWORD(&reg->hccr);
1076
1077 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1078 for (cnt = 6000000 ; cnt && d2; cnt--) {
1079 udelay(5);
1080 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1081 barrier();
1082 }
1083
1084 spin_unlock_irqrestore(&ha->hardware_lock, flags);
124f85e6
AV		 1085
1086 if (IS_NOPOLLING_TYPE(ha))
1087 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 1088}
1089
88c26663
AV		 1090/**
1091 * qla24xx_reset_chip() - Reset ISP24xx chip.
1092 * @ha: HA context
1093 *
1094 * Returns 0 on success.
1095 */
1096void
e315cd28 1097qla24xx_reset_chip(scsi_qla_host_t *vha)
88c26663 1098{
e315cd28 1099 struct qla_hw_data *ha = vha->hw;
85880801
AV		 1100
1101 if (pci_channel_offline(ha->pdev) &&
1102 ha->flags.pci_channel_io_perm_failure) {
1103 return;
1104 }
1105
fd34f556 1106 ha->isp_ops->disable_intrs(ha);
88c26663
AV		 1107
1108 /* Perform RISC reset. */
e315cd28 1109 qla24xx_reset_risc(vha);
88c26663
AV		 1110}
1111
1da177e4
LT		 1112/**
1113 * qla2x00_chip_diag() - Test chip for proper operation.
1114 * @ha: HA context
1115 *
1116 * Returns 0 on success.
1117 */
abbd8870 1118int
e315cd28 1119qla2x00_chip_diag(scsi_qla_host_t *vha)
1da177e4
LT		 1120{
1121 int rval;
e315cd28 1122 struct qla_hw_data *ha = vha->hw;
3d71644c 1123 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 1124 unsigned long flags = 0;
1125 uint16_t data;
1126 uint32_t cnt;
1127 uint16_t mb[5];
73208dfd 1128 struct req_que *req = ha->req_q_map[0];
1da177e4
LT		 1129
1130 /* Assume a failed state */
1131 rval = QLA_FUNCTION_FAILED;
1132
7c3df132
SK		 1133 ql_dbg(ql_dbg_init, vha, 0x007b,
1134 "Testing device at %lx.\n", (u_long)&reg->flash_address);
1da177e4
LT		 1135
1136 spin_lock_irqsave(&ha->hardware_lock, flags);
1137
1138 /* Reset ISP chip. */
1139 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1140
1141 /*
1142 * We need to have a delay here since the card will not respond while
1143 * in reset causing an MCA on some architectures.
1144 */
1145 udelay(20);
1146 data = qla2x00_debounce_register(&reg->ctrl_status);
1147 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
1148 udelay(5);
1149 data = RD_REG_WORD(&reg->ctrl_status);
1150 barrier();
1151 }
1152
1153 if (!cnt)
1154 goto chip_diag_failed;
1155
7c3df132
SK		 1156 ql_dbg(ql_dbg_init, vha, 0x007c,
1157 "Reset register cleared by chip reset.\n");
1da177e4
LT		 1158
1159 /* Reset RISC processor. */
1160 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1161 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1162
1163 /* Workaround for QLA2312 PCI parity error */
1164 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1165 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
1166 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
1167 udelay(5);
1168 data = RD_MAILBOX_REG(ha, reg, 0);
fa2a1ce5 1169 barrier();
1da177e4
LT		 1170 }
1171 } else
1172 udelay(10);
1173
1174 if (!cnt)
1175 goto chip_diag_failed;
1176
1177 /* Check product ID of chip */
7c3df132 1178 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
1da177e4
LT		 1179
1180 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
1181 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
1182 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
1183 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
1184 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
1185 mb[3] != PROD_ID_3) {
7c3df132
SK		 1186 ql_log(ql_log_warn, vha, 0x0062,
1187 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
1188 mb[1], mb[2], mb[3]);
1da177e4
LT		 1189
1190 goto chip_diag_failed;
1191 }
1192 ha->product_id[0] = mb[1];
1193 ha->product_id[1] = mb[2];
1194 ha->product_id[2] = mb[3];
1195 ha->product_id[3] = mb[4];
1196
1197 /* Adjust fw RISC transfer size */
73208dfd 1198 if (req->length > 1024)
1da177e4
LT		 1199 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
1200 else
1201 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
73208dfd 1202 req->length;
1da177e4
LT		 1203
1204 if (IS_QLA2200(ha) &&
1205 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
1206 /* Limit firmware transfer size with a 2200A */
7c3df132 1207 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1da177e4 1208
ea5b6382 1209 ha->device_type |= DT_ISP2200A;
1da177e4
LT		 1210 ha->fw_transfer_size = 128;
1211 }
1212
1213 /* Wrap Incoming Mailboxes Test. */
1214 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1215
7c3df132 1216 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
e315cd28 1217 rval = qla2x00_mbx_reg_test(vha);
7c3df132
SK		 1218 if (rval)
1219 ql_log(ql_log_warn, vha, 0x0080,
1220 "Failed mailbox send register test.\n");
1221 else
1da177e4
LT		 1222 /* Flag a successful rval */
1223 rval = QLA_SUCCESS;
1da177e4
LT		 1224 spin_lock_irqsave(&ha->hardware_lock, flags);
1225
1226chip_diag_failed:
1227 if (rval)
7c3df132
SK		 1228 ql_log(ql_log_info, vha, 0x0081,
1229 "Chip diagnostics **** FAILED ****.\n");
1da177e4
LT		 1230
1231 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1232
1233 return (rval);
1234}
1235
0107109e
AV		 1236/**
1237 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
1238 * @ha: HA context
1239 *
1240 * Returns 0 on success.
1241 */
1242int
e315cd28 1243qla24xx_chip_diag(scsi_qla_host_t *vha)
0107109e
AV		 1244{
1245 int rval;
e315cd28 1246 struct qla_hw_data *ha = vha->hw;
73208dfd 1247 struct req_que *req = ha->req_q_map[0];
0107109e 1248
a9083016
GM		 1249 if (IS_QLA82XX(ha))
1250 return QLA_SUCCESS;
1251
73208dfd 1252 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
0107109e 1253
e315cd28 1254 rval = qla2x00_mbx_reg_test(vha);
0107109e 1255 if (rval) {
7c3df132
SK		 1256 ql_log(ql_log_warn, vha, 0x0082,
1257 "Failed mailbox send register test.\n");
0107109e
AV		 1258 } else {
1259 /* Flag a successful rval */
1260 rval = QLA_SUCCESS;
1261 }
1262
1263 return rval;
1264}
1265
a7a167bf 1266void
e315cd28 1267qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
0107109e 1268{
a7a167bf
AV		 1269 int rval;
1270 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
73208dfd 1271 eft_size, fce_size, mq_size;
df613b96
AV		 1272 dma_addr_t tc_dma;
1273 void *tc;
e315cd28 1274 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 1275 struct req_que *req = ha->req_q_map[0];
1276 struct rsp_que *rsp = ha->rsp_q_map[0];
a7a167bf
AV		 1277
1278 if (ha->fw_dump) {
7c3df132
SK		 1279 ql_dbg(ql_dbg_init, vha, 0x00bd,
1280 "Firmware dump already allocated.\n");
a7a167bf
AV		 1281 return;
1282 }
d4e3e04d 1283
0107109e 1284 ha->fw_dumped = 0;
73208dfd 1285 fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
d4e3e04d 1286 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
a7a167bf 1287 fixed_size = sizeof(struct qla2100_fw_dump);
d4e3e04d 1288 } else if (IS_QLA23XX(ha)) {
a7a167bf
AV		 1289 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
1290 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
1291 sizeof(uint16_t);
e428924c 1292 } else if (IS_FWI2_CAPABLE(ha)) {
6246b8a1
GM		 1293 if (IS_QLA83XX(ha))
1294 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
1295 else if (IS_QLA81XX(ha))
3a03eb79
AV		 1296 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
1297 else if (IS_QLA25XX(ha))
1298 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
1299 else
1300 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
a7a167bf
AV		 1301 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
1302 sizeof(uint32_t);
050c9bb1 1303 if (ha->mqenable) {
6246b8a1
GM		 1304 if (!IS_QLA83XX(ha))
1305 mq_size = sizeof(struct qla2xxx_mq_chain);
050c9bb1
GM		 1306 /*
1307 * Allocate maximum buffer size for all queues.
1308 * Resizing must be done at end-of-dump processing.
1309 */
1310 mq_size += ha->max_req_queues *
1311 (req->length * sizeof(request_t));
1312 mq_size += ha->max_rsp_queues *
1313 (rsp->length * sizeof(response_t));
1314 }
2d70c103
NB		 1315 if (ha->tgt.atio_q_length)
1316 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
df613b96 1317 /* Allocate memory for Fibre Channel Event Buffer. */
6246b8a1 1318 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha))
436a7b11 1319 goto try_eft;
df613b96
AV		 1320
1321 tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
1322 GFP_KERNEL);
1323 if (!tc) {
7c3df132
SK		 1324 ql_log(ql_log_warn, vha, 0x00be,
1325 "Unable to allocate (%d KB) for FCE.\n",
1326 FCE_SIZE / 1024);
17d98630 1327 goto try_eft;
df613b96
AV		 1328 }
1329
1330 memset(tc, 0, FCE_SIZE);
e315cd28 1331 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
df613b96
AV		 1332 ha->fce_mb, &ha->fce_bufs);
1333 if (rval) {
7c3df132
SK		 1334 ql_log(ql_log_warn, vha, 0x00bf,
1335 "Unable to initialize FCE (%d).\n", rval);
df613b96
AV		 1336 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
1337 tc_dma);
1338 ha->flags.fce_enabled = 0;
17d98630 1339 goto try_eft;
df613b96 1340 }
cfb0919c 1341 ql_dbg(ql_dbg_init, vha, 0x00c0,
7c3df132 1342 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
df613b96 1343
7d9dade3 1344 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
df613b96
AV		 1345 ha->flags.fce_enabled = 1;
1346 ha->fce_dma = tc_dma;
1347 ha->fce = tc;
436a7b11
AV		 1348try_eft:
1349 /* Allocate memory for Extended Trace Buffer. */
1350 tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
1351 GFP_KERNEL);
1352 if (!tc) {
7c3df132
SK		 1353 ql_log(ql_log_warn, vha, 0x00c1,
1354 "Unable to allocate (%d KB) for EFT.\n",
1355 EFT_SIZE / 1024);
436a7b11
AV		 1356 goto cont_alloc;
1357 }
1358
1359 memset(tc, 0, EFT_SIZE);
e315cd28 1360 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
436a7b11 1361 if (rval) {
7c3df132
SK		 1362 ql_log(ql_log_warn, vha, 0x00c2,
1363 "Unable to initialize EFT (%d).\n", rval);
436a7b11
AV		 1364 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
1365 tc_dma);
1366 goto cont_alloc;
1367 }
cfb0919c 1368 ql_dbg(ql_dbg_init, vha, 0x00c3,
7c3df132 1369 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
436a7b11
AV		 1370
1371 eft_size = EFT_SIZE;
1372 ha->eft_dma = tc_dma;
1373 ha->eft = tc;
d4e3e04d 1374 }
a7a167bf 1375cont_alloc:
73208dfd
AC		 1376 req_q_size = req->length * sizeof(request_t);
1377 rsp_q_size = rsp->length * sizeof(response_t);
a7a167bf
AV		 1378
1379 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
2afa19a9 1380 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
bb99de67
AV		 1381 ha->chain_offset = dump_size;
1382 dump_size += mq_size + fce_size;
d4e3e04d
AV		 1383
1384 ha->fw_dump = vmalloc(dump_size);
a7a167bf 1385 if (!ha->fw_dump) {
7c3df132
SK		 1386 ql_log(ql_log_warn, vha, 0x00c4,
1387 "Unable to allocate (%d KB) for firmware dump.\n",
1388 dump_size / 1024);
a7a167bf 1389
e30d1756
MI		 1390 if (ha->fce) {
1391 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
1392 ha->fce_dma);
1393 ha->fce = NULL;
1394 ha->fce_dma = 0;
1395 }
1396
a7a167bf
AV		 1397 if (ha->eft) {
1398 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
1399 ha->eft_dma);
1400 ha->eft = NULL;
1401 ha->eft_dma = 0;
1402 }
1403 return;
1404 }
cfb0919c 1405 ql_dbg(ql_dbg_init, vha, 0x00c5,
7c3df132 1406 "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
a7a167bf
AV		 1407
1408 ha->fw_dump_len = dump_size;
1409 ha->fw_dump->signature[0] = 'Q';
1410 ha->fw_dump->signature[1] = 'L';
1411 ha->fw_dump->signature[2] = 'G';
1412 ha->fw_dump->signature[3] = 'C';
1413 ha->fw_dump->version = __constant_htonl(1);
1414
1415 ha->fw_dump->fixed_size = htonl(fixed_size);
1416 ha->fw_dump->mem_size = htonl(mem_size);
1417 ha->fw_dump->req_q_size = htonl(req_q_size);
1418 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
1419
1420 ha->fw_dump->eft_size = htonl(eft_size);
1421 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
1422 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
1423
1424 ha->fw_dump->header_size =
1425 htonl(offsetof(struct qla2xxx_fw_dump, isp));
0107109e
AV		 1426}
1427
18e7555a
AV		 1428static int
1429qla81xx_mpi_sync(scsi_qla_host_t *vha)
1430{
1431#define MPS_MASK 0xe0
1432 int rval;
1433 uint16_t dc;
1434 uint32_t dw;
18e7555a
AV		 1435
1436 if (!IS_QLA81XX(vha->hw))
1437 return QLA_SUCCESS;
1438
1439 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
1440 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1441 ql_log(ql_log_warn, vha, 0x0105,
1442 "Unable to acquire semaphore.\n");
18e7555a
AV		 1443 goto done;
1444 }
1445
1446 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
1447 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
1448 if (rval != QLA_SUCCESS) {
7c3df132 1449 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
18e7555a
AV		 1450 goto done_release;
1451 }
1452
1453 dc &= MPS_MASK;
1454 if (dc == (dw & MPS_MASK))
1455 goto done_release;
1456
1457 dw &= ~MPS_MASK;
1458 dw |= dc;
1459 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
1460 if (rval != QLA_SUCCESS) {
7c3df132 1461 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
18e7555a
AV		 1462 }
1463
1464done_release:
1465 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
1466 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1467 ql_log(ql_log_warn, vha, 0x006d,
1468 "Unable to release semaphore.\n");
18e7555a
AV		 1469 }
1470
1471done:
1472 return rval;
1473}
1474
1da177e4
LT		 1475/**
1476 * qla2x00_setup_chip() - Load and start RISC firmware.
1477 * @ha: HA context
1478 *
1479 * Returns 0 on success.
1480 */
1481static int
e315cd28 1482qla2x00_setup_chip(scsi_qla_host_t *vha)
1da177e4 1483{
0107109e
AV		 1484 int rval;
1485 uint32_t srisc_address = 0;
e315cd28 1486 struct qla_hw_data *ha = vha->hw;
3db0652e
AV		 1487 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1488 unsigned long flags;
dda772e8 1489 uint16_t fw_major_version;
3db0652e 1490
a9083016
GM		 1491 if (IS_QLA82XX(ha)) {
1492 rval = ha->isp_ops->load_risc(vha, &srisc_address);
14e303d9
AV		 1493 if (rval == QLA_SUCCESS) {
1494 qla2x00_stop_firmware(vha);
a9083016 1495 goto enable_82xx_npiv;
14e303d9 1496 } else
b963752f 1497 goto failed;
a9083016
GM		 1498 }
1499
3db0652e
AV		 1500 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1501 /* Disable SRAM, Instruction RAM and GP RAM parity. */
1502 spin_lock_irqsave(&ha->hardware_lock, flags);
1503 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
1504 RD_REG_WORD(&reg->hccr);
1505 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1506 }
1da177e4 1507
18e7555a
AV		 1508 qla81xx_mpi_sync(vha);
1509
1da177e4 1510 /* Load firmware sequences */
e315cd28 1511 rval = ha->isp_ops->load_risc(vha, &srisc_address);
0107109e 1512 if (rval == QLA_SUCCESS) {
7c3df132
SK		 1513 ql_dbg(ql_dbg_init, vha, 0x00c9,
1514 "Verifying Checksum of loaded RISC code.\n");
1da177e4 1515
e315cd28 1516 rval = qla2x00_verify_checksum(vha, srisc_address);
1da177e4
LT		 1517 if (rval == QLA_SUCCESS) {
1518 /* Start firmware execution. */
7c3df132
SK		 1519 ql_dbg(ql_dbg_init, vha, 0x00ca,
1520 "Starting firmware.\n");
1da177e4 1521
e315cd28 1522 rval = qla2x00_execute_fw(vha, srisc_address);
1da177e4 1523 /* Retrieve firmware information. */
dda772e8 1524 if (rval == QLA_SUCCESS) {
a9083016 1525enable_82xx_npiv:
dda772e8 1526 fw_major_version = ha->fw_major_version;
3173167f
GM		 1527 if (IS_QLA82XX(ha))
1528 qla82xx_check_md_needed(vha);
6246b8a1
GM		 1529 else
1530 rval = qla2x00_get_fw_version(vha);
ca9e9c3e
AV		 1531 if (rval != QLA_SUCCESS)
1532 goto failed;
2c3dfe3f 1533 ha->flags.npiv_supported = 0;
e315cd28 1534 if (IS_QLA2XXX_MIDTYPE(ha) &&
946fb891 1535 (ha->fw_attributes & BIT_2)) {
2c3dfe3f 1536 ha->flags.npiv_supported = 1;
4d0ea247
SJ		 1537 if ((!ha->max_npiv_vports) ||
1538 ((ha->max_npiv_vports + 1) %
eb66dc60 1539 MIN_MULTI_ID_FABRIC))
4d0ea247 1540 ha->max_npiv_vports =
eb66dc60 1541 MIN_MULTI_ID_FABRIC - 1;
4d0ea247 1542 }
24a08138
AV		 1543 qla2x00_get_resource_cnts(vha, NULL,
1544 &ha->fw_xcb_count, NULL, NULL,
f3a0a77e 1545 &ha->max_npiv_vports, NULL);
d743de66 1546
be5ea3cf
SK		 1547 if (!fw_major_version && ql2xallocfwdump
1548 && !IS_QLA82XX(ha))
08de2844 1549 qla2x00_alloc_fw_dump(vha);
1da177e4
LT		 1550 }
1551 } else {
7c3df132
SK		 1552 ql_log(ql_log_fatal, vha, 0x00cd,
1553 "ISP Firmware failed checksum.\n");
1554 goto failed;
1da177e4
LT		 1555 }
1556 }
1557
3db0652e
AV		 1558 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1559 /* Enable proper parity. */
1560 spin_lock_irqsave(&ha->hardware_lock, flags);
1561 if (IS_QLA2300(ha))
1562 /* SRAM parity */
1563 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
1564 else
1565 /* SRAM, Instruction RAM and GP RAM parity */
1566 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
1567 RD_REG_WORD(&reg->hccr);
1568 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1569 }
1570
6246b8a1
GM		 1571 if (IS_QLA83XX(ha))
1572 goto skip_fac_check;
1573
1d2874de
JC		 1574 if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1575 uint32_t size;
1576
1577 rval = qla81xx_fac_get_sector_size(vha, &size);
1578 if (rval == QLA_SUCCESS) {
1579 ha->flags.fac_supported = 1;
1580 ha->fdt_block_size = size << 2;
1581 } else {
7c3df132 1582 ql_log(ql_log_warn, vha, 0x00ce,
1d2874de
JC		 1583 "Unsupported FAC firmware (%d.%02d.%02d).\n",
1584 ha->fw_major_version, ha->fw_minor_version,
1585 ha->fw_subminor_version);
6246b8a1
GM		 1586skip_fac_check:
1587 if (IS_QLA83XX(ha)) {
1588 ha->flags.fac_supported = 0;
1589 rval = QLA_SUCCESS;
1590 }
1d2874de
JC		 1591 }
1592 }
ca9e9c3e 1593failed:
1da177e4 1594 if (rval) {
7c3df132
SK		 1595 ql_log(ql_log_fatal, vha, 0x00cf,
1596 "Setup chip ****FAILED****.\n");
1da177e4
LT		 1597 }
1598
1599 return (rval);
1600}
1601
1602/**
1603 * qla2x00_init_response_q_entries() - Initializes response queue entries.
1604 * @ha: HA context
1605 *
1606 * Beginning of request ring has initialization control block already built
1607 * by nvram config routine.
1608 *
1609 * Returns 0 on success.
1610 */
73208dfd
AC		 1611void
1612qla2x00_init_response_q_entries(struct rsp_que *rsp)
1da177e4
LT		 1613{
1614 uint16_t cnt;
1615 response_t *pkt;
1616
2afa19a9
AC		 1617 rsp->ring_ptr = rsp->ring;
1618 rsp->ring_index = 0;
1619 rsp->status_srb = NULL;
e315cd28
AC		 1620 pkt = rsp->ring_ptr;
1621 for (cnt = 0; cnt < rsp->length; cnt++) {
1da177e4
LT		 1622 pkt->signature = RESPONSE_PROCESSED;
1623 pkt++;
1624 }
1da177e4
LT		 1625}
1626
1627/**
1628 * qla2x00_update_fw_options() - Read and process firmware options.
1629 * @ha: HA context
1630 *
1631 * Returns 0 on success.
1632 */
abbd8870 1633void
e315cd28 1634qla2x00_update_fw_options(scsi_qla_host_t *vha)
1da177e4
LT		 1635{
1636 uint16_t swing, emphasis, tx_sens, rx_sens;
e315cd28 1637 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 1638
1639 memset(ha->fw_options, 0, sizeof(ha->fw_options));
e315cd28 1640 qla2x00_get_fw_options(vha, ha->fw_options);
1da177e4
LT		 1641
1642 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1643 return;
1644
1645 /* Serial Link options. */
7c3df132
SK		 1646 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
1647 "Serial link options.\n");
1648 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
1649 (uint8_t *)&ha->fw_seriallink_options,
1650 sizeof(ha->fw_seriallink_options));
1da177e4
LT		 1651
1652 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1653 if (ha->fw_seriallink_options[3] & BIT_2) {
1654 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
1655
1656 /* 1G settings */
1657 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
1658 emphasis = (ha->fw_seriallink_options[2] &
1659 (BIT_4 | BIT_3)) >> 3;
1660 tx_sens = ha->fw_seriallink_options[0] &
fa2a1ce5 1661 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1662 rx_sens = (ha->fw_seriallink_options[0] &
1663 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1664 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
1665 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1666 if (rx_sens == 0x0)
1667 rx_sens = 0x3;
1668 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
1669 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1670 ha->fw_options[10] |= BIT_5 |
1671 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1672 (tx_sens & (BIT_1 | BIT_0));
1673
1674 /* 2G settings */
1675 swing = (ha->fw_seriallink_options[2] &
1676 (BIT_7 | BIT_6 | BIT_5)) >> 5;
1677 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
1678 tx_sens = ha->fw_seriallink_options[1] &
fa2a1ce5 1679 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1680 rx_sens = (ha->fw_seriallink_options[1] &
1681 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1682 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
1683 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1684 if (rx_sens == 0x0)
1685 rx_sens = 0x3;
1686 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
1687 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1688 ha->fw_options[11] |= BIT_5 |
1689 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1690 (tx_sens & (BIT_1 | BIT_0));
1691 }
1692
1693 /* FCP2 options. */
1694 /* Return command IOCBs without waiting for an ABTS to complete. */
1695 ha->fw_options[3] |= BIT_13;
1696
1697 /* LED scheme. */
1698 if (ha->flags.enable_led_scheme)
1699 ha->fw_options[2] |= BIT_12;
1700
48c02fde 1701 /* Detect ISP6312. */
1702 if (IS_QLA6312(ha))
1703 ha->fw_options[2] |= BIT_13;
1704
1da177e4 1705 /* Update firmware options. */
e315cd28 1706 qla2x00_set_fw_options(vha, ha->fw_options);
1da177e4
LT		 1707}
1708
0107109e 1709void
e315cd28 1710qla24xx_update_fw_options(scsi_qla_host_t *vha)
0107109e
AV		 1711{
1712 int rval;
e315cd28 1713 struct qla_hw_data *ha = vha->hw;
0107109e 1714
a9083016
GM		 1715 if (IS_QLA82XX(ha))
1716 return;
1717
0107109e 1718 /* Update Serial Link options. */
f94097ed 1719 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
0107109e
AV		 1720 return;
1721
e315cd28 1722 rval = qla2x00_set_serdes_params(vha,
f94097ed 1723 le16_to_cpu(ha->fw_seriallink_options24[1]),
1724 le16_to_cpu(ha->fw_seriallink_options24[2]),
1725 le16_to_cpu(ha->fw_seriallink_options24[3]));
0107109e 1726 if (rval != QLA_SUCCESS) {
7c3df132 1727 ql_log(ql_log_warn, vha, 0x0104,
0107109e
AV		 1728 "Unable to update Serial Link options (%x).\n", rval);
1729 }
1730}
1731
abbd8870 1732void
e315cd28 1733qla2x00_config_rings(struct scsi_qla_host *vha)
abbd8870 1734{
e315cd28 1735 struct qla_hw_data *ha = vha->hw;
3d71644c 1736 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
73208dfd
AC		 1737 struct req_que *req = ha->req_q_map[0];
1738 struct rsp_que *rsp = ha->rsp_q_map[0];
abbd8870
AV		 1739
1740 /* Setup ring parameters in initialization control block. */
1741 ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0);
1742 ha->init_cb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 1743 ha->init_cb->request_q_length = cpu_to_le16(req->length);
1744 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
1745 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1746 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1747 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1748 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
abbd8870
AV		 1749
1750 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
1751 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
1752 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
1753 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
1754 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
1755}
1756
0107109e 1757void
e315cd28 1758qla24xx_config_rings(struct scsi_qla_host *vha)
0107109e 1759{
e315cd28 1760 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 1761 device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0);
1762 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
1763 struct qla_msix_entry *msix;
0107109e 1764 struct init_cb_24xx *icb;
73208dfd
AC		 1765 uint16_t rid = 0;
1766 struct req_que *req = ha->req_q_map[0];
1767 struct rsp_que *rsp = ha->rsp_q_map[0];
0107109e 1768
6246b8a1 1769 /* Setup ring parameters in initialization control block. */
0107109e
AV		 1770 icb = (struct init_cb_24xx *)ha->init_cb;
1771 icb->request_q_outpointer = __constant_cpu_to_le16(0);
1772 icb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 1773 icb->request_q_length = cpu_to_le16(req->length);
1774 icb->response_q_length = cpu_to_le16(rsp->length);
1775 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1776 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1777 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1778 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
0107109e 1779
2d70c103
NB		 1780 /* Setup ATIO queue dma pointers for target mode */
1781 icb->atio_q_inpointer = __constant_cpu_to_le16(0);
1782 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
1783 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
1784 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
1785
6246b8a1 1786 if (ha->mqenable || IS_QLA83XX(ha)) {
73208dfd
AC		 1787 icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS);
1788 icb->rid = __constant_cpu_to_le16(rid);
1789 if (ha->flags.msix_enabled) {
1790 msix = &ha->msix_entries[1];
7c3df132
SK		 1791 ql_dbg(ql_dbg_init, vha, 0x00fd,
1792 "Registering vector 0x%x for base que.\n",
1793 msix->entry);
73208dfd
AC		 1794 icb->msix = cpu_to_le16(msix->entry);
1795 }
1796 /* Use alternate PCI bus number */
1797 if (MSB(rid))
1798 icb->firmware_options_2 |=
1799 __constant_cpu_to_le32(BIT_19);
1800 /* Use alternate PCI devfn */
1801 if (LSB(rid))
1802 icb->firmware_options_2 |=
1803 __constant_cpu_to_le32(BIT_18);
1804
3155754a 1805 /* Use Disable MSIX Handshake mode for capable adapters */
6246b8a1
GM		 1806 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
1807 (ha->flags.msix_enabled)) {
3155754a
AC		 1808 icb->firmware_options_2 &=
1809 __constant_cpu_to_le32(~BIT_22);
1810 ha->flags.disable_msix_handshake = 1;
7c3df132
SK		 1811 ql_dbg(ql_dbg_init, vha, 0x00fe,
1812 "MSIX Handshake Disable Mode turned on.\n");
3155754a
AC		 1813 } else {
1814 icb->firmware_options_2 |=
1815 __constant_cpu_to_le32(BIT_22);
1816 }
73208dfd 1817 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_23);
73208dfd
AC		 1818
1819 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
1820 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
1821 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
1822 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
1823 } else {
1824 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
1825 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
1826 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
1827 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
1828 }
2d70c103
NB		 1829 qlt_24xx_config_rings(vha, reg);
1830
73208dfd
AC		 1831 /* PCI posting */
1832 RD_REG_DWORD(&ioreg->hccr);
0107109e
AV		 1833}
1834
1da177e4
LT		 1835/**
1836 * qla2x00_init_rings() - Initializes firmware.
1837 * @ha: HA context
1838 *
1839 * Beginning of request ring has initialization control block already built
1840 * by nvram config routine.
1841 *
1842 * Returns 0 on success.
1843 */
1844static int
e315cd28 1845qla2x00_init_rings(scsi_qla_host_t *vha)
1da177e4
LT		 1846{
1847 int rval;
1848 unsigned long flags = 0;
29bdccbe 1849 int cnt, que;
e315cd28 1850 struct qla_hw_data *ha = vha->hw;
29bdccbe
AC		 1851 struct req_que *req;
1852 struct rsp_que *rsp;
2c3dfe3f
SJ		 1853 struct mid_init_cb_24xx *mid_init_cb =
1854 (struct mid_init_cb_24xx *) ha->init_cb;
1da177e4
LT		 1855
1856 spin_lock_irqsave(&ha->hardware_lock, flags);
1857
1858 /* Clear outstanding commands array. */
2afa19a9 1859 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe
AC		 1860 req = ha->req_q_map[que];
1861 if (!req)
1862 continue;
2afa19a9 1863 for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++)
29bdccbe 1864 req->outstanding_cmds[cnt] = NULL;
1da177e4 1865
2afa19a9 1866 req->current_outstanding_cmd = 1;
1da177e4 1867
29bdccbe
AC		 1868 /* Initialize firmware. */
1869 req->ring_ptr = req->ring;
1870 req->ring_index = 0;
1871 req->cnt = req->length;
1872 }
1da177e4 1873
2afa19a9 1874 for (que = 0; que < ha->max_rsp_queues; que++) {
29bdccbe
AC		 1875 rsp = ha->rsp_q_map[que];
1876 if (!rsp)
1877 continue;
29bdccbe
AC		 1878 /* Initialize response queue entries */
1879 qla2x00_init_response_q_entries(rsp);
1880 }
1da177e4 1881
542bce1f 1882 spin_lock(&ha->vport_slock);
feafb7b1 1883
542bce1f 1884 spin_unlock(&ha->vport_slock);
feafb7b1 1885
2d70c103
NB		 1886 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
1887 ha->tgt.atio_ring_index = 0;
1888 /* Initialize ATIO queue entries */
1889 qlt_init_atio_q_entries(vha);
1890
e315cd28 1891 ha->isp_ops->config_rings(vha);
1da177e4
LT		 1892
1893 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1894
1895 /* Update any ISP specific firmware options before initialization. */
e315cd28 1896 ha->isp_ops->update_fw_options(vha);
1da177e4 1897
7c3df132 1898 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
2c3dfe3f 1899
605aa2bc
LC		 1900 if (ha->flags.npiv_supported) {
1901 if (ha->operating_mode == LOOP)
1902 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
c48339de 1903 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
605aa2bc
LC		 1904 }
1905
24a08138
AV		 1906 if (IS_FWI2_CAPABLE(ha)) {
1907 mid_init_cb->options = __constant_cpu_to_le16(BIT_1);
1908 mid_init_cb->init_cb.execution_throttle =
1909 cpu_to_le16(ha->fw_xcb_count);
1910 }
2c3dfe3f 1911
e315cd28 1912 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
1da177e4 1913 if (rval) {
7c3df132
SK		 1914 ql_log(ql_log_fatal, vha, 0x00d2,
1915 "Init Firmware **** FAILED ****.\n");
1da177e4 1916 } else {
7c3df132
SK		 1917 ql_dbg(ql_dbg_init, vha, 0x00d3,
1918 "Init Firmware -- success.\n");
1da177e4
LT		 1919 }
1920
1921 return (rval);
1922}
1923
1924/**
1925 * qla2x00_fw_ready() - Waits for firmware ready.
1926 * @ha: HA context
1927 *
1928 * Returns 0 on success.
1929 */
1930static int
e315cd28 1931qla2x00_fw_ready(scsi_qla_host_t *vha)
1da177e4
LT		 1932{
1933 int rval;
4d4df193 1934 unsigned long wtime, mtime, cs84xx_time;
1da177e4
LT		 1935 uint16_t min_wait; /* Minimum wait time if loop is down */
1936 uint16_t wait_time; /* Wait time if loop is coming ready */
656e8912 1937 uint16_t state[5];
e315cd28 1938 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 1939
1940 rval = QLA_SUCCESS;
1941
1942 /* 20 seconds for loop down. */
fa2a1ce5 1943 min_wait = 20;
1da177e4
LT		 1944
1945 /*
1946 * Firmware should take at most one RATOV to login, plus 5 seconds for
1947 * our own processing.
1948 */
1949 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
1950 wait_time = min_wait;
1951 }
1952
1953 /* Min wait time if loop down */
1954 mtime = jiffies + (min_wait * HZ);
1955
1956 /* wait time before firmware ready */
1957 wtime = jiffies + (wait_time * HZ);
1958
1959 /* Wait for ISP to finish LIP */
e315cd28 1960 if (!vha->flags.init_done)
7c3df132
SK		 1961 ql_log(ql_log_info, vha, 0x801e,
1962 "Waiting for LIP to complete.\n");
1da177e4
LT		 1963
1964 do {
e315cd28 1965 rval = qla2x00_get_firmware_state(vha, state);
1da177e4 1966 if (rval == QLA_SUCCESS) {
4d4df193 1967 if (state[0] < FSTATE_LOSS_OF_SYNC) {
e315cd28 1968 vha->device_flags &= ~DFLG_NO_CABLE;
1da177e4 1969 }
4d4df193 1970 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
7c3df132
SK		 1971 ql_dbg(ql_dbg_taskm, vha, 0x801f,
1972 "fw_state=%x 84xx=%x.\n", state[0],
1973 state[2]);
4d4df193
HK		 1974 if ((state[2] & FSTATE_LOGGED_IN) &&
1975 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
7c3df132
SK		 1976 ql_dbg(ql_dbg_taskm, vha, 0x8028,
1977 "Sending verify iocb.\n");
4d4df193
HK		 1978
1979 cs84xx_time = jiffies;
e315cd28 1980 rval = qla84xx_init_chip(vha);
7c3df132
SK		 1981 if (rval != QLA_SUCCESS) {
1982 ql_log(ql_log_warn,
cfb0919c 1983 vha, 0x8007,
7c3df132 1984 "Init chip failed.\n");
4d4df193 1985 break;
7c3df132 1986 }
4d4df193
HK		 1987
1988 /* Add time taken to initialize. */
1989 cs84xx_time = jiffies - cs84xx_time;
1990 wtime += cs84xx_time;
1991 mtime += cs84xx_time;
cfb0919c 1992 ql_dbg(ql_dbg_taskm, vha, 0x8008,
7c3df132
SK		 1993 "Increasing wait time by %ld. "
1994 "New time %ld.\n", cs84xx_time,
1995 wtime);
4d4df193
HK		 1996 }
1997 } else if (state[0] == FSTATE_READY) {
7c3df132
SK		 1998 ql_dbg(ql_dbg_taskm, vha, 0x8037,
1999 "F/W Ready - OK.\n");
1da177e4 2000
e315cd28 2001 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1da177e4
LT		 2002 &ha->login_timeout, &ha->r_a_tov);
2003
2004 rval = QLA_SUCCESS;
2005 break;
2006 }
2007
2008 rval = QLA_FUNCTION_FAILED;
2009
e315cd28 2010 if (atomic_read(&vha->loop_down_timer) &&
4d4df193 2011 state[0] != FSTATE_READY) {
1da177e4 2012 /* Loop down. Timeout on min_wait for states
fa2a1ce5
AV		 2013 * other than Wait for Login.
2014 */
1da177e4 2015 if (time_after_eq(jiffies, mtime)) {
7c3df132 2016 ql_log(ql_log_info, vha, 0x8038,
1da177e4
LT		 2017 "Cable is unplugged...\n");
2018
e315cd28 2019 vha->device_flags |= DFLG_NO_CABLE;
1da177e4
LT		 2020 break;
2021 }
2022 }
2023 } else {
2024 /* Mailbox cmd failed. Timeout on min_wait. */
cdbb0a4f 2025 if (time_after_eq(jiffies, mtime) ||
7190575f 2026 ha->flags.isp82xx_fw_hung)
1da177e4
LT		 2027 break;
2028 }
2029
2030 if (time_after_eq(jiffies, wtime))
2031 break;
2032
2033 /* Delay for a while */
2034 msleep(500);
1da177e4
LT		 2035 } while (1);
2036
7c3df132
SK		 2037 ql_dbg(ql_dbg_taskm, vha, 0x803a,
2038 "fw_state=%x (%x, %x, %x, %x) " "curr time=%lx.\n", state[0],
2039 state[1], state[2], state[3], state[4], jiffies);
1da177e4 2040
cfb0919c 2041 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132
SK		 2042 ql_log(ql_log_warn, vha, 0x803b,
2043 "Firmware ready **** FAILED ****.\n");
1da177e4
LT		 2044 }
2045
2046 return (rval);
2047}
2048
2049/*
2050* qla2x00_configure_hba
2051* Setup adapter context.
2052*
2053* Input:
2054* ha = adapter state pointer.
2055*
2056* Returns:
2057* 0 = success
2058*
2059* Context:
2060* Kernel context.
2061*/
2062static int
e315cd28 2063qla2x00_configure_hba(scsi_qla_host_t *vha)
1da177e4
LT		 2064{
2065 int rval;
2066 uint16_t loop_id;
2067 uint16_t topo;
2c3dfe3f 2068 uint16_t sw_cap;
1da177e4
LT		 2069 uint8_t al_pa;
2070 uint8_t area;
2071 uint8_t domain;
2072 char connect_type[22];
e315cd28 2073 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2074
2075 /* Get host addresses. */
e315cd28 2076 rval = qla2x00_get_adapter_id(vha,
2c3dfe3f 2077 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
1da177e4 2078 if (rval != QLA_SUCCESS) {
e315cd28 2079 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
6246b8a1 2080 IS_CNA_CAPABLE(ha) ||
33135aa2 2081 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
7c3df132
SK		 2082 ql_dbg(ql_dbg_disc, vha, 0x2008,
2083 "Loop is in a transition state.\n");
33135aa2 2084 } else {
7c3df132
SK		 2085 ql_log(ql_log_warn, vha, 0x2009,
2086 "Unable to get host loop ID.\n");
e315cd28 2087 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
33135aa2 2088 }
1da177e4
LT		 2089 return (rval);
2090 }
2091
2092 if (topo == 4) {
7c3df132
SK		 2093 ql_log(ql_log_info, vha, 0x200a,
2094 "Cannot get topology - retrying.\n");
1da177e4
LT		 2095 return (QLA_FUNCTION_FAILED);
2096 }
2097
e315cd28 2098 vha->loop_id = loop_id;
1da177e4
LT		 2099
2100 /* initialize */
2101 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
2102 ha->operating_mode = LOOP;
2c3dfe3f 2103 ha->switch_cap = 0;
1da177e4
LT		 2104
2105 switch (topo) {
2106 case 0:
7c3df132 2107 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
1da177e4
LT		 2108 ha->current_topology = ISP_CFG_NL;
2109 strcpy(connect_type, "(Loop)");
2110 break;
2111
2112 case 1:
7c3df132 2113 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2c3dfe3f 2114 ha->switch_cap = sw_cap;
1da177e4
LT		 2115 ha->current_topology = ISP_CFG_FL;
2116 strcpy(connect_type, "(FL_Port)");
2117 break;
2118
2119 case 2:
7c3df132 2120 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
1da177e4
LT		 2121 ha->operating_mode = P2P;
2122 ha->current_topology = ISP_CFG_N;
2123 strcpy(connect_type, "(N_Port-to-N_Port)");
2124 break;
2125
2126 case 3:
7c3df132 2127 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2c3dfe3f 2128 ha->switch_cap = sw_cap;
1da177e4
LT		 2129 ha->operating_mode = P2P;
2130 ha->current_topology = ISP_CFG_F;
2131 strcpy(connect_type, "(F_Port)");
2132 break;
2133
2134 default:
7c3df132
SK		 2135 ql_dbg(ql_dbg_disc, vha, 0x200f,
2136 "HBA in unknown topology %x, using NL.\n", topo);
1da177e4
LT		 2137 ha->current_topology = ISP_CFG_NL;
2138 strcpy(connect_type, "(Loop)");
2139 break;
2140 }
2141
2142 /* Save Host port and loop ID. */
2143 /* byte order - Big Endian */
e315cd28
AC		 2144 vha->d_id.b.domain = domain;
2145 vha->d_id.b.area = area;
2146 vha->d_id.b.al_pa = al_pa;
1da177e4 2147
2d70c103
NB		 2148 spin_lock(&ha->vport_slock);
2149 qlt_update_vp_map(vha, SET_AL_PA);
2150 spin_unlock(&ha->vport_slock);
2151
e315cd28 2152 if (!vha->flags.init_done)
7c3df132
SK		 2153 ql_log(ql_log_info, vha, 0x2010,
2154 "Topology - %s, Host Loop address 0x%x.\n",
e315cd28 2155 connect_type, vha->loop_id);
1da177e4
LT		 2156
2157 if (rval) {
7c3df132
SK		 2158 ql_log(ql_log_warn, vha, 0x2011,
2159 "%s FAILED\n", __func__);
1da177e4 2160 } else {
7c3df132
SK		 2161 ql_dbg(ql_dbg_disc, vha, 0x2012,
2162 "%s success\n", __func__);
1da177e4
LT		 2163 }
2164
2165 return(rval);
2166}
2167
a9083016 2168inline void
e315cd28
AC		 2169qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
2170 char *def)
9bb9fcf2
AV		 2171{
2172 char *st, *en;
2173 uint16_t index;
e315cd28 2174 struct qla_hw_data *ha = vha->hw;
ab671149 2175 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
6246b8a1 2176 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
9bb9fcf2
AV		 2177
2178 if (memcmp(model, BINZERO, len) != 0) {
2179 strncpy(ha->model_number, model, len);
2180 st = en = ha->model_number;
2181 en += len - 1;
2182 while (en > st) {
2183 if (*en != 0x20 && *en != 0x00)
2184 break;
2185 *en-- = '\0';
2186 }
2187
2188 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2189 if (use_tbl &&
2190 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 2191 index < QLA_MODEL_NAMES)
1ee27146
JC		 2192 strncpy(ha->model_desc,
2193 qla2x00_model_name[index * 2 + 1],
2194 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2195 } else {
2196 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2197 if (use_tbl &&
2198 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2
AV		 2199 index < QLA_MODEL_NAMES) {
2200 strcpy(ha->model_number,
2201 qla2x00_model_name[index * 2]);
1ee27146
JC		 2202 strncpy(ha->model_desc,
2203 qla2x00_model_name[index * 2 + 1],
2204 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2205 } else {
2206 strcpy(ha->model_number, def);
2207 }
2208 }
1ee27146 2209 if (IS_FWI2_CAPABLE(ha))
e315cd28 2210 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
1ee27146 2211 sizeof(ha->model_desc));
9bb9fcf2
AV		 2212}
2213
4e08df3f
DM		 2214/* On sparc systems, obtain port and node WWN from firmware
2215 * properties.
2216 */
e315cd28 2217static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4e08df3f
DM		 2218{
2219#ifdef CONFIG_SPARC
e315cd28 2220 struct qla_hw_data *ha = vha->hw;
4e08df3f 2221 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 2222 struct device_node *dp = pci_device_to_OF_node(pdev);
2223 const u8 *val;
4e08df3f
DM		 2224 int len;
2225
2226 val = of_get_property(dp, "port-wwn", &len);
2227 if (val && len >= WWN_SIZE)
2228 memcpy(nv->port_name, val, WWN_SIZE);
2229
2230 val = of_get_property(dp, "node-wwn", &len);
2231 if (val && len >= WWN_SIZE)
2232 memcpy(nv->node_name, val, WWN_SIZE);
2233#endif
2234}
2235
1da177e4
LT		 2236/*
2237* NVRAM configuration for ISP 2xxx
2238*
2239* Input:
2240* ha = adapter block pointer.
2241*
2242* Output:
2243* initialization control block in response_ring
2244* host adapters parameters in host adapter block
2245*
2246* Returns:
2247* 0 = success.
2248*/
abbd8870 2249int
e315cd28 2250qla2x00_nvram_config(scsi_qla_host_t *vha)
1da177e4 2251{
4e08df3f 2252 int rval;
0107109e
AV		 2253 uint8_t chksum = 0;
2254 uint16_t cnt;
2255 uint8_t *dptr1, *dptr2;
e315cd28 2256 struct qla_hw_data *ha = vha->hw;
0107109e 2257 init_cb_t *icb = ha->init_cb;
281afe19
SJ		 2258 nvram_t *nv = ha->nvram;
2259 uint8_t *ptr = ha->nvram;
3d71644c 2260 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2261
4e08df3f
DM		 2262 rval = QLA_SUCCESS;
2263
1da177e4 2264 /* Determine NVRAM starting address. */
0107109e 2265 ha->nvram_size = sizeof(nvram_t);
1da177e4
LT		 2266 ha->nvram_base = 0;
2267 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
2268 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
2269 ha->nvram_base = 0x80;
2270
2271 /* Get NVRAM data and calculate checksum. */
e315cd28 2272 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
0107109e
AV		 2273 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
2274 chksum += *ptr++;
1da177e4 2275
7c3df132
SK		 2276 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
2277 "Contents of NVRAM.\n");
2278 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
2279 (uint8_t *)nv, ha->nvram_size);
1da177e4
LT		 2280
2281 /* Bad NVRAM data, set defaults parameters. */
2282 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
2283 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
2284 /* Reset NVRAM data. */
7c3df132 2285 ql_log(ql_log_warn, vha, 0x0064,
9e336520 2286 "Inconsistent NVRAM "
7c3df132
SK		 2287 "detected: checksum=0x%x id=%c version=0x%x.\n",
2288 chksum, nv->id[0], nv->nvram_version);
2289 ql_log(ql_log_warn, vha, 0x0065,
2290 "Falling back to "
2291 "functioning (yet invalid -- WWPN) defaults.\n");
4e08df3f
DM		 2292
2293 /*
2294 * Set default initialization control block.
2295 */
2296 memset(nv, 0, ha->nvram_size);
2297 nv->parameter_block_version = ICB_VERSION;
2298
2299 if (IS_QLA23XX(ha)) {
2300 nv->firmware_options[0] = BIT_2 | BIT_1;
2301 nv->firmware_options[1] = BIT_7 | BIT_5;
2302 nv->add_firmware_options[0] = BIT_5;
2303 nv->add_firmware_options[1] = BIT_5 | BIT_4;
2304 nv->frame_payload_size = __constant_cpu_to_le16(2048);
2305 nv->special_options[1] = BIT_7;
2306 } else if (IS_QLA2200(ha)) {
2307 nv->firmware_options[0] = BIT_2 | BIT_1;
2308 nv->firmware_options[1] = BIT_7 | BIT_5;
2309 nv->add_firmware_options[0] = BIT_5;
2310 nv->add_firmware_options[1] = BIT_5 | BIT_4;
2311 nv->frame_payload_size = __constant_cpu_to_le16(1024);
2312 } else if (IS_QLA2100(ha)) {
2313 nv->firmware_options[0] = BIT_3 | BIT_1;
2314 nv->firmware_options[1] = BIT_5;
2315 nv->frame_payload_size = __constant_cpu_to_le16(1024);
2316 }
2317
2318 nv->max_iocb_allocation = __constant_cpu_to_le16(256);
2319 nv->execution_throttle = __constant_cpu_to_le16(16);
2320 nv->retry_count = 8;
2321 nv->retry_delay = 1;
2322
2323 nv->port_name[0] = 33;
2324 nv->port_name[3] = 224;
2325 nv->port_name[4] = 139;
2326
e315cd28 2327 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 2328
2329 nv->login_timeout = 4;
2330
2331 /*
2332 * Set default host adapter parameters
2333 */
2334 nv->host_p[1] = BIT_2;
2335 nv->reset_delay = 5;
2336 nv->port_down_retry_count = 8;
2337 nv->max_luns_per_target = __constant_cpu_to_le16(8);
2338 nv->link_down_timeout = 60;
2339
2340 rval = 1;
1da177e4
LT		 2341 }
2342
2343#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
2344 /*
2345 * The SN2 does not provide BIOS emulation which means you can't change
2346 * potentially bogus BIOS settings. Force the use of default settings
2347 * for link rate and frame size. Hope that the rest of the settings
2348 * are valid.
2349 */
2350 if (ia64_platform_is("sn2")) {
2351 nv->frame_payload_size = __constant_cpu_to_le16(2048);
2352 if (IS_QLA23XX(ha))
2353 nv->special_options[1] = BIT_7;
2354 }
2355#endif
2356
2357 /* Reset Initialization control block */
0107109e 2358 memset(icb, 0, ha->init_cb_size);
1da177e4
LT		 2359
2360 /*
2361 * Setup driver NVRAM options.
2362 */
2363 nv->firmware_options[0] |= (BIT_6 | BIT_1);
2364 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
2365 nv->firmware_options[1] |= (BIT_5 | BIT_0);
2366 nv->firmware_options[1] &= ~BIT_4;
2367
2368 if (IS_QLA23XX(ha)) {
2369 nv->firmware_options[0] |= BIT_2;
2370 nv->firmware_options[0] &= ~BIT_3;
2d70c103 2371 nv->special_options[0] &= ~BIT_6;
0107109e 2372 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
1da177e4
LT		 2373
2374 if (IS_QLA2300(ha)) {
2375 if (ha->fb_rev == FPM_2310) {
2376 strcpy(ha->model_number, "QLA2310");
2377 } else {
2378 strcpy(ha->model_number, "QLA2300");
2379 }
2380 } else {
e315cd28 2381 qla2x00_set_model_info(vha, nv->model_number,
9bb9fcf2 2382 sizeof(nv->model_number), "QLA23xx");
1da177e4
LT		 2383 }
2384 } else if (IS_QLA2200(ha)) {
2385 nv->firmware_options[0] |= BIT_2;
2386 /*
2387 * 'Point-to-point preferred, else loop' is not a safe
2388 * connection mode setting.
2389 */
2390 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
2391 (BIT_5 | BIT_4)) {
2392 /* Force 'loop preferred, else point-to-point'. */
2393 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
2394 nv->add_firmware_options[0] |= BIT_5;
2395 }
2396 strcpy(ha->model_number, "QLA22xx");
2397 } else /*if (IS_QLA2100(ha))*/ {
2398 strcpy(ha->model_number, "QLA2100");
2399 }
2400
2401 /*
2402 * Copy over NVRAM RISC parameter block to initialization control block.
2403 */
2404 dptr1 = (uint8_t *)icb;
2405 dptr2 = (uint8_t *)&nv->parameter_block_version;
2406 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
2407 while (cnt--)
2408 *dptr1++ = *dptr2++;
2409
2410 /* Copy 2nd half. */
2411 dptr1 = (uint8_t *)icb->add_firmware_options;
2412 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
2413 while (cnt--)
2414 *dptr1++ = *dptr2++;
2415
5341e868
AV		 2416 /* Use alternate WWN? */
2417 if (nv->host_p[1] & BIT_7) {
2418 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
2419 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
2420 }
2421
1da177e4
LT		 2422 /* Prepare nodename */
2423 if ((icb->firmware_options[1] & BIT_6) == 0) {
2424 /*
2425 * Firmware will apply the following mask if the nodename was
2426 * not provided.
2427 */
2428 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
2429 icb->node_name[0] &= 0xF0;
2430 }
2431
2432 /*
2433 * Set host adapter parameters.
2434 */
3ce8866c
SK		 2435
2436 /*
2437 * BIT_7 in the host-parameters section allows for modification to
2438 * internal driver logging.
2439 */
0181944f 2440 if (nv->host_p[0] & BIT_7)
cfb0919c 2441 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1da177e4
LT		 2442 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
2443 /* Always load RISC code on non ISP2[12]00 chips. */
2444 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
2445 ha->flags.disable_risc_code_load = 0;
2446 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
2447 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
2448 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
06c22bd1 2449 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
d4c760c2 2450 ha->flags.disable_serdes = 0;
1da177e4
LT		 2451
2452 ha->operating_mode =
2453 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
2454
2455 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
2456 sizeof(ha->fw_seriallink_options));
2457
2458 /* save HBA serial number */
2459 ha->serial0 = icb->port_name[5];
2460 ha->serial1 = icb->port_name[6];
2461 ha->serial2 = icb->port_name[7];
e315cd28
AC		 2462 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
2463 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
1da177e4
LT		 2464
2465 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
2466
2467 ha->retry_count = nv->retry_count;
2468
2469 /* Set minimum login_timeout to 4 seconds. */
5b91490e 2470 if (nv->login_timeout != ql2xlogintimeout)
1da177e4
LT		 2471 nv->login_timeout = ql2xlogintimeout;
2472 if (nv->login_timeout < 4)
2473 nv->login_timeout = 4;
2474 ha->login_timeout = nv->login_timeout;
2475 icb->login_timeout = nv->login_timeout;
2476
00a537b8
AV		 2477 /* Set minimum RATOV to 100 tenths of a second. */
2478 ha->r_a_tov = 100;
1da177e4 2479
1da177e4
LT		 2480 ha->loop_reset_delay = nv->reset_delay;
2481
1da177e4
LT		 2482 /* Link Down Timeout = 0:
2483 *
2484 * When Port Down timer expires we will start returning
2485 * I/O's to OS with "DID_NO_CONNECT".
2486 *
2487 * Link Down Timeout != 0:
2488 *
2489 * The driver waits for the link to come up after link down
2490 * before returning I/Os to OS with "DID_NO_CONNECT".
fa2a1ce5 2491 */
1da177e4
LT		 2492 if (nv->link_down_timeout == 0) {
2493 ha->loop_down_abort_time =
354d6b21 2494 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
1da177e4
LT		 2495 } else {
2496 ha->link_down_timeout = nv->link_down_timeout;
2497 ha->loop_down_abort_time =
2498 (LOOP_DOWN_TIME - ha->link_down_timeout);
fa2a1ce5 2499 }
1da177e4 2500
1da177e4
LT		 2501 /*
2502 * Need enough time to try and get the port back.
2503 */
2504 ha->port_down_retry_count = nv->port_down_retry_count;
2505 if (qlport_down_retry)
2506 ha->port_down_retry_count = qlport_down_retry;
2507 /* Set login_retry_count */
2508 ha->login_retry_count = nv->retry_count;
2509 if (ha->port_down_retry_count == nv->port_down_retry_count &&
2510 ha->port_down_retry_count > 3)
2511 ha->login_retry_count = ha->port_down_retry_count;
2512 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
2513 ha->login_retry_count = ha->port_down_retry_count;
2514 if (ql2xloginretrycount)
2515 ha->login_retry_count = ql2xloginretrycount;
2516
1da177e4
LT		 2517 icb->lun_enables = __constant_cpu_to_le16(0);
2518 icb->command_resource_count = 0;
2519 icb->immediate_notify_resource_count = 0;
2520 icb->timeout = __constant_cpu_to_le16(0);
2521
2522 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
2523 /* Enable RIO */
2524 icb->firmware_options[0] &= ~BIT_3;
2525 icb->add_firmware_options[0] &=
2526 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
2527 icb->add_firmware_options[0] |= BIT_2;
2528 icb->response_accumulation_timer = 3;
2529 icb->interrupt_delay_timer = 5;
2530
e315cd28 2531 vha->flags.process_response_queue = 1;
1da177e4 2532 } else {
4fdfefe5 2533 /* Enable ZIO. */
e315cd28 2534 if (!vha->flags.init_done) {
4fdfefe5
AV		 2535 ha->zio_mode = icb->add_firmware_options[0] &
2536 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
2537 ha->zio_timer = icb->interrupt_delay_timer ?
2538 icb->interrupt_delay_timer: 2;
2539 }
1da177e4
LT		 2540 icb->add_firmware_options[0] &=
2541 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
e315cd28 2542 vha->flags.process_response_queue = 0;
4fdfefe5 2543 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d 2544 ha->zio_mode = QLA_ZIO_MODE_6;
2545
7c3df132 2546 ql_log(ql_log_info, vha, 0x0068,
4fdfefe5
AV		 2547 "ZIO mode %d enabled; timer delay (%d us).\n",
2548 ha->zio_mode, ha->zio_timer * 100);
1da177e4 2549
4fdfefe5
AV		 2550 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
2551 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
e315cd28 2552 vha->flags.process_response_queue = 1;
1da177e4
LT		 2553 }
2554 }
2555
4e08df3f 2556 if (rval) {
7c3df132
SK		 2557 ql_log(ql_log_warn, vha, 0x0069,
2558 "NVRAM configuration failed.\n");
4e08df3f
DM		 2559 }
2560 return (rval);
1da177e4
LT		 2561}
2562
19a7b4ae
JSEC		 2563static void
2564qla2x00_rport_del(void *data)
2565{
2566 fc_port_t *fcport = data;
d97994dc 2567 struct fc_rport *rport;
2d70c103 2568 scsi_qla_host_t *vha = fcport->vha;
044d78e1 2569 unsigned long flags;
d97994dc 2570
044d78e1 2571 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
ac280b67 2572 rport = fcport->drport ? fcport->drport: fcport->rport;
d97994dc 2573 fcport->drport = NULL;
044d78e1 2574 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
2d70c103 2575 if (rport) {
d97994dc 2576 fc_remote_port_delete(rport);
2d70c103
NB		 2577 /*
2578 * Release the target mode FC NEXUS in qla_target.c code
2579 * if target mod is enabled.
2580 */
2581 qlt_fc_port_deleted(vha, fcport);
2582 }
19a7b4ae
JSEC		 2583}
2584
1da177e4
LT		 2585/**
2586 * qla2x00_alloc_fcport() - Allocate a generic fcport.
2587 * @ha: HA context
2588 * @flags: allocation flags
2589 *
2590 * Returns a pointer to the allocated fcport, or NULL, if none available.
2591 */
9a069e19 2592fc_port_t *
e315cd28 2593qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
1da177e4
LT		 2594{
2595 fc_port_t *fcport;
2596
bbfbbbc1
MK		 2597 fcport = kzalloc(sizeof(fc_port_t), flags);
2598 if (!fcport)
2599 return NULL;
1da177e4
LT		 2600
2601 /* Setup fcport template structure. */
e315cd28 2602 fcport->vha = vha;
1da177e4
LT		 2603 fcport->port_type = FCT_UNKNOWN;
2604 fcport->loop_id = FC_NO_LOOP_ID;
ec426e10 2605 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
ad3e0eda 2606 fcport->supported_classes = FC_COS_UNSPECIFIED;
c0822b63 2607 fcport->scan_state = QLA_FCPORT_SCAN_NONE;
1da177e4 2608
bbfbbbc1 2609 return fcport;
1da177e4
LT		 2610}
2611
2612/*
2613 * qla2x00_configure_loop
2614 * Updates Fibre Channel Device Database with what is actually on loop.
2615 *
2616 * Input:
2617 * ha = adapter block pointer.
2618 *
2619 * Returns:
2620 * 0 = success.
2621 * 1 = error.
2622 * 2 = database was full and device was not configured.
2623 */
2624static int
e315cd28 2625qla2x00_configure_loop(scsi_qla_host_t *vha)
1da177e4
LT		 2626{
2627 int rval;
2628 unsigned long flags, save_flags;
e315cd28 2629 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2630 rval = QLA_SUCCESS;
2631
2632 /* Get Initiator ID */
e315cd28
AC		 2633 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
2634 rval = qla2x00_configure_hba(vha);
1da177e4 2635 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2636 ql_dbg(ql_dbg_disc, vha, 0x2013,
2637 "Unable to configure HBA.\n");
1da177e4
LT		 2638 return (rval);
2639 }
2640 }
2641
e315cd28 2642 save_flags = flags = vha->dpc_flags;
7c3df132
SK		 2643 ql_dbg(ql_dbg_disc, vha, 0x2014,
2644 "Configure loop -- dpc flags = 0x%lx.\n", flags);
1da177e4
LT		 2645
2646 /*
2647 * If we have both an RSCN and PORT UPDATE pending then handle them
2648 * both at the same time.
2649 */
e315cd28
AC		 2650 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2651 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
1da177e4 2652
3064ff39
MH		 2653 qla2x00_get_data_rate(vha);
2654
1da177e4
LT		 2655 /* Determine what we need to do */
2656 if (ha->current_topology == ISP_CFG_FL &&
2657 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2658
1da177e4
LT		 2659 set_bit(RSCN_UPDATE, &flags);
2660
2661 } else if (ha->current_topology == ISP_CFG_F &&
2662 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2663
1da177e4
LT		 2664 set_bit(RSCN_UPDATE, &flags);
2665 clear_bit(LOCAL_LOOP_UPDATE, &flags);
21333b48
AV		 2666
2667 } else if (ha->current_topology == ISP_CFG_N) {
2668 clear_bit(RSCN_UPDATE, &flags);
1da177e4 2669
e315cd28 2670 } else if (!vha->flags.online ||
1da177e4
LT		 2671 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
2672
1da177e4
LT		 2673 set_bit(RSCN_UPDATE, &flags);
2674 set_bit(LOCAL_LOOP_UPDATE, &flags);
2675 }
2676
2677 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
7c3df132
SK		 2678 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
2679 ql_dbg(ql_dbg_disc, vha, 0x2015,
2680 "Loop resync needed, failing.\n");
1da177e4 2681 rval = QLA_FUNCTION_FAILED;
642ef983 2682 } else
e315cd28 2683 rval = qla2x00_configure_local_loop(vha);
1da177e4
LT		 2684 }
2685
2686 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
7c3df132
SK		 2687 if (LOOP_TRANSITION(vha)) {
2688 ql_dbg(ql_dbg_disc, vha, 0x201e,
2689 "Needs RSCN update and loop transition.\n");
1da177e4 2690 rval = QLA_FUNCTION_FAILED;
7c3df132 2691 }
e315cd28
AC		 2692 else
2693 rval = qla2x00_configure_fabric(vha);
1da177e4
LT		 2694 }
2695
2696 if (rval == QLA_SUCCESS) {
e315cd28
AC		 2697 if (atomic_read(&vha->loop_down_timer) ||
2698 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4
LT		 2699 rval = QLA_FUNCTION_FAILED;
2700 } else {
e315cd28 2701 atomic_set(&vha->loop_state, LOOP_READY);
7c3df132
SK		 2702 ql_dbg(ql_dbg_disc, vha, 0x2069,
2703 "LOOP READY.\n");
1da177e4
LT		 2704 }
2705 }
2706
2707 if (rval) {
7c3df132
SK		 2708 ql_dbg(ql_dbg_disc, vha, 0x206a,
2709 "%s *** FAILED ***.\n", __func__);
1da177e4 2710 } else {
7c3df132
SK		 2711 ql_dbg(ql_dbg_disc, vha, 0x206b,
2712 "%s: exiting normally.\n", __func__);
1da177e4
LT		 2713 }
2714
cc3ef7bc 2715 /* Restore state if a resync event occurred during processing */
e315cd28 2716 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4 2717 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
e315cd28 2718 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
f4658b6c 2719 if (test_bit(RSCN_UPDATE, &save_flags)) {
e315cd28 2720 set_bit(RSCN_UPDATE, &vha->dpc_flags);
f4658b6c 2721 }
1da177e4
LT		 2722 }
2723
2724 return (rval);
2725}
2726
2727
2728
2729/*
2730 * qla2x00_configure_local_loop
2731 * Updates Fibre Channel Device Database with local loop devices.
2732 *
2733 * Input:
2734 * ha = adapter block pointer.
2735 *
2736 * Returns:
2737 * 0 = success.
2738 */
2739static int
e315cd28 2740qla2x00_configure_local_loop(scsi_qla_host_t *vha)
1da177e4
LT		 2741{
2742 int rval, rval2;
2743 int found_devs;
2744 int found;
2745 fc_port_t *fcport, *new_fcport;
2746
2747 uint16_t index;
2748 uint16_t entries;
2749 char *id_iter;
2750 uint16_t loop_id;
2751 uint8_t domain, area, al_pa;
e315cd28 2752 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2753
2754 found_devs = 0;
2755 new_fcport = NULL;
642ef983 2756 entries = MAX_FIBRE_DEVICES_LOOP;
1da177e4 2757
7c3df132
SK		 2758 ql_dbg(ql_dbg_disc, vha, 0x2016,
2759 "Getting FCAL position map.\n");
2760 if (ql2xextended_error_logging & ql_dbg_disc)
2761 qla2x00_get_fcal_position_map(vha, NULL);
1da177e4
LT		 2762
2763 /* Get list of logged in devices. */
642ef983 2764 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
e315cd28 2765 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
1da177e4
LT		 2766 &entries);
2767 if (rval != QLA_SUCCESS)
2768 goto cleanup_allocation;
2769
7c3df132
SK		 2770 ql_dbg(ql_dbg_disc, vha, 0x2017,
2771 "Entries in ID list (%d).\n", entries);
2772 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
2773 (uint8_t *)ha->gid_list,
2774 entries * sizeof(struct gid_list_info));
1da177e4
LT		 2775
2776 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 2777 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 2778 if (new_fcport == NULL) {
7c3df132
SK		 2779 ql_log(ql_log_warn, vha, 0x2018,
2780 "Memory allocation failed for fcport.\n");
1da177e4
LT		 2781 rval = QLA_MEMORY_ALLOC_FAILED;
2782 goto cleanup_allocation;
2783 }
2784 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
2785
2786 /*
2787 * Mark local devices that were present with FCF_DEVICE_LOST for now.
2788 */
e315cd28 2789 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 2790 if (atomic_read(&fcport->state) == FCS_ONLINE &&
2791 fcport->port_type != FCT_BROADCAST &&
2792 (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
2793
7c3df132
SK		 2794 ql_dbg(ql_dbg_disc, vha, 0x2019,
2795 "Marking port lost loop_id=0x%04x.\n",
2796 fcport->loop_id);
1da177e4 2797
ec426e10 2798 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 2799 }
2800 }
2801
2802 /* Add devices to port list. */
2803 id_iter = (char *)ha->gid_list;
2804 for (index = 0; index < entries; index++) {
2805 domain = ((struct gid_list_info *)id_iter)->domain;
2806 area = ((struct gid_list_info *)id_iter)->area;
2807 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
abbd8870 2808 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1da177e4
LT		 2809 loop_id = (uint16_t)
2810 ((struct gid_list_info *)id_iter)->loop_id_2100;
abbd8870 2811 else
1da177e4
LT		 2812 loop_id = le16_to_cpu(
2813 ((struct gid_list_info *)id_iter)->loop_id);
abbd8870 2814 id_iter += ha->gid_list_info_size;
1da177e4
LT		 2815
2816 /* Bypass reserved domain fields. */
2817 if ((domain & 0xf0) == 0xf0)
2818 continue;
2819
2820 /* Bypass if not same domain and area of adapter. */
f7d289f6 2821 if (area && domain &&
e315cd28 2822 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
1da177e4
LT		 2823 continue;
2824
2825 /* Bypass invalid local loop ID. */
2826 if (loop_id > LAST_LOCAL_LOOP_ID)
2827 continue;
2828
370d550e
AE		 2829 memset(new_fcport, 0, sizeof(fc_port_t));
2830
1da177e4
LT		 2831 /* Fill in member data. */
2832 new_fcport->d_id.b.domain = domain;
2833 new_fcport->d_id.b.area = area;
2834 new_fcport->d_id.b.al_pa = al_pa;
2835 new_fcport->loop_id = loop_id;
e315cd28 2836 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
1da177e4 2837 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 2838 ql_dbg(ql_dbg_disc, vha, 0x201a,
2839 "Failed to retrieve fcport information "
2840 "-- get_port_database=%x, loop_id=0x%04x.\n",
2841 rval2, new_fcport->loop_id);
2842 ql_dbg(ql_dbg_disc, vha, 0x201b,
2843 "Scheduling resync.\n");
e315cd28 2844 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 2845 continue;
2846 }
2847
2848 /* Check for matching device in port list. */
2849 found = 0;
2850 fcport = NULL;
e315cd28 2851 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 2852 if (memcmp(new_fcport->port_name, fcport->port_name,
2853 WWN_SIZE))
2854 continue;
2855
ddb9b126 2856 fcport->flags &= ~FCF_FABRIC_DEVICE;
1da177e4
LT		 2857 fcport->loop_id = new_fcport->loop_id;
2858 fcport->port_type = new_fcport->port_type;
2859 fcport->d_id.b24 = new_fcport->d_id.b24;
2860 memcpy(fcport->node_name, new_fcport->node_name,
2861 WWN_SIZE);
2862
2863 found++;
2864 break;
2865 }
2866
2867 if (!found) {
2868 /* New device, add to fcports list. */
e315cd28 2869 list_add_tail(&new_fcport->list, &vha->vp_fcports);
1da177e4
LT		 2870
2871 /* Allocate a new replacement fcport. */
2872 fcport = new_fcport;
e315cd28 2873 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 2874 if (new_fcport == NULL) {
7c3df132
SK		 2875 ql_log(ql_log_warn, vha, 0x201c,
2876 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 2877 rval = QLA_MEMORY_ALLOC_FAILED;
2878 goto cleanup_allocation;
2879 }
2880 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
2881 }
2882
d8b45213 2883 /* Base iIDMA settings on HBA port speed. */
a3cbdfad 2884 fcport->fp_speed = ha->link_data_rate;
d8b45213 2885
e315cd28 2886 qla2x00_update_fcport(vha, fcport);
1da177e4
LT		 2887
2888 found_devs++;
2889 }
2890
2891cleanup_allocation:
c9475cb0 2892 kfree(new_fcport);
1da177e4
LT		 2893
2894 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2895 ql_dbg(ql_dbg_disc, vha, 0x201d,
2896 "Configure local loop error exit: rval=%x.\n", rval);
1da177e4
LT		 2897 }
2898
1da177e4
LT		 2899 return (rval);
2900}
2901
d8b45213 2902static void
e315cd28 2903qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
d8b45213 2904{
9f8fddee 2905 char *link_speed;
d8b45213 2906 int rval;
1bb39548 2907 uint16_t mb[4];
e315cd28 2908 struct qla_hw_data *ha = vha->hw;
d8b45213 2909
c76f2c01 2910 if (!IS_IIDMA_CAPABLE(ha))
d8b45213
AV		 2911 return;
2912
c9afb9a2
GM		 2913 if (atomic_read(&fcport->state) != FCS_ONLINE)
2914 return;
2915
39bd9622
AV		 2916 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
2917 fcport->fp_speed > ha->link_data_rate)
d8b45213
AV		 2918 return;
2919
e315cd28 2920 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
a3cbdfad 2921 mb);
d8b45213 2922 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2923 ql_dbg(ql_dbg_disc, vha, 0x2004,
2924 "Unable to adjust iIDMA "
2925 "%02x%02x%02x%02x%02x%02x%02x%02x -- %04x %x %04x "
2926 "%04x.\n", fcport->port_name[0], fcport->port_name[1],
d8b45213
AV		 2927 fcport->port_name[2], fcport->port_name[3],
2928 fcport->port_name[4], fcport->port_name[5],
2929 fcport->port_name[6], fcport->port_name[7], rval,
7c3df132 2930 fcport->fp_speed, mb[0], mb[1]);
d8b45213 2931 } else {
daae62a3 2932 link_speed = qla2x00_get_link_speed_str(ha);
7c3df132
SK		 2933 ql_dbg(ql_dbg_disc, vha, 0x2005,
2934 "iIDMA adjusted to %s GB/s "
2935 "on %02x%02x%02x%02x%02x%02x%02x%02x.\n", link_speed,
2936 fcport->port_name[0], fcport->port_name[1],
2937 fcport->port_name[2], fcport->port_name[3],
2938 fcport->port_name[4], fcport->port_name[5],
2939 fcport->port_name[6], fcport->port_name[7]);
d8b45213
AV		 2940 }
2941}
2942
23be331d 2943static void
e315cd28 2944qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
8482e118 2945{
2946 struct fc_rport_identifiers rport_ids;
bdf79621 2947 struct fc_rport *rport;
044d78e1 2948 unsigned long flags;
8482e118 2949
ac280b67 2950 qla2x00_rport_del(fcport);
8482e118 2951
f8b02a85
AV		 2952 rport_ids.node_name = wwn_to_u64(fcport->node_name);
2953 rport_ids.port_name = wwn_to_u64(fcport->port_name);
8482e118 2954 rport_ids.port_id = fcport->d_id.b.domain << 16 |
2955 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
77d74143 2956 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
e315cd28 2957 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
77d74143 2958 if (!rport) {
7c3df132
SK		 2959 ql_log(ql_log_warn, vha, 0x2006,
2960 "Unable to allocate fc remote port.\n");
77d74143
AV		 2961 return;
2962 }
2d70c103
NB		 2963 /*
2964 * Create target mode FC NEXUS in qla_target.c if target mode is
2965 * enabled..
2966 */
2967 qlt_fc_port_added(vha, fcport);
2968
044d78e1 2969 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
19a7b4ae 2970 *((fc_port_t **)rport->dd_data) = fcport;
044d78e1 2971 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
d97994dc 2972
ad3e0eda 2973 rport->supported_classes = fcport->supported_classes;
77d74143 2974
8482e118 2975 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
2976 if (fcport->port_type == FCT_INITIATOR)
2977 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
2978 if (fcport->port_type == FCT_TARGET)
2979 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
77d74143 2980 fc_remote_port_rolechg(rport, rport_ids.roles);
1da177e4
LT		 2981}
2982
23be331d
AB		 2983/*
2984 * qla2x00_update_fcport
2985 * Updates device on list.
2986 *
2987 * Input:
2988 * ha = adapter block pointer.
2989 * fcport = port structure pointer.
2990 *
2991 * Return:
2992 * 0 - Success
2993 * BIT_0 - error
2994 *
2995 * Context:
2996 * Kernel context.
2997 */
2998void
e315cd28 2999qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
23be331d 3000{
e315cd28 3001 fcport->vha = vha;
23be331d 3002 fcport->login_retry = 0;
5ff1d584 3003 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
23be331d 3004
e315cd28 3005 qla2x00_iidma_fcport(vha, fcport);
21090cbe 3006 qla24xx_update_fcport_fcp_prio(vha, fcport);
e315cd28 3007 qla2x00_reg_remote_port(vha, fcport);
ec426e10 3008 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
23be331d
AB		 3009}
3010
1da177e4
LT		 3011/*
3012 * qla2x00_configure_fabric
3013 * Setup SNS devices with loop ID's.
3014 *
3015 * Input:
3016 * ha = adapter block pointer.
3017 *
3018 * Returns:
3019 * 0 = success.
3020 * BIT_0 = error
3021 */
3022static int
e315cd28 3023qla2x00_configure_fabric(scsi_qla_host_t *vha)
1da177e4 3024{
b3b02e6e 3025 int rval;
4dc77c36 3026 fc_port_t *fcport;
1da177e4
LT		 3027 uint16_t next_loopid;
3028 uint16_t mb[MAILBOX_REGISTER_COUNT];
0107109e 3029 uint16_t loop_id;
1da177e4 3030 LIST_HEAD(new_fcports);
e315cd28
AC		 3031 struct qla_hw_data *ha = vha->hw;
3032 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3033
3034 /* If FL port exists, then SNS is present */
e428924c 3035 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3036 loop_id = NPH_F_PORT;
3037 else
3038 loop_id = SNS_FL_PORT;
e315cd28 3039 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
1da177e4 3040 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3041 ql_dbg(ql_dbg_disc, vha, 0x201f,
3042 "MBX_GET_PORT_NAME failed, No FL Port.\n");
1da177e4 3043
e315cd28 3044 vha->device_flags &= ~SWITCH_FOUND;
1da177e4
LT		 3045 return (QLA_SUCCESS);
3046 }
e315cd28 3047 vha->device_flags |= SWITCH_FOUND;
1da177e4 3048
1da177e4 3049 do {
cca5335c
AV		 3050 /* FDMI support. */
3051 if (ql2xfdmienable &&
e315cd28
AC		 3052 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
3053 qla2x00_fdmi_register(vha);
cca5335c 3054
1da177e4 3055 /* Ensure we are logged into the SNS. */
e428924c 3056 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3057 loop_id = NPH_SNS;
3058 else
3059 loop_id = SIMPLE_NAME_SERVER;
0b91d116
CD		 3060 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
3061 0xfc, mb, BIT_1|BIT_0);
3062 if (rval != QLA_SUCCESS) {
3063 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
4dc77c36 3064 break;
0b91d116 3065 }
1da177e4 3066 if (mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 3067 ql_dbg(ql_dbg_disc, vha, 0x2042,
3068 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
3069 "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
3070 mb[2], mb[6], mb[7]);
1da177e4
LT		 3071 return (QLA_SUCCESS);
3072 }
3073
e315cd28
AC		 3074 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
3075 if (qla2x00_rft_id(vha)) {
1da177e4 3076 /* EMPTY */
7c3df132
SK		 3077 ql_dbg(ql_dbg_disc, vha, 0x2045,
3078 "Register FC-4 TYPE failed.\n");
1da177e4 3079 }
e315cd28 3080 if (qla2x00_rff_id(vha)) {
1da177e4 3081 /* EMPTY */
7c3df132
SK		 3082 ql_dbg(ql_dbg_disc, vha, 0x2049,
3083 "Register FC-4 Features failed.\n");
1da177e4 3084 }
e315cd28 3085 if (qla2x00_rnn_id(vha)) {
1da177e4 3086 /* EMPTY */
7c3df132
SK		 3087 ql_dbg(ql_dbg_disc, vha, 0x204f,
3088 "Register Node Name failed.\n");
e315cd28 3089 } else if (qla2x00_rsnn_nn(vha)) {
1da177e4 3090 /* EMPTY */
7c3df132
SK		 3091 ql_dbg(ql_dbg_disc, vha, 0x2053,
3092 "Register Symobilic Node Name failed.\n");
1da177e4
LT		 3093 }
3094 }
3095
e315cd28 3096 rval = qla2x00_find_all_fabric_devs(vha, &new_fcports);
1da177e4
LT		 3097 if (rval != QLA_SUCCESS)
3098 break;
3099
4dc77c36
JC		 3100 /* Add new ports to existing port list */
3101 list_splice_tail_init(&new_fcports, &vha->vp_fcports);
3102
3103 /* Starting free loop ID. */
3104 next_loopid = ha->min_external_loopid;
3105
e315cd28
AC		 3106 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3107 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1da177e4
LT		 3108 break;
3109
3110 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
3111 continue;
3112
4dc77c36 3113 /* Logout lost/gone fabric devices (non-FCP2) */
c0822b63 3114 if (fcport->scan_state != QLA_FCPORT_SCAN_FOUND &&
b3b02e6e 3115 atomic_read(&fcport->state) == FCS_ONLINE) {
e315cd28 3116 qla2x00_mark_device_lost(vha, fcport,
d97994dc 3117 ql2xplogiabsentdevice, 0);
1da177e4 3118 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3119 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
1da177e4
LT		 3120 fcport->port_type != FCT_INITIATOR &&
3121 fcport->port_type != FCT_BROADCAST) {
e315cd28 3122 ha->isp_ops->fabric_logout(vha,
1c7c6357
AV		 3123 fcport->loop_id,
3124 fcport->d_id.b.domain,
3125 fcport->d_id.b.area,
3126 fcport->d_id.b.al_pa);
1da177e4 3127 }
c0822b63 3128 continue;
1da177e4 3129 }
c0822b63 3130 fcport->scan_state = QLA_FCPORT_SCAN_NONE;
1da177e4 3131
4dc77c36
JC		 3132 /* Login fabric devices that need a login */
3133 if ((fcport->flags & FCF_LOGIN_NEEDED) != 0 &&
3134 atomic_read(&vha->loop_down_timer) == 0) {
3135 if (fcport->loop_id == FC_NO_LOOP_ID) {
3136 fcport->loop_id = next_loopid;
3137 rval = qla2x00_find_new_loop_id(
3138 base_vha, fcport);
3139 if (rval != QLA_SUCCESS) {
3140 /* Ran out of IDs to use */
3141 continue;
3142 }
1da177e4
LT		 3143 }
3144 }
1da177e4 3145
bdf79621 3146 /* Login and update database */
e315cd28 3147 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
1da177e4
LT		 3148 }
3149 } while (0);
3150
1da177e4 3151 if (rval) {
7c3df132
SK		 3152 ql_dbg(ql_dbg_disc, vha, 0x2068,
3153 "Configure fabric error exit rval=%d.\n", rval);
1da177e4
LT		 3154 }
3155
3156 return (rval);
3157}
3158
1da177e4
LT		 3159/*
3160 * qla2x00_find_all_fabric_devs
3161 *
3162 * Input:
3163 * ha = adapter block pointer.
3164 * dev = database device entry pointer.
3165 *
3166 * Returns:
3167 * 0 = success.
3168 *
3169 * Context:
3170 * Kernel context.
3171 */
3172static int
e315cd28
AC		 3173qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
3174 struct list_head *new_fcports)
1da177e4
LT		 3175{
3176 int rval;
3177 uint16_t loop_id;
3178 fc_port_t *fcport, *new_fcport, *fcptemp;
3179 int found;
3180
3181 sw_info_t *swl;
3182 int swl_idx;
3183 int first_dev, last_dev;
1516ef44 3184 port_id_t wrap = {}, nxt_d_id;
e315cd28
AC		 3185 struct qla_hw_data *ha = vha->hw;
3186 struct scsi_qla_host *vp, *base_vha = pci_get_drvdata(ha->pdev);
ee546b6e 3187 struct scsi_qla_host *tvp;
1da177e4
LT		 3188
3189 rval = QLA_SUCCESS;
3190
3191 /* Try GID_PT to get device list, else GAN. */
7a67735b 3192 if (!ha->swl)
642ef983 3193 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
7a67735b
AV		 3194 GFP_KERNEL);
3195 swl = ha->swl;
bbfbbbc1 3196 if (!swl) {
1da177e4 3197 /*EMPTY*/
7c3df132
SK		 3198 ql_dbg(ql_dbg_disc, vha, 0x2054,
3199 "GID_PT allocations failed, fallback on GA_NXT.\n");
1da177e4 3200 } else {
642ef983 3201 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
e315cd28 3202 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
1da177e4 3203 swl = NULL;
e315cd28 3204 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3205 swl = NULL;
e315cd28 3206 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3207 swl = NULL;
e5896bd5 3208 } else if (ql2xiidmaenable &&
e315cd28
AC		 3209 qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) {
3210 qla2x00_gpsc(vha, swl);
1da177e4 3211 }
e8c72ba5
CD		 3212
3213 /* If other queries succeeded probe for FC-4 type */
3214 if (swl)
3215 qla2x00_gff_id(vha, swl);
1da177e4
LT		 3216 }
3217 swl_idx = 0;
3218
3219 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 3220 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3221 if (new_fcport == NULL) {
7c3df132
SK		 3222 ql_log(ql_log_warn, vha, 0x205e,
3223 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3224 return (QLA_MEMORY_ALLOC_FAILED);
3225 }
3226 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
1da177e4
LT		 3227 /* Set start port ID scan at adapter ID. */
3228 first_dev = 1;
3229 last_dev = 0;
3230
3231 /* Starting free loop ID. */
e315cd28
AC		 3232 loop_id = ha->min_external_loopid;
3233 for (; loop_id <= ha->max_loop_id; loop_id++) {
3234 if (qla2x00_is_reserved_id(vha, loop_id))
1da177e4
LT		 3235 continue;
3236
3a6478df
GM		 3237 if (ha->current_topology == ISP_CFG_FL &&
3238 (atomic_read(&vha->loop_down_timer) ||
3239 LOOP_TRANSITION(vha))) {
bb2d52b2
AV		 3240 atomic_set(&vha->loop_down_timer, 0);
3241 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
3242 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1da177e4 3243 break;
bb2d52b2 3244 }
1da177e4
LT		 3245
3246 if (swl != NULL) {
3247 if (last_dev) {
3248 wrap.b24 = new_fcport->d_id.b24;
3249 } else {
3250 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
3251 memcpy(new_fcport->node_name,
3252 swl[swl_idx].node_name, WWN_SIZE);
3253 memcpy(new_fcport->port_name,
3254 swl[swl_idx].port_name, WWN_SIZE);
d8b45213
AV		 3255 memcpy(new_fcport->fabric_port_name,
3256 swl[swl_idx].fabric_port_name, WWN_SIZE);
3257 new_fcport->fp_speed = swl[swl_idx].fp_speed;
e8c72ba5 3258 new_fcport->fc4_type = swl[swl_idx].fc4_type;
1da177e4
LT		 3259
3260 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
3261 last_dev = 1;
3262 }
3263 swl_idx++;
3264 }
3265 } else {
3266 /* Send GA_NXT to the switch */
e315cd28 3267 rval = qla2x00_ga_nxt(vha, new_fcport);
1da177e4 3268 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3269 ql_log(ql_log_warn, vha, 0x2064,
3270 "SNS scan failed -- assuming "
3271 "zero-entry result.\n");
1da177e4
LT		 3272 list_for_each_entry_safe(fcport, fcptemp,
3273 new_fcports, list) {
3274 list_del(&fcport->list);
3275 kfree(fcport);
3276 }
3277 rval = QLA_SUCCESS;
3278 break;
3279 }
3280 }
3281
3282 /* If wrap on switch device list, exit. */
3283 if (first_dev) {
3284 wrap.b24 = new_fcport->d_id.b24;
3285 first_dev = 0;
3286 } else if (new_fcport->d_id.b24 == wrap.b24) {
7c3df132
SK		 3287 ql_dbg(ql_dbg_disc, vha, 0x2065,
3288 "Device wrap (%02x%02x%02x).\n",
3289 new_fcport->d_id.b.domain,
3290 new_fcport->d_id.b.area,
3291 new_fcport->d_id.b.al_pa);
1da177e4
LT		 3292 break;
3293 }
3294
2c3dfe3f 3295 /* Bypass if same physical adapter. */
e315cd28 3296 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
1da177e4
LT		 3297 continue;
3298
2c3dfe3f 3299 /* Bypass virtual ports of the same host. */
e315cd28
AC		 3300 found = 0;
3301 if (ha->num_vhosts) {
feafb7b1
AE		 3302 unsigned long flags;
3303
3304 spin_lock_irqsave(&ha->vport_slock, flags);
ee546b6e 3305 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
e315cd28
AC		 3306 if (new_fcport->d_id.b24 == vp->d_id.b24) {
3307 found = 1;
2c3dfe3f 3308 break;
e315cd28 3309 }
2c3dfe3f 3310 }
feafb7b1
AE		 3311 spin_unlock_irqrestore(&ha->vport_slock, flags);
3312
e315cd28 3313 if (found)
2c3dfe3f
SJ		 3314 continue;
3315 }
3316
f7d289f6
AV		 3317 /* Bypass if same domain and area of adapter. */
3318 if (((new_fcport->d_id.b24 & 0xffff00) ==
e315cd28 3319 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
f7d289f6
AV		 3320 ISP_CFG_FL)
3321 continue;
3322
1da177e4
LT		 3323 /* Bypass reserved domain fields. */
3324 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
3325 continue;
3326
e8c72ba5 3327 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
4da26e16
CD		 3328 if (ql2xgffidenable &&
3329 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
3330 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
e8c72ba5
CD		 3331 continue;
3332
1da177e4
LT		 3333 /* Locate matching device in database. */
3334 found = 0;
e315cd28 3335 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3336 if (memcmp(new_fcport->port_name, fcport->port_name,
3337 WWN_SIZE))
3338 continue;
3339
c0822b63 3340 fcport->scan_state = QLA_FCPORT_SCAN_FOUND;
b3b02e6e 3341
1da177e4
LT		 3342 found++;
3343
d8b45213
AV		 3344 /* Update port state. */
3345 memcpy(fcport->fabric_port_name,
3346 new_fcport->fabric_port_name, WWN_SIZE);
3347 fcport->fp_speed = new_fcport->fp_speed;
3348
1da177e4
LT		 3349 /*
3350 * If address the same and state FCS_ONLINE, nothing
3351 * changed.
3352 */
3353 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
3354 atomic_read(&fcport->state) == FCS_ONLINE) {
3355 break;
3356 }
3357
3358 /*
3359 * If device was not a fabric device before.
3360 */
3361 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3362 fcport->d_id.b24 = new_fcport->d_id.b24;
5f16b331 3363 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3364 fcport->flags |= (FCF_FABRIC_DEVICE |
3365 FCF_LOGIN_NEEDED);
1da177e4
LT		 3366 break;
3367 }
3368
3369 /*
3370 * Port ID changed or device was marked to be updated;
3371 * Log it out if still logged in and mark it for
3372 * relogin later.
3373 */
3374 fcport->d_id.b24 = new_fcport->d_id.b24;
3375 fcport->flags |= FCF_LOGIN_NEEDED;
3376 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3377 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
0eba25df 3378 (fcport->flags & FCF_ASYNC_SENT) == 0 &&
1da177e4
LT		 3379 fcport->port_type != FCT_INITIATOR &&
3380 fcport->port_type != FCT_BROADCAST) {
e315cd28 3381 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3382 fcport->d_id.b.domain, fcport->d_id.b.area,
3383 fcport->d_id.b.al_pa);
5f16b331 3384 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3385 }
3386
3387 break;
3388 }
3389
3390 if (found)
3391 continue;
1da177e4
LT		 3392 /* If device was not in our fcports list, then add it. */
3393 list_add_tail(&new_fcport->list, new_fcports);
3394
3395 /* Allocate a new replacement fcport. */
3396 nxt_d_id.b24 = new_fcport->d_id.b24;
e315cd28 3397 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3398 if (new_fcport == NULL) {
7c3df132
SK		 3399 ql_log(ql_log_warn, vha, 0x2066,
3400 "Memory allocation failed for fcport.\n");
1da177e4
LT		 3401 return (QLA_MEMORY_ALLOC_FAILED);
3402 }
3403 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
3404 new_fcport->d_id.b24 = nxt_d_id.b24;
3405 }
3406
c9475cb0 3407 kfree(new_fcport);
1da177e4 3408
1da177e4
LT		 3409 return (rval);
3410}
3411
3412/*
3413 * qla2x00_find_new_loop_id
3414 * Scan through our port list and find a new usable loop ID.
3415 *
3416 * Input:
3417 * ha: adapter state pointer.
3418 * dev: port structure pointer.
3419 *
3420 * Returns:
3421 * qla2x00 local function return status code.
3422 *
3423 * Context:
3424 * Kernel context.
3425 */
03bcfb57 3426int
e315cd28 3427qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
1da177e4
LT		 3428{
3429 int rval;
e315cd28 3430 struct qla_hw_data *ha = vha->hw;
feafb7b1 3431 unsigned long flags = 0;
1da177e4
LT		 3432
3433 rval = QLA_SUCCESS;
3434
5f16b331 3435 spin_lock_irqsave(&ha->vport_slock, flags);
1da177e4 3436
5f16b331
CD		 3437 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
3438 LOOPID_MAP_SIZE);
3439 if (dev->loop_id >= LOOPID_MAP_SIZE ||
3440 qla2x00_is_reserved_id(vha, dev->loop_id)) {
3441 dev->loop_id = FC_NO_LOOP_ID;
3442 rval = QLA_FUNCTION_FAILED;
3443 } else
3444 set_bit(dev->loop_id, ha->loop_id_map);
1da177e4 3445
5f16b331 3446 spin_unlock_irqrestore(&ha->vport_slock, flags);
1da177e4 3447
5f16b331
CD		 3448 if (rval == QLA_SUCCESS)
3449 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
3450 "Assigning new loopid=%x, portid=%x.\n",
3451 dev->loop_id, dev->d_id.b24);
3452 else
3453 ql_log(ql_log_warn, dev->vha, 0x2087,
3454 "No loop_id's available, portid=%x.\n",
3455 dev->d_id.b24);
1da177e4
LT		 3456
3457 return (rval);
3458}
3459
1da177e4
LT		 3460/*
3461 * qla2x00_fabric_dev_login
3462 * Login fabric target device and update FC port database.
3463 *
3464 * Input:
3465 * ha: adapter state pointer.
3466 * fcport: port structure list pointer.
3467 * next_loopid: contains value of a new loop ID that can be used
3468 * by the next login attempt.
3469 *
3470 * Returns:
3471 * qla2x00 local function return status code.
3472 *
3473 * Context:
3474 * Kernel context.
3475 */
3476static int
e315cd28 3477qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3478 uint16_t *next_loopid)
3479{
3480 int rval;
3481 int retry;
0107109e 3482 uint8_t opts;
e315cd28 3483 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3484
3485 rval = QLA_SUCCESS;
3486 retry = 0;
3487
ac280b67 3488 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584
AV		 3489 if (fcport->flags & FCF_ASYNC_SENT)
3490 return rval;
3491 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 3492 rval = qla2x00_post_async_login_work(vha, fcport, NULL);
3493 if (!rval)
3494 return rval;
3495 }
3496
5ff1d584 3497 fcport->flags &= ~FCF_ASYNC_SENT;
e315cd28 3498 rval = qla2x00_fabric_login(vha, fcport, next_loopid);
1da177e4 3499 if (rval == QLA_SUCCESS) {
f08b7251 3500 /* Send an ADISC to FCP2 devices.*/
0107109e 3501 opts = 0;
f08b7251 3502 if (fcport->flags & FCF_FCP2_DEVICE)
0107109e 3503 opts |= BIT_1;
e315cd28 3504 rval = qla2x00_get_port_database(vha, fcport, opts);
1da177e4 3505 if (rval != QLA_SUCCESS) {
e315cd28 3506 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3507 fcport->d_id.b.domain, fcport->d_id.b.area,
3508 fcport->d_id.b.al_pa);
e315cd28 3509 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4 3510 } else {
e315cd28 3511 qla2x00_update_fcport(vha, fcport);
1da177e4 3512 }
0b91d116
CD		 3513 } else {
3514 /* Retry Login. */
3515 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3516 }
3517
3518 return (rval);
3519}
3520
3521/*
3522 * qla2x00_fabric_login
3523 * Issue fabric login command.
3524 *
3525 * Input:
3526 * ha = adapter block pointer.
3527 * device = pointer to FC device type structure.
3528 *
3529 * Returns:
3530 * 0 - Login successfully
3531 * 1 - Login failed
3532 * 2 - Initiator device
3533 * 3 - Fatal error
3534 */
3535int
e315cd28 3536qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3537 uint16_t *next_loopid)
3538{
3539 int rval;
3540 int retry;
3541 uint16_t tmp_loopid;
3542 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 3543 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3544
3545 retry = 0;
3546 tmp_loopid = 0;
3547
3548 for (;;) {
7c3df132
SK		 3549 ql_dbg(ql_dbg_disc, vha, 0x2000,
3550 "Trying Fabric Login w/loop id 0x%04x for port "
3551 "%02x%02x%02x.\n",
3552 fcport->loop_id, fcport->d_id.b.domain,
3553 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3554
3555 /* Login fcport on switch. */
0b91d116 3556 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
1da177e4
LT		 3557 fcport->d_id.b.domain, fcport->d_id.b.area,
3558 fcport->d_id.b.al_pa, mb, BIT_0);
0b91d116
CD		 3559 if (rval != QLA_SUCCESS) {
3560 return rval;
3561 }
1da177e4
LT		 3562 if (mb[0] == MBS_PORT_ID_USED) {
3563 /*
3564 * Device has another loop ID. The firmware team
0107109e
AV		 3565 * recommends the driver perform an implicit login with
3566 * the specified ID again. The ID we just used is save
3567 * here so we return with an ID that can be tried by
3568 * the next login.
1da177e4
LT		 3569 */
3570 retry++;
3571 tmp_loopid = fcport->loop_id;
3572 fcport->loop_id = mb[1];
3573
7c3df132
SK		 3574 ql_dbg(ql_dbg_disc, vha, 0x2001,
3575 "Fabric Login: port in use - next loop "
3576 "id=0x%04x, port id= %02x%02x%02x.\n",
1da177e4 3577 fcport->loop_id, fcport->d_id.b.domain,
7c3df132 3578 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3579
3580 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
3581 /*
3582 * Login succeeded.
3583 */
3584 if (retry) {
3585 /* A retry occurred before. */
3586 *next_loopid = tmp_loopid;
3587 } else {
3588 /*
3589 * No retry occurred before. Just increment the
3590 * ID value for next login.
3591 */
3592 *next_loopid = (fcport->loop_id + 1);
3593 }
3594
3595 if (mb[1] & BIT_0) {
3596 fcport->port_type = FCT_INITIATOR;
3597 } else {
3598 fcport->port_type = FCT_TARGET;
3599 if (mb[1] & BIT_1) {
8474f3a0 3600 fcport->flags |= FCF_FCP2_DEVICE;
1da177e4
LT		 3601 }
3602 }
3603
ad3e0eda
AV		 3604 if (mb[10] & BIT_0)
3605 fcport->supported_classes |= FC_COS_CLASS2;
3606 if (mb[10] & BIT_1)
3607 fcport->supported_classes |= FC_COS_CLASS3;
3608
2d70c103
NB		 3609 if (IS_FWI2_CAPABLE(ha)) {
3610 if (mb[10] & BIT_7)
3611 fcport->flags |=
3612 FCF_CONF_COMP_SUPPORTED;
3613 }
3614
1da177e4
LT		 3615 rval = QLA_SUCCESS;
3616 break;
3617 } else if (mb[0] == MBS_LOOP_ID_USED) {
3618 /*
3619 * Loop ID already used, try next loop ID.
3620 */
3621 fcport->loop_id++;
e315cd28 3622 rval = qla2x00_find_new_loop_id(vha, fcport);
1da177e4
LT		 3623 if (rval != QLA_SUCCESS) {
3624 /* Ran out of loop IDs to use */
3625 break;
3626 }
3627 } else if (mb[0] == MBS_COMMAND_ERROR) {
3628 /*
3629 * Firmware possibly timed out during login. If NO
3630 * retries are left to do then the device is declared
3631 * dead.
3632 */
3633 *next_loopid = fcport->loop_id;
e315cd28 3634 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3635 fcport->d_id.b.domain, fcport->d_id.b.area,
3636 fcport->d_id.b.al_pa);
e315cd28 3637 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3638
3639 rval = 1;
3640 break;
3641 } else {
3642 /*
3643 * unrecoverable / not handled error
3644 */
7c3df132
SK		 3645 ql_dbg(ql_dbg_disc, vha, 0x2002,
3646 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
3647 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
3648 fcport->d_id.b.area, fcport->d_id.b.al_pa,
3649 fcport->loop_id, jiffies);
1da177e4
LT		 3650
3651 *next_loopid = fcport->loop_id;
e315cd28 3652 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3653 fcport->d_id.b.domain, fcport->d_id.b.area,
3654 fcport->d_id.b.al_pa);
5f16b331 3655 qla2x00_clear_loop_id(fcport);
0eedfcf0 3656 fcport->login_retry = 0;
1da177e4
LT		 3657
3658 rval = 3;
3659 break;
3660 }
3661 }
3662
3663 return (rval);
3664}
3665
3666/*
3667 * qla2x00_local_device_login
3668 * Issue local device login command.
3669 *
3670 * Input:
3671 * ha = adapter block pointer.
3672 * loop_id = loop id of device to login to.
3673 *
3674 * Returns (Where's the #define!!!!):
3675 * 0 - Login successfully
3676 * 1 - Login failed
3677 * 3 - Fatal error
3678 */
3679int
e315cd28 3680qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
1da177e4
LT		 3681{
3682 int rval;
3683 uint16_t mb[MAILBOX_REGISTER_COUNT];
3684
3685 memset(mb, 0, sizeof(mb));
e315cd28 3686 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
1da177e4
LT		 3687 if (rval == QLA_SUCCESS) {
3688 /* Interrogate mailbox registers for any errors */
3689 if (mb[0] == MBS_COMMAND_ERROR)
3690 rval = 1;
3691 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
3692 /* device not in PCB table */
3693 rval = 3;
3694 }
3695
3696 return (rval);
3697}
3698
3699/*
3700 * qla2x00_loop_resync
3701 * Resync with fibre channel devices.
3702 *
3703 * Input:
3704 * ha = adapter block pointer.
3705 *
3706 * Returns:
3707 * 0 = success
3708 */
3709int
e315cd28 3710qla2x00_loop_resync(scsi_qla_host_t *vha)
1da177e4 3711{
73208dfd 3712 int rval = QLA_SUCCESS;
1da177e4 3713 uint32_t wait_time;
67c2e93a
AC		 3714 struct req_que *req;
3715 struct rsp_que *rsp;
3716
7163ea81 3717 if (vha->hw->flags.cpu_affinity_enabled)
67c2e93a
AC		 3718 req = vha->hw->req_q_map[0];
3719 else
3720 req = vha->req;
3721 rsp = req->rsp;
1da177e4 3722
e315cd28
AC		 3723 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
3724 if (vha->flags.online) {
3725 if (!(rval = qla2x00_fw_ready(vha))) {
1da177e4
LT		 3726 /* Wait at most MAX_TARGET RSCNs for a stable link. */
3727 wait_time = 256;
3728 do {
0107109e 3729 /* Issue a marker after FW becomes ready. */
73208dfd
AC		 3730 qla2x00_marker(vha, req, rsp, 0, 0,
3731 MK_SYNC_ALL);
e315cd28 3732 vha->marker_needed = 0;
1da177e4
LT		 3733
3734 /* Remap devices on Loop. */
e315cd28 3735 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4 3736
e315cd28 3737 qla2x00_configure_loop(vha);
1da177e4 3738 wait_time--;
e315cd28
AC		 3739 } while (!atomic_read(&vha->loop_down_timer) &&
3740 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
3741 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
3742 &vha->dpc_flags)));
1da177e4 3743 }
1da177e4
LT		 3744 }
3745
e315cd28 3746 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
1da177e4 3747 return (QLA_FUNCTION_FAILED);
1da177e4 3748
e315cd28 3749 if (rval)
7c3df132
SK		 3750 ql_dbg(ql_dbg_disc, vha, 0x206c,
3751 "%s *** FAILED ***.\n", __func__);
1da177e4
LT		 3752
3753 return (rval);
3754}
3755
579d12b5
SK		 3756/*
3757* qla2x00_perform_loop_resync
3758* Description: This function will set the appropriate flags and call
3759* qla2x00_loop_resync. If successful loop will be resynced
3760* Arguments : scsi_qla_host_t pointer
3761* returm : Success or Failure
3762*/
3763
3764int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
3765{
3766 int32_t rval = 0;
3767
3768 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
3769 /*Configure the flags so that resync happens properly*/
3770 atomic_set(&ha->loop_down_timer, 0);
3771 if (!(ha->device_flags & DFLG_NO_CABLE)) {
3772 atomic_set(&ha->loop_state, LOOP_UP);
3773 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
3774 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
3775 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
3776
3777 rval = qla2x00_loop_resync(ha);
3778 } else
3779 atomic_set(&ha->loop_state, LOOP_DEAD);
3780
3781 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
3782 }
3783
3784 return rval;
3785}
3786
d97994dc 3787void
67becc00 3788qla2x00_update_fcports(scsi_qla_host_t *base_vha)
d97994dc 3789{
3790 fc_port_t *fcport;
feafb7b1
AE		 3791 struct scsi_qla_host *vha;
3792 struct qla_hw_data *ha = base_vha->hw;
3793 unsigned long flags;
d97994dc 3794
feafb7b1 3795 spin_lock_irqsave(&ha->vport_slock, flags);
d97994dc 3796 /* Go with deferred removal of rport references. */
feafb7b1
AE		 3797 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
3798 atomic_inc(&vha->vref_count);
3799 list_for_each_entry(fcport, &vha->vp_fcports, list) {
8ae598d0 3800 if (fcport->drport &&
feafb7b1
AE		 3801 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
3802 spin_unlock_irqrestore(&ha->vport_slock, flags);
3803
67becc00 3804 qla2x00_rport_del(fcport);
feafb7b1
AE		 3805
3806 spin_lock_irqsave(&ha->vport_slock, flags);
3807 }
3808 }
3809 atomic_dec(&vha->vref_count);
3810 }
3811 spin_unlock_irqrestore(&ha->vport_slock, flags);
d97994dc 3812}
3813
7d613ac6
SV		 3814/* Assumes idc_lock always held on entry */
3815void
3816qla83xx_reset_ownership(scsi_qla_host_t *vha)
3817{
3818 struct qla_hw_data *ha = vha->hw;
3819 uint32_t drv_presence, drv_presence_mask;
3820 uint32_t dev_part_info1, dev_part_info2, class_type;
3821 uint32_t class_type_mask = 0x3;
3822 uint16_t fcoe_other_function = 0xffff, i;
3823
3824 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
3825
3826 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
3827 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
3828 for (i = 0; i < 8; i++) {
3829 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
3830 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
3831 (i != ha->portnum)) {
3832 fcoe_other_function = i;
3833 break;
3834 }
3835 }
3836 if (fcoe_other_function == 0xffff) {
3837 for (i = 0; i < 8; i++) {
3838 class_type = ((dev_part_info2 >> (i * 4)) &
3839 class_type_mask);
3840 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
3841 ((i + 8) != ha->portnum)) {
3842 fcoe_other_function = i + 8;
3843 break;
3844 }
3845 }
3846 }
3847 /*
3848 * Prepare drv-presence mask based on fcoe functions present.
3849 * However consider only valid physical fcoe function numbers (0-15).
3850 */
3851 drv_presence_mask = ~((1 << (ha->portnum)) |
3852 ((fcoe_other_function == 0xffff) ?
3853 0 : (1 << (fcoe_other_function))));
3854
3855 /* We are the reset owner iff:
3856 * - No other protocol drivers present.
3857 * - This is the lowest among fcoe functions. */
3858 if (!(drv_presence & drv_presence_mask) &&
3859 (ha->portnum < fcoe_other_function)) {
3860 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
3861 "This host is Reset owner.\n");
3862 ha->flags.nic_core_reset_owner = 1;
3863 }
3864}
3865
3866int
3867__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
3868{
3869 int rval = QLA_SUCCESS;
3870 struct qla_hw_data *ha = vha->hw;
3871 uint32_t drv_ack;
3872
3873 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
3874 if (rval == QLA_SUCCESS) {
3875 drv_ack |= (1 << ha->portnum);
3876 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
3877 }
3878
3879 return rval;
3880}
3881
3882int
3883qla83xx_set_drv_ack(scsi_qla_host_t *vha)
3884{
3885 int rval = QLA_SUCCESS;
3886
3887 qla83xx_idc_lock(vha, 0);
3888 rval = __qla83xx_set_drv_ack(vha);
3889 qla83xx_idc_unlock(vha, 0);
3890
3891 return rval;
3892}
3893
3894int
3895__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
3896{
3897 int rval = QLA_SUCCESS;
3898 struct qla_hw_data *ha = vha->hw;
3899 uint32_t drv_ack;
3900
3901 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
3902 if (rval == QLA_SUCCESS) {
3903 drv_ack &= ~(1 << ha->portnum);
3904 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
3905 }
3906
3907 return rval;
3908}
3909
3910int
3911qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
3912{
3913 int rval = QLA_SUCCESS;
3914
3915 qla83xx_idc_lock(vha, 0);
3916 rval = __qla83xx_clear_drv_ack(vha);
3917 qla83xx_idc_unlock(vha, 0);
3918
3919 return rval;
3920}
3921
3922const char *
3923qla83xx_dev_state_to_string(uint32_t dev_state)
3924{
3925 switch (dev_state) {
3926 case QLA8XXX_DEV_COLD:
3927 return "COLD/RE-INIT";
3928 case QLA8XXX_DEV_INITIALIZING:
3929 return "INITIALIZING";
3930 case QLA8XXX_DEV_READY:
3931 return "READY";
3932 case QLA8XXX_DEV_NEED_RESET:
3933 return "NEED RESET";
3934 case QLA8XXX_DEV_NEED_QUIESCENT:
3935 return "NEED QUIESCENT";
3936 case QLA8XXX_DEV_FAILED:
3937 return "FAILED";
3938 case QLA8XXX_DEV_QUIESCENT:
3939 return "QUIESCENT";
3940 default:
3941 return "Unknown";
3942 }
3943}
3944
3945/* Assumes idc-lock always held on entry */
3946void
3947qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
3948{
3949 struct qla_hw_data *ha = vha->hw;
3950 uint32_t idc_audit_reg = 0, duration_secs = 0;
3951
3952 switch (audit_type) {
3953 case IDC_AUDIT_TIMESTAMP:
3954 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
3955 idc_audit_reg = (ha->portnum) |
3956 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
3957 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
3958 break;
3959
3960 case IDC_AUDIT_COMPLETION:
3961 duration_secs = ((jiffies_to_msecs(jiffies) -
3962 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
3963 idc_audit_reg = (ha->portnum) |
3964 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
3965 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
3966 break;
3967
3968 default:
3969 ql_log(ql_log_warn, vha, 0xb078,
3970 "Invalid audit type specified.\n");
3971 break;
3972 }
3973}
3974
3975/* Assumes idc_lock always held on entry */
3976int
3977qla83xx_initiating_reset(scsi_qla_host_t *vha)
3978{
3979 struct qla_hw_data *ha = vha->hw;
3980 uint32_t idc_control, dev_state;
3981
3982 __qla83xx_get_idc_control(vha, &idc_control);
3983 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
3984 ql_log(ql_log_info, vha, 0xb080,
3985 "NIC Core reset has been disabled. idc-control=0x%x\n",
3986 idc_control);
3987 return QLA_FUNCTION_FAILED;
3988 }
3989
3990 /* Set NEED-RESET iff in READY state and we are the reset-owner */
3991 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
3992 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
3993 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
3994 QLA8XXX_DEV_NEED_RESET);
3995 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
3996 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
3997 } else {
3998 const char *state = qla83xx_dev_state_to_string(dev_state);
3999 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
4000
4001 /* SV: XXX: Is timeout required here? */
4002 /* Wait for IDC state change READY -> NEED_RESET */
4003 while (dev_state == QLA8XXX_DEV_READY) {
4004 qla83xx_idc_unlock(vha, 0);
4005 msleep(200);
4006 qla83xx_idc_lock(vha, 0);
4007 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4008 }
4009 }
4010
4011 /* Send IDC ack by writing to drv-ack register */
4012 __qla83xx_set_drv_ack(vha);
4013
4014 return QLA_SUCCESS;
4015}
4016
4017int
4018__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
4019{
4020 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4021}
4022
4023int
4024qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
4025{
4026 int rval = QLA_SUCCESS;
4027
4028 qla83xx_idc_lock(vha, 0);
4029 rval = __qla83xx_set_idc_control(vha, idc_control);
4030 qla83xx_idc_unlock(vha, 0);
4031
4032 return rval;
4033}
4034
4035int
4036__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
4037{
4038 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4039}
4040
4041int
4042qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
4043{
4044 int rval = QLA_SUCCESS;
4045
4046 qla83xx_idc_lock(vha, 0);
4047 rval = __qla83xx_get_idc_control(vha, idc_control);
4048 qla83xx_idc_unlock(vha, 0);
4049
4050 return rval;
4051}
4052
4053int
4054qla83xx_check_driver_presence(scsi_qla_host_t *vha)
4055{
4056 uint32_t drv_presence = 0;
4057 struct qla_hw_data *ha = vha->hw;
4058
4059 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4060 if (drv_presence & (1 << ha->portnum))
4061 return QLA_SUCCESS;
4062 else
4063 return QLA_TEST_FAILED;
4064}
4065
4066int
4067qla83xx_nic_core_reset(scsi_qla_host_t *vha)
4068{
4069 int rval = QLA_SUCCESS;
4070 struct qla_hw_data *ha = vha->hw;
4071
4072 ql_dbg(ql_dbg_p3p, vha, 0xb058,
4073 "Entered %s().\n", __func__);
4074
4075 if (vha->device_flags & DFLG_DEV_FAILED) {
4076 ql_log(ql_log_warn, vha, 0xb059,
4077 "Device in unrecoverable FAILED state.\n");
4078 return QLA_FUNCTION_FAILED;
4079 }
4080
4081 qla83xx_idc_lock(vha, 0);
4082
4083 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
4084 ql_log(ql_log_warn, vha, 0xb05a,
4085 "Function=0x%x has been removed from IDC participation.\n",
4086 ha->portnum);
4087 rval = QLA_FUNCTION_FAILED;
4088 goto exit;
4089 }
4090
4091 qla83xx_reset_ownership(vha);
4092
4093 rval = qla83xx_initiating_reset(vha);
4094
4095 /*
4096 * Perform reset if we are the reset-owner,
4097 * else wait till IDC state changes to READY/FAILED.
4098 */
4099 if (rval == QLA_SUCCESS) {
4100 rval = qla83xx_idc_state_handler(vha);
4101
4102 if (rval == QLA_SUCCESS)
4103 ha->flags.nic_core_hung = 0;
4104 __qla83xx_clear_drv_ack(vha);
4105 }
4106
4107exit:
4108 qla83xx_idc_unlock(vha, 0);
4109
4110 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
4111
4112 return rval;
4113}
4114
81178772
SK		 4115int
4116qla2xxx_mctp_dump(scsi_qla_host_t *vha)
4117{
4118 struct qla_hw_data *ha = vha->hw;
4119 int rval = QLA_FUNCTION_FAILED;
4120
4121 if (!IS_MCTP_CAPABLE(ha)) {
4122 /* This message can be removed from the final version */
4123 ql_log(ql_log_info, vha, 0x506d,
4124 "This board is not MCTP capable\n");
4125 return rval;
4126 }
4127
4128 if (!ha->mctp_dump) {
4129 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
4130 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
4131
4132 if (!ha->mctp_dump) {
4133 ql_log(ql_log_warn, vha, 0x506e,
4134 "Failed to allocate memory for mctp dump\n");
4135 return rval;
4136 }
4137 }
4138
4139#define MCTP_DUMP_STR_ADDR 0x00000000
4140 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
4141 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
4142 if (rval != QLA_SUCCESS) {
4143 ql_log(ql_log_warn, vha, 0x506f,
4144 "Failed to capture mctp dump\n");
4145 } else {
4146 ql_log(ql_log_info, vha, 0x5070,
4147 "Mctp dump capture for host (%ld/%p).\n",
4148 vha->host_no, ha->mctp_dump);
4149 ha->mctp_dumped = 1;
4150 }
4151
4152 if (!ha->flags.nic_core_reset_hdlr_active) {
4153 ha->flags.nic_core_reset_hdlr_active = 1;
4154 rval = qla83xx_restart_nic_firmware(vha);
4155 if (rval)
4156 /* NIC Core reset failed. */
4157 ql_log(ql_log_warn, vha, 0x5071,
4158 "Failed to restart nic firmware\n");
4159 else
4160 ql_dbg(ql_dbg_p3p, vha, 0xb084,
4161 "Restarted NIC firmware successfully.\n");
4162 ha->flags.nic_core_reset_hdlr_active = 0;
4163 }
4164
4165 return rval;
4166
4167}
4168
579d12b5 4169/*
8fcd6b8b 4170* qla2x00_quiesce_io
579d12b5
SK		 4171* Description: This function will block the new I/Os
4172* Its not aborting any I/Os as context
4173* is not destroyed during quiescence
4174* Arguments: scsi_qla_host_t
4175* return : void
4176*/
4177void
8fcd6b8b 4178qla2x00_quiesce_io(scsi_qla_host_t *vha)
579d12b5
SK		 4179{
4180 struct qla_hw_data *ha = vha->hw;
4181 struct scsi_qla_host *vp;
4182
8fcd6b8b
CD		 4183 ql_dbg(ql_dbg_dpc, vha, 0x401d,
4184 "Quiescing I/O - ha=%p.\n", ha);
579d12b5
SK		 4185
4186 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
4187 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4188 atomic_set(&vha->loop_state, LOOP_DOWN);
4189 qla2x00_mark_all_devices_lost(vha, 0);
4190 list_for_each_entry(vp, &ha->vp_list, list)
8fcd6b8b 4191 qla2x00_mark_all_devices_lost(vp, 0);
579d12b5
SK		 4192 } else {
4193 if (!atomic_read(&vha->loop_down_timer))
4194 atomic_set(&vha->loop_down_timer,
4195 LOOP_DOWN_TIME);
4196 }
4197 /* Wait for pending cmds to complete */
4198 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
4199}
4200
a9083016
GM		 4201void
4202qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
4203{
4204 struct qla_hw_data *ha = vha->hw;
579d12b5 4205 struct scsi_qla_host *vp;
feafb7b1 4206 unsigned long flags;
6aef87be 4207 fc_port_t *fcport;
a9083016 4208
e46ef004
SK		 4209 /* For ISP82XX, driver waits for completion of the commands.
4210 * online flag should be set.
4211 */
4212 if (!IS_QLA82XX(ha))
4213 vha->flags.online = 0;
a9083016
GM		 4214 ha->flags.chip_reset_done = 0;
4215 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2be21fa2 4216 vha->qla_stats.total_isp_aborts++;
a9083016 4217
7c3df132
SK		 4218 ql_log(ql_log_info, vha, 0x00af,
4219 "Performing ISP error recovery - ha=%p.\n", ha);
a9083016 4220
e46ef004
SK		 4221 /* For ISP82XX, reset_chip is just disabling interrupts.
4222 * Driver waits for the completion of the commands.
4223 * the interrupts need to be enabled.
4224 */
a9083016
GM		 4225 if (!IS_QLA82XX(ha))
4226 ha->isp_ops->reset_chip(vha);
4227
4228 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
4229 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4230 atomic_set(&vha->loop_state, LOOP_DOWN);
4231 qla2x00_mark_all_devices_lost(vha, 0);
feafb7b1
AE		 4232
4233 spin_lock_irqsave(&ha->vport_slock, flags);
579d12b5 4234 list_for_each_entry(vp, &ha->vp_list, list) {
feafb7b1
AE		 4235 atomic_inc(&vp->vref_count);
4236 spin_unlock_irqrestore(&ha->vport_slock, flags);
4237
a9083016 4238 qla2x00_mark_all_devices_lost(vp, 0);
feafb7b1
AE		 4239
4240 spin_lock_irqsave(&ha->vport_slock, flags);
4241 atomic_dec(&vp->vref_count);
4242 }
4243 spin_unlock_irqrestore(&ha->vport_slock, flags);
a9083016
GM		 4244 } else {
4245 if (!atomic_read(&vha->loop_down_timer))
4246 atomic_set(&vha->loop_down_timer,
4247 LOOP_DOWN_TIME);
4248 }
4249
6aef87be
AV		 4250 /* Clear all async request states across all VPs. */
4251 list_for_each_entry(fcport, &vha->vp_fcports, list)
4252 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4253 spin_lock_irqsave(&ha->vport_slock, flags);
4254 list_for_each_entry(vp, &ha->vp_list, list) {
4255 atomic_inc(&vp->vref_count);
4256 spin_unlock_irqrestore(&ha->vport_slock, flags);
4257
4258 list_for_each_entry(fcport, &vp->vp_fcports, list)
4259 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4260
4261 spin_lock_irqsave(&ha->vport_slock, flags);
4262 atomic_dec(&vp->vref_count);
4263 }
4264 spin_unlock_irqrestore(&ha->vport_slock, flags);
4265
bddd2d65
LC		 4266 if (!ha->flags.eeh_busy) {
4267 /* Make sure for ISP 82XX IO DMA is complete */
4268 if (IS_QLA82XX(ha)) {
7190575f 4269 qla82xx_chip_reset_cleanup(vha);
7c3df132
SK		 4270 ql_log(ql_log_info, vha, 0x00b4,
4271 "Done chip reset cleanup.\n");
a9083016 4272
e46ef004
SK		 4273 /* Done waiting for pending commands.
4274 * Reset the online flag.
4275 */
4276 vha->flags.online = 0;
4d78c973 4277 }
a9083016 4278
bddd2d65
LC		 4279 /* Requeue all commands in outstanding command list. */
4280 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
4281 }
a9083016
GM		 4282}
4283
1da177e4
LT		 4284/*
4285* qla2x00_abort_isp
4286* Resets ISP and aborts all outstanding commands.
4287*
4288* Input:
4289* ha = adapter block pointer.
4290*
4291* Returns:
4292* 0 = success
4293*/
4294int
e315cd28 4295qla2x00_abort_isp(scsi_qla_host_t *vha)
1da177e4 4296{
476e8978 4297 int rval;
1da177e4 4298 uint8_t status = 0;
e315cd28
AC		 4299 struct qla_hw_data *ha = vha->hw;
4300 struct scsi_qla_host *vp;
73208dfd 4301 struct req_que *req = ha->req_q_map[0];
feafb7b1 4302 unsigned long flags;
1da177e4 4303
e315cd28 4304 if (vha->flags.online) {
a9083016 4305 qla2x00_abort_isp_cleanup(vha);
1da177e4 4306
a6171297
SV		 4307 if (IS_QLA8031(ha)) {
4308 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
4309 "Clearing fcoe driver presence.\n");
4310 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
4311 ql_dbg(ql_dbg_p3p, vha, 0xb073,
4312 "Error while clearing DRV-Presence.\n");
4313 }
4314
85880801
AV		 4315 if (unlikely(pci_channel_offline(ha->pdev) &&
4316 ha->flags.pci_channel_io_perm_failure)) {
4317 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4318 status = 0;
4319 return status;
4320 }
4321
73208dfd 4322 ha->isp_ops->get_flash_version(vha, req->ring);
30c47662 4323
e315cd28 4324 ha->isp_ops->nvram_config(vha);
1da177e4 4325
e315cd28
AC		 4326 if (!qla2x00_restart_isp(vha)) {
4327 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4 4328
e315cd28 4329 if (!atomic_read(&vha->loop_down_timer)) {
1da177e4
LT		 4330 /*
4331 * Issue marker command only when we are going
4332 * to start the I/O .
4333 */
e315cd28 4334 vha->marker_needed = 1;
1da177e4
LT		 4335 }
4336
e315cd28 4337 vha->flags.online = 1;
1da177e4 4338
fd34f556 4339 ha->isp_ops->enable_intrs(ha);
1da177e4 4340
fa2a1ce5 4341 ha->isp_abort_cnt = 0;
e315cd28 4342 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
476e8978 4343
6246b8a1
GM		 4344 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
4345 qla2x00_get_fw_version(vha);
df613b96
AV		 4346 if (ha->fce) {
4347 ha->flags.fce_enabled = 1;
4348 memset(ha->fce, 0,
4349 fce_calc_size(ha->fce_bufs));
e315cd28 4350 rval = qla2x00_enable_fce_trace(vha,
df613b96
AV		 4351 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
4352 &ha->fce_bufs);
4353 if (rval) {
7c3df132 4354 ql_log(ql_log_warn, vha, 0x8033,
df613b96
AV		 4355 "Unable to reinitialize FCE "
4356 "(%d).\n", rval);
4357 ha->flags.fce_enabled = 0;
4358 }
4359 }
436a7b11
AV		 4360
4361 if (ha->eft) {
4362 memset(ha->eft, 0, EFT_SIZE);
e315cd28 4363 rval = qla2x00_enable_eft_trace(vha,
436a7b11
AV		 4364 ha->eft_dma, EFT_NUM_BUFFERS);
4365 if (rval) {
7c3df132 4366 ql_log(ql_log_warn, vha, 0x8034,
436a7b11
AV		 4367 "Unable to reinitialize EFT "
4368 "(%d).\n", rval);
4369 }
4370 }
1da177e4 4371 } else { /* failed the ISP abort */
e315cd28
AC		 4372 vha->flags.online = 1;
4373 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
1da177e4 4374 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 4375 ql_log(ql_log_fatal, vha, 0x8035,
4376 "ISP error recover failed - "
4377 "board disabled.\n");
fa2a1ce5 4378 /*
1da177e4
LT		 4379 * The next call disables the board
4380 * completely.
4381 */
e315cd28
AC		 4382 ha->isp_ops->reset_adapter(vha);
4383 vha->flags.online = 0;
1da177e4 4384 clear_bit(ISP_ABORT_RETRY,
e315cd28 4385 &vha->dpc_flags);
1da177e4
LT		 4386 status = 0;
4387 } else { /* schedule another ISP abort */
4388 ha->isp_abort_cnt--;
7c3df132
SK		 4389 ql_dbg(ql_dbg_taskm, vha, 0x8020,
4390 "ISP abort - retry remaining %d.\n",
4391 ha->isp_abort_cnt);
1da177e4
LT		 4392 status = 1;
4393 }
4394 } else {
4395 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 4396 ql_dbg(ql_dbg_taskm, vha, 0x8021,
4397 "ISP error recovery - retrying (%d) "
4398 "more times.\n", ha->isp_abort_cnt);
e315cd28 4399 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1da177e4
LT		 4400 status = 1;
4401 }
4402 }
fa2a1ce5 4403
1da177e4
LT		 4404 }
4405
e315cd28 4406 if (!status) {
7c3df132 4407 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
feafb7b1
AE		 4408
4409 spin_lock_irqsave(&ha->vport_slock, flags);
4410 list_for_each_entry(vp, &ha->vp_list, list) {
4411 if (vp->vp_idx) {
4412 atomic_inc(&vp->vref_count);
4413 spin_unlock_irqrestore(&ha->vport_slock, flags);
4414
e315cd28 4415 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 4416
4417 spin_lock_irqsave(&ha->vport_slock, flags);
4418 atomic_dec(&vp->vref_count);
4419 }
e315cd28 4420 }
feafb7b1
AE		 4421 spin_unlock_irqrestore(&ha->vport_slock, flags);
4422
7d613ac6
SV		 4423 if (IS_QLA8031(ha)) {
4424 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
4425 "Setting back fcoe driver presence.\n");
4426 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
4427 ql_dbg(ql_dbg_p3p, vha, 0xb074,
4428 "Error while setting DRV-Presence.\n");
4429 }
e315cd28 4430 } else {
d8424f68
JP		 4431 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
4432 __func__);
1da177e4
LT		 4433 }
4434
4435 return(status);
4436}
4437
4438/*
4439* qla2x00_restart_isp
4440* restarts the ISP after a reset
4441*
4442* Input:
4443* ha = adapter block pointer.
4444*
4445* Returns:
4446* 0 = success
4447*/
4448static int
e315cd28 4449qla2x00_restart_isp(scsi_qla_host_t *vha)
1da177e4 4450{
c6b2fca8 4451 int status = 0;
1da177e4 4452 uint32_t wait_time;
e315cd28 4453 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 4454 struct req_que *req = ha->req_q_map[0];
4455 struct rsp_que *rsp = ha->rsp_q_map[0];
2d70c103 4456 unsigned long flags;
1da177e4
LT		 4457
4458 /* If firmware needs to be loaded */
e315cd28
AC		 4459 if (qla2x00_isp_firmware(vha)) {
4460 vha->flags.online = 0;
4461 status = ha->isp_ops->chip_diag(vha);
4462 if (!status)
4463 status = qla2x00_setup_chip(vha);
1da177e4
LT		 4464 }
4465
e315cd28
AC		 4466 if (!status && !(status = qla2x00_init_rings(vha))) {
4467 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
2533cf67 4468 ha->flags.chip_reset_done = 1;
73208dfd
AC		 4469 /* Initialize the queues in use */
4470 qla25xx_init_queues(ha);
4471
e315cd28
AC		 4472 status = qla2x00_fw_ready(vha);
4473 if (!status) {
7c3df132
SK		 4474 ql_dbg(ql_dbg_taskm, vha, 0x8031,
4475 "Start configure loop status = %d.\n", status);
0107109e
AV		 4476
4477 /* Issue a marker after FW becomes ready. */
73208dfd 4478 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
0107109e 4479
e315cd28 4480 vha->flags.online = 1;
2d70c103
NB		 4481
4482 /*
4483 * Process any ATIO queue entries that came in
4484 * while we weren't online.
4485 */
4486 spin_lock_irqsave(&ha->hardware_lock, flags);
4487 if (qla_tgt_mode_enabled(vha))
4488 qlt_24xx_process_atio_queue(vha);
4489 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4490
1da177e4
LT		 4491 /* Wait at most MAX_TARGET RSCNs for a stable link. */
4492 wait_time = 256;
4493 do {
e315cd28
AC		 4494 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
4495 qla2x00_configure_loop(vha);
1da177e4 4496 wait_time--;
e315cd28
AC		 4497 } while (!atomic_read(&vha->loop_down_timer) &&
4498 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
4499 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
4500 &vha->dpc_flags)));
1da177e4
LT		 4501 }
4502
4503 /* if no cable then assume it's good */
e315cd28 4504 if ((vha->device_flags & DFLG_NO_CABLE))
1da177e4
LT		 4505 status = 0;
4506
7c3df132
SK		 4507 ql_dbg(ql_dbg_taskm, vha, 0x8032,
4508 "Configure loop done, status = 0x%x.\n", status);
1da177e4
LT		 4509 }
4510 return (status);
4511}
4512
73208dfd
AC		 4513static int
4514qla25xx_init_queues(struct qla_hw_data *ha)
4515{
4516 struct rsp_que *rsp = NULL;
4517 struct req_que *req = NULL;
4518 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
4519 int ret = -1;
4520 int i;
4521
2afa19a9 4522 for (i = 1; i < ha->max_rsp_queues; i++) {
73208dfd
AC		 4523 rsp = ha->rsp_q_map[i];
4524 if (rsp) {
4525 rsp->options &= ~BIT_0;
618a7523 4526 ret = qla25xx_init_rsp_que(base_vha, rsp);
73208dfd 4527 if (ret != QLA_SUCCESS)
7c3df132
SK		 4528 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
4529 "%s Rsp que: %d init failed.\n",
4530 __func__, rsp->id);
73208dfd 4531 else
7c3df132
SK		 4532 ql_dbg(ql_dbg_init, base_vha, 0x0100,
4533 "%s Rsp que: %d inited.\n",
4534 __func__, rsp->id);
73208dfd 4535 }
2afa19a9
AC		 4536 }
4537 for (i = 1; i < ha->max_req_queues; i++) {
73208dfd
AC		 4538 req = ha->req_q_map[i];
4539 if (req) {
29bdccbe 4540 /* Clear outstanding commands array. */
73208dfd 4541 req->options &= ~BIT_0;
618a7523 4542 ret = qla25xx_init_req_que(base_vha, req);
73208dfd 4543 if (ret != QLA_SUCCESS)
7c3df132
SK		 4544 ql_dbg(ql_dbg_init, base_vha, 0x0101,
4545 "%s Req que: %d init failed.\n",
4546 __func__, req->id);
73208dfd 4547 else
7c3df132
SK		 4548 ql_dbg(ql_dbg_init, base_vha, 0x0102,
4549 "%s Req que: %d inited.\n",
4550 __func__, req->id);
73208dfd
AC		 4551 }
4552 }
4553 return ret;
4554}
4555
1da177e4
LT		 4556/*
4557* qla2x00_reset_adapter
4558* Reset adapter.
4559*
4560* Input:
4561* ha = adapter block pointer.
4562*/
abbd8870 4563void
e315cd28 4564qla2x00_reset_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 4565{
4566 unsigned long flags = 0;
e315cd28 4567 struct qla_hw_data *ha = vha->hw;
3d71644c 4568 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 4569
e315cd28 4570 vha->flags.online = 0;
fd34f556 4571 ha->isp_ops->disable_intrs(ha);
1da177e4 4572
1da177e4
LT		 4573 spin_lock_irqsave(&ha->hardware_lock, flags);
4574 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
4575 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4576 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
4577 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4578 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4579}
0107109e
AV		 4580
4581void
e315cd28 4582qla24xx_reset_adapter(scsi_qla_host_t *vha)
0107109e
AV		 4583{
4584 unsigned long flags = 0;
e315cd28 4585 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 4586 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
4587
a9083016
GM		 4588 if (IS_QLA82XX(ha))
4589 return;
4590
e315cd28 4591 vha->flags.online = 0;
fd34f556 4592 ha->isp_ops->disable_intrs(ha);
0107109e
AV		 4593
4594 spin_lock_irqsave(&ha->hardware_lock, flags);
4595 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
4596 RD_REG_DWORD(&reg->hccr);
4597 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
4598 RD_REG_DWORD(&reg->hccr);
4599 spin_unlock_irqrestore(&ha->hardware_lock, flags);
09ff36d3
AV		 4600
4601 if (IS_NOPOLLING_TYPE(ha))
4602 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 4603}
4604
4e08df3f
DM		 4605/* On sparc systems, obtain port and node WWN from firmware
4606 * properties.
4607 */
e315cd28
AC		 4608static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
4609 struct nvram_24xx *nv)
4e08df3f
DM		 4610{
4611#ifdef CONFIG_SPARC
e315cd28 4612 struct qla_hw_data *ha = vha->hw;
4e08df3f 4613 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 4614 struct device_node *dp = pci_device_to_OF_node(pdev);
4615 const u8 *val;
4e08df3f
DM		 4616 int len;
4617
4618 val = of_get_property(dp, "port-wwn", &len);
4619 if (val && len >= WWN_SIZE)
4620 memcpy(nv->port_name, val, WWN_SIZE);
4621
4622 val = of_get_property(dp, "node-wwn", &len);
4623 if (val && len >= WWN_SIZE)
4624 memcpy(nv->node_name, val, WWN_SIZE);
4625#endif
4626}
4627
0107109e 4628int
e315cd28 4629qla24xx_nvram_config(scsi_qla_host_t *vha)
0107109e 4630{
4e08df3f 4631 int rval;
0107109e
AV		 4632 struct init_cb_24xx *icb;
4633 struct nvram_24xx *nv;
4634 uint32_t *dptr;
4635 uint8_t *dptr1, *dptr2;
4636 uint32_t chksum;
4637 uint16_t cnt;
e315cd28 4638 struct qla_hw_data *ha = vha->hw;
0107109e 4639
4e08df3f 4640 rval = QLA_SUCCESS;
0107109e 4641 icb = (struct init_cb_24xx *)ha->init_cb;
281afe19 4642 nv = ha->nvram;
0107109e
AV		 4643
4644 /* Determine NVRAM starting address. */
e5b68a61
AC		 4645 if (ha->flags.port0) {
4646 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
4647 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
4648 } else {
0107109e 4649 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
6f641790 4650 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
4651 }
e5b68a61
AC		 4652 ha->nvram_size = sizeof(struct nvram_24xx);
4653 ha->vpd_size = FA_NVRAM_VPD_SIZE;
a9083016
GM		 4654 if (IS_QLA82XX(ha))
4655 ha->vpd_size = FA_VPD_SIZE_82XX;
0107109e 4656
281afe19
SJ		 4657 /* Get VPD data into cache */
4658 ha->vpd = ha->nvram + VPD_OFFSET;
e315cd28 4659 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
281afe19
SJ		 4660 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
4661
4662 /* Get NVRAM data into cache and calculate checksum. */
0107109e 4663 dptr = (uint32_t *)nv;
e315cd28 4664 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
0107109e
AV		 4665 ha->nvram_size);
4666 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
4667 chksum += le32_to_cpu(*dptr++);
4668
7c3df132
SK		 4669 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
4670 "Contents of NVRAM\n");
4671 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
4672 (uint8_t *)nv, ha->nvram_size);
0107109e
AV		 4673
4674 /* Bad NVRAM data, set defaults parameters. */
4675 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
4676 || nv->id[3] != ' ' ||
4677 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
4678 /* Reset NVRAM data. */
7c3df132 4679 ql_log(ql_log_warn, vha, 0x006b,
9e336520 4680 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132
SK		 4681 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
4682 ql_log(ql_log_warn, vha, 0x006c,
4683 "Falling back to functioning (yet invalid -- WWPN) "
4684 "defaults.\n");
4e08df3f
DM		 4685
4686 /*
4687 * Set default initialization control block.
4688 */
4689 memset(nv, 0, ha->nvram_size);
4690 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
4691 nv->version = __constant_cpu_to_le16(ICB_VERSION);
4692 nv->frame_payload_size = __constant_cpu_to_le16(2048);
4693 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4694 nv->exchange_count = __constant_cpu_to_le16(0);
4695 nv->hard_address = __constant_cpu_to_le16(124);
4696 nv->port_name[0] = 0x21;
e5b68a61 4697 nv->port_name[1] = 0x00 + ha->port_no;
4e08df3f
DM		 4698 nv->port_name[2] = 0x00;
4699 nv->port_name[3] = 0xe0;
4700 nv->port_name[4] = 0x8b;
4701 nv->port_name[5] = 0x1c;
4702 nv->port_name[6] = 0x55;
4703 nv->port_name[7] = 0x86;
4704 nv->node_name[0] = 0x20;
4705 nv->node_name[1] = 0x00;
4706 nv->node_name[2] = 0x00;
4707 nv->node_name[3] = 0xe0;
4708 nv->node_name[4] = 0x8b;
4709 nv->node_name[5] = 0x1c;
4710 nv->node_name[6] = 0x55;
4711 nv->node_name[7] = 0x86;
e315cd28 4712 qla24xx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 4713 nv->login_retry_count = __constant_cpu_to_le16(8);
4714 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
4715 nv->login_timeout = __constant_cpu_to_le16(0);
4716 nv->firmware_options_1 =
4717 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
4718 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
4719 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
4720 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
4721 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
4722 nv->efi_parameters = __constant_cpu_to_le32(0);
4723 nv->reset_delay = 5;
4724 nv->max_luns_per_target = __constant_cpu_to_le16(128);
4725 nv->port_down_retry_count = __constant_cpu_to_le16(30);
4726 nv->link_down_timeout = __constant_cpu_to_le16(30);
4727
4728 rval = 1;
0107109e
AV		 4729 }
4730
2d70c103
NB		 4731 if (!qla_ini_mode_enabled(vha)) {
4732 /* Don't enable full login after initial LIP */
4733 nv->firmware_options_1 &= __constant_cpu_to_le32(~BIT_13);
4734 /* Don't enable LIP full login for initiator */
4735 nv->host_p &= __constant_cpu_to_le32(~BIT_10);
4736 }
4737
4738 qlt_24xx_config_nvram_stage1(vha, nv);
4739
0107109e 4740 /* Reset Initialization control block */
e315cd28 4741 memset(icb, 0, ha->init_cb_size);
0107109e
AV		 4742
4743 /* Copy 1st segment. */
4744 dptr1 = (uint8_t *)icb;
4745 dptr2 = (uint8_t *)&nv->version;
4746 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
4747 while (cnt--)
4748 *dptr1++ = *dptr2++;
4749
4750 icb->login_retry_count = nv->login_retry_count;
3ea66e28 4751 icb->link_down_on_nos = nv->link_down_on_nos;
0107109e
AV		 4752
4753 /* Copy 2nd segment. */
4754 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
4755 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
4756 cnt = (uint8_t *)&icb->reserved_3 -
4757 (uint8_t *)&icb->interrupt_delay_timer;
4758 while (cnt--)
4759 *dptr1++ = *dptr2++;
4760
4761 /*
4762 * Setup driver NVRAM options.
4763 */
e315cd28 4764 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9bb9fcf2 4765 "QLA2462");
0107109e 4766
2d70c103
NB		 4767 qlt_24xx_config_nvram_stage2(vha, icb);
4768
5341e868 4769 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
2d70c103 4770 /* Use alternate WWN? */
5341e868
AV		 4771 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
4772 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
4773 }
4774
0107109e 4775 /* Prepare nodename */
fd0e7e4d 4776 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
0107109e
AV		 4777 /*
4778 * Firmware will apply the following mask if the nodename was
4779 * not provided.
4780 */
4781 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
4782 icb->node_name[0] &= 0xF0;
4783 }
4784
4785 /* Set host adapter parameters. */
4786 ha->flags.disable_risc_code_load = 0;
0c8c39af
AV		 4787 ha->flags.enable_lip_reset = 0;
4788 ha->flags.enable_lip_full_login =
4789 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
4790 ha->flags.enable_target_reset =
4791 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
0107109e 4792 ha->flags.enable_led_scheme = 0;
d4c760c2 4793 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
0107109e 4794
fd0e7e4d
AV		 4795 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
4796 (BIT_6 | BIT_5 | BIT_4)) >> 4;
0107109e
AV		 4797
4798 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
4799 sizeof(ha->fw_seriallink_options24));
4800
4801 /* save HBA serial number */
4802 ha->serial0 = icb->port_name[5];
4803 ha->serial1 = icb->port_name[6];
4804 ha->serial2 = icb->port_name[7];
e315cd28
AC		 4805 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
4806 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
0107109e 4807
bc8fb3cb 4808 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4809
0107109e
AV		 4810 ha->retry_count = le16_to_cpu(nv->login_retry_count);
4811
4812 /* Set minimum login_timeout to 4 seconds. */
4813 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
4814 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
4815 if (le16_to_cpu(nv->login_timeout) < 4)
4816 nv->login_timeout = __constant_cpu_to_le16(4);
4817 ha->login_timeout = le16_to_cpu(nv->login_timeout);
c6852c4c 4818 icb->login_timeout = nv->login_timeout;
0107109e 4819
00a537b8
AV		 4820 /* Set minimum RATOV to 100 tenths of a second. */
4821 ha->r_a_tov = 100;
0107109e
AV		 4822
4823 ha->loop_reset_delay = nv->reset_delay;
4824
4825 /* Link Down Timeout = 0:
4826 *
4827 * When Port Down timer expires we will start returning
4828 * I/O's to OS with "DID_NO_CONNECT".
4829 *
4830 * Link Down Timeout != 0:
4831 *
4832 * The driver waits for the link to come up after link down
4833 * before returning I/Os to OS with "DID_NO_CONNECT".
4834 */
4835 if (le16_to_cpu(nv->link_down_timeout) == 0) {
4836 ha->loop_down_abort_time =
4837 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
4838 } else {
4839 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
4840 ha->loop_down_abort_time =
4841 (LOOP_DOWN_TIME - ha->link_down_timeout);
4842 }
4843
4844 /* Need enough time to try and get the port back. */
4845 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
4846 if (qlport_down_retry)
4847 ha->port_down_retry_count = qlport_down_retry;
4848
4849 /* Set login_retry_count */
4850 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
4851 if (ha->port_down_retry_count ==
4852 le16_to_cpu(nv->port_down_retry_count) &&
4853 ha->port_down_retry_count > 3)
4854 ha->login_retry_count = ha->port_down_retry_count;
4855 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
4856 ha->login_retry_count = ha->port_down_retry_count;
4857 if (ql2xloginretrycount)
4858 ha->login_retry_count = ql2xloginretrycount;
4859
4fdfefe5 4860 /* Enable ZIO. */
e315cd28 4861 if (!vha->flags.init_done) {
4fdfefe5
AV		 4862 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
4863 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
4864 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
4865 le16_to_cpu(icb->interrupt_delay_timer): 2;
4866 }
4867 icb->firmware_options_2 &= __constant_cpu_to_le32(
4868 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
e315cd28 4869 vha->flags.process_response_queue = 0;
4fdfefe5 4870 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d 4871 ha->zio_mode = QLA_ZIO_MODE_6;
4872
7c3df132 4873 ql_log(ql_log_info, vha, 0x006f,
4fdfefe5
AV		 4874 "ZIO mode %d enabled; timer delay (%d us).\n",
4875 ha->zio_mode, ha->zio_timer * 100);
4876
4877 icb->firmware_options_2 |= cpu_to_le32(
4878 (uint32_t)ha->zio_mode);
4879 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
e315cd28 4880 vha->flags.process_response_queue = 1;
4fdfefe5
AV		 4881 }
4882
4e08df3f 4883 if (rval) {
7c3df132
SK		 4884 ql_log(ql_log_warn, vha, 0x0070,
4885 "NVRAM configuration failed.\n");
4e08df3f
DM		 4886 }
4887 return (rval);
0107109e
AV		 4888}
4889
413975a0 4890static int
cbc8eb67
AV		 4891qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
4892 uint32_t faddr)
d1c61909 4893{
73208dfd 4894 int rval = QLA_SUCCESS;
d1c61909 4895 int segments, fragment;
d1c61909
AV		 4896 uint32_t *dcode, dlen;
4897 uint32_t risc_addr;
4898 uint32_t risc_size;
4899 uint32_t i;
e315cd28 4900 struct qla_hw_data *ha = vha->hw;
73208dfd 4901 struct req_que *req = ha->req_q_map[0];
eaac30be 4902
7c3df132 4903 ql_dbg(ql_dbg_init, vha, 0x008b,
cfb0919c 4904 "FW: Loading firmware from flash (%x).\n", faddr);
eaac30be 4905
d1c61909
AV		 4906 rval = QLA_SUCCESS;
4907
4908 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 4909 dcode = (uint32_t *)req->ring;
d1c61909
AV		 4910 *srisc_addr = 0;
4911
4912 /* Validate firmware image by checking version. */
e315cd28 4913 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
d1c61909
AV		 4914 for (i = 0; i < 4; i++)
4915 dcode[i] = be32_to_cpu(dcode[i]);
4916 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
4917 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
4918 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
4919 dcode[3] == 0)) {
7c3df132
SK		 4920 ql_log(ql_log_fatal, vha, 0x008c,
4921 "Unable to verify the integrity of flash firmware "
4922 "image.\n");
4923 ql_log(ql_log_fatal, vha, 0x008d,
4924 "Firmware data: %08x %08x %08x %08x.\n",
4925 dcode[0], dcode[1], dcode[2], dcode[3]);
d1c61909
AV		 4926
4927 return QLA_FUNCTION_FAILED;
4928 }
4929
4930 while (segments && rval == QLA_SUCCESS) {
4931 /* Read segment's load information. */
e315cd28 4932 qla24xx_read_flash_data(vha, dcode, faddr, 4);
d1c61909
AV		 4933
4934 risc_addr = be32_to_cpu(dcode[2]);
4935 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
4936 risc_size = be32_to_cpu(dcode[3]);
4937
4938 fragment = 0;
4939 while (risc_size > 0 && rval == QLA_SUCCESS) {
4940 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
4941 if (dlen > risc_size)
4942 dlen = risc_size;
4943
7c3df132
SK		 4944 ql_dbg(ql_dbg_init, vha, 0x008e,
4945 "Loading risc segment@ risc addr %x "
4946 "number of dwords 0x%x offset 0x%x.\n",
4947 risc_addr, dlen, faddr);
d1c61909 4948
e315cd28 4949 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
d1c61909
AV		 4950 for (i = 0; i < dlen; i++)
4951 dcode[i] = swab32(dcode[i]);
4952
73208dfd 4953 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
d1c61909
AV		 4954 dlen);
4955 if (rval) {
7c3df132
SK		 4956 ql_log(ql_log_fatal, vha, 0x008f,
4957 "Failed to load segment %d of firmware.\n",
4958 fragment);
d1c61909
AV		 4959 break;
4960 }
4961
4962 faddr += dlen;
4963 risc_addr += dlen;
4964 risc_size -= dlen;
4965 fragment++;
4966 }
4967
4968 /* Next segment. */
4969 segments--;
4970 }
4971
4972 return rval;
4973}
4974
d1c61909
AV		 4975#define QLA_FW_URL "ftp://ftp.qlogic.com/outgoing/linux/firmware/"
4976
0107109e 4977int
e315cd28 4978qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5433383e
AV		 4979{
4980 int rval;
4981 int i, fragment;
4982 uint16_t *wcode, *fwcode;
4983 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
4984 struct fw_blob *blob;
e315cd28 4985 struct qla_hw_data *ha = vha->hw;
73208dfd 4986 struct req_que *req = ha->req_q_map[0];
5433383e
AV		 4987
4988 /* Load firmware blob. */
e315cd28 4989 blob = qla2x00_request_firmware(vha);
5433383e 4990 if (!blob) {
7c3df132
SK		 4991 ql_log(ql_log_info, vha, 0x0083,
4992 "Fimware image unavailable.\n");
4993 ql_log(ql_log_info, vha, 0x0084,
4994 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5433383e
AV		 4995 return QLA_FUNCTION_FAILED;
4996 }
4997
4998 rval = QLA_SUCCESS;
4999
73208dfd 5000 wcode = (uint16_t *)req->ring;
5433383e
AV		 5001 *srisc_addr = 0;
5002 fwcode = (uint16_t *)blob->fw->data;
5003 fwclen = 0;
5004
5005 /* Validate firmware image by checking version. */
5006 if (blob->fw->size < 8 * sizeof(uint16_t)) {
7c3df132
SK		 5007 ql_log(ql_log_fatal, vha, 0x0085,
5008 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e
AV		 5009 blob->fw->size);
5010 goto fail_fw_integrity;
5011 }
5012 for (i = 0; i < 4; i++)
5013 wcode[i] = be16_to_cpu(fwcode[i + 4]);
5014 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
5015 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
5016 wcode[2] == 0 && wcode[3] == 0)) {
7c3df132
SK		 5017 ql_log(ql_log_fatal, vha, 0x0086,
5018 "Unable to verify integrity of firmware image.\n");
5019 ql_log(ql_log_fatal, vha, 0x0087,
5020 "Firmware data: %04x %04x %04x %04x.\n",
5021 wcode[0], wcode[1], wcode[2], wcode[3]);
5433383e
AV		 5022 goto fail_fw_integrity;
5023 }
5024
5025 seg = blob->segs;
5026 while (*seg && rval == QLA_SUCCESS) {
5027 risc_addr = *seg;
5028 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
5029 risc_size = be16_to_cpu(fwcode[3]);
5030
5031 /* Validate firmware image size. */
5032 fwclen += risc_size * sizeof(uint16_t);
5033 if (blob->fw->size < fwclen) {
7c3df132 5034 ql_log(ql_log_fatal, vha, 0x0088,
5433383e 5035 "Unable to verify integrity of firmware image "
7c3df132 5036 "(%Zd).\n", blob->fw->size);
5433383e
AV		 5037 goto fail_fw_integrity;
5038 }
5039
5040 fragment = 0;
5041 while (risc_size > 0 && rval == QLA_SUCCESS) {
5042 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
5043 if (wlen > risc_size)
5044 wlen = risc_size;
7c3df132
SK		 5045 ql_dbg(ql_dbg_init, vha, 0x0089,
5046 "Loading risc segment@ risc addr %x number of "
5047 "words 0x%x.\n", risc_addr, wlen);
5433383e
AV		 5048
5049 for (i = 0; i < wlen; i++)
5050 wcode[i] = swab16(fwcode[i]);
5051
73208dfd 5052 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5433383e
AV		 5053 wlen);
5054 if (rval) {
7c3df132
SK		 5055 ql_log(ql_log_fatal, vha, 0x008a,
5056 "Failed to load segment %d of firmware.\n",
5057 fragment);
5433383e
AV		 5058 break;
5059 }
5060
5061 fwcode += wlen;
5062 risc_addr += wlen;
5063 risc_size -= wlen;
5064 fragment++;
5065 }
5066
5067 /* Next segment. */
5068 seg++;
5069 }
5070 return rval;
5071
5072fail_fw_integrity:
5073 return QLA_FUNCTION_FAILED;
5074}
5075
eaac30be
AV		 5076static int
5077qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
0107109e
AV		 5078{
5079 int rval;
5080 int segments, fragment;
5081 uint32_t *dcode, dlen;
5082 uint32_t risc_addr;
5083 uint32_t risc_size;
5084 uint32_t i;
5433383e 5085 struct fw_blob *blob;
0107109e 5086 uint32_t *fwcode, fwclen;
e315cd28 5087 struct qla_hw_data *ha = vha->hw;
73208dfd 5088 struct req_que *req = ha->req_q_map[0];
0107109e 5089
5433383e 5090 /* Load firmware blob. */
e315cd28 5091 blob = qla2x00_request_firmware(vha);
5433383e 5092 if (!blob) {
7c3df132
SK		 5093 ql_log(ql_log_warn, vha, 0x0090,
5094 "Fimware image unavailable.\n");
5095 ql_log(ql_log_warn, vha, 0x0091,
5096 "Firmware images can be retrieved from: "
5097 QLA_FW_URL ".\n");
d1c61909 5098
eaac30be 5099 return QLA_FUNCTION_FAILED;
0107109e
AV		 5100 }
5101
cfb0919c
CD		 5102 ql_dbg(ql_dbg_init, vha, 0x0092,
5103 "FW: Loading via request-firmware.\n");
eaac30be 5104
0107109e
AV		 5105 rval = QLA_SUCCESS;
5106
5107 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5108 dcode = (uint32_t *)req->ring;
0107109e 5109 *srisc_addr = 0;
5433383e 5110 fwcode = (uint32_t *)blob->fw->data;
0107109e
AV		 5111 fwclen = 0;
5112
5113 /* Validate firmware image by checking version. */
5433383e 5114 if (blob->fw->size < 8 * sizeof(uint32_t)) {
7c3df132
SK		 5115 ql_log(ql_log_fatal, vha, 0x0093,
5116 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e 5117 blob->fw->size);
0107109e
AV		 5118 goto fail_fw_integrity;
5119 }
5120 for (i = 0; i < 4; i++)
5121 dcode[i] = be32_to_cpu(fwcode[i + 4]);
5122 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5123 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5124 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5125 dcode[3] == 0)) {
7c3df132
SK		 5126 ql_log(ql_log_fatal, vha, 0x0094,
5127 "Unable to verify integrity of firmware image (%Zd).\n",
5128 blob->fw->size);
5129 ql_log(ql_log_fatal, vha, 0x0095,
5130 "Firmware data: %08x %08x %08x %08x.\n",
5131 dcode[0], dcode[1], dcode[2], dcode[3]);
0107109e
AV		 5132 goto fail_fw_integrity;
5133 }
5134
5135 while (segments && rval == QLA_SUCCESS) {
5136 risc_addr = be32_to_cpu(fwcode[2]);
5137 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5138 risc_size = be32_to_cpu(fwcode[3]);
5139
5140 /* Validate firmware image size. */
5141 fwclen += risc_size * sizeof(uint32_t);
5433383e 5142 if (blob->fw->size < fwclen) {
7c3df132 5143 ql_log(ql_log_fatal, vha, 0x0096,
5433383e 5144 "Unable to verify integrity of firmware image "
7c3df132 5145 "(%Zd).\n", blob->fw->size);
5433383e 5146
0107109e
AV		 5147 goto fail_fw_integrity;
5148 }
5149
5150 fragment = 0;
5151 while (risc_size > 0 && rval == QLA_SUCCESS) {
5152 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5153 if (dlen > risc_size)
5154 dlen = risc_size;
5155
7c3df132
SK		 5156 ql_dbg(ql_dbg_init, vha, 0x0097,
5157 "Loading risc segment@ risc addr %x "
5158 "number of dwords 0x%x.\n", risc_addr, dlen);
0107109e
AV		 5159
5160 for (i = 0; i < dlen; i++)
5161 dcode[i] = swab32(fwcode[i]);
5162
73208dfd 5163 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
590f98e5 5164 dlen);
0107109e 5165 if (rval) {
7c3df132
SK		 5166 ql_log(ql_log_fatal, vha, 0x0098,
5167 "Failed to load segment %d of firmware.\n",
5168 fragment);
0107109e
AV		 5169 break;
5170 }
5171
5172 fwcode += dlen;
5173 risc_addr += dlen;
5174 risc_size -= dlen;
5175 fragment++;
5176 }
5177
5178 /* Next segment. */
5179 segments--;
5180 }
0107109e
AV		 5181 return rval;
5182
5183fail_fw_integrity:
0107109e 5184 return QLA_FUNCTION_FAILED;
0107109e 5185}
18c6c127 5186
eaac30be
AV		 5187int
5188qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5189{
5190 int rval;
5191
e337d907
AV		 5192 if (ql2xfwloadbin == 1)
5193 return qla81xx_load_risc(vha, srisc_addr);
5194
eaac30be
AV		 5195 /*
5196 * FW Load priority:
5197 * 1) Firmware via request-firmware interface (.bin file).
5198 * 2) Firmware residing in flash.
5199 */
5200 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5201 if (rval == QLA_SUCCESS)
5202 return rval;
5203
cbc8eb67
AV		 5204 return qla24xx_load_risc_flash(vha, srisc_addr,
5205 vha->hw->flt_region_fw);
eaac30be
AV		 5206}
5207
5208int
5209qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5210{
5211 int rval;
cbc8eb67 5212 struct qla_hw_data *ha = vha->hw;
eaac30be 5213
e337d907 5214 if (ql2xfwloadbin == 2)
cbc8eb67 5215 goto try_blob_fw;
e337d907 5216
eaac30be
AV		 5217 /*
5218 * FW Load priority:
5219 * 1) Firmware residing in flash.
5220 * 2) Firmware via request-firmware interface (.bin file).
cbc8eb67 5221 * 3) Golden-Firmware residing in flash -- limited operation.
eaac30be 5222 */
cbc8eb67 5223 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
eaac30be
AV		 5224 if (rval == QLA_SUCCESS)
5225 return rval;
5226
cbc8eb67
AV		 5227try_blob_fw:
5228 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5229 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
5230 return rval;
5231
7c3df132
SK		 5232 ql_log(ql_log_info, vha, 0x0099,
5233 "Attempting to fallback to golden firmware.\n");
cbc8eb67
AV		 5234 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
5235 if (rval != QLA_SUCCESS)
5236 return rval;
5237
7c3df132 5238 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
cbc8eb67 5239 ha->flags.running_gold_fw = 1;
cbc8eb67 5240 return rval;
eaac30be
AV		 5241}
5242
18c6c127 5243void
e315cd28 5244qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
18c6c127
AV		 5245{
5246 int ret, retries;
e315cd28 5247 struct qla_hw_data *ha = vha->hw;
18c6c127 5248
85880801
AV		 5249 if (ha->flags.pci_channel_io_perm_failure)
5250 return;
e428924c 5251 if (!IS_FWI2_CAPABLE(ha))
18c6c127 5252 return;
75edf81d
AV		 5253 if (!ha->fw_major_version)
5254 return;
18c6c127 5255
e315cd28 5256 ret = qla2x00_stop_firmware(vha);
7c7f1f29 5257 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
b469a7cb 5258 ret != QLA_INVALID_COMMAND && retries ; retries--) {
e315cd28
AC		 5259 ha->isp_ops->reset_chip(vha);
5260 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
18c6c127 5261 continue;
e315cd28 5262 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
18c6c127 5263 continue;
7c3df132
SK		 5264 ql_log(ql_log_info, vha, 0x8015,
5265 "Attempting retry of stop-firmware command.\n");
e315cd28 5266 ret = qla2x00_stop_firmware(vha);
18c6c127
AV		 5267 }
5268}
2c3dfe3f
SJ		 5269
5270int
e315cd28 5271qla24xx_configure_vhba(scsi_qla_host_t *vha)
2c3dfe3f
SJ		 5272{
5273 int rval = QLA_SUCCESS;
0b91d116 5274 int rval2;
2c3dfe3f 5275 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28
AC		 5276 struct qla_hw_data *ha = vha->hw;
5277 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
67c2e93a
AC		 5278 struct req_que *req;
5279 struct rsp_que *rsp;
2c3dfe3f 5280
e315cd28 5281 if (!vha->vp_idx)
2c3dfe3f
SJ		 5282 return -EINVAL;
5283
e315cd28 5284 rval = qla2x00_fw_ready(base_vha);
7163ea81 5285 if (ha->flags.cpu_affinity_enabled)
67c2e93a
AC		 5286 req = ha->req_q_map[0];
5287 else
5288 req = vha->req;
5289 rsp = req->rsp;
5290
2c3dfe3f 5291 if (rval == QLA_SUCCESS) {
e315cd28 5292 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
73208dfd 5293 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
2c3dfe3f
SJ		 5294 }
5295
e315cd28 5296 vha->flags.management_server_logged_in = 0;
2c3dfe3f
SJ		 5297
5298 /* Login to SNS first */
0b91d116
CD		 5299 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
5300 BIT_1);
5301 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
5302 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
5303 ql_dbg(ql_dbg_init, vha, 0x0120,
5304 "Failed SNS login: loop_id=%x, rval2=%d\n",
5305 NPH_SNS, rval2);
5306 else
5307 ql_dbg(ql_dbg_init, vha, 0x0103,
5308 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
5309 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
5310 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
2c3dfe3f
SJ		 5311 return (QLA_FUNCTION_FAILED);
5312 }
5313
e315cd28
AC		 5314 atomic_set(&vha->loop_down_timer, 0);
5315 atomic_set(&vha->loop_state, LOOP_UP);
5316 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5317 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5318 rval = qla2x00_loop_resync(base_vha);
2c3dfe3f
SJ		 5319
5320 return rval;
5321}
4d4df193
HK		 5322
5323/* 84XX Support **************************************************************/
5324
5325static LIST_HEAD(qla_cs84xx_list);
5326static DEFINE_MUTEX(qla_cs84xx_mutex);
5327
5328static struct qla_chip_state_84xx *
e315cd28 5329qla84xx_get_chip(struct scsi_qla_host *vha)
4d4df193
HK		 5330{
5331 struct qla_chip_state_84xx *cs84xx;
e315cd28 5332 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5333
5334 mutex_lock(&qla_cs84xx_mutex);
5335
5336 /* Find any shared 84xx chip. */
5337 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
5338 if (cs84xx->bus == ha->pdev->bus) {
5339 kref_get(&cs84xx->kref);
5340 goto done;
5341 }
5342 }
5343
5344 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
5345 if (!cs84xx)
5346 goto done;
5347
5348 kref_init(&cs84xx->kref);
5349 spin_lock_init(&cs84xx->access_lock);
5350 mutex_init(&cs84xx->fw_update_mutex);
5351 cs84xx->bus = ha->pdev->bus;
5352
5353 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
5354done:
5355 mutex_unlock(&qla_cs84xx_mutex);
5356 return cs84xx;
5357}
5358
5359static void
5360__qla84xx_chip_release(struct kref *kref)
5361{
5362 struct qla_chip_state_84xx *cs84xx =
5363 container_of(kref, struct qla_chip_state_84xx, kref);
5364
5365 mutex_lock(&qla_cs84xx_mutex);
5366 list_del(&cs84xx->list);
5367 mutex_unlock(&qla_cs84xx_mutex);
5368 kfree(cs84xx);
5369}
5370
5371void
e315cd28 5372qla84xx_put_chip(struct scsi_qla_host *vha)
4d4df193 5373{
e315cd28 5374 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5375 if (ha->cs84xx)
5376 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
5377}
5378
5379static int
e315cd28 5380qla84xx_init_chip(scsi_qla_host_t *vha)
4d4df193
HK		 5381{
5382 int rval;
5383 uint16_t status[2];
e315cd28 5384 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5385
5386 mutex_lock(&ha->cs84xx->fw_update_mutex);
5387
e315cd28 5388 rval = qla84xx_verify_chip(vha, status);
4d4df193
HK		 5389
5390 mutex_unlock(&ha->cs84xx->fw_update_mutex);
5391
5392 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
5393 QLA_SUCCESS;
5394}
3a03eb79
AV		 5395
5396/* 81XX Support **************************************************************/
5397
5398int
5399qla81xx_nvram_config(scsi_qla_host_t *vha)
5400{
5401 int rval;
5402 struct init_cb_81xx *icb;
5403 struct nvram_81xx *nv;
5404 uint32_t *dptr;
5405 uint8_t *dptr1, *dptr2;
5406 uint32_t chksum;
5407 uint16_t cnt;
5408 struct qla_hw_data *ha = vha->hw;
5409
5410 rval = QLA_SUCCESS;
5411 icb = (struct init_cb_81xx *)ha->init_cb;
5412 nv = ha->nvram;
5413
5414 /* Determine NVRAM starting address. */
5415 ha->nvram_size = sizeof(struct nvram_81xx);
3a03eb79 5416 ha->vpd_size = FA_NVRAM_VPD_SIZE;
3a03eb79
AV		 5417
5418 /* Get VPD data into cache */
5419 ha->vpd = ha->nvram + VPD_OFFSET;
3d79038f
AV		 5420 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
5421 ha->vpd_size);
3a03eb79
AV		 5422
5423 /* Get NVRAM data into cache and calculate checksum. */
3d79038f 5424 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
3a03eb79 5425 ha->nvram_size);
3d79038f 5426 dptr = (uint32_t *)nv;
3a03eb79
AV		 5427 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
5428 chksum += le32_to_cpu(*dptr++);
5429
7c3df132
SK		 5430 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
5431 "Contents of NVRAM:\n");
5432 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
5433 (uint8_t *)nv, ha->nvram_size);
3a03eb79
AV		 5434
5435 /* Bad NVRAM data, set defaults parameters. */
5436 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
5437 || nv->id[3] != ' ' ||
5438 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
5439 /* Reset NVRAM data. */
7c3df132 5440 ql_log(ql_log_info, vha, 0x0073,
9e336520 5441 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132 5442 "version=0x%x.\n", chksum, nv->id[0],
3a03eb79 5443 le16_to_cpu(nv->nvram_version));
7c3df132
SK		 5444 ql_log(ql_log_info, vha, 0x0074,
5445 "Falling back to functioning (yet invalid -- WWPN) "
5446 "defaults.\n");
3a03eb79
AV		 5447
5448 /*
5449 * Set default initialization control block.
5450 */
5451 memset(nv, 0, ha->nvram_size);
5452 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
5453 nv->version = __constant_cpu_to_le16(ICB_VERSION);
5454 nv->frame_payload_size = __constant_cpu_to_le16(2048);
5455 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5456 nv->exchange_count = __constant_cpu_to_le16(0);
5457 nv->port_name[0] = 0x21;
e5b68a61 5458 nv->port_name[1] = 0x00 + ha->port_no;
3a03eb79
AV		 5459 nv->port_name[2] = 0x00;
5460 nv->port_name[3] = 0xe0;
5461 nv->port_name[4] = 0x8b;
5462 nv->port_name[5] = 0x1c;
5463 nv->port_name[6] = 0x55;
5464 nv->port_name[7] = 0x86;
5465 nv->node_name[0] = 0x20;
5466 nv->node_name[1] = 0x00;
5467 nv->node_name[2] = 0x00;
5468 nv->node_name[3] = 0xe0;
5469 nv->node_name[4] = 0x8b;
5470 nv->node_name[5] = 0x1c;
5471 nv->node_name[6] = 0x55;
5472 nv->node_name[7] = 0x86;
5473 nv->login_retry_count = __constant_cpu_to_le16(8);
5474 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
5475 nv->login_timeout = __constant_cpu_to_le16(0);
5476 nv->firmware_options_1 =
5477 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
5478 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
5479 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
5480 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
5481 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
5482 nv->efi_parameters = __constant_cpu_to_le32(0);
5483 nv->reset_delay = 5;
5484 nv->max_luns_per_target = __constant_cpu_to_le16(128);
5485 nv->port_down_retry_count = __constant_cpu_to_le16(30);
6246b8a1 5486 nv->link_down_timeout = __constant_cpu_to_le16(180);
eeebcc92 5487 nv->enode_mac[0] = 0x00;
6246b8a1
GM		 5488 nv->enode_mac[1] = 0xC0;
5489 nv->enode_mac[2] = 0xDD;
3a03eb79
AV		 5490 nv->enode_mac[3] = 0x04;
5491 nv->enode_mac[4] = 0x05;
e5b68a61 5492 nv->enode_mac[5] = 0x06 + ha->port_no;
3a03eb79
AV		 5493
5494 rval = 1;
5495 }
5496
5497 /* Reset Initialization control block */
773120e4 5498 memset(icb, 0, ha->init_cb_size);
3a03eb79
AV		 5499
5500 /* Copy 1st segment. */
5501 dptr1 = (uint8_t *)icb;
5502 dptr2 = (uint8_t *)&nv->version;
5503 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
5504 while (cnt--)
5505 *dptr1++ = *dptr2++;
5506
5507 icb->login_retry_count = nv->login_retry_count;
5508
5509 /* Copy 2nd segment. */
5510 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
5511 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
5512 cnt = (uint8_t *)&icb->reserved_5 -
5513 (uint8_t *)&icb->interrupt_delay_timer;
5514 while (cnt--)
5515 *dptr1++ = *dptr2++;
5516
5517 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
5518 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
5519 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
69e5f1ea
AV		 5520 icb->enode_mac[0] = 0x00;
5521 icb->enode_mac[1] = 0xC0;
5522 icb->enode_mac[2] = 0xDD;
3a03eb79
AV		 5523 icb->enode_mac[3] = 0x04;
5524 icb->enode_mac[4] = 0x05;
e5b68a61 5525 icb->enode_mac[5] = 0x06 + ha->port_no;
3a03eb79
AV		 5526 }
5527
b64b0e8f
AV		 5528 /* Use extended-initialization control block. */
5529 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
5530
3a03eb79
AV		 5531 /*
5532 * Setup driver NVRAM options.
5533 */
5534 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
a9083016 5535 "QLE8XXX");
3a03eb79
AV		 5536
5537 /* Use alternate WWN? */
5538 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
5539 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
5540 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
5541 }
5542
5543 /* Prepare nodename */
5544 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
5545 /*
5546 * Firmware will apply the following mask if the nodename was
5547 * not provided.
5548 */
5549 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
5550 icb->node_name[0] &= 0xF0;
5551 }
5552
5553 /* Set host adapter parameters. */
5554 ha->flags.disable_risc_code_load = 0;
5555 ha->flags.enable_lip_reset = 0;
5556 ha->flags.enable_lip_full_login =
5557 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
5558 ha->flags.enable_target_reset =
5559 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
5560 ha->flags.enable_led_scheme = 0;
5561 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
5562
5563 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
5564 (BIT_6 | BIT_5 | BIT_4)) >> 4;
5565
5566 /* save HBA serial number */
5567 ha->serial0 = icb->port_name[5];
5568 ha->serial1 = icb->port_name[6];
5569 ha->serial2 = icb->port_name[7];
5570 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
5571 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
5572
5573 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5574
5575 ha->retry_count = le16_to_cpu(nv->login_retry_count);
5576
5577 /* Set minimum login_timeout to 4 seconds. */
5578 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
5579 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
5580 if (le16_to_cpu(nv->login_timeout) < 4)
5581 nv->login_timeout = __constant_cpu_to_le16(4);
5582 ha->login_timeout = le16_to_cpu(nv->login_timeout);
5583 icb->login_timeout = nv->login_timeout;
5584
5585 /* Set minimum RATOV to 100 tenths of a second. */
5586 ha->r_a_tov = 100;
5587
5588 ha->loop_reset_delay = nv->reset_delay;
5589
5590 /* Link Down Timeout = 0:
5591 *
5592 * When Port Down timer expires we will start returning
5593 * I/O's to OS with "DID_NO_CONNECT".
5594 *
5595 * Link Down Timeout != 0:
5596 *
5597 * The driver waits for the link to come up after link down
5598 * before returning I/Os to OS with "DID_NO_CONNECT".
5599 */
5600 if (le16_to_cpu(nv->link_down_timeout) == 0) {
5601 ha->loop_down_abort_time =
5602 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
5603 } else {
5604 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
5605 ha->loop_down_abort_time =
5606 (LOOP_DOWN_TIME - ha->link_down_timeout);
5607 }
5608
5609 /* Need enough time to try and get the port back. */
5610 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
5611 if (qlport_down_retry)
5612 ha->port_down_retry_count = qlport_down_retry;
5613
5614 /* Set login_retry_count */
5615 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
5616 if (ha->port_down_retry_count ==
5617 le16_to_cpu(nv->port_down_retry_count) &&
5618 ha->port_down_retry_count > 3)
5619 ha->login_retry_count = ha->port_down_retry_count;
5620 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
5621 ha->login_retry_count = ha->port_down_retry_count;
5622 if (ql2xloginretrycount)
5623 ha->login_retry_count = ql2xloginretrycount;
5624
6246b8a1
GM		 5625 /* if not running MSI-X we need handshaking on interrupts */
5626 if (!vha->hw->flags.msix_enabled && IS_QLA83XX(ha))
5627 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_22);
5628
3a03eb79
AV		 5629 /* Enable ZIO. */
5630 if (!vha->flags.init_done) {
5631 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
5632 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
5633 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
5634 le16_to_cpu(icb->interrupt_delay_timer): 2;
5635 }
5636 icb->firmware_options_2 &= __constant_cpu_to_le32(
5637 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
5638 vha->flags.process_response_queue = 0;
5639 if (ha->zio_mode != QLA_ZIO_DISABLED) {
5640 ha->zio_mode = QLA_ZIO_MODE_6;
5641
7c3df132 5642 ql_log(ql_log_info, vha, 0x0075,
3a03eb79 5643 "ZIO mode %d enabled; timer delay (%d us).\n",
7c3df132
SK		 5644 ha->zio_mode,
5645 ha->zio_timer * 100);
3a03eb79
AV		 5646
5647 icb->firmware_options_2 |= cpu_to_le32(
5648 (uint32_t)ha->zio_mode);
5649 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
5650 vha->flags.process_response_queue = 1;
5651 }
5652
5653 if (rval) {
7c3df132
SK		 5654 ql_log(ql_log_warn, vha, 0x0076,
5655 "NVRAM configuration failed.\n");
3a03eb79
AV		 5656 }
5657 return (rval);
5658}
5659
a9083016
GM		 5660int
5661qla82xx_restart_isp(scsi_qla_host_t *vha)
5662{
5663 int status, rval;
5664 uint32_t wait_time;
5665 struct qla_hw_data *ha = vha->hw;
5666 struct req_que *req = ha->req_q_map[0];
5667 struct rsp_que *rsp = ha->rsp_q_map[0];
5668 struct scsi_qla_host *vp;
feafb7b1 5669 unsigned long flags;
a9083016
GM		 5670
5671 status = qla2x00_init_rings(vha);
5672 if (!status) {
5673 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5674 ha->flags.chip_reset_done = 1;
5675
5676 status = qla2x00_fw_ready(vha);
5677 if (!status) {
7c3df132
SK		 5678 ql_log(ql_log_info, vha, 0x803c,
5679 "Start configure loop, status =%d.\n", status);
a9083016
GM		 5680
5681 /* Issue a marker after FW becomes ready. */
5682 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
5683
5684 vha->flags.online = 1;
5685 /* Wait at most MAX_TARGET RSCNs for a stable link. */
5686 wait_time = 256;
5687 do {
5688 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5689 qla2x00_configure_loop(vha);
5690 wait_time--;
5691 } while (!atomic_read(&vha->loop_down_timer) &&
5692 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) &&
5693 wait_time &&
5694 (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)));
5695 }
5696
5697 /* if no cable then assume it's good */
5698 if ((vha->device_flags & DFLG_NO_CABLE))
5699 status = 0;
5700
cfb0919c 5701 ql_log(ql_log_info, vha, 0x8000,
7c3df132 5702 "Configure loop done, status = 0x%x.\n", status);
a9083016
GM		 5703 }
5704
5705 if (!status) {
5706 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5707
5708 if (!atomic_read(&vha->loop_down_timer)) {
5709 /*
5710 * Issue marker command only when we are going
5711 * to start the I/O .
5712 */
5713 vha->marker_needed = 1;
5714 }
5715
5716 vha->flags.online = 1;
5717
5718 ha->isp_ops->enable_intrs(ha);
5719
5720 ha->isp_abort_cnt = 0;
5721 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
5722
53296788 5723 /* Update the firmware version */
3173167f 5724 status = qla82xx_check_md_needed(vha);
53296788 5725
a9083016
GM		 5726 if (ha->fce) {
5727 ha->flags.fce_enabled = 1;
5728 memset(ha->fce, 0,
5729 fce_calc_size(ha->fce_bufs));
5730 rval = qla2x00_enable_fce_trace(vha,
5731 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
5732 &ha->fce_bufs);
5733 if (rval) {
cfb0919c 5734 ql_log(ql_log_warn, vha, 0x8001,
7c3df132
SK		 5735 "Unable to reinitialize FCE (%d).\n",
5736 rval);
a9083016
GM		 5737 ha->flags.fce_enabled = 0;
5738 }
5739 }
5740
5741 if (ha->eft) {
5742 memset(ha->eft, 0, EFT_SIZE);
5743 rval = qla2x00_enable_eft_trace(vha,
5744 ha->eft_dma, EFT_NUM_BUFFERS);
5745 if (rval) {
cfb0919c 5746 ql_log(ql_log_warn, vha, 0x8010,
7c3df132
SK		 5747 "Unable to reinitialize EFT (%d).\n",
5748 rval);
a9083016
GM		 5749 }
5750 }
a9083016
GM		 5751 }
5752
5753 if (!status) {
cfb0919c 5754 ql_dbg(ql_dbg_taskm, vha, 0x8011,
7c3df132 5755 "qla82xx_restart_isp succeeded.\n");
feafb7b1
AE		 5756
5757 spin_lock_irqsave(&ha->vport_slock, flags);
5758 list_for_each_entry(vp, &ha->vp_list, list) {
5759 if (vp->vp_idx) {
5760 atomic_inc(&vp->vref_count);
5761 spin_unlock_irqrestore(&ha->vport_slock, flags);
5762
a9083016 5763 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 5764
5765 spin_lock_irqsave(&ha->vport_slock, flags);
5766 atomic_dec(&vp->vref_count);
5767 }
a9083016 5768 }
feafb7b1
AE		 5769 spin_unlock_irqrestore(&ha->vport_slock, flags);
5770
a9083016 5771 } else {
cfb0919c 5772 ql_log(ql_log_warn, vha, 0x8016,
7c3df132 5773 "qla82xx_restart_isp **** FAILED ****.\n");
a9083016
GM		 5774 }
5775
5776 return status;
5777}
5778
3a03eb79 5779void
ae97c91e 5780qla81xx_update_fw_options(scsi_qla_host_t *vha)
3a03eb79 5781{
ae97c91e
AV		 5782 struct qla_hw_data *ha = vha->hw;
5783
5784 if (!ql2xetsenable)
5785 return;
5786
5787 /* Enable ETS Burst. */
5788 memset(ha->fw_options, 0, sizeof(ha->fw_options));
5789 ha->fw_options[2] |= BIT_9;
5790 qla2x00_set_fw_options(vha, ha->fw_options);
3a03eb79 5791}
09ff701a
SR		 5792
5793/*
5794 * qla24xx_get_fcp_prio
5795 * Gets the fcp cmd priority value for the logged in port.
5796 * Looks for a match of the port descriptors within
5797 * each of the fcp prio config entries. If a match is found,
5798 * the tag (priority) value is returned.
5799 *
5800 * Input:
21090cbe 5801 * vha = scsi host structure pointer.
09ff701a
SR		 5802 * fcport = port structure pointer.
5803 *
5804 * Return:
6c452a45 5805 * non-zero (if found)
f28a0a96 5806 * -1 (if not found)
09ff701a
SR		 5807 *
5808 * Context:
5809 * Kernel context
5810 */
f28a0a96 5811static int
09ff701a
SR		 5812qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
5813{
5814 int i, entries;
5815 uint8_t pid_match, wwn_match;
f28a0a96 5816 int priority;
09ff701a
SR		 5817 uint32_t pid1, pid2;
5818 uint64_t wwn1, wwn2;
5819 struct qla_fcp_prio_entry *pri_entry;
5820 struct qla_hw_data *ha = vha->hw;
5821
5822 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
f28a0a96 5823 return -1;
09ff701a 5824
f28a0a96 5825 priority = -1;
09ff701a
SR		 5826 entries = ha->fcp_prio_cfg->num_entries;
5827 pri_entry = &ha->fcp_prio_cfg->entry[0];
5828
5829 for (i = 0; i < entries; i++) {
5830 pid_match = wwn_match = 0;
5831
5832 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
5833 pri_entry++;
5834 continue;
5835 }
5836
5837 /* check source pid for a match */
5838 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
5839 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
5840 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
5841 if (pid1 == INVALID_PORT_ID)
5842 pid_match++;
5843 else if (pid1 == pid2)
5844 pid_match++;
5845 }
5846
5847 /* check destination pid for a match */
5848 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
5849 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
5850 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
5851 if (pid1 == INVALID_PORT_ID)
5852 pid_match++;
5853 else if (pid1 == pid2)
5854 pid_match++;
5855 }
5856
5857 /* check source WWN for a match */
5858 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
5859 wwn1 = wwn_to_u64(vha->port_name);
5860 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
5861 if (wwn2 == (uint64_t)-1)
5862 wwn_match++;
5863 else if (wwn1 == wwn2)
5864 wwn_match++;
5865 }
5866
5867 /* check destination WWN for a match */
5868 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
5869 wwn1 = wwn_to_u64(fcport->port_name);
5870 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
5871 if (wwn2 == (uint64_t)-1)
5872 wwn_match++;
5873 else if (wwn1 == wwn2)
5874 wwn_match++;
5875 }
5876
5877 if (pid_match == 2 || wwn_match == 2) {
5878 /* Found a matching entry */
5879 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
5880 priority = pri_entry->tag;
5881 break;
5882 }
5883
5884 pri_entry++;
5885 }
5886
5887 return priority;
5888}
5889
5890/*
5891 * qla24xx_update_fcport_fcp_prio
5892 * Activates fcp priority for the logged in fc port
5893 *
5894 * Input:
21090cbe 5895 * vha = scsi host structure pointer.
09ff701a
SR		 5896 * fcp = port structure pointer.
5897 *
5898 * Return:
5899 * QLA_SUCCESS or QLA_FUNCTION_FAILED
5900 *
5901 * Context:
5902 * Kernel context.
5903 */
5904int
21090cbe 5905qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
09ff701a
SR		 5906{
5907 int ret;
f28a0a96 5908 int priority;
09ff701a
SR		 5909 uint16_t mb[5];
5910
21090cbe
MI		 5911 if (fcport->port_type != FCT_TARGET ||
5912 fcport->loop_id == FC_NO_LOOP_ID)
09ff701a
SR		 5913 return QLA_FUNCTION_FAILED;
5914
21090cbe 5915 priority = qla24xx_get_fcp_prio(vha, fcport);
f28a0a96
AV		 5916 if (priority < 0)
5917 return QLA_FUNCTION_FAILED;
5918
a00f6296
SK		 5919 if (IS_QLA82XX(vha->hw)) {
5920 fcport->fcp_prio = priority & 0xf;
5921 return QLA_SUCCESS;
5922 }
5923
21090cbe 5924 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
cfb0919c
CD		 5925 if (ret == QLA_SUCCESS) {
5926 if (fcport->fcp_prio != priority)
5927 ql_dbg(ql_dbg_user, vha, 0x709e,
5928 "Updated FCP_CMND priority - value=%d loop_id=%d "
5929 "port_id=%02x%02x%02x.\n", priority,
5930 fcport->loop_id, fcport->d_id.b.domain,
5931 fcport->d_id.b.area, fcport->d_id.b.al_pa);
a00f6296 5932 fcport->fcp_prio = priority & 0xf;
cfb0919c 5933 } else
7c3df132 5934 ql_dbg(ql_dbg_user, vha, 0x704f,
cfb0919c
CD		 5935 "Unable to update FCP_CMND priority - ret=0x%x for "
5936 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
5937 fcport->d_id.b.domain, fcport->d_id.b.area,
5938 fcport->d_id.b.al_pa);
09ff701a
SR		 5939 return ret;
5940}
5941
5942/*
5943 * qla24xx_update_all_fcp_prio
5944 * Activates fcp priority for all the logged in ports
5945 *
5946 * Input:
5947 * ha = adapter block pointer.
5948 *
5949 * Return:
5950 * QLA_SUCCESS or QLA_FUNCTION_FAILED
5951 *
5952 * Context:
5953 * Kernel context.
5954 */
5955int
5956qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
5957{
5958 int ret;
5959 fc_port_t *fcport;
5960
5961 ret = QLA_FUNCTION_FAILED;
5962 /* We need to set priority for all logged in ports */
5963 list_for_each_entry(fcport, &vha->vp_fcports, list)
5964 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
5965
5966 return ret;
5967}
Linux kernel - Deliverables
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