Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
fa90c54f | 2 | * QLogic Fibre Channel HBA Driver |
bd21eaf9 | 3 | * Copyright (c) 2003-2014 QLogic Corporation |
1da177e4 | 4 | * |
fa90c54f | 5 | * See LICENSE.qla2xxx for copyright and licensing details. |
1da177e4 LT |
6 | */ |
7 | #include "qla_def.h" | |
73208dfd | 8 | #include "qla_gbl.h" |
1da177e4 LT |
9 | |
10 | #include <linux/delay.h> | |
5a0e3ad6 | 11 | #include <linux/slab.h> |
0107109e | 12 | #include <linux/vmalloc.h> |
1da177e4 LT |
13 | |
14 | #include "qla_devtbl.h" | |
15 | ||
4e08df3f DM |
16 | #ifdef CONFIG_SPARC |
17 | #include <asm/prom.h> | |
4e08df3f DM |
18 | #endif |
19 | ||
2d70c103 NB |
20 | #include <target/target_core_base.h> |
21 | #include "qla_target.h" | |
22 | ||
1da177e4 LT |
23 | /* |
24 | * QLogic ISP2x00 Hardware Support Function Prototypes. | |
25 | */ | |
1da177e4 | 26 | static int qla2x00_isp_firmware(scsi_qla_host_t *); |
1da177e4 | 27 | static int qla2x00_setup_chip(scsi_qla_host_t *); |
1da177e4 LT |
28 | static int qla2x00_fw_ready(scsi_qla_host_t *); |
29 | static int qla2x00_configure_hba(scsi_qla_host_t *); | |
1da177e4 LT |
30 | static int qla2x00_configure_loop(scsi_qla_host_t *); |
31 | static int qla2x00_configure_local_loop(scsi_qla_host_t *); | |
1da177e4 LT |
32 | static int qla2x00_configure_fabric(scsi_qla_host_t *); |
33 | static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *); | |
1da177e4 LT |
34 | static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *, |
35 | uint16_t *); | |
1da177e4 LT |
36 | |
37 | static int qla2x00_restart_isp(scsi_qla_host_t *); | |
1da177e4 | 38 | |
4d4df193 HK |
39 | static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *); |
40 | static int qla84xx_init_chip(scsi_qla_host_t *); | |
73208dfd | 41 | static int qla25xx_init_queues(struct qla_hw_data *); |
4d4df193 | 42 | |
ac280b67 AV |
43 | /* SRB Extensions ---------------------------------------------------------- */ |
44 | ||
9ba56b95 GM |
45 | void |
46 | qla2x00_sp_timeout(unsigned long __data) | |
ac280b67 AV |
47 | { |
48 | srb_t *sp = (srb_t *)__data; | |
4916392b | 49 | struct srb_iocb *iocb; |
ac280b67 AV |
50 | fc_port_t *fcport = sp->fcport; |
51 | struct qla_hw_data *ha = fcport->vha->hw; | |
52 | struct req_que *req; | |
53 | unsigned long flags; | |
54 | ||
55 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
56 | req = ha->req_q_map[0]; | |
57 | req->outstanding_cmds[sp->handle] = NULL; | |
9ba56b95 | 58 | iocb = &sp->u.iocb_cmd; |
4916392b | 59 | iocb->timeout(sp); |
9ba56b95 | 60 | sp->free(fcport->vha, sp); |
6ac52608 | 61 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
ac280b67 AV |
62 | } |
63 | ||
9ba56b95 GM |
64 | void |
65 | qla2x00_sp_free(void *data, void *ptr) | |
ac280b67 | 66 | { |
9ba56b95 GM |
67 | srb_t *sp = (srb_t *)ptr; |
68 | struct srb_iocb *iocb = &sp->u.iocb_cmd; | |
69 | struct scsi_qla_host *vha = (scsi_qla_host_t *)data; | |
ac280b67 | 70 | |
4d97cc53 | 71 | del_timer(&iocb->timer); |
b00ee7d7 | 72 | qla2x00_rel_sp(vha, sp); |
ac280b67 AV |
73 | } |
74 | ||
ac280b67 AV |
75 | /* Asynchronous Login/Logout Routines -------------------------------------- */ |
76 | ||
a9b6f722 | 77 | unsigned long |
5b91490e AV |
78 | qla2x00_get_async_timeout(struct scsi_qla_host *vha) |
79 | { | |
80 | unsigned long tmo; | |
81 | struct qla_hw_data *ha = vha->hw; | |
82 | ||
83 | /* Firmware should use switch negotiated r_a_tov for timeout. */ | |
84 | tmo = ha->r_a_tov / 10 * 2; | |
8ae6d9c7 GM |
85 | if (IS_QLAFX00(ha)) { |
86 | tmo = FX00_DEF_RATOV * 2; | |
87 | } else if (!IS_FWI2_CAPABLE(ha)) { | |
5b91490e AV |
88 | /* |
89 | * Except for earlier ISPs where the timeout is seeded from the | |
90 | * initialization control block. | |
91 | */ | |
92 | tmo = ha->login_timeout; | |
93 | } | |
94 | return tmo; | |
95 | } | |
ac280b67 AV |
96 | |
97 | static void | |
9ba56b95 | 98 | qla2x00_async_iocb_timeout(void *data) |
ac280b67 | 99 | { |
9ba56b95 | 100 | srb_t *sp = (srb_t *)data; |
ac280b67 | 101 | fc_port_t *fcport = sp->fcport; |
ac280b67 | 102 | |
7c3df132 | 103 | ql_dbg(ql_dbg_disc, fcport->vha, 0x2071, |
cfb0919c | 104 | "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n", |
9ba56b95 | 105 | sp->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area, |
7c3df132 | 106 | fcport->d_id.b.al_pa); |
ac280b67 | 107 | |
5ff1d584 | 108 | fcport->flags &= ~FCF_ASYNC_SENT; |
9ba56b95 GM |
109 | if (sp->type == SRB_LOGIN_CMD) { |
110 | struct srb_iocb *lio = &sp->u.iocb_cmd; | |
ac280b67 | 111 | qla2x00_post_async_logout_work(fcport->vha, fcport, NULL); |
6ac52608 AV |
112 | /* Retry as needed. */ |
113 | lio->u.logio.data[0] = MBS_COMMAND_ERROR; | |
114 | lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ? | |
115 | QLA_LOGIO_LOGIN_RETRIED : 0; | |
116 | qla2x00_post_async_login_done_work(fcport->vha, fcport, | |
117 | lio->u.logio.data); | |
118 | } | |
ac280b67 AV |
119 | } |
120 | ||
99b0bec7 | 121 | static void |
9ba56b95 | 122 | qla2x00_async_login_sp_done(void *data, void *ptr, int res) |
99b0bec7 | 123 | { |
9ba56b95 GM |
124 | srb_t *sp = (srb_t *)ptr; |
125 | struct srb_iocb *lio = &sp->u.iocb_cmd; | |
126 | struct scsi_qla_host *vha = (scsi_qla_host_t *)data; | |
127 | ||
128 | if (!test_bit(UNLOADING, &vha->dpc_flags)) | |
129 | qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport, | |
130 | lio->u.logio.data); | |
131 | sp->free(sp->fcport->vha, sp); | |
99b0bec7 AV |
132 | } |
133 | ||
ac280b67 AV |
134 | int |
135 | qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport, | |
136 | uint16_t *data) | |
137 | { | |
ac280b67 | 138 | srb_t *sp; |
4916392b | 139 | struct srb_iocb *lio; |
ac280b67 AV |
140 | int rval; |
141 | ||
142 | rval = QLA_FUNCTION_FAILED; | |
9ba56b95 | 143 | sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); |
ac280b67 AV |
144 | if (!sp) |
145 | goto done; | |
146 | ||
9ba56b95 GM |
147 | sp->type = SRB_LOGIN_CMD; |
148 | sp->name = "login"; | |
149 | qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); | |
150 | ||
151 | lio = &sp->u.iocb_cmd; | |
3822263e | 152 | lio->timeout = qla2x00_async_iocb_timeout; |
9ba56b95 | 153 | sp->done = qla2x00_async_login_sp_done; |
4916392b | 154 | lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI; |
ac280b67 | 155 | if (data[1] & QLA_LOGIO_LOGIN_RETRIED) |
4916392b | 156 | lio->u.logio.flags |= SRB_LOGIN_RETRIED; |
ac280b67 AV |
157 | rval = qla2x00_start_sp(sp); |
158 | if (rval != QLA_SUCCESS) | |
159 | goto done_free_sp; | |
160 | ||
7c3df132 | 161 | ql_dbg(ql_dbg_disc, vha, 0x2072, |
cfb0919c CD |
162 | "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x " |
163 | "retries=%d.\n", sp->handle, fcport->loop_id, | |
164 | fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa, | |
165 | fcport->login_retry); | |
ac280b67 AV |
166 | return rval; |
167 | ||
168 | done_free_sp: | |
9ba56b95 | 169 | sp->free(fcport->vha, sp); |
ac280b67 AV |
170 | done: |
171 | return rval; | |
172 | } | |
173 | ||
99b0bec7 | 174 | static void |
9ba56b95 | 175 | qla2x00_async_logout_sp_done(void *data, void *ptr, int res) |
99b0bec7 | 176 | { |
9ba56b95 GM |
177 | srb_t *sp = (srb_t *)ptr; |
178 | struct srb_iocb *lio = &sp->u.iocb_cmd; | |
179 | struct scsi_qla_host *vha = (scsi_qla_host_t *)data; | |
180 | ||
181 | if (!test_bit(UNLOADING, &vha->dpc_flags)) | |
182 | qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport, | |
183 | lio->u.logio.data); | |
184 | sp->free(sp->fcport->vha, sp); | |
99b0bec7 AV |
185 | } |
186 | ||
ac280b67 AV |
187 | int |
188 | qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport) | |
189 | { | |
ac280b67 | 190 | srb_t *sp; |
4916392b | 191 | struct srb_iocb *lio; |
ac280b67 AV |
192 | int rval; |
193 | ||
194 | rval = QLA_FUNCTION_FAILED; | |
9ba56b95 | 195 | sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); |
ac280b67 AV |
196 | if (!sp) |
197 | goto done; | |
198 | ||
9ba56b95 GM |
199 | sp->type = SRB_LOGOUT_CMD; |
200 | sp->name = "logout"; | |
201 | qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); | |
202 | ||
203 | lio = &sp->u.iocb_cmd; | |
3822263e | 204 | lio->timeout = qla2x00_async_iocb_timeout; |
9ba56b95 | 205 | sp->done = qla2x00_async_logout_sp_done; |
ac280b67 AV |
206 | rval = qla2x00_start_sp(sp); |
207 | if (rval != QLA_SUCCESS) | |
208 | goto done_free_sp; | |
209 | ||
7c3df132 | 210 | ql_dbg(ql_dbg_disc, vha, 0x2070, |
cfb0919c CD |
211 | "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n", |
212 | sp->handle, fcport->loop_id, fcport->d_id.b.domain, | |
213 | fcport->d_id.b.area, fcport->d_id.b.al_pa); | |
ac280b67 AV |
214 | return rval; |
215 | ||
216 | done_free_sp: | |
9ba56b95 | 217 | sp->free(fcport->vha, sp); |
ac280b67 AV |
218 | done: |
219 | return rval; | |
220 | } | |
221 | ||
5ff1d584 | 222 | static void |
9ba56b95 | 223 | qla2x00_async_adisc_sp_done(void *data, void *ptr, int res) |
5ff1d584 | 224 | { |
9ba56b95 GM |
225 | srb_t *sp = (srb_t *)ptr; |
226 | struct srb_iocb *lio = &sp->u.iocb_cmd; | |
227 | struct scsi_qla_host *vha = (scsi_qla_host_t *)data; | |
228 | ||
229 | if (!test_bit(UNLOADING, &vha->dpc_flags)) | |
230 | qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport, | |
231 | lio->u.logio.data); | |
232 | sp->free(sp->fcport->vha, sp); | |
5ff1d584 AV |
233 | } |
234 | ||
235 | int | |
236 | qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport, | |
237 | uint16_t *data) | |
238 | { | |
5ff1d584 | 239 | srb_t *sp; |
4916392b | 240 | struct srb_iocb *lio; |
5ff1d584 AV |
241 | int rval; |
242 | ||
243 | rval = QLA_FUNCTION_FAILED; | |
9ba56b95 | 244 | sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); |
5ff1d584 AV |
245 | if (!sp) |
246 | goto done; | |
247 | ||
9ba56b95 GM |
248 | sp->type = SRB_ADISC_CMD; |
249 | sp->name = "adisc"; | |
250 | qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); | |
251 | ||
252 | lio = &sp->u.iocb_cmd; | |
3822263e | 253 | lio->timeout = qla2x00_async_iocb_timeout; |
9ba56b95 | 254 | sp->done = qla2x00_async_adisc_sp_done; |
5ff1d584 | 255 | if (data[1] & QLA_LOGIO_LOGIN_RETRIED) |
4916392b | 256 | lio->u.logio.flags |= SRB_LOGIN_RETRIED; |
5ff1d584 AV |
257 | rval = qla2x00_start_sp(sp); |
258 | if (rval != QLA_SUCCESS) | |
259 | goto done_free_sp; | |
260 | ||
7c3df132 | 261 | ql_dbg(ql_dbg_disc, vha, 0x206f, |
cfb0919c CD |
262 | "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n", |
263 | sp->handle, fcport->loop_id, fcport->d_id.b.domain, | |
264 | fcport->d_id.b.area, fcport->d_id.b.al_pa); | |
5ff1d584 AV |
265 | return rval; |
266 | ||
267 | done_free_sp: | |
9ba56b95 | 268 | sp->free(fcport->vha, sp); |
5ff1d584 AV |
269 | done: |
270 | return rval; | |
271 | } | |
272 | ||
3822263e | 273 | static void |
faef62d1 | 274 | qla2x00_tmf_iocb_timeout(void *data) |
3822263e | 275 | { |
faef62d1 AB |
276 | srb_t *sp = (srb_t *)data; |
277 | struct srb_iocb *tmf = &sp->u.iocb_cmd; | |
3822263e | 278 | |
faef62d1 AB |
279 | tmf->u.tmf.comp_status = CS_TIMEOUT; |
280 | complete(&tmf->u.tmf.comp); | |
281 | } | |
9ba56b95 | 282 | |
faef62d1 AB |
283 | static void |
284 | qla2x00_tmf_sp_done(void *data, void *ptr, int res) | |
285 | { | |
286 | srb_t *sp = (srb_t *)ptr; | |
287 | struct srb_iocb *tmf = &sp->u.iocb_cmd; | |
288 | complete(&tmf->u.tmf.comp); | |
3822263e MI |
289 | } |
290 | ||
291 | int | |
faef62d1 | 292 | qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun, |
3822263e MI |
293 | uint32_t tag) |
294 | { | |
295 | struct scsi_qla_host *vha = fcport->vha; | |
faef62d1 | 296 | struct srb_iocb *tm_iocb; |
3822263e | 297 | srb_t *sp; |
faef62d1 | 298 | int rval = QLA_FUNCTION_FAILED; |
3822263e | 299 | |
9ba56b95 | 300 | sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); |
3822263e MI |
301 | if (!sp) |
302 | goto done; | |
303 | ||
faef62d1 | 304 | tm_iocb = &sp->u.iocb_cmd; |
9ba56b95 GM |
305 | sp->type = SRB_TM_CMD; |
306 | sp->name = "tmf"; | |
faef62d1 AB |
307 | qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha)); |
308 | tm_iocb->u.tmf.flags = flags; | |
309 | tm_iocb->u.tmf.lun = lun; | |
310 | tm_iocb->u.tmf.data = tag; | |
311 | sp->done = qla2x00_tmf_sp_done; | |
312 | tm_iocb->timeout = qla2x00_tmf_iocb_timeout; | |
313 | init_completion(&tm_iocb->u.tmf.comp); | |
3822263e MI |
314 | |
315 | rval = qla2x00_start_sp(sp); | |
316 | if (rval != QLA_SUCCESS) | |
317 | goto done_free_sp; | |
318 | ||
7c3df132 | 319 | ql_dbg(ql_dbg_taskm, vha, 0x802f, |
cfb0919c CD |
320 | "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n", |
321 | sp->handle, fcport->loop_id, fcport->d_id.b.domain, | |
322 | fcport->d_id.b.area, fcport->d_id.b.al_pa); | |
faef62d1 AB |
323 | |
324 | wait_for_completion(&tm_iocb->u.tmf.comp); | |
325 | ||
326 | rval = tm_iocb->u.tmf.comp_status == CS_COMPLETE ? | |
327 | QLA_SUCCESS : QLA_FUNCTION_FAILED; | |
328 | ||
329 | if ((rval != QLA_SUCCESS) || tm_iocb->u.tmf.data) { | |
330 | ql_dbg(ql_dbg_taskm, vha, 0x8030, | |
331 | "TM IOCB failed (%x).\n", rval); | |
332 | } | |
333 | ||
334 | if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) { | |
335 | flags = tm_iocb->u.tmf.flags; | |
336 | lun = (uint16_t)tm_iocb->u.tmf.lun; | |
337 | ||
338 | /* Issue Marker IOCB */ | |
339 | qla2x00_marker(vha, vha->hw->req_q_map[0], | |
340 | vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun, | |
341 | flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID); | |
342 | } | |
3822263e MI |
343 | |
344 | done_free_sp: | |
faef62d1 | 345 | sp->free(vha, sp); |
3822263e MI |
346 | done: |
347 | return rval; | |
348 | } | |
349 | ||
4440e46d AB |
350 | static void |
351 | qla24xx_abort_iocb_timeout(void *data) | |
352 | { | |
353 | srb_t *sp = (srb_t *)data; | |
354 | struct srb_iocb *abt = &sp->u.iocb_cmd; | |
355 | ||
356 | abt->u.abt.comp_status = CS_TIMEOUT; | |
357 | complete(&abt->u.abt.comp); | |
358 | } | |
359 | ||
360 | static void | |
361 | qla24xx_abort_sp_done(void *data, void *ptr, int res) | |
362 | { | |
363 | srb_t *sp = (srb_t *)ptr; | |
364 | struct srb_iocb *abt = &sp->u.iocb_cmd; | |
365 | ||
366 | complete(&abt->u.abt.comp); | |
367 | } | |
368 | ||
369 | static int | |
370 | qla24xx_async_abort_cmd(srb_t *cmd_sp) | |
371 | { | |
372 | scsi_qla_host_t *vha = cmd_sp->fcport->vha; | |
373 | fc_port_t *fcport = cmd_sp->fcport; | |
374 | struct srb_iocb *abt_iocb; | |
375 | srb_t *sp; | |
376 | int rval = QLA_FUNCTION_FAILED; | |
377 | ||
378 | sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); | |
379 | if (!sp) | |
380 | goto done; | |
381 | ||
382 | abt_iocb = &sp->u.iocb_cmd; | |
383 | sp->type = SRB_ABT_CMD; | |
384 | sp->name = "abort"; | |
385 | qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha)); | |
386 | abt_iocb->u.abt.cmd_hndl = cmd_sp->handle; | |
387 | sp->done = qla24xx_abort_sp_done; | |
388 | abt_iocb->timeout = qla24xx_abort_iocb_timeout; | |
389 | init_completion(&abt_iocb->u.abt.comp); | |
390 | ||
391 | rval = qla2x00_start_sp(sp); | |
392 | if (rval != QLA_SUCCESS) | |
393 | goto done_free_sp; | |
394 | ||
395 | ql_dbg(ql_dbg_async, vha, 0x507c, | |
396 | "Abort command issued - hdl=%x, target_id=%x\n", | |
397 | cmd_sp->handle, fcport->tgt_id); | |
398 | ||
399 | wait_for_completion(&abt_iocb->u.abt.comp); | |
400 | ||
401 | rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ? | |
402 | QLA_SUCCESS : QLA_FUNCTION_FAILED; | |
403 | ||
404 | done_free_sp: | |
405 | sp->free(vha, sp); | |
406 | done: | |
407 | return rval; | |
408 | } | |
409 | ||
410 | int | |
411 | qla24xx_async_abort_command(srb_t *sp) | |
412 | { | |
413 | unsigned long flags = 0; | |
414 | ||
415 | uint32_t handle; | |
416 | fc_port_t *fcport = sp->fcport; | |
417 | struct scsi_qla_host *vha = fcport->vha; | |
418 | struct qla_hw_data *ha = vha->hw; | |
419 | struct req_que *req = vha->req; | |
420 | ||
421 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
422 | for (handle = 1; handle < req->num_outstanding_cmds; handle++) { | |
423 | if (req->outstanding_cmds[handle] == sp) | |
424 | break; | |
425 | } | |
426 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
427 | if (handle == req->num_outstanding_cmds) { | |
428 | /* Command not found. */ | |
429 | return QLA_FUNCTION_FAILED; | |
430 | } | |
431 | if (sp->type == SRB_FXIOCB_DCMD) | |
432 | return qlafx00_fx_disc(vha, &vha->hw->mr.fcport, | |
433 | FXDISC_ABORT_IOCTL); | |
434 | ||
435 | return qla24xx_async_abort_cmd(sp); | |
436 | } | |
437 | ||
4916392b | 438 | void |
ac280b67 AV |
439 | qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport, |
440 | uint16_t *data) | |
441 | { | |
442 | int rval; | |
ac280b67 AV |
443 | |
444 | switch (data[0]) { | |
445 | case MBS_COMMAND_COMPLETE: | |
a4f92a32 AV |
446 | /* |
447 | * Driver must validate login state - If PRLI not complete, | |
448 | * force a relogin attempt via implicit LOGO, PLOGI, and PRLI | |
449 | * requests. | |
450 | */ | |
451 | rval = qla2x00_get_port_database(vha, fcport, 0); | |
0eba25df AE |
452 | if (rval == QLA_NOT_LOGGED_IN) { |
453 | fcport->flags &= ~FCF_ASYNC_SENT; | |
454 | fcport->flags |= FCF_LOGIN_NEEDED; | |
455 | set_bit(RELOGIN_NEEDED, &vha->dpc_flags); | |
456 | break; | |
457 | } | |
458 | ||
a4f92a32 AV |
459 | if (rval != QLA_SUCCESS) { |
460 | qla2x00_post_async_logout_work(vha, fcport, NULL); | |
461 | qla2x00_post_async_login_work(vha, fcport, NULL); | |
462 | break; | |
463 | } | |
99b0bec7 | 464 | if (fcport->flags & FCF_FCP2_DEVICE) { |
5ff1d584 AV |
465 | qla2x00_post_async_adisc_work(vha, fcport, data); |
466 | break; | |
99b0bec7 AV |
467 | } |
468 | qla2x00_update_fcport(vha, fcport); | |
ac280b67 AV |
469 | break; |
470 | case MBS_COMMAND_ERROR: | |
5ff1d584 | 471 | fcport->flags &= ~FCF_ASYNC_SENT; |
ac280b67 AV |
472 | if (data[1] & QLA_LOGIO_LOGIN_RETRIED) |
473 | set_bit(RELOGIN_NEEDED, &vha->dpc_flags); | |
474 | else | |
80d79440 | 475 | qla2x00_mark_device_lost(vha, fcport, 1, 0); |
ac280b67 AV |
476 | break; |
477 | case MBS_PORT_ID_USED: | |
478 | fcport->loop_id = data[1]; | |
6ac52608 | 479 | qla2x00_post_async_logout_work(vha, fcport, NULL); |
ac280b67 AV |
480 | qla2x00_post_async_login_work(vha, fcport, NULL); |
481 | break; | |
482 | case MBS_LOOP_ID_USED: | |
483 | fcport->loop_id++; | |
484 | rval = qla2x00_find_new_loop_id(vha, fcport); | |
485 | if (rval != QLA_SUCCESS) { | |
5ff1d584 | 486 | fcport->flags &= ~FCF_ASYNC_SENT; |
80d79440 | 487 | qla2x00_mark_device_lost(vha, fcport, 1, 0); |
ac280b67 AV |
488 | break; |
489 | } | |
490 | qla2x00_post_async_login_work(vha, fcport, NULL); | |
491 | break; | |
492 | } | |
4916392b | 493 | return; |
ac280b67 AV |
494 | } |
495 | ||
4916392b | 496 | void |
ac280b67 AV |
497 | qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport, |
498 | uint16_t *data) | |
499 | { | |
500 | qla2x00_mark_device_lost(vha, fcport, 1, 0); | |
4916392b | 501 | return; |
ac280b67 AV |
502 | } |
503 | ||
4916392b | 504 | void |
5ff1d584 AV |
505 | qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport, |
506 | uint16_t *data) | |
507 | { | |
508 | if (data[0] == MBS_COMMAND_COMPLETE) { | |
509 | qla2x00_update_fcport(vha, fcport); | |
510 | ||
4916392b | 511 | return; |
5ff1d584 AV |
512 | } |
513 | ||
514 | /* Retry login. */ | |
515 | fcport->flags &= ~FCF_ASYNC_SENT; | |
516 | if (data[1] & QLA_LOGIO_LOGIN_RETRIED) | |
517 | set_bit(RELOGIN_NEEDED, &vha->dpc_flags); | |
518 | else | |
80d79440 | 519 | qla2x00_mark_device_lost(vha, fcport, 1, 0); |
5ff1d584 | 520 | |
4916392b | 521 | return; |
5ff1d584 AV |
522 | } |
523 | ||
1da177e4 LT |
524 | /****************************************************************************/ |
525 | /* QLogic ISP2x00 Hardware Support Functions. */ | |
526 | /****************************************************************************/ | |
527 | ||
fa492630 | 528 | static int |
7d613ac6 SV |
529 | qla83xx_nic_core_fw_load(scsi_qla_host_t *vha) |
530 | { | |
531 | int rval = QLA_SUCCESS; | |
532 | struct qla_hw_data *ha = vha->hw; | |
533 | uint32_t idc_major_ver, idc_minor_ver; | |
711aa7f7 | 534 | uint16_t config[4]; |
7d613ac6 SV |
535 | |
536 | qla83xx_idc_lock(vha, 0); | |
537 | ||
538 | /* SV: TODO: Assign initialization timeout from | |
539 | * flash-info / other param | |
540 | */ | |
541 | ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT; | |
542 | ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT; | |
543 | ||
544 | /* Set our fcoe function presence */ | |
545 | if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) { | |
546 | ql_dbg(ql_dbg_p3p, vha, 0xb077, | |
547 | "Error while setting DRV-Presence.\n"); | |
548 | rval = QLA_FUNCTION_FAILED; | |
549 | goto exit; | |
550 | } | |
551 | ||
552 | /* Decide the reset ownership */ | |
553 | qla83xx_reset_ownership(vha); | |
554 | ||
555 | /* | |
556 | * On first protocol driver load: | |
557 | * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery | |
558 | * register. | |
559 | * Others: Check compatibility with current IDC Major version. | |
560 | */ | |
561 | qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver); | |
562 | if (ha->flags.nic_core_reset_owner) { | |
563 | /* Set IDC Major version */ | |
564 | idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION; | |
565 | qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver); | |
566 | ||
567 | /* Clearing IDC-Lock-Recovery register */ | |
568 | qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0); | |
569 | } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) { | |
570 | /* | |
571 | * Clear further IDC participation if we are not compatible with | |
572 | * the current IDC Major Version. | |
573 | */ | |
574 | ql_log(ql_log_warn, vha, 0xb07d, | |
575 | "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n", | |
576 | idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION); | |
577 | __qla83xx_clear_drv_presence(vha); | |
578 | rval = QLA_FUNCTION_FAILED; | |
579 | goto exit; | |
580 | } | |
581 | /* Each function sets its supported Minor version. */ | |
582 | qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver); | |
583 | idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2)); | |
584 | qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver); | |
585 | ||
711aa7f7 SK |
586 | if (ha->flags.nic_core_reset_owner) { |
587 | memset(config, 0, sizeof(config)); | |
588 | if (!qla81xx_get_port_config(vha, config)) | |
589 | qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, | |
590 | QLA8XXX_DEV_READY); | |
591 | } | |
592 | ||
7d613ac6 SV |
593 | rval = qla83xx_idc_state_handler(vha); |
594 | ||
595 | exit: | |
596 | qla83xx_idc_unlock(vha, 0); | |
597 | ||
598 | return rval; | |
599 | } | |
600 | ||
1da177e4 LT |
601 | /* |
602 | * qla2x00_initialize_adapter | |
603 | * Initialize board. | |
604 | * | |
605 | * Input: | |
606 | * ha = adapter block pointer. | |
607 | * | |
608 | * Returns: | |
609 | * 0 = success | |
610 | */ | |
611 | int | |
e315cd28 | 612 | qla2x00_initialize_adapter(scsi_qla_host_t *vha) |
1da177e4 LT |
613 | { |
614 | int rval; | |
e315cd28 | 615 | struct qla_hw_data *ha = vha->hw; |
73208dfd | 616 | struct req_que *req = ha->req_q_map[0]; |
2533cf67 | 617 | |
1da177e4 | 618 | /* Clear adapter flags. */ |
e315cd28 | 619 | vha->flags.online = 0; |
2533cf67 | 620 | ha->flags.chip_reset_done = 0; |
e315cd28 | 621 | vha->flags.reset_active = 0; |
85880801 AV |
622 | ha->flags.pci_channel_io_perm_failure = 0; |
623 | ha->flags.eeh_busy = 0; | |
fabbb8df | 624 | vha->qla_stats.jiffies_at_last_reset = get_jiffies_64(); |
e315cd28 AC |
625 | atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); |
626 | atomic_set(&vha->loop_state, LOOP_DOWN); | |
627 | vha->device_flags = DFLG_NO_CABLE; | |
628 | vha->dpc_flags = 0; | |
629 | vha->flags.management_server_logged_in = 0; | |
630 | vha->marker_needed = 0; | |
1da177e4 LT |
631 | ha->isp_abort_cnt = 0; |
632 | ha->beacon_blink_led = 0; | |
633 | ||
73208dfd AC |
634 | set_bit(0, ha->req_qid_map); |
635 | set_bit(0, ha->rsp_qid_map); | |
636 | ||
cfb0919c | 637 | ql_dbg(ql_dbg_init, vha, 0x0040, |
7c3df132 | 638 | "Configuring PCI space...\n"); |
e315cd28 | 639 | rval = ha->isp_ops->pci_config(vha); |
1da177e4 | 640 | if (rval) { |
7c3df132 SK |
641 | ql_log(ql_log_warn, vha, 0x0044, |
642 | "Unable to configure PCI space.\n"); | |
1da177e4 LT |
643 | return (rval); |
644 | } | |
645 | ||
e315cd28 | 646 | ha->isp_ops->reset_chip(vha); |
1da177e4 | 647 | |
e315cd28 | 648 | rval = qla2xxx_get_flash_info(vha); |
c00d8994 | 649 | if (rval) { |
7c3df132 SK |
650 | ql_log(ql_log_fatal, vha, 0x004f, |
651 | "Unable to validate FLASH data.\n"); | |
7ec0effd AD |
652 | return rval; |
653 | } | |
654 | ||
655 | if (IS_QLA8044(ha)) { | |
656 | qla8044_read_reset_template(vha); | |
657 | ||
658 | /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0. | |
659 | * If DONRESET_BIT0 is set, drivers should not set dev_state | |
660 | * to NEED_RESET. But if NEED_RESET is set, drivers should | |
661 | * should honor the reset. */ | |
662 | if (ql2xdontresethba == 1) | |
663 | qla8044_set_idc_dontreset(vha); | |
c00d8994 AV |
664 | } |
665 | ||
73208dfd | 666 | ha->isp_ops->get_flash_version(vha, req->ring); |
cfb0919c | 667 | ql_dbg(ql_dbg_init, vha, 0x0061, |
7c3df132 | 668 | "Configure NVRAM parameters...\n"); |
0107109e | 669 | |
e315cd28 | 670 | ha->isp_ops->nvram_config(vha); |
1da177e4 | 671 | |
d4c760c2 AV |
672 | if (ha->flags.disable_serdes) { |
673 | /* Mask HBA via NVRAM settings? */ | |
7c3df132 | 674 | ql_log(ql_log_info, vha, 0x0077, |
7b833558 | 675 | "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name); |
d4c760c2 AV |
676 | return QLA_FUNCTION_FAILED; |
677 | } | |
678 | ||
cfb0919c | 679 | ql_dbg(ql_dbg_init, vha, 0x0078, |
7c3df132 | 680 | "Verifying loaded RISC code...\n"); |
1da177e4 | 681 | |
e315cd28 AC |
682 | if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) { |
683 | rval = ha->isp_ops->chip_diag(vha); | |
d19044c3 AV |
684 | if (rval) |
685 | return (rval); | |
e315cd28 | 686 | rval = qla2x00_setup_chip(vha); |
d19044c3 AV |
687 | if (rval) |
688 | return (rval); | |
1da177e4 | 689 | } |
a9083016 | 690 | |
4d4df193 | 691 | if (IS_QLA84XX(ha)) { |
e315cd28 | 692 | ha->cs84xx = qla84xx_get_chip(vha); |
4d4df193 | 693 | if (!ha->cs84xx) { |
7c3df132 | 694 | ql_log(ql_log_warn, vha, 0x00d0, |
4d4df193 HK |
695 | "Unable to configure ISP84XX.\n"); |
696 | return QLA_FUNCTION_FAILED; | |
697 | } | |
698 | } | |
2d70c103 NB |
699 | |
700 | if (qla_ini_mode_enabled(vha)) | |
701 | rval = qla2x00_init_rings(vha); | |
702 | ||
2533cf67 | 703 | ha->flags.chip_reset_done = 1; |
1da177e4 | 704 | |
9a069e19 | 705 | if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) { |
6c452a45 | 706 | /* Issue verify 84xx FW IOCB to complete 84xx initialization */ |
9a069e19 GM |
707 | rval = qla84xx_init_chip(vha); |
708 | if (rval != QLA_SUCCESS) { | |
7c3df132 SK |
709 | ql_log(ql_log_warn, vha, 0x00d4, |
710 | "Unable to initialize ISP84XX.\n"); | |
8d2b21db | 711 | qla84xx_put_chip(vha); |
9a069e19 GM |
712 | } |
713 | } | |
714 | ||
7d613ac6 SV |
715 | /* Load the NIC Core f/w if we are the first protocol driver. */ |
716 | if (IS_QLA8031(ha)) { | |
717 | rval = qla83xx_nic_core_fw_load(vha); | |
718 | if (rval) | |
719 | ql_log(ql_log_warn, vha, 0x0124, | |
720 | "Error in initializing NIC Core f/w.\n"); | |
721 | } | |
722 | ||
2f0f3f4f MI |
723 | if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha)) |
724 | qla24xx_read_fcp_prio_cfg(vha); | |
09ff701a | 725 | |
c46e65c7 JC |
726 | if (IS_P3P_TYPE(ha)) |
727 | qla82xx_set_driver_version(vha, QLA2XXX_VERSION); | |
728 | else | |
729 | qla25xx_set_driver_version(vha, QLA2XXX_VERSION); | |
730 | ||
1da177e4 LT |
731 | return (rval); |
732 | } | |
733 | ||
734 | /** | |
abbd8870 | 735 | * qla2100_pci_config() - Setup ISP21xx PCI configuration registers. |
1da177e4 LT |
736 | * @ha: HA context |
737 | * | |
738 | * Returns 0 on success. | |
739 | */ | |
abbd8870 | 740 | int |
e315cd28 | 741 | qla2100_pci_config(scsi_qla_host_t *vha) |
1da177e4 | 742 | { |
a157b101 | 743 | uint16_t w; |
abbd8870 | 744 | unsigned long flags; |
e315cd28 | 745 | struct qla_hw_data *ha = vha->hw; |
3d71644c | 746 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 | 747 | |
1da177e4 | 748 | pci_set_master(ha->pdev); |
af6177d8 | 749 | pci_try_set_mwi(ha->pdev); |
1da177e4 | 750 | |
1da177e4 | 751 | pci_read_config_word(ha->pdev, PCI_COMMAND, &w); |
a157b101 | 752 | w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); |
abbd8870 AV |
753 | pci_write_config_word(ha->pdev, PCI_COMMAND, w); |
754 | ||
737faece | 755 | pci_disable_rom(ha->pdev); |
1da177e4 LT |
756 | |
757 | /* Get PCI bus information. */ | |
758 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
3d71644c | 759 | ha->pci_attr = RD_REG_WORD(®->ctrl_status); |
1da177e4 LT |
760 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
761 | ||
abbd8870 AV |
762 | return QLA_SUCCESS; |
763 | } | |
1da177e4 | 764 | |
abbd8870 AV |
765 | /** |
766 | * qla2300_pci_config() - Setup ISP23xx PCI configuration registers. | |
767 | * @ha: HA context | |
768 | * | |
769 | * Returns 0 on success. | |
770 | */ | |
771 | int | |
e315cd28 | 772 | qla2300_pci_config(scsi_qla_host_t *vha) |
abbd8870 | 773 | { |
a157b101 | 774 | uint16_t w; |
abbd8870 AV |
775 | unsigned long flags = 0; |
776 | uint32_t cnt; | |
e315cd28 | 777 | struct qla_hw_data *ha = vha->hw; |
3d71644c | 778 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 | 779 | |
abbd8870 | 780 | pci_set_master(ha->pdev); |
af6177d8 | 781 | pci_try_set_mwi(ha->pdev); |
1da177e4 | 782 | |
abbd8870 | 783 | pci_read_config_word(ha->pdev, PCI_COMMAND, &w); |
a157b101 | 784 | w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); |
1da177e4 | 785 | |
abbd8870 AV |
786 | if (IS_QLA2322(ha) || IS_QLA6322(ha)) |
787 | w &= ~PCI_COMMAND_INTX_DISABLE; | |
a157b101 | 788 | pci_write_config_word(ha->pdev, PCI_COMMAND, w); |
1da177e4 | 789 | |
abbd8870 AV |
790 | /* |
791 | * If this is a 2300 card and not 2312, reset the | |
792 | * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately, | |
793 | * the 2310 also reports itself as a 2300 so we need to get the | |
794 | * fb revision level -- a 6 indicates it really is a 2300 and | |
795 | * not a 2310. | |
796 | */ | |
797 | if (IS_QLA2300(ha)) { | |
798 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1da177e4 | 799 | |
abbd8870 | 800 | /* Pause RISC. */ |
3d71644c | 801 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); |
abbd8870 | 802 | for (cnt = 0; cnt < 30000; cnt++) { |
3d71644c | 803 | if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) != 0) |
abbd8870 | 804 | break; |
1da177e4 | 805 | |
abbd8870 AV |
806 | udelay(10); |
807 | } | |
1da177e4 | 808 | |
abbd8870 | 809 | /* Select FPM registers. */ |
3d71644c AV |
810 | WRT_REG_WORD(®->ctrl_status, 0x20); |
811 | RD_REG_WORD(®->ctrl_status); | |
abbd8870 AV |
812 | |
813 | /* Get the fb rev level */ | |
3d71644c | 814 | ha->fb_rev = RD_FB_CMD_REG(ha, reg); |
abbd8870 AV |
815 | |
816 | if (ha->fb_rev == FPM_2300) | |
a157b101 | 817 | pci_clear_mwi(ha->pdev); |
abbd8870 AV |
818 | |
819 | /* Deselect FPM registers. */ | |
3d71644c AV |
820 | WRT_REG_WORD(®->ctrl_status, 0x0); |
821 | RD_REG_WORD(®->ctrl_status); | |
abbd8870 AV |
822 | |
823 | /* Release RISC module. */ | |
3d71644c | 824 | WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); |
abbd8870 | 825 | for (cnt = 0; cnt < 30000; cnt++) { |
3d71644c | 826 | if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0) |
abbd8870 AV |
827 | break; |
828 | ||
829 | udelay(10); | |
1da177e4 | 830 | } |
1da177e4 | 831 | |
abbd8870 AV |
832 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
833 | } | |
1da177e4 | 834 | |
abbd8870 AV |
835 | pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80); |
836 | ||
737faece | 837 | pci_disable_rom(ha->pdev); |
1da177e4 | 838 | |
abbd8870 AV |
839 | /* Get PCI bus information. */ |
840 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
3d71644c | 841 | ha->pci_attr = RD_REG_WORD(®->ctrl_status); |
abbd8870 AV |
842 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
843 | ||
844 | return QLA_SUCCESS; | |
1da177e4 LT |
845 | } |
846 | ||
0107109e AV |
847 | /** |
848 | * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers. | |
849 | * @ha: HA context | |
850 | * | |
851 | * Returns 0 on success. | |
852 | */ | |
853 | int | |
e315cd28 | 854 | qla24xx_pci_config(scsi_qla_host_t *vha) |
0107109e | 855 | { |
a157b101 | 856 | uint16_t w; |
0107109e | 857 | unsigned long flags = 0; |
e315cd28 | 858 | struct qla_hw_data *ha = vha->hw; |
0107109e | 859 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
0107109e AV |
860 | |
861 | pci_set_master(ha->pdev); | |
af6177d8 | 862 | pci_try_set_mwi(ha->pdev); |
0107109e AV |
863 | |
864 | pci_read_config_word(ha->pdev, PCI_COMMAND, &w); | |
a157b101 | 865 | w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); |
0107109e AV |
866 | w &= ~PCI_COMMAND_INTX_DISABLE; |
867 | pci_write_config_word(ha->pdev, PCI_COMMAND, w); | |
868 | ||
869 | pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80); | |
870 | ||
871 | /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */ | |
f85ec187 AV |
872 | if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX)) |
873 | pcix_set_mmrbc(ha->pdev, 2048); | |
0107109e AV |
874 | |
875 | /* PCIe -- adjust Maximum Read Request Size (2048). */ | |
e67f1321 | 876 | if (pci_is_pcie(ha->pdev)) |
5ffd3a52 | 877 | pcie_set_readrq(ha->pdev, 4096); |
0107109e | 878 | |
737faece | 879 | pci_disable_rom(ha->pdev); |
0107109e | 880 | |
44c10138 | 881 | ha->chip_revision = ha->pdev->revision; |
a8488abe | 882 | |
0107109e AV |
883 | /* Get PCI bus information. */ |
884 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
885 | ha->pci_attr = RD_REG_DWORD(®->ctrl_status); | |
886 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
887 | ||
888 | return QLA_SUCCESS; | |
889 | } | |
890 | ||
c3a2f0df AV |
891 | /** |
892 | * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers. | |
893 | * @ha: HA context | |
894 | * | |
895 | * Returns 0 on success. | |
896 | */ | |
897 | int | |
e315cd28 | 898 | qla25xx_pci_config(scsi_qla_host_t *vha) |
c3a2f0df AV |
899 | { |
900 | uint16_t w; | |
e315cd28 | 901 | struct qla_hw_data *ha = vha->hw; |
c3a2f0df AV |
902 | |
903 | pci_set_master(ha->pdev); | |
904 | pci_try_set_mwi(ha->pdev); | |
905 | ||
906 | pci_read_config_word(ha->pdev, PCI_COMMAND, &w); | |
907 | w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); | |
908 | w &= ~PCI_COMMAND_INTX_DISABLE; | |
909 | pci_write_config_word(ha->pdev, PCI_COMMAND, w); | |
910 | ||
911 | /* PCIe -- adjust Maximum Read Request Size (2048). */ | |
e67f1321 | 912 | if (pci_is_pcie(ha->pdev)) |
5ffd3a52 | 913 | pcie_set_readrq(ha->pdev, 4096); |
c3a2f0df | 914 | |
737faece | 915 | pci_disable_rom(ha->pdev); |
c3a2f0df AV |
916 | |
917 | ha->chip_revision = ha->pdev->revision; | |
918 | ||
919 | return QLA_SUCCESS; | |
920 | } | |
921 | ||
1da177e4 LT |
922 | /** |
923 | * qla2x00_isp_firmware() - Choose firmware image. | |
924 | * @ha: HA context | |
925 | * | |
926 | * Returns 0 on success. | |
927 | */ | |
928 | static int | |
e315cd28 | 929 | qla2x00_isp_firmware(scsi_qla_host_t *vha) |
1da177e4 LT |
930 | { |
931 | int rval; | |
42e421b1 AV |
932 | uint16_t loop_id, topo, sw_cap; |
933 | uint8_t domain, area, al_pa; | |
e315cd28 | 934 | struct qla_hw_data *ha = vha->hw; |
1da177e4 LT |
935 | |
936 | /* Assume loading risc code */ | |
fa2a1ce5 | 937 | rval = QLA_FUNCTION_FAILED; |
1da177e4 LT |
938 | |
939 | if (ha->flags.disable_risc_code_load) { | |
7c3df132 | 940 | ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n"); |
1da177e4 LT |
941 | |
942 | /* Verify checksum of loaded RISC code. */ | |
e315cd28 | 943 | rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address); |
42e421b1 AV |
944 | if (rval == QLA_SUCCESS) { |
945 | /* And, verify we are not in ROM code. */ | |
e315cd28 | 946 | rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa, |
42e421b1 AV |
947 | &area, &domain, &topo, &sw_cap); |
948 | } | |
1da177e4 LT |
949 | } |
950 | ||
7c3df132 SK |
951 | if (rval) |
952 | ql_dbg(ql_dbg_init, vha, 0x007a, | |
953 | "**** Load RISC code ****.\n"); | |
1da177e4 LT |
954 | |
955 | return (rval); | |
956 | } | |
957 | ||
958 | /** | |
959 | * qla2x00_reset_chip() - Reset ISP chip. | |
960 | * @ha: HA context | |
961 | * | |
962 | * Returns 0 on success. | |
963 | */ | |
abbd8870 | 964 | void |
e315cd28 | 965 | qla2x00_reset_chip(scsi_qla_host_t *vha) |
1da177e4 LT |
966 | { |
967 | unsigned long flags = 0; | |
e315cd28 | 968 | struct qla_hw_data *ha = vha->hw; |
3d71644c | 969 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 | 970 | uint32_t cnt; |
1da177e4 LT |
971 | uint16_t cmd; |
972 | ||
85880801 AV |
973 | if (unlikely(pci_channel_offline(ha->pdev))) |
974 | return; | |
975 | ||
fd34f556 | 976 | ha->isp_ops->disable_intrs(ha); |
1da177e4 LT |
977 | |
978 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
979 | ||
980 | /* Turn off master enable */ | |
981 | cmd = 0; | |
982 | pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd); | |
983 | cmd &= ~PCI_COMMAND_MASTER; | |
984 | pci_write_config_word(ha->pdev, PCI_COMMAND, cmd); | |
985 | ||
986 | if (!IS_QLA2100(ha)) { | |
987 | /* Pause RISC. */ | |
988 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); | |
989 | if (IS_QLA2200(ha) || IS_QLA2300(ha)) { | |
990 | for (cnt = 0; cnt < 30000; cnt++) { | |
991 | if ((RD_REG_WORD(®->hccr) & | |
992 | HCCR_RISC_PAUSE) != 0) | |
993 | break; | |
994 | udelay(100); | |
995 | } | |
996 | } else { | |
997 | RD_REG_WORD(®->hccr); /* PCI Posting. */ | |
998 | udelay(10); | |
999 | } | |
1000 | ||
1001 | /* Select FPM registers. */ | |
1002 | WRT_REG_WORD(®->ctrl_status, 0x20); | |
1003 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1004 | ||
1005 | /* FPM Soft Reset. */ | |
1006 | WRT_REG_WORD(®->fpm_diag_config, 0x100); | |
1007 | RD_REG_WORD(®->fpm_diag_config); /* PCI Posting. */ | |
1008 | ||
1009 | /* Toggle Fpm Reset. */ | |
1010 | if (!IS_QLA2200(ha)) { | |
1011 | WRT_REG_WORD(®->fpm_diag_config, 0x0); | |
1012 | RD_REG_WORD(®->fpm_diag_config); /* PCI Posting. */ | |
1013 | } | |
1014 | ||
1015 | /* Select frame buffer registers. */ | |
1016 | WRT_REG_WORD(®->ctrl_status, 0x10); | |
1017 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1018 | ||
1019 | /* Reset frame buffer FIFOs. */ | |
1020 | if (IS_QLA2200(ha)) { | |
1021 | WRT_FB_CMD_REG(ha, reg, 0xa000); | |
1022 | RD_FB_CMD_REG(ha, reg); /* PCI Posting. */ | |
1023 | } else { | |
1024 | WRT_FB_CMD_REG(ha, reg, 0x00fc); | |
1025 | ||
1026 | /* Read back fb_cmd until zero or 3 seconds max */ | |
1027 | for (cnt = 0; cnt < 3000; cnt++) { | |
1028 | if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0) | |
1029 | break; | |
1030 | udelay(100); | |
1031 | } | |
1032 | } | |
1033 | ||
1034 | /* Select RISC module registers. */ | |
1035 | WRT_REG_WORD(®->ctrl_status, 0); | |
1036 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1037 | ||
1038 | /* Reset RISC processor. */ | |
1039 | WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); | |
1040 | RD_REG_WORD(®->hccr); /* PCI Posting. */ | |
1041 | ||
1042 | /* Release RISC processor. */ | |
1043 | WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); | |
1044 | RD_REG_WORD(®->hccr); /* PCI Posting. */ | |
1045 | } | |
1046 | ||
1047 | WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); | |
1048 | WRT_REG_WORD(®->hccr, HCCR_CLR_HOST_INT); | |
1049 | ||
1050 | /* Reset ISP chip. */ | |
1051 | WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); | |
1052 | ||
1053 | /* Wait for RISC to recover from reset. */ | |
1054 | if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { | |
1055 | /* | |
1056 | * It is necessary to for a delay here since the card doesn't | |
1057 | * respond to PCI reads during a reset. On some architectures | |
1058 | * this will result in an MCA. | |
1059 | */ | |
1060 | udelay(20); | |
1061 | for (cnt = 30000; cnt; cnt--) { | |
1062 | if ((RD_REG_WORD(®->ctrl_status) & | |
1063 | CSR_ISP_SOFT_RESET) == 0) | |
1064 | break; | |
1065 | udelay(100); | |
1066 | } | |
1067 | } else | |
1068 | udelay(10); | |
1069 | ||
1070 | /* Reset RISC processor. */ | |
1071 | WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); | |
1072 | ||
1073 | WRT_REG_WORD(®->semaphore, 0); | |
1074 | ||
1075 | /* Release RISC processor. */ | |
1076 | WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); | |
1077 | RD_REG_WORD(®->hccr); /* PCI Posting. */ | |
1078 | ||
1079 | if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { | |
1080 | for (cnt = 0; cnt < 30000; cnt++) { | |
ffb39f03 | 1081 | if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY) |
1da177e4 | 1082 | break; |
1da177e4 LT |
1083 | |
1084 | udelay(100); | |
1085 | } | |
1086 | } else | |
1087 | udelay(100); | |
1088 | ||
1089 | /* Turn on master enable */ | |
1090 | cmd |= PCI_COMMAND_MASTER; | |
1091 | pci_write_config_word(ha->pdev, PCI_COMMAND, cmd); | |
1092 | ||
1093 | /* Disable RISC pause on FPM parity error. */ | |
1094 | if (!IS_QLA2100(ha)) { | |
1095 | WRT_REG_WORD(®->hccr, HCCR_DISABLE_PARITY_PAUSE); | |
1096 | RD_REG_WORD(®->hccr); /* PCI Posting. */ | |
1097 | } | |
1098 | ||
1099 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1100 | } | |
1101 | ||
b1d46989 MI |
1102 | /** |
1103 | * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC. | |
1104 | * | |
1105 | * Returns 0 on success. | |
1106 | */ | |
fa492630 | 1107 | static int |
b1d46989 MI |
1108 | qla81xx_reset_mpi(scsi_qla_host_t *vha) |
1109 | { | |
1110 | uint16_t mb[4] = {0x1010, 0, 1, 0}; | |
1111 | ||
6246b8a1 GM |
1112 | if (!IS_QLA81XX(vha->hw)) |
1113 | return QLA_SUCCESS; | |
1114 | ||
b1d46989 MI |
1115 | return qla81xx_write_mpi_register(vha, mb); |
1116 | } | |
1117 | ||
0107109e | 1118 | /** |
88c26663 | 1119 | * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC. |
0107109e AV |
1120 | * @ha: HA context |
1121 | * | |
1122 | * Returns 0 on success. | |
1123 | */ | |
d14e72fb | 1124 | static inline int |
e315cd28 | 1125 | qla24xx_reset_risc(scsi_qla_host_t *vha) |
0107109e AV |
1126 | { |
1127 | unsigned long flags = 0; | |
e315cd28 | 1128 | struct qla_hw_data *ha = vha->hw; |
0107109e AV |
1129 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
1130 | uint32_t cnt, d2; | |
335a1cc9 | 1131 | uint16_t wd; |
b1d46989 | 1132 | static int abts_cnt; /* ISP abort retry counts */ |
d14e72fb | 1133 | int rval = QLA_SUCCESS; |
0107109e | 1134 | |
0107109e AV |
1135 | spin_lock_irqsave(&ha->hardware_lock, flags); |
1136 | ||
1137 | /* Reset RISC. */ | |
1138 | WRT_REG_DWORD(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); | |
1139 | for (cnt = 0; cnt < 30000; cnt++) { | |
1140 | if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) | |
1141 | break; | |
1142 | ||
1143 | udelay(10); | |
1144 | } | |
1145 | ||
d14e72fb HM |
1146 | if (!(RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE)) |
1147 | set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags); | |
1148 | ||
1149 | ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017e, | |
1150 | "HCCR: 0x%x, Control Status %x, DMA active status:0x%x\n", | |
1151 | RD_REG_DWORD(®->hccr), | |
1152 | RD_REG_DWORD(®->ctrl_status), | |
1153 | (RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE)); | |
1154 | ||
0107109e AV |
1155 | WRT_REG_DWORD(®->ctrl_status, |
1156 | CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); | |
335a1cc9 | 1157 | pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); |
88c26663 | 1158 | |
335a1cc9 | 1159 | udelay(100); |
d14e72fb | 1160 | |
88c26663 | 1161 | /* Wait for firmware to complete NVRAM accesses. */ |
88c26663 | 1162 | d2 = (uint32_t) RD_REG_WORD(®->mailbox0); |
d14e72fb HM |
1163 | for (cnt = 10000; RD_REG_WORD(®->mailbox0) != 0 && |
1164 | rval == QLA_SUCCESS; cnt--) { | |
88c26663 | 1165 | barrier(); |
d14e72fb HM |
1166 | if (cnt) |
1167 | udelay(5); | |
1168 | else | |
1169 | rval = QLA_FUNCTION_TIMEOUT; | |
88c26663 AV |
1170 | } |
1171 | ||
d14e72fb HM |
1172 | if (rval == QLA_SUCCESS) |
1173 | set_bit(ISP_MBX_RDY, &ha->fw_dump_cap_flags); | |
1174 | ||
1175 | ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017f, | |
1176 | "HCCR: 0x%x, MailBox0 Status 0x%x\n", | |
1177 | RD_REG_DWORD(®->hccr), | |
1178 | RD_REG_DWORD(®->mailbox0)); | |
1179 | ||
335a1cc9 | 1180 | /* Wait for soft-reset to complete. */ |
0107109e | 1181 | d2 = RD_REG_DWORD(®->ctrl_status); |
d14e72fb | 1182 | for (cnt = 0; cnt < 6000000; cnt++) { |
0107109e | 1183 | barrier(); |
d14e72fb HM |
1184 | if ((RD_REG_DWORD(®->ctrl_status) & |
1185 | CSRX_ISP_SOFT_RESET) == 0) | |
1186 | break; | |
1187 | ||
1188 | udelay(5); | |
0107109e | 1189 | } |
d14e72fb HM |
1190 | if (!(RD_REG_DWORD(®->ctrl_status) & CSRX_ISP_SOFT_RESET)) |
1191 | set_bit(ISP_SOFT_RESET_CMPL, &ha->fw_dump_cap_flags); | |
1192 | ||
1193 | ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015d, | |
1194 | "HCCR: 0x%x, Soft Reset status: 0x%x\n", | |
1195 | RD_REG_DWORD(®->hccr), | |
1196 | RD_REG_DWORD(®->ctrl_status)); | |
0107109e | 1197 | |
b1d46989 MI |
1198 | /* If required, do an MPI FW reset now */ |
1199 | if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) { | |
1200 | if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) { | |
1201 | if (++abts_cnt < 5) { | |
1202 | set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); | |
1203 | set_bit(MPI_RESET_NEEDED, &vha->dpc_flags); | |
1204 | } else { | |
1205 | /* | |
1206 | * We exhausted the ISP abort retries. We have to | |
1207 | * set the board offline. | |
1208 | */ | |
1209 | abts_cnt = 0; | |
1210 | vha->flags.online = 0; | |
1211 | } | |
1212 | } | |
1213 | } | |
1214 | ||
0107109e AV |
1215 | WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET); |
1216 | RD_REG_DWORD(®->hccr); | |
1217 | ||
1218 | WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE); | |
1219 | RD_REG_DWORD(®->hccr); | |
1220 | ||
1221 | WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); | |
1222 | RD_REG_DWORD(®->hccr); | |
1223 | ||
1224 | d2 = (uint32_t) RD_REG_WORD(®->mailbox0); | |
d14e72fb HM |
1225 | for (cnt = 6000000; RD_REG_WORD(®->mailbox0) != 0 && |
1226 | rval == QLA_SUCCESS; cnt--) { | |
0107109e | 1227 | barrier(); |
d14e72fb HM |
1228 | if (cnt) |
1229 | udelay(5); | |
1230 | else | |
1231 | rval = QLA_FUNCTION_TIMEOUT; | |
0107109e | 1232 | } |
d14e72fb HM |
1233 | if (rval == QLA_SUCCESS) |
1234 | set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags); | |
1235 | ||
1236 | ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015e, | |
1237 | "Host Risc 0x%x, mailbox0 0x%x\n", | |
1238 | RD_REG_DWORD(®->hccr), | |
1239 | RD_REG_WORD(®->mailbox0)); | |
0107109e AV |
1240 | |
1241 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
124f85e6 | 1242 | |
d14e72fb HM |
1243 | ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015f, |
1244 | "Driver in %s mode\n", | |
1245 | IS_NOPOLLING_TYPE(ha) ? "Interrupt" : "Polling"); | |
1246 | ||
124f85e6 AV |
1247 | if (IS_NOPOLLING_TYPE(ha)) |
1248 | ha->isp_ops->enable_intrs(ha); | |
d14e72fb HM |
1249 | |
1250 | return rval; | |
0107109e AV |
1251 | } |
1252 | ||
4ea2c9c7 JC |
1253 | static void |
1254 | qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data) | |
1255 | { | |
1256 | struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24; | |
1257 | ||
1258 | WRT_REG_DWORD(®->iobase_addr, RISC_REGISTER_BASE_OFFSET); | |
1259 | *data = RD_REG_DWORD(®->iobase_window + RISC_REGISTER_WINDOW_OFFET); | |
1260 | ||
1261 | } | |
1262 | ||
1263 | static void | |
1264 | qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data) | |
1265 | { | |
1266 | struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24; | |
1267 | ||
1268 | WRT_REG_DWORD(®->iobase_addr, RISC_REGISTER_BASE_OFFSET); | |
1269 | WRT_REG_DWORD(®->iobase_window + RISC_REGISTER_WINDOW_OFFET, data); | |
1270 | } | |
1271 | ||
1272 | static void | |
1273 | qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha) | |
1274 | { | |
1275 | struct qla_hw_data *ha = vha->hw; | |
1276 | uint32_t wd32 = 0; | |
1277 | uint delta_msec = 100; | |
1278 | uint elapsed_msec = 0; | |
1279 | uint timeout_msec; | |
1280 | ulong n; | |
1281 | ||
1282 | if (!IS_QLA25XX(ha) && !IS_QLA2031(ha)) | |
1283 | return; | |
1284 | ||
1285 | attempt: | |
1286 | timeout_msec = TIMEOUT_SEMAPHORE; | |
1287 | n = timeout_msec / delta_msec; | |
1288 | while (n--) { | |
1289 | qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET); | |
1290 | qla25xx_read_risc_sema_reg(vha, &wd32); | |
1291 | if (wd32 & RISC_SEMAPHORE) | |
1292 | break; | |
1293 | msleep(delta_msec); | |
1294 | elapsed_msec += delta_msec; | |
1295 | if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED) | |
1296 | goto force; | |
1297 | } | |
1298 | ||
1299 | if (!(wd32 & RISC_SEMAPHORE)) | |
1300 | goto force; | |
1301 | ||
1302 | if (!(wd32 & RISC_SEMAPHORE_FORCE)) | |
1303 | goto acquired; | |
1304 | ||
1305 | qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR); | |
1306 | timeout_msec = TIMEOUT_SEMAPHORE_FORCE; | |
1307 | n = timeout_msec / delta_msec; | |
1308 | while (n--) { | |
1309 | qla25xx_read_risc_sema_reg(vha, &wd32); | |
1310 | if (!(wd32 & RISC_SEMAPHORE_FORCE)) | |
1311 | break; | |
1312 | msleep(delta_msec); | |
1313 | elapsed_msec += delta_msec; | |
1314 | if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED) | |
1315 | goto force; | |
1316 | } | |
1317 | ||
1318 | if (wd32 & RISC_SEMAPHORE_FORCE) | |
1319 | qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR); | |
1320 | ||
1321 | goto attempt; | |
1322 | ||
1323 | force: | |
1324 | qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET); | |
1325 | ||
1326 | acquired: | |
1327 | return; | |
1328 | } | |
1329 | ||
88c26663 AV |
1330 | /** |
1331 | * qla24xx_reset_chip() - Reset ISP24xx chip. | |
1332 | * @ha: HA context | |
1333 | * | |
1334 | * Returns 0 on success. | |
1335 | */ | |
1336 | void | |
e315cd28 | 1337 | qla24xx_reset_chip(scsi_qla_host_t *vha) |
88c26663 | 1338 | { |
e315cd28 | 1339 | struct qla_hw_data *ha = vha->hw; |
85880801 AV |
1340 | |
1341 | if (pci_channel_offline(ha->pdev) && | |
1342 | ha->flags.pci_channel_io_perm_failure) { | |
1343 | return; | |
1344 | } | |
1345 | ||
fd34f556 | 1346 | ha->isp_ops->disable_intrs(ha); |
88c26663 | 1347 | |
4ea2c9c7 JC |
1348 | qla25xx_manipulate_risc_semaphore(vha); |
1349 | ||
88c26663 | 1350 | /* Perform RISC reset. */ |
e315cd28 | 1351 | qla24xx_reset_risc(vha); |
88c26663 AV |
1352 | } |
1353 | ||
1da177e4 LT |
1354 | /** |
1355 | * qla2x00_chip_diag() - Test chip for proper operation. | |
1356 | * @ha: HA context | |
1357 | * | |
1358 | * Returns 0 on success. | |
1359 | */ | |
abbd8870 | 1360 | int |
e315cd28 | 1361 | qla2x00_chip_diag(scsi_qla_host_t *vha) |
1da177e4 LT |
1362 | { |
1363 | int rval; | |
e315cd28 | 1364 | struct qla_hw_data *ha = vha->hw; |
3d71644c | 1365 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 LT |
1366 | unsigned long flags = 0; |
1367 | uint16_t data; | |
1368 | uint32_t cnt; | |
1369 | uint16_t mb[5]; | |
73208dfd | 1370 | struct req_que *req = ha->req_q_map[0]; |
1da177e4 LT |
1371 | |
1372 | /* Assume a failed state */ | |
1373 | rval = QLA_FUNCTION_FAILED; | |
1374 | ||
7c3df132 SK |
1375 | ql_dbg(ql_dbg_init, vha, 0x007b, |
1376 | "Testing device at %lx.\n", (u_long)®->flash_address); | |
1da177e4 LT |
1377 | |
1378 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1379 | ||
1380 | /* Reset ISP chip. */ | |
1381 | WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); | |
1382 | ||
1383 | /* | |
1384 | * We need to have a delay here since the card will not respond while | |
1385 | * in reset causing an MCA on some architectures. | |
1386 | */ | |
1387 | udelay(20); | |
1388 | data = qla2x00_debounce_register(®->ctrl_status); | |
1389 | for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) { | |
1390 | udelay(5); | |
1391 | data = RD_REG_WORD(®->ctrl_status); | |
1392 | barrier(); | |
1393 | } | |
1394 | ||
1395 | if (!cnt) | |
1396 | goto chip_diag_failed; | |
1397 | ||
7c3df132 SK |
1398 | ql_dbg(ql_dbg_init, vha, 0x007c, |
1399 | "Reset register cleared by chip reset.\n"); | |
1da177e4 LT |
1400 | |
1401 | /* Reset RISC processor. */ | |
1402 | WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); | |
1403 | WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); | |
1404 | ||
1405 | /* Workaround for QLA2312 PCI parity error */ | |
1406 | if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { | |
1407 | data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0)); | |
1408 | for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) { | |
1409 | udelay(5); | |
1410 | data = RD_MAILBOX_REG(ha, reg, 0); | |
fa2a1ce5 | 1411 | barrier(); |
1da177e4 LT |
1412 | } |
1413 | } else | |
1414 | udelay(10); | |
1415 | ||
1416 | if (!cnt) | |
1417 | goto chip_diag_failed; | |
1418 | ||
1419 | /* Check product ID of chip */ | |
7c3df132 | 1420 | ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n"); |
1da177e4 LT |
1421 | |
1422 | mb[1] = RD_MAILBOX_REG(ha, reg, 1); | |
1423 | mb[2] = RD_MAILBOX_REG(ha, reg, 2); | |
1424 | mb[3] = RD_MAILBOX_REG(ha, reg, 3); | |
1425 | mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4)); | |
1426 | if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) || | |
1427 | mb[3] != PROD_ID_3) { | |
7c3df132 SK |
1428 | ql_log(ql_log_warn, vha, 0x0062, |
1429 | "Wrong product ID = 0x%x,0x%x,0x%x.\n", | |
1430 | mb[1], mb[2], mb[3]); | |
1da177e4 LT |
1431 | |
1432 | goto chip_diag_failed; | |
1433 | } | |
1434 | ha->product_id[0] = mb[1]; | |
1435 | ha->product_id[1] = mb[2]; | |
1436 | ha->product_id[2] = mb[3]; | |
1437 | ha->product_id[3] = mb[4]; | |
1438 | ||
1439 | /* Adjust fw RISC transfer size */ | |
73208dfd | 1440 | if (req->length > 1024) |
1da177e4 LT |
1441 | ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024; |
1442 | else | |
1443 | ha->fw_transfer_size = REQUEST_ENTRY_SIZE * | |
73208dfd | 1444 | req->length; |
1da177e4 LT |
1445 | |
1446 | if (IS_QLA2200(ha) && | |
1447 | RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) { | |
1448 | /* Limit firmware transfer size with a 2200A */ | |
7c3df132 | 1449 | ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n"); |
1da177e4 | 1450 | |
ea5b6382 | 1451 | ha->device_type |= DT_ISP2200A; |
1da177e4 LT |
1452 | ha->fw_transfer_size = 128; |
1453 | } | |
1454 | ||
1455 | /* Wrap Incoming Mailboxes Test. */ | |
1456 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1457 | ||
7c3df132 | 1458 | ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n"); |
e315cd28 | 1459 | rval = qla2x00_mbx_reg_test(vha); |
7c3df132 SK |
1460 | if (rval) |
1461 | ql_log(ql_log_warn, vha, 0x0080, | |
1462 | "Failed mailbox send register test.\n"); | |
1463 | else | |
1da177e4 LT |
1464 | /* Flag a successful rval */ |
1465 | rval = QLA_SUCCESS; | |
1da177e4 LT |
1466 | spin_lock_irqsave(&ha->hardware_lock, flags); |
1467 | ||
1468 | chip_diag_failed: | |
1469 | if (rval) | |
7c3df132 SK |
1470 | ql_log(ql_log_info, vha, 0x0081, |
1471 | "Chip diagnostics **** FAILED ****.\n"); | |
1da177e4 LT |
1472 | |
1473 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1474 | ||
1475 | return (rval); | |
1476 | } | |
1477 | ||
0107109e AV |
1478 | /** |
1479 | * qla24xx_chip_diag() - Test ISP24xx for proper operation. | |
1480 | * @ha: HA context | |
1481 | * | |
1482 | * Returns 0 on success. | |
1483 | */ | |
1484 | int | |
e315cd28 | 1485 | qla24xx_chip_diag(scsi_qla_host_t *vha) |
0107109e AV |
1486 | { |
1487 | int rval; | |
e315cd28 | 1488 | struct qla_hw_data *ha = vha->hw; |
73208dfd | 1489 | struct req_que *req = ha->req_q_map[0]; |
0107109e | 1490 | |
7ec0effd | 1491 | if (IS_P3P_TYPE(ha)) |
a9083016 GM |
1492 | return QLA_SUCCESS; |
1493 | ||
73208dfd | 1494 | ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length; |
0107109e | 1495 | |
e315cd28 | 1496 | rval = qla2x00_mbx_reg_test(vha); |
0107109e | 1497 | if (rval) { |
7c3df132 SK |
1498 | ql_log(ql_log_warn, vha, 0x0082, |
1499 | "Failed mailbox send register test.\n"); | |
0107109e AV |
1500 | } else { |
1501 | /* Flag a successful rval */ | |
1502 | rval = QLA_SUCCESS; | |
1503 | } | |
1504 | ||
1505 | return rval; | |
1506 | } | |
1507 | ||
a7a167bf | 1508 | void |
e315cd28 | 1509 | qla2x00_alloc_fw_dump(scsi_qla_host_t *vha) |
0107109e | 1510 | { |
a7a167bf AV |
1511 | int rval; |
1512 | uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size, | |
73208dfd | 1513 | eft_size, fce_size, mq_size; |
df613b96 AV |
1514 | dma_addr_t tc_dma; |
1515 | void *tc; | |
e315cd28 | 1516 | struct qla_hw_data *ha = vha->hw; |
73208dfd AC |
1517 | struct req_que *req = ha->req_q_map[0]; |
1518 | struct rsp_que *rsp = ha->rsp_q_map[0]; | |
a7a167bf AV |
1519 | |
1520 | if (ha->fw_dump) { | |
7c3df132 SK |
1521 | ql_dbg(ql_dbg_init, vha, 0x00bd, |
1522 | "Firmware dump already allocated.\n"); | |
a7a167bf AV |
1523 | return; |
1524 | } | |
d4e3e04d | 1525 | |
0107109e | 1526 | ha->fw_dumped = 0; |
61f098dd | 1527 | ha->fw_dump_cap_flags = 0; |
f73cb695 CD |
1528 | dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0; |
1529 | req_q_size = rsp_q_size = 0; | |
1530 | ||
1531 | if (IS_QLA27XX(ha)) | |
1532 | goto try_fce; | |
1533 | ||
d4e3e04d | 1534 | if (IS_QLA2100(ha) || IS_QLA2200(ha)) { |
a7a167bf | 1535 | fixed_size = sizeof(struct qla2100_fw_dump); |
d4e3e04d | 1536 | } else if (IS_QLA23XX(ha)) { |
a7a167bf AV |
1537 | fixed_size = offsetof(struct qla2300_fw_dump, data_ram); |
1538 | mem_size = (ha->fw_memory_size - 0x11000 + 1) * | |
1539 | sizeof(uint16_t); | |
e428924c | 1540 | } else if (IS_FWI2_CAPABLE(ha)) { |
b20f02e1 | 1541 | if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) |
6246b8a1 GM |
1542 | fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem); |
1543 | else if (IS_QLA81XX(ha)) | |
3a03eb79 AV |
1544 | fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem); |
1545 | else if (IS_QLA25XX(ha)) | |
1546 | fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem); | |
1547 | else | |
1548 | fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem); | |
f73cb695 | 1549 | |
a7a167bf AV |
1550 | mem_size = (ha->fw_memory_size - 0x100000 + 1) * |
1551 | sizeof(uint32_t); | |
050c9bb1 | 1552 | if (ha->mqenable) { |
b20f02e1 | 1553 | if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha)) |
6246b8a1 | 1554 | mq_size = sizeof(struct qla2xxx_mq_chain); |
050c9bb1 GM |
1555 | /* |
1556 | * Allocate maximum buffer size for all queues. | |
1557 | * Resizing must be done at end-of-dump processing. | |
1558 | */ | |
1559 | mq_size += ha->max_req_queues * | |
1560 | (req->length * sizeof(request_t)); | |
1561 | mq_size += ha->max_rsp_queues * | |
1562 | (rsp->length * sizeof(response_t)); | |
1563 | } | |
00876ae8 | 1564 | if (ha->tgt.atio_ring) |
2d70c103 | 1565 | mq_size += ha->tgt.atio_q_length * sizeof(request_t); |
df613b96 | 1566 | /* Allocate memory for Fibre Channel Event Buffer. */ |
f73cb695 CD |
1567 | if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) && |
1568 | !IS_QLA27XX(ha)) | |
436a7b11 | 1569 | goto try_eft; |
df613b96 | 1570 | |
f73cb695 CD |
1571 | try_fce: |
1572 | if (ha->fce) | |
1573 | dma_free_coherent(&ha->pdev->dev, | |
1574 | FCE_SIZE, ha->fce, ha->fce_dma); | |
1575 | ||
1576 | /* Allocate memory for Fibre Channel Event Buffer. */ | |
0ea85b50 JP |
1577 | tc = dma_zalloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma, |
1578 | GFP_KERNEL); | |
df613b96 | 1579 | if (!tc) { |
7c3df132 SK |
1580 | ql_log(ql_log_warn, vha, 0x00be, |
1581 | "Unable to allocate (%d KB) for FCE.\n", | |
1582 | FCE_SIZE / 1024); | |
17d98630 | 1583 | goto try_eft; |
df613b96 AV |
1584 | } |
1585 | ||
e315cd28 | 1586 | rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS, |
df613b96 AV |
1587 | ha->fce_mb, &ha->fce_bufs); |
1588 | if (rval) { | |
7c3df132 SK |
1589 | ql_log(ql_log_warn, vha, 0x00bf, |
1590 | "Unable to initialize FCE (%d).\n", rval); | |
df613b96 AV |
1591 | dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc, |
1592 | tc_dma); | |
1593 | ha->flags.fce_enabled = 0; | |
17d98630 | 1594 | goto try_eft; |
df613b96 | 1595 | } |
cfb0919c | 1596 | ql_dbg(ql_dbg_init, vha, 0x00c0, |
7c3df132 | 1597 | "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024); |
df613b96 | 1598 | |
7d9dade3 | 1599 | fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE; |
df613b96 AV |
1600 | ha->flags.fce_enabled = 1; |
1601 | ha->fce_dma = tc_dma; | |
1602 | ha->fce = tc; | |
f73cb695 | 1603 | |
436a7b11 | 1604 | try_eft: |
f73cb695 CD |
1605 | if (ha->eft) |
1606 | dma_free_coherent(&ha->pdev->dev, | |
1607 | EFT_SIZE, ha->eft, ha->eft_dma); | |
1608 | ||
436a7b11 | 1609 | /* Allocate memory for Extended Trace Buffer. */ |
0ea85b50 JP |
1610 | tc = dma_zalloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma, |
1611 | GFP_KERNEL); | |
436a7b11 | 1612 | if (!tc) { |
7c3df132 SK |
1613 | ql_log(ql_log_warn, vha, 0x00c1, |
1614 | "Unable to allocate (%d KB) for EFT.\n", | |
1615 | EFT_SIZE / 1024); | |
436a7b11 AV |
1616 | goto cont_alloc; |
1617 | } | |
1618 | ||
e315cd28 | 1619 | rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS); |
436a7b11 | 1620 | if (rval) { |
7c3df132 SK |
1621 | ql_log(ql_log_warn, vha, 0x00c2, |
1622 | "Unable to initialize EFT (%d).\n", rval); | |
436a7b11 AV |
1623 | dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc, |
1624 | tc_dma); | |
1625 | goto cont_alloc; | |
1626 | } | |
cfb0919c | 1627 | ql_dbg(ql_dbg_init, vha, 0x00c3, |
7c3df132 | 1628 | "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024); |
436a7b11 AV |
1629 | |
1630 | eft_size = EFT_SIZE; | |
1631 | ha->eft_dma = tc_dma; | |
1632 | ha->eft = tc; | |
d4e3e04d | 1633 | } |
f73cb695 | 1634 | |
a7a167bf | 1635 | cont_alloc: |
f73cb695 CD |
1636 | if (IS_QLA27XX(ha)) { |
1637 | if (!ha->fw_dump_template) { | |
1638 | ql_log(ql_log_warn, vha, 0x00ba, | |
1639 | "Failed missing fwdump template\n"); | |
1640 | return; | |
1641 | } | |
1642 | dump_size = qla27xx_fwdt_calculate_dump_size(vha); | |
1643 | ql_dbg(ql_dbg_init, vha, 0x00fa, | |
1644 | "-> allocating fwdump (%x bytes)...\n", dump_size); | |
1645 | goto allocate; | |
1646 | } | |
1647 | ||
73208dfd AC |
1648 | req_q_size = req->length * sizeof(request_t); |
1649 | rsp_q_size = rsp->length * sizeof(response_t); | |
a7a167bf | 1650 | dump_size = offsetof(struct qla2xxx_fw_dump, isp); |
2afa19a9 | 1651 | dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size; |
bb99de67 AV |
1652 | ha->chain_offset = dump_size; |
1653 | dump_size += mq_size + fce_size; | |
d4e3e04d | 1654 | |
f73cb695 | 1655 | allocate: |
d4e3e04d | 1656 | ha->fw_dump = vmalloc(dump_size); |
a7a167bf | 1657 | if (!ha->fw_dump) { |
7c3df132 SK |
1658 | ql_log(ql_log_warn, vha, 0x00c4, |
1659 | "Unable to allocate (%d KB) for firmware dump.\n", | |
1660 | dump_size / 1024); | |
a7a167bf | 1661 | |
e30d1756 MI |
1662 | if (ha->fce) { |
1663 | dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce, | |
1664 | ha->fce_dma); | |
1665 | ha->fce = NULL; | |
1666 | ha->fce_dma = 0; | |
1667 | } | |
1668 | ||
a7a167bf AV |
1669 | if (ha->eft) { |
1670 | dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft, | |
1671 | ha->eft_dma); | |
1672 | ha->eft = NULL; | |
1673 | ha->eft_dma = 0; | |
1674 | } | |
1675 | return; | |
1676 | } | |
f73cb695 | 1677 | ha->fw_dump_len = dump_size; |
cfb0919c | 1678 | ql_dbg(ql_dbg_init, vha, 0x00c5, |
7c3df132 | 1679 | "Allocated (%d KB) for firmware dump.\n", dump_size / 1024); |
a7a167bf | 1680 | |
f73cb695 CD |
1681 | if (IS_QLA27XX(ha)) |
1682 | return; | |
1683 | ||
a7a167bf AV |
1684 | ha->fw_dump->signature[0] = 'Q'; |
1685 | ha->fw_dump->signature[1] = 'L'; | |
1686 | ha->fw_dump->signature[2] = 'G'; | |
1687 | ha->fw_dump->signature[3] = 'C'; | |
1688 | ha->fw_dump->version = __constant_htonl(1); | |
1689 | ||
1690 | ha->fw_dump->fixed_size = htonl(fixed_size); | |
1691 | ha->fw_dump->mem_size = htonl(mem_size); | |
1692 | ha->fw_dump->req_q_size = htonl(req_q_size); | |
1693 | ha->fw_dump->rsp_q_size = htonl(rsp_q_size); | |
1694 | ||
1695 | ha->fw_dump->eft_size = htonl(eft_size); | |
1696 | ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma)); | |
1697 | ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma)); | |
1698 | ||
1699 | ha->fw_dump->header_size = | |
1700 | htonl(offsetof(struct qla2xxx_fw_dump, isp)); | |
0107109e AV |
1701 | } |
1702 | ||
18e7555a AV |
1703 | static int |
1704 | qla81xx_mpi_sync(scsi_qla_host_t *vha) | |
1705 | { | |
1706 | #define MPS_MASK 0xe0 | |
1707 | int rval; | |
1708 | uint16_t dc; | |
1709 | uint32_t dw; | |
18e7555a AV |
1710 | |
1711 | if (!IS_QLA81XX(vha->hw)) | |
1712 | return QLA_SUCCESS; | |
1713 | ||
1714 | rval = qla2x00_write_ram_word(vha, 0x7c00, 1); | |
1715 | if (rval != QLA_SUCCESS) { | |
7c3df132 SK |
1716 | ql_log(ql_log_warn, vha, 0x0105, |
1717 | "Unable to acquire semaphore.\n"); | |
18e7555a AV |
1718 | goto done; |
1719 | } | |
1720 | ||
1721 | pci_read_config_word(vha->hw->pdev, 0x54, &dc); | |
1722 | rval = qla2x00_read_ram_word(vha, 0x7a15, &dw); | |
1723 | if (rval != QLA_SUCCESS) { | |
7c3df132 | 1724 | ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n"); |
18e7555a AV |
1725 | goto done_release; |
1726 | } | |
1727 | ||
1728 | dc &= MPS_MASK; | |
1729 | if (dc == (dw & MPS_MASK)) | |
1730 | goto done_release; | |
1731 | ||
1732 | dw &= ~MPS_MASK; | |
1733 | dw |= dc; | |
1734 | rval = qla2x00_write_ram_word(vha, 0x7a15, dw); | |
1735 | if (rval != QLA_SUCCESS) { | |
7c3df132 | 1736 | ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n"); |
18e7555a AV |
1737 | } |
1738 | ||
1739 | done_release: | |
1740 | rval = qla2x00_write_ram_word(vha, 0x7c00, 0); | |
1741 | if (rval != QLA_SUCCESS) { | |
7c3df132 SK |
1742 | ql_log(ql_log_warn, vha, 0x006d, |
1743 | "Unable to release semaphore.\n"); | |
18e7555a AV |
1744 | } |
1745 | ||
1746 | done: | |
1747 | return rval; | |
1748 | } | |
1749 | ||
8d93f550 CD |
1750 | int |
1751 | qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req) | |
1752 | { | |
1753 | /* Don't try to reallocate the array */ | |
1754 | if (req->outstanding_cmds) | |
1755 | return QLA_SUCCESS; | |
1756 | ||
1757 | if (!IS_FWI2_CAPABLE(ha) || (ha->mqiobase && | |
1758 | (ql2xmultique_tag || ql2xmaxqueues > 1))) | |
1759 | req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS; | |
1760 | else { | |
1761 | if (ha->fw_xcb_count <= ha->fw_iocb_count) | |
1762 | req->num_outstanding_cmds = ha->fw_xcb_count; | |
1763 | else | |
1764 | req->num_outstanding_cmds = ha->fw_iocb_count; | |
1765 | } | |
1766 | ||
1767 | req->outstanding_cmds = kzalloc(sizeof(srb_t *) * | |
1768 | req->num_outstanding_cmds, GFP_KERNEL); | |
1769 | ||
1770 | if (!req->outstanding_cmds) { | |
1771 | /* | |
1772 | * Try to allocate a minimal size just so we can get through | |
1773 | * initialization. | |
1774 | */ | |
1775 | req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS; | |
1776 | req->outstanding_cmds = kzalloc(sizeof(srb_t *) * | |
1777 | req->num_outstanding_cmds, GFP_KERNEL); | |
1778 | ||
1779 | if (!req->outstanding_cmds) { | |
1780 | ql_log(ql_log_fatal, NULL, 0x0126, | |
1781 | "Failed to allocate memory for " | |
1782 | "outstanding_cmds for req_que %p.\n", req); | |
1783 | req->num_outstanding_cmds = 0; | |
1784 | return QLA_FUNCTION_FAILED; | |
1785 | } | |
1786 | } | |
1787 | ||
1788 | return QLA_SUCCESS; | |
1789 | } | |
1790 | ||
1da177e4 LT |
1791 | /** |
1792 | * qla2x00_setup_chip() - Load and start RISC firmware. | |
1793 | * @ha: HA context | |
1794 | * | |
1795 | * Returns 0 on success. | |
1796 | */ | |
1797 | static int | |
e315cd28 | 1798 | qla2x00_setup_chip(scsi_qla_host_t *vha) |
1da177e4 | 1799 | { |
0107109e AV |
1800 | int rval; |
1801 | uint32_t srisc_address = 0; | |
e315cd28 | 1802 | struct qla_hw_data *ha = vha->hw; |
3db0652e AV |
1803 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1804 | unsigned long flags; | |
dda772e8 | 1805 | uint16_t fw_major_version; |
3db0652e | 1806 | |
7ec0effd | 1807 | if (IS_P3P_TYPE(ha)) { |
a9083016 | 1808 | rval = ha->isp_ops->load_risc(vha, &srisc_address); |
14e303d9 AV |
1809 | if (rval == QLA_SUCCESS) { |
1810 | qla2x00_stop_firmware(vha); | |
a9083016 | 1811 | goto enable_82xx_npiv; |
14e303d9 | 1812 | } else |
b963752f | 1813 | goto failed; |
a9083016 GM |
1814 | } |
1815 | ||
3db0652e AV |
1816 | if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) { |
1817 | /* Disable SRAM, Instruction RAM and GP RAM parity. */ | |
1818 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1819 | WRT_REG_WORD(®->hccr, (HCCR_ENABLE_PARITY + 0x0)); | |
1820 | RD_REG_WORD(®->hccr); | |
1821 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1822 | } | |
1da177e4 | 1823 | |
18e7555a AV |
1824 | qla81xx_mpi_sync(vha); |
1825 | ||
1da177e4 | 1826 | /* Load firmware sequences */ |
e315cd28 | 1827 | rval = ha->isp_ops->load_risc(vha, &srisc_address); |
0107109e | 1828 | if (rval == QLA_SUCCESS) { |
7c3df132 SK |
1829 | ql_dbg(ql_dbg_init, vha, 0x00c9, |
1830 | "Verifying Checksum of loaded RISC code.\n"); | |
1da177e4 | 1831 | |
e315cd28 | 1832 | rval = qla2x00_verify_checksum(vha, srisc_address); |
1da177e4 LT |
1833 | if (rval == QLA_SUCCESS) { |
1834 | /* Start firmware execution. */ | |
7c3df132 SK |
1835 | ql_dbg(ql_dbg_init, vha, 0x00ca, |
1836 | "Starting firmware.\n"); | |
1da177e4 | 1837 | |
e315cd28 | 1838 | rval = qla2x00_execute_fw(vha, srisc_address); |
1da177e4 | 1839 | /* Retrieve firmware information. */ |
dda772e8 | 1840 | if (rval == QLA_SUCCESS) { |
a9083016 | 1841 | enable_82xx_npiv: |
dda772e8 | 1842 | fw_major_version = ha->fw_major_version; |
7ec0effd | 1843 | if (IS_P3P_TYPE(ha)) |
3173167f | 1844 | qla82xx_check_md_needed(vha); |
6246b8a1 GM |
1845 | else |
1846 | rval = qla2x00_get_fw_version(vha); | |
ca9e9c3e AV |
1847 | if (rval != QLA_SUCCESS) |
1848 | goto failed; | |
2c3dfe3f | 1849 | ha->flags.npiv_supported = 0; |
e315cd28 | 1850 | if (IS_QLA2XXX_MIDTYPE(ha) && |
946fb891 | 1851 | (ha->fw_attributes & BIT_2)) { |
2c3dfe3f | 1852 | ha->flags.npiv_supported = 1; |
4d0ea247 SJ |
1853 | if ((!ha->max_npiv_vports) || |
1854 | ((ha->max_npiv_vports + 1) % | |
eb66dc60 | 1855 | MIN_MULTI_ID_FABRIC)) |
4d0ea247 | 1856 | ha->max_npiv_vports = |
eb66dc60 | 1857 | MIN_MULTI_ID_FABRIC - 1; |
4d0ea247 | 1858 | } |
24a08138 | 1859 | qla2x00_get_resource_cnts(vha, NULL, |
8d93f550 | 1860 | &ha->fw_xcb_count, NULL, &ha->fw_iocb_count, |
f3a0a77e | 1861 | &ha->max_npiv_vports, NULL); |
d743de66 | 1862 | |
8d93f550 CD |
1863 | /* |
1864 | * Allocate the array of outstanding commands | |
1865 | * now that we know the firmware resources. | |
1866 | */ | |
1867 | rval = qla2x00_alloc_outstanding_cmds(ha, | |
1868 | vha->req); | |
1869 | if (rval != QLA_SUCCESS) | |
1870 | goto failed; | |
1871 | ||
be5ea3cf | 1872 | if (!fw_major_version && ql2xallocfwdump |
7ec0effd | 1873 | && !(IS_P3P_TYPE(ha))) |
08de2844 | 1874 | qla2x00_alloc_fw_dump(vha); |
3b6e5b9d CD |
1875 | } else { |
1876 | goto failed; | |
1da177e4 LT |
1877 | } |
1878 | } else { | |
7c3df132 SK |
1879 | ql_log(ql_log_fatal, vha, 0x00cd, |
1880 | "ISP Firmware failed checksum.\n"); | |
1881 | goto failed; | |
1da177e4 | 1882 | } |
c74d88a4 AV |
1883 | } else |
1884 | goto failed; | |
1da177e4 | 1885 | |
3db0652e AV |
1886 | if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) { |
1887 | /* Enable proper parity. */ | |
1888 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1889 | if (IS_QLA2300(ha)) | |
1890 | /* SRAM parity */ | |
1891 | WRT_REG_WORD(®->hccr, HCCR_ENABLE_PARITY + 0x1); | |
1892 | else | |
1893 | /* SRAM, Instruction RAM and GP RAM parity */ | |
1894 | WRT_REG_WORD(®->hccr, HCCR_ENABLE_PARITY + 0x7); | |
1895 | RD_REG_WORD(®->hccr); | |
1896 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1897 | } | |
1898 | ||
f3982d89 CD |
1899 | if (IS_QLA27XX(ha)) |
1900 | ha->flags.fac_supported = 1; | |
1901 | else if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) { | |
1d2874de JC |
1902 | uint32_t size; |
1903 | ||
1904 | rval = qla81xx_fac_get_sector_size(vha, &size); | |
1905 | if (rval == QLA_SUCCESS) { | |
1906 | ha->flags.fac_supported = 1; | |
1907 | ha->fdt_block_size = size << 2; | |
1908 | } else { | |
7c3df132 | 1909 | ql_log(ql_log_warn, vha, 0x00ce, |
1d2874de JC |
1910 | "Unsupported FAC firmware (%d.%02d.%02d).\n", |
1911 | ha->fw_major_version, ha->fw_minor_version, | |
1912 | ha->fw_subminor_version); | |
1ca60e3b | 1913 | |
f73cb695 | 1914 | if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) { |
6246b8a1 GM |
1915 | ha->flags.fac_supported = 0; |
1916 | rval = QLA_SUCCESS; | |
1917 | } | |
1d2874de JC |
1918 | } |
1919 | } | |
ca9e9c3e | 1920 | failed: |
1da177e4 | 1921 | if (rval) { |
7c3df132 SK |
1922 | ql_log(ql_log_fatal, vha, 0x00cf, |
1923 | "Setup chip ****FAILED****.\n"); | |
1da177e4 LT |
1924 | } |
1925 | ||
1926 | return (rval); | |
1927 | } | |
1928 | ||
1929 | /** | |
1930 | * qla2x00_init_response_q_entries() - Initializes response queue entries. | |
1931 | * @ha: HA context | |
1932 | * | |
1933 | * Beginning of request ring has initialization control block already built | |
1934 | * by nvram config routine. | |
1935 | * | |
1936 | * Returns 0 on success. | |
1937 | */ | |
73208dfd AC |
1938 | void |
1939 | qla2x00_init_response_q_entries(struct rsp_que *rsp) | |
1da177e4 LT |
1940 | { |
1941 | uint16_t cnt; | |
1942 | response_t *pkt; | |
1943 | ||
2afa19a9 AC |
1944 | rsp->ring_ptr = rsp->ring; |
1945 | rsp->ring_index = 0; | |
1946 | rsp->status_srb = NULL; | |
e315cd28 AC |
1947 | pkt = rsp->ring_ptr; |
1948 | for (cnt = 0; cnt < rsp->length; cnt++) { | |
1da177e4 LT |
1949 | pkt->signature = RESPONSE_PROCESSED; |
1950 | pkt++; | |
1951 | } | |
1da177e4 LT |
1952 | } |
1953 | ||
1954 | /** | |
1955 | * qla2x00_update_fw_options() - Read and process firmware options. | |
1956 | * @ha: HA context | |
1957 | * | |
1958 | * Returns 0 on success. | |
1959 | */ | |
abbd8870 | 1960 | void |
e315cd28 | 1961 | qla2x00_update_fw_options(scsi_qla_host_t *vha) |
1da177e4 LT |
1962 | { |
1963 | uint16_t swing, emphasis, tx_sens, rx_sens; | |
e315cd28 | 1964 | struct qla_hw_data *ha = vha->hw; |
1da177e4 LT |
1965 | |
1966 | memset(ha->fw_options, 0, sizeof(ha->fw_options)); | |
e315cd28 | 1967 | qla2x00_get_fw_options(vha, ha->fw_options); |
1da177e4 LT |
1968 | |
1969 | if (IS_QLA2100(ha) || IS_QLA2200(ha)) | |
1970 | return; | |
1971 | ||
1972 | /* Serial Link options. */ | |
7c3df132 SK |
1973 | ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115, |
1974 | "Serial link options.\n"); | |
1975 | ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109, | |
1976 | (uint8_t *)&ha->fw_seriallink_options, | |
1977 | sizeof(ha->fw_seriallink_options)); | |
1da177e4 LT |
1978 | |
1979 | ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; | |
1980 | if (ha->fw_seriallink_options[3] & BIT_2) { | |
1981 | ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING; | |
1982 | ||
1983 | /* 1G settings */ | |
1984 | swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0); | |
1985 | emphasis = (ha->fw_seriallink_options[2] & | |
1986 | (BIT_4 | BIT_3)) >> 3; | |
1987 | tx_sens = ha->fw_seriallink_options[0] & | |
fa2a1ce5 | 1988 | (BIT_3 | BIT_2 | BIT_1 | BIT_0); |
1da177e4 LT |
1989 | rx_sens = (ha->fw_seriallink_options[0] & |
1990 | (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4; | |
1991 | ha->fw_options[10] = (emphasis << 14) | (swing << 8); | |
1992 | if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { | |
1993 | if (rx_sens == 0x0) | |
1994 | rx_sens = 0x3; | |
1995 | ha->fw_options[10] |= (tx_sens << 4) | rx_sens; | |
1996 | } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) | |
1997 | ha->fw_options[10] |= BIT_5 | | |
1998 | ((rx_sens & (BIT_1 | BIT_0)) << 2) | | |
1999 | (tx_sens & (BIT_1 | BIT_0)); | |
2000 | ||
2001 | /* 2G settings */ | |
2002 | swing = (ha->fw_seriallink_options[2] & | |
2003 | (BIT_7 | BIT_6 | BIT_5)) >> 5; | |
2004 | emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0); | |
2005 | tx_sens = ha->fw_seriallink_options[1] & | |
fa2a1ce5 | 2006 | (BIT_3 | BIT_2 | BIT_1 | BIT_0); |
1da177e4 LT |
2007 | rx_sens = (ha->fw_seriallink_options[1] & |
2008 | (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4; | |
2009 | ha->fw_options[11] = (emphasis << 14) | (swing << 8); | |
2010 | if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { | |
2011 | if (rx_sens == 0x0) | |
2012 | rx_sens = 0x3; | |
2013 | ha->fw_options[11] |= (tx_sens << 4) | rx_sens; | |
2014 | } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) | |
2015 | ha->fw_options[11] |= BIT_5 | | |
2016 | ((rx_sens & (BIT_1 | BIT_0)) << 2) | | |
2017 | (tx_sens & (BIT_1 | BIT_0)); | |
2018 | } | |
2019 | ||
2020 | /* FCP2 options. */ | |
2021 | /* Return command IOCBs without waiting for an ABTS to complete. */ | |
2022 | ha->fw_options[3] |= BIT_13; | |
2023 | ||
2024 | /* LED scheme. */ | |
2025 | if (ha->flags.enable_led_scheme) | |
2026 | ha->fw_options[2] |= BIT_12; | |
2027 | ||
48c02fde | 2028 | /* Detect ISP6312. */ |
2029 | if (IS_QLA6312(ha)) | |
2030 | ha->fw_options[2] |= BIT_13; | |
2031 | ||
1da177e4 | 2032 | /* Update firmware options. */ |
e315cd28 | 2033 | qla2x00_set_fw_options(vha, ha->fw_options); |
1da177e4 LT |
2034 | } |
2035 | ||
0107109e | 2036 | void |
e315cd28 | 2037 | qla24xx_update_fw_options(scsi_qla_host_t *vha) |
0107109e AV |
2038 | { |
2039 | int rval; | |
e315cd28 | 2040 | struct qla_hw_data *ha = vha->hw; |
0107109e | 2041 | |
7ec0effd | 2042 | if (IS_P3P_TYPE(ha)) |
a9083016 GM |
2043 | return; |
2044 | ||
0107109e | 2045 | /* Update Serial Link options. */ |
f94097ed | 2046 | if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0) |
0107109e AV |
2047 | return; |
2048 | ||
e315cd28 | 2049 | rval = qla2x00_set_serdes_params(vha, |
f94097ed | 2050 | le16_to_cpu(ha->fw_seriallink_options24[1]), |
2051 | le16_to_cpu(ha->fw_seriallink_options24[2]), | |
2052 | le16_to_cpu(ha->fw_seriallink_options24[3])); | |
0107109e | 2053 | if (rval != QLA_SUCCESS) { |
7c3df132 | 2054 | ql_log(ql_log_warn, vha, 0x0104, |
0107109e AV |
2055 | "Unable to update Serial Link options (%x).\n", rval); |
2056 | } | |
2057 | } | |
2058 | ||
abbd8870 | 2059 | void |
e315cd28 | 2060 | qla2x00_config_rings(struct scsi_qla_host *vha) |
abbd8870 | 2061 | { |
e315cd28 | 2062 | struct qla_hw_data *ha = vha->hw; |
3d71644c | 2063 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
73208dfd AC |
2064 | struct req_que *req = ha->req_q_map[0]; |
2065 | struct rsp_que *rsp = ha->rsp_q_map[0]; | |
abbd8870 AV |
2066 | |
2067 | /* Setup ring parameters in initialization control block. */ | |
2068 | ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0); | |
2069 | ha->init_cb->response_q_inpointer = __constant_cpu_to_le16(0); | |
e315cd28 AC |
2070 | ha->init_cb->request_q_length = cpu_to_le16(req->length); |
2071 | ha->init_cb->response_q_length = cpu_to_le16(rsp->length); | |
2072 | ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma)); | |
2073 | ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma)); | |
2074 | ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); | |
2075 | ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); | |
abbd8870 AV |
2076 | |
2077 | WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0); | |
2078 | WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0); | |
2079 | WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0); | |
2080 | WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0); | |
2081 | RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */ | |
2082 | } | |
2083 | ||
0107109e | 2084 | void |
e315cd28 | 2085 | qla24xx_config_rings(struct scsi_qla_host *vha) |
0107109e | 2086 | { |
e315cd28 | 2087 | struct qla_hw_data *ha = vha->hw; |
73208dfd AC |
2088 | device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0); |
2089 | struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp; | |
2090 | struct qla_msix_entry *msix; | |
0107109e | 2091 | struct init_cb_24xx *icb; |
73208dfd AC |
2092 | uint16_t rid = 0; |
2093 | struct req_que *req = ha->req_q_map[0]; | |
2094 | struct rsp_que *rsp = ha->rsp_q_map[0]; | |
0107109e | 2095 | |
6246b8a1 | 2096 | /* Setup ring parameters in initialization control block. */ |
0107109e AV |
2097 | icb = (struct init_cb_24xx *)ha->init_cb; |
2098 | icb->request_q_outpointer = __constant_cpu_to_le16(0); | |
2099 | icb->response_q_inpointer = __constant_cpu_to_le16(0); | |
e315cd28 AC |
2100 | icb->request_q_length = cpu_to_le16(req->length); |
2101 | icb->response_q_length = cpu_to_le16(rsp->length); | |
2102 | icb->request_q_address[0] = cpu_to_le32(LSD(req->dma)); | |
2103 | icb->request_q_address[1] = cpu_to_le32(MSD(req->dma)); | |
2104 | icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); | |
2105 | icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); | |
0107109e | 2106 | |
2d70c103 NB |
2107 | /* Setup ATIO queue dma pointers for target mode */ |
2108 | icb->atio_q_inpointer = __constant_cpu_to_le16(0); | |
2109 | icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length); | |
2110 | icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma)); | |
2111 | icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma)); | |
2112 | ||
7c6300e3 JC |
2113 | if (IS_SHADOW_REG_CAPABLE(ha)) |
2114 | icb->firmware_options_2 |= | |
2115 | __constant_cpu_to_le32(BIT_30|BIT_29); | |
2116 | ||
f73cb695 | 2117 | if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) { |
73208dfd AC |
2118 | icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS); |
2119 | icb->rid = __constant_cpu_to_le16(rid); | |
2120 | if (ha->flags.msix_enabled) { | |
2121 | msix = &ha->msix_entries[1]; | |
7c3df132 SK |
2122 | ql_dbg(ql_dbg_init, vha, 0x00fd, |
2123 | "Registering vector 0x%x for base que.\n", | |
2124 | msix->entry); | |
73208dfd AC |
2125 | icb->msix = cpu_to_le16(msix->entry); |
2126 | } | |
2127 | /* Use alternate PCI bus number */ | |
2128 | if (MSB(rid)) | |
2129 | icb->firmware_options_2 |= | |
2130 | __constant_cpu_to_le32(BIT_19); | |
2131 | /* Use alternate PCI devfn */ | |
2132 | if (LSB(rid)) | |
2133 | icb->firmware_options_2 |= | |
2134 | __constant_cpu_to_le32(BIT_18); | |
2135 | ||
3155754a | 2136 | /* Use Disable MSIX Handshake mode for capable adapters */ |
6246b8a1 GM |
2137 | if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) && |
2138 | (ha->flags.msix_enabled)) { | |
3155754a AC |
2139 | icb->firmware_options_2 &= |
2140 | __constant_cpu_to_le32(~BIT_22); | |
2141 | ha->flags.disable_msix_handshake = 1; | |
7c3df132 SK |
2142 | ql_dbg(ql_dbg_init, vha, 0x00fe, |
2143 | "MSIX Handshake Disable Mode turned on.\n"); | |
3155754a AC |
2144 | } else { |
2145 | icb->firmware_options_2 |= | |
2146 | __constant_cpu_to_le32(BIT_22); | |
2147 | } | |
73208dfd | 2148 | icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_23); |
73208dfd AC |
2149 | |
2150 | WRT_REG_DWORD(®->isp25mq.req_q_in, 0); | |
2151 | WRT_REG_DWORD(®->isp25mq.req_q_out, 0); | |
2152 | WRT_REG_DWORD(®->isp25mq.rsp_q_in, 0); | |
2153 | WRT_REG_DWORD(®->isp25mq.rsp_q_out, 0); | |
2154 | } else { | |
2155 | WRT_REG_DWORD(®->isp24.req_q_in, 0); | |
2156 | WRT_REG_DWORD(®->isp24.req_q_out, 0); | |
2157 | WRT_REG_DWORD(®->isp24.rsp_q_in, 0); | |
2158 | WRT_REG_DWORD(®->isp24.rsp_q_out, 0); | |
2159 | } | |
aa230bc5 | 2160 | qlt_24xx_config_rings(vha); |
2d70c103 | 2161 | |
73208dfd AC |
2162 | /* PCI posting */ |
2163 | RD_REG_DWORD(&ioreg->hccr); | |
0107109e AV |
2164 | } |
2165 | ||
1da177e4 LT |
2166 | /** |
2167 | * qla2x00_init_rings() - Initializes firmware. | |
2168 | * @ha: HA context | |
2169 | * | |
2170 | * Beginning of request ring has initialization control block already built | |
2171 | * by nvram config routine. | |
2172 | * | |
2173 | * Returns 0 on success. | |
2174 | */ | |
8ae6d9c7 | 2175 | int |
e315cd28 | 2176 | qla2x00_init_rings(scsi_qla_host_t *vha) |
1da177e4 LT |
2177 | { |
2178 | int rval; | |
2179 | unsigned long flags = 0; | |
29bdccbe | 2180 | int cnt, que; |
e315cd28 | 2181 | struct qla_hw_data *ha = vha->hw; |
29bdccbe AC |
2182 | struct req_que *req; |
2183 | struct rsp_que *rsp; | |
2c3dfe3f SJ |
2184 | struct mid_init_cb_24xx *mid_init_cb = |
2185 | (struct mid_init_cb_24xx *) ha->init_cb; | |
1da177e4 LT |
2186 | |
2187 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
2188 | ||
2189 | /* Clear outstanding commands array. */ | |
2afa19a9 | 2190 | for (que = 0; que < ha->max_req_queues; que++) { |
29bdccbe AC |
2191 | req = ha->req_q_map[que]; |
2192 | if (!req) | |
2193 | continue; | |
7c6300e3 JC |
2194 | req->out_ptr = (void *)(req->ring + req->length); |
2195 | *req->out_ptr = 0; | |
8d93f550 | 2196 | for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) |
29bdccbe | 2197 | req->outstanding_cmds[cnt] = NULL; |
1da177e4 | 2198 | |
2afa19a9 | 2199 | req->current_outstanding_cmd = 1; |
1da177e4 | 2200 | |
29bdccbe AC |
2201 | /* Initialize firmware. */ |
2202 | req->ring_ptr = req->ring; | |
2203 | req->ring_index = 0; | |
2204 | req->cnt = req->length; | |
2205 | } | |
1da177e4 | 2206 | |
2afa19a9 | 2207 | for (que = 0; que < ha->max_rsp_queues; que++) { |
29bdccbe AC |
2208 | rsp = ha->rsp_q_map[que]; |
2209 | if (!rsp) | |
2210 | continue; | |
7c6300e3 JC |
2211 | rsp->in_ptr = (void *)(rsp->ring + rsp->length); |
2212 | *rsp->in_ptr = 0; | |
29bdccbe | 2213 | /* Initialize response queue entries */ |
8ae6d9c7 GM |
2214 | if (IS_QLAFX00(ha)) |
2215 | qlafx00_init_response_q_entries(rsp); | |
2216 | else | |
2217 | qla2x00_init_response_q_entries(rsp); | |
29bdccbe | 2218 | } |
1da177e4 | 2219 | |
2d70c103 NB |
2220 | ha->tgt.atio_ring_ptr = ha->tgt.atio_ring; |
2221 | ha->tgt.atio_ring_index = 0; | |
2222 | /* Initialize ATIO queue entries */ | |
2223 | qlt_init_atio_q_entries(vha); | |
2224 | ||
e315cd28 | 2225 | ha->isp_ops->config_rings(vha); |
1da177e4 LT |
2226 | |
2227 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
2228 | ||
8ae6d9c7 GM |
2229 | ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n"); |
2230 | ||
2231 | if (IS_QLAFX00(ha)) { | |
2232 | rval = qlafx00_init_firmware(vha, ha->init_cb_size); | |
2233 | goto next_check; | |
2234 | } | |
2235 | ||
1da177e4 | 2236 | /* Update any ISP specific firmware options before initialization. */ |
e315cd28 | 2237 | ha->isp_ops->update_fw_options(vha); |
1da177e4 | 2238 | |
605aa2bc | 2239 | if (ha->flags.npiv_supported) { |
45980cc2 | 2240 | if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha)) |
605aa2bc | 2241 | ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1; |
c48339de | 2242 | mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports); |
605aa2bc LC |
2243 | } |
2244 | ||
24a08138 AV |
2245 | if (IS_FWI2_CAPABLE(ha)) { |
2246 | mid_init_cb->options = __constant_cpu_to_le16(BIT_1); | |
2247 | mid_init_cb->init_cb.execution_throttle = | |
2248 | cpu_to_le16(ha->fw_xcb_count); | |
25232cc9 HM |
2249 | /* D-Port Status */ |
2250 | if (IS_DPORT_CAPABLE(ha)) | |
2251 | mid_init_cb->init_cb.firmware_options_1 |= | |
2252 | cpu_to_le16(BIT_7); | |
2486c627 HM |
2253 | /* Enable FA-WWPN */ |
2254 | ha->flags.fawwpn_enabled = | |
2255 | (mid_init_cb->init_cb.firmware_options_1 & BIT_6) ? 1 : 0; | |
2256 | ql_dbg(ql_dbg_init, vha, 0x0141, "FA-WWPN Support: %s.\n", | |
2257 | (ha->flags.fawwpn_enabled) ? "enabled" : "disabled"); | |
24a08138 | 2258 | } |
2c3dfe3f | 2259 | |
e315cd28 | 2260 | rval = qla2x00_init_firmware(vha, ha->init_cb_size); |
8ae6d9c7 | 2261 | next_check: |
1da177e4 | 2262 | if (rval) { |
7c3df132 SK |
2263 | ql_log(ql_log_fatal, vha, 0x00d2, |
2264 | "Init Firmware **** FAILED ****.\n"); | |
1da177e4 | 2265 | } else { |
7c3df132 SK |
2266 | ql_dbg(ql_dbg_init, vha, 0x00d3, |
2267 | "Init Firmware -- success.\n"); | |
1da177e4 LT |
2268 | } |
2269 | ||
2270 | return (rval); | |
2271 | } | |
2272 | ||
2273 | /** | |
2274 | * qla2x00_fw_ready() - Waits for firmware ready. | |
2275 | * @ha: HA context | |
2276 | * | |
2277 | * Returns 0 on success. | |
2278 | */ | |
2279 | static int | |
e315cd28 | 2280 | qla2x00_fw_ready(scsi_qla_host_t *vha) |
1da177e4 LT |
2281 | { |
2282 | int rval; | |
4d4df193 | 2283 | unsigned long wtime, mtime, cs84xx_time; |
1da177e4 LT |
2284 | uint16_t min_wait; /* Minimum wait time if loop is down */ |
2285 | uint16_t wait_time; /* Wait time if loop is coming ready */ | |
b5a340dd | 2286 | uint16_t state[6]; |
e315cd28 | 2287 | struct qla_hw_data *ha = vha->hw; |
1da177e4 | 2288 | |
8ae6d9c7 GM |
2289 | if (IS_QLAFX00(vha->hw)) |
2290 | return qlafx00_fw_ready(vha); | |
2291 | ||
1da177e4 LT |
2292 | rval = QLA_SUCCESS; |
2293 | ||
33461491 CD |
2294 | /* Time to wait for loop down */ |
2295 | if (IS_P3P_TYPE(ha)) | |
2296 | min_wait = 30; | |
2297 | else | |
2298 | min_wait = 20; | |
1da177e4 LT |
2299 | |
2300 | /* | |
2301 | * Firmware should take at most one RATOV to login, plus 5 seconds for | |
2302 | * our own processing. | |
2303 | */ | |
2304 | if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) { | |
2305 | wait_time = min_wait; | |
2306 | } | |
2307 | ||
2308 | /* Min wait time if loop down */ | |
2309 | mtime = jiffies + (min_wait * HZ); | |
2310 | ||
2311 | /* wait time before firmware ready */ | |
2312 | wtime = jiffies + (wait_time * HZ); | |
2313 | ||
2314 | /* Wait for ISP to finish LIP */ | |
e315cd28 | 2315 | if (!vha->flags.init_done) |
7c3df132 SK |
2316 | ql_log(ql_log_info, vha, 0x801e, |
2317 | "Waiting for LIP to complete.\n"); | |
1da177e4 LT |
2318 | |
2319 | do { | |
5b939038 | 2320 | memset(state, -1, sizeof(state)); |
e315cd28 | 2321 | rval = qla2x00_get_firmware_state(vha, state); |
1da177e4 | 2322 | if (rval == QLA_SUCCESS) { |
4d4df193 | 2323 | if (state[0] < FSTATE_LOSS_OF_SYNC) { |
e315cd28 | 2324 | vha->device_flags &= ~DFLG_NO_CABLE; |
1da177e4 | 2325 | } |
4d4df193 | 2326 | if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) { |
7c3df132 SK |
2327 | ql_dbg(ql_dbg_taskm, vha, 0x801f, |
2328 | "fw_state=%x 84xx=%x.\n", state[0], | |
2329 | state[2]); | |
4d4df193 HK |
2330 | if ((state[2] & FSTATE_LOGGED_IN) && |
2331 | (state[2] & FSTATE_WAITING_FOR_VERIFY)) { | |
7c3df132 SK |
2332 | ql_dbg(ql_dbg_taskm, vha, 0x8028, |
2333 | "Sending verify iocb.\n"); | |
4d4df193 HK |
2334 | |
2335 | cs84xx_time = jiffies; | |
e315cd28 | 2336 | rval = qla84xx_init_chip(vha); |
7c3df132 SK |
2337 | if (rval != QLA_SUCCESS) { |
2338 | ql_log(ql_log_warn, | |
cfb0919c | 2339 | vha, 0x8007, |
7c3df132 | 2340 | "Init chip failed.\n"); |
4d4df193 | 2341 | break; |
7c3df132 | 2342 | } |
4d4df193 HK |
2343 | |
2344 | /* Add time taken to initialize. */ | |
2345 | cs84xx_time = jiffies - cs84xx_time; | |
2346 | wtime += cs84xx_time; | |
2347 | mtime += cs84xx_time; | |
cfb0919c | 2348 | ql_dbg(ql_dbg_taskm, vha, 0x8008, |
7c3df132 SK |
2349 | "Increasing wait time by %ld. " |
2350 | "New time %ld.\n", cs84xx_time, | |
2351 | wtime); | |
4d4df193 HK |
2352 | } |
2353 | } else if (state[0] == FSTATE_READY) { | |
7c3df132 SK |
2354 | ql_dbg(ql_dbg_taskm, vha, 0x8037, |
2355 | "F/W Ready - OK.\n"); | |
1da177e4 | 2356 | |
e315cd28 | 2357 | qla2x00_get_retry_cnt(vha, &ha->retry_count, |
1da177e4 LT |
2358 | &ha->login_timeout, &ha->r_a_tov); |
2359 | ||
2360 | rval = QLA_SUCCESS; | |
2361 | break; | |
2362 | } | |
2363 | ||
2364 | rval = QLA_FUNCTION_FAILED; | |
2365 | ||
e315cd28 | 2366 | if (atomic_read(&vha->loop_down_timer) && |
4d4df193 | 2367 | state[0] != FSTATE_READY) { |
1da177e4 | 2368 | /* Loop down. Timeout on min_wait for states |
fa2a1ce5 AV |
2369 | * other than Wait for Login. |
2370 | */ | |
1da177e4 | 2371 | if (time_after_eq(jiffies, mtime)) { |
7c3df132 | 2372 | ql_log(ql_log_info, vha, 0x8038, |
1da177e4 LT |
2373 | "Cable is unplugged...\n"); |
2374 | ||
e315cd28 | 2375 | vha->device_flags |= DFLG_NO_CABLE; |
1da177e4 LT |
2376 | break; |
2377 | } | |
2378 | } | |
2379 | } else { | |
2380 | /* Mailbox cmd failed. Timeout on min_wait. */ | |
cdbb0a4f | 2381 | if (time_after_eq(jiffies, mtime) || |
7190575f | 2382 | ha->flags.isp82xx_fw_hung) |
1da177e4 LT |
2383 | break; |
2384 | } | |
2385 | ||
2386 | if (time_after_eq(jiffies, wtime)) | |
2387 | break; | |
2388 | ||
2389 | /* Delay for a while */ | |
2390 | msleep(500); | |
1da177e4 LT |
2391 | } while (1); |
2392 | ||
7c3df132 | 2393 | ql_dbg(ql_dbg_taskm, vha, 0x803a, |
b5a340dd JC |
2394 | "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0], |
2395 | state[1], state[2], state[3], state[4], state[5], jiffies); | |
1da177e4 | 2396 | |
cfb0919c | 2397 | if (rval && !(vha->device_flags & DFLG_NO_CABLE)) { |
7c3df132 SK |
2398 | ql_log(ql_log_warn, vha, 0x803b, |
2399 | "Firmware ready **** FAILED ****.\n"); | |
1da177e4 LT |
2400 | } |
2401 | ||
2402 | return (rval); | |
2403 | } | |
2404 | ||
2405 | /* | |
2406 | * qla2x00_configure_hba | |
2407 | * Setup adapter context. | |
2408 | * | |
2409 | * Input: | |
2410 | * ha = adapter state pointer. | |
2411 | * | |
2412 | * Returns: | |
2413 | * 0 = success | |
2414 | * | |
2415 | * Context: | |
2416 | * Kernel context. | |
2417 | */ | |
2418 | static int | |
e315cd28 | 2419 | qla2x00_configure_hba(scsi_qla_host_t *vha) |
1da177e4 LT |
2420 | { |
2421 | int rval; | |
2422 | uint16_t loop_id; | |
2423 | uint16_t topo; | |
2c3dfe3f | 2424 | uint16_t sw_cap; |
1da177e4 LT |
2425 | uint8_t al_pa; |
2426 | uint8_t area; | |
2427 | uint8_t domain; | |
2428 | char connect_type[22]; | |
e315cd28 | 2429 | struct qla_hw_data *ha = vha->hw; |
f24b5cb8 | 2430 | unsigned long flags; |
61e1b269 | 2431 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); |
1da177e4 LT |
2432 | |
2433 | /* Get host addresses. */ | |
e315cd28 | 2434 | rval = qla2x00_get_adapter_id(vha, |
2c3dfe3f | 2435 | &loop_id, &al_pa, &area, &domain, &topo, &sw_cap); |
1da177e4 | 2436 | if (rval != QLA_SUCCESS) { |
e315cd28 | 2437 | if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) || |
6246b8a1 | 2438 | IS_CNA_CAPABLE(ha) || |
33135aa2 | 2439 | (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) { |
7c3df132 SK |
2440 | ql_dbg(ql_dbg_disc, vha, 0x2008, |
2441 | "Loop is in a transition state.\n"); | |
33135aa2 | 2442 | } else { |
7c3df132 SK |
2443 | ql_log(ql_log_warn, vha, 0x2009, |
2444 | "Unable to get host loop ID.\n"); | |
61e1b269 JC |
2445 | if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) && |
2446 | (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) { | |
2447 | ql_log(ql_log_warn, vha, 0x1151, | |
2448 | "Doing link init.\n"); | |
2449 | if (qla24xx_link_initialize(vha) == QLA_SUCCESS) | |
2450 | return rval; | |
2451 | } | |
e315cd28 | 2452 | set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); |
33135aa2 | 2453 | } |
1da177e4 LT |
2454 | return (rval); |
2455 | } | |
2456 | ||
2457 | if (topo == 4) { | |
7c3df132 SK |
2458 | ql_log(ql_log_info, vha, 0x200a, |
2459 | "Cannot get topology - retrying.\n"); | |
1da177e4 LT |
2460 | return (QLA_FUNCTION_FAILED); |
2461 | } | |
2462 | ||
e315cd28 | 2463 | vha->loop_id = loop_id; |
1da177e4 LT |
2464 | |
2465 | /* initialize */ | |
2466 | ha->min_external_loopid = SNS_FIRST_LOOP_ID; | |
2467 | ha->operating_mode = LOOP; | |
2c3dfe3f | 2468 | ha->switch_cap = 0; |
1da177e4 LT |
2469 | |
2470 | switch (topo) { | |
2471 | case 0: | |
7c3df132 | 2472 | ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n"); |
1da177e4 LT |
2473 | ha->current_topology = ISP_CFG_NL; |
2474 | strcpy(connect_type, "(Loop)"); | |
2475 | break; | |
2476 | ||
2477 | case 1: | |
7c3df132 | 2478 | ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n"); |
2c3dfe3f | 2479 | ha->switch_cap = sw_cap; |
1da177e4 LT |
2480 | ha->current_topology = ISP_CFG_FL; |
2481 | strcpy(connect_type, "(FL_Port)"); | |
2482 | break; | |
2483 | ||
2484 | case 2: | |
7c3df132 | 2485 | ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n"); |
1da177e4 LT |
2486 | ha->operating_mode = P2P; |
2487 | ha->current_topology = ISP_CFG_N; | |
2488 | strcpy(connect_type, "(N_Port-to-N_Port)"); | |
2489 | break; | |
2490 | ||
2491 | case 3: | |
7c3df132 | 2492 | ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n"); |
2c3dfe3f | 2493 | ha->switch_cap = sw_cap; |
1da177e4 LT |
2494 | ha->operating_mode = P2P; |
2495 | ha->current_topology = ISP_CFG_F; | |
2496 | strcpy(connect_type, "(F_Port)"); | |
2497 | break; | |
2498 | ||
2499 | default: | |
7c3df132 SK |
2500 | ql_dbg(ql_dbg_disc, vha, 0x200f, |
2501 | "HBA in unknown topology %x, using NL.\n", topo); | |
1da177e4 LT |
2502 | ha->current_topology = ISP_CFG_NL; |
2503 | strcpy(connect_type, "(Loop)"); | |
2504 | break; | |
2505 | } | |
2506 | ||
2507 | /* Save Host port and loop ID. */ | |
2508 | /* byte order - Big Endian */ | |
e315cd28 AC |
2509 | vha->d_id.b.domain = domain; |
2510 | vha->d_id.b.area = area; | |
2511 | vha->d_id.b.al_pa = al_pa; | |
1da177e4 | 2512 | |
f24b5cb8 | 2513 | spin_lock_irqsave(&ha->vport_slock, flags); |
2d70c103 | 2514 | qlt_update_vp_map(vha, SET_AL_PA); |
f24b5cb8 | 2515 | spin_unlock_irqrestore(&ha->vport_slock, flags); |
2d70c103 | 2516 | |
e315cd28 | 2517 | if (!vha->flags.init_done) |
7c3df132 SK |
2518 | ql_log(ql_log_info, vha, 0x2010, |
2519 | "Topology - %s, Host Loop address 0x%x.\n", | |
e315cd28 | 2520 | connect_type, vha->loop_id); |
1da177e4 | 2521 | |
1da177e4 LT |
2522 | return(rval); |
2523 | } | |
2524 | ||
a9083016 | 2525 | inline void |
e315cd28 AC |
2526 | qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len, |
2527 | char *def) | |
9bb9fcf2 AV |
2528 | { |
2529 | char *st, *en; | |
2530 | uint16_t index; | |
e315cd28 | 2531 | struct qla_hw_data *ha = vha->hw; |
ab671149 | 2532 | int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && |
6246b8a1 | 2533 | !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha); |
9bb9fcf2 AV |
2534 | |
2535 | if (memcmp(model, BINZERO, len) != 0) { | |
2536 | strncpy(ha->model_number, model, len); | |
2537 | st = en = ha->model_number; | |
2538 | en += len - 1; | |
2539 | while (en > st) { | |
2540 | if (*en != 0x20 && *en != 0x00) | |
2541 | break; | |
2542 | *en-- = '\0'; | |
2543 | } | |
2544 | ||
2545 | index = (ha->pdev->subsystem_device & 0xff); | |
7d0dba17 AV |
2546 | if (use_tbl && |
2547 | ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC && | |
9bb9fcf2 | 2548 | index < QLA_MODEL_NAMES) |
1ee27146 JC |
2549 | strncpy(ha->model_desc, |
2550 | qla2x00_model_name[index * 2 + 1], | |
2551 | sizeof(ha->model_desc) - 1); | |
9bb9fcf2 AV |
2552 | } else { |
2553 | index = (ha->pdev->subsystem_device & 0xff); | |
7d0dba17 AV |
2554 | if (use_tbl && |
2555 | ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC && | |
9bb9fcf2 AV |
2556 | index < QLA_MODEL_NAMES) { |
2557 | strcpy(ha->model_number, | |
2558 | qla2x00_model_name[index * 2]); | |
1ee27146 JC |
2559 | strncpy(ha->model_desc, |
2560 | qla2x00_model_name[index * 2 + 1], | |
2561 | sizeof(ha->model_desc) - 1); | |
9bb9fcf2 AV |
2562 | } else { |
2563 | strcpy(ha->model_number, def); | |
2564 | } | |
2565 | } | |
1ee27146 | 2566 | if (IS_FWI2_CAPABLE(ha)) |
e315cd28 | 2567 | qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc, |
1ee27146 | 2568 | sizeof(ha->model_desc)); |
9bb9fcf2 AV |
2569 | } |
2570 | ||
4e08df3f DM |
2571 | /* On sparc systems, obtain port and node WWN from firmware |
2572 | * properties. | |
2573 | */ | |
e315cd28 | 2574 | static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv) |
4e08df3f DM |
2575 | { |
2576 | #ifdef CONFIG_SPARC | |
e315cd28 | 2577 | struct qla_hw_data *ha = vha->hw; |
4e08df3f | 2578 | struct pci_dev *pdev = ha->pdev; |
15576bc8 DM |
2579 | struct device_node *dp = pci_device_to_OF_node(pdev); |
2580 | const u8 *val; | |
4e08df3f DM |
2581 | int len; |
2582 | ||
2583 | val = of_get_property(dp, "port-wwn", &len); | |
2584 | if (val && len >= WWN_SIZE) | |
2585 | memcpy(nv->port_name, val, WWN_SIZE); | |
2586 | ||
2587 | val = of_get_property(dp, "node-wwn", &len); | |
2588 | if (val && len >= WWN_SIZE) | |
2589 | memcpy(nv->node_name, val, WWN_SIZE); | |
2590 | #endif | |
2591 | } | |
2592 | ||
1da177e4 LT |
2593 | /* |
2594 | * NVRAM configuration for ISP 2xxx | |
2595 | * | |
2596 | * Input: | |
2597 | * ha = adapter block pointer. | |
2598 | * | |
2599 | * Output: | |
2600 | * initialization control block in response_ring | |
2601 | * host adapters parameters in host adapter block | |
2602 | * | |
2603 | * Returns: | |
2604 | * 0 = success. | |
2605 | */ | |
abbd8870 | 2606 | int |
e315cd28 | 2607 | qla2x00_nvram_config(scsi_qla_host_t *vha) |
1da177e4 | 2608 | { |
4e08df3f | 2609 | int rval; |
0107109e AV |
2610 | uint8_t chksum = 0; |
2611 | uint16_t cnt; | |
2612 | uint8_t *dptr1, *dptr2; | |
e315cd28 | 2613 | struct qla_hw_data *ha = vha->hw; |
0107109e | 2614 | init_cb_t *icb = ha->init_cb; |
281afe19 SJ |
2615 | nvram_t *nv = ha->nvram; |
2616 | uint8_t *ptr = ha->nvram; | |
3d71644c | 2617 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 | 2618 | |
4e08df3f DM |
2619 | rval = QLA_SUCCESS; |
2620 | ||
1da177e4 | 2621 | /* Determine NVRAM starting address. */ |
0107109e | 2622 | ha->nvram_size = sizeof(nvram_t); |
1da177e4 LT |
2623 | ha->nvram_base = 0; |
2624 | if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) | |
2625 | if ((RD_REG_WORD(®->ctrl_status) >> 14) == 1) | |
2626 | ha->nvram_base = 0x80; | |
2627 | ||
2628 | /* Get NVRAM data and calculate checksum. */ | |
e315cd28 | 2629 | ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size); |
0107109e AV |
2630 | for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++) |
2631 | chksum += *ptr++; | |
1da177e4 | 2632 | |
7c3df132 SK |
2633 | ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f, |
2634 | "Contents of NVRAM.\n"); | |
2635 | ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110, | |
2636 | (uint8_t *)nv, ha->nvram_size); | |
1da177e4 LT |
2637 | |
2638 | /* Bad NVRAM data, set defaults parameters. */ | |
2639 | if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || | |
2640 | nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) { | |
2641 | /* Reset NVRAM data. */ | |
7c3df132 | 2642 | ql_log(ql_log_warn, vha, 0x0064, |
9e336520 | 2643 | "Inconsistent NVRAM " |
7c3df132 SK |
2644 | "detected: checksum=0x%x id=%c version=0x%x.\n", |
2645 | chksum, nv->id[0], nv->nvram_version); | |
2646 | ql_log(ql_log_warn, vha, 0x0065, | |
2647 | "Falling back to " | |
2648 | "functioning (yet invalid -- WWPN) defaults.\n"); | |
4e08df3f DM |
2649 | |
2650 | /* | |
2651 | * Set default initialization control block. | |
2652 | */ | |
2653 | memset(nv, 0, ha->nvram_size); | |
2654 | nv->parameter_block_version = ICB_VERSION; | |
2655 | ||
2656 | if (IS_QLA23XX(ha)) { | |
2657 | nv->firmware_options[0] = BIT_2 | BIT_1; | |
2658 | nv->firmware_options[1] = BIT_7 | BIT_5; | |
2659 | nv->add_firmware_options[0] = BIT_5; | |
2660 | nv->add_firmware_options[1] = BIT_5 | BIT_4; | |
98aee70d | 2661 | nv->frame_payload_size = 2048; |
4e08df3f DM |
2662 | nv->special_options[1] = BIT_7; |
2663 | } else if (IS_QLA2200(ha)) { | |
2664 | nv->firmware_options[0] = BIT_2 | BIT_1; | |
2665 | nv->firmware_options[1] = BIT_7 | BIT_5; | |
2666 | nv->add_firmware_options[0] = BIT_5; | |
2667 | nv->add_firmware_options[1] = BIT_5 | BIT_4; | |
98aee70d | 2668 | nv->frame_payload_size = 1024; |
4e08df3f DM |
2669 | } else if (IS_QLA2100(ha)) { |
2670 | nv->firmware_options[0] = BIT_3 | BIT_1; | |
2671 | nv->firmware_options[1] = BIT_5; | |
98aee70d | 2672 | nv->frame_payload_size = 1024; |
4e08df3f DM |
2673 | } |
2674 | ||
2675 | nv->max_iocb_allocation = __constant_cpu_to_le16(256); | |
2676 | nv->execution_throttle = __constant_cpu_to_le16(16); | |
2677 | nv->retry_count = 8; | |
2678 | nv->retry_delay = 1; | |
2679 | ||
2680 | nv->port_name[0] = 33; | |
2681 | nv->port_name[3] = 224; | |
2682 | nv->port_name[4] = 139; | |
2683 | ||
e315cd28 | 2684 | qla2xxx_nvram_wwn_from_ofw(vha, nv); |
4e08df3f DM |
2685 | |
2686 | nv->login_timeout = 4; | |
2687 | ||
2688 | /* | |
2689 | * Set default host adapter parameters | |
2690 | */ | |
2691 | nv->host_p[1] = BIT_2; | |
2692 | nv->reset_delay = 5; | |
2693 | nv->port_down_retry_count = 8; | |
2694 | nv->max_luns_per_target = __constant_cpu_to_le16(8); | |
2695 | nv->link_down_timeout = 60; | |
2696 | ||
2697 | rval = 1; | |
1da177e4 LT |
2698 | } |
2699 | ||
2700 | #if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2) | |
2701 | /* | |
2702 | * The SN2 does not provide BIOS emulation which means you can't change | |
2703 | * potentially bogus BIOS settings. Force the use of default settings | |
2704 | * for link rate and frame size. Hope that the rest of the settings | |
2705 | * are valid. | |
2706 | */ | |
2707 | if (ia64_platform_is("sn2")) { | |
98aee70d | 2708 | nv->frame_payload_size = 2048; |
1da177e4 LT |
2709 | if (IS_QLA23XX(ha)) |
2710 | nv->special_options[1] = BIT_7; | |
2711 | } | |
2712 | #endif | |
2713 | ||
2714 | /* Reset Initialization control block */ | |
0107109e | 2715 | memset(icb, 0, ha->init_cb_size); |
1da177e4 LT |
2716 | |
2717 | /* | |
2718 | * Setup driver NVRAM options. | |
2719 | */ | |
2720 | nv->firmware_options[0] |= (BIT_6 | BIT_1); | |
2721 | nv->firmware_options[0] &= ~(BIT_5 | BIT_4); | |
2722 | nv->firmware_options[1] |= (BIT_5 | BIT_0); | |
2723 | nv->firmware_options[1] &= ~BIT_4; | |
2724 | ||
2725 | if (IS_QLA23XX(ha)) { | |
2726 | nv->firmware_options[0] |= BIT_2; | |
2727 | nv->firmware_options[0] &= ~BIT_3; | |
2d70c103 | 2728 | nv->special_options[0] &= ~BIT_6; |
0107109e | 2729 | nv->add_firmware_options[1] |= BIT_5 | BIT_4; |
1da177e4 LT |
2730 | |
2731 | if (IS_QLA2300(ha)) { | |
2732 | if (ha->fb_rev == FPM_2310) { | |
2733 | strcpy(ha->model_number, "QLA2310"); | |
2734 | } else { | |
2735 | strcpy(ha->model_number, "QLA2300"); | |
2736 | } | |
2737 | } else { | |
e315cd28 | 2738 | qla2x00_set_model_info(vha, nv->model_number, |
9bb9fcf2 | 2739 | sizeof(nv->model_number), "QLA23xx"); |
1da177e4 LT |
2740 | } |
2741 | } else if (IS_QLA2200(ha)) { | |
2742 | nv->firmware_options[0] |= BIT_2; | |
2743 | /* | |
2744 | * 'Point-to-point preferred, else loop' is not a safe | |
2745 | * connection mode setting. | |
2746 | */ | |
2747 | if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) == | |
2748 | (BIT_5 | BIT_4)) { | |
2749 | /* Force 'loop preferred, else point-to-point'. */ | |
2750 | nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4); | |
2751 | nv->add_firmware_options[0] |= BIT_5; | |
2752 | } | |
2753 | strcpy(ha->model_number, "QLA22xx"); | |
2754 | } else /*if (IS_QLA2100(ha))*/ { | |
2755 | strcpy(ha->model_number, "QLA2100"); | |
2756 | } | |
2757 | ||
2758 | /* | |
2759 | * Copy over NVRAM RISC parameter block to initialization control block. | |
2760 | */ | |
2761 | dptr1 = (uint8_t *)icb; | |
2762 | dptr2 = (uint8_t *)&nv->parameter_block_version; | |
2763 | cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version; | |
2764 | while (cnt--) | |
2765 | *dptr1++ = *dptr2++; | |
2766 | ||
2767 | /* Copy 2nd half. */ | |
2768 | dptr1 = (uint8_t *)icb->add_firmware_options; | |
2769 | cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options; | |
2770 | while (cnt--) | |
2771 | *dptr1++ = *dptr2++; | |
2772 | ||
5341e868 AV |
2773 | /* Use alternate WWN? */ |
2774 | if (nv->host_p[1] & BIT_7) { | |
2775 | memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE); | |
2776 | memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE); | |
2777 | } | |
2778 | ||
1da177e4 LT |
2779 | /* Prepare nodename */ |
2780 | if ((icb->firmware_options[1] & BIT_6) == 0) { | |
2781 | /* | |
2782 | * Firmware will apply the following mask if the nodename was | |
2783 | * not provided. | |
2784 | */ | |
2785 | memcpy(icb->node_name, icb->port_name, WWN_SIZE); | |
2786 | icb->node_name[0] &= 0xF0; | |
2787 | } | |
2788 | ||
2789 | /* | |
2790 | * Set host adapter parameters. | |
2791 | */ | |
3ce8866c SK |
2792 | |
2793 | /* | |
2794 | * BIT_7 in the host-parameters section allows for modification to | |
2795 | * internal driver logging. | |
2796 | */ | |
0181944f | 2797 | if (nv->host_p[0] & BIT_7) |
cfb0919c | 2798 | ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; |
1da177e4 LT |
2799 | ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0); |
2800 | /* Always load RISC code on non ISP2[12]00 chips. */ | |
2801 | if (!IS_QLA2100(ha) && !IS_QLA2200(ha)) | |
2802 | ha->flags.disable_risc_code_load = 0; | |
2803 | ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0); | |
2804 | ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0); | |
2805 | ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0); | |
06c22bd1 | 2806 | ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0; |
d4c760c2 | 2807 | ha->flags.disable_serdes = 0; |
1da177e4 LT |
2808 | |
2809 | ha->operating_mode = | |
2810 | (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4; | |
2811 | ||
2812 | memcpy(ha->fw_seriallink_options, nv->seriallink_options, | |
2813 | sizeof(ha->fw_seriallink_options)); | |
2814 | ||
2815 | /* save HBA serial number */ | |
2816 | ha->serial0 = icb->port_name[5]; | |
2817 | ha->serial1 = icb->port_name[6]; | |
2818 | ha->serial2 = icb->port_name[7]; | |
e315cd28 AC |
2819 | memcpy(vha->node_name, icb->node_name, WWN_SIZE); |
2820 | memcpy(vha->port_name, icb->port_name, WWN_SIZE); | |
1da177e4 LT |
2821 | |
2822 | icb->execution_throttle = __constant_cpu_to_le16(0xFFFF); | |
2823 | ||
2824 | ha->retry_count = nv->retry_count; | |
2825 | ||
2826 | /* Set minimum login_timeout to 4 seconds. */ | |
5b91490e | 2827 | if (nv->login_timeout != ql2xlogintimeout) |
1da177e4 LT |
2828 | nv->login_timeout = ql2xlogintimeout; |
2829 | if (nv->login_timeout < 4) | |
2830 | nv->login_timeout = 4; | |
2831 | ha->login_timeout = nv->login_timeout; | |
2832 | icb->login_timeout = nv->login_timeout; | |
2833 | ||
00a537b8 AV |
2834 | /* Set minimum RATOV to 100 tenths of a second. */ |
2835 | ha->r_a_tov = 100; | |
1da177e4 | 2836 | |
1da177e4 LT |
2837 | ha->loop_reset_delay = nv->reset_delay; |
2838 | ||
1da177e4 LT |
2839 | /* Link Down Timeout = 0: |
2840 | * | |
2841 | * When Port Down timer expires we will start returning | |
2842 | * I/O's to OS with "DID_NO_CONNECT". | |
2843 | * | |
2844 | * Link Down Timeout != 0: | |
2845 | * | |
2846 | * The driver waits for the link to come up after link down | |
2847 | * before returning I/Os to OS with "DID_NO_CONNECT". | |
fa2a1ce5 | 2848 | */ |
1da177e4 LT |
2849 | if (nv->link_down_timeout == 0) { |
2850 | ha->loop_down_abort_time = | |
354d6b21 | 2851 | (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT); |
1da177e4 LT |
2852 | } else { |
2853 | ha->link_down_timeout = nv->link_down_timeout; | |
2854 | ha->loop_down_abort_time = | |
2855 | (LOOP_DOWN_TIME - ha->link_down_timeout); | |
fa2a1ce5 | 2856 | } |
1da177e4 | 2857 | |
1da177e4 LT |
2858 | /* |
2859 | * Need enough time to try and get the port back. | |
2860 | */ | |
2861 | ha->port_down_retry_count = nv->port_down_retry_count; | |
2862 | if (qlport_down_retry) | |
2863 | ha->port_down_retry_count = qlport_down_retry; | |
2864 | /* Set login_retry_count */ | |
2865 | ha->login_retry_count = nv->retry_count; | |
2866 | if (ha->port_down_retry_count == nv->port_down_retry_count && | |
2867 | ha->port_down_retry_count > 3) | |
2868 | ha->login_retry_count = ha->port_down_retry_count; | |
2869 | else if (ha->port_down_retry_count > (int)ha->login_retry_count) | |
2870 | ha->login_retry_count = ha->port_down_retry_count; | |
2871 | if (ql2xloginretrycount) | |
2872 | ha->login_retry_count = ql2xloginretrycount; | |
2873 | ||
1da177e4 LT |
2874 | icb->lun_enables = __constant_cpu_to_le16(0); |
2875 | icb->command_resource_count = 0; | |
2876 | icb->immediate_notify_resource_count = 0; | |
2877 | icb->timeout = __constant_cpu_to_le16(0); | |
2878 | ||
2879 | if (IS_QLA2100(ha) || IS_QLA2200(ha)) { | |
2880 | /* Enable RIO */ | |
2881 | icb->firmware_options[0] &= ~BIT_3; | |
2882 | icb->add_firmware_options[0] &= | |
2883 | ~(BIT_3 | BIT_2 | BIT_1 | BIT_0); | |
2884 | icb->add_firmware_options[0] |= BIT_2; | |
2885 | icb->response_accumulation_timer = 3; | |
2886 | icb->interrupt_delay_timer = 5; | |
2887 | ||
e315cd28 | 2888 | vha->flags.process_response_queue = 1; |
1da177e4 | 2889 | } else { |
4fdfefe5 | 2890 | /* Enable ZIO. */ |
e315cd28 | 2891 | if (!vha->flags.init_done) { |
4fdfefe5 AV |
2892 | ha->zio_mode = icb->add_firmware_options[0] & |
2893 | (BIT_3 | BIT_2 | BIT_1 | BIT_0); | |
2894 | ha->zio_timer = icb->interrupt_delay_timer ? | |
2895 | icb->interrupt_delay_timer: 2; | |
2896 | } | |
1da177e4 LT |
2897 | icb->add_firmware_options[0] &= |
2898 | ~(BIT_3 | BIT_2 | BIT_1 | BIT_0); | |
e315cd28 | 2899 | vha->flags.process_response_queue = 0; |
4fdfefe5 | 2900 | if (ha->zio_mode != QLA_ZIO_DISABLED) { |
4a59f71d | 2901 | ha->zio_mode = QLA_ZIO_MODE_6; |
2902 | ||
7c3df132 | 2903 | ql_log(ql_log_info, vha, 0x0068, |
4fdfefe5 AV |
2904 | "ZIO mode %d enabled; timer delay (%d us).\n", |
2905 | ha->zio_mode, ha->zio_timer * 100); | |
1da177e4 | 2906 | |
4fdfefe5 AV |
2907 | icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode; |
2908 | icb->interrupt_delay_timer = (uint8_t)ha->zio_timer; | |
e315cd28 | 2909 | vha->flags.process_response_queue = 1; |
1da177e4 LT |
2910 | } |
2911 | } | |
2912 | ||
4e08df3f | 2913 | if (rval) { |
7c3df132 SK |
2914 | ql_log(ql_log_warn, vha, 0x0069, |
2915 | "NVRAM configuration failed.\n"); | |
4e08df3f DM |
2916 | } |
2917 | return (rval); | |
1da177e4 LT |
2918 | } |
2919 | ||
19a7b4ae JSEC |
2920 | static void |
2921 | qla2x00_rport_del(void *data) | |
2922 | { | |
2923 | fc_port_t *fcport = data; | |
d97994dc | 2924 | struct fc_rport *rport; |
2d70c103 | 2925 | scsi_qla_host_t *vha = fcport->vha; |
044d78e1 | 2926 | unsigned long flags; |
ba9f6f64 | 2927 | unsigned long vha_flags; |
d97994dc | 2928 | |
044d78e1 | 2929 | spin_lock_irqsave(fcport->vha->host->host_lock, flags); |
ac280b67 | 2930 | rport = fcport->drport ? fcport->drport: fcport->rport; |
d97994dc | 2931 | fcport->drport = NULL; |
044d78e1 | 2932 | spin_unlock_irqrestore(fcport->vha->host->host_lock, flags); |
2d70c103 | 2933 | if (rport) { |
d97994dc | 2934 | fc_remote_port_delete(rport); |
2d70c103 NB |
2935 | /* |
2936 | * Release the target mode FC NEXUS in qla_target.c code | |
2937 | * if target mod is enabled. | |
2938 | */ | |
ba9f6f64 | 2939 | spin_lock_irqsave(&vha->hw->hardware_lock, vha_flags); |
2d70c103 | 2940 | qlt_fc_port_deleted(vha, fcport); |
ba9f6f64 | 2941 | spin_unlock_irqrestore(&vha->hw->hardware_lock, vha_flags); |
2d70c103 | 2942 | } |
19a7b4ae JSEC |
2943 | } |
2944 | ||
1da177e4 LT |
2945 | /** |
2946 | * qla2x00_alloc_fcport() - Allocate a generic fcport. | |
2947 | * @ha: HA context | |
2948 | * @flags: allocation flags | |
2949 | * | |
2950 | * Returns a pointer to the allocated fcport, or NULL, if none available. | |
2951 | */ | |
9a069e19 | 2952 | fc_port_t * |
e315cd28 | 2953 | qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags) |
1da177e4 LT |
2954 | { |
2955 | fc_port_t *fcport; | |
2956 | ||
bbfbbbc1 MK |
2957 | fcport = kzalloc(sizeof(fc_port_t), flags); |
2958 | if (!fcport) | |
2959 | return NULL; | |
1da177e4 LT |
2960 | |
2961 | /* Setup fcport template structure. */ | |
e315cd28 | 2962 | fcport->vha = vha; |
1da177e4 LT |
2963 | fcport->port_type = FCT_UNKNOWN; |
2964 | fcport->loop_id = FC_NO_LOOP_ID; | |
ec426e10 | 2965 | qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED); |
ad3e0eda | 2966 | fcport->supported_classes = FC_COS_UNSPECIFIED; |
1da177e4 | 2967 | |
bbfbbbc1 | 2968 | return fcport; |
1da177e4 LT |
2969 | } |
2970 | ||
2971 | /* | |
2972 | * qla2x00_configure_loop | |
2973 | * Updates Fibre Channel Device Database with what is actually on loop. | |
2974 | * | |
2975 | * Input: | |
2976 | * ha = adapter block pointer. | |
2977 | * | |
2978 | * Returns: | |
2979 | * 0 = success. | |
2980 | * 1 = error. | |
2981 | * 2 = database was full and device was not configured. | |
2982 | */ | |
2983 | static int | |
e315cd28 | 2984 | qla2x00_configure_loop(scsi_qla_host_t *vha) |
1da177e4 LT |
2985 | { |
2986 | int rval; | |
2987 | unsigned long flags, save_flags; | |
e315cd28 | 2988 | struct qla_hw_data *ha = vha->hw; |
1da177e4 LT |
2989 | rval = QLA_SUCCESS; |
2990 | ||
2991 | /* Get Initiator ID */ | |
e315cd28 AC |
2992 | if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) { |
2993 | rval = qla2x00_configure_hba(vha); | |
1da177e4 | 2994 | if (rval != QLA_SUCCESS) { |
7c3df132 SK |
2995 | ql_dbg(ql_dbg_disc, vha, 0x2013, |
2996 | "Unable to configure HBA.\n"); | |
1da177e4 LT |
2997 | return (rval); |
2998 | } | |
2999 | } | |
3000 | ||
e315cd28 | 3001 | save_flags = flags = vha->dpc_flags; |
7c3df132 SK |
3002 | ql_dbg(ql_dbg_disc, vha, 0x2014, |
3003 | "Configure loop -- dpc flags = 0x%lx.\n", flags); | |
1da177e4 LT |
3004 | |
3005 | /* | |
3006 | * If we have both an RSCN and PORT UPDATE pending then handle them | |
3007 | * both at the same time. | |
3008 | */ | |
e315cd28 AC |
3009 | clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); |
3010 | clear_bit(RSCN_UPDATE, &vha->dpc_flags); | |
1da177e4 | 3011 | |
3064ff39 MH |
3012 | qla2x00_get_data_rate(vha); |
3013 | ||
1da177e4 LT |
3014 | /* Determine what we need to do */ |
3015 | if (ha->current_topology == ISP_CFG_FL && | |
3016 | (test_bit(LOCAL_LOOP_UPDATE, &flags))) { | |
3017 | ||
1da177e4 LT |
3018 | set_bit(RSCN_UPDATE, &flags); |
3019 | ||
3020 | } else if (ha->current_topology == ISP_CFG_F && | |
3021 | (test_bit(LOCAL_LOOP_UPDATE, &flags))) { | |
3022 | ||
1da177e4 LT |
3023 | set_bit(RSCN_UPDATE, &flags); |
3024 | clear_bit(LOCAL_LOOP_UPDATE, &flags); | |
21333b48 AV |
3025 | |
3026 | } else if (ha->current_topology == ISP_CFG_N) { | |
3027 | clear_bit(RSCN_UPDATE, &flags); | |
1da177e4 | 3028 | |
e315cd28 | 3029 | } else if (!vha->flags.online || |
1da177e4 LT |
3030 | (test_bit(ABORT_ISP_ACTIVE, &flags))) { |
3031 | ||
1da177e4 LT |
3032 | set_bit(RSCN_UPDATE, &flags); |
3033 | set_bit(LOCAL_LOOP_UPDATE, &flags); | |
3034 | } | |
3035 | ||
3036 | if (test_bit(LOCAL_LOOP_UPDATE, &flags)) { | |
7c3df132 SK |
3037 | if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { |
3038 | ql_dbg(ql_dbg_disc, vha, 0x2015, | |
3039 | "Loop resync needed, failing.\n"); | |
1da177e4 | 3040 | rval = QLA_FUNCTION_FAILED; |
642ef983 | 3041 | } else |
e315cd28 | 3042 | rval = qla2x00_configure_local_loop(vha); |
1da177e4 LT |
3043 | } |
3044 | ||
3045 | if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) { | |
7c3df132 SK |
3046 | if (LOOP_TRANSITION(vha)) { |
3047 | ql_dbg(ql_dbg_disc, vha, 0x201e, | |
3048 | "Needs RSCN update and loop transition.\n"); | |
1da177e4 | 3049 | rval = QLA_FUNCTION_FAILED; |
7c3df132 | 3050 | } |
e315cd28 AC |
3051 | else |
3052 | rval = qla2x00_configure_fabric(vha); | |
1da177e4 LT |
3053 | } |
3054 | ||
3055 | if (rval == QLA_SUCCESS) { | |
e315cd28 AC |
3056 | if (atomic_read(&vha->loop_down_timer) || |
3057 | test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { | |
1da177e4 LT |
3058 | rval = QLA_FUNCTION_FAILED; |
3059 | } else { | |
e315cd28 | 3060 | atomic_set(&vha->loop_state, LOOP_READY); |
7c3df132 SK |
3061 | ql_dbg(ql_dbg_disc, vha, 0x2069, |
3062 | "LOOP READY.\n"); | |
1da177e4 LT |
3063 | } |
3064 | } | |
3065 | ||
3066 | if (rval) { | |
7c3df132 SK |
3067 | ql_dbg(ql_dbg_disc, vha, 0x206a, |
3068 | "%s *** FAILED ***.\n", __func__); | |
1da177e4 | 3069 | } else { |
7c3df132 SK |
3070 | ql_dbg(ql_dbg_disc, vha, 0x206b, |
3071 | "%s: exiting normally.\n", __func__); | |
1da177e4 LT |
3072 | } |
3073 | ||
cc3ef7bc | 3074 | /* Restore state if a resync event occurred during processing */ |
e315cd28 | 3075 | if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { |
1da177e4 | 3076 | if (test_bit(LOCAL_LOOP_UPDATE, &save_flags)) |
e315cd28 | 3077 | set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); |
f4658b6c | 3078 | if (test_bit(RSCN_UPDATE, &save_flags)) { |
e315cd28 | 3079 | set_bit(RSCN_UPDATE, &vha->dpc_flags); |
f4658b6c | 3080 | } |
1da177e4 LT |
3081 | } |
3082 | ||
3083 | return (rval); | |
3084 | } | |
3085 | ||
3086 | ||
3087 | ||
3088 | /* | |
3089 | * qla2x00_configure_local_loop | |
3090 | * Updates Fibre Channel Device Database with local loop devices. | |
3091 | * | |
3092 | * Input: | |
3093 | * ha = adapter block pointer. | |
3094 | * | |
3095 | * Returns: | |
3096 | * 0 = success. | |
3097 | */ | |
3098 | static int | |
e315cd28 | 3099 | qla2x00_configure_local_loop(scsi_qla_host_t *vha) |
1da177e4 LT |
3100 | { |
3101 | int rval, rval2; | |
3102 | int found_devs; | |
3103 | int found; | |
3104 | fc_port_t *fcport, *new_fcport; | |
3105 | ||
3106 | uint16_t index; | |
3107 | uint16_t entries; | |
3108 | char *id_iter; | |
3109 | uint16_t loop_id; | |
3110 | uint8_t domain, area, al_pa; | |
e315cd28 | 3111 | struct qla_hw_data *ha = vha->hw; |
1da177e4 LT |
3112 | |
3113 | found_devs = 0; | |
3114 | new_fcport = NULL; | |
642ef983 | 3115 | entries = MAX_FIBRE_DEVICES_LOOP; |
1da177e4 | 3116 | |
1da177e4 | 3117 | /* Get list of logged in devices. */ |
642ef983 | 3118 | memset(ha->gid_list, 0, qla2x00_gid_list_size(ha)); |
e315cd28 | 3119 | rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma, |
1da177e4 LT |
3120 | &entries); |
3121 | if (rval != QLA_SUCCESS) | |
3122 | goto cleanup_allocation; | |
3123 | ||
7c3df132 SK |
3124 | ql_dbg(ql_dbg_disc, vha, 0x2017, |
3125 | "Entries in ID list (%d).\n", entries); | |
3126 | ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075, | |
3127 | (uint8_t *)ha->gid_list, | |
3128 | entries * sizeof(struct gid_list_info)); | |
1da177e4 LT |
3129 | |
3130 | /* Allocate temporary fcport for any new fcports discovered. */ | |
e315cd28 | 3131 | new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); |
1da177e4 | 3132 | if (new_fcport == NULL) { |
7c3df132 SK |
3133 | ql_log(ql_log_warn, vha, 0x2018, |
3134 | "Memory allocation failed for fcport.\n"); | |
1da177e4 LT |
3135 | rval = QLA_MEMORY_ALLOC_FAILED; |
3136 | goto cleanup_allocation; | |
3137 | } | |
3138 | new_fcport->flags &= ~FCF_FABRIC_DEVICE; | |
3139 | ||
3140 | /* | |
3141 | * Mark local devices that were present with FCF_DEVICE_LOST for now. | |
3142 | */ | |
e315cd28 | 3143 | list_for_each_entry(fcport, &vha->vp_fcports, list) { |
1da177e4 LT |
3144 | if (atomic_read(&fcport->state) == FCS_ONLINE && |
3145 | fcport->port_type != FCT_BROADCAST && | |
3146 | (fcport->flags & FCF_FABRIC_DEVICE) == 0) { | |
3147 | ||
7c3df132 SK |
3148 | ql_dbg(ql_dbg_disc, vha, 0x2019, |
3149 | "Marking port lost loop_id=0x%04x.\n", | |
3150 | fcport->loop_id); | |
1da177e4 | 3151 | |
ec426e10 | 3152 | qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); |
1da177e4 LT |
3153 | } |
3154 | } | |
3155 | ||
3156 | /* Add devices to port list. */ | |
3157 | id_iter = (char *)ha->gid_list; | |
3158 | for (index = 0; index < entries; index++) { | |
3159 | domain = ((struct gid_list_info *)id_iter)->domain; | |
3160 | area = ((struct gid_list_info *)id_iter)->area; | |
3161 | al_pa = ((struct gid_list_info *)id_iter)->al_pa; | |
abbd8870 | 3162 | if (IS_QLA2100(ha) || IS_QLA2200(ha)) |
1da177e4 LT |
3163 | loop_id = (uint16_t) |
3164 | ((struct gid_list_info *)id_iter)->loop_id_2100; | |
abbd8870 | 3165 | else |
1da177e4 LT |
3166 | loop_id = le16_to_cpu( |
3167 | ((struct gid_list_info *)id_iter)->loop_id); | |
abbd8870 | 3168 | id_iter += ha->gid_list_info_size; |
1da177e4 LT |
3169 | |
3170 | /* Bypass reserved domain fields. */ | |
3171 | if ((domain & 0xf0) == 0xf0) | |
3172 | continue; | |
3173 | ||
3174 | /* Bypass if not same domain and area of adapter. */ | |
f7d289f6 | 3175 | if (area && domain && |
e315cd28 | 3176 | (area != vha->d_id.b.area || domain != vha->d_id.b.domain)) |
1da177e4 LT |
3177 | continue; |
3178 | ||
3179 | /* Bypass invalid local loop ID. */ | |
3180 | if (loop_id > LAST_LOCAL_LOOP_ID) | |
3181 | continue; | |
3182 | ||
370d550e AE |
3183 | memset(new_fcport, 0, sizeof(fc_port_t)); |
3184 | ||
1da177e4 LT |
3185 | /* Fill in member data. */ |
3186 | new_fcport->d_id.b.domain = domain; | |
3187 | new_fcport->d_id.b.area = area; | |
3188 | new_fcport->d_id.b.al_pa = al_pa; | |
3189 | new_fcport->loop_id = loop_id; | |
e315cd28 | 3190 | rval2 = qla2x00_get_port_database(vha, new_fcport, 0); |
1da177e4 | 3191 | if (rval2 != QLA_SUCCESS) { |
7c3df132 SK |
3192 | ql_dbg(ql_dbg_disc, vha, 0x201a, |
3193 | "Failed to retrieve fcport information " | |
3194 | "-- get_port_database=%x, loop_id=0x%04x.\n", | |
3195 | rval2, new_fcport->loop_id); | |
3196 | ql_dbg(ql_dbg_disc, vha, 0x201b, | |
3197 | "Scheduling resync.\n"); | |
e315cd28 | 3198 | set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); |
1da177e4 LT |
3199 | continue; |
3200 | } | |
3201 | ||
3202 | /* Check for matching device in port list. */ | |
3203 | found = 0; | |
3204 | fcport = NULL; | |
e315cd28 | 3205 | list_for_each_entry(fcport, &vha->vp_fcports, list) { |
1da177e4 LT |
3206 | if (memcmp(new_fcport->port_name, fcport->port_name, |
3207 | WWN_SIZE)) | |
3208 | continue; | |
3209 | ||
ddb9b126 | 3210 | fcport->flags &= ~FCF_FABRIC_DEVICE; |
1da177e4 LT |
3211 | fcport->loop_id = new_fcport->loop_id; |
3212 | fcport->port_type = new_fcport->port_type; | |
3213 | fcport->d_id.b24 = new_fcport->d_id.b24; | |
3214 | memcpy(fcport->node_name, new_fcport->node_name, | |
3215 | WWN_SIZE); | |
3216 | ||
3217 | found++; | |
3218 | break; | |
3219 | } | |
3220 | ||
3221 | if (!found) { | |
3222 | /* New device, add to fcports list. */ | |
e315cd28 | 3223 | list_add_tail(&new_fcport->list, &vha->vp_fcports); |
1da177e4 LT |
3224 | |
3225 | /* Allocate a new replacement fcport. */ | |
3226 | fcport = new_fcport; | |
e315cd28 | 3227 | new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); |
1da177e4 | 3228 | if (new_fcport == NULL) { |
7c3df132 SK |
3229 | ql_log(ql_log_warn, vha, 0x201c, |
3230 | "Failed to allocate memory for fcport.\n"); | |
1da177e4 LT |
3231 | rval = QLA_MEMORY_ALLOC_FAILED; |
3232 | goto cleanup_allocation; | |
3233 | } | |
3234 | new_fcport->flags &= ~FCF_FABRIC_DEVICE; | |
3235 | } | |
3236 | ||
d8b45213 | 3237 | /* Base iIDMA settings on HBA port speed. */ |
a3cbdfad | 3238 | fcport->fp_speed = ha->link_data_rate; |
d8b45213 | 3239 | |
e315cd28 | 3240 | qla2x00_update_fcport(vha, fcport); |
1da177e4 LT |
3241 | |
3242 | found_devs++; | |
3243 | } | |
3244 | ||
3245 | cleanup_allocation: | |
c9475cb0 | 3246 | kfree(new_fcport); |
1da177e4 LT |
3247 | |
3248 | if (rval != QLA_SUCCESS) { | |
7c3df132 SK |
3249 | ql_dbg(ql_dbg_disc, vha, 0x201d, |
3250 | "Configure local loop error exit: rval=%x.\n", rval); | |
1da177e4 LT |
3251 | } |
3252 | ||
1da177e4 LT |
3253 | return (rval); |
3254 | } | |
3255 | ||
d8b45213 | 3256 | static void |
e315cd28 | 3257 | qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport) |
d8b45213 | 3258 | { |
d8b45213 | 3259 | int rval; |
93f2bd67 | 3260 | uint16_t mb[MAILBOX_REGISTER_COUNT]; |
e315cd28 | 3261 | struct qla_hw_data *ha = vha->hw; |
d8b45213 | 3262 | |
c76f2c01 | 3263 | if (!IS_IIDMA_CAPABLE(ha)) |
d8b45213 AV |
3264 | return; |
3265 | ||
c9afb9a2 GM |
3266 | if (atomic_read(&fcport->state) != FCS_ONLINE) |
3267 | return; | |
3268 | ||
39bd9622 AV |
3269 | if (fcport->fp_speed == PORT_SPEED_UNKNOWN || |
3270 | fcport->fp_speed > ha->link_data_rate) | |
d8b45213 AV |
3271 | return; |
3272 | ||
e315cd28 | 3273 | rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed, |
a3cbdfad | 3274 | mb); |
d8b45213 | 3275 | if (rval != QLA_SUCCESS) { |
7c3df132 | 3276 | ql_dbg(ql_dbg_disc, vha, 0x2004, |
7b833558 OK |
3277 | "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n", |
3278 | fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]); | |
d8b45213 | 3279 | } else { |
7c3df132 | 3280 | ql_dbg(ql_dbg_disc, vha, 0x2005, |
7b833558 | 3281 | "iIDMA adjusted to %s GB/s on %8phN.\n", |
d0297c9a | 3282 | qla2x00_get_link_speed_str(ha, fcport->fp_speed), |
7b833558 | 3283 | fcport->port_name); |
d8b45213 AV |
3284 | } |
3285 | } | |
3286 | ||
23be331d | 3287 | static void |
e315cd28 | 3288 | qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport) |
8482e118 | 3289 | { |
3290 | struct fc_rport_identifiers rport_ids; | |
bdf79621 | 3291 | struct fc_rport *rport; |
044d78e1 | 3292 | unsigned long flags; |
8482e118 | 3293 | |
f8b02a85 AV |
3294 | rport_ids.node_name = wwn_to_u64(fcport->node_name); |
3295 | rport_ids.port_name = wwn_to_u64(fcport->port_name); | |
8482e118 | 3296 | rport_ids.port_id = fcport->d_id.b.domain << 16 | |
3297 | fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa; | |
77d74143 | 3298 | rport_ids.roles = FC_RPORT_ROLE_UNKNOWN; |
e315cd28 | 3299 | fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids); |
77d74143 | 3300 | if (!rport) { |
7c3df132 SK |
3301 | ql_log(ql_log_warn, vha, 0x2006, |
3302 | "Unable to allocate fc remote port.\n"); | |
77d74143 AV |
3303 | return; |
3304 | } | |
2d70c103 NB |
3305 | /* |
3306 | * Create target mode FC NEXUS in qla_target.c if target mode is | |
3307 | * enabled.. | |
3308 | */ | |
ba9f6f64 | 3309 | |
2d70c103 NB |
3310 | qlt_fc_port_added(vha, fcport); |
3311 | ||
044d78e1 | 3312 | spin_lock_irqsave(fcport->vha->host->host_lock, flags); |
19a7b4ae | 3313 | *((fc_port_t **)rport->dd_data) = fcport; |
044d78e1 | 3314 | spin_unlock_irqrestore(fcport->vha->host->host_lock, flags); |
d97994dc | 3315 | |
ad3e0eda | 3316 | rport->supported_classes = fcport->supported_classes; |
77d74143 | 3317 | |
8482e118 | 3318 | rport_ids.roles = FC_RPORT_ROLE_UNKNOWN; |
3319 | if (fcport->port_type == FCT_INITIATOR) | |
3320 | rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR; | |
3321 | if (fcport->port_type == FCT_TARGET) | |
3322 | rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET; | |
77d74143 | 3323 | fc_remote_port_rolechg(rport, rport_ids.roles); |
1da177e4 LT |
3324 | } |
3325 | ||
23be331d AB |
3326 | /* |
3327 | * qla2x00_update_fcport | |
3328 | * Updates device on list. | |
3329 | * | |
3330 | * Input: | |
3331 | * ha = adapter block pointer. | |
3332 | * fcport = port structure pointer. | |
3333 | * | |
3334 | * Return: | |
3335 | * 0 - Success | |
3336 | * BIT_0 - error | |
3337 | * | |
3338 | * Context: | |
3339 | * Kernel context. | |
3340 | */ | |
3341 | void | |
e315cd28 | 3342 | qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport) |
23be331d | 3343 | { |
e315cd28 | 3344 | fcport->vha = vha; |
8ae6d9c7 GM |
3345 | |
3346 | if (IS_QLAFX00(vha->hw)) { | |
3347 | qla2x00_set_fcport_state(fcport, FCS_ONLINE); | |
3348 | qla2x00_reg_remote_port(vha, fcport); | |
3349 | return; | |
3350 | } | |
23be331d | 3351 | fcport->login_retry = 0; |
5ff1d584 | 3352 | fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); |
23be331d | 3353 | |
1f93da52 | 3354 | qla2x00_set_fcport_state(fcport, FCS_ONLINE); |
e315cd28 | 3355 | qla2x00_iidma_fcport(vha, fcport); |
21090cbe | 3356 | qla24xx_update_fcport_fcp_prio(vha, fcport); |
e315cd28 | 3357 | qla2x00_reg_remote_port(vha, fcport); |
23be331d AB |
3358 | } |
3359 | ||
1da177e4 LT |
3360 | /* |
3361 | * qla2x00_configure_fabric | |
3362 | * Setup SNS devices with loop ID's. | |
3363 | * | |
3364 | * Input: | |
3365 | * ha = adapter block pointer. | |
3366 | * | |
3367 | * Returns: | |
3368 | * 0 = success. | |
3369 | * BIT_0 = error | |
3370 | */ | |
3371 | static int | |
e315cd28 | 3372 | qla2x00_configure_fabric(scsi_qla_host_t *vha) |
1da177e4 | 3373 | { |
b3b02e6e | 3374 | int rval; |
e452ceb6 | 3375 | fc_port_t *fcport, *fcptemp; |
1da177e4 LT |
3376 | uint16_t next_loopid; |
3377 | uint16_t mb[MAILBOX_REGISTER_COUNT]; | |
0107109e | 3378 | uint16_t loop_id; |
1da177e4 | 3379 | LIST_HEAD(new_fcports); |
e315cd28 AC |
3380 | struct qla_hw_data *ha = vha->hw; |
3381 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); | |
1da177e4 LT |
3382 | |
3383 | /* If FL port exists, then SNS is present */ | |
e428924c | 3384 | if (IS_FWI2_CAPABLE(ha)) |
0107109e AV |
3385 | loop_id = NPH_F_PORT; |
3386 | else | |
3387 | loop_id = SNS_FL_PORT; | |
e315cd28 | 3388 | rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1); |
1da177e4 | 3389 | if (rval != QLA_SUCCESS) { |
7c3df132 SK |
3390 | ql_dbg(ql_dbg_disc, vha, 0x201f, |
3391 | "MBX_GET_PORT_NAME failed, No FL Port.\n"); | |
1da177e4 | 3392 | |
e315cd28 | 3393 | vha->device_flags &= ~SWITCH_FOUND; |
1da177e4 LT |
3394 | return (QLA_SUCCESS); |
3395 | } | |
e315cd28 | 3396 | vha->device_flags |= SWITCH_FOUND; |
1da177e4 | 3397 | |
1da177e4 | 3398 | do { |
cca5335c AV |
3399 | /* FDMI support. */ |
3400 | if (ql2xfdmienable && | |
e315cd28 AC |
3401 | test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags)) |
3402 | qla2x00_fdmi_register(vha); | |
cca5335c | 3403 | |
1da177e4 | 3404 | /* Ensure we are logged into the SNS. */ |
e428924c | 3405 | if (IS_FWI2_CAPABLE(ha)) |
0107109e AV |
3406 | loop_id = NPH_SNS; |
3407 | else | |
3408 | loop_id = SIMPLE_NAME_SERVER; | |
0b91d116 CD |
3409 | rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff, |
3410 | 0xfc, mb, BIT_1|BIT_0); | |
3411 | if (rval != QLA_SUCCESS) { | |
3412 | set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); | |
e452ceb6 | 3413 | return rval; |
0b91d116 | 3414 | } |
1da177e4 | 3415 | if (mb[0] != MBS_COMMAND_COMPLETE) { |
7c3df132 SK |
3416 | ql_dbg(ql_dbg_disc, vha, 0x2042, |
3417 | "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x " | |
3418 | "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1], | |
3419 | mb[2], mb[6], mb[7]); | |
1da177e4 LT |
3420 | return (QLA_SUCCESS); |
3421 | } | |
3422 | ||
e315cd28 AC |
3423 | if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) { |
3424 | if (qla2x00_rft_id(vha)) { | |
1da177e4 | 3425 | /* EMPTY */ |
7c3df132 SK |
3426 | ql_dbg(ql_dbg_disc, vha, 0x2045, |
3427 | "Register FC-4 TYPE failed.\n"); | |
1da177e4 | 3428 | } |
e315cd28 | 3429 | if (qla2x00_rff_id(vha)) { |
1da177e4 | 3430 | /* EMPTY */ |
7c3df132 SK |
3431 | ql_dbg(ql_dbg_disc, vha, 0x2049, |
3432 | "Register FC-4 Features failed.\n"); | |
1da177e4 | 3433 | } |
e315cd28 | 3434 | if (qla2x00_rnn_id(vha)) { |
1da177e4 | 3435 | /* EMPTY */ |
7c3df132 SK |
3436 | ql_dbg(ql_dbg_disc, vha, 0x204f, |
3437 | "Register Node Name failed.\n"); | |
e315cd28 | 3438 | } else if (qla2x00_rsnn_nn(vha)) { |
1da177e4 | 3439 | /* EMPTY */ |
7c3df132 SK |
3440 | ql_dbg(ql_dbg_disc, vha, 0x2053, |
3441 | "Register Symobilic Node Name failed.\n"); | |
1da177e4 LT |
3442 | } |
3443 | } | |
3444 | ||
827210ba JC |
3445 | #define QLA_FCPORT_SCAN 1 |
3446 | #define QLA_FCPORT_FOUND 2 | |
3447 | ||
3448 | list_for_each_entry(fcport, &vha->vp_fcports, list) { | |
3449 | fcport->scan_state = QLA_FCPORT_SCAN; | |
3450 | } | |
3451 | ||
e315cd28 | 3452 | rval = qla2x00_find_all_fabric_devs(vha, &new_fcports); |
1da177e4 LT |
3453 | if (rval != QLA_SUCCESS) |
3454 | break; | |
3455 | ||
e452ceb6 JC |
3456 | /* |
3457 | * Logout all previous fabric devices marked lost, except | |
3458 | * FCP2 devices. | |
3459 | */ | |
e315cd28 AC |
3460 | list_for_each_entry(fcport, &vha->vp_fcports, list) { |
3461 | if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) | |
1da177e4 LT |
3462 | break; |
3463 | ||
3464 | if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) | |
3465 | continue; | |
3466 | ||
827210ba | 3467 | if (fcport->scan_state == QLA_FCPORT_SCAN && |
b3b02e6e | 3468 | atomic_read(&fcport->state) == FCS_ONLINE) { |
e315cd28 | 3469 | qla2x00_mark_device_lost(vha, fcport, |
d97994dc | 3470 | ql2xplogiabsentdevice, 0); |
1da177e4 | 3471 | if (fcport->loop_id != FC_NO_LOOP_ID && |
f08b7251 | 3472 | (fcport->flags & FCF_FCP2_DEVICE) == 0 && |
1da177e4 LT |
3473 | fcport->port_type != FCT_INITIATOR && |
3474 | fcport->port_type != FCT_BROADCAST) { | |
e315cd28 | 3475 | ha->isp_ops->fabric_logout(vha, |
1c7c6357 AV |
3476 | fcport->loop_id, |
3477 | fcport->d_id.b.domain, | |
3478 | fcport->d_id.b.area, | |
3479 | fcport->d_id.b.al_pa); | |
1a5c69bf | 3480 | qla2x00_clear_loop_id(fcport); |
1da177e4 LT |
3481 | } |
3482 | } | |
e452ceb6 | 3483 | } |
1da177e4 | 3484 | |
e452ceb6 JC |
3485 | /* Starting free loop ID. */ |
3486 | next_loopid = ha->min_external_loopid; | |
3487 | ||
3488 | /* | |
3489 | * Scan through our port list and login entries that need to be | |
3490 | * logged in. | |
3491 | */ | |
3492 | list_for_each_entry(fcport, &vha->vp_fcports, list) { | |
3493 | if (atomic_read(&vha->loop_down_timer) || | |
3494 | test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) | |
3495 | break; | |
3496 | ||
3497 | if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 || | |
3498 | (fcport->flags & FCF_LOGIN_NEEDED) == 0) | |
3499 | continue; | |
3500 | ||
3501 | if (fcport->loop_id == FC_NO_LOOP_ID) { | |
3502 | fcport->loop_id = next_loopid; | |
3503 | rval = qla2x00_find_new_loop_id( | |
3504 | base_vha, fcport); | |
3505 | if (rval != QLA_SUCCESS) { | |
3506 | /* Ran out of IDs to use */ | |
3507 | break; | |
1da177e4 LT |
3508 | } |
3509 | } | |
e452ceb6 JC |
3510 | /* Login and update database */ |
3511 | qla2x00_fabric_dev_login(vha, fcport, &next_loopid); | |
3512 | } | |
3513 | ||
3514 | /* Exit if out of loop IDs. */ | |
3515 | if (rval != QLA_SUCCESS) { | |
3516 | break; | |
3517 | } | |
3518 | ||
3519 | /* | |
3520 | * Login and add the new devices to our port list. | |
3521 | */ | |
3522 | list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) { | |
3523 | if (atomic_read(&vha->loop_down_timer) || | |
3524 | test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) | |
3525 | break; | |
3526 | ||
3527 | /* Find a new loop ID to use. */ | |
3528 | fcport->loop_id = next_loopid; | |
3529 | rval = qla2x00_find_new_loop_id(base_vha, fcport); | |
3530 | if (rval != QLA_SUCCESS) { | |
3531 | /* Ran out of IDs to use */ | |
3532 | break; | |
3533 | } | |
1da177e4 | 3534 | |
bdf79621 | 3535 | /* Login and update database */ |
e315cd28 | 3536 | qla2x00_fabric_dev_login(vha, fcport, &next_loopid); |
e452ceb6 JC |
3537 | |
3538 | list_move_tail(&fcport->list, &vha->vp_fcports); | |
1da177e4 LT |
3539 | } |
3540 | } while (0); | |
3541 | ||
e452ceb6 JC |
3542 | /* Free all new device structures not processed. */ |
3543 | list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) { | |
3544 | list_del(&fcport->list); | |
3545 | kfree(fcport); | |
3546 | } | |
3547 | ||
1da177e4 | 3548 | if (rval) { |
7c3df132 SK |
3549 | ql_dbg(ql_dbg_disc, vha, 0x2068, |
3550 | "Configure fabric error exit rval=%d.\n", rval); | |
1da177e4 LT |
3551 | } |
3552 | ||
3553 | return (rval); | |
3554 | } | |
3555 | ||
1da177e4 LT |
3556 | /* |
3557 | * qla2x00_find_all_fabric_devs | |
3558 | * | |
3559 | * Input: | |
3560 | * ha = adapter block pointer. | |
3561 | * dev = database device entry pointer. | |
3562 | * | |
3563 | * Returns: | |
3564 | * 0 = success. | |
3565 | * | |
3566 | * Context: | |
3567 | * Kernel context. | |
3568 | */ | |
3569 | static int | |
e315cd28 AC |
3570 | qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha, |
3571 | struct list_head *new_fcports) | |
1da177e4 LT |
3572 | { |
3573 | int rval; | |
3574 | uint16_t loop_id; | |
3575 | fc_port_t *fcport, *new_fcport, *fcptemp; | |
3576 | int found; | |
3577 | ||
3578 | sw_info_t *swl; | |
3579 | int swl_idx; | |
3580 | int first_dev, last_dev; | |
1516ef44 | 3581 | port_id_t wrap = {}, nxt_d_id; |
e315cd28 | 3582 | struct qla_hw_data *ha = vha->hw; |
bb4cf5b7 | 3583 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
1da177e4 LT |
3584 | |
3585 | rval = QLA_SUCCESS; | |
3586 | ||
3587 | /* Try GID_PT to get device list, else GAN. */ | |
7a67735b | 3588 | if (!ha->swl) |
642ef983 | 3589 | ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t), |
7a67735b AV |
3590 | GFP_KERNEL); |
3591 | swl = ha->swl; | |
bbfbbbc1 | 3592 | if (!swl) { |
1da177e4 | 3593 | /*EMPTY*/ |
7c3df132 SK |
3594 | ql_dbg(ql_dbg_disc, vha, 0x2054, |
3595 | "GID_PT allocations failed, fallback on GA_NXT.\n"); | |
1da177e4 | 3596 | } else { |
642ef983 | 3597 | memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t)); |
e315cd28 | 3598 | if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) { |
1da177e4 | 3599 | swl = NULL; |
e315cd28 | 3600 | } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) { |
1da177e4 | 3601 | swl = NULL; |
e315cd28 | 3602 | } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) { |
1da177e4 | 3603 | swl = NULL; |
e5896bd5 | 3604 | } else if (ql2xiidmaenable && |
e315cd28 AC |
3605 | qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) { |
3606 | qla2x00_gpsc(vha, swl); | |
1da177e4 | 3607 | } |
e8c72ba5 CD |
3608 | |
3609 | /* If other queries succeeded probe for FC-4 type */ | |
3610 | if (swl) | |
3611 | qla2x00_gff_id(vha, swl); | |
1da177e4 LT |
3612 | } |
3613 | swl_idx = 0; | |
3614 | ||
3615 | /* Allocate temporary fcport for any new fcports discovered. */ | |
e315cd28 | 3616 | new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); |
1da177e4 | 3617 | if (new_fcport == NULL) { |
7c3df132 SK |
3618 | ql_log(ql_log_warn, vha, 0x205e, |
3619 | "Failed to allocate memory for fcport.\n"); | |
1da177e4 LT |
3620 | return (QLA_MEMORY_ALLOC_FAILED); |
3621 | } | |
3622 | new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED); | |
1da177e4 LT |
3623 | /* Set start port ID scan at adapter ID. */ |
3624 | first_dev = 1; | |
3625 | last_dev = 0; | |
3626 | ||
3627 | /* Starting free loop ID. */ | |
e315cd28 AC |
3628 | loop_id = ha->min_external_loopid; |
3629 | for (; loop_id <= ha->max_loop_id; loop_id++) { | |
3630 | if (qla2x00_is_reserved_id(vha, loop_id)) | |
1da177e4 LT |
3631 | continue; |
3632 | ||
3a6478df GM |
3633 | if (ha->current_topology == ISP_CFG_FL && |
3634 | (atomic_read(&vha->loop_down_timer) || | |
3635 | LOOP_TRANSITION(vha))) { | |
bb2d52b2 AV |
3636 | atomic_set(&vha->loop_down_timer, 0); |
3637 | set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); | |
3638 | set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); | |
1da177e4 | 3639 | break; |
bb2d52b2 | 3640 | } |
1da177e4 LT |
3641 | |
3642 | if (swl != NULL) { | |
3643 | if (last_dev) { | |
3644 | wrap.b24 = new_fcport->d_id.b24; | |
3645 | } else { | |
3646 | new_fcport->d_id.b24 = swl[swl_idx].d_id.b24; | |
3647 | memcpy(new_fcport->node_name, | |
3648 | swl[swl_idx].node_name, WWN_SIZE); | |
3649 | memcpy(new_fcport->port_name, | |
3650 | swl[swl_idx].port_name, WWN_SIZE); | |
d8b45213 AV |
3651 | memcpy(new_fcport->fabric_port_name, |
3652 | swl[swl_idx].fabric_port_name, WWN_SIZE); | |
3653 | new_fcport->fp_speed = swl[swl_idx].fp_speed; | |
e8c72ba5 | 3654 | new_fcport->fc4_type = swl[swl_idx].fc4_type; |
1da177e4 LT |
3655 | |
3656 | if (swl[swl_idx].d_id.b.rsvd_1 != 0) { | |
3657 | last_dev = 1; | |
3658 | } | |
3659 | swl_idx++; | |
3660 | } | |
3661 | } else { | |
3662 | /* Send GA_NXT to the switch */ | |
e315cd28 | 3663 | rval = qla2x00_ga_nxt(vha, new_fcport); |
1da177e4 | 3664 | if (rval != QLA_SUCCESS) { |
7c3df132 SK |
3665 | ql_log(ql_log_warn, vha, 0x2064, |
3666 | "SNS scan failed -- assuming " | |
3667 | "zero-entry result.\n"); | |
1da177e4 LT |
3668 | list_for_each_entry_safe(fcport, fcptemp, |
3669 | new_fcports, list) { | |
3670 | list_del(&fcport->list); | |
3671 | kfree(fcport); | |
3672 | } | |
3673 | rval = QLA_SUCCESS; | |
3674 | break; | |
3675 | } | |
3676 | } | |
3677 | ||
3678 | /* If wrap on switch device list, exit. */ | |
3679 | if (first_dev) { | |
3680 | wrap.b24 = new_fcport->d_id.b24; | |
3681 | first_dev = 0; | |
3682 | } else if (new_fcport->d_id.b24 == wrap.b24) { | |
7c3df132 SK |
3683 | ql_dbg(ql_dbg_disc, vha, 0x2065, |
3684 | "Device wrap (%02x%02x%02x).\n", | |
3685 | new_fcport->d_id.b.domain, | |
3686 | new_fcport->d_id.b.area, | |
3687 | new_fcport->d_id.b.al_pa); | |
1da177e4 LT |
3688 | break; |
3689 | } | |
3690 | ||
2c3dfe3f | 3691 | /* Bypass if same physical adapter. */ |
e315cd28 | 3692 | if (new_fcport->d_id.b24 == base_vha->d_id.b24) |
1da177e4 LT |
3693 | continue; |
3694 | ||
2c3dfe3f | 3695 | /* Bypass virtual ports of the same host. */ |
bb4cf5b7 CD |
3696 | if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24)) |
3697 | continue; | |
2c3dfe3f | 3698 | |
f7d289f6 AV |
3699 | /* Bypass if same domain and area of adapter. */ |
3700 | if (((new_fcport->d_id.b24 & 0xffff00) == | |
e315cd28 | 3701 | (vha->d_id.b24 & 0xffff00)) && ha->current_topology == |
f7d289f6 AV |
3702 | ISP_CFG_FL) |
3703 | continue; | |
3704 | ||
1da177e4 LT |
3705 | /* Bypass reserved domain fields. */ |
3706 | if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0) | |
3707 | continue; | |
3708 | ||
e8c72ba5 | 3709 | /* Bypass ports whose FCP-4 type is not FCP_SCSI */ |
4da26e16 CD |
3710 | if (ql2xgffidenable && |
3711 | (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI && | |
3712 | new_fcport->fc4_type != FC4_TYPE_UNKNOWN)) | |
e8c72ba5 CD |
3713 | continue; |
3714 | ||
1da177e4 LT |
3715 | /* Locate matching device in database. */ |
3716 | found = 0; | |
e315cd28 | 3717 | list_for_each_entry(fcport, &vha->vp_fcports, list) { |
1da177e4 LT |
3718 | if (memcmp(new_fcport->port_name, fcport->port_name, |
3719 | WWN_SIZE)) | |
3720 | continue; | |
3721 | ||
827210ba | 3722 | fcport->scan_state = QLA_FCPORT_FOUND; |
b3b02e6e | 3723 | |
1da177e4 LT |
3724 | found++; |
3725 | ||
d8b45213 AV |
3726 | /* Update port state. */ |
3727 | memcpy(fcport->fabric_port_name, | |
3728 | new_fcport->fabric_port_name, WWN_SIZE); | |
3729 | fcport->fp_speed = new_fcport->fp_speed; | |
3730 | ||
1da177e4 LT |
3731 | /* |
3732 | * If address the same and state FCS_ONLINE, nothing | |
3733 | * changed. | |
3734 | */ | |
3735 | if (fcport->d_id.b24 == new_fcport->d_id.b24 && | |
3736 | atomic_read(&fcport->state) == FCS_ONLINE) { | |
3737 | break; | |
3738 | } | |
3739 | ||
3740 | /* | |
3741 | * If device was not a fabric device before. | |
3742 | */ | |
3743 | if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) { | |
3744 | fcport->d_id.b24 = new_fcport->d_id.b24; | |
5f16b331 | 3745 | qla2x00_clear_loop_id(fcport); |
1da177e4 LT |
3746 | fcport->flags |= (FCF_FABRIC_DEVICE | |
3747 | FCF_LOGIN_NEEDED); | |
1da177e4 LT |
3748 | break; |
3749 | } | |
3750 | ||
3751 | /* | |
3752 | * Port ID changed or device was marked to be updated; | |
3753 | * Log it out if still logged in and mark it for | |
3754 | * relogin later. | |
3755 | */ | |
3756 | fcport->d_id.b24 = new_fcport->d_id.b24; | |
3757 | fcport->flags |= FCF_LOGIN_NEEDED; | |
3758 | if (fcport->loop_id != FC_NO_LOOP_ID && | |
f08b7251 | 3759 | (fcport->flags & FCF_FCP2_DEVICE) == 0 && |
0eba25df | 3760 | (fcport->flags & FCF_ASYNC_SENT) == 0 && |
1da177e4 LT |
3761 | fcport->port_type != FCT_INITIATOR && |
3762 | fcport->port_type != FCT_BROADCAST) { | |
e315cd28 | 3763 | ha->isp_ops->fabric_logout(vha, fcport->loop_id, |
1c7c6357 AV |
3764 | fcport->d_id.b.domain, fcport->d_id.b.area, |
3765 | fcport->d_id.b.al_pa); | |
5f16b331 | 3766 | qla2x00_clear_loop_id(fcport); |
1da177e4 LT |
3767 | } |
3768 | ||
3769 | break; | |
3770 | } | |
3771 | ||
3772 | if (found) | |
3773 | continue; | |
1da177e4 LT |
3774 | /* If device was not in our fcports list, then add it. */ |
3775 | list_add_tail(&new_fcport->list, new_fcports); | |
3776 | ||
3777 | /* Allocate a new replacement fcport. */ | |
3778 | nxt_d_id.b24 = new_fcport->d_id.b24; | |
e315cd28 | 3779 | new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); |
1da177e4 | 3780 | if (new_fcport == NULL) { |
7c3df132 SK |
3781 | ql_log(ql_log_warn, vha, 0x2066, |
3782 | "Memory allocation failed for fcport.\n"); | |
1da177e4 LT |
3783 | return (QLA_MEMORY_ALLOC_FAILED); |
3784 | } | |
3785 | new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED); | |
3786 | new_fcport->d_id.b24 = nxt_d_id.b24; | |
3787 | } | |
3788 | ||
c9475cb0 | 3789 | kfree(new_fcport); |
1da177e4 | 3790 | |
1da177e4 LT |
3791 | return (rval); |
3792 | } | |
3793 | ||
3794 | /* | |
3795 | * qla2x00_find_new_loop_id | |
3796 | * Scan through our port list and find a new usable loop ID. | |
3797 | * | |
3798 | * Input: | |
3799 | * ha: adapter state pointer. | |
3800 | * dev: port structure pointer. | |
3801 | * | |
3802 | * Returns: | |
3803 | * qla2x00 local function return status code. | |
3804 | * | |
3805 | * Context: | |
3806 | * Kernel context. | |
3807 | */ | |
03bcfb57 | 3808 | int |
e315cd28 | 3809 | qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev) |
1da177e4 LT |
3810 | { |
3811 | int rval; | |
e315cd28 | 3812 | struct qla_hw_data *ha = vha->hw; |
feafb7b1 | 3813 | unsigned long flags = 0; |
1da177e4 LT |
3814 | |
3815 | rval = QLA_SUCCESS; | |
3816 | ||
5f16b331 | 3817 | spin_lock_irqsave(&ha->vport_slock, flags); |
1da177e4 | 3818 | |
5f16b331 CD |
3819 | dev->loop_id = find_first_zero_bit(ha->loop_id_map, |
3820 | LOOPID_MAP_SIZE); | |
3821 | if (dev->loop_id >= LOOPID_MAP_SIZE || | |
3822 | qla2x00_is_reserved_id(vha, dev->loop_id)) { | |
3823 | dev->loop_id = FC_NO_LOOP_ID; | |
3824 | rval = QLA_FUNCTION_FAILED; | |
3825 | } else | |
3826 | set_bit(dev->loop_id, ha->loop_id_map); | |
1da177e4 | 3827 | |
5f16b331 | 3828 | spin_unlock_irqrestore(&ha->vport_slock, flags); |
1da177e4 | 3829 | |
5f16b331 CD |
3830 | if (rval == QLA_SUCCESS) |
3831 | ql_dbg(ql_dbg_disc, dev->vha, 0x2086, | |
3832 | "Assigning new loopid=%x, portid=%x.\n", | |
3833 | dev->loop_id, dev->d_id.b24); | |
3834 | else | |
3835 | ql_log(ql_log_warn, dev->vha, 0x2087, | |
3836 | "No loop_id's available, portid=%x.\n", | |
3837 | dev->d_id.b24); | |
1da177e4 LT |
3838 | |
3839 | return (rval); | |
3840 | } | |
3841 | ||
1da177e4 LT |
3842 | /* |
3843 | * qla2x00_fabric_dev_login | |
3844 | * Login fabric target device and update FC port database. | |
3845 | * | |
3846 | * Input: | |
3847 | * ha: adapter state pointer. | |
3848 | * fcport: port structure list pointer. | |
3849 | * next_loopid: contains value of a new loop ID that can be used | |
3850 | * by the next login attempt. | |
3851 | * | |
3852 | * Returns: | |
3853 | * qla2x00 local function return status code. | |
3854 | * | |
3855 | * Context: | |
3856 | * Kernel context. | |
3857 | */ | |
3858 | static int | |
e315cd28 | 3859 | qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport, |
1da177e4 LT |
3860 | uint16_t *next_loopid) |
3861 | { | |
3862 | int rval; | |
3863 | int retry; | |
0107109e | 3864 | uint8_t opts; |
e315cd28 | 3865 | struct qla_hw_data *ha = vha->hw; |
1da177e4 LT |
3866 | |
3867 | rval = QLA_SUCCESS; | |
3868 | retry = 0; | |
3869 | ||
ac280b67 | 3870 | if (IS_ALOGIO_CAPABLE(ha)) { |
5ff1d584 AV |
3871 | if (fcport->flags & FCF_ASYNC_SENT) |
3872 | return rval; | |
3873 | fcport->flags |= FCF_ASYNC_SENT; | |
ac280b67 AV |
3874 | rval = qla2x00_post_async_login_work(vha, fcport, NULL); |
3875 | if (!rval) | |
3876 | return rval; | |
3877 | } | |
3878 | ||
5ff1d584 | 3879 | fcport->flags &= ~FCF_ASYNC_SENT; |
e315cd28 | 3880 | rval = qla2x00_fabric_login(vha, fcport, next_loopid); |
1da177e4 | 3881 | if (rval == QLA_SUCCESS) { |
f08b7251 | 3882 | /* Send an ADISC to FCP2 devices.*/ |
0107109e | 3883 | opts = 0; |
f08b7251 | 3884 | if (fcport->flags & FCF_FCP2_DEVICE) |
0107109e | 3885 | opts |= BIT_1; |
e315cd28 | 3886 | rval = qla2x00_get_port_database(vha, fcport, opts); |
1da177e4 | 3887 | if (rval != QLA_SUCCESS) { |
e315cd28 | 3888 | ha->isp_ops->fabric_logout(vha, fcport->loop_id, |
1c7c6357 AV |
3889 | fcport->d_id.b.domain, fcport->d_id.b.area, |
3890 | fcport->d_id.b.al_pa); | |
e315cd28 | 3891 | qla2x00_mark_device_lost(vha, fcport, 1, 0); |
1da177e4 | 3892 | } else { |
e315cd28 | 3893 | qla2x00_update_fcport(vha, fcport); |
1da177e4 | 3894 | } |
0b91d116 CD |
3895 | } else { |
3896 | /* Retry Login. */ | |
3897 | qla2x00_mark_device_lost(vha, fcport, 1, 0); | |
1da177e4 LT |
3898 | } |
3899 | ||
3900 | return (rval); | |
3901 | } | |
3902 | ||
3903 | /* | |
3904 | * qla2x00_fabric_login | |
3905 | * Issue fabric login command. | |
3906 | * | |
3907 | * Input: | |
3908 | * ha = adapter block pointer. | |
3909 | * device = pointer to FC device type structure. | |
3910 | * | |
3911 | * Returns: | |
3912 | * 0 - Login successfully | |
3913 | * 1 - Login failed | |
3914 | * 2 - Initiator device | |
3915 | * 3 - Fatal error | |
3916 | */ | |
3917 | int | |
e315cd28 | 3918 | qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport, |
1da177e4 LT |
3919 | uint16_t *next_loopid) |
3920 | { | |
3921 | int rval; | |
3922 | int retry; | |
3923 | uint16_t tmp_loopid; | |
3924 | uint16_t mb[MAILBOX_REGISTER_COUNT]; | |
e315cd28 | 3925 | struct qla_hw_data *ha = vha->hw; |
1da177e4 LT |
3926 | |
3927 | retry = 0; | |
3928 | tmp_loopid = 0; | |
3929 | ||
3930 | for (;;) { | |
7c3df132 SK |
3931 | ql_dbg(ql_dbg_disc, vha, 0x2000, |
3932 | "Trying Fabric Login w/loop id 0x%04x for port " | |
3933 | "%02x%02x%02x.\n", | |
3934 | fcport->loop_id, fcport->d_id.b.domain, | |
3935 | fcport->d_id.b.area, fcport->d_id.b.al_pa); | |
1da177e4 LT |
3936 | |
3937 | /* Login fcport on switch. */ | |
0b91d116 | 3938 | rval = ha->isp_ops->fabric_login(vha, fcport->loop_id, |
1da177e4 LT |
3939 | fcport->d_id.b.domain, fcport->d_id.b.area, |
3940 | fcport->d_id.b.al_pa, mb, BIT_0); | |
0b91d116 CD |
3941 | if (rval != QLA_SUCCESS) { |
3942 | return rval; | |
3943 | } | |
1da177e4 LT |
3944 | if (mb[0] == MBS_PORT_ID_USED) { |
3945 | /* | |
3946 | * Device has another loop ID. The firmware team | |
0107109e AV |
3947 | * recommends the driver perform an implicit login with |
3948 | * the specified ID again. The ID we just used is save | |
3949 | * here so we return with an ID that can be tried by | |
3950 | * the next login. | |
1da177e4 LT |
3951 | */ |
3952 | retry++; | |
3953 | tmp_loopid = fcport->loop_id; | |
3954 | fcport->loop_id = mb[1]; | |
3955 | ||
7c3df132 SK |
3956 | ql_dbg(ql_dbg_disc, vha, 0x2001, |
3957 | "Fabric Login: port in use - next loop " | |
3958 | "id=0x%04x, port id= %02x%02x%02x.\n", | |
1da177e4 | 3959 | fcport->loop_id, fcport->d_id.b.domain, |
7c3df132 | 3960 | fcport->d_id.b.area, fcport->d_id.b.al_pa); |
1da177e4 LT |
3961 | |
3962 | } else if (mb[0] == MBS_COMMAND_COMPLETE) { | |
3963 | /* | |
3964 | * Login succeeded. | |
3965 | */ | |
3966 | if (retry) { | |
3967 | /* A retry occurred before. */ | |
3968 | *next_loopid = tmp_loopid; | |
3969 | } else { | |
3970 | /* | |
3971 | * No retry occurred before. Just increment the | |
3972 | * ID value for next login. | |
3973 | */ | |
3974 | *next_loopid = (fcport->loop_id + 1); | |
3975 | } | |
3976 | ||
3977 | if (mb[1] & BIT_0) { | |
3978 | fcport->port_type = FCT_INITIATOR; | |
3979 | } else { | |
3980 | fcport->port_type = FCT_TARGET; | |
3981 | if (mb[1] & BIT_1) { | |
8474f3a0 | 3982 | fcport->flags |= FCF_FCP2_DEVICE; |
1da177e4 LT |
3983 | } |
3984 | } | |
3985 | ||
ad3e0eda AV |
3986 | if (mb[10] & BIT_0) |
3987 | fcport->supported_classes |= FC_COS_CLASS2; | |
3988 | if (mb[10] & BIT_1) | |
3989 | fcport->supported_classes |= FC_COS_CLASS3; | |
3990 | ||
2d70c103 NB |
3991 | if (IS_FWI2_CAPABLE(ha)) { |
3992 | if (mb[10] & BIT_7) | |
3993 | fcport->flags |= | |
3994 | FCF_CONF_COMP_SUPPORTED; | |
3995 | } | |
3996 | ||
1da177e4 LT |
3997 | rval = QLA_SUCCESS; |
3998 | break; | |
3999 | } else if (mb[0] == MBS_LOOP_ID_USED) { | |
4000 | /* | |
4001 | * Loop ID already used, try next loop ID. | |
4002 | */ | |
4003 | fcport->loop_id++; | |
e315cd28 | 4004 | rval = qla2x00_find_new_loop_id(vha, fcport); |
1da177e4 LT |
4005 | if (rval != QLA_SUCCESS) { |
4006 | /* Ran out of loop IDs to use */ | |
4007 | break; | |
4008 | } | |
4009 | } else if (mb[0] == MBS_COMMAND_ERROR) { | |
4010 | /* | |
4011 | * Firmware possibly timed out during login. If NO | |
4012 | * retries are left to do then the device is declared | |
4013 | * dead. | |
4014 | */ | |
4015 | *next_loopid = fcport->loop_id; | |
e315cd28 | 4016 | ha->isp_ops->fabric_logout(vha, fcport->loop_id, |
1c7c6357 AV |
4017 | fcport->d_id.b.domain, fcport->d_id.b.area, |
4018 | fcport->d_id.b.al_pa); | |
e315cd28 | 4019 | qla2x00_mark_device_lost(vha, fcport, 1, 0); |
1da177e4 LT |
4020 | |
4021 | rval = 1; | |
4022 | break; | |
4023 | } else { | |
4024 | /* | |
4025 | * unrecoverable / not handled error | |
4026 | */ | |
7c3df132 SK |
4027 | ql_dbg(ql_dbg_disc, vha, 0x2002, |
4028 | "Failed=%x port_id=%02x%02x%02x loop_id=%x " | |
4029 | "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain, | |
4030 | fcport->d_id.b.area, fcport->d_id.b.al_pa, | |
4031 | fcport->loop_id, jiffies); | |
1da177e4 LT |
4032 | |
4033 | *next_loopid = fcport->loop_id; | |
e315cd28 | 4034 | ha->isp_ops->fabric_logout(vha, fcport->loop_id, |
1c7c6357 AV |
4035 | fcport->d_id.b.domain, fcport->d_id.b.area, |
4036 | fcport->d_id.b.al_pa); | |
5f16b331 | 4037 | qla2x00_clear_loop_id(fcport); |
0eedfcf0 | 4038 | fcport->login_retry = 0; |
1da177e4 LT |
4039 | |
4040 | rval = 3; | |
4041 | break; | |
4042 | } | |
4043 | } | |
4044 | ||
4045 | return (rval); | |
4046 | } | |
4047 | ||
4048 | /* | |
4049 | * qla2x00_local_device_login | |
4050 | * Issue local device login command. | |
4051 | * | |
4052 | * Input: | |
4053 | * ha = adapter block pointer. | |
4054 | * loop_id = loop id of device to login to. | |
4055 | * | |
4056 | * Returns (Where's the #define!!!!): | |
4057 | * 0 - Login successfully | |
4058 | * 1 - Login failed | |
4059 | * 3 - Fatal error | |
4060 | */ | |
4061 | int | |
e315cd28 | 4062 | qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport) |
1da177e4 LT |
4063 | { |
4064 | int rval; | |
4065 | uint16_t mb[MAILBOX_REGISTER_COUNT]; | |
4066 | ||
4067 | memset(mb, 0, sizeof(mb)); | |
e315cd28 | 4068 | rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0); |
1da177e4 LT |
4069 | if (rval == QLA_SUCCESS) { |
4070 | /* Interrogate mailbox registers for any errors */ | |
4071 | if (mb[0] == MBS_COMMAND_ERROR) | |
4072 | rval = 1; | |
4073 | else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR) | |
4074 | /* device not in PCB table */ | |
4075 | rval = 3; | |
4076 | } | |
4077 | ||
4078 | return (rval); | |
4079 | } | |
4080 | ||
4081 | /* | |
4082 | * qla2x00_loop_resync | |
4083 | * Resync with fibre channel devices. | |
4084 | * | |
4085 | * Input: | |
4086 | * ha = adapter block pointer. | |
4087 | * | |
4088 | * Returns: | |
4089 | * 0 = success | |
4090 | */ | |
4091 | int | |
e315cd28 | 4092 | qla2x00_loop_resync(scsi_qla_host_t *vha) |
1da177e4 | 4093 | { |
73208dfd | 4094 | int rval = QLA_SUCCESS; |
1da177e4 | 4095 | uint32_t wait_time; |
67c2e93a AC |
4096 | struct req_que *req; |
4097 | struct rsp_que *rsp; | |
4098 | ||
7163ea81 | 4099 | if (vha->hw->flags.cpu_affinity_enabled) |
67c2e93a AC |
4100 | req = vha->hw->req_q_map[0]; |
4101 | else | |
4102 | req = vha->req; | |
4103 | rsp = req->rsp; | |
1da177e4 | 4104 | |
e315cd28 AC |
4105 | clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); |
4106 | if (vha->flags.online) { | |
4107 | if (!(rval = qla2x00_fw_ready(vha))) { | |
1da177e4 LT |
4108 | /* Wait at most MAX_TARGET RSCNs for a stable link. */ |
4109 | wait_time = 256; | |
4110 | do { | |
8ae6d9c7 GM |
4111 | if (!IS_QLAFX00(vha->hw)) { |
4112 | /* | |
4113 | * Issue a marker after FW becomes | |
4114 | * ready. | |
4115 | */ | |
4116 | qla2x00_marker(vha, req, rsp, 0, 0, | |
4117 | MK_SYNC_ALL); | |
4118 | vha->marker_needed = 0; | |
4119 | } | |
1da177e4 LT |
4120 | |
4121 | /* Remap devices on Loop. */ | |
e315cd28 | 4122 | clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); |
1da177e4 | 4123 | |
8ae6d9c7 GM |
4124 | if (IS_QLAFX00(vha->hw)) |
4125 | qlafx00_configure_devices(vha); | |
4126 | else | |
4127 | qla2x00_configure_loop(vha); | |
4128 | ||
1da177e4 | 4129 | wait_time--; |
e315cd28 AC |
4130 | } while (!atomic_read(&vha->loop_down_timer) && |
4131 | !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) | |
4132 | && wait_time && (test_bit(LOOP_RESYNC_NEEDED, | |
4133 | &vha->dpc_flags))); | |
1da177e4 | 4134 | } |
1da177e4 LT |
4135 | } |
4136 | ||
e315cd28 | 4137 | if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) |
1da177e4 | 4138 | return (QLA_FUNCTION_FAILED); |
1da177e4 | 4139 | |
e315cd28 | 4140 | if (rval) |
7c3df132 SK |
4141 | ql_dbg(ql_dbg_disc, vha, 0x206c, |
4142 | "%s *** FAILED ***.\n", __func__); | |
1da177e4 LT |
4143 | |
4144 | return (rval); | |
4145 | } | |
4146 | ||
579d12b5 SK |
4147 | /* |
4148 | * qla2x00_perform_loop_resync | |
4149 | * Description: This function will set the appropriate flags and call | |
4150 | * qla2x00_loop_resync. If successful loop will be resynced | |
4151 | * Arguments : scsi_qla_host_t pointer | |
4152 | * returm : Success or Failure | |
4153 | */ | |
4154 | ||
4155 | int qla2x00_perform_loop_resync(scsi_qla_host_t *ha) | |
4156 | { | |
4157 | int32_t rval = 0; | |
4158 | ||
4159 | if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) { | |
4160 | /*Configure the flags so that resync happens properly*/ | |
4161 | atomic_set(&ha->loop_down_timer, 0); | |
4162 | if (!(ha->device_flags & DFLG_NO_CABLE)) { | |
4163 | atomic_set(&ha->loop_state, LOOP_UP); | |
4164 | set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags); | |
4165 | set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags); | |
4166 | set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags); | |
4167 | ||
4168 | rval = qla2x00_loop_resync(ha); | |
4169 | } else | |
4170 | atomic_set(&ha->loop_state, LOOP_DEAD); | |
4171 | ||
4172 | clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags); | |
4173 | } | |
4174 | ||
4175 | return rval; | |
4176 | } | |
4177 | ||
d97994dc | 4178 | void |
67becc00 | 4179 | qla2x00_update_fcports(scsi_qla_host_t *base_vha) |
d97994dc | 4180 | { |
4181 | fc_port_t *fcport; | |
feafb7b1 AE |
4182 | struct scsi_qla_host *vha; |
4183 | struct qla_hw_data *ha = base_vha->hw; | |
4184 | unsigned long flags; | |
d97994dc | 4185 | |
feafb7b1 | 4186 | spin_lock_irqsave(&ha->vport_slock, flags); |
d97994dc | 4187 | /* Go with deferred removal of rport references. */ |
feafb7b1 AE |
4188 | list_for_each_entry(vha, &base_vha->hw->vp_list, list) { |
4189 | atomic_inc(&vha->vref_count); | |
4190 | list_for_each_entry(fcport, &vha->vp_fcports, list) { | |
8ae598d0 | 4191 | if (fcport->drport && |
feafb7b1 AE |
4192 | atomic_read(&fcport->state) != FCS_UNCONFIGURED) { |
4193 | spin_unlock_irqrestore(&ha->vport_slock, flags); | |
67becc00 | 4194 | qla2x00_rport_del(fcport); |
feafb7b1 AE |
4195 | spin_lock_irqsave(&ha->vport_slock, flags); |
4196 | } | |
4197 | } | |
4198 | atomic_dec(&vha->vref_count); | |
4199 | } | |
4200 | spin_unlock_irqrestore(&ha->vport_slock, flags); | |
d97994dc | 4201 | } |
4202 | ||
7d613ac6 SV |
4203 | /* Assumes idc_lock always held on entry */ |
4204 | void | |
4205 | qla83xx_reset_ownership(scsi_qla_host_t *vha) | |
4206 | { | |
4207 | struct qla_hw_data *ha = vha->hw; | |
4208 | uint32_t drv_presence, drv_presence_mask; | |
4209 | uint32_t dev_part_info1, dev_part_info2, class_type; | |
4210 | uint32_t class_type_mask = 0x3; | |
4211 | uint16_t fcoe_other_function = 0xffff, i; | |
4212 | ||
7ec0effd AD |
4213 | if (IS_QLA8044(ha)) { |
4214 | drv_presence = qla8044_rd_direct(vha, | |
4215 | QLA8044_CRB_DRV_ACTIVE_INDEX); | |
4216 | dev_part_info1 = qla8044_rd_direct(vha, | |
4217 | QLA8044_CRB_DEV_PART_INFO_INDEX); | |
4218 | dev_part_info2 = qla8044_rd_direct(vha, | |
4219 | QLA8044_CRB_DEV_PART_INFO2); | |
4220 | } else { | |
4221 | qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); | |
4222 | qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1); | |
4223 | qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2); | |
4224 | } | |
7d613ac6 SV |
4225 | for (i = 0; i < 8; i++) { |
4226 | class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask); | |
4227 | if ((class_type == QLA83XX_CLASS_TYPE_FCOE) && | |
4228 | (i != ha->portnum)) { | |
4229 | fcoe_other_function = i; | |
4230 | break; | |
4231 | } | |
4232 | } | |
4233 | if (fcoe_other_function == 0xffff) { | |
4234 | for (i = 0; i < 8; i++) { | |
4235 | class_type = ((dev_part_info2 >> (i * 4)) & | |
4236 | class_type_mask); | |
4237 | if ((class_type == QLA83XX_CLASS_TYPE_FCOE) && | |
4238 | ((i + 8) != ha->portnum)) { | |
4239 | fcoe_other_function = i + 8; | |
4240 | break; | |
4241 | } | |
4242 | } | |
4243 | } | |
4244 | /* | |
4245 | * Prepare drv-presence mask based on fcoe functions present. | |
4246 | * However consider only valid physical fcoe function numbers (0-15). | |
4247 | */ | |
4248 | drv_presence_mask = ~((1 << (ha->portnum)) | | |
4249 | ((fcoe_other_function == 0xffff) ? | |
4250 | 0 : (1 << (fcoe_other_function)))); | |
4251 | ||
4252 | /* We are the reset owner iff: | |
4253 | * - No other protocol drivers present. | |
4254 | * - This is the lowest among fcoe functions. */ | |
4255 | if (!(drv_presence & drv_presence_mask) && | |
4256 | (ha->portnum < fcoe_other_function)) { | |
4257 | ql_dbg(ql_dbg_p3p, vha, 0xb07f, | |
4258 | "This host is Reset owner.\n"); | |
4259 | ha->flags.nic_core_reset_owner = 1; | |
4260 | } | |
4261 | } | |
4262 | ||
fa492630 | 4263 | static int |
7d613ac6 SV |
4264 | __qla83xx_set_drv_ack(scsi_qla_host_t *vha) |
4265 | { | |
4266 | int rval = QLA_SUCCESS; | |
4267 | struct qla_hw_data *ha = vha->hw; | |
4268 | uint32_t drv_ack; | |
4269 | ||
4270 | rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); | |
4271 | if (rval == QLA_SUCCESS) { | |
4272 | drv_ack |= (1 << ha->portnum); | |
4273 | rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack); | |
4274 | } | |
4275 | ||
4276 | return rval; | |
4277 | } | |
4278 | ||
fa492630 | 4279 | static int |
7d613ac6 SV |
4280 | __qla83xx_clear_drv_ack(scsi_qla_host_t *vha) |
4281 | { | |
4282 | int rval = QLA_SUCCESS; | |
4283 | struct qla_hw_data *ha = vha->hw; | |
4284 | uint32_t drv_ack; | |
4285 | ||
4286 | rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); | |
4287 | if (rval == QLA_SUCCESS) { | |
4288 | drv_ack &= ~(1 << ha->portnum); | |
4289 | rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack); | |
4290 | } | |
4291 | ||
4292 | return rval; | |
4293 | } | |
4294 | ||
fa492630 | 4295 | static const char * |
7d613ac6 SV |
4296 | qla83xx_dev_state_to_string(uint32_t dev_state) |
4297 | { | |
4298 | switch (dev_state) { | |
4299 | case QLA8XXX_DEV_COLD: | |
4300 | return "COLD/RE-INIT"; | |
4301 | case QLA8XXX_DEV_INITIALIZING: | |
4302 | return "INITIALIZING"; | |
4303 | case QLA8XXX_DEV_READY: | |
4304 | return "READY"; | |
4305 | case QLA8XXX_DEV_NEED_RESET: | |
4306 | return "NEED RESET"; | |
4307 | case QLA8XXX_DEV_NEED_QUIESCENT: | |
4308 | return "NEED QUIESCENT"; | |
4309 | case QLA8XXX_DEV_FAILED: | |
4310 | return "FAILED"; | |
4311 | case QLA8XXX_DEV_QUIESCENT: | |
4312 | return "QUIESCENT"; | |
4313 | default: | |
4314 | return "Unknown"; | |
4315 | } | |
4316 | } | |
4317 | ||
4318 | /* Assumes idc-lock always held on entry */ | |
4319 | void | |
4320 | qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type) | |
4321 | { | |
4322 | struct qla_hw_data *ha = vha->hw; | |
4323 | uint32_t idc_audit_reg = 0, duration_secs = 0; | |
4324 | ||
4325 | switch (audit_type) { | |
4326 | case IDC_AUDIT_TIMESTAMP: | |
4327 | ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000); | |
4328 | idc_audit_reg = (ha->portnum) | | |
4329 | (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8); | |
4330 | qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg); | |
4331 | break; | |
4332 | ||
4333 | case IDC_AUDIT_COMPLETION: | |
4334 | duration_secs = ((jiffies_to_msecs(jiffies) - | |
4335 | jiffies_to_msecs(ha->idc_audit_ts)) / 1000); | |
4336 | idc_audit_reg = (ha->portnum) | | |
4337 | (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8); | |
4338 | qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg); | |
4339 | break; | |
4340 | ||
4341 | default: | |
4342 | ql_log(ql_log_warn, vha, 0xb078, | |
4343 | "Invalid audit type specified.\n"); | |
4344 | break; | |
4345 | } | |
4346 | } | |
4347 | ||
4348 | /* Assumes idc_lock always held on entry */ | |
fa492630 | 4349 | static int |
7d613ac6 SV |
4350 | qla83xx_initiating_reset(scsi_qla_host_t *vha) |
4351 | { | |
4352 | struct qla_hw_data *ha = vha->hw; | |
4353 | uint32_t idc_control, dev_state; | |
4354 | ||
4355 | __qla83xx_get_idc_control(vha, &idc_control); | |
4356 | if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) { | |
4357 | ql_log(ql_log_info, vha, 0xb080, | |
4358 | "NIC Core reset has been disabled. idc-control=0x%x\n", | |
4359 | idc_control); | |
4360 | return QLA_FUNCTION_FAILED; | |
4361 | } | |
4362 | ||
4363 | /* Set NEED-RESET iff in READY state and we are the reset-owner */ | |
4364 | qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state); | |
4365 | if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) { | |
4366 | qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, | |
4367 | QLA8XXX_DEV_NEED_RESET); | |
4368 | ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n"); | |
4369 | qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP); | |
4370 | } else { | |
4371 | const char *state = qla83xx_dev_state_to_string(dev_state); | |
4372 | ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state); | |
4373 | ||
4374 | /* SV: XXX: Is timeout required here? */ | |
4375 | /* Wait for IDC state change READY -> NEED_RESET */ | |
4376 | while (dev_state == QLA8XXX_DEV_READY) { | |
4377 | qla83xx_idc_unlock(vha, 0); | |
4378 | msleep(200); | |
4379 | qla83xx_idc_lock(vha, 0); | |
4380 | qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state); | |
4381 | } | |
4382 | } | |
4383 | ||
4384 | /* Send IDC ack by writing to drv-ack register */ | |
4385 | __qla83xx_set_drv_ack(vha); | |
4386 | ||
4387 | return QLA_SUCCESS; | |
4388 | } | |
4389 | ||
4390 | int | |
4391 | __qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control) | |
4392 | { | |
4393 | return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control); | |
4394 | } | |
4395 | ||
7d613ac6 SV |
4396 | int |
4397 | __qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control) | |
4398 | { | |
4399 | return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control); | |
4400 | } | |
4401 | ||
fa492630 | 4402 | static int |
7d613ac6 SV |
4403 | qla83xx_check_driver_presence(scsi_qla_host_t *vha) |
4404 | { | |
4405 | uint32_t drv_presence = 0; | |
4406 | struct qla_hw_data *ha = vha->hw; | |
4407 | ||
4408 | qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); | |
4409 | if (drv_presence & (1 << ha->portnum)) | |
4410 | return QLA_SUCCESS; | |
4411 | else | |
4412 | return QLA_TEST_FAILED; | |
4413 | } | |
4414 | ||
4415 | int | |
4416 | qla83xx_nic_core_reset(scsi_qla_host_t *vha) | |
4417 | { | |
4418 | int rval = QLA_SUCCESS; | |
4419 | struct qla_hw_data *ha = vha->hw; | |
4420 | ||
4421 | ql_dbg(ql_dbg_p3p, vha, 0xb058, | |
4422 | "Entered %s().\n", __func__); | |
4423 | ||
4424 | if (vha->device_flags & DFLG_DEV_FAILED) { | |
4425 | ql_log(ql_log_warn, vha, 0xb059, | |
4426 | "Device in unrecoverable FAILED state.\n"); | |
4427 | return QLA_FUNCTION_FAILED; | |
4428 | } | |
4429 | ||
4430 | qla83xx_idc_lock(vha, 0); | |
4431 | ||
4432 | if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) { | |
4433 | ql_log(ql_log_warn, vha, 0xb05a, | |
4434 | "Function=0x%x has been removed from IDC participation.\n", | |
4435 | ha->portnum); | |
4436 | rval = QLA_FUNCTION_FAILED; | |
4437 | goto exit; | |
4438 | } | |
4439 | ||
4440 | qla83xx_reset_ownership(vha); | |
4441 | ||
4442 | rval = qla83xx_initiating_reset(vha); | |
4443 | ||
4444 | /* | |
4445 | * Perform reset if we are the reset-owner, | |
4446 | * else wait till IDC state changes to READY/FAILED. | |
4447 | */ | |
4448 | if (rval == QLA_SUCCESS) { | |
4449 | rval = qla83xx_idc_state_handler(vha); | |
4450 | ||
4451 | if (rval == QLA_SUCCESS) | |
4452 | ha->flags.nic_core_hung = 0; | |
4453 | __qla83xx_clear_drv_ack(vha); | |
4454 | } | |
4455 | ||
4456 | exit: | |
4457 | qla83xx_idc_unlock(vha, 0); | |
4458 | ||
4459 | ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__); | |
4460 | ||
4461 | return rval; | |
4462 | } | |
4463 | ||
81178772 SK |
4464 | int |
4465 | qla2xxx_mctp_dump(scsi_qla_host_t *vha) | |
4466 | { | |
4467 | struct qla_hw_data *ha = vha->hw; | |
4468 | int rval = QLA_FUNCTION_FAILED; | |
4469 | ||
4470 | if (!IS_MCTP_CAPABLE(ha)) { | |
4471 | /* This message can be removed from the final version */ | |
4472 | ql_log(ql_log_info, vha, 0x506d, | |
4473 | "This board is not MCTP capable\n"); | |
4474 | return rval; | |
4475 | } | |
4476 | ||
4477 | if (!ha->mctp_dump) { | |
4478 | ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev, | |
4479 | MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL); | |
4480 | ||
4481 | if (!ha->mctp_dump) { | |
4482 | ql_log(ql_log_warn, vha, 0x506e, | |
4483 | "Failed to allocate memory for mctp dump\n"); | |
4484 | return rval; | |
4485 | } | |
4486 | } | |
4487 | ||
4488 | #define MCTP_DUMP_STR_ADDR 0x00000000 | |
4489 | rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma, | |
4490 | MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4); | |
4491 | if (rval != QLA_SUCCESS) { | |
4492 | ql_log(ql_log_warn, vha, 0x506f, | |
4493 | "Failed to capture mctp dump\n"); | |
4494 | } else { | |
4495 | ql_log(ql_log_info, vha, 0x5070, | |
4496 | "Mctp dump capture for host (%ld/%p).\n", | |
4497 | vha->host_no, ha->mctp_dump); | |
4498 | ha->mctp_dumped = 1; | |
4499 | } | |
4500 | ||
409ee0fe | 4501 | if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) { |
81178772 SK |
4502 | ha->flags.nic_core_reset_hdlr_active = 1; |
4503 | rval = qla83xx_restart_nic_firmware(vha); | |
4504 | if (rval) | |
4505 | /* NIC Core reset failed. */ | |
4506 | ql_log(ql_log_warn, vha, 0x5071, | |
4507 | "Failed to restart nic firmware\n"); | |
4508 | else | |
4509 | ql_dbg(ql_dbg_p3p, vha, 0xb084, | |
4510 | "Restarted NIC firmware successfully.\n"); | |
4511 | ha->flags.nic_core_reset_hdlr_active = 0; | |
4512 | } | |
4513 | ||
4514 | return rval; | |
4515 | ||
4516 | } | |
4517 | ||
579d12b5 | 4518 | /* |
8fcd6b8b | 4519 | * qla2x00_quiesce_io |
579d12b5 SK |
4520 | * Description: This function will block the new I/Os |
4521 | * Its not aborting any I/Os as context | |
4522 | * is not destroyed during quiescence | |
4523 | * Arguments: scsi_qla_host_t | |
4524 | * return : void | |
4525 | */ | |
4526 | void | |
8fcd6b8b | 4527 | qla2x00_quiesce_io(scsi_qla_host_t *vha) |
579d12b5 SK |
4528 | { |
4529 | struct qla_hw_data *ha = vha->hw; | |
4530 | struct scsi_qla_host *vp; | |
4531 | ||
8fcd6b8b CD |
4532 | ql_dbg(ql_dbg_dpc, vha, 0x401d, |
4533 | "Quiescing I/O - ha=%p.\n", ha); | |
579d12b5 SK |
4534 | |
4535 | atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME); | |
4536 | if (atomic_read(&vha->loop_state) != LOOP_DOWN) { | |
4537 | atomic_set(&vha->loop_state, LOOP_DOWN); | |
4538 | qla2x00_mark_all_devices_lost(vha, 0); | |
4539 | list_for_each_entry(vp, &ha->vp_list, list) | |
8fcd6b8b | 4540 | qla2x00_mark_all_devices_lost(vp, 0); |
579d12b5 SK |
4541 | } else { |
4542 | if (!atomic_read(&vha->loop_down_timer)) | |
4543 | atomic_set(&vha->loop_down_timer, | |
4544 | LOOP_DOWN_TIME); | |
4545 | } | |
4546 | /* Wait for pending cmds to complete */ | |
4547 | qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST); | |
4548 | } | |
4549 | ||
a9083016 GM |
4550 | void |
4551 | qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha) | |
4552 | { | |
4553 | struct qla_hw_data *ha = vha->hw; | |
579d12b5 | 4554 | struct scsi_qla_host *vp; |
feafb7b1 | 4555 | unsigned long flags; |
6aef87be | 4556 | fc_port_t *fcport; |
a9083016 | 4557 | |
e46ef004 SK |
4558 | /* For ISP82XX, driver waits for completion of the commands. |
4559 | * online flag should be set. | |
4560 | */ | |
7ec0effd | 4561 | if (!(IS_P3P_TYPE(ha))) |
e46ef004 | 4562 | vha->flags.online = 0; |
a9083016 GM |
4563 | ha->flags.chip_reset_done = 0; |
4564 | clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); | |
2be21fa2 | 4565 | vha->qla_stats.total_isp_aborts++; |
a9083016 | 4566 | |
7c3df132 SK |
4567 | ql_log(ql_log_info, vha, 0x00af, |
4568 | "Performing ISP error recovery - ha=%p.\n", ha); | |
a9083016 | 4569 | |
e46ef004 SK |
4570 | /* For ISP82XX, reset_chip is just disabling interrupts. |
4571 | * Driver waits for the completion of the commands. | |
4572 | * the interrupts need to be enabled. | |
4573 | */ | |
7ec0effd | 4574 | if (!(IS_P3P_TYPE(ha))) |
a9083016 GM |
4575 | ha->isp_ops->reset_chip(vha); |
4576 | ||
4577 | atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); | |
4578 | if (atomic_read(&vha->loop_state) != LOOP_DOWN) { | |
4579 | atomic_set(&vha->loop_state, LOOP_DOWN); | |
4580 | qla2x00_mark_all_devices_lost(vha, 0); | |
feafb7b1 AE |
4581 | |
4582 | spin_lock_irqsave(&ha->vport_slock, flags); | |
579d12b5 | 4583 | list_for_each_entry(vp, &ha->vp_list, list) { |
feafb7b1 AE |
4584 | atomic_inc(&vp->vref_count); |
4585 | spin_unlock_irqrestore(&ha->vport_slock, flags); | |
4586 | ||
a9083016 | 4587 | qla2x00_mark_all_devices_lost(vp, 0); |
feafb7b1 AE |
4588 | |
4589 | spin_lock_irqsave(&ha->vport_slock, flags); | |
4590 | atomic_dec(&vp->vref_count); | |
4591 | } | |
4592 | spin_unlock_irqrestore(&ha->vport_slock, flags); | |
a9083016 GM |
4593 | } else { |
4594 | if (!atomic_read(&vha->loop_down_timer)) | |
4595 | atomic_set(&vha->loop_down_timer, | |
4596 | LOOP_DOWN_TIME); | |
4597 | } | |
4598 | ||
6aef87be AV |
4599 | /* Clear all async request states across all VPs. */ |
4600 | list_for_each_entry(fcport, &vha->vp_fcports, list) | |
4601 | fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); | |
4602 | spin_lock_irqsave(&ha->vport_slock, flags); | |
4603 | list_for_each_entry(vp, &ha->vp_list, list) { | |
4604 | atomic_inc(&vp->vref_count); | |
4605 | spin_unlock_irqrestore(&ha->vport_slock, flags); | |
4606 | ||
4607 | list_for_each_entry(fcport, &vp->vp_fcports, list) | |
4608 | fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); | |
4609 | ||
4610 | spin_lock_irqsave(&ha->vport_slock, flags); | |
4611 | atomic_dec(&vp->vref_count); | |
4612 | } | |
4613 | spin_unlock_irqrestore(&ha->vport_slock, flags); | |
4614 | ||
bddd2d65 LC |
4615 | if (!ha->flags.eeh_busy) { |
4616 | /* Make sure for ISP 82XX IO DMA is complete */ | |
7ec0effd | 4617 | if (IS_P3P_TYPE(ha)) { |
7190575f | 4618 | qla82xx_chip_reset_cleanup(vha); |
7c3df132 SK |
4619 | ql_log(ql_log_info, vha, 0x00b4, |
4620 | "Done chip reset cleanup.\n"); | |
a9083016 | 4621 | |
e46ef004 SK |
4622 | /* Done waiting for pending commands. |
4623 | * Reset the online flag. | |
4624 | */ | |
4625 | vha->flags.online = 0; | |
4d78c973 | 4626 | } |
a9083016 | 4627 | |
bddd2d65 LC |
4628 | /* Requeue all commands in outstanding command list. */ |
4629 | qla2x00_abort_all_cmds(vha, DID_RESET << 16); | |
4630 | } | |
b6a029e1 AE |
4631 | |
4632 | ha->chip_reset++; | |
4633 | /* memory barrier */ | |
4634 | wmb(); | |
a9083016 GM |
4635 | } |
4636 | ||
1da177e4 LT |
4637 | /* |
4638 | * qla2x00_abort_isp | |
4639 | * Resets ISP and aborts all outstanding commands. | |
4640 | * | |
4641 | * Input: | |
4642 | * ha = adapter block pointer. | |
4643 | * | |
4644 | * Returns: | |
4645 | * 0 = success | |
4646 | */ | |
4647 | int | |
e315cd28 | 4648 | qla2x00_abort_isp(scsi_qla_host_t *vha) |
1da177e4 | 4649 | { |
476e8978 | 4650 | int rval; |
1da177e4 | 4651 | uint8_t status = 0; |
e315cd28 AC |
4652 | struct qla_hw_data *ha = vha->hw; |
4653 | struct scsi_qla_host *vp; | |
73208dfd | 4654 | struct req_que *req = ha->req_q_map[0]; |
feafb7b1 | 4655 | unsigned long flags; |
1da177e4 | 4656 | |
e315cd28 | 4657 | if (vha->flags.online) { |
a9083016 | 4658 | qla2x00_abort_isp_cleanup(vha); |
1da177e4 | 4659 | |
a6171297 SV |
4660 | if (IS_QLA8031(ha)) { |
4661 | ql_dbg(ql_dbg_p3p, vha, 0xb05c, | |
4662 | "Clearing fcoe driver presence.\n"); | |
4663 | if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS) | |
4664 | ql_dbg(ql_dbg_p3p, vha, 0xb073, | |
4665 | "Error while clearing DRV-Presence.\n"); | |
4666 | } | |
4667 | ||
85880801 AV |
4668 | if (unlikely(pci_channel_offline(ha->pdev) && |
4669 | ha->flags.pci_channel_io_perm_failure)) { | |
4670 | clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); | |
4671 | status = 0; | |
4672 | return status; | |
4673 | } | |
4674 | ||
73208dfd | 4675 | ha->isp_ops->get_flash_version(vha, req->ring); |
30c47662 | 4676 | |
e315cd28 | 4677 | ha->isp_ops->nvram_config(vha); |
1da177e4 | 4678 | |
e315cd28 AC |
4679 | if (!qla2x00_restart_isp(vha)) { |
4680 | clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); | |
1da177e4 | 4681 | |
e315cd28 | 4682 | if (!atomic_read(&vha->loop_down_timer)) { |
1da177e4 LT |
4683 | /* |
4684 | * Issue marker command only when we are going | |
4685 | * to start the I/O . | |
4686 | */ | |
e315cd28 | 4687 | vha->marker_needed = 1; |
1da177e4 LT |
4688 | } |
4689 | ||
e315cd28 | 4690 | vha->flags.online = 1; |
1da177e4 | 4691 | |
fd34f556 | 4692 | ha->isp_ops->enable_intrs(ha); |
1da177e4 | 4693 | |
fa2a1ce5 | 4694 | ha->isp_abort_cnt = 0; |
e315cd28 | 4695 | clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); |
476e8978 | 4696 | |
6246b8a1 GM |
4697 | if (IS_QLA81XX(ha) || IS_QLA8031(ha)) |
4698 | qla2x00_get_fw_version(vha); | |
df613b96 AV |
4699 | if (ha->fce) { |
4700 | ha->flags.fce_enabled = 1; | |
4701 | memset(ha->fce, 0, | |
4702 | fce_calc_size(ha->fce_bufs)); | |
e315cd28 | 4703 | rval = qla2x00_enable_fce_trace(vha, |
df613b96 AV |
4704 | ha->fce_dma, ha->fce_bufs, ha->fce_mb, |
4705 | &ha->fce_bufs); | |
4706 | if (rval) { | |
7c3df132 | 4707 | ql_log(ql_log_warn, vha, 0x8033, |
df613b96 AV |
4708 | "Unable to reinitialize FCE " |
4709 | "(%d).\n", rval); | |
4710 | ha->flags.fce_enabled = 0; | |
4711 | } | |
4712 | } | |
436a7b11 AV |
4713 | |
4714 | if (ha->eft) { | |
4715 | memset(ha->eft, 0, EFT_SIZE); | |
e315cd28 | 4716 | rval = qla2x00_enable_eft_trace(vha, |
436a7b11 AV |
4717 | ha->eft_dma, EFT_NUM_BUFFERS); |
4718 | if (rval) { | |
7c3df132 | 4719 | ql_log(ql_log_warn, vha, 0x8034, |
436a7b11 AV |
4720 | "Unable to reinitialize EFT " |
4721 | "(%d).\n", rval); | |
4722 | } | |
4723 | } | |
1da177e4 | 4724 | } else { /* failed the ISP abort */ |
e315cd28 AC |
4725 | vha->flags.online = 1; |
4726 | if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { | |
1da177e4 | 4727 | if (ha->isp_abort_cnt == 0) { |
7c3df132 SK |
4728 | ql_log(ql_log_fatal, vha, 0x8035, |
4729 | "ISP error recover failed - " | |
4730 | "board disabled.\n"); | |
fa2a1ce5 | 4731 | /* |
1da177e4 LT |
4732 | * The next call disables the board |
4733 | * completely. | |
4734 | */ | |
e315cd28 AC |
4735 | ha->isp_ops->reset_adapter(vha); |
4736 | vha->flags.online = 0; | |
1da177e4 | 4737 | clear_bit(ISP_ABORT_RETRY, |
e315cd28 | 4738 | &vha->dpc_flags); |
1da177e4 LT |
4739 | status = 0; |
4740 | } else { /* schedule another ISP abort */ | |
4741 | ha->isp_abort_cnt--; | |
7c3df132 SK |
4742 | ql_dbg(ql_dbg_taskm, vha, 0x8020, |
4743 | "ISP abort - retry remaining %d.\n", | |
4744 | ha->isp_abort_cnt); | |
1da177e4 LT |
4745 | status = 1; |
4746 | } | |
4747 | } else { | |
4748 | ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; | |
7c3df132 SK |
4749 | ql_dbg(ql_dbg_taskm, vha, 0x8021, |
4750 | "ISP error recovery - retrying (%d) " | |
4751 | "more times.\n", ha->isp_abort_cnt); | |
e315cd28 | 4752 | set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); |
1da177e4 LT |
4753 | status = 1; |
4754 | } | |
4755 | } | |
fa2a1ce5 | 4756 | |
1da177e4 LT |
4757 | } |
4758 | ||
e315cd28 | 4759 | if (!status) { |
7c3df132 | 4760 | ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__); |
feafb7b1 AE |
4761 | |
4762 | spin_lock_irqsave(&ha->vport_slock, flags); | |
4763 | list_for_each_entry(vp, &ha->vp_list, list) { | |
4764 | if (vp->vp_idx) { | |
4765 | atomic_inc(&vp->vref_count); | |
4766 | spin_unlock_irqrestore(&ha->vport_slock, flags); | |
4767 | ||
e315cd28 | 4768 | qla2x00_vp_abort_isp(vp); |
feafb7b1 AE |
4769 | |
4770 | spin_lock_irqsave(&ha->vport_slock, flags); | |
4771 | atomic_dec(&vp->vref_count); | |
4772 | } | |
e315cd28 | 4773 | } |
feafb7b1 AE |
4774 | spin_unlock_irqrestore(&ha->vport_slock, flags); |
4775 | ||
7d613ac6 SV |
4776 | if (IS_QLA8031(ha)) { |
4777 | ql_dbg(ql_dbg_p3p, vha, 0xb05d, | |
4778 | "Setting back fcoe driver presence.\n"); | |
4779 | if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS) | |
4780 | ql_dbg(ql_dbg_p3p, vha, 0xb074, | |
4781 | "Error while setting DRV-Presence.\n"); | |
4782 | } | |
e315cd28 | 4783 | } else { |
d8424f68 JP |
4784 | ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n", |
4785 | __func__); | |
1da177e4 LT |
4786 | } |
4787 | ||
4788 | return(status); | |
4789 | } | |
4790 | ||
4791 | /* | |
4792 | * qla2x00_restart_isp | |
4793 | * restarts the ISP after a reset | |
4794 | * | |
4795 | * Input: | |
4796 | * ha = adapter block pointer. | |
4797 | * | |
4798 | * Returns: | |
4799 | * 0 = success | |
4800 | */ | |
4801 | static int | |
e315cd28 | 4802 | qla2x00_restart_isp(scsi_qla_host_t *vha) |
1da177e4 | 4803 | { |
c6b2fca8 | 4804 | int status = 0; |
e315cd28 | 4805 | struct qla_hw_data *ha = vha->hw; |
73208dfd AC |
4806 | struct req_que *req = ha->req_q_map[0]; |
4807 | struct rsp_que *rsp = ha->rsp_q_map[0]; | |
2d70c103 | 4808 | unsigned long flags; |
1da177e4 LT |
4809 | |
4810 | /* If firmware needs to be loaded */ | |
e315cd28 AC |
4811 | if (qla2x00_isp_firmware(vha)) { |
4812 | vha->flags.online = 0; | |
4813 | status = ha->isp_ops->chip_diag(vha); | |
4814 | if (!status) | |
4815 | status = qla2x00_setup_chip(vha); | |
1da177e4 LT |
4816 | } |
4817 | ||
e315cd28 AC |
4818 | if (!status && !(status = qla2x00_init_rings(vha))) { |
4819 | clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); | |
2533cf67 | 4820 | ha->flags.chip_reset_done = 1; |
7108b76e | 4821 | |
73208dfd AC |
4822 | /* Initialize the queues in use */ |
4823 | qla25xx_init_queues(ha); | |
4824 | ||
e315cd28 AC |
4825 | status = qla2x00_fw_ready(vha); |
4826 | if (!status) { | |
0107109e | 4827 | /* Issue a marker after FW becomes ready. */ |
73208dfd | 4828 | qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL); |
0107109e | 4829 | |
e315cd28 | 4830 | vha->flags.online = 1; |
2d70c103 NB |
4831 | |
4832 | /* | |
4833 | * Process any ATIO queue entries that came in | |
4834 | * while we weren't online. | |
4835 | */ | |
4836 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
4837 | if (qla_tgt_mode_enabled(vha)) | |
4838 | qlt_24xx_process_atio_queue(vha); | |
4839 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
4840 | ||
7108b76e | 4841 | set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); |
1da177e4 LT |
4842 | } |
4843 | ||
4844 | /* if no cable then assume it's good */ | |
e315cd28 | 4845 | if ((vha->device_flags & DFLG_NO_CABLE)) |
1da177e4 | 4846 | status = 0; |
1da177e4 LT |
4847 | } |
4848 | return (status); | |
4849 | } | |
4850 | ||
73208dfd AC |
4851 | static int |
4852 | qla25xx_init_queues(struct qla_hw_data *ha) | |
4853 | { | |
4854 | struct rsp_que *rsp = NULL; | |
4855 | struct req_que *req = NULL; | |
4856 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); | |
4857 | int ret = -1; | |
4858 | int i; | |
4859 | ||
2afa19a9 | 4860 | for (i = 1; i < ha->max_rsp_queues; i++) { |
73208dfd AC |
4861 | rsp = ha->rsp_q_map[i]; |
4862 | if (rsp) { | |
4863 | rsp->options &= ~BIT_0; | |
618a7523 | 4864 | ret = qla25xx_init_rsp_que(base_vha, rsp); |
73208dfd | 4865 | if (ret != QLA_SUCCESS) |
7c3df132 SK |
4866 | ql_dbg(ql_dbg_init, base_vha, 0x00ff, |
4867 | "%s Rsp que: %d init failed.\n", | |
4868 | __func__, rsp->id); | |
73208dfd | 4869 | else |
7c3df132 SK |
4870 | ql_dbg(ql_dbg_init, base_vha, 0x0100, |
4871 | "%s Rsp que: %d inited.\n", | |
4872 | __func__, rsp->id); | |
73208dfd | 4873 | } |
2afa19a9 AC |
4874 | } |
4875 | for (i = 1; i < ha->max_req_queues; i++) { | |
73208dfd AC |
4876 | req = ha->req_q_map[i]; |
4877 | if (req) { | |
29bdccbe | 4878 | /* Clear outstanding commands array. */ |
73208dfd | 4879 | req->options &= ~BIT_0; |
618a7523 | 4880 | ret = qla25xx_init_req_que(base_vha, req); |
73208dfd | 4881 | if (ret != QLA_SUCCESS) |
7c3df132 SK |
4882 | ql_dbg(ql_dbg_init, base_vha, 0x0101, |
4883 | "%s Req que: %d init failed.\n", | |
4884 | __func__, req->id); | |
73208dfd | 4885 | else |
7c3df132 SK |
4886 | ql_dbg(ql_dbg_init, base_vha, 0x0102, |
4887 | "%s Req que: %d inited.\n", | |
4888 | __func__, req->id); | |
73208dfd AC |
4889 | } |
4890 | } | |
4891 | return ret; | |
4892 | } | |
4893 | ||
1da177e4 LT |
4894 | /* |
4895 | * qla2x00_reset_adapter | |
4896 | * Reset adapter. | |
4897 | * | |
4898 | * Input: | |
4899 | * ha = adapter block pointer. | |
4900 | */ | |
abbd8870 | 4901 | void |
e315cd28 | 4902 | qla2x00_reset_adapter(scsi_qla_host_t *vha) |
1da177e4 LT |
4903 | { |
4904 | unsigned long flags = 0; | |
e315cd28 | 4905 | struct qla_hw_data *ha = vha->hw; |
3d71644c | 4906 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 | 4907 | |
e315cd28 | 4908 | vha->flags.online = 0; |
fd34f556 | 4909 | ha->isp_ops->disable_intrs(ha); |
1da177e4 | 4910 | |
1da177e4 LT |
4911 | spin_lock_irqsave(&ha->hardware_lock, flags); |
4912 | WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); | |
4913 | RD_REG_WORD(®->hccr); /* PCI Posting. */ | |
4914 | WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); | |
4915 | RD_REG_WORD(®->hccr); /* PCI Posting. */ | |
4916 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
4917 | } | |
0107109e AV |
4918 | |
4919 | void | |
e315cd28 | 4920 | qla24xx_reset_adapter(scsi_qla_host_t *vha) |
0107109e AV |
4921 | { |
4922 | unsigned long flags = 0; | |
e315cd28 | 4923 | struct qla_hw_data *ha = vha->hw; |
0107109e AV |
4924 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
4925 | ||
7ec0effd | 4926 | if (IS_P3P_TYPE(ha)) |
a9083016 GM |
4927 | return; |
4928 | ||
e315cd28 | 4929 | vha->flags.online = 0; |
fd34f556 | 4930 | ha->isp_ops->disable_intrs(ha); |
0107109e AV |
4931 | |
4932 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
4933 | WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET); | |
4934 | RD_REG_DWORD(®->hccr); | |
4935 | WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE); | |
4936 | RD_REG_DWORD(®->hccr); | |
4937 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
09ff36d3 AV |
4938 | |
4939 | if (IS_NOPOLLING_TYPE(ha)) | |
4940 | ha->isp_ops->enable_intrs(ha); | |
0107109e AV |
4941 | } |
4942 | ||
4e08df3f DM |
4943 | /* On sparc systems, obtain port and node WWN from firmware |
4944 | * properties. | |
4945 | */ | |
e315cd28 AC |
4946 | static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, |
4947 | struct nvram_24xx *nv) | |
4e08df3f DM |
4948 | { |
4949 | #ifdef CONFIG_SPARC | |
e315cd28 | 4950 | struct qla_hw_data *ha = vha->hw; |
4e08df3f | 4951 | struct pci_dev *pdev = ha->pdev; |
15576bc8 DM |
4952 | struct device_node *dp = pci_device_to_OF_node(pdev); |
4953 | const u8 *val; | |
4e08df3f DM |
4954 | int len; |
4955 | ||
4956 | val = of_get_property(dp, "port-wwn", &len); | |
4957 | if (val && len >= WWN_SIZE) | |
4958 | memcpy(nv->port_name, val, WWN_SIZE); | |
4959 | ||
4960 | val = of_get_property(dp, "node-wwn", &len); | |
4961 | if (val && len >= WWN_SIZE) | |
4962 | memcpy(nv->node_name, val, WWN_SIZE); | |
4963 | #endif | |
4964 | } | |
4965 | ||
0107109e | 4966 | int |
e315cd28 | 4967 | qla24xx_nvram_config(scsi_qla_host_t *vha) |
0107109e | 4968 | { |
4e08df3f | 4969 | int rval; |
0107109e AV |
4970 | struct init_cb_24xx *icb; |
4971 | struct nvram_24xx *nv; | |
4972 | uint32_t *dptr; | |
4973 | uint8_t *dptr1, *dptr2; | |
4974 | uint32_t chksum; | |
4975 | uint16_t cnt; | |
e315cd28 | 4976 | struct qla_hw_data *ha = vha->hw; |
0107109e | 4977 | |
4e08df3f | 4978 | rval = QLA_SUCCESS; |
0107109e | 4979 | icb = (struct init_cb_24xx *)ha->init_cb; |
281afe19 | 4980 | nv = ha->nvram; |
0107109e AV |
4981 | |
4982 | /* Determine NVRAM starting address. */ | |
f73cb695 | 4983 | if (ha->port_no == 0) { |
e5b68a61 AC |
4984 | ha->nvram_base = FA_NVRAM_FUNC0_ADDR; |
4985 | ha->vpd_base = FA_NVRAM_VPD0_ADDR; | |
4986 | } else { | |
0107109e | 4987 | ha->nvram_base = FA_NVRAM_FUNC1_ADDR; |
6f641790 | 4988 | ha->vpd_base = FA_NVRAM_VPD1_ADDR; |
4989 | } | |
f73cb695 | 4990 | |
e5b68a61 AC |
4991 | ha->nvram_size = sizeof(struct nvram_24xx); |
4992 | ha->vpd_size = FA_NVRAM_VPD_SIZE; | |
0107109e | 4993 | |
281afe19 SJ |
4994 | /* Get VPD data into cache */ |
4995 | ha->vpd = ha->nvram + VPD_OFFSET; | |
e315cd28 | 4996 | ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd, |
281afe19 SJ |
4997 | ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4); |
4998 | ||
4999 | /* Get NVRAM data into cache and calculate checksum. */ | |
0107109e | 5000 | dptr = (uint32_t *)nv; |
e315cd28 | 5001 | ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base, |
0107109e AV |
5002 | ha->nvram_size); |
5003 | for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++) | |
5004 | chksum += le32_to_cpu(*dptr++); | |
5005 | ||
7c3df132 SK |
5006 | ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a, |
5007 | "Contents of NVRAM\n"); | |
5008 | ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d, | |
5009 | (uint8_t *)nv, ha->nvram_size); | |
0107109e AV |
5010 | |
5011 | /* Bad NVRAM data, set defaults parameters. */ | |
5012 | if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P' | |
5013 | || nv->id[3] != ' ' || | |
5014 | nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) { | |
5015 | /* Reset NVRAM data. */ | |
7c3df132 | 5016 | ql_log(ql_log_warn, vha, 0x006b, |
9e336520 | 5017 | "Inconsistent NVRAM detected: checksum=0x%x id=%c " |
7c3df132 SK |
5018 | "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version); |
5019 | ql_log(ql_log_warn, vha, 0x006c, | |
5020 | "Falling back to functioning (yet invalid -- WWPN) " | |
5021 | "defaults.\n"); | |
4e08df3f DM |
5022 | |
5023 | /* | |
5024 | * Set default initialization control block. | |
5025 | */ | |
5026 | memset(nv, 0, ha->nvram_size); | |
5027 | nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION); | |
5028 | nv->version = __constant_cpu_to_le16(ICB_VERSION); | |
98aee70d | 5029 | nv->frame_payload_size = 2048; |
4e08df3f DM |
5030 | nv->execution_throttle = __constant_cpu_to_le16(0xFFFF); |
5031 | nv->exchange_count = __constant_cpu_to_le16(0); | |
5032 | nv->hard_address = __constant_cpu_to_le16(124); | |
5033 | nv->port_name[0] = 0x21; | |
f73cb695 | 5034 | nv->port_name[1] = 0x00 + ha->port_no + 1; |
4e08df3f DM |
5035 | nv->port_name[2] = 0x00; |
5036 | nv->port_name[3] = 0xe0; | |
5037 | nv->port_name[4] = 0x8b; | |
5038 | nv->port_name[5] = 0x1c; | |
5039 | nv->port_name[6] = 0x55; | |
5040 | nv->port_name[7] = 0x86; | |
5041 | nv->node_name[0] = 0x20; | |
5042 | nv->node_name[1] = 0x00; | |
5043 | nv->node_name[2] = 0x00; | |
5044 | nv->node_name[3] = 0xe0; | |
5045 | nv->node_name[4] = 0x8b; | |
5046 | nv->node_name[5] = 0x1c; | |
5047 | nv->node_name[6] = 0x55; | |
5048 | nv->node_name[7] = 0x86; | |
e315cd28 | 5049 | qla24xx_nvram_wwn_from_ofw(vha, nv); |
4e08df3f DM |
5050 | nv->login_retry_count = __constant_cpu_to_le16(8); |
5051 | nv->interrupt_delay_timer = __constant_cpu_to_le16(0); | |
5052 | nv->login_timeout = __constant_cpu_to_le16(0); | |
5053 | nv->firmware_options_1 = | |
5054 | __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1); | |
5055 | nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4); | |
5056 | nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12); | |
5057 | nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13); | |
5058 | nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10); | |
5059 | nv->efi_parameters = __constant_cpu_to_le32(0); | |
5060 | nv->reset_delay = 5; | |
5061 | nv->max_luns_per_target = __constant_cpu_to_le16(128); | |
5062 | nv->port_down_retry_count = __constant_cpu_to_le16(30); | |
5063 | nv->link_down_timeout = __constant_cpu_to_le16(30); | |
5064 | ||
5065 | rval = 1; | |
0107109e AV |
5066 | } |
5067 | ||
2d70c103 NB |
5068 | if (!qla_ini_mode_enabled(vha)) { |
5069 | /* Don't enable full login after initial LIP */ | |
5070 | nv->firmware_options_1 &= __constant_cpu_to_le32(~BIT_13); | |
5071 | /* Don't enable LIP full login for initiator */ | |
5072 | nv->host_p &= __constant_cpu_to_le32(~BIT_10); | |
5073 | } | |
5074 | ||
5075 | qlt_24xx_config_nvram_stage1(vha, nv); | |
5076 | ||
0107109e | 5077 | /* Reset Initialization control block */ |
e315cd28 | 5078 | memset(icb, 0, ha->init_cb_size); |
0107109e AV |
5079 | |
5080 | /* Copy 1st segment. */ | |
5081 | dptr1 = (uint8_t *)icb; | |
5082 | dptr2 = (uint8_t *)&nv->version; | |
5083 | cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version; | |
5084 | while (cnt--) | |
5085 | *dptr1++ = *dptr2++; | |
5086 | ||
5087 | icb->login_retry_count = nv->login_retry_count; | |
3ea66e28 | 5088 | icb->link_down_on_nos = nv->link_down_on_nos; |
0107109e AV |
5089 | |
5090 | /* Copy 2nd segment. */ | |
5091 | dptr1 = (uint8_t *)&icb->interrupt_delay_timer; | |
5092 | dptr2 = (uint8_t *)&nv->interrupt_delay_timer; | |
5093 | cnt = (uint8_t *)&icb->reserved_3 - | |
5094 | (uint8_t *)&icb->interrupt_delay_timer; | |
5095 | while (cnt--) | |
5096 | *dptr1++ = *dptr2++; | |
5097 | ||
5098 | /* | |
5099 | * Setup driver NVRAM options. | |
5100 | */ | |
e315cd28 | 5101 | qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name), |
9bb9fcf2 | 5102 | "QLA2462"); |
0107109e | 5103 | |
2d70c103 NB |
5104 | qlt_24xx_config_nvram_stage2(vha, icb); |
5105 | ||
5341e868 | 5106 | if (nv->host_p & __constant_cpu_to_le32(BIT_15)) { |
2d70c103 | 5107 | /* Use alternate WWN? */ |
5341e868 AV |
5108 | memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE); |
5109 | memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE); | |
5110 | } | |
5111 | ||
0107109e | 5112 | /* Prepare nodename */ |
fd0e7e4d | 5113 | if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) { |
0107109e AV |
5114 | /* |
5115 | * Firmware will apply the following mask if the nodename was | |
5116 | * not provided. | |
5117 | */ | |
5118 | memcpy(icb->node_name, icb->port_name, WWN_SIZE); | |
5119 | icb->node_name[0] &= 0xF0; | |
5120 | } | |
5121 | ||
5122 | /* Set host adapter parameters. */ | |
5123 | ha->flags.disable_risc_code_load = 0; | |
0c8c39af AV |
5124 | ha->flags.enable_lip_reset = 0; |
5125 | ha->flags.enable_lip_full_login = | |
5126 | le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0; | |
5127 | ha->flags.enable_target_reset = | |
5128 | le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0; | |
0107109e | 5129 | ha->flags.enable_led_scheme = 0; |
d4c760c2 | 5130 | ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0; |
0107109e | 5131 | |
fd0e7e4d AV |
5132 | ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) & |
5133 | (BIT_6 | BIT_5 | BIT_4)) >> 4; | |
0107109e AV |
5134 | |
5135 | memcpy(ha->fw_seriallink_options24, nv->seriallink_options, | |
5136 | sizeof(ha->fw_seriallink_options24)); | |
5137 | ||
5138 | /* save HBA serial number */ | |
5139 | ha->serial0 = icb->port_name[5]; | |
5140 | ha->serial1 = icb->port_name[6]; | |
5141 | ha->serial2 = icb->port_name[7]; | |
e315cd28 AC |
5142 | memcpy(vha->node_name, icb->node_name, WWN_SIZE); |
5143 | memcpy(vha->port_name, icb->port_name, WWN_SIZE); | |
0107109e | 5144 | |
bc8fb3cb | 5145 | icb->execution_throttle = __constant_cpu_to_le16(0xFFFF); |
5146 | ||
0107109e AV |
5147 | ha->retry_count = le16_to_cpu(nv->login_retry_count); |
5148 | ||
5149 | /* Set minimum login_timeout to 4 seconds. */ | |
5150 | if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout) | |
5151 | nv->login_timeout = cpu_to_le16(ql2xlogintimeout); | |
5152 | if (le16_to_cpu(nv->login_timeout) < 4) | |
5153 | nv->login_timeout = __constant_cpu_to_le16(4); | |
5154 | ha->login_timeout = le16_to_cpu(nv->login_timeout); | |
c6852c4c | 5155 | icb->login_timeout = nv->login_timeout; |
0107109e | 5156 | |
00a537b8 AV |
5157 | /* Set minimum RATOV to 100 tenths of a second. */ |
5158 | ha->r_a_tov = 100; | |
0107109e AV |
5159 | |
5160 | ha->loop_reset_delay = nv->reset_delay; | |
5161 | ||
5162 | /* Link Down Timeout = 0: | |
5163 | * | |
5164 | * When Port Down timer expires we will start returning | |
5165 | * I/O's to OS with "DID_NO_CONNECT". | |
5166 | * | |
5167 | * Link Down Timeout != 0: | |
5168 | * | |
5169 | * The driver waits for the link to come up after link down | |
5170 | * before returning I/Os to OS with "DID_NO_CONNECT". | |
5171 | */ | |
5172 | if (le16_to_cpu(nv->link_down_timeout) == 0) { | |
5173 | ha->loop_down_abort_time = | |
5174 | (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT); | |
5175 | } else { | |
5176 | ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout); | |
5177 | ha->loop_down_abort_time = | |
5178 | (LOOP_DOWN_TIME - ha->link_down_timeout); | |
5179 | } | |
5180 | ||
5181 | /* Need enough time to try and get the port back. */ | |
5182 | ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count); | |
5183 | if (qlport_down_retry) | |
5184 | ha->port_down_retry_count = qlport_down_retry; | |
5185 | ||
5186 | /* Set login_retry_count */ | |
5187 | ha->login_retry_count = le16_to_cpu(nv->login_retry_count); | |
5188 | if (ha->port_down_retry_count == | |
5189 | le16_to_cpu(nv->port_down_retry_count) && | |
5190 | ha->port_down_retry_count > 3) | |
5191 | ha->login_retry_count = ha->port_down_retry_count; | |
5192 | else if (ha->port_down_retry_count > (int)ha->login_retry_count) | |
5193 | ha->login_retry_count = ha->port_down_retry_count; | |
5194 | if (ql2xloginretrycount) | |
5195 | ha->login_retry_count = ql2xloginretrycount; | |
5196 | ||
4fdfefe5 | 5197 | /* Enable ZIO. */ |
e315cd28 | 5198 | if (!vha->flags.init_done) { |
4fdfefe5 AV |
5199 | ha->zio_mode = le32_to_cpu(icb->firmware_options_2) & |
5200 | (BIT_3 | BIT_2 | BIT_1 | BIT_0); | |
5201 | ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ? | |
5202 | le16_to_cpu(icb->interrupt_delay_timer): 2; | |
5203 | } | |
5204 | icb->firmware_options_2 &= __constant_cpu_to_le32( | |
5205 | ~(BIT_3 | BIT_2 | BIT_1 | BIT_0)); | |
e315cd28 | 5206 | vha->flags.process_response_queue = 0; |
4fdfefe5 | 5207 | if (ha->zio_mode != QLA_ZIO_DISABLED) { |
4a59f71d | 5208 | ha->zio_mode = QLA_ZIO_MODE_6; |
5209 | ||
7c3df132 | 5210 | ql_log(ql_log_info, vha, 0x006f, |
4fdfefe5 AV |
5211 | "ZIO mode %d enabled; timer delay (%d us).\n", |
5212 | ha->zio_mode, ha->zio_timer * 100); | |
5213 | ||
5214 | icb->firmware_options_2 |= cpu_to_le32( | |
5215 | (uint32_t)ha->zio_mode); | |
5216 | icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer); | |
e315cd28 | 5217 | vha->flags.process_response_queue = 1; |
4fdfefe5 AV |
5218 | } |
5219 | ||
4e08df3f | 5220 | if (rval) { |
7c3df132 SK |
5221 | ql_log(ql_log_warn, vha, 0x0070, |
5222 | "NVRAM configuration failed.\n"); | |
4e08df3f DM |
5223 | } |
5224 | return (rval); | |
0107109e AV |
5225 | } |
5226 | ||
413975a0 | 5227 | static int |
cbc8eb67 AV |
5228 | qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr, |
5229 | uint32_t faddr) | |
d1c61909 | 5230 | { |
73208dfd | 5231 | int rval = QLA_SUCCESS; |
d1c61909 | 5232 | int segments, fragment; |
d1c61909 AV |
5233 | uint32_t *dcode, dlen; |
5234 | uint32_t risc_addr; | |
5235 | uint32_t risc_size; | |
5236 | uint32_t i; | |
e315cd28 | 5237 | struct qla_hw_data *ha = vha->hw; |
73208dfd | 5238 | struct req_que *req = ha->req_q_map[0]; |
eaac30be | 5239 | |
7c3df132 | 5240 | ql_dbg(ql_dbg_init, vha, 0x008b, |
cfb0919c | 5241 | "FW: Loading firmware from flash (%x).\n", faddr); |
eaac30be | 5242 | |
d1c61909 AV |
5243 | rval = QLA_SUCCESS; |
5244 | ||
5245 | segments = FA_RISC_CODE_SEGMENTS; | |
73208dfd | 5246 | dcode = (uint32_t *)req->ring; |
d1c61909 AV |
5247 | *srisc_addr = 0; |
5248 | ||
5249 | /* Validate firmware image by checking version. */ | |
e315cd28 | 5250 | qla24xx_read_flash_data(vha, dcode, faddr + 4, 4); |
d1c61909 AV |
5251 | for (i = 0; i < 4; i++) |
5252 | dcode[i] = be32_to_cpu(dcode[i]); | |
5253 | if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff && | |
5254 | dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) || | |
5255 | (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && | |
5256 | dcode[3] == 0)) { | |
7c3df132 SK |
5257 | ql_log(ql_log_fatal, vha, 0x008c, |
5258 | "Unable to verify the integrity of flash firmware " | |
5259 | "image.\n"); | |
5260 | ql_log(ql_log_fatal, vha, 0x008d, | |
5261 | "Firmware data: %08x %08x %08x %08x.\n", | |
5262 | dcode[0], dcode[1], dcode[2], dcode[3]); | |
d1c61909 AV |
5263 | |
5264 | return QLA_FUNCTION_FAILED; | |
5265 | } | |
5266 | ||
5267 | while (segments && rval == QLA_SUCCESS) { | |
5268 | /* Read segment's load information. */ | |
e315cd28 | 5269 | qla24xx_read_flash_data(vha, dcode, faddr, 4); |
d1c61909 AV |
5270 | |
5271 | risc_addr = be32_to_cpu(dcode[2]); | |
5272 | *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr; | |
5273 | risc_size = be32_to_cpu(dcode[3]); | |
5274 | ||
5275 | fragment = 0; | |
5276 | while (risc_size > 0 && rval == QLA_SUCCESS) { | |
5277 | dlen = (uint32_t)(ha->fw_transfer_size >> 2); | |
5278 | if (dlen > risc_size) | |
5279 | dlen = risc_size; | |
5280 | ||
7c3df132 SK |
5281 | ql_dbg(ql_dbg_init, vha, 0x008e, |
5282 | "Loading risc segment@ risc addr %x " | |
5283 | "number of dwords 0x%x offset 0x%x.\n", | |
5284 | risc_addr, dlen, faddr); | |
d1c61909 | 5285 | |
e315cd28 | 5286 | qla24xx_read_flash_data(vha, dcode, faddr, dlen); |
d1c61909 AV |
5287 | for (i = 0; i < dlen; i++) |
5288 | dcode[i] = swab32(dcode[i]); | |
5289 | ||
73208dfd | 5290 | rval = qla2x00_load_ram(vha, req->dma, risc_addr, |
d1c61909 AV |
5291 | dlen); |
5292 | if (rval) { | |
7c3df132 SK |
5293 | ql_log(ql_log_fatal, vha, 0x008f, |
5294 | "Failed to load segment %d of firmware.\n", | |
5295 | fragment); | |
f261f7af | 5296 | return QLA_FUNCTION_FAILED; |
d1c61909 AV |
5297 | } |
5298 | ||
5299 | faddr += dlen; | |
5300 | risc_addr += dlen; | |
5301 | risc_size -= dlen; | |
5302 | fragment++; | |
5303 | } | |
5304 | ||
5305 | /* Next segment. */ | |
5306 | segments--; | |
5307 | } | |
5308 | ||
f73cb695 CD |
5309 | if (!IS_QLA27XX(ha)) |
5310 | return rval; | |
5311 | ||
5312 | if (ha->fw_dump_template) | |
5313 | vfree(ha->fw_dump_template); | |
5314 | ha->fw_dump_template = NULL; | |
5315 | ha->fw_dump_template_len = 0; | |
5316 | ||
5317 | ql_dbg(ql_dbg_init, vha, 0x0161, | |
5318 | "Loading fwdump template from %x\n", faddr); | |
5319 | qla24xx_read_flash_data(vha, dcode, faddr, 7); | |
5320 | risc_size = be32_to_cpu(dcode[2]); | |
5321 | ql_dbg(ql_dbg_init, vha, 0x0162, | |
5322 | "-> array size %x dwords\n", risc_size); | |
5323 | if (risc_size == 0 || risc_size == ~0) | |
5324 | goto default_template; | |
5325 | ||
5326 | dlen = (risc_size - 8) * sizeof(*dcode); | |
5327 | ql_dbg(ql_dbg_init, vha, 0x0163, | |
5328 | "-> template allocating %x bytes...\n", dlen); | |
5329 | ha->fw_dump_template = vmalloc(dlen); | |
5330 | if (!ha->fw_dump_template) { | |
5331 | ql_log(ql_log_warn, vha, 0x0164, | |
5332 | "Failed fwdump template allocate %x bytes.\n", risc_size); | |
5333 | goto default_template; | |
5334 | } | |
5335 | ||
5336 | faddr += 7; | |
5337 | risc_size -= 8; | |
5338 | dcode = ha->fw_dump_template; | |
5339 | qla24xx_read_flash_data(vha, dcode, faddr, risc_size); | |
5340 | for (i = 0; i < risc_size; i++) | |
5341 | dcode[i] = le32_to_cpu(dcode[i]); | |
5342 | ||
5343 | if (!qla27xx_fwdt_template_valid(dcode)) { | |
5344 | ql_log(ql_log_warn, vha, 0x0165, | |
5345 | "Failed fwdump template validate\n"); | |
5346 | goto default_template; | |
5347 | } | |
5348 | ||
5349 | dlen = qla27xx_fwdt_template_size(dcode); | |
5350 | ql_dbg(ql_dbg_init, vha, 0x0166, | |
5351 | "-> template size %x bytes\n", dlen); | |
5352 | if (dlen > risc_size * sizeof(*dcode)) { | |
5353 | ql_log(ql_log_warn, vha, 0x0167, | |
97ea702b CD |
5354 | "Failed fwdump template exceeds array by %x bytes\n", |
5355 | (uint32_t)(dlen - risc_size * sizeof(*dcode))); | |
f73cb695 CD |
5356 | goto default_template; |
5357 | } | |
5358 | ha->fw_dump_template_len = dlen; | |
5359 | return rval; | |
5360 | ||
5361 | default_template: | |
5362 | ql_log(ql_log_warn, vha, 0x0168, "Using default fwdump template\n"); | |
5363 | if (ha->fw_dump_template) | |
5364 | vfree(ha->fw_dump_template); | |
5365 | ha->fw_dump_template = NULL; | |
5366 | ha->fw_dump_template_len = 0; | |
5367 | ||
5368 | dlen = qla27xx_fwdt_template_default_size(); | |
5369 | ql_dbg(ql_dbg_init, vha, 0x0169, | |
5370 | "-> template allocating %x bytes...\n", dlen); | |
5371 | ha->fw_dump_template = vmalloc(dlen); | |
5372 | if (!ha->fw_dump_template) { | |
5373 | ql_log(ql_log_warn, vha, 0x016a, | |
5374 | "Failed fwdump template allocate %x bytes.\n", risc_size); | |
5375 | goto failed_template; | |
5376 | } | |
5377 | ||
5378 | dcode = ha->fw_dump_template; | |
5379 | risc_size = dlen / sizeof(*dcode); | |
5380 | memcpy(dcode, qla27xx_fwdt_template_default(), dlen); | |
5381 | for (i = 0; i < risc_size; i++) | |
5382 | dcode[i] = be32_to_cpu(dcode[i]); | |
5383 | ||
5384 | if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) { | |
5385 | ql_log(ql_log_warn, vha, 0x016b, | |
5386 | "Failed fwdump template validate\n"); | |
5387 | goto failed_template; | |
5388 | } | |
5389 | ||
5390 | dlen = qla27xx_fwdt_template_size(ha->fw_dump_template); | |
5391 | ql_dbg(ql_dbg_init, vha, 0x016c, | |
5392 | "-> template size %x bytes\n", dlen); | |
5393 | ha->fw_dump_template_len = dlen; | |
5394 | return rval; | |
5395 | ||
5396 | failed_template: | |
5397 | ql_log(ql_log_warn, vha, 0x016d, "Failed default fwdump template\n"); | |
5398 | if (ha->fw_dump_template) | |
5399 | vfree(ha->fw_dump_template); | |
5400 | ha->fw_dump_template = NULL; | |
5401 | ha->fw_dump_template_len = 0; | |
d1c61909 AV |
5402 | return rval; |
5403 | } | |
5404 | ||
e9454a88 | 5405 | #define QLA_FW_URL "http://ldriver.qlogic.com/firmware/" |
d1c61909 | 5406 | |
0107109e | 5407 | int |
e315cd28 | 5408 | qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) |
5433383e AV |
5409 | { |
5410 | int rval; | |
5411 | int i, fragment; | |
5412 | uint16_t *wcode, *fwcode; | |
5413 | uint32_t risc_addr, risc_size, fwclen, wlen, *seg; | |
5414 | struct fw_blob *blob; | |
e315cd28 | 5415 | struct qla_hw_data *ha = vha->hw; |
73208dfd | 5416 | struct req_que *req = ha->req_q_map[0]; |
5433383e AV |
5417 | |
5418 | /* Load firmware blob. */ | |
e315cd28 | 5419 | blob = qla2x00_request_firmware(vha); |
5433383e | 5420 | if (!blob) { |
7c3df132 | 5421 | ql_log(ql_log_info, vha, 0x0083, |
94bcf830 | 5422 | "Firmware image unavailable.\n"); |
7c3df132 SK |
5423 | ql_log(ql_log_info, vha, 0x0084, |
5424 | "Firmware images can be retrieved from: "QLA_FW_URL ".\n"); | |
5433383e AV |
5425 | return QLA_FUNCTION_FAILED; |
5426 | } | |
5427 | ||
5428 | rval = QLA_SUCCESS; | |
5429 | ||
73208dfd | 5430 | wcode = (uint16_t *)req->ring; |
5433383e AV |
5431 | *srisc_addr = 0; |
5432 | fwcode = (uint16_t *)blob->fw->data; | |
5433 | fwclen = 0; | |
5434 | ||
5435 | /* Validate firmware image by checking version. */ | |
5436 | if (blob->fw->size < 8 * sizeof(uint16_t)) { | |
7c3df132 SK |
5437 | ql_log(ql_log_fatal, vha, 0x0085, |
5438 | "Unable to verify integrity of firmware image (%Zd).\n", | |
5433383e AV |
5439 | blob->fw->size); |
5440 | goto fail_fw_integrity; | |
5441 | } | |
5442 | for (i = 0; i < 4; i++) | |
5443 | wcode[i] = be16_to_cpu(fwcode[i + 4]); | |
5444 | if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff && | |
5445 | wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 && | |
5446 | wcode[2] == 0 && wcode[3] == 0)) { | |
7c3df132 SK |
5447 | ql_log(ql_log_fatal, vha, 0x0086, |
5448 | "Unable to verify integrity of firmware image.\n"); | |
5449 | ql_log(ql_log_fatal, vha, 0x0087, | |
5450 | "Firmware data: %04x %04x %04x %04x.\n", | |
5451 | wcode[0], wcode[1], wcode[2], wcode[3]); | |
5433383e AV |
5452 | goto fail_fw_integrity; |
5453 | } | |
5454 | ||
5455 | seg = blob->segs; | |
5456 | while (*seg && rval == QLA_SUCCESS) { | |
5457 | risc_addr = *seg; | |
5458 | *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr; | |
5459 | risc_size = be16_to_cpu(fwcode[3]); | |
5460 | ||
5461 | /* Validate firmware image size. */ | |
5462 | fwclen += risc_size * sizeof(uint16_t); | |
5463 | if (blob->fw->size < fwclen) { | |
7c3df132 | 5464 | ql_log(ql_log_fatal, vha, 0x0088, |
5433383e | 5465 | "Unable to verify integrity of firmware image " |
7c3df132 | 5466 | "(%Zd).\n", blob->fw->size); |
5433383e AV |
5467 | goto fail_fw_integrity; |
5468 | } | |
5469 | ||
5470 | fragment = 0; | |
5471 | while (risc_size > 0 && rval == QLA_SUCCESS) { | |
5472 | wlen = (uint16_t)(ha->fw_transfer_size >> 1); | |
5473 | if (wlen > risc_size) | |
5474 | wlen = risc_size; | |
7c3df132 SK |
5475 | ql_dbg(ql_dbg_init, vha, 0x0089, |
5476 | "Loading risc segment@ risc addr %x number of " | |
5477 | "words 0x%x.\n", risc_addr, wlen); | |
5433383e AV |
5478 | |
5479 | for (i = 0; i < wlen; i++) | |
5480 | wcode[i] = swab16(fwcode[i]); | |
5481 | ||
73208dfd | 5482 | rval = qla2x00_load_ram(vha, req->dma, risc_addr, |
5433383e AV |
5483 | wlen); |
5484 | if (rval) { | |
7c3df132 SK |
5485 | ql_log(ql_log_fatal, vha, 0x008a, |
5486 | "Failed to load segment %d of firmware.\n", | |
5487 | fragment); | |
5433383e AV |
5488 | break; |
5489 | } | |
5490 | ||
5491 | fwcode += wlen; | |
5492 | risc_addr += wlen; | |
5493 | risc_size -= wlen; | |
5494 | fragment++; | |
5495 | } | |
5496 | ||
5497 | /* Next segment. */ | |
5498 | seg++; | |
5499 | } | |
5500 | return rval; | |
5501 | ||
5502 | fail_fw_integrity: | |
5503 | return QLA_FUNCTION_FAILED; | |
5504 | } | |
5505 | ||
eaac30be AV |
5506 | static int |
5507 | qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr) | |
0107109e AV |
5508 | { |
5509 | int rval; | |
5510 | int segments, fragment; | |
5511 | uint32_t *dcode, dlen; | |
5512 | uint32_t risc_addr; | |
5513 | uint32_t risc_size; | |
5514 | uint32_t i; | |
5433383e | 5515 | struct fw_blob *blob; |
f73cb695 CD |
5516 | const uint32_t *fwcode; |
5517 | uint32_t fwclen; | |
e315cd28 | 5518 | struct qla_hw_data *ha = vha->hw; |
73208dfd | 5519 | struct req_que *req = ha->req_q_map[0]; |
0107109e | 5520 | |
5433383e | 5521 | /* Load firmware blob. */ |
e315cd28 | 5522 | blob = qla2x00_request_firmware(vha); |
5433383e | 5523 | if (!blob) { |
7c3df132 | 5524 | ql_log(ql_log_warn, vha, 0x0090, |
94bcf830 | 5525 | "Firmware image unavailable.\n"); |
7c3df132 SK |
5526 | ql_log(ql_log_warn, vha, 0x0091, |
5527 | "Firmware images can be retrieved from: " | |
5528 | QLA_FW_URL ".\n"); | |
d1c61909 | 5529 | |
eaac30be | 5530 | return QLA_FUNCTION_FAILED; |
0107109e AV |
5531 | } |
5532 | ||
cfb0919c CD |
5533 | ql_dbg(ql_dbg_init, vha, 0x0092, |
5534 | "FW: Loading via request-firmware.\n"); | |
eaac30be | 5535 | |
0107109e AV |
5536 | rval = QLA_SUCCESS; |
5537 | ||
5538 | segments = FA_RISC_CODE_SEGMENTS; | |
73208dfd | 5539 | dcode = (uint32_t *)req->ring; |
0107109e | 5540 | *srisc_addr = 0; |
5433383e | 5541 | fwcode = (uint32_t *)blob->fw->data; |
0107109e AV |
5542 | fwclen = 0; |
5543 | ||
5544 | /* Validate firmware image by checking version. */ | |
5433383e | 5545 | if (blob->fw->size < 8 * sizeof(uint32_t)) { |
7c3df132 SK |
5546 | ql_log(ql_log_fatal, vha, 0x0093, |
5547 | "Unable to verify integrity of firmware image (%Zd).\n", | |
5433383e | 5548 | blob->fw->size); |
f73cb695 | 5549 | return QLA_FUNCTION_FAILED; |
0107109e AV |
5550 | } |
5551 | for (i = 0; i < 4; i++) | |
5552 | dcode[i] = be32_to_cpu(fwcode[i + 4]); | |
5553 | if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff && | |
5554 | dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) || | |
5555 | (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && | |
5556 | dcode[3] == 0)) { | |
7c3df132 SK |
5557 | ql_log(ql_log_fatal, vha, 0x0094, |
5558 | "Unable to verify integrity of firmware image (%Zd).\n", | |
5559 | blob->fw->size); | |
5560 | ql_log(ql_log_fatal, vha, 0x0095, | |
5561 | "Firmware data: %08x %08x %08x %08x.\n", | |
5562 | dcode[0], dcode[1], dcode[2], dcode[3]); | |
f73cb695 | 5563 | return QLA_FUNCTION_FAILED; |
0107109e AV |
5564 | } |
5565 | ||
5566 | while (segments && rval == QLA_SUCCESS) { | |
5567 | risc_addr = be32_to_cpu(fwcode[2]); | |
5568 | *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr; | |
5569 | risc_size = be32_to_cpu(fwcode[3]); | |
5570 | ||
5571 | /* Validate firmware image size. */ | |
5572 | fwclen += risc_size * sizeof(uint32_t); | |
5433383e | 5573 | if (blob->fw->size < fwclen) { |
7c3df132 | 5574 | ql_log(ql_log_fatal, vha, 0x0096, |
5433383e | 5575 | "Unable to verify integrity of firmware image " |
7c3df132 | 5576 | "(%Zd).\n", blob->fw->size); |
f73cb695 | 5577 | return QLA_FUNCTION_FAILED; |
0107109e AV |
5578 | } |
5579 | ||
5580 | fragment = 0; | |
5581 | while (risc_size > 0 && rval == QLA_SUCCESS) { | |
5582 | dlen = (uint32_t)(ha->fw_transfer_size >> 2); | |
5583 | if (dlen > risc_size) | |
5584 | dlen = risc_size; | |
5585 | ||
7c3df132 SK |
5586 | ql_dbg(ql_dbg_init, vha, 0x0097, |
5587 | "Loading risc segment@ risc addr %x " | |
5588 | "number of dwords 0x%x.\n", risc_addr, dlen); | |
0107109e AV |
5589 | |
5590 | for (i = 0; i < dlen; i++) | |
5591 | dcode[i] = swab32(fwcode[i]); | |
5592 | ||
73208dfd | 5593 | rval = qla2x00_load_ram(vha, req->dma, risc_addr, |
590f98e5 | 5594 | dlen); |
0107109e | 5595 | if (rval) { |
7c3df132 SK |
5596 | ql_log(ql_log_fatal, vha, 0x0098, |
5597 | "Failed to load segment %d of firmware.\n", | |
5598 | fragment); | |
f261f7af | 5599 | return QLA_FUNCTION_FAILED; |
0107109e AV |
5600 | } |
5601 | ||
5602 | fwcode += dlen; | |
5603 | risc_addr += dlen; | |
5604 | risc_size -= dlen; | |
5605 | fragment++; | |
5606 | } | |
5607 | ||
5608 | /* Next segment. */ | |
5609 | segments--; | |
5610 | } | |
f73cb695 CD |
5611 | |
5612 | if (!IS_QLA27XX(ha)) | |
5613 | return rval; | |
5614 | ||
5615 | if (ha->fw_dump_template) | |
5616 | vfree(ha->fw_dump_template); | |
5617 | ha->fw_dump_template = NULL; | |
5618 | ha->fw_dump_template_len = 0; | |
5619 | ||
5620 | ql_dbg(ql_dbg_init, vha, 0x171, | |
97ea702b CD |
5621 | "Loading fwdump template from %x\n", |
5622 | (uint32_t)((void *)fwcode - (void *)blob->fw->data)); | |
f73cb695 CD |
5623 | risc_size = be32_to_cpu(fwcode[2]); |
5624 | ql_dbg(ql_dbg_init, vha, 0x172, | |
5625 | "-> array size %x dwords\n", risc_size); | |
5626 | if (risc_size == 0 || risc_size == ~0) | |
5627 | goto default_template; | |
5628 | ||
5629 | dlen = (risc_size - 8) * sizeof(*fwcode); | |
5630 | ql_dbg(ql_dbg_init, vha, 0x0173, | |
5631 | "-> template allocating %x bytes...\n", dlen); | |
5632 | ha->fw_dump_template = vmalloc(dlen); | |
5633 | if (!ha->fw_dump_template) { | |
5634 | ql_log(ql_log_warn, vha, 0x0174, | |
5635 | "Failed fwdump template allocate %x bytes.\n", risc_size); | |
5636 | goto default_template; | |
5637 | } | |
5638 | ||
5639 | fwcode += 7; | |
5640 | risc_size -= 8; | |
5641 | dcode = ha->fw_dump_template; | |
5642 | for (i = 0; i < risc_size; i++) | |
5643 | dcode[i] = le32_to_cpu(fwcode[i]); | |
5644 | ||
5645 | if (!qla27xx_fwdt_template_valid(dcode)) { | |
5646 | ql_log(ql_log_warn, vha, 0x0175, | |
5647 | "Failed fwdump template validate\n"); | |
5648 | goto default_template; | |
5649 | } | |
5650 | ||
5651 | dlen = qla27xx_fwdt_template_size(dcode); | |
5652 | ql_dbg(ql_dbg_init, vha, 0x0176, | |
5653 | "-> template size %x bytes\n", dlen); | |
5654 | if (dlen > risc_size * sizeof(*fwcode)) { | |
5655 | ql_log(ql_log_warn, vha, 0x0177, | |
97ea702b CD |
5656 | "Failed fwdump template exceeds array by %x bytes\n", |
5657 | (uint32_t)(dlen - risc_size * sizeof(*fwcode))); | |
f73cb695 CD |
5658 | goto default_template; |
5659 | } | |
5660 | ha->fw_dump_template_len = dlen; | |
0107109e AV |
5661 | return rval; |
5662 | ||
f73cb695 CD |
5663 | default_template: |
5664 | ql_log(ql_log_warn, vha, 0x0178, "Using default fwdump template\n"); | |
5665 | if (ha->fw_dump_template) | |
5666 | vfree(ha->fw_dump_template); | |
5667 | ha->fw_dump_template = NULL; | |
5668 | ha->fw_dump_template_len = 0; | |
5669 | ||
5670 | dlen = qla27xx_fwdt_template_default_size(); | |
5671 | ql_dbg(ql_dbg_init, vha, 0x0179, | |
5672 | "-> template allocating %x bytes...\n", dlen); | |
5673 | ha->fw_dump_template = vmalloc(dlen); | |
5674 | if (!ha->fw_dump_template) { | |
5675 | ql_log(ql_log_warn, vha, 0x017a, | |
5676 | "Failed fwdump template allocate %x bytes.\n", risc_size); | |
5677 | goto failed_template; | |
5678 | } | |
5679 | ||
5680 | dcode = ha->fw_dump_template; | |
5681 | risc_size = dlen / sizeof(*fwcode); | |
5682 | fwcode = qla27xx_fwdt_template_default(); | |
5683 | for (i = 0; i < risc_size; i++) | |
5684 | dcode[i] = be32_to_cpu(fwcode[i]); | |
5685 | ||
5686 | if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) { | |
5687 | ql_log(ql_log_warn, vha, 0x017b, | |
5688 | "Failed fwdump template validate\n"); | |
5689 | goto failed_template; | |
5690 | } | |
5691 | ||
5692 | dlen = qla27xx_fwdt_template_size(ha->fw_dump_template); | |
5693 | ql_dbg(ql_dbg_init, vha, 0x017c, | |
5694 | "-> template size %x bytes\n", dlen); | |
5695 | ha->fw_dump_template_len = dlen; | |
5696 | return rval; | |
5697 | ||
5698 | failed_template: | |
5699 | ql_log(ql_log_warn, vha, 0x017d, "Failed default fwdump template\n"); | |
5700 | if (ha->fw_dump_template) | |
5701 | vfree(ha->fw_dump_template); | |
5702 | ha->fw_dump_template = NULL; | |
5703 | ha->fw_dump_template_len = 0; | |
5704 | return rval; | |
0107109e | 5705 | } |
18c6c127 | 5706 | |
eaac30be AV |
5707 | int |
5708 | qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) | |
5709 | { | |
5710 | int rval; | |
5711 | ||
e337d907 AV |
5712 | if (ql2xfwloadbin == 1) |
5713 | return qla81xx_load_risc(vha, srisc_addr); | |
5714 | ||
eaac30be AV |
5715 | /* |
5716 | * FW Load priority: | |
5717 | * 1) Firmware via request-firmware interface (.bin file). | |
5718 | * 2) Firmware residing in flash. | |
5719 | */ | |
5720 | rval = qla24xx_load_risc_blob(vha, srisc_addr); | |
5721 | if (rval == QLA_SUCCESS) | |
5722 | return rval; | |
5723 | ||
cbc8eb67 AV |
5724 | return qla24xx_load_risc_flash(vha, srisc_addr, |
5725 | vha->hw->flt_region_fw); | |
eaac30be AV |
5726 | } |
5727 | ||
5728 | int | |
5729 | qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) | |
5730 | { | |
5731 | int rval; | |
cbc8eb67 | 5732 | struct qla_hw_data *ha = vha->hw; |
eaac30be | 5733 | |
e337d907 | 5734 | if (ql2xfwloadbin == 2) |
cbc8eb67 | 5735 | goto try_blob_fw; |
e337d907 | 5736 | |
eaac30be AV |
5737 | /* |
5738 | * FW Load priority: | |
5739 | * 1) Firmware residing in flash. | |
5740 | * 2) Firmware via request-firmware interface (.bin file). | |
cbc8eb67 | 5741 | * 3) Golden-Firmware residing in flash -- limited operation. |
eaac30be | 5742 | */ |
cbc8eb67 | 5743 | rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw); |
eaac30be AV |
5744 | if (rval == QLA_SUCCESS) |
5745 | return rval; | |
5746 | ||
cbc8eb67 AV |
5747 | try_blob_fw: |
5748 | rval = qla24xx_load_risc_blob(vha, srisc_addr); | |
5749 | if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw) | |
5750 | return rval; | |
5751 | ||
7c3df132 SK |
5752 | ql_log(ql_log_info, vha, 0x0099, |
5753 | "Attempting to fallback to golden firmware.\n"); | |
cbc8eb67 AV |
5754 | rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw); |
5755 | if (rval != QLA_SUCCESS) | |
5756 | return rval; | |
5757 | ||
7c3df132 | 5758 | ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n"); |
cbc8eb67 | 5759 | ha->flags.running_gold_fw = 1; |
cbc8eb67 | 5760 | return rval; |
eaac30be AV |
5761 | } |
5762 | ||
18c6c127 | 5763 | void |
e315cd28 | 5764 | qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha) |
18c6c127 AV |
5765 | { |
5766 | int ret, retries; | |
e315cd28 | 5767 | struct qla_hw_data *ha = vha->hw; |
18c6c127 | 5768 | |
85880801 AV |
5769 | if (ha->flags.pci_channel_io_perm_failure) |
5770 | return; | |
e428924c | 5771 | if (!IS_FWI2_CAPABLE(ha)) |
18c6c127 | 5772 | return; |
75edf81d AV |
5773 | if (!ha->fw_major_version) |
5774 | return; | |
18c6c127 | 5775 | |
e315cd28 | 5776 | ret = qla2x00_stop_firmware(vha); |
7c7f1f29 | 5777 | for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT && |
b469a7cb | 5778 | ret != QLA_INVALID_COMMAND && retries ; retries--) { |
e315cd28 AC |
5779 | ha->isp_ops->reset_chip(vha); |
5780 | if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS) | |
18c6c127 | 5781 | continue; |
e315cd28 | 5782 | if (qla2x00_setup_chip(vha) != QLA_SUCCESS) |
18c6c127 | 5783 | continue; |
7c3df132 SK |
5784 | ql_log(ql_log_info, vha, 0x8015, |
5785 | "Attempting retry of stop-firmware command.\n"); | |
e315cd28 | 5786 | ret = qla2x00_stop_firmware(vha); |
18c6c127 AV |
5787 | } |
5788 | } | |
2c3dfe3f SJ |
5789 | |
5790 | int | |
e315cd28 | 5791 | qla24xx_configure_vhba(scsi_qla_host_t *vha) |
2c3dfe3f SJ |
5792 | { |
5793 | int rval = QLA_SUCCESS; | |
0b91d116 | 5794 | int rval2; |
2c3dfe3f | 5795 | uint16_t mb[MAILBOX_REGISTER_COUNT]; |
e315cd28 AC |
5796 | struct qla_hw_data *ha = vha->hw; |
5797 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); | |
67c2e93a AC |
5798 | struct req_que *req; |
5799 | struct rsp_que *rsp; | |
2c3dfe3f | 5800 | |
e315cd28 | 5801 | if (!vha->vp_idx) |
2c3dfe3f SJ |
5802 | return -EINVAL; |
5803 | ||
e315cd28 | 5804 | rval = qla2x00_fw_ready(base_vha); |
7163ea81 | 5805 | if (ha->flags.cpu_affinity_enabled) |
67c2e93a AC |
5806 | req = ha->req_q_map[0]; |
5807 | else | |
5808 | req = vha->req; | |
5809 | rsp = req->rsp; | |
5810 | ||
2c3dfe3f | 5811 | if (rval == QLA_SUCCESS) { |
e315cd28 | 5812 | clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); |
73208dfd | 5813 | qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL); |
2c3dfe3f SJ |
5814 | } |
5815 | ||
e315cd28 | 5816 | vha->flags.management_server_logged_in = 0; |
2c3dfe3f SJ |
5817 | |
5818 | /* Login to SNS first */ | |
0b91d116 CD |
5819 | rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb, |
5820 | BIT_1); | |
5821 | if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) { | |
5822 | if (rval2 == QLA_MEMORY_ALLOC_FAILED) | |
5823 | ql_dbg(ql_dbg_init, vha, 0x0120, | |
5824 | "Failed SNS login: loop_id=%x, rval2=%d\n", | |
5825 | NPH_SNS, rval2); | |
5826 | else | |
5827 | ql_dbg(ql_dbg_init, vha, 0x0103, | |
5828 | "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x " | |
5829 | "mb[2]=%x mb[6]=%x mb[7]=%x.\n", | |
5830 | NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]); | |
2c3dfe3f SJ |
5831 | return (QLA_FUNCTION_FAILED); |
5832 | } | |
5833 | ||
e315cd28 AC |
5834 | atomic_set(&vha->loop_down_timer, 0); |
5835 | atomic_set(&vha->loop_state, LOOP_UP); | |
5836 | set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); | |
5837 | set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); | |
5838 | rval = qla2x00_loop_resync(base_vha); | |
2c3dfe3f SJ |
5839 | |
5840 | return rval; | |
5841 | } | |
4d4df193 HK |
5842 | |
5843 | /* 84XX Support **************************************************************/ | |
5844 | ||
5845 | static LIST_HEAD(qla_cs84xx_list); | |
5846 | static DEFINE_MUTEX(qla_cs84xx_mutex); | |
5847 | ||
5848 | static struct qla_chip_state_84xx * | |
e315cd28 | 5849 | qla84xx_get_chip(struct scsi_qla_host *vha) |
4d4df193 HK |
5850 | { |
5851 | struct qla_chip_state_84xx *cs84xx; | |
e315cd28 | 5852 | struct qla_hw_data *ha = vha->hw; |
4d4df193 HK |
5853 | |
5854 | mutex_lock(&qla_cs84xx_mutex); | |
5855 | ||
5856 | /* Find any shared 84xx chip. */ | |
5857 | list_for_each_entry(cs84xx, &qla_cs84xx_list, list) { | |
5858 | if (cs84xx->bus == ha->pdev->bus) { | |
5859 | kref_get(&cs84xx->kref); | |
5860 | goto done; | |
5861 | } | |
5862 | } | |
5863 | ||
5864 | cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL); | |
5865 | if (!cs84xx) | |
5866 | goto done; | |
5867 | ||
5868 | kref_init(&cs84xx->kref); | |
5869 | spin_lock_init(&cs84xx->access_lock); | |
5870 | mutex_init(&cs84xx->fw_update_mutex); | |
5871 | cs84xx->bus = ha->pdev->bus; | |
5872 | ||
5873 | list_add_tail(&cs84xx->list, &qla_cs84xx_list); | |
5874 | done: | |
5875 | mutex_unlock(&qla_cs84xx_mutex); | |
5876 | return cs84xx; | |
5877 | } | |
5878 | ||
5879 | static void | |
5880 | __qla84xx_chip_release(struct kref *kref) | |
5881 | { | |
5882 | struct qla_chip_state_84xx *cs84xx = | |
5883 | container_of(kref, struct qla_chip_state_84xx, kref); | |
5884 | ||
5885 | mutex_lock(&qla_cs84xx_mutex); | |
5886 | list_del(&cs84xx->list); | |
5887 | mutex_unlock(&qla_cs84xx_mutex); | |
5888 | kfree(cs84xx); | |
5889 | } | |
5890 | ||
5891 | void | |
e315cd28 | 5892 | qla84xx_put_chip(struct scsi_qla_host *vha) |
4d4df193 | 5893 | { |
e315cd28 | 5894 | struct qla_hw_data *ha = vha->hw; |
4d4df193 HK |
5895 | if (ha->cs84xx) |
5896 | kref_put(&ha->cs84xx->kref, __qla84xx_chip_release); | |
5897 | } | |
5898 | ||
5899 | static int | |
e315cd28 | 5900 | qla84xx_init_chip(scsi_qla_host_t *vha) |
4d4df193 HK |
5901 | { |
5902 | int rval; | |
5903 | uint16_t status[2]; | |
e315cd28 | 5904 | struct qla_hw_data *ha = vha->hw; |
4d4df193 HK |
5905 | |
5906 | mutex_lock(&ha->cs84xx->fw_update_mutex); | |
5907 | ||
e315cd28 | 5908 | rval = qla84xx_verify_chip(vha, status); |
4d4df193 HK |
5909 | |
5910 | mutex_unlock(&ha->cs84xx->fw_update_mutex); | |
5911 | ||
5912 | return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED: | |
5913 | QLA_SUCCESS; | |
5914 | } | |
3a03eb79 AV |
5915 | |
5916 | /* 81XX Support **************************************************************/ | |
5917 | ||
5918 | int | |
5919 | qla81xx_nvram_config(scsi_qla_host_t *vha) | |
5920 | { | |
5921 | int rval; | |
5922 | struct init_cb_81xx *icb; | |
5923 | struct nvram_81xx *nv; | |
5924 | uint32_t *dptr; | |
5925 | uint8_t *dptr1, *dptr2; | |
5926 | uint32_t chksum; | |
5927 | uint16_t cnt; | |
5928 | struct qla_hw_data *ha = vha->hw; | |
5929 | ||
5930 | rval = QLA_SUCCESS; | |
5931 | icb = (struct init_cb_81xx *)ha->init_cb; | |
5932 | nv = ha->nvram; | |
5933 | ||
5934 | /* Determine NVRAM starting address. */ | |
5935 | ha->nvram_size = sizeof(struct nvram_81xx); | |
3a03eb79 | 5936 | ha->vpd_size = FA_NVRAM_VPD_SIZE; |
7ec0effd AD |
5937 | if (IS_P3P_TYPE(ha) || IS_QLA8031(ha)) |
5938 | ha->vpd_size = FA_VPD_SIZE_82XX; | |
3a03eb79 AV |
5939 | |
5940 | /* Get VPD data into cache */ | |
5941 | ha->vpd = ha->nvram + VPD_OFFSET; | |
3d79038f AV |
5942 | ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2, |
5943 | ha->vpd_size); | |
3a03eb79 AV |
5944 | |
5945 | /* Get NVRAM data into cache and calculate checksum. */ | |
3d79038f | 5946 | ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2, |
3a03eb79 | 5947 | ha->nvram_size); |
3d79038f | 5948 | dptr = (uint32_t *)nv; |
3a03eb79 AV |
5949 | for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++) |
5950 | chksum += le32_to_cpu(*dptr++); | |
5951 | ||
7c3df132 SK |
5952 | ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111, |
5953 | "Contents of NVRAM:\n"); | |
5954 | ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112, | |
5955 | (uint8_t *)nv, ha->nvram_size); | |
3a03eb79 AV |
5956 | |
5957 | /* Bad NVRAM data, set defaults parameters. */ | |
5958 | if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P' | |
5959 | || nv->id[3] != ' ' || | |
5960 | nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) { | |
5961 | /* Reset NVRAM data. */ | |
7c3df132 | 5962 | ql_log(ql_log_info, vha, 0x0073, |
9e336520 | 5963 | "Inconsistent NVRAM detected: checksum=0x%x id=%c " |
7c3df132 | 5964 | "version=0x%x.\n", chksum, nv->id[0], |
3a03eb79 | 5965 | le16_to_cpu(nv->nvram_version)); |
7c3df132 SK |
5966 | ql_log(ql_log_info, vha, 0x0074, |
5967 | "Falling back to functioning (yet invalid -- WWPN) " | |
5968 | "defaults.\n"); | |
3a03eb79 AV |
5969 | |
5970 | /* | |
5971 | * Set default initialization control block. | |
5972 | */ | |
5973 | memset(nv, 0, ha->nvram_size); | |
5974 | nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION); | |
5975 | nv->version = __constant_cpu_to_le16(ICB_VERSION); | |
98aee70d | 5976 | nv->frame_payload_size = 2048; |
3a03eb79 AV |
5977 | nv->execution_throttle = __constant_cpu_to_le16(0xFFFF); |
5978 | nv->exchange_count = __constant_cpu_to_le16(0); | |
5979 | nv->port_name[0] = 0x21; | |
f73cb695 | 5980 | nv->port_name[1] = 0x00 + ha->port_no + 1; |
3a03eb79 AV |
5981 | nv->port_name[2] = 0x00; |
5982 | nv->port_name[3] = 0xe0; | |
5983 | nv->port_name[4] = 0x8b; | |
5984 | nv->port_name[5] = 0x1c; | |
5985 | nv->port_name[6] = 0x55; | |
5986 | nv->port_name[7] = 0x86; | |
5987 | nv->node_name[0] = 0x20; | |
5988 | nv->node_name[1] = 0x00; | |
5989 | nv->node_name[2] = 0x00; | |
5990 | nv->node_name[3] = 0xe0; | |
5991 | nv->node_name[4] = 0x8b; | |
5992 | nv->node_name[5] = 0x1c; | |
5993 | nv->node_name[6] = 0x55; | |
5994 | nv->node_name[7] = 0x86; | |
5995 | nv->login_retry_count = __constant_cpu_to_le16(8); | |
5996 | nv->interrupt_delay_timer = __constant_cpu_to_le16(0); | |
5997 | nv->login_timeout = __constant_cpu_to_le16(0); | |
5998 | nv->firmware_options_1 = | |
5999 | __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1); | |
6000 | nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4); | |
6001 | nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12); | |
6002 | nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13); | |
6003 | nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10); | |
6004 | nv->efi_parameters = __constant_cpu_to_le32(0); | |
6005 | nv->reset_delay = 5; | |
6006 | nv->max_luns_per_target = __constant_cpu_to_le16(128); | |
6007 | nv->port_down_retry_count = __constant_cpu_to_le16(30); | |
6246b8a1 | 6008 | nv->link_down_timeout = __constant_cpu_to_le16(180); |
eeebcc92 | 6009 | nv->enode_mac[0] = 0x00; |
6246b8a1 GM |
6010 | nv->enode_mac[1] = 0xC0; |
6011 | nv->enode_mac[2] = 0xDD; | |
3a03eb79 AV |
6012 | nv->enode_mac[3] = 0x04; |
6013 | nv->enode_mac[4] = 0x05; | |
f73cb695 | 6014 | nv->enode_mac[5] = 0x06 + ha->port_no + 1; |
3a03eb79 AV |
6015 | |
6016 | rval = 1; | |
6017 | } | |
6018 | ||
9e522cd8 AE |
6019 | if (IS_T10_PI_CAPABLE(ha)) |
6020 | nv->frame_payload_size &= ~7; | |
6021 | ||
aa230bc5 AE |
6022 | qlt_81xx_config_nvram_stage1(vha, nv); |
6023 | ||
3a03eb79 | 6024 | /* Reset Initialization control block */ |
773120e4 | 6025 | memset(icb, 0, ha->init_cb_size); |
3a03eb79 AV |
6026 | |
6027 | /* Copy 1st segment. */ | |
6028 | dptr1 = (uint8_t *)icb; | |
6029 | dptr2 = (uint8_t *)&nv->version; | |
6030 | cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version; | |
6031 | while (cnt--) | |
6032 | *dptr1++ = *dptr2++; | |
6033 | ||
6034 | icb->login_retry_count = nv->login_retry_count; | |
6035 | ||
6036 | /* Copy 2nd segment. */ | |
6037 | dptr1 = (uint8_t *)&icb->interrupt_delay_timer; | |
6038 | dptr2 = (uint8_t *)&nv->interrupt_delay_timer; | |
6039 | cnt = (uint8_t *)&icb->reserved_5 - | |
6040 | (uint8_t *)&icb->interrupt_delay_timer; | |
6041 | while (cnt--) | |
6042 | *dptr1++ = *dptr2++; | |
6043 | ||
6044 | memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac)); | |
6045 | /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */ | |
6046 | if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) { | |
69e5f1ea AV |
6047 | icb->enode_mac[0] = 0x00; |
6048 | icb->enode_mac[1] = 0xC0; | |
6049 | icb->enode_mac[2] = 0xDD; | |
3a03eb79 AV |
6050 | icb->enode_mac[3] = 0x04; |
6051 | icb->enode_mac[4] = 0x05; | |
f73cb695 | 6052 | icb->enode_mac[5] = 0x06 + ha->port_no + 1; |
3a03eb79 AV |
6053 | } |
6054 | ||
b64b0e8f AV |
6055 | /* Use extended-initialization control block. */ |
6056 | memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb)); | |
6057 | ||
3a03eb79 AV |
6058 | /* |
6059 | * Setup driver NVRAM options. | |
6060 | */ | |
6061 | qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name), | |
a9083016 | 6062 | "QLE8XXX"); |
3a03eb79 | 6063 | |
aa230bc5 AE |
6064 | qlt_81xx_config_nvram_stage2(vha, icb); |
6065 | ||
3a03eb79 AV |
6066 | /* Use alternate WWN? */ |
6067 | if (nv->host_p & __constant_cpu_to_le32(BIT_15)) { | |
6068 | memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE); | |
6069 | memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE); | |
6070 | } | |
6071 | ||
6072 | /* Prepare nodename */ | |
6073 | if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) { | |
6074 | /* | |
6075 | * Firmware will apply the following mask if the nodename was | |
6076 | * not provided. | |
6077 | */ | |
6078 | memcpy(icb->node_name, icb->port_name, WWN_SIZE); | |
6079 | icb->node_name[0] &= 0xF0; | |
6080 | } | |
6081 | ||
6082 | /* Set host adapter parameters. */ | |
6083 | ha->flags.disable_risc_code_load = 0; | |
6084 | ha->flags.enable_lip_reset = 0; | |
6085 | ha->flags.enable_lip_full_login = | |
6086 | le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0; | |
6087 | ha->flags.enable_target_reset = | |
6088 | le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0; | |
6089 | ha->flags.enable_led_scheme = 0; | |
6090 | ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0; | |
6091 | ||
6092 | ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) & | |
6093 | (BIT_6 | BIT_5 | BIT_4)) >> 4; | |
6094 | ||
6095 | /* save HBA serial number */ | |
6096 | ha->serial0 = icb->port_name[5]; | |
6097 | ha->serial1 = icb->port_name[6]; | |
6098 | ha->serial2 = icb->port_name[7]; | |
6099 | memcpy(vha->node_name, icb->node_name, WWN_SIZE); | |
6100 | memcpy(vha->port_name, icb->port_name, WWN_SIZE); | |
6101 | ||
6102 | icb->execution_throttle = __constant_cpu_to_le16(0xFFFF); | |
6103 | ||
6104 | ha->retry_count = le16_to_cpu(nv->login_retry_count); | |
6105 | ||
6106 | /* Set minimum login_timeout to 4 seconds. */ | |
6107 | if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout) | |
6108 | nv->login_timeout = cpu_to_le16(ql2xlogintimeout); | |
6109 | if (le16_to_cpu(nv->login_timeout) < 4) | |
6110 | nv->login_timeout = __constant_cpu_to_le16(4); | |
6111 | ha->login_timeout = le16_to_cpu(nv->login_timeout); | |
6112 | icb->login_timeout = nv->login_timeout; | |
6113 | ||
6114 | /* Set minimum RATOV to 100 tenths of a second. */ | |
6115 | ha->r_a_tov = 100; | |
6116 | ||
6117 | ha->loop_reset_delay = nv->reset_delay; | |
6118 | ||
6119 | /* Link Down Timeout = 0: | |
6120 | * | |
7ec0effd | 6121 | * When Port Down timer expires we will start returning |
3a03eb79 AV |
6122 | * I/O's to OS with "DID_NO_CONNECT". |
6123 | * | |
6124 | * Link Down Timeout != 0: | |
6125 | * | |
6126 | * The driver waits for the link to come up after link down | |
6127 | * before returning I/Os to OS with "DID_NO_CONNECT". | |
6128 | */ | |
6129 | if (le16_to_cpu(nv->link_down_timeout) == 0) { | |
6130 | ha->loop_down_abort_time = | |
6131 | (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT); | |
6132 | } else { | |
6133 | ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout); | |
6134 | ha->loop_down_abort_time = | |
6135 | (LOOP_DOWN_TIME - ha->link_down_timeout); | |
6136 | } | |
6137 | ||
6138 | /* Need enough time to try and get the port back. */ | |
6139 | ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count); | |
6140 | if (qlport_down_retry) | |
6141 | ha->port_down_retry_count = qlport_down_retry; | |
6142 | ||
6143 | /* Set login_retry_count */ | |
6144 | ha->login_retry_count = le16_to_cpu(nv->login_retry_count); | |
6145 | if (ha->port_down_retry_count == | |
6146 | le16_to_cpu(nv->port_down_retry_count) && | |
6147 | ha->port_down_retry_count > 3) | |
6148 | ha->login_retry_count = ha->port_down_retry_count; | |
6149 | else if (ha->port_down_retry_count > (int)ha->login_retry_count) | |
6150 | ha->login_retry_count = ha->port_down_retry_count; | |
6151 | if (ql2xloginretrycount) | |
6152 | ha->login_retry_count = ql2xloginretrycount; | |
6153 | ||
6246b8a1 | 6154 | /* if not running MSI-X we need handshaking on interrupts */ |
f73cb695 | 6155 | if (!vha->hw->flags.msix_enabled && (IS_QLA83XX(ha) || IS_QLA27XX(ha))) |
6246b8a1 GM |
6156 | icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_22); |
6157 | ||
3a03eb79 AV |
6158 | /* Enable ZIO. */ |
6159 | if (!vha->flags.init_done) { | |
6160 | ha->zio_mode = le32_to_cpu(icb->firmware_options_2) & | |
6161 | (BIT_3 | BIT_2 | BIT_1 | BIT_0); | |
6162 | ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ? | |
6163 | le16_to_cpu(icb->interrupt_delay_timer): 2; | |
6164 | } | |
6165 | icb->firmware_options_2 &= __constant_cpu_to_le32( | |
6166 | ~(BIT_3 | BIT_2 | BIT_1 | BIT_0)); | |
6167 | vha->flags.process_response_queue = 0; | |
6168 | if (ha->zio_mode != QLA_ZIO_DISABLED) { | |
6169 | ha->zio_mode = QLA_ZIO_MODE_6; | |
6170 | ||
7c3df132 | 6171 | ql_log(ql_log_info, vha, 0x0075, |
3a03eb79 | 6172 | "ZIO mode %d enabled; timer delay (%d us).\n", |
7c3df132 SK |
6173 | ha->zio_mode, |
6174 | ha->zio_timer * 100); | |
3a03eb79 AV |
6175 | |
6176 | icb->firmware_options_2 |= cpu_to_le32( | |
6177 | (uint32_t)ha->zio_mode); | |
6178 | icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer); | |
6179 | vha->flags.process_response_queue = 1; | |
6180 | } | |
6181 | ||
6182 | if (rval) { | |
7c3df132 SK |
6183 | ql_log(ql_log_warn, vha, 0x0076, |
6184 | "NVRAM configuration failed.\n"); | |
3a03eb79 AV |
6185 | } |
6186 | return (rval); | |
6187 | } | |
6188 | ||
a9083016 GM |
6189 | int |
6190 | qla82xx_restart_isp(scsi_qla_host_t *vha) | |
6191 | { | |
6192 | int status, rval; | |
a9083016 GM |
6193 | struct qla_hw_data *ha = vha->hw; |
6194 | struct req_que *req = ha->req_q_map[0]; | |
6195 | struct rsp_que *rsp = ha->rsp_q_map[0]; | |
6196 | struct scsi_qla_host *vp; | |
feafb7b1 | 6197 | unsigned long flags; |
a9083016 GM |
6198 | |
6199 | status = qla2x00_init_rings(vha); | |
6200 | if (!status) { | |
6201 | clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); | |
6202 | ha->flags.chip_reset_done = 1; | |
6203 | ||
6204 | status = qla2x00_fw_ready(vha); | |
6205 | if (!status) { | |
a9083016 GM |
6206 | /* Issue a marker after FW becomes ready. */ |
6207 | qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL); | |
a9083016 | 6208 | vha->flags.online = 1; |
7108b76e | 6209 | set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); |
a9083016 GM |
6210 | } |
6211 | ||
6212 | /* if no cable then assume it's good */ | |
6213 | if ((vha->device_flags & DFLG_NO_CABLE)) | |
6214 | status = 0; | |
a9083016 GM |
6215 | } |
6216 | ||
6217 | if (!status) { | |
6218 | clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); | |
6219 | ||
6220 | if (!atomic_read(&vha->loop_down_timer)) { | |
6221 | /* | |
6222 | * Issue marker command only when we are going | |
6223 | * to start the I/O . | |
6224 | */ | |
6225 | vha->marker_needed = 1; | |
6226 | } | |
6227 | ||
a9083016 GM |
6228 | ha->isp_ops->enable_intrs(ha); |
6229 | ||
6230 | ha->isp_abort_cnt = 0; | |
6231 | clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); | |
6232 | ||
53296788 | 6233 | /* Update the firmware version */ |
3173167f | 6234 | status = qla82xx_check_md_needed(vha); |
53296788 | 6235 | |
a9083016 GM |
6236 | if (ha->fce) { |
6237 | ha->flags.fce_enabled = 1; | |
6238 | memset(ha->fce, 0, | |
6239 | fce_calc_size(ha->fce_bufs)); | |
6240 | rval = qla2x00_enable_fce_trace(vha, | |
6241 | ha->fce_dma, ha->fce_bufs, ha->fce_mb, | |
6242 | &ha->fce_bufs); | |
6243 | if (rval) { | |
cfb0919c | 6244 | ql_log(ql_log_warn, vha, 0x8001, |
7c3df132 SK |
6245 | "Unable to reinitialize FCE (%d).\n", |
6246 | rval); | |
a9083016 GM |
6247 | ha->flags.fce_enabled = 0; |
6248 | } | |
6249 | } | |
6250 | ||
6251 | if (ha->eft) { | |
6252 | memset(ha->eft, 0, EFT_SIZE); | |
6253 | rval = qla2x00_enable_eft_trace(vha, | |
6254 | ha->eft_dma, EFT_NUM_BUFFERS); | |
6255 | if (rval) { | |
cfb0919c | 6256 | ql_log(ql_log_warn, vha, 0x8010, |
7c3df132 SK |
6257 | "Unable to reinitialize EFT (%d).\n", |
6258 | rval); | |
a9083016 GM |
6259 | } |
6260 | } | |
a9083016 GM |
6261 | } |
6262 | ||
6263 | if (!status) { | |
cfb0919c | 6264 | ql_dbg(ql_dbg_taskm, vha, 0x8011, |
7c3df132 | 6265 | "qla82xx_restart_isp succeeded.\n"); |
feafb7b1 AE |
6266 | |
6267 | spin_lock_irqsave(&ha->vport_slock, flags); | |
6268 | list_for_each_entry(vp, &ha->vp_list, list) { | |
6269 | if (vp->vp_idx) { | |
6270 | atomic_inc(&vp->vref_count); | |
6271 | spin_unlock_irqrestore(&ha->vport_slock, flags); | |
6272 | ||
a9083016 | 6273 | qla2x00_vp_abort_isp(vp); |
feafb7b1 AE |
6274 | |
6275 | spin_lock_irqsave(&ha->vport_slock, flags); | |
6276 | atomic_dec(&vp->vref_count); | |
6277 | } | |
a9083016 | 6278 | } |
feafb7b1 AE |
6279 | spin_unlock_irqrestore(&ha->vport_slock, flags); |
6280 | ||
a9083016 | 6281 | } else { |
cfb0919c | 6282 | ql_log(ql_log_warn, vha, 0x8016, |
7c3df132 | 6283 | "qla82xx_restart_isp **** FAILED ****.\n"); |
a9083016 GM |
6284 | } |
6285 | ||
6286 | return status; | |
6287 | } | |
6288 | ||
3a03eb79 | 6289 | void |
ae97c91e | 6290 | qla81xx_update_fw_options(scsi_qla_host_t *vha) |
3a03eb79 | 6291 | { |
ae97c91e AV |
6292 | struct qla_hw_data *ha = vha->hw; |
6293 | ||
6294 | if (!ql2xetsenable) | |
6295 | return; | |
6296 | ||
6297 | /* Enable ETS Burst. */ | |
6298 | memset(ha->fw_options, 0, sizeof(ha->fw_options)); | |
6299 | ha->fw_options[2] |= BIT_9; | |
6300 | qla2x00_set_fw_options(vha, ha->fw_options); | |
3a03eb79 | 6301 | } |
09ff701a SR |
6302 | |
6303 | /* | |
6304 | * qla24xx_get_fcp_prio | |
6305 | * Gets the fcp cmd priority value for the logged in port. | |
6306 | * Looks for a match of the port descriptors within | |
6307 | * each of the fcp prio config entries. If a match is found, | |
6308 | * the tag (priority) value is returned. | |
6309 | * | |
6310 | * Input: | |
21090cbe | 6311 | * vha = scsi host structure pointer. |
09ff701a SR |
6312 | * fcport = port structure pointer. |
6313 | * | |
6314 | * Return: | |
6c452a45 | 6315 | * non-zero (if found) |
f28a0a96 | 6316 | * -1 (if not found) |
09ff701a SR |
6317 | * |
6318 | * Context: | |
6319 | * Kernel context | |
6320 | */ | |
f28a0a96 | 6321 | static int |
09ff701a SR |
6322 | qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport) |
6323 | { | |
6324 | int i, entries; | |
6325 | uint8_t pid_match, wwn_match; | |
f28a0a96 | 6326 | int priority; |
09ff701a SR |
6327 | uint32_t pid1, pid2; |
6328 | uint64_t wwn1, wwn2; | |
6329 | struct qla_fcp_prio_entry *pri_entry; | |
6330 | struct qla_hw_data *ha = vha->hw; | |
6331 | ||
6332 | if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled) | |
f28a0a96 | 6333 | return -1; |
09ff701a | 6334 | |
f28a0a96 | 6335 | priority = -1; |
09ff701a SR |
6336 | entries = ha->fcp_prio_cfg->num_entries; |
6337 | pri_entry = &ha->fcp_prio_cfg->entry[0]; | |
6338 | ||
6339 | for (i = 0; i < entries; i++) { | |
6340 | pid_match = wwn_match = 0; | |
6341 | ||
6342 | if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) { | |
6343 | pri_entry++; | |
6344 | continue; | |
6345 | } | |
6346 | ||
6347 | /* check source pid for a match */ | |
6348 | if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) { | |
6349 | pid1 = pri_entry->src_pid & INVALID_PORT_ID; | |
6350 | pid2 = vha->d_id.b24 & INVALID_PORT_ID; | |
6351 | if (pid1 == INVALID_PORT_ID) | |
6352 | pid_match++; | |
6353 | else if (pid1 == pid2) | |
6354 | pid_match++; | |
6355 | } | |
6356 | ||
6357 | /* check destination pid for a match */ | |
6358 | if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) { | |
6359 | pid1 = pri_entry->dst_pid & INVALID_PORT_ID; | |
6360 | pid2 = fcport->d_id.b24 & INVALID_PORT_ID; | |
6361 | if (pid1 == INVALID_PORT_ID) | |
6362 | pid_match++; | |
6363 | else if (pid1 == pid2) | |
6364 | pid_match++; | |
6365 | } | |
6366 | ||
6367 | /* check source WWN for a match */ | |
6368 | if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) { | |
6369 | wwn1 = wwn_to_u64(vha->port_name); | |
6370 | wwn2 = wwn_to_u64(pri_entry->src_wwpn); | |
6371 | if (wwn2 == (uint64_t)-1) | |
6372 | wwn_match++; | |
6373 | else if (wwn1 == wwn2) | |
6374 | wwn_match++; | |
6375 | } | |
6376 | ||
6377 | /* check destination WWN for a match */ | |
6378 | if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) { | |
6379 | wwn1 = wwn_to_u64(fcport->port_name); | |
6380 | wwn2 = wwn_to_u64(pri_entry->dst_wwpn); | |
6381 | if (wwn2 == (uint64_t)-1) | |
6382 | wwn_match++; | |
6383 | else if (wwn1 == wwn2) | |
6384 | wwn_match++; | |
6385 | } | |
6386 | ||
6387 | if (pid_match == 2 || wwn_match == 2) { | |
6388 | /* Found a matching entry */ | |
6389 | if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID) | |
6390 | priority = pri_entry->tag; | |
6391 | break; | |
6392 | } | |
6393 | ||
6394 | pri_entry++; | |
6395 | } | |
6396 | ||
6397 | return priority; | |
6398 | } | |
6399 | ||
6400 | /* | |
6401 | * qla24xx_update_fcport_fcp_prio | |
6402 | * Activates fcp priority for the logged in fc port | |
6403 | * | |
6404 | * Input: | |
21090cbe | 6405 | * vha = scsi host structure pointer. |
09ff701a SR |
6406 | * fcp = port structure pointer. |
6407 | * | |
6408 | * Return: | |
6409 | * QLA_SUCCESS or QLA_FUNCTION_FAILED | |
6410 | * | |
6411 | * Context: | |
6412 | * Kernel context. | |
6413 | */ | |
6414 | int | |
21090cbe | 6415 | qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport) |
09ff701a SR |
6416 | { |
6417 | int ret; | |
f28a0a96 | 6418 | int priority; |
09ff701a SR |
6419 | uint16_t mb[5]; |
6420 | ||
21090cbe MI |
6421 | if (fcport->port_type != FCT_TARGET || |
6422 | fcport->loop_id == FC_NO_LOOP_ID) | |
09ff701a SR |
6423 | return QLA_FUNCTION_FAILED; |
6424 | ||
21090cbe | 6425 | priority = qla24xx_get_fcp_prio(vha, fcport); |
f28a0a96 AV |
6426 | if (priority < 0) |
6427 | return QLA_FUNCTION_FAILED; | |
6428 | ||
7ec0effd | 6429 | if (IS_P3P_TYPE(vha->hw)) { |
a00f6296 SK |
6430 | fcport->fcp_prio = priority & 0xf; |
6431 | return QLA_SUCCESS; | |
6432 | } | |
6433 | ||
21090cbe | 6434 | ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb); |
cfb0919c CD |
6435 | if (ret == QLA_SUCCESS) { |
6436 | if (fcport->fcp_prio != priority) | |
6437 | ql_dbg(ql_dbg_user, vha, 0x709e, | |
6438 | "Updated FCP_CMND priority - value=%d loop_id=%d " | |
6439 | "port_id=%02x%02x%02x.\n", priority, | |
6440 | fcport->loop_id, fcport->d_id.b.domain, | |
6441 | fcport->d_id.b.area, fcport->d_id.b.al_pa); | |
a00f6296 | 6442 | fcport->fcp_prio = priority & 0xf; |
cfb0919c | 6443 | } else |
7c3df132 | 6444 | ql_dbg(ql_dbg_user, vha, 0x704f, |
cfb0919c CD |
6445 | "Unable to update FCP_CMND priority - ret=0x%x for " |
6446 | "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id, | |
6447 | fcport->d_id.b.domain, fcport->d_id.b.area, | |
6448 | fcport->d_id.b.al_pa); | |
09ff701a SR |
6449 | return ret; |
6450 | } | |
6451 | ||
6452 | /* | |
6453 | * qla24xx_update_all_fcp_prio | |
6454 | * Activates fcp priority for all the logged in ports | |
6455 | * | |
6456 | * Input: | |
6457 | * ha = adapter block pointer. | |
6458 | * | |
6459 | * Return: | |
6460 | * QLA_SUCCESS or QLA_FUNCTION_FAILED | |
6461 | * | |
6462 | * Context: | |
6463 | * Kernel context. | |
6464 | */ | |
6465 | int | |
6466 | qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha) | |
6467 | { | |
6468 | int ret; | |
6469 | fc_port_t *fcport; | |
6470 | ||
6471 | ret = QLA_FUNCTION_FAILED; | |
6472 | /* We need to set priority for all logged in ports */ | |
6473 | list_for_each_entry(fcport, &vha->vp_fcports, list) | |
6474 | ret = qla24xx_update_fcport_fcp_prio(vha, fcport); | |
6475 | ||
6476 | return ret; | |
6477 | } |