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[SCSI] qla2xxx: Parameterize the link speed of hba rather than fcport.
[deliverable/linux.git] / drivers / scsi / qla2xxx / qla_init.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
46152ceb 3 * Copyright (c) 2003-2012 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
73208dfd 8#include "qla_gbl.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/slab.h>
0107109e 12#include <linux/vmalloc.h>
1da177e4
LT		 13
14#include "qla_devtbl.h"
15
4e08df3f
DM		 16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
4e08df3f
DM		 18#endif
19
2d70c103
NB		 20#include <target/target_core_base.h>
21#include "qla_target.h"
22
1da177e4
LT		 23/*
24* QLogic ISP2x00 Hardware Support Function Prototypes.
25*/
1da177e4 26static int qla2x00_isp_firmware(scsi_qla_host_t *);
1da177e4 27static int qla2x00_setup_chip(scsi_qla_host_t *);
1da177e4
LT		 28static int qla2x00_init_rings(scsi_qla_host_t *);
29static int qla2x00_fw_ready(scsi_qla_host_t *);
30static int qla2x00_configure_hba(scsi_qla_host_t *);
1da177e4
LT		 31static int qla2x00_configure_loop(scsi_qla_host_t *);
32static int qla2x00_configure_local_loop(scsi_qla_host_t *);
1da177e4
LT		 33static int qla2x00_configure_fabric(scsi_qla_host_t *);
34static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *);
1da177e4
LT		 35static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
36 uint16_t *);
1da177e4
LT		 37
38static int qla2x00_restart_isp(scsi_qla_host_t *);
1da177e4 39
4d4df193
HK		 40static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
41static int qla84xx_init_chip(scsi_qla_host_t *);
73208dfd 42static int qla25xx_init_queues(struct qla_hw_data *);
4d4df193 43
ac280b67
AV		 44/* SRB Extensions ---------------------------------------------------------- */
45
9ba56b95
GM		 46void
47qla2x00_sp_timeout(unsigned long __data)
ac280b67
AV		 48{
49 srb_t *sp = (srb_t *)__data;
4916392b 50 struct srb_iocb *iocb;
ac280b67
AV		 51 fc_port_t *fcport = sp->fcport;
52 struct qla_hw_data *ha = fcport->vha->hw;
53 struct req_que *req;
54 unsigned long flags;
55
56 spin_lock_irqsave(&ha->hardware_lock, flags);
57 req = ha->req_q_map[0];
58 req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 59 iocb = &sp->u.iocb_cmd;
4916392b 60 iocb->timeout(sp);
9ba56b95 61 sp->free(fcport->vha, sp);
6ac52608 62 spin_unlock_irqrestore(&ha->hardware_lock, flags);
ac280b67
AV		 63}
64
9ba56b95
GM		 65void
66qla2x00_sp_free(void *data, void *ptr)
ac280b67 67{
9ba56b95
GM		 68 srb_t *sp = (srb_t *)ptr;
69 struct srb_iocb *iocb = &sp->u.iocb_cmd;
70 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
ac280b67 71
4d97cc53 72 del_timer(&iocb->timer);
9ba56b95 73 mempool_free(sp, vha->hw->srb_mempool);
feafb7b1
AE		 74
75 QLA_VHA_MARK_NOT_BUSY(vha);
ac280b67
AV		 76}
77
ac280b67
AV		 78/* Asynchronous Login/Logout Routines -------------------------------------- */
79
a9b6f722 80unsigned long
5b91490e
AV		 81qla2x00_get_async_timeout(struct scsi_qla_host *vha)
82{
83 unsigned long tmo;
84 struct qla_hw_data *ha = vha->hw;
85
86 /* Firmware should use switch negotiated r_a_tov for timeout. */
87 tmo = ha->r_a_tov / 10 * 2;
88 if (!IS_FWI2_CAPABLE(ha)) {
89 /*
90 * Except for earlier ISPs where the timeout is seeded from the
91 * initialization control block.
92 */
93 tmo = ha->login_timeout;
94 }
95 return tmo;
96}
ac280b67
AV		 97
98static void
9ba56b95 99qla2x00_async_iocb_timeout(void *data)
ac280b67 100{
9ba56b95 101 srb_t *sp = (srb_t *)data;
ac280b67 102 fc_port_t *fcport = sp->fcport;
ac280b67 103
7c3df132 104 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
cfb0919c 105 "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n",
9ba56b95 106 sp->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area,
7c3df132 107 fcport->d_id.b.al_pa);
ac280b67 108
5ff1d584 109 fcport->flags &= ~FCF_ASYNC_SENT;
9ba56b95
GM		 110 if (sp->type == SRB_LOGIN_CMD) {
111 struct srb_iocb *lio = &sp->u.iocb_cmd;
ac280b67 112 qla2x00_post_async_logout_work(fcport->vha, fcport, NULL);
6ac52608
AV		 113 /* Retry as needed. */
114 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
115 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
116 QLA_LOGIO_LOGIN_RETRIED : 0;
117 qla2x00_post_async_login_done_work(fcport->vha, fcport,
118 lio->u.logio.data);
119 }
ac280b67
AV		 120}
121
99b0bec7 122static void
9ba56b95 123qla2x00_async_login_sp_done(void *data, void *ptr, int res)
99b0bec7 124{
9ba56b95
GM		 125 srb_t *sp = (srb_t *)ptr;
126 struct srb_iocb *lio = &sp->u.iocb_cmd;
127 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
128
129 if (!test_bit(UNLOADING, &vha->dpc_flags))
130 qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport,
131 lio->u.logio.data);
132 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 133}
134
ac280b67
AV		 135int
136qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
137 uint16_t *data)
138{
ac280b67 139 srb_t *sp;
4916392b 140 struct srb_iocb *lio;
ac280b67
AV		 141 int rval;
142
143 rval = QLA_FUNCTION_FAILED;
9ba56b95 144 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 145 if (!sp)
146 goto done;
147
9ba56b95
GM		 148 sp->type = SRB_LOGIN_CMD;
149 sp->name = "login";
150 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
151
152 lio = &sp->u.iocb_cmd;
3822263e 153 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 154 sp->done = qla2x00_async_login_sp_done;
4916392b 155 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
ac280b67 156 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 157 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
ac280b67
AV		 158 rval = qla2x00_start_sp(sp);
159 if (rval != QLA_SUCCESS)
160 goto done_free_sp;
161
7c3df132 162 ql_dbg(ql_dbg_disc, vha, 0x2072,
cfb0919c
CD		 163 "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x "
164 "retries=%d.\n", sp->handle, fcport->loop_id,
165 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
166 fcport->login_retry);
ac280b67
AV		 167 return rval;
168
169done_free_sp:
9ba56b95 170 sp->free(fcport->vha, sp);
ac280b67
AV		 171done:
172 return rval;
173}
174
99b0bec7 175static void
9ba56b95 176qla2x00_async_logout_sp_done(void *data, void *ptr, int res)
99b0bec7 177{
9ba56b95
GM		 178 srb_t *sp = (srb_t *)ptr;
179 struct srb_iocb *lio = &sp->u.iocb_cmd;
180 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
181
182 if (!test_bit(UNLOADING, &vha->dpc_flags))
183 qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport,
184 lio->u.logio.data);
185 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 186}
187
ac280b67
AV		 188int
189qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
190{
ac280b67 191 srb_t *sp;
4916392b 192 struct srb_iocb *lio;
ac280b67
AV		 193 int rval;
194
195 rval = QLA_FUNCTION_FAILED;
9ba56b95 196 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 197 if (!sp)
198 goto done;
199
9ba56b95
GM		 200 sp->type = SRB_LOGOUT_CMD;
201 sp->name = "logout";
202 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
203
204 lio = &sp->u.iocb_cmd;
3822263e 205 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 206 sp->done = qla2x00_async_logout_sp_done;
ac280b67
AV		 207 rval = qla2x00_start_sp(sp);
208 if (rval != QLA_SUCCESS)
209 goto done_free_sp;
210
7c3df132 211 ql_dbg(ql_dbg_disc, vha, 0x2070,
cfb0919c
CD		 212 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
213 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
214 fcport->d_id.b.area, fcport->d_id.b.al_pa);
ac280b67
AV		 215 return rval;
216
217done_free_sp:
9ba56b95 218 sp->free(fcport->vha, sp);
ac280b67
AV		 219done:
220 return rval;
221}
222
5ff1d584 223static void
9ba56b95 224qla2x00_async_adisc_sp_done(void *data, void *ptr, int res)
5ff1d584 225{
9ba56b95
GM		 226 srb_t *sp = (srb_t *)ptr;
227 struct srb_iocb *lio = &sp->u.iocb_cmd;
228 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
229
230 if (!test_bit(UNLOADING, &vha->dpc_flags))
231 qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport,
232 lio->u.logio.data);
233 sp->free(sp->fcport->vha, sp);
5ff1d584
AV		 234}
235
236int
237qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
238 uint16_t *data)
239{
5ff1d584 240 srb_t *sp;
4916392b 241 struct srb_iocb *lio;
5ff1d584
AV		 242 int rval;
243
244 rval = QLA_FUNCTION_FAILED;
9ba56b95 245 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
5ff1d584
AV		 246 if (!sp)
247 goto done;
248
9ba56b95
GM		 249 sp->type = SRB_ADISC_CMD;
250 sp->name = "adisc";
251 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
252
253 lio = &sp->u.iocb_cmd;
3822263e 254 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 255 sp->done = qla2x00_async_adisc_sp_done;
5ff1d584 256 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 257 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
5ff1d584
AV		 258 rval = qla2x00_start_sp(sp);
259 if (rval != QLA_SUCCESS)
260 goto done_free_sp;
261
7c3df132 262 ql_dbg(ql_dbg_disc, vha, 0x206f,
cfb0919c
CD		 263 "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
264 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
265 fcport->d_id.b.area, fcport->d_id.b.al_pa);
5ff1d584
AV		 266 return rval;
267
268done_free_sp:
9ba56b95 269 sp->free(fcport->vha, sp);
5ff1d584
AV		 270done:
271 return rval;
272}
273
3822263e 274static void
9ba56b95 275qla2x00_async_tm_cmd_done(void *data, void *ptr, int res)
3822263e 276{
9ba56b95
GM		 277 srb_t *sp = (srb_t *)ptr;
278 struct srb_iocb *iocb = &sp->u.iocb_cmd;
279 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
280 uint32_t flags;
281 uint16_t lun;
282 int rval;
3822263e 283
9ba56b95
GM		 284 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
285 flags = iocb->u.tmf.flags;
286 lun = (uint16_t)iocb->u.tmf.lun;
287
288 /* Issue Marker IOCB */
289 rval = qla2x00_marker(vha, vha->hw->req_q_map[0],
290 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
291 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
292
293 if ((rval != QLA_SUCCESS) || iocb->u.tmf.data) {
294 ql_dbg(ql_dbg_taskm, vha, 0x8030,
295 "TM IOCB failed (%x).\n", rval);
296 }
297 }
298 sp->free(sp->fcport->vha, sp);
3822263e
MI		 299}
300
301int
9ba56b95 302qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t tm_flags, uint32_t lun,
3822263e
MI		 303 uint32_t tag)
304{
305 struct scsi_qla_host *vha = fcport->vha;
3822263e 306 srb_t *sp;
3822263e
MI		 307 struct srb_iocb *tcf;
308 int rval;
309
310 rval = QLA_FUNCTION_FAILED;
9ba56b95 311 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
3822263e
MI		 312 if (!sp)
313 goto done;
314
9ba56b95
GM		 315 sp->type = SRB_TM_CMD;
316 sp->name = "tmf";
317 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
318
319 tcf = &sp->u.iocb_cmd;
320 tcf->u.tmf.flags = tm_flags;
3822263e
MI		 321 tcf->u.tmf.lun = lun;
322 tcf->u.tmf.data = tag;
323 tcf->timeout = qla2x00_async_iocb_timeout;
9ba56b95 324 sp->done = qla2x00_async_tm_cmd_done;
3822263e
MI		 325
326 rval = qla2x00_start_sp(sp);
327 if (rval != QLA_SUCCESS)
328 goto done_free_sp;
329
7c3df132 330 ql_dbg(ql_dbg_taskm, vha, 0x802f,
cfb0919c
CD		 331 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
332 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
333 fcport->d_id.b.area, fcport->d_id.b.al_pa);
3822263e
MI		 334 return rval;
335
336done_free_sp:
9ba56b95 337 sp->free(fcport->vha, sp);
3822263e
MI		 338done:
339 return rval;
340}
341
4916392b 342void
ac280b67
AV		 343qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport,
344 uint16_t *data)
345{
346 int rval;
ac280b67
AV		 347
348 switch (data[0]) {
349 case MBS_COMMAND_COMPLETE:
a4f92a32
AV		 350 /*
351 * Driver must validate login state - If PRLI not complete,
352 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
353 * requests.
354 */
355 rval = qla2x00_get_port_database(vha, fcport, 0);
0eba25df
AE		 356 if (rval == QLA_NOT_LOGGED_IN) {
357 fcport->flags &= ~FCF_ASYNC_SENT;
358 fcport->flags |= FCF_LOGIN_NEEDED;
359 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
360 break;
361 }
362
a4f92a32
AV		 363 if (rval != QLA_SUCCESS) {
364 qla2x00_post_async_logout_work(vha, fcport, NULL);
365 qla2x00_post_async_login_work(vha, fcport, NULL);
366 break;
367 }
99b0bec7 368 if (fcport->flags & FCF_FCP2_DEVICE) {
5ff1d584
AV		 369 qla2x00_post_async_adisc_work(vha, fcport, data);
370 break;
99b0bec7
AV		 371 }
372 qla2x00_update_fcport(vha, fcport);
ac280b67
AV		 373 break;
374 case MBS_COMMAND_ERROR:
5ff1d584 375 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 376 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
377 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
378 else
80d79440 379 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 380 break;
381 case MBS_PORT_ID_USED:
382 fcport->loop_id = data[1];
6ac52608 383 qla2x00_post_async_logout_work(vha, fcport, NULL);
ac280b67
AV		 384 qla2x00_post_async_login_work(vha, fcport, NULL);
385 break;
386 case MBS_LOOP_ID_USED:
387 fcport->loop_id++;
388 rval = qla2x00_find_new_loop_id(vha, fcport);
389 if (rval != QLA_SUCCESS) {
5ff1d584 390 fcport->flags &= ~FCF_ASYNC_SENT;
80d79440 391 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 392 break;
393 }
394 qla2x00_post_async_login_work(vha, fcport, NULL);
395 break;
396 }
4916392b 397 return;
ac280b67
AV		 398}
399
4916392b 400void
ac280b67
AV		 401qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
402 uint16_t *data)
403{
404 qla2x00_mark_device_lost(vha, fcport, 1, 0);
4916392b 405 return;
ac280b67
AV		 406}
407
4916392b 408void
5ff1d584
AV		 409qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
410 uint16_t *data)
411{
412 if (data[0] == MBS_COMMAND_COMPLETE) {
413 qla2x00_update_fcport(vha, fcport);
414
4916392b 415 return;
5ff1d584
AV		 416 }
417
418 /* Retry login. */
419 fcport->flags &= ~FCF_ASYNC_SENT;
420 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
421 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
422 else
80d79440 423 qla2x00_mark_device_lost(vha, fcport, 1, 0);
5ff1d584 424
4916392b 425 return;
5ff1d584
AV		 426}
427
1da177e4
LT		 428/****************************************************************************/
429/* QLogic ISP2x00 Hardware Support Functions. */
430/****************************************************************************/
431
fa492630 432static int
7d613ac6
SV		 433qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
434{
435 int rval = QLA_SUCCESS;
436 struct qla_hw_data *ha = vha->hw;
437 uint32_t idc_major_ver, idc_minor_ver;
711aa7f7 438 uint16_t config[4];
7d613ac6
SV		 439
440 qla83xx_idc_lock(vha, 0);
441
442 /* SV: TODO: Assign initialization timeout from
443 * flash-info / other param
444 */
445 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
446 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
447
448 /* Set our fcoe function presence */
449 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
450 ql_dbg(ql_dbg_p3p, vha, 0xb077,
451 "Error while setting DRV-Presence.\n");
452 rval = QLA_FUNCTION_FAILED;
453 goto exit;
454 }
455
456 /* Decide the reset ownership */
457 qla83xx_reset_ownership(vha);
458
459 /*
460 * On first protocol driver load:
461 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
462 * register.
463 * Others: Check compatibility with current IDC Major version.
464 */
465 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
466 if (ha->flags.nic_core_reset_owner) {
467 /* Set IDC Major version */
468 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
469 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
470
471 /* Clearing IDC-Lock-Recovery register */
472 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
473 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
474 /*
475 * Clear further IDC participation if we are not compatible with
476 * the current IDC Major Version.
477 */
478 ql_log(ql_log_warn, vha, 0xb07d,
479 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
480 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
481 __qla83xx_clear_drv_presence(vha);
482 rval = QLA_FUNCTION_FAILED;
483 goto exit;
484 }
485 /* Each function sets its supported Minor version. */
486 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
487 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
488 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
489
711aa7f7
SK		 490 if (ha->flags.nic_core_reset_owner) {
491 memset(config, 0, sizeof(config));
492 if (!qla81xx_get_port_config(vha, config))
493 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
494 QLA8XXX_DEV_READY);
495 }
496
7d613ac6
SV		 497 rval = qla83xx_idc_state_handler(vha);
498
499exit:
500 qla83xx_idc_unlock(vha, 0);
501
502 return rval;
503}
504
1da177e4
LT		 505/*
506* qla2x00_initialize_adapter
507* Initialize board.
508*
509* Input:
510* ha = adapter block pointer.
511*
512* Returns:
513* 0 = success
514*/
515int
e315cd28 516qla2x00_initialize_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 517{
518 int rval;
e315cd28 519 struct qla_hw_data *ha = vha->hw;
73208dfd 520 struct req_que *req = ha->req_q_map[0];
2533cf67 521
1da177e4 522 /* Clear adapter flags. */
e315cd28 523 vha->flags.online = 0;
2533cf67 524 ha->flags.chip_reset_done = 0;
e315cd28 525 vha->flags.reset_active = 0;
85880801
AV		 526 ha->flags.pci_channel_io_perm_failure = 0;
527 ha->flags.eeh_busy = 0;
794a5691 528 ha->flags.thermal_supported = 1;
e315cd28
AC		 529 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
530 atomic_set(&vha->loop_state, LOOP_DOWN);
531 vha->device_flags = DFLG_NO_CABLE;
532 vha->dpc_flags = 0;
533 vha->flags.management_server_logged_in = 0;
534 vha->marker_needed = 0;
1da177e4
LT		 535 ha->isp_abort_cnt = 0;
536 ha->beacon_blink_led = 0;
537
73208dfd
AC		 538 set_bit(0, ha->req_qid_map);
539 set_bit(0, ha->rsp_qid_map);
540
cfb0919c 541 ql_dbg(ql_dbg_init, vha, 0x0040,
7c3df132 542 "Configuring PCI space...\n");
e315cd28 543 rval = ha->isp_ops->pci_config(vha);
1da177e4 544 if (rval) {
7c3df132
SK		 545 ql_log(ql_log_warn, vha, 0x0044,
546 "Unable to configure PCI space.\n");
1da177e4
LT		 547 return (rval);
548 }
549
e315cd28 550 ha->isp_ops->reset_chip(vha);
1da177e4 551
e315cd28 552 rval = qla2xxx_get_flash_info(vha);
c00d8994 553 if (rval) {
7c3df132
SK		 554 ql_log(ql_log_fatal, vha, 0x004f,
555 "Unable to validate FLASH data.\n");
c00d8994
AV		 556 return (rval);
557 }
558
73208dfd 559 ha->isp_ops->get_flash_version(vha, req->ring);
cfb0919c 560 ql_dbg(ql_dbg_init, vha, 0x0061,
7c3df132 561 "Configure NVRAM parameters...\n");
0107109e 562
e315cd28 563 ha->isp_ops->nvram_config(vha);
1da177e4 564
d4c760c2
AV		 565 if (ha->flags.disable_serdes) {
566 /* Mask HBA via NVRAM settings? */
7c3df132
SK		 567 ql_log(ql_log_info, vha, 0x0077,
568 "Masking HBA WWPN "
d4c760c2 569 "%02x%02x%02x%02x%02x%02x%02x%02x (via NVRAM).\n",
e315cd28
AC		 570 vha->port_name[0], vha->port_name[1],
571 vha->port_name[2], vha->port_name[3],
572 vha->port_name[4], vha->port_name[5],
573 vha->port_name[6], vha->port_name[7]);
d4c760c2
AV		 574 return QLA_FUNCTION_FAILED;
575 }
576
cfb0919c 577 ql_dbg(ql_dbg_init, vha, 0x0078,
7c3df132 578 "Verifying loaded RISC code...\n");
1da177e4 579
e315cd28
AC		 580 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
581 rval = ha->isp_ops->chip_diag(vha);
d19044c3
AV		 582 if (rval)
583 return (rval);
e315cd28 584 rval = qla2x00_setup_chip(vha);
d19044c3
AV		 585 if (rval)
586 return (rval);
1da177e4 587 }
a9083016 588
4d4df193 589 if (IS_QLA84XX(ha)) {
e315cd28 590 ha->cs84xx = qla84xx_get_chip(vha);
4d4df193 591 if (!ha->cs84xx) {
7c3df132 592 ql_log(ql_log_warn, vha, 0x00d0,
4d4df193
HK		 593 "Unable to configure ISP84XX.\n");
594 return QLA_FUNCTION_FAILED;
595 }
596 }
2d70c103
NB		 597
598 if (qla_ini_mode_enabled(vha))
599 rval = qla2x00_init_rings(vha);
600
2533cf67 601 ha->flags.chip_reset_done = 1;
1da177e4 602
9a069e19 603 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
6c452a45 604 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
9a069e19
GM		 605 rval = qla84xx_init_chip(vha);
606 if (rval != QLA_SUCCESS) {
7c3df132
SK		 607 ql_log(ql_log_warn, vha, 0x00d4,
608 "Unable to initialize ISP84XX.\n");
9a069e19
GM		 609 qla84xx_put_chip(vha);
610 }
611 }
612
7d613ac6
SV		 613 /* Load the NIC Core f/w if we are the first protocol driver. */
614 if (IS_QLA8031(ha)) {
615 rval = qla83xx_nic_core_fw_load(vha);
616 if (rval)
617 ql_log(ql_log_warn, vha, 0x0124,
618 "Error in initializing NIC Core f/w.\n");
619 }
620
2f0f3f4f
MI		 621 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
622 qla24xx_read_fcp_prio_cfg(vha);
09ff701a 623
1da177e4
LT		 624 return (rval);
625}
626
627/**
abbd8870 628 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
1da177e4
LT		 629 * @ha: HA context
630 *
631 * Returns 0 on success.
632 */
abbd8870 633int
e315cd28 634qla2100_pci_config(scsi_qla_host_t *vha)
1da177e4 635{
a157b101 636 uint16_t w;
abbd8870 637 unsigned long flags;
e315cd28 638 struct qla_hw_data *ha = vha->hw;
3d71644c 639 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 640
1da177e4 641 pci_set_master(ha->pdev);
af6177d8 642 pci_try_set_mwi(ha->pdev);
1da177e4 643
1da177e4 644 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 645 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
abbd8870
AV		 646 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
647
737faece 648 pci_disable_rom(ha->pdev);
1da177e4
LT		 649
650 /* Get PCI bus information. */
651 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 652 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
1da177e4
LT		 653 spin_unlock_irqrestore(&ha->hardware_lock, flags);
654
abbd8870
AV		 655 return QLA_SUCCESS;
656}
1da177e4 657
abbd8870
AV		 658/**
659 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
660 * @ha: HA context
661 *
662 * Returns 0 on success.
663 */
664int
e315cd28 665qla2300_pci_config(scsi_qla_host_t *vha)
abbd8870 666{
a157b101 667 uint16_t w;
abbd8870
AV		 668 unsigned long flags = 0;
669 uint32_t cnt;
e315cd28 670 struct qla_hw_data *ha = vha->hw;
3d71644c 671 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 672
abbd8870 673 pci_set_master(ha->pdev);
af6177d8 674 pci_try_set_mwi(ha->pdev);
1da177e4 675
abbd8870 676 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 677 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1da177e4 678
abbd8870
AV		 679 if (IS_QLA2322(ha) || IS_QLA6322(ha))
680 w &= ~PCI_COMMAND_INTX_DISABLE;
a157b101 681 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1da177e4 682
abbd8870
AV		 683 /*
684 * If this is a 2300 card and not 2312, reset the
685 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
686 * the 2310 also reports itself as a 2300 so we need to get the
687 * fb revision level -- a 6 indicates it really is a 2300 and
688 * not a 2310.
689 */
690 if (IS_QLA2300(ha)) {
691 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 692
abbd8870 693 /* Pause RISC. */
3d71644c 694 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
abbd8870 695 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 696 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
abbd8870 697 break;
1da177e4 698
abbd8870
AV		 699 udelay(10);
700 }
1da177e4 701
abbd8870 702 /* Select FPM registers. */
3d71644c
AV		 703 WRT_REG_WORD(&reg->ctrl_status, 0x20);
704 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 705
706 /* Get the fb rev level */
3d71644c 707 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
abbd8870
AV		 708
709 if (ha->fb_rev == FPM_2300)
a157b101 710 pci_clear_mwi(ha->pdev);
abbd8870
AV		 711
712 /* Deselect FPM registers. */
3d71644c
AV		 713 WRT_REG_WORD(&reg->ctrl_status, 0x0);
714 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 715
716 /* Release RISC module. */
3d71644c 717 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
abbd8870 718 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 719 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
abbd8870
AV		 720 break;
721
722 udelay(10);
1da177e4 723 }
1da177e4 724
abbd8870
AV		 725 spin_unlock_irqrestore(&ha->hardware_lock, flags);
726 }
1da177e4 727
abbd8870
AV		 728 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
729
737faece 730 pci_disable_rom(ha->pdev);
1da177e4 731
abbd8870
AV		 732 /* Get PCI bus information. */
733 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 734 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 735 spin_unlock_irqrestore(&ha->hardware_lock, flags);
736
737 return QLA_SUCCESS;
1da177e4
LT		 738}
739
0107109e
AV		 740/**
741 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
742 * @ha: HA context
743 *
744 * Returns 0 on success.
745 */
746int
e315cd28 747qla24xx_pci_config(scsi_qla_host_t *vha)
0107109e 748{
a157b101 749 uint16_t w;
0107109e 750 unsigned long flags = 0;
e315cd28 751 struct qla_hw_data *ha = vha->hw;
0107109e 752 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
0107109e
AV		 753
754 pci_set_master(ha->pdev);
af6177d8 755 pci_try_set_mwi(ha->pdev);
0107109e
AV		 756
757 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 758 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
0107109e
AV		 759 w &= ~PCI_COMMAND_INTX_DISABLE;
760 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
761
762 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
763
764 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
f85ec187
AV		 765 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
766 pcix_set_mmrbc(ha->pdev, 2048);
0107109e
AV		 767
768 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 769 if (pci_is_pcie(ha->pdev))
5ffd3a52 770 pcie_set_readrq(ha->pdev, 4096);
0107109e 771
737faece 772 pci_disable_rom(ha->pdev);
0107109e 773
44c10138 774 ha->chip_revision = ha->pdev->revision;
a8488abe 775
0107109e
AV		 776 /* Get PCI bus information. */
777 spin_lock_irqsave(&ha->hardware_lock, flags);
778 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
779 spin_unlock_irqrestore(&ha->hardware_lock, flags);
780
781 return QLA_SUCCESS;
782}
783
c3a2f0df
AV		 784/**
785 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
786 * @ha: HA context
787 *
788 * Returns 0 on success.
789 */
790int
e315cd28 791qla25xx_pci_config(scsi_qla_host_t *vha)
c3a2f0df
AV		 792{
793 uint16_t w;
e315cd28 794 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 795
796 pci_set_master(ha->pdev);
797 pci_try_set_mwi(ha->pdev);
798
799 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
800 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
801 w &= ~PCI_COMMAND_INTX_DISABLE;
802 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
803
804 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 805 if (pci_is_pcie(ha->pdev))
5ffd3a52 806 pcie_set_readrq(ha->pdev, 4096);
c3a2f0df 807
737faece 808 pci_disable_rom(ha->pdev);
c3a2f0df
AV		 809
810 ha->chip_revision = ha->pdev->revision;
811
812 return QLA_SUCCESS;
813}
814
1da177e4
LT		 815/**
816 * qla2x00_isp_firmware() - Choose firmware image.
817 * @ha: HA context
818 *
819 * Returns 0 on success.
820 */
821static int
e315cd28 822qla2x00_isp_firmware(scsi_qla_host_t *vha)
1da177e4
LT		 823{
824 int rval;
42e421b1
AV		 825 uint16_t loop_id, topo, sw_cap;
826 uint8_t domain, area, al_pa;
e315cd28 827 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 828
829 /* Assume loading risc code */
fa2a1ce5 830 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 831
832 if (ha->flags.disable_risc_code_load) {
7c3df132 833 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
1da177e4
LT		 834
835 /* Verify checksum of loaded RISC code. */
e315cd28 836 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
42e421b1
AV		 837 if (rval == QLA_SUCCESS) {
838 /* And, verify we are not in ROM code. */
e315cd28 839 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
42e421b1
AV		 840 &area, &domain, &topo, &sw_cap);
841 }
1da177e4
LT		 842 }
843
7c3df132
SK		 844 if (rval)
845 ql_dbg(ql_dbg_init, vha, 0x007a,
846 "**** Load RISC code ****.\n");
1da177e4
LT		 847
848 return (rval);
849}
850
851/**
852 * qla2x00_reset_chip() - Reset ISP chip.
853 * @ha: HA context
854 *
855 * Returns 0 on success.
856 */
abbd8870 857void
e315cd28 858qla2x00_reset_chip(scsi_qla_host_t *vha)
1da177e4
LT		 859{
860 unsigned long flags = 0;
e315cd28 861 struct qla_hw_data *ha = vha->hw;
3d71644c 862 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 863 uint32_t cnt;
1da177e4
LT		 864 uint16_t cmd;
865
85880801
AV		 866 if (unlikely(pci_channel_offline(ha->pdev)))
867 return;
868
fd34f556 869 ha->isp_ops->disable_intrs(ha);
1da177e4
LT		 870
871 spin_lock_irqsave(&ha->hardware_lock, flags);
872
873 /* Turn off master enable */
874 cmd = 0;
875 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
876 cmd &= ~PCI_COMMAND_MASTER;
877 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
878
879 if (!IS_QLA2100(ha)) {
880 /* Pause RISC. */
881 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
882 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
883 for (cnt = 0; cnt < 30000; cnt++) {
884 if ((RD_REG_WORD(&reg->hccr) &
885 HCCR_RISC_PAUSE) != 0)
886 break;
887 udelay(100);
888 }
889 } else {
890 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
891 udelay(10);
892 }
893
894 /* Select FPM registers. */
895 WRT_REG_WORD(&reg->ctrl_status, 0x20);
896 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
897
898 /* FPM Soft Reset. */
899 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
900 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
901
902 /* Toggle Fpm Reset. */
903 if (!IS_QLA2200(ha)) {
904 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
905 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
906 }
907
908 /* Select frame buffer registers. */
909 WRT_REG_WORD(&reg->ctrl_status, 0x10);
910 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
911
912 /* Reset frame buffer FIFOs. */
913 if (IS_QLA2200(ha)) {
914 WRT_FB_CMD_REG(ha, reg, 0xa000);
915 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
916 } else {
917 WRT_FB_CMD_REG(ha, reg, 0x00fc);
918
919 /* Read back fb_cmd until zero or 3 seconds max */
920 for (cnt = 0; cnt < 3000; cnt++) {
921 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
922 break;
923 udelay(100);
924 }
925 }
926
927 /* Select RISC module registers. */
928 WRT_REG_WORD(&reg->ctrl_status, 0);
929 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
930
931 /* Reset RISC processor. */
932 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
933 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
934
935 /* Release RISC processor. */
936 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
937 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
938 }
939
940 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
941 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
942
943 /* Reset ISP chip. */
944 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
945
946 /* Wait for RISC to recover from reset. */
947 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
948 /*
949 * It is necessary to for a delay here since the card doesn't
950 * respond to PCI reads during a reset. On some architectures
951 * this will result in an MCA.
952 */
953 udelay(20);
954 for (cnt = 30000; cnt; cnt--) {
955 if ((RD_REG_WORD(&reg->ctrl_status) &
956 CSR_ISP_SOFT_RESET) == 0)
957 break;
958 udelay(100);
959 }
960 } else
961 udelay(10);
962
963 /* Reset RISC processor. */
964 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
965
966 WRT_REG_WORD(&reg->semaphore, 0);
967
968 /* Release RISC processor. */
969 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
970 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
971
972 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
973 for (cnt = 0; cnt < 30000; cnt++) {
ffb39f03 974 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1da177e4 975 break;
1da177e4
LT		 976
977 udelay(100);
978 }
979 } else
980 udelay(100);
981
982 /* Turn on master enable */
983 cmd |= PCI_COMMAND_MASTER;
984 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
985
986 /* Disable RISC pause on FPM parity error. */
987 if (!IS_QLA2100(ha)) {
988 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
989 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
990 }
991
992 spin_unlock_irqrestore(&ha->hardware_lock, flags);
993}
994
b1d46989
MI		 995/**
996 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
997 *
998 * Returns 0 on success.
999 */
fa492630 1000static int
b1d46989
MI		 1001qla81xx_reset_mpi(scsi_qla_host_t *vha)
1002{
1003 uint16_t mb[4] = {0x1010, 0, 1, 0};
1004
6246b8a1
GM		 1005 if (!IS_QLA81XX(vha->hw))
1006 return QLA_SUCCESS;
1007
b1d46989
MI		 1008 return qla81xx_write_mpi_register(vha, mb);
1009}
1010
0107109e 1011/**
88c26663 1012 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
0107109e
AV		 1013 * @ha: HA context
1014 *
1015 * Returns 0 on success.
1016 */
88c26663 1017static inline void
e315cd28 1018qla24xx_reset_risc(scsi_qla_host_t *vha)
0107109e
AV		 1019{
1020 unsigned long flags = 0;
e315cd28 1021 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 1022 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1023 uint32_t cnt, d2;
335a1cc9 1024 uint16_t wd;
b1d46989 1025 static int abts_cnt; /* ISP abort retry counts */
0107109e 1026
0107109e
AV		 1027 spin_lock_irqsave(&ha->hardware_lock, flags);
1028
1029 /* Reset RISC. */
1030 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1031 for (cnt = 0; cnt < 30000; cnt++) {
1032 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
1033 break;
1034
1035 udelay(10);
1036 }
1037
1038 WRT_REG_DWORD(&reg->ctrl_status,
1039 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335a1cc9 1040 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
88c26663 1041
335a1cc9 1042 udelay(100);
88c26663 1043 /* Wait for firmware to complete NVRAM accesses. */
88c26663
AV		 1044 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1045 for (cnt = 10000 ; cnt && d2; cnt--) {
1046 udelay(5);
1047 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1048 barrier();
1049 }
1050
335a1cc9 1051 /* Wait for soft-reset to complete. */
0107109e
AV		 1052 d2 = RD_REG_DWORD(&reg->ctrl_status);
1053 for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) {
1054 udelay(5);
1055 d2 = RD_REG_DWORD(&reg->ctrl_status);
1056 barrier();
1057 }
1058
b1d46989
MI		 1059 /* If required, do an MPI FW reset now */
1060 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
1061 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
1062 if (++abts_cnt < 5) {
1063 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1064 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
1065 } else {
1066 /*
1067 * We exhausted the ISP abort retries. We have to
1068 * set the board offline.
1069 */
1070 abts_cnt = 0;
1071 vha->flags.online = 0;
1072 }
1073 }
1074 }
1075
0107109e
AV		 1076 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
1077 RD_REG_DWORD(&reg->hccr);
1078
1079 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
1080 RD_REG_DWORD(&reg->hccr);
1081
1082 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
1083 RD_REG_DWORD(&reg->hccr);
1084
1085 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1086 for (cnt = 6000000 ; cnt && d2; cnt--) {
1087 udelay(5);
1088 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1089 barrier();
1090 }
1091
1092 spin_unlock_irqrestore(&ha->hardware_lock, flags);
124f85e6
AV		 1093
1094 if (IS_NOPOLLING_TYPE(ha))
1095 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 1096}
1097
4ea2c9c7
JC		 1098static void
1099qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
1100{
1101 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1102
1103 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1104 *data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);
1105
1106}
1107
1108static void
1109qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
1110{
1111 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1112
1113 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1114 WRT_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
1115}
1116
1117static void
1118qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
1119{
1120 struct qla_hw_data *ha = vha->hw;
1121 uint32_t wd32 = 0;
1122 uint delta_msec = 100;
1123 uint elapsed_msec = 0;
1124 uint timeout_msec;
1125 ulong n;
1126
1127 if (!IS_QLA25XX(ha) && !IS_QLA2031(ha))
1128 return;
1129
1130attempt:
1131 timeout_msec = TIMEOUT_SEMAPHORE;
1132 n = timeout_msec / delta_msec;
1133 while (n--) {
1134 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
1135 qla25xx_read_risc_sema_reg(vha, &wd32);
1136 if (wd32 & RISC_SEMAPHORE)
1137 break;
1138 msleep(delta_msec);
1139 elapsed_msec += delta_msec;
1140 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1141 goto force;
1142 }
1143
1144 if (!(wd32 & RISC_SEMAPHORE))
1145 goto force;
1146
1147 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1148 goto acquired;
1149
1150 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
1151 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
1152 n = timeout_msec / delta_msec;
1153 while (n--) {
1154 qla25xx_read_risc_sema_reg(vha, &wd32);
1155 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1156 break;
1157 msleep(delta_msec);
1158 elapsed_msec += delta_msec;
1159 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1160 goto force;
1161 }
1162
1163 if (wd32 & RISC_SEMAPHORE_FORCE)
1164 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
1165
1166 goto attempt;
1167
1168force:
1169 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
1170
1171acquired:
1172 return;
1173}
1174
88c26663
AV		 1175/**
1176 * qla24xx_reset_chip() - Reset ISP24xx chip.
1177 * @ha: HA context
1178 *
1179 * Returns 0 on success.
1180 */
1181void
e315cd28 1182qla24xx_reset_chip(scsi_qla_host_t *vha)
88c26663 1183{
e315cd28 1184 struct qla_hw_data *ha = vha->hw;
85880801
AV		 1185
1186 if (pci_channel_offline(ha->pdev) &&
1187 ha->flags.pci_channel_io_perm_failure) {
1188 return;
1189 }
1190
fd34f556 1191 ha->isp_ops->disable_intrs(ha);
88c26663 1192
4ea2c9c7
JC		 1193 qla25xx_manipulate_risc_semaphore(vha);
1194
88c26663 1195 /* Perform RISC reset. */
e315cd28 1196 qla24xx_reset_risc(vha);
88c26663
AV		 1197}
1198
1da177e4
LT		 1199/**
1200 * qla2x00_chip_diag() - Test chip for proper operation.
1201 * @ha: HA context
1202 *
1203 * Returns 0 on success.
1204 */
abbd8870 1205int
e315cd28 1206qla2x00_chip_diag(scsi_qla_host_t *vha)
1da177e4
LT		 1207{
1208 int rval;
e315cd28 1209 struct qla_hw_data *ha = vha->hw;
3d71644c 1210 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 1211 unsigned long flags = 0;
1212 uint16_t data;
1213 uint32_t cnt;
1214 uint16_t mb[5];
73208dfd 1215 struct req_que *req = ha->req_q_map[0];
1da177e4
LT		 1216
1217 /* Assume a failed state */
1218 rval = QLA_FUNCTION_FAILED;
1219
7c3df132
SK		 1220 ql_dbg(ql_dbg_init, vha, 0x007b,
1221 "Testing device at %lx.\n", (u_long)&reg->flash_address);
1da177e4
LT		 1222
1223 spin_lock_irqsave(&ha->hardware_lock, flags);
1224
1225 /* Reset ISP chip. */
1226 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1227
1228 /*
1229 * We need to have a delay here since the card will not respond while
1230 * in reset causing an MCA on some architectures.
1231 */
1232 udelay(20);
1233 data = qla2x00_debounce_register(&reg->ctrl_status);
1234 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
1235 udelay(5);
1236 data = RD_REG_WORD(&reg->ctrl_status);
1237 barrier();
1238 }
1239
1240 if (!cnt)
1241 goto chip_diag_failed;
1242
7c3df132
SK		 1243 ql_dbg(ql_dbg_init, vha, 0x007c,
1244 "Reset register cleared by chip reset.\n");
1da177e4
LT		 1245
1246 /* Reset RISC processor. */
1247 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1248 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1249
1250 /* Workaround for QLA2312 PCI parity error */
1251 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1252 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
1253 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
1254 udelay(5);
1255 data = RD_MAILBOX_REG(ha, reg, 0);
fa2a1ce5 1256 barrier();
1da177e4
LT		 1257 }
1258 } else
1259 udelay(10);
1260
1261 if (!cnt)
1262 goto chip_diag_failed;
1263
1264 /* Check product ID of chip */
7c3df132 1265 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
1da177e4
LT		 1266
1267 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
1268 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
1269 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
1270 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
1271 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
1272 mb[3] != PROD_ID_3) {
7c3df132
SK		 1273 ql_log(ql_log_warn, vha, 0x0062,
1274 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
1275 mb[1], mb[2], mb[3]);
1da177e4
LT		 1276
1277 goto chip_diag_failed;
1278 }
1279 ha->product_id[0] = mb[1];
1280 ha->product_id[1] = mb[2];
1281 ha->product_id[2] = mb[3];
1282 ha->product_id[3] = mb[4];
1283
1284 /* Adjust fw RISC transfer size */
73208dfd 1285 if (req->length > 1024)
1da177e4
LT		 1286 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
1287 else
1288 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
73208dfd 1289 req->length;
1da177e4
LT		 1290
1291 if (IS_QLA2200(ha) &&
1292 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
1293 /* Limit firmware transfer size with a 2200A */
7c3df132 1294 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1da177e4 1295
ea5b6382 1296 ha->device_type |= DT_ISP2200A;
1da177e4
LT		 1297 ha->fw_transfer_size = 128;
1298 }
1299
1300 /* Wrap Incoming Mailboxes Test. */
1301 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1302
7c3df132 1303 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
e315cd28 1304 rval = qla2x00_mbx_reg_test(vha);
7c3df132
SK		 1305 if (rval)
1306 ql_log(ql_log_warn, vha, 0x0080,
1307 "Failed mailbox send register test.\n");
1308 else
1da177e4
LT		 1309 /* Flag a successful rval */
1310 rval = QLA_SUCCESS;
1da177e4
LT		 1311 spin_lock_irqsave(&ha->hardware_lock, flags);
1312
1313chip_diag_failed:
1314 if (rval)
7c3df132
SK		 1315 ql_log(ql_log_info, vha, 0x0081,
1316 "Chip diagnostics **** FAILED ****.\n");
1da177e4
LT		 1317
1318 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1319
1320 return (rval);
1321}
1322
0107109e
AV		 1323/**
1324 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
1325 * @ha: HA context
1326 *
1327 * Returns 0 on success.
1328 */
1329int
e315cd28 1330qla24xx_chip_diag(scsi_qla_host_t *vha)
0107109e
AV		 1331{
1332 int rval;
e315cd28 1333 struct qla_hw_data *ha = vha->hw;
73208dfd 1334 struct req_que *req = ha->req_q_map[0];
0107109e 1335
a9083016
GM		 1336 if (IS_QLA82XX(ha))
1337 return QLA_SUCCESS;
1338
73208dfd 1339 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
0107109e 1340
e315cd28 1341 rval = qla2x00_mbx_reg_test(vha);
0107109e 1342 if (rval) {
7c3df132
SK		 1343 ql_log(ql_log_warn, vha, 0x0082,
1344 "Failed mailbox send register test.\n");
0107109e
AV		 1345 } else {
1346 /* Flag a successful rval */
1347 rval = QLA_SUCCESS;
1348 }
1349
1350 return rval;
1351}
1352
a7a167bf 1353void
e315cd28 1354qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
0107109e 1355{
a7a167bf
AV		 1356 int rval;
1357 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
73208dfd 1358 eft_size, fce_size, mq_size;
df613b96
AV		 1359 dma_addr_t tc_dma;
1360 void *tc;
e315cd28 1361 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 1362 struct req_que *req = ha->req_q_map[0];
1363 struct rsp_que *rsp = ha->rsp_q_map[0];
a7a167bf
AV		 1364
1365 if (ha->fw_dump) {
7c3df132
SK		 1366 ql_dbg(ql_dbg_init, vha, 0x00bd,
1367 "Firmware dump already allocated.\n");
a7a167bf
AV		 1368 return;
1369 }
d4e3e04d 1370
0107109e 1371 ha->fw_dumped = 0;
73208dfd 1372 fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
d4e3e04d 1373 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
a7a167bf 1374 fixed_size = sizeof(struct qla2100_fw_dump);
d4e3e04d 1375 } else if (IS_QLA23XX(ha)) {
a7a167bf
AV		 1376 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
1377 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
1378 sizeof(uint16_t);
e428924c 1379 } else if (IS_FWI2_CAPABLE(ha)) {
6246b8a1
GM		 1380 if (IS_QLA83XX(ha))
1381 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
1382 else if (IS_QLA81XX(ha))
3a03eb79
AV		 1383 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
1384 else if (IS_QLA25XX(ha))
1385 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
1386 else
1387 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
a7a167bf
AV		 1388 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
1389 sizeof(uint32_t);
050c9bb1 1390 if (ha->mqenable) {
6246b8a1
GM		 1391 if (!IS_QLA83XX(ha))
1392 mq_size = sizeof(struct qla2xxx_mq_chain);
050c9bb1
GM		 1393 /*
1394 * Allocate maximum buffer size for all queues.
1395 * Resizing must be done at end-of-dump processing.
1396 */
1397 mq_size += ha->max_req_queues *
1398 (req->length * sizeof(request_t));
1399 mq_size += ha->max_rsp_queues *
1400 (rsp->length * sizeof(response_t));
1401 }
2d70c103
NB		 1402 if (ha->tgt.atio_q_length)
1403 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
df613b96 1404 /* Allocate memory for Fibre Channel Event Buffer. */
6246b8a1 1405 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha))
436a7b11 1406 goto try_eft;
df613b96
AV		 1407
1408 tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
1409 GFP_KERNEL);
1410 if (!tc) {
7c3df132
SK		 1411 ql_log(ql_log_warn, vha, 0x00be,
1412 "Unable to allocate (%d KB) for FCE.\n",
1413 FCE_SIZE / 1024);
17d98630 1414 goto try_eft;
df613b96
AV		 1415 }
1416
1417 memset(tc, 0, FCE_SIZE);
e315cd28 1418 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
df613b96
AV		 1419 ha->fce_mb, &ha->fce_bufs);
1420 if (rval) {
7c3df132
SK		 1421 ql_log(ql_log_warn, vha, 0x00bf,
1422 "Unable to initialize FCE (%d).\n", rval);
df613b96
AV		 1423 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
1424 tc_dma);
1425 ha->flags.fce_enabled = 0;
17d98630 1426 goto try_eft;
df613b96 1427 }
cfb0919c 1428 ql_dbg(ql_dbg_init, vha, 0x00c0,
7c3df132 1429 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
df613b96 1430
7d9dade3 1431 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
df613b96
AV		 1432 ha->flags.fce_enabled = 1;
1433 ha->fce_dma = tc_dma;
1434 ha->fce = tc;
436a7b11
AV		 1435try_eft:
1436 /* Allocate memory for Extended Trace Buffer. */
1437 tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
1438 GFP_KERNEL);
1439 if (!tc) {
7c3df132
SK		 1440 ql_log(ql_log_warn, vha, 0x00c1,
1441 "Unable to allocate (%d KB) for EFT.\n",
1442 EFT_SIZE / 1024);
436a7b11
AV		 1443 goto cont_alloc;
1444 }
1445
1446 memset(tc, 0, EFT_SIZE);
e315cd28 1447 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
436a7b11 1448 if (rval) {
7c3df132
SK		 1449 ql_log(ql_log_warn, vha, 0x00c2,
1450 "Unable to initialize EFT (%d).\n", rval);
436a7b11
AV		 1451 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
1452 tc_dma);
1453 goto cont_alloc;
1454 }
cfb0919c 1455 ql_dbg(ql_dbg_init, vha, 0x00c3,
7c3df132 1456 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
436a7b11
AV		 1457
1458 eft_size = EFT_SIZE;
1459 ha->eft_dma = tc_dma;
1460 ha->eft = tc;
d4e3e04d 1461 }
a7a167bf 1462cont_alloc:
73208dfd
AC		 1463 req_q_size = req->length * sizeof(request_t);
1464 rsp_q_size = rsp->length * sizeof(response_t);
a7a167bf
AV		 1465
1466 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
2afa19a9 1467 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
bb99de67
AV		 1468 ha->chain_offset = dump_size;
1469 dump_size += mq_size + fce_size;
d4e3e04d
AV		 1470
1471 ha->fw_dump = vmalloc(dump_size);
a7a167bf 1472 if (!ha->fw_dump) {
7c3df132
SK		 1473 ql_log(ql_log_warn, vha, 0x00c4,
1474 "Unable to allocate (%d KB) for firmware dump.\n",
1475 dump_size / 1024);
a7a167bf 1476
e30d1756
MI		 1477 if (ha->fce) {
1478 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
1479 ha->fce_dma);
1480 ha->fce = NULL;
1481 ha->fce_dma = 0;
1482 }
1483
a7a167bf
AV		 1484 if (ha->eft) {
1485 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
1486 ha->eft_dma);
1487 ha->eft = NULL;
1488 ha->eft_dma = 0;
1489 }
1490 return;
1491 }
cfb0919c 1492 ql_dbg(ql_dbg_init, vha, 0x00c5,
7c3df132 1493 "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
a7a167bf
AV		 1494
1495 ha->fw_dump_len = dump_size;
1496 ha->fw_dump->signature[0] = 'Q';
1497 ha->fw_dump->signature[1] = 'L';
1498 ha->fw_dump->signature[2] = 'G';
1499 ha->fw_dump->signature[3] = 'C';
1500 ha->fw_dump->version = __constant_htonl(1);
1501
1502 ha->fw_dump->fixed_size = htonl(fixed_size);
1503 ha->fw_dump->mem_size = htonl(mem_size);
1504 ha->fw_dump->req_q_size = htonl(req_q_size);
1505 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
1506
1507 ha->fw_dump->eft_size = htonl(eft_size);
1508 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
1509 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
1510
1511 ha->fw_dump->header_size =
1512 htonl(offsetof(struct qla2xxx_fw_dump, isp));
0107109e
AV		 1513}
1514
18e7555a
AV		 1515static int
1516qla81xx_mpi_sync(scsi_qla_host_t *vha)
1517{
1518#define MPS_MASK 0xe0
1519 int rval;
1520 uint16_t dc;
1521 uint32_t dw;
18e7555a
AV		 1522
1523 if (!IS_QLA81XX(vha->hw))
1524 return QLA_SUCCESS;
1525
1526 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
1527 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1528 ql_log(ql_log_warn, vha, 0x0105,
1529 "Unable to acquire semaphore.\n");
18e7555a
AV		 1530 goto done;
1531 }
1532
1533 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
1534 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
1535 if (rval != QLA_SUCCESS) {
7c3df132 1536 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
18e7555a
AV		 1537 goto done_release;
1538 }
1539
1540 dc &= MPS_MASK;
1541 if (dc == (dw & MPS_MASK))
1542 goto done_release;
1543
1544 dw &= ~MPS_MASK;
1545 dw |= dc;
1546 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
1547 if (rval != QLA_SUCCESS) {
7c3df132 1548 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
18e7555a
AV		 1549 }
1550
1551done_release:
1552 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
1553 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1554 ql_log(ql_log_warn, vha, 0x006d,
1555 "Unable to release semaphore.\n");
18e7555a
AV		 1556 }
1557
1558done:
1559 return rval;
1560}
1561
1da177e4
LT		 1562/**
1563 * qla2x00_setup_chip() - Load and start RISC firmware.
1564 * @ha: HA context
1565 *
1566 * Returns 0 on success.
1567 */
1568static int
e315cd28 1569qla2x00_setup_chip(scsi_qla_host_t *vha)
1da177e4 1570{
0107109e
AV		 1571 int rval;
1572 uint32_t srisc_address = 0;
e315cd28 1573 struct qla_hw_data *ha = vha->hw;
3db0652e
AV		 1574 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1575 unsigned long flags;
dda772e8 1576 uint16_t fw_major_version;
3db0652e 1577
a9083016
GM		 1578 if (IS_QLA82XX(ha)) {
1579 rval = ha->isp_ops->load_risc(vha, &srisc_address);
14e303d9
AV		 1580 if (rval == QLA_SUCCESS) {
1581 qla2x00_stop_firmware(vha);
a9083016 1582 goto enable_82xx_npiv;
14e303d9 1583 } else
b963752f 1584 goto failed;
a9083016
GM		 1585 }
1586
3db0652e
AV		 1587 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1588 /* Disable SRAM, Instruction RAM and GP RAM parity. */
1589 spin_lock_irqsave(&ha->hardware_lock, flags);
1590 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
1591 RD_REG_WORD(&reg->hccr);
1592 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1593 }
1da177e4 1594
18e7555a
AV		 1595 qla81xx_mpi_sync(vha);
1596
1da177e4 1597 /* Load firmware sequences */
e315cd28 1598 rval = ha->isp_ops->load_risc(vha, &srisc_address);
0107109e 1599 if (rval == QLA_SUCCESS) {
7c3df132
SK		 1600 ql_dbg(ql_dbg_init, vha, 0x00c9,
1601 "Verifying Checksum of loaded RISC code.\n");
1da177e4 1602
e315cd28 1603 rval = qla2x00_verify_checksum(vha, srisc_address);
1da177e4
LT		 1604 if (rval == QLA_SUCCESS) {
1605 /* Start firmware execution. */
7c3df132
SK		 1606 ql_dbg(ql_dbg_init, vha, 0x00ca,
1607 "Starting firmware.\n");
1da177e4 1608
e315cd28 1609 rval = qla2x00_execute_fw(vha, srisc_address);
1da177e4 1610 /* Retrieve firmware information. */
dda772e8 1611 if (rval == QLA_SUCCESS) {
a9083016 1612enable_82xx_npiv:
dda772e8 1613 fw_major_version = ha->fw_major_version;
3173167f
GM		 1614 if (IS_QLA82XX(ha))
1615 qla82xx_check_md_needed(vha);
6246b8a1
GM		 1616 else
1617 rval = qla2x00_get_fw_version(vha);
ca9e9c3e
AV		 1618 if (rval != QLA_SUCCESS)
1619 goto failed;
2c3dfe3f 1620 ha->flags.npiv_supported = 0;
e315cd28 1621 if (IS_QLA2XXX_MIDTYPE(ha) &&
946fb891 1622 (ha->fw_attributes & BIT_2)) {
2c3dfe3f 1623 ha->flags.npiv_supported = 1;
4d0ea247
SJ		 1624 if ((!ha->max_npiv_vports) ||
1625 ((ha->max_npiv_vports + 1) %
eb66dc60 1626 MIN_MULTI_ID_FABRIC))
4d0ea247 1627 ha->max_npiv_vports =
eb66dc60 1628 MIN_MULTI_ID_FABRIC - 1;
4d0ea247 1629 }
24a08138
AV		 1630 qla2x00_get_resource_cnts(vha, NULL,
1631 &ha->fw_xcb_count, NULL, NULL,
f3a0a77e 1632 &ha->max_npiv_vports, NULL);
d743de66 1633
be5ea3cf
SK		 1634 if (!fw_major_version && ql2xallocfwdump
1635 && !IS_QLA82XX(ha))
08de2844 1636 qla2x00_alloc_fw_dump(vha);
1da177e4
LT		 1637 }
1638 } else {
7c3df132
SK		 1639 ql_log(ql_log_fatal, vha, 0x00cd,
1640 "ISP Firmware failed checksum.\n");
1641 goto failed;
1da177e4 1642 }
c74d88a4
AV		 1643 } else
1644 goto failed;
1da177e4 1645
3db0652e
AV		 1646 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1647 /* Enable proper parity. */
1648 spin_lock_irqsave(&ha->hardware_lock, flags);
1649 if (IS_QLA2300(ha))
1650 /* SRAM parity */
1651 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
1652 else
1653 /* SRAM, Instruction RAM and GP RAM parity */
1654 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
1655 RD_REG_WORD(&reg->hccr);
1656 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1657 }
1658
6246b8a1
GM		 1659 if (IS_QLA83XX(ha))
1660 goto skip_fac_check;
1661
1d2874de
JC		 1662 if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1663 uint32_t size;
1664
1665 rval = qla81xx_fac_get_sector_size(vha, &size);
1666 if (rval == QLA_SUCCESS) {
1667 ha->flags.fac_supported = 1;
1668 ha->fdt_block_size = size << 2;
1669 } else {
7c3df132 1670 ql_log(ql_log_warn, vha, 0x00ce,
1d2874de
JC		 1671 "Unsupported FAC firmware (%d.%02d.%02d).\n",
1672 ha->fw_major_version, ha->fw_minor_version,
1673 ha->fw_subminor_version);
6246b8a1
GM		 1674skip_fac_check:
1675 if (IS_QLA83XX(ha)) {
1676 ha->flags.fac_supported = 0;
1677 rval = QLA_SUCCESS;
1678 }
1d2874de
JC		 1679 }
1680 }
ca9e9c3e 1681failed:
1da177e4 1682 if (rval) {
7c3df132
SK		 1683 ql_log(ql_log_fatal, vha, 0x00cf,
1684 "Setup chip ****FAILED****.\n");
1da177e4
LT		 1685 }
1686
1687 return (rval);
1688}
1689
1690/**
1691 * qla2x00_init_response_q_entries() - Initializes response queue entries.
1692 * @ha: HA context
1693 *
1694 * Beginning of request ring has initialization control block already built
1695 * by nvram config routine.
1696 *
1697 * Returns 0 on success.
1698 */
73208dfd
AC		 1699void
1700qla2x00_init_response_q_entries(struct rsp_que *rsp)
1da177e4
LT		 1701{
1702 uint16_t cnt;
1703 response_t *pkt;
1704
2afa19a9
AC		 1705 rsp->ring_ptr = rsp->ring;
1706 rsp->ring_index = 0;
1707 rsp->status_srb = NULL;
e315cd28
AC		 1708 pkt = rsp->ring_ptr;
1709 for (cnt = 0; cnt < rsp->length; cnt++) {
1da177e4
LT		 1710 pkt->signature = RESPONSE_PROCESSED;
1711 pkt++;
1712 }
1da177e4
LT		 1713}
1714
1715/**
1716 * qla2x00_update_fw_options() - Read and process firmware options.
1717 * @ha: HA context
1718 *
1719 * Returns 0 on success.
1720 */
abbd8870 1721void
e315cd28 1722qla2x00_update_fw_options(scsi_qla_host_t *vha)
1da177e4
LT		 1723{
1724 uint16_t swing, emphasis, tx_sens, rx_sens;
e315cd28 1725 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 1726
1727 memset(ha->fw_options, 0, sizeof(ha->fw_options));
e315cd28 1728 qla2x00_get_fw_options(vha, ha->fw_options);
1da177e4
LT		 1729
1730 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1731 return;
1732
1733 /* Serial Link options. */
7c3df132
SK		 1734 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
1735 "Serial link options.\n");
1736 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
1737 (uint8_t *)&ha->fw_seriallink_options,
1738 sizeof(ha->fw_seriallink_options));
1da177e4
LT		 1739
1740 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1741 if (ha->fw_seriallink_options[3] & BIT_2) {
1742 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
1743
1744 /* 1G settings */
1745 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
1746 emphasis = (ha->fw_seriallink_options[2] &
1747 (BIT_4 | BIT_3)) >> 3;
1748 tx_sens = ha->fw_seriallink_options[0] &
fa2a1ce5 1749 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1750 rx_sens = (ha->fw_seriallink_options[0] &
1751 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1752 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
1753 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1754 if (rx_sens == 0x0)
1755 rx_sens = 0x3;
1756 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
1757 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1758 ha->fw_options[10] |= BIT_5 |
1759 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1760 (tx_sens & (BIT_1 | BIT_0));
1761
1762 /* 2G settings */
1763 swing = (ha->fw_seriallink_options[2] &
1764 (BIT_7 | BIT_6 | BIT_5)) >> 5;
1765 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
1766 tx_sens = ha->fw_seriallink_options[1] &
fa2a1ce5 1767 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1768 rx_sens = (ha->fw_seriallink_options[1] &
1769 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1770 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
1771 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1772 if (rx_sens == 0x0)
1773 rx_sens = 0x3;
1774 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
1775 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1776 ha->fw_options[11] |= BIT_5 |
1777 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1778 (tx_sens & (BIT_1 | BIT_0));
1779 }
1780
1781 /* FCP2 options. */
1782 /* Return command IOCBs without waiting for an ABTS to complete. */
1783 ha->fw_options[3] |= BIT_13;
1784
1785 /* LED scheme. */
1786 if (ha->flags.enable_led_scheme)
1787 ha->fw_options[2] |= BIT_12;
1788
48c02fde 1789 /* Detect ISP6312. */
1790 if (IS_QLA6312(ha))
1791 ha->fw_options[2] |= BIT_13;
1792
1da177e4 1793 /* Update firmware options. */
e315cd28 1794 qla2x00_set_fw_options(vha, ha->fw_options);
1da177e4
LT		 1795}
1796
0107109e 1797void
e315cd28 1798qla24xx_update_fw_options(scsi_qla_host_t *vha)
0107109e
AV		 1799{
1800 int rval;
e315cd28 1801 struct qla_hw_data *ha = vha->hw;
0107109e 1802
a9083016
GM		 1803 if (IS_QLA82XX(ha))
1804 return;
1805
0107109e 1806 /* Update Serial Link options. */
f94097ed 1807 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
0107109e
AV		 1808 return;
1809
e315cd28 1810 rval = qla2x00_set_serdes_params(vha,
f94097ed 1811 le16_to_cpu(ha->fw_seriallink_options24[1]),
1812 le16_to_cpu(ha->fw_seriallink_options24[2]),
1813 le16_to_cpu(ha->fw_seriallink_options24[3]));
0107109e 1814 if (rval != QLA_SUCCESS) {
7c3df132 1815 ql_log(ql_log_warn, vha, 0x0104,
0107109e
AV		 1816 "Unable to update Serial Link options (%x).\n", rval);
1817 }
1818}
1819
abbd8870 1820void
e315cd28 1821qla2x00_config_rings(struct scsi_qla_host *vha)
abbd8870 1822{
e315cd28 1823 struct qla_hw_data *ha = vha->hw;
3d71644c 1824 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
73208dfd
AC		 1825 struct req_que *req = ha->req_q_map[0];
1826 struct rsp_que *rsp = ha->rsp_q_map[0];
abbd8870
AV		 1827
1828 /* Setup ring parameters in initialization control block. */
1829 ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0);
1830 ha->init_cb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 1831 ha->init_cb->request_q_length = cpu_to_le16(req->length);
1832 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
1833 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1834 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1835 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1836 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
abbd8870
AV		 1837
1838 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
1839 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
1840 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
1841 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
1842 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
1843}
1844
0107109e 1845void
e315cd28 1846qla24xx_config_rings(struct scsi_qla_host *vha)
0107109e 1847{
e315cd28 1848 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 1849 device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0);
1850 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
1851 struct qla_msix_entry *msix;
0107109e 1852 struct init_cb_24xx *icb;
73208dfd
AC		 1853 uint16_t rid = 0;
1854 struct req_que *req = ha->req_q_map[0];
1855 struct rsp_que *rsp = ha->rsp_q_map[0];
0107109e 1856
6246b8a1 1857 /* Setup ring parameters in initialization control block. */
0107109e
AV		 1858 icb = (struct init_cb_24xx *)ha->init_cb;
1859 icb->request_q_outpointer = __constant_cpu_to_le16(0);
1860 icb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 1861 icb->request_q_length = cpu_to_le16(req->length);
1862 icb->response_q_length = cpu_to_le16(rsp->length);
1863 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1864 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1865 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1866 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
0107109e 1867
2d70c103
NB		 1868 /* Setup ATIO queue dma pointers for target mode */
1869 icb->atio_q_inpointer = __constant_cpu_to_le16(0);
1870 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
1871 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
1872 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
1873
6246b8a1 1874 if (ha->mqenable || IS_QLA83XX(ha)) {
73208dfd
AC		 1875 icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS);
1876 icb->rid = __constant_cpu_to_le16(rid);
1877 if (ha->flags.msix_enabled) {
1878 msix = &ha->msix_entries[1];
7c3df132
SK		 1879 ql_dbg(ql_dbg_init, vha, 0x00fd,
1880 "Registering vector 0x%x for base que.\n",
1881 msix->entry);
73208dfd
AC		 1882 icb->msix = cpu_to_le16(msix->entry);
1883 }
1884 /* Use alternate PCI bus number */
1885 if (MSB(rid))
1886 icb->firmware_options_2 |=
1887 __constant_cpu_to_le32(BIT_19);
1888 /* Use alternate PCI devfn */
1889 if (LSB(rid))
1890 icb->firmware_options_2 |=
1891 __constant_cpu_to_le32(BIT_18);
1892
3155754a 1893 /* Use Disable MSIX Handshake mode for capable adapters */
6246b8a1
GM		 1894 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
1895 (ha->flags.msix_enabled)) {
3155754a
AC		 1896 icb->firmware_options_2 &=
1897 __constant_cpu_to_le32(~BIT_22);
1898 ha->flags.disable_msix_handshake = 1;
7c3df132
SK		 1899 ql_dbg(ql_dbg_init, vha, 0x00fe,
1900 "MSIX Handshake Disable Mode turned on.\n");
3155754a
AC		 1901 } else {
1902 icb->firmware_options_2 |=
1903 __constant_cpu_to_le32(BIT_22);
1904 }
73208dfd 1905 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_23);
73208dfd
AC		 1906
1907 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
1908 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
1909 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
1910 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
1911 } else {
1912 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
1913 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
1914 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
1915 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
1916 }
2d70c103
NB		 1917 qlt_24xx_config_rings(vha, reg);
1918
73208dfd
AC		 1919 /* PCI posting */
1920 RD_REG_DWORD(&ioreg->hccr);
0107109e
AV		 1921}
1922
1da177e4
LT		 1923/**
1924 * qla2x00_init_rings() - Initializes firmware.
1925 * @ha: HA context
1926 *
1927 * Beginning of request ring has initialization control block already built
1928 * by nvram config routine.
1929 *
1930 * Returns 0 on success.
1931 */
1932static int
e315cd28 1933qla2x00_init_rings(scsi_qla_host_t *vha)
1da177e4
LT		 1934{
1935 int rval;
1936 unsigned long flags = 0;
29bdccbe 1937 int cnt, que;
e315cd28 1938 struct qla_hw_data *ha = vha->hw;
29bdccbe
AC		 1939 struct req_que *req;
1940 struct rsp_que *rsp;
2c3dfe3f
SJ		 1941 struct mid_init_cb_24xx *mid_init_cb =
1942 (struct mid_init_cb_24xx *) ha->init_cb;
1da177e4
LT		 1943
1944 spin_lock_irqsave(&ha->hardware_lock, flags);
1945
1946 /* Clear outstanding commands array. */
2afa19a9 1947 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe
AC		 1948 req = ha->req_q_map[que];
1949 if (!req)
1950 continue;
2afa19a9 1951 for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++)
29bdccbe 1952 req->outstanding_cmds[cnt] = NULL;
1da177e4 1953
2afa19a9 1954 req->current_outstanding_cmd = 1;
1da177e4 1955
29bdccbe
AC		 1956 /* Initialize firmware. */
1957 req->ring_ptr = req->ring;
1958 req->ring_index = 0;
1959 req->cnt = req->length;
1960 }
1da177e4 1961
2afa19a9 1962 for (que = 0; que < ha->max_rsp_queues; que++) {
29bdccbe
AC		 1963 rsp = ha->rsp_q_map[que];
1964 if (!rsp)
1965 continue;
29bdccbe
AC		 1966 /* Initialize response queue entries */
1967 qla2x00_init_response_q_entries(rsp);
1968 }
1da177e4 1969
2d70c103
NB		 1970 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
1971 ha->tgt.atio_ring_index = 0;
1972 /* Initialize ATIO queue entries */
1973 qlt_init_atio_q_entries(vha);
1974
e315cd28 1975 ha->isp_ops->config_rings(vha);
1da177e4
LT		 1976
1977 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1978
1979 /* Update any ISP specific firmware options before initialization. */
e315cd28 1980 ha->isp_ops->update_fw_options(vha);
1da177e4 1981
7c3df132 1982 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
2c3dfe3f 1983
605aa2bc 1984 if (ha->flags.npiv_supported) {
45980cc2 1985 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
605aa2bc 1986 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
c48339de 1987 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
605aa2bc
LC		 1988 }
1989
24a08138
AV		 1990 if (IS_FWI2_CAPABLE(ha)) {
1991 mid_init_cb->options = __constant_cpu_to_le16(BIT_1);
1992 mid_init_cb->init_cb.execution_throttle =
1993 cpu_to_le16(ha->fw_xcb_count);
1994 }
2c3dfe3f 1995
e315cd28 1996 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
1da177e4 1997 if (rval) {
7c3df132
SK		 1998 ql_log(ql_log_fatal, vha, 0x00d2,
1999 "Init Firmware **** FAILED ****.\n");
1da177e4 2000 } else {
7c3df132
SK		 2001 ql_dbg(ql_dbg_init, vha, 0x00d3,
2002 "Init Firmware -- success.\n");
1da177e4
LT		 2003 }
2004
2005 return (rval);
2006}
2007
2008/**
2009 * qla2x00_fw_ready() - Waits for firmware ready.
2010 * @ha: HA context
2011 *
2012 * Returns 0 on success.
2013 */
2014static int
e315cd28 2015qla2x00_fw_ready(scsi_qla_host_t *vha)
1da177e4
LT		 2016{
2017 int rval;
4d4df193 2018 unsigned long wtime, mtime, cs84xx_time;
1da177e4
LT		 2019 uint16_t min_wait; /* Minimum wait time if loop is down */
2020 uint16_t wait_time; /* Wait time if loop is coming ready */
656e8912 2021 uint16_t state[5];
e315cd28 2022 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2023
2024 rval = QLA_SUCCESS;
2025
2026 /* 20 seconds for loop down. */
fa2a1ce5 2027 min_wait = 20;
1da177e4
LT		 2028
2029 /*
2030 * Firmware should take at most one RATOV to login, plus 5 seconds for
2031 * our own processing.
2032 */
2033 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
2034 wait_time = min_wait;
2035 }
2036
2037 /* Min wait time if loop down */
2038 mtime = jiffies + (min_wait * HZ);
2039
2040 /* wait time before firmware ready */
2041 wtime = jiffies + (wait_time * HZ);
2042
2043 /* Wait for ISP to finish LIP */
e315cd28 2044 if (!vha->flags.init_done)
7c3df132
SK		 2045 ql_log(ql_log_info, vha, 0x801e,
2046 "Waiting for LIP to complete.\n");
1da177e4
LT		 2047
2048 do {
5b939038 2049 memset(state, -1, sizeof(state));
e315cd28 2050 rval = qla2x00_get_firmware_state(vha, state);
1da177e4 2051 if (rval == QLA_SUCCESS) {
4d4df193 2052 if (state[0] < FSTATE_LOSS_OF_SYNC) {
e315cd28 2053 vha->device_flags &= ~DFLG_NO_CABLE;
1da177e4 2054 }
4d4df193 2055 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
7c3df132
SK		 2056 ql_dbg(ql_dbg_taskm, vha, 0x801f,
2057 "fw_state=%x 84xx=%x.\n", state[0],
2058 state[2]);
4d4df193
HK		 2059 if ((state[2] & FSTATE_LOGGED_IN) &&
2060 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
7c3df132
SK		 2061 ql_dbg(ql_dbg_taskm, vha, 0x8028,
2062 "Sending verify iocb.\n");
4d4df193
HK		 2063
2064 cs84xx_time = jiffies;
e315cd28 2065 rval = qla84xx_init_chip(vha);
7c3df132
SK		 2066 if (rval != QLA_SUCCESS) {
2067 ql_log(ql_log_warn,
cfb0919c 2068 vha, 0x8007,
7c3df132 2069 "Init chip failed.\n");
4d4df193 2070 break;
7c3df132 2071 }
4d4df193
HK		 2072
2073 /* Add time taken to initialize. */
2074 cs84xx_time = jiffies - cs84xx_time;
2075 wtime += cs84xx_time;
2076 mtime += cs84xx_time;
cfb0919c 2077 ql_dbg(ql_dbg_taskm, vha, 0x8008,
7c3df132
SK		 2078 "Increasing wait time by %ld. "
2079 "New time %ld.\n", cs84xx_time,
2080 wtime);
4d4df193
HK		 2081 }
2082 } else if (state[0] == FSTATE_READY) {
7c3df132
SK		 2083 ql_dbg(ql_dbg_taskm, vha, 0x8037,
2084 "F/W Ready - OK.\n");
1da177e4 2085
e315cd28 2086 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1da177e4
LT		 2087 &ha->login_timeout, &ha->r_a_tov);
2088
2089 rval = QLA_SUCCESS;
2090 break;
2091 }
2092
2093 rval = QLA_FUNCTION_FAILED;
2094
e315cd28 2095 if (atomic_read(&vha->loop_down_timer) &&
4d4df193 2096 state[0] != FSTATE_READY) {
1da177e4 2097 /* Loop down. Timeout on min_wait for states
fa2a1ce5
AV		 2098 * other than Wait for Login.
2099 */
1da177e4 2100 if (time_after_eq(jiffies, mtime)) {
7c3df132 2101 ql_log(ql_log_info, vha, 0x8038,
1da177e4
LT		 2102 "Cable is unplugged...\n");
2103
e315cd28 2104 vha->device_flags |= DFLG_NO_CABLE;
1da177e4
LT		 2105 break;
2106 }
2107 }
2108 } else {
2109 /* Mailbox cmd failed. Timeout on min_wait. */
cdbb0a4f 2110 if (time_after_eq(jiffies, mtime) ||
7190575f 2111 ha->flags.isp82xx_fw_hung)
1da177e4
LT		 2112 break;
2113 }
2114
2115 if (time_after_eq(jiffies, wtime))
2116 break;
2117
2118 /* Delay for a while */
2119 msleep(500);
1da177e4
LT		 2120 } while (1);
2121
7c3df132
SK		 2122 ql_dbg(ql_dbg_taskm, vha, 0x803a,
2123 "fw_state=%x (%x, %x, %x, %x) " "curr time=%lx.\n", state[0],
2124 state[1], state[2], state[3], state[4], jiffies);
1da177e4 2125
cfb0919c 2126 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132
SK		 2127 ql_log(ql_log_warn, vha, 0x803b,
2128 "Firmware ready **** FAILED ****.\n");
1da177e4
LT		 2129 }
2130
2131 return (rval);
2132}
2133
2134/*
2135* qla2x00_configure_hba
2136* Setup adapter context.
2137*
2138* Input:
2139* ha = adapter state pointer.
2140*
2141* Returns:
2142* 0 = success
2143*
2144* Context:
2145* Kernel context.
2146*/
2147static int
e315cd28 2148qla2x00_configure_hba(scsi_qla_host_t *vha)
1da177e4
LT		 2149{
2150 int rval;
2151 uint16_t loop_id;
2152 uint16_t topo;
2c3dfe3f 2153 uint16_t sw_cap;
1da177e4
LT		 2154 uint8_t al_pa;
2155 uint8_t area;
2156 uint8_t domain;
2157 char connect_type[22];
e315cd28 2158 struct qla_hw_data *ha = vha->hw;
f24b5cb8 2159 unsigned long flags;
1da177e4
LT		 2160
2161 /* Get host addresses. */
e315cd28 2162 rval = qla2x00_get_adapter_id(vha,
2c3dfe3f 2163 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
1da177e4 2164 if (rval != QLA_SUCCESS) {
e315cd28 2165 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
6246b8a1 2166 IS_CNA_CAPABLE(ha) ||
33135aa2 2167 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
7c3df132
SK		 2168 ql_dbg(ql_dbg_disc, vha, 0x2008,
2169 "Loop is in a transition state.\n");
33135aa2 2170 } else {
7c3df132
SK		 2171 ql_log(ql_log_warn, vha, 0x2009,
2172 "Unable to get host loop ID.\n");
e315cd28 2173 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
33135aa2 2174 }
1da177e4
LT		 2175 return (rval);
2176 }
2177
2178 if (topo == 4) {
7c3df132
SK		 2179 ql_log(ql_log_info, vha, 0x200a,
2180 "Cannot get topology - retrying.\n");
1da177e4
LT		 2181 return (QLA_FUNCTION_FAILED);
2182 }
2183
e315cd28 2184 vha->loop_id = loop_id;
1da177e4
LT		 2185
2186 /* initialize */
2187 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
2188 ha->operating_mode = LOOP;
2c3dfe3f 2189 ha->switch_cap = 0;
1da177e4
LT		 2190
2191 switch (topo) {
2192 case 0:
7c3df132 2193 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
1da177e4
LT		 2194 ha->current_topology = ISP_CFG_NL;
2195 strcpy(connect_type, "(Loop)");
2196 break;
2197
2198 case 1:
7c3df132 2199 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2c3dfe3f 2200 ha->switch_cap = sw_cap;
1da177e4
LT		 2201 ha->current_topology = ISP_CFG_FL;
2202 strcpy(connect_type, "(FL_Port)");
2203 break;
2204
2205 case 2:
7c3df132 2206 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
1da177e4
LT		 2207 ha->operating_mode = P2P;
2208 ha->current_topology = ISP_CFG_N;
2209 strcpy(connect_type, "(N_Port-to-N_Port)");
2210 break;
2211
2212 case 3:
7c3df132 2213 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2c3dfe3f 2214 ha->switch_cap = sw_cap;
1da177e4
LT		 2215 ha->operating_mode = P2P;
2216 ha->current_topology = ISP_CFG_F;
2217 strcpy(connect_type, "(F_Port)");
2218 break;
2219
2220 default:
7c3df132
SK		 2221 ql_dbg(ql_dbg_disc, vha, 0x200f,
2222 "HBA in unknown topology %x, using NL.\n", topo);
1da177e4
LT		 2223 ha->current_topology = ISP_CFG_NL;
2224 strcpy(connect_type, "(Loop)");
2225 break;
2226 }
2227
2228 /* Save Host port and loop ID. */
2229 /* byte order - Big Endian */
e315cd28
AC		 2230 vha->d_id.b.domain = domain;
2231 vha->d_id.b.area = area;
2232 vha->d_id.b.al_pa = al_pa;
1da177e4 2233
f24b5cb8 2234 spin_lock_irqsave(&ha->vport_slock, flags);
2d70c103 2235 qlt_update_vp_map(vha, SET_AL_PA);
f24b5cb8 2236 spin_unlock_irqrestore(&ha->vport_slock, flags);
2d70c103 2237
e315cd28 2238 if (!vha->flags.init_done)
7c3df132
SK		 2239 ql_log(ql_log_info, vha, 0x2010,
2240 "Topology - %s, Host Loop address 0x%x.\n",
e315cd28 2241 connect_type, vha->loop_id);
1da177e4
LT		 2242
2243 if (rval) {
7c3df132
SK		 2244 ql_log(ql_log_warn, vha, 0x2011,
2245 "%s FAILED\n", __func__);
1da177e4 2246 } else {
7c3df132
SK		 2247 ql_dbg(ql_dbg_disc, vha, 0x2012,
2248 "%s success\n", __func__);
1da177e4
LT		 2249 }
2250
2251 return(rval);
2252}
2253
a9083016 2254inline void
e315cd28
AC		 2255qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
2256 char *def)
9bb9fcf2
AV		 2257{
2258 char *st, *en;
2259 uint16_t index;
e315cd28 2260 struct qla_hw_data *ha = vha->hw;
ab671149 2261 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
6246b8a1 2262 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
9bb9fcf2
AV		 2263
2264 if (memcmp(model, BINZERO, len) != 0) {
2265 strncpy(ha->model_number, model, len);
2266 st = en = ha->model_number;
2267 en += len - 1;
2268 while (en > st) {
2269 if (*en != 0x20 && *en != 0x00)
2270 break;
2271 *en-- = '\0';
2272 }
2273
2274 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2275 if (use_tbl &&
2276 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 2277 index < QLA_MODEL_NAMES)
1ee27146
JC		 2278 strncpy(ha->model_desc,
2279 qla2x00_model_name[index * 2 + 1],
2280 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2281 } else {
2282 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2283 if (use_tbl &&
2284 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2
AV		 2285 index < QLA_MODEL_NAMES) {
2286 strcpy(ha->model_number,
2287 qla2x00_model_name[index * 2]);
1ee27146
JC		 2288 strncpy(ha->model_desc,
2289 qla2x00_model_name[index * 2 + 1],
2290 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2291 } else {
2292 strcpy(ha->model_number, def);
2293 }
2294 }
1ee27146 2295 if (IS_FWI2_CAPABLE(ha))
e315cd28 2296 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
1ee27146 2297 sizeof(ha->model_desc));
9bb9fcf2
AV		 2298}
2299
4e08df3f
DM		 2300/* On sparc systems, obtain port and node WWN from firmware
2301 * properties.
2302 */
e315cd28 2303static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4e08df3f
DM		 2304{
2305#ifdef CONFIG_SPARC
e315cd28 2306 struct qla_hw_data *ha = vha->hw;
4e08df3f 2307 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 2308 struct device_node *dp = pci_device_to_OF_node(pdev);
2309 const u8 *val;
4e08df3f
DM		 2310 int len;
2311
2312 val = of_get_property(dp, "port-wwn", &len);
2313 if (val && len >= WWN_SIZE)
2314 memcpy(nv->port_name, val, WWN_SIZE);
2315
2316 val = of_get_property(dp, "node-wwn", &len);
2317 if (val && len >= WWN_SIZE)
2318 memcpy(nv->node_name, val, WWN_SIZE);
2319#endif
2320}
2321
1da177e4
LT		 2322/*
2323* NVRAM configuration for ISP 2xxx
2324*
2325* Input:
2326* ha = adapter block pointer.
2327*
2328* Output:
2329* initialization control block in response_ring
2330* host adapters parameters in host adapter block
2331*
2332* Returns:
2333* 0 = success.
2334*/
abbd8870 2335int
e315cd28 2336qla2x00_nvram_config(scsi_qla_host_t *vha)
1da177e4 2337{
4e08df3f 2338 int rval;
0107109e
AV		 2339 uint8_t chksum = 0;
2340 uint16_t cnt;
2341 uint8_t *dptr1, *dptr2;
e315cd28 2342 struct qla_hw_data *ha = vha->hw;
0107109e 2343 init_cb_t *icb = ha->init_cb;
281afe19
SJ		 2344 nvram_t *nv = ha->nvram;
2345 uint8_t *ptr = ha->nvram;
3d71644c 2346 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2347
4e08df3f
DM		 2348 rval = QLA_SUCCESS;
2349
1da177e4 2350 /* Determine NVRAM starting address. */
0107109e 2351 ha->nvram_size = sizeof(nvram_t);
1da177e4
LT		 2352 ha->nvram_base = 0;
2353 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
2354 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
2355 ha->nvram_base = 0x80;
2356
2357 /* Get NVRAM data and calculate checksum. */
e315cd28 2358 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
0107109e
AV		 2359 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
2360 chksum += *ptr++;
1da177e4 2361
7c3df132
SK		 2362 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
2363 "Contents of NVRAM.\n");
2364 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
2365 (uint8_t *)nv, ha->nvram_size);
1da177e4
LT		 2366
2367 /* Bad NVRAM data, set defaults parameters. */
2368 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
2369 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
2370 /* Reset NVRAM data. */
7c3df132 2371 ql_log(ql_log_warn, vha, 0x0064,
9e336520 2372 "Inconsistent NVRAM "
7c3df132
SK		 2373 "detected: checksum=0x%x id=%c version=0x%x.\n",
2374 chksum, nv->id[0], nv->nvram_version);
2375 ql_log(ql_log_warn, vha, 0x0065,
2376 "Falling back to "
2377 "functioning (yet invalid -- WWPN) defaults.\n");
4e08df3f
DM		 2378
2379 /*
2380 * Set default initialization control block.
2381 */
2382 memset(nv, 0, ha->nvram_size);
2383 nv->parameter_block_version = ICB_VERSION;
2384
2385 if (IS_QLA23XX(ha)) {
2386 nv->firmware_options[0] = BIT_2 | BIT_1;
2387 nv->firmware_options[1] = BIT_7 | BIT_5;
2388 nv->add_firmware_options[0] = BIT_5;
2389 nv->add_firmware_options[1] = BIT_5 | BIT_4;
2390 nv->frame_payload_size = __constant_cpu_to_le16(2048);
2391 nv->special_options[1] = BIT_7;
2392 } else if (IS_QLA2200(ha)) {
2393 nv->firmware_options[0] = BIT_2 | BIT_1;
2394 nv->firmware_options[1] = BIT_7 | BIT_5;
2395 nv->add_firmware_options[0] = BIT_5;
2396 nv->add_firmware_options[1] = BIT_5 | BIT_4;
2397 nv->frame_payload_size = __constant_cpu_to_le16(1024);
2398 } else if (IS_QLA2100(ha)) {
2399 nv->firmware_options[0] = BIT_3 | BIT_1;
2400 nv->firmware_options[1] = BIT_5;
2401 nv->frame_payload_size = __constant_cpu_to_le16(1024);
2402 }
2403
2404 nv->max_iocb_allocation = __constant_cpu_to_le16(256);
2405 nv->execution_throttle = __constant_cpu_to_le16(16);
2406 nv->retry_count = 8;
2407 nv->retry_delay = 1;
2408
2409 nv->port_name[0] = 33;
2410 nv->port_name[3] = 224;
2411 nv->port_name[4] = 139;
2412
e315cd28 2413 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 2414
2415 nv->login_timeout = 4;
2416
2417 /*
2418 * Set default host adapter parameters
2419 */
2420 nv->host_p[1] = BIT_2;
2421 nv->reset_delay = 5;
2422 nv->port_down_retry_count = 8;
2423 nv->max_luns_per_target = __constant_cpu_to_le16(8);
2424 nv->link_down_timeout = 60;
2425
2426 rval = 1;
1da177e4
LT		 2427 }
2428
2429#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
2430 /*
2431 * The SN2 does not provide BIOS emulation which means you can't change
2432 * potentially bogus BIOS settings. Force the use of default settings
2433 * for link rate and frame size. Hope that the rest of the settings
2434 * are valid.
2435 */
2436 if (ia64_platform_is("sn2")) {
2437 nv->frame_payload_size = __constant_cpu_to_le16(2048);
2438 if (IS_QLA23XX(ha))
2439 nv->special_options[1] = BIT_7;
2440 }
2441#endif
2442
2443 /* Reset Initialization control block */
0107109e 2444 memset(icb, 0, ha->init_cb_size);
1da177e4
LT		 2445
2446 /*
2447 * Setup driver NVRAM options.
2448 */
2449 nv->firmware_options[0] |= (BIT_6 | BIT_1);
2450 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
2451 nv->firmware_options[1] |= (BIT_5 | BIT_0);
2452 nv->firmware_options[1] &= ~BIT_4;
2453
2454 if (IS_QLA23XX(ha)) {
2455 nv->firmware_options[0] |= BIT_2;
2456 nv->firmware_options[0] &= ~BIT_3;
2d70c103 2457 nv->special_options[0] &= ~BIT_6;
0107109e 2458 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
1da177e4
LT		 2459
2460 if (IS_QLA2300(ha)) {
2461 if (ha->fb_rev == FPM_2310) {
2462 strcpy(ha->model_number, "QLA2310");
2463 } else {
2464 strcpy(ha->model_number, "QLA2300");
2465 }
2466 } else {
e315cd28 2467 qla2x00_set_model_info(vha, nv->model_number,
9bb9fcf2 2468 sizeof(nv->model_number), "QLA23xx");
1da177e4
LT		 2469 }
2470 } else if (IS_QLA2200(ha)) {
2471 nv->firmware_options[0] |= BIT_2;
2472 /*
2473 * 'Point-to-point preferred, else loop' is not a safe
2474 * connection mode setting.
2475 */
2476 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
2477 (BIT_5 | BIT_4)) {
2478 /* Force 'loop preferred, else point-to-point'. */
2479 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
2480 nv->add_firmware_options[0] |= BIT_5;
2481 }
2482 strcpy(ha->model_number, "QLA22xx");
2483 } else /*if (IS_QLA2100(ha))*/ {
2484 strcpy(ha->model_number, "QLA2100");
2485 }
2486
2487 /*
2488 * Copy over NVRAM RISC parameter block to initialization control block.
2489 */
2490 dptr1 = (uint8_t *)icb;
2491 dptr2 = (uint8_t *)&nv->parameter_block_version;
2492 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
2493 while (cnt--)
2494 *dptr1++ = *dptr2++;
2495
2496 /* Copy 2nd half. */
2497 dptr1 = (uint8_t *)icb->add_firmware_options;
2498 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
2499 while (cnt--)
2500 *dptr1++ = *dptr2++;
2501
5341e868
AV		 2502 /* Use alternate WWN? */
2503 if (nv->host_p[1] & BIT_7) {
2504 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
2505 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
2506 }
2507
1da177e4
LT		 2508 /* Prepare nodename */
2509 if ((icb->firmware_options[1] & BIT_6) == 0) {
2510 /*
2511 * Firmware will apply the following mask if the nodename was
2512 * not provided.
2513 */
2514 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
2515 icb->node_name[0] &= 0xF0;
2516 }
2517
2518 /*
2519 * Set host adapter parameters.
2520 */
3ce8866c
SK		 2521
2522 /*
2523 * BIT_7 in the host-parameters section allows for modification to
2524 * internal driver logging.
2525 */
0181944f 2526 if (nv->host_p[0] & BIT_7)
cfb0919c 2527 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1da177e4
LT		 2528 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
2529 /* Always load RISC code on non ISP2[12]00 chips. */
2530 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
2531 ha->flags.disable_risc_code_load = 0;
2532 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
2533 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
2534 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
06c22bd1 2535 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
d4c760c2 2536 ha->flags.disable_serdes = 0;
1da177e4
LT		 2537
2538 ha->operating_mode =
2539 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
2540
2541 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
2542 sizeof(ha->fw_seriallink_options));
2543
2544 /* save HBA serial number */
2545 ha->serial0 = icb->port_name[5];
2546 ha->serial1 = icb->port_name[6];
2547 ha->serial2 = icb->port_name[7];
e315cd28
AC		 2548 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
2549 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
1da177e4
LT		 2550
2551 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
2552
2553 ha->retry_count = nv->retry_count;
2554
2555 /* Set minimum login_timeout to 4 seconds. */
5b91490e 2556 if (nv->login_timeout != ql2xlogintimeout)
1da177e4
LT		 2557 nv->login_timeout = ql2xlogintimeout;
2558 if (nv->login_timeout < 4)
2559 nv->login_timeout = 4;
2560 ha->login_timeout = nv->login_timeout;
2561 icb->login_timeout = nv->login_timeout;
2562
00a537b8
AV		 2563 /* Set minimum RATOV to 100 tenths of a second. */
2564 ha->r_a_tov = 100;
1da177e4 2565
1da177e4
LT		 2566 ha->loop_reset_delay = nv->reset_delay;
2567
1da177e4
LT		 2568 /* Link Down Timeout = 0:
2569 *
2570 * When Port Down timer expires we will start returning
2571 * I/O's to OS with "DID_NO_CONNECT".
2572 *
2573 * Link Down Timeout != 0:
2574 *
2575 * The driver waits for the link to come up after link down
2576 * before returning I/Os to OS with "DID_NO_CONNECT".
fa2a1ce5 2577 */
1da177e4
LT		 2578 if (nv->link_down_timeout == 0) {
2579 ha->loop_down_abort_time =
354d6b21 2580 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
1da177e4
LT		 2581 } else {
2582 ha->link_down_timeout = nv->link_down_timeout;
2583 ha->loop_down_abort_time =
2584 (LOOP_DOWN_TIME - ha->link_down_timeout);
fa2a1ce5 2585 }
1da177e4 2586
1da177e4
LT		 2587 /*
2588 * Need enough time to try and get the port back.
2589 */
2590 ha->port_down_retry_count = nv->port_down_retry_count;
2591 if (qlport_down_retry)
2592 ha->port_down_retry_count = qlport_down_retry;
2593 /* Set login_retry_count */
2594 ha->login_retry_count = nv->retry_count;
2595 if (ha->port_down_retry_count == nv->port_down_retry_count &&
2596 ha->port_down_retry_count > 3)
2597 ha->login_retry_count = ha->port_down_retry_count;
2598 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
2599 ha->login_retry_count = ha->port_down_retry_count;
2600 if (ql2xloginretrycount)
2601 ha->login_retry_count = ql2xloginretrycount;
2602
1da177e4
LT		 2603 icb->lun_enables = __constant_cpu_to_le16(0);
2604 icb->command_resource_count = 0;
2605 icb->immediate_notify_resource_count = 0;
2606 icb->timeout = __constant_cpu_to_le16(0);
2607
2608 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
2609 /* Enable RIO */
2610 icb->firmware_options[0] &= ~BIT_3;
2611 icb->add_firmware_options[0] &=
2612 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
2613 icb->add_firmware_options[0] |= BIT_2;
2614 icb->response_accumulation_timer = 3;
2615 icb->interrupt_delay_timer = 5;
2616
e315cd28 2617 vha->flags.process_response_queue = 1;
1da177e4 2618 } else {
4fdfefe5 2619 /* Enable ZIO. */
e315cd28 2620 if (!vha->flags.init_done) {
4fdfefe5
AV		 2621 ha->zio_mode = icb->add_firmware_options[0] &
2622 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
2623 ha->zio_timer = icb->interrupt_delay_timer ?
2624 icb->interrupt_delay_timer: 2;
2625 }
1da177e4
LT		 2626 icb->add_firmware_options[0] &=
2627 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
e315cd28 2628 vha->flags.process_response_queue = 0;
4fdfefe5 2629 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d 2630 ha->zio_mode = QLA_ZIO_MODE_6;
2631
7c3df132 2632 ql_log(ql_log_info, vha, 0x0068,
4fdfefe5
AV		 2633 "ZIO mode %d enabled; timer delay (%d us).\n",
2634 ha->zio_mode, ha->zio_timer * 100);
1da177e4 2635
4fdfefe5
AV		 2636 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
2637 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
e315cd28 2638 vha->flags.process_response_queue = 1;
1da177e4
LT		 2639 }
2640 }
2641
4e08df3f 2642 if (rval) {
7c3df132
SK		 2643 ql_log(ql_log_warn, vha, 0x0069,
2644 "NVRAM configuration failed.\n");
4e08df3f
DM		 2645 }
2646 return (rval);
1da177e4
LT		 2647}
2648
19a7b4ae
JSEC		 2649static void
2650qla2x00_rport_del(void *data)
2651{
2652 fc_port_t *fcport = data;
d97994dc 2653 struct fc_rport *rport;
2d70c103 2654 scsi_qla_host_t *vha = fcport->vha;
044d78e1 2655 unsigned long flags;
d97994dc 2656
044d78e1 2657 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
ac280b67 2658 rport = fcport->drport ? fcport->drport: fcport->rport;
d97994dc 2659 fcport->drport = NULL;
044d78e1 2660 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
2d70c103 2661 if (rport) {
d97994dc 2662 fc_remote_port_delete(rport);
2d70c103
NB		 2663 /*
2664 * Release the target mode FC NEXUS in qla_target.c code
2665 * if target mod is enabled.
2666 */
2667 qlt_fc_port_deleted(vha, fcport);
2668 }
19a7b4ae
JSEC		 2669}
2670
1da177e4
LT		 2671/**
2672 * qla2x00_alloc_fcport() - Allocate a generic fcport.
2673 * @ha: HA context
2674 * @flags: allocation flags
2675 *
2676 * Returns a pointer to the allocated fcport, or NULL, if none available.
2677 */
9a069e19 2678fc_port_t *
e315cd28 2679qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
1da177e4
LT		 2680{
2681 fc_port_t *fcport;
2682
bbfbbbc1
MK		 2683 fcport = kzalloc(sizeof(fc_port_t), flags);
2684 if (!fcport)
2685 return NULL;
1da177e4
LT		 2686
2687 /* Setup fcport template structure. */
e315cd28 2688 fcport->vha = vha;
1da177e4
LT		 2689 fcport->port_type = FCT_UNKNOWN;
2690 fcport->loop_id = FC_NO_LOOP_ID;
ec426e10 2691 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
ad3e0eda 2692 fcport->supported_classes = FC_COS_UNSPECIFIED;
c0822b63 2693 fcport->scan_state = QLA_FCPORT_SCAN_NONE;
1da177e4 2694
bbfbbbc1 2695 return fcport;
1da177e4
LT		 2696}
2697
2698/*
2699 * qla2x00_configure_loop
2700 * Updates Fibre Channel Device Database with what is actually on loop.
2701 *
2702 * Input:
2703 * ha = adapter block pointer.
2704 *
2705 * Returns:
2706 * 0 = success.
2707 * 1 = error.
2708 * 2 = database was full and device was not configured.
2709 */
2710static int
e315cd28 2711qla2x00_configure_loop(scsi_qla_host_t *vha)
1da177e4
LT		 2712{
2713 int rval;
2714 unsigned long flags, save_flags;
e315cd28 2715 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2716 rval = QLA_SUCCESS;
2717
2718 /* Get Initiator ID */
e315cd28
AC		 2719 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
2720 rval = qla2x00_configure_hba(vha);
1da177e4 2721 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2722 ql_dbg(ql_dbg_disc, vha, 0x2013,
2723 "Unable to configure HBA.\n");
1da177e4
LT		 2724 return (rval);
2725 }
2726 }
2727
e315cd28 2728 save_flags = flags = vha->dpc_flags;
7c3df132
SK		 2729 ql_dbg(ql_dbg_disc, vha, 0x2014,
2730 "Configure loop -- dpc flags = 0x%lx.\n", flags);
1da177e4
LT		 2731
2732 /*
2733 * If we have both an RSCN and PORT UPDATE pending then handle them
2734 * both at the same time.
2735 */
e315cd28
AC		 2736 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2737 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
1da177e4 2738
3064ff39
MH		 2739 qla2x00_get_data_rate(vha);
2740
1da177e4
LT		 2741 /* Determine what we need to do */
2742 if (ha->current_topology == ISP_CFG_FL &&
2743 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2744
1da177e4
LT		 2745 set_bit(RSCN_UPDATE, &flags);
2746
2747 } else if (ha->current_topology == ISP_CFG_F &&
2748 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2749
1da177e4
LT		 2750 set_bit(RSCN_UPDATE, &flags);
2751 clear_bit(LOCAL_LOOP_UPDATE, &flags);
21333b48
AV		 2752
2753 } else if (ha->current_topology == ISP_CFG_N) {
2754 clear_bit(RSCN_UPDATE, &flags);
1da177e4 2755
e315cd28 2756 } else if (!vha->flags.online ||
1da177e4
LT		 2757 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
2758
1da177e4
LT		 2759 set_bit(RSCN_UPDATE, &flags);
2760 set_bit(LOCAL_LOOP_UPDATE, &flags);
2761 }
2762
2763 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
7c3df132
SK		 2764 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
2765 ql_dbg(ql_dbg_disc, vha, 0x2015,
2766 "Loop resync needed, failing.\n");
1da177e4 2767 rval = QLA_FUNCTION_FAILED;
642ef983 2768 } else
e315cd28 2769 rval = qla2x00_configure_local_loop(vha);
1da177e4
LT		 2770 }
2771
2772 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
7c3df132
SK		 2773 if (LOOP_TRANSITION(vha)) {
2774 ql_dbg(ql_dbg_disc, vha, 0x201e,
2775 "Needs RSCN update and loop transition.\n");
1da177e4 2776 rval = QLA_FUNCTION_FAILED;
7c3df132 2777 }
e315cd28
AC		 2778 else
2779 rval = qla2x00_configure_fabric(vha);
1da177e4
LT		 2780 }
2781
2782 if (rval == QLA_SUCCESS) {
e315cd28
AC		 2783 if (atomic_read(&vha->loop_down_timer) ||
2784 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4
LT		 2785 rval = QLA_FUNCTION_FAILED;
2786 } else {
e315cd28 2787 atomic_set(&vha->loop_state, LOOP_READY);
7c3df132
SK		 2788 ql_dbg(ql_dbg_disc, vha, 0x2069,
2789 "LOOP READY.\n");
1da177e4
LT		 2790 }
2791 }
2792
2793 if (rval) {
7c3df132
SK		 2794 ql_dbg(ql_dbg_disc, vha, 0x206a,
2795 "%s *** FAILED ***.\n", __func__);
1da177e4 2796 } else {
7c3df132
SK		 2797 ql_dbg(ql_dbg_disc, vha, 0x206b,
2798 "%s: exiting normally.\n", __func__);
1da177e4
LT		 2799 }
2800
cc3ef7bc 2801 /* Restore state if a resync event occurred during processing */
e315cd28 2802 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4 2803 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
e315cd28 2804 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
f4658b6c 2805 if (test_bit(RSCN_UPDATE, &save_flags)) {
e315cd28 2806 set_bit(RSCN_UPDATE, &vha->dpc_flags);
f4658b6c 2807 }
1da177e4
LT		 2808 }
2809
2810 return (rval);
2811}
2812
2813
2814
2815/*
2816 * qla2x00_configure_local_loop
2817 * Updates Fibre Channel Device Database with local loop devices.
2818 *
2819 * Input:
2820 * ha = adapter block pointer.
2821 *
2822 * Returns:
2823 * 0 = success.
2824 */
2825static int
e315cd28 2826qla2x00_configure_local_loop(scsi_qla_host_t *vha)
1da177e4
LT		 2827{
2828 int rval, rval2;
2829 int found_devs;
2830 int found;
2831 fc_port_t *fcport, *new_fcport;
2832
2833 uint16_t index;
2834 uint16_t entries;
2835 char *id_iter;
2836 uint16_t loop_id;
2837 uint8_t domain, area, al_pa;
e315cd28 2838 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2839
2840 found_devs = 0;
2841 new_fcport = NULL;
642ef983 2842 entries = MAX_FIBRE_DEVICES_LOOP;
1da177e4 2843
1da177e4 2844 /* Get list of logged in devices. */
642ef983 2845 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
e315cd28 2846 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
1da177e4
LT		 2847 &entries);
2848 if (rval != QLA_SUCCESS)
2849 goto cleanup_allocation;
2850
7c3df132
SK		 2851 ql_dbg(ql_dbg_disc, vha, 0x2017,
2852 "Entries in ID list (%d).\n", entries);
2853 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
2854 (uint8_t *)ha->gid_list,
2855 entries * sizeof(struct gid_list_info));
1da177e4
LT		 2856
2857 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 2858 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 2859 if (new_fcport == NULL) {
7c3df132
SK		 2860 ql_log(ql_log_warn, vha, 0x2018,
2861 "Memory allocation failed for fcport.\n");
1da177e4
LT		 2862 rval = QLA_MEMORY_ALLOC_FAILED;
2863 goto cleanup_allocation;
2864 }
2865 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
2866
2867 /*
2868 * Mark local devices that were present with FCF_DEVICE_LOST for now.
2869 */
e315cd28 2870 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 2871 if (atomic_read(&fcport->state) == FCS_ONLINE &&
2872 fcport->port_type != FCT_BROADCAST &&
2873 (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
2874
7c3df132
SK		 2875 ql_dbg(ql_dbg_disc, vha, 0x2019,
2876 "Marking port lost loop_id=0x%04x.\n",
2877 fcport->loop_id);
1da177e4 2878
ec426e10 2879 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 2880 }
2881 }
2882
2883 /* Add devices to port list. */
2884 id_iter = (char *)ha->gid_list;
2885 for (index = 0; index < entries; index++) {
2886 domain = ((struct gid_list_info *)id_iter)->domain;
2887 area = ((struct gid_list_info *)id_iter)->area;
2888 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
abbd8870 2889 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1da177e4
LT		 2890 loop_id = (uint16_t)
2891 ((struct gid_list_info *)id_iter)->loop_id_2100;
abbd8870 2892 else
1da177e4
LT		 2893 loop_id = le16_to_cpu(
2894 ((struct gid_list_info *)id_iter)->loop_id);
abbd8870 2895 id_iter += ha->gid_list_info_size;
1da177e4
LT		 2896
2897 /* Bypass reserved domain fields. */
2898 if ((domain & 0xf0) == 0xf0)
2899 continue;
2900
2901 /* Bypass if not same domain and area of adapter. */
f7d289f6 2902 if (area && domain &&
e315cd28 2903 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
1da177e4
LT		 2904 continue;
2905
2906 /* Bypass invalid local loop ID. */
2907 if (loop_id > LAST_LOCAL_LOOP_ID)
2908 continue;
2909
370d550e
AE		 2910 memset(new_fcport, 0, sizeof(fc_port_t));
2911
1da177e4
LT		 2912 /* Fill in member data. */
2913 new_fcport->d_id.b.domain = domain;
2914 new_fcport->d_id.b.area = area;
2915 new_fcport->d_id.b.al_pa = al_pa;
2916 new_fcport->loop_id = loop_id;
e315cd28 2917 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
1da177e4 2918 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 2919 ql_dbg(ql_dbg_disc, vha, 0x201a,
2920 "Failed to retrieve fcport information "
2921 "-- get_port_database=%x, loop_id=0x%04x.\n",
2922 rval2, new_fcport->loop_id);
2923 ql_dbg(ql_dbg_disc, vha, 0x201b,
2924 "Scheduling resync.\n");
e315cd28 2925 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 2926 continue;
2927 }
2928
2929 /* Check for matching device in port list. */
2930 found = 0;
2931 fcport = NULL;
e315cd28 2932 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 2933 if (memcmp(new_fcport->port_name, fcport->port_name,
2934 WWN_SIZE))
2935 continue;
2936
ddb9b126 2937 fcport->flags &= ~FCF_FABRIC_DEVICE;
1da177e4
LT		 2938 fcport->loop_id = new_fcport->loop_id;
2939 fcport->port_type = new_fcport->port_type;
2940 fcport->d_id.b24 = new_fcport->d_id.b24;
2941 memcpy(fcport->node_name, new_fcport->node_name,
2942 WWN_SIZE);
2943
2944 found++;
2945 break;
2946 }
2947
2948 if (!found) {
2949 /* New device, add to fcports list. */
e315cd28 2950 list_add_tail(&new_fcport->list, &vha->vp_fcports);
1da177e4
LT		 2951
2952 /* Allocate a new replacement fcport. */
2953 fcport = new_fcport;
e315cd28 2954 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 2955 if (new_fcport == NULL) {
7c3df132
SK		 2956 ql_log(ql_log_warn, vha, 0x201c,
2957 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 2958 rval = QLA_MEMORY_ALLOC_FAILED;
2959 goto cleanup_allocation;
2960 }
2961 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
2962 }
2963
d8b45213 2964 /* Base iIDMA settings on HBA port speed. */
a3cbdfad 2965 fcport->fp_speed = ha->link_data_rate;
d8b45213 2966
e315cd28 2967 qla2x00_update_fcport(vha, fcport);
1da177e4
LT		 2968
2969 found_devs++;
2970 }
2971
2972cleanup_allocation:
c9475cb0 2973 kfree(new_fcport);
1da177e4
LT		 2974
2975 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2976 ql_dbg(ql_dbg_disc, vha, 0x201d,
2977 "Configure local loop error exit: rval=%x.\n", rval);
1da177e4
LT		 2978 }
2979
1da177e4
LT		 2980 return (rval);
2981}
2982
d8b45213 2983static void
e315cd28 2984qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
d8b45213 2985{
d8b45213 2986 int rval;
1bb39548 2987 uint16_t mb[4];
e315cd28 2988 struct qla_hw_data *ha = vha->hw;
d8b45213 2989
c76f2c01 2990 if (!IS_IIDMA_CAPABLE(ha))
d8b45213
AV		 2991 return;
2992
c9afb9a2
GM		 2993 if (atomic_read(&fcport->state) != FCS_ONLINE)
2994 return;
2995
39bd9622
AV		 2996 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
2997 fcport->fp_speed > ha->link_data_rate)
d8b45213
AV		 2998 return;
2999
e315cd28 3000 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
a3cbdfad 3001 mb);
d8b45213 3002 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3003 ql_dbg(ql_dbg_disc, vha, 0x2004,
3004 "Unable to adjust iIDMA "
3005 "%02x%02x%02x%02x%02x%02x%02x%02x -- %04x %x %04x "
3006 "%04x.\n", fcport->port_name[0], fcport->port_name[1],
d8b45213
AV		 3007 fcport->port_name[2], fcport->port_name[3],
3008 fcport->port_name[4], fcport->port_name[5],
3009 fcport->port_name[6], fcport->port_name[7], rval,
7c3df132 3010 fcport->fp_speed, mb[0], mb[1]);
d8b45213 3011 } else {
7c3df132
SK		 3012 ql_dbg(ql_dbg_disc, vha, 0x2005,
3013 "iIDMA adjusted to %s GB/s "
d0297c9a
JC		 3014 "on %02x%02x%02x%02x%02x%02x%02x%02x.\n",
3015 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
7c3df132
SK		 3016 fcport->port_name[0], fcport->port_name[1],
3017 fcport->port_name[2], fcport->port_name[3],
3018 fcport->port_name[4], fcport->port_name[5],
3019 fcport->port_name[6], fcport->port_name[7]);
d8b45213
AV		 3020 }
3021}
3022
23be331d 3023static void
e315cd28 3024qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
8482e118 3025{
3026 struct fc_rport_identifiers rport_ids;
bdf79621 3027 struct fc_rport *rport;
044d78e1 3028 unsigned long flags;
8482e118 3029
ac280b67 3030 qla2x00_rport_del(fcport);
8482e118 3031
f8b02a85
AV		 3032 rport_ids.node_name = wwn_to_u64(fcport->node_name);
3033 rport_ids.port_name = wwn_to_u64(fcport->port_name);
8482e118 3034 rport_ids.port_id = fcport->d_id.b.domain << 16 |
3035 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
77d74143 3036 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
e315cd28 3037 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
77d74143 3038 if (!rport) {
7c3df132
SK		 3039 ql_log(ql_log_warn, vha, 0x2006,
3040 "Unable to allocate fc remote port.\n");
77d74143
AV		 3041 return;
3042 }
2d70c103
NB		 3043 /*
3044 * Create target mode FC NEXUS in qla_target.c if target mode is
3045 * enabled..
3046 */
3047 qlt_fc_port_added(vha, fcport);
3048
044d78e1 3049 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
19a7b4ae 3050 *((fc_port_t **)rport->dd_data) = fcport;
044d78e1 3051 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
d97994dc 3052
ad3e0eda 3053 rport->supported_classes = fcport->supported_classes;
77d74143 3054
8482e118 3055 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
3056 if (fcport->port_type == FCT_INITIATOR)
3057 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
3058 if (fcport->port_type == FCT_TARGET)
3059 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
77d74143 3060 fc_remote_port_rolechg(rport, rport_ids.roles);
1da177e4
LT		 3061}
3062
23be331d
AB		 3063/*
3064 * qla2x00_update_fcport
3065 * Updates device on list.
3066 *
3067 * Input:
3068 * ha = adapter block pointer.
3069 * fcport = port structure pointer.
3070 *
3071 * Return:
3072 * 0 - Success
3073 * BIT_0 - error
3074 *
3075 * Context:
3076 * Kernel context.
3077 */
3078void
e315cd28 3079qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
23be331d 3080{
e315cd28 3081 fcport->vha = vha;
23be331d 3082 fcport->login_retry = 0;
5ff1d584 3083 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
23be331d 3084
1f93da52 3085 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
e315cd28 3086 qla2x00_iidma_fcport(vha, fcport);
21090cbe 3087 qla24xx_update_fcport_fcp_prio(vha, fcport);
e315cd28 3088 qla2x00_reg_remote_port(vha, fcport);
23be331d
AB		 3089}
3090
1da177e4
LT		 3091/*
3092 * qla2x00_configure_fabric
3093 * Setup SNS devices with loop ID's.
3094 *
3095 * Input:
3096 * ha = adapter block pointer.
3097 *
3098 * Returns:
3099 * 0 = success.
3100 * BIT_0 = error
3101 */
3102static int
e315cd28 3103qla2x00_configure_fabric(scsi_qla_host_t *vha)
1da177e4 3104{
b3b02e6e 3105 int rval;
4dc77c36 3106 fc_port_t *fcport;
1da177e4
LT		 3107 uint16_t next_loopid;
3108 uint16_t mb[MAILBOX_REGISTER_COUNT];
0107109e 3109 uint16_t loop_id;
1da177e4 3110 LIST_HEAD(new_fcports);
e315cd28
AC		 3111 struct qla_hw_data *ha = vha->hw;
3112 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3113
3114 /* If FL port exists, then SNS is present */
e428924c 3115 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3116 loop_id = NPH_F_PORT;
3117 else
3118 loop_id = SNS_FL_PORT;
e315cd28 3119 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
1da177e4 3120 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3121 ql_dbg(ql_dbg_disc, vha, 0x201f,
3122 "MBX_GET_PORT_NAME failed, No FL Port.\n");
1da177e4 3123
e315cd28 3124 vha->device_flags &= ~SWITCH_FOUND;
1da177e4
LT		 3125 return (QLA_SUCCESS);
3126 }
e315cd28 3127 vha->device_flags |= SWITCH_FOUND;
1da177e4 3128
1da177e4 3129 do {
cca5335c
AV		 3130 /* FDMI support. */
3131 if (ql2xfdmienable &&
e315cd28
AC		 3132 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
3133 qla2x00_fdmi_register(vha);
cca5335c 3134
1da177e4 3135 /* Ensure we are logged into the SNS. */
e428924c 3136 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3137 loop_id = NPH_SNS;
3138 else
3139 loop_id = SIMPLE_NAME_SERVER;
0b91d116
CD		 3140 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
3141 0xfc, mb, BIT_1|BIT_0);
3142 if (rval != QLA_SUCCESS) {
3143 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
4dc77c36 3144 break;
0b91d116 3145 }
1da177e4 3146 if (mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 3147 ql_dbg(ql_dbg_disc, vha, 0x2042,
3148 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
3149 "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
3150 mb[2], mb[6], mb[7]);
1da177e4
LT		 3151 return (QLA_SUCCESS);
3152 }
3153
e315cd28
AC		 3154 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
3155 if (qla2x00_rft_id(vha)) {
1da177e4 3156 /* EMPTY */
7c3df132
SK		 3157 ql_dbg(ql_dbg_disc, vha, 0x2045,
3158 "Register FC-4 TYPE failed.\n");
1da177e4 3159 }
e315cd28 3160 if (qla2x00_rff_id(vha)) {
1da177e4 3161 /* EMPTY */
7c3df132
SK		 3162 ql_dbg(ql_dbg_disc, vha, 0x2049,
3163 "Register FC-4 Features failed.\n");
1da177e4 3164 }
e315cd28 3165 if (qla2x00_rnn_id(vha)) {
1da177e4 3166 /* EMPTY */
7c3df132
SK		 3167 ql_dbg(ql_dbg_disc, vha, 0x204f,
3168 "Register Node Name failed.\n");
e315cd28 3169 } else if (qla2x00_rsnn_nn(vha)) {
1da177e4 3170 /* EMPTY */
7c3df132
SK		 3171 ql_dbg(ql_dbg_disc, vha, 0x2053,
3172 "Register Symobilic Node Name failed.\n");
1da177e4
LT		 3173 }
3174 }
3175
e315cd28 3176 rval = qla2x00_find_all_fabric_devs(vha, &new_fcports);
1da177e4
LT		 3177 if (rval != QLA_SUCCESS)
3178 break;
3179
4dc77c36
JC		 3180 /* Add new ports to existing port list */
3181 list_splice_tail_init(&new_fcports, &vha->vp_fcports);
3182
3183 /* Starting free loop ID. */
3184 next_loopid = ha->min_external_loopid;
3185
e315cd28
AC		 3186 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3187 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1da177e4
LT		 3188 break;
3189
3190 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
3191 continue;
3192
4dc77c36 3193 /* Logout lost/gone fabric devices (non-FCP2) */
c0822b63 3194 if (fcport->scan_state != QLA_FCPORT_SCAN_FOUND &&
b3b02e6e 3195 atomic_read(&fcport->state) == FCS_ONLINE) {
e315cd28 3196 qla2x00_mark_device_lost(vha, fcport,
d97994dc 3197 ql2xplogiabsentdevice, 0);
1da177e4 3198 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3199 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
1da177e4
LT		 3200 fcport->port_type != FCT_INITIATOR &&
3201 fcport->port_type != FCT_BROADCAST) {
e315cd28 3202 ha->isp_ops->fabric_logout(vha,
1c7c6357
AV		 3203 fcport->loop_id,
3204 fcport->d_id.b.domain,
3205 fcport->d_id.b.area,
3206 fcport->d_id.b.al_pa);
1da177e4 3207 }
c0822b63 3208 continue;
1da177e4 3209 }
c0822b63 3210 fcport->scan_state = QLA_FCPORT_SCAN_NONE;
1da177e4 3211
4dc77c36
JC		 3212 /* Login fabric devices that need a login */
3213 if ((fcport->flags & FCF_LOGIN_NEEDED) != 0 &&
3214 atomic_read(&vha->loop_down_timer) == 0) {
3215 if (fcport->loop_id == FC_NO_LOOP_ID) {
3216 fcport->loop_id = next_loopid;
3217 rval = qla2x00_find_new_loop_id(
3218 base_vha, fcport);
3219 if (rval != QLA_SUCCESS) {
3220 /* Ran out of IDs to use */
3221 continue;
3222 }
1da177e4
LT		 3223 }
3224 }
1da177e4 3225
bdf79621 3226 /* Login and update database */
e315cd28 3227 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
1da177e4
LT		 3228 }
3229 } while (0);
3230
1da177e4 3231 if (rval) {
7c3df132
SK		 3232 ql_dbg(ql_dbg_disc, vha, 0x2068,
3233 "Configure fabric error exit rval=%d.\n", rval);
1da177e4
LT		 3234 }
3235
3236 return (rval);
3237}
3238
1da177e4
LT		 3239/*
3240 * qla2x00_find_all_fabric_devs
3241 *
3242 * Input:
3243 * ha = adapter block pointer.
3244 * dev = database device entry pointer.
3245 *
3246 * Returns:
3247 * 0 = success.
3248 *
3249 * Context:
3250 * Kernel context.
3251 */
3252static int
e315cd28
AC		 3253qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
3254 struct list_head *new_fcports)
1da177e4
LT		 3255{
3256 int rval;
3257 uint16_t loop_id;
3258 fc_port_t *fcport, *new_fcport, *fcptemp;
3259 int found;
3260
3261 sw_info_t *swl;
3262 int swl_idx;
3263 int first_dev, last_dev;
1516ef44 3264 port_id_t wrap = {}, nxt_d_id;
e315cd28
AC		 3265 struct qla_hw_data *ha = vha->hw;
3266 struct scsi_qla_host *vp, *base_vha = pci_get_drvdata(ha->pdev);
ee546b6e 3267 struct scsi_qla_host *tvp;
1da177e4
LT		 3268
3269 rval = QLA_SUCCESS;
3270
3271 /* Try GID_PT to get device list, else GAN. */
7a67735b 3272 if (!ha->swl)
642ef983 3273 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
7a67735b
AV		 3274 GFP_KERNEL);
3275 swl = ha->swl;
bbfbbbc1 3276 if (!swl) {
1da177e4 3277 /*EMPTY*/
7c3df132
SK		 3278 ql_dbg(ql_dbg_disc, vha, 0x2054,
3279 "GID_PT allocations failed, fallback on GA_NXT.\n");
1da177e4 3280 } else {
642ef983 3281 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
e315cd28 3282 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
1da177e4 3283 swl = NULL;
e315cd28 3284 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3285 swl = NULL;
e315cd28 3286 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3287 swl = NULL;
e5896bd5 3288 } else if (ql2xiidmaenable &&
e315cd28
AC		 3289 qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) {
3290 qla2x00_gpsc(vha, swl);
1da177e4 3291 }
e8c72ba5
CD		 3292
3293 /* If other queries succeeded probe for FC-4 type */
3294 if (swl)
3295 qla2x00_gff_id(vha, swl);
1da177e4
LT		 3296 }
3297 swl_idx = 0;
3298
3299 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 3300 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3301 if (new_fcport == NULL) {
7c3df132
SK		 3302 ql_log(ql_log_warn, vha, 0x205e,
3303 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3304 return (QLA_MEMORY_ALLOC_FAILED);
3305 }
3306 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
1da177e4
LT		 3307 /* Set start port ID scan at adapter ID. */
3308 first_dev = 1;
3309 last_dev = 0;
3310
3311 /* Starting free loop ID. */
e315cd28
AC		 3312 loop_id = ha->min_external_loopid;
3313 for (; loop_id <= ha->max_loop_id; loop_id++) {
3314 if (qla2x00_is_reserved_id(vha, loop_id))
1da177e4
LT		 3315 continue;
3316
3a6478df
GM		 3317 if (ha->current_topology == ISP_CFG_FL &&
3318 (atomic_read(&vha->loop_down_timer) ||
3319 LOOP_TRANSITION(vha))) {
bb2d52b2
AV		 3320 atomic_set(&vha->loop_down_timer, 0);
3321 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
3322 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1da177e4 3323 break;
bb2d52b2 3324 }
1da177e4
LT		 3325
3326 if (swl != NULL) {
3327 if (last_dev) {
3328 wrap.b24 = new_fcport->d_id.b24;
3329 } else {
3330 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
3331 memcpy(new_fcport->node_name,
3332 swl[swl_idx].node_name, WWN_SIZE);
3333 memcpy(new_fcport->port_name,
3334 swl[swl_idx].port_name, WWN_SIZE);
d8b45213
AV		 3335 memcpy(new_fcport->fabric_port_name,
3336 swl[swl_idx].fabric_port_name, WWN_SIZE);
3337 new_fcport->fp_speed = swl[swl_idx].fp_speed;
e8c72ba5 3338 new_fcport->fc4_type = swl[swl_idx].fc4_type;
1da177e4
LT		 3339
3340 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
3341 last_dev = 1;
3342 }
3343 swl_idx++;
3344 }
3345 } else {
3346 /* Send GA_NXT to the switch */
e315cd28 3347 rval = qla2x00_ga_nxt(vha, new_fcport);
1da177e4 3348 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3349 ql_log(ql_log_warn, vha, 0x2064,
3350 "SNS scan failed -- assuming "
3351 "zero-entry result.\n");
1da177e4
LT		 3352 list_for_each_entry_safe(fcport, fcptemp,
3353 new_fcports, list) {
3354 list_del(&fcport->list);
3355 kfree(fcport);
3356 }
3357 rval = QLA_SUCCESS;
3358 break;
3359 }
3360 }
3361
3362 /* If wrap on switch device list, exit. */
3363 if (first_dev) {
3364 wrap.b24 = new_fcport->d_id.b24;
3365 first_dev = 0;
3366 } else if (new_fcport->d_id.b24 == wrap.b24) {
7c3df132
SK		 3367 ql_dbg(ql_dbg_disc, vha, 0x2065,
3368 "Device wrap (%02x%02x%02x).\n",
3369 new_fcport->d_id.b.domain,
3370 new_fcport->d_id.b.area,
3371 new_fcport->d_id.b.al_pa);
1da177e4
LT		 3372 break;
3373 }
3374
2c3dfe3f 3375 /* Bypass if same physical adapter. */
e315cd28 3376 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
1da177e4
LT		 3377 continue;
3378
2c3dfe3f 3379 /* Bypass virtual ports of the same host. */
e315cd28
AC		 3380 found = 0;
3381 if (ha->num_vhosts) {
feafb7b1
AE		 3382 unsigned long flags;
3383
3384 spin_lock_irqsave(&ha->vport_slock, flags);
ee546b6e 3385 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
e315cd28
AC		 3386 if (new_fcport->d_id.b24 == vp->d_id.b24) {
3387 found = 1;
2c3dfe3f 3388 break;
e315cd28 3389 }
2c3dfe3f 3390 }
feafb7b1
AE		 3391 spin_unlock_irqrestore(&ha->vport_slock, flags);
3392
e315cd28 3393 if (found)
2c3dfe3f
SJ		 3394 continue;
3395 }
3396
f7d289f6
AV		 3397 /* Bypass if same domain and area of adapter. */
3398 if (((new_fcport->d_id.b24 & 0xffff00) ==
e315cd28 3399 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
f7d289f6
AV		 3400 ISP_CFG_FL)
3401 continue;
3402
1da177e4
LT		 3403 /* Bypass reserved domain fields. */
3404 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
3405 continue;
3406
e8c72ba5 3407 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
4da26e16
CD		 3408 if (ql2xgffidenable &&
3409 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
3410 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
e8c72ba5
CD		 3411 continue;
3412
1da177e4
LT		 3413 /* Locate matching device in database. */
3414 found = 0;
e315cd28 3415 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3416 if (memcmp(new_fcport->port_name, fcport->port_name,
3417 WWN_SIZE))
3418 continue;
3419
c0822b63 3420 fcport->scan_state = QLA_FCPORT_SCAN_FOUND;
b3b02e6e 3421
1da177e4
LT		 3422 found++;
3423
d8b45213
AV		 3424 /* Update port state. */
3425 memcpy(fcport->fabric_port_name,
3426 new_fcport->fabric_port_name, WWN_SIZE);
3427 fcport->fp_speed = new_fcport->fp_speed;
3428
1da177e4
LT		 3429 /*
3430 * If address the same and state FCS_ONLINE, nothing
3431 * changed.
3432 */
3433 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
3434 atomic_read(&fcport->state) == FCS_ONLINE) {
3435 break;
3436 }
3437
3438 /*
3439 * If device was not a fabric device before.
3440 */
3441 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3442 fcport->d_id.b24 = new_fcport->d_id.b24;
5f16b331 3443 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3444 fcport->flags |= (FCF_FABRIC_DEVICE |
3445 FCF_LOGIN_NEEDED);
1da177e4
LT		 3446 break;
3447 }
3448
3449 /*
3450 * Port ID changed or device was marked to be updated;
3451 * Log it out if still logged in and mark it for
3452 * relogin later.
3453 */
3454 fcport->d_id.b24 = new_fcport->d_id.b24;
3455 fcport->flags |= FCF_LOGIN_NEEDED;
3456 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3457 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
0eba25df 3458 (fcport->flags & FCF_ASYNC_SENT) == 0 &&
1da177e4
LT		 3459 fcport->port_type != FCT_INITIATOR &&
3460 fcport->port_type != FCT_BROADCAST) {
e315cd28 3461 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3462 fcport->d_id.b.domain, fcport->d_id.b.area,
3463 fcport->d_id.b.al_pa);
5f16b331 3464 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3465 }
3466
3467 break;
3468 }
3469
3470 if (found)
3471 continue;
1da177e4
LT		 3472 /* If device was not in our fcports list, then add it. */
3473 list_add_tail(&new_fcport->list, new_fcports);
3474
3475 /* Allocate a new replacement fcport. */
3476 nxt_d_id.b24 = new_fcport->d_id.b24;
e315cd28 3477 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3478 if (new_fcport == NULL) {
7c3df132
SK		 3479 ql_log(ql_log_warn, vha, 0x2066,
3480 "Memory allocation failed for fcport.\n");
1da177e4
LT		 3481 return (QLA_MEMORY_ALLOC_FAILED);
3482 }
3483 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
3484 new_fcport->d_id.b24 = nxt_d_id.b24;
3485 }
3486
c9475cb0 3487 kfree(new_fcport);
1da177e4 3488
1da177e4
LT		 3489 return (rval);
3490}
3491
3492/*
3493 * qla2x00_find_new_loop_id
3494 * Scan through our port list and find a new usable loop ID.
3495 *
3496 * Input:
3497 * ha: adapter state pointer.
3498 * dev: port structure pointer.
3499 *
3500 * Returns:
3501 * qla2x00 local function return status code.
3502 *
3503 * Context:
3504 * Kernel context.
3505 */
03bcfb57 3506int
e315cd28 3507qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
1da177e4
LT		 3508{
3509 int rval;
e315cd28 3510 struct qla_hw_data *ha = vha->hw;
feafb7b1 3511 unsigned long flags = 0;
1da177e4
LT		 3512
3513 rval = QLA_SUCCESS;
3514
5f16b331 3515 spin_lock_irqsave(&ha->vport_slock, flags);
1da177e4 3516
5f16b331
CD		 3517 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
3518 LOOPID_MAP_SIZE);
3519 if (dev->loop_id >= LOOPID_MAP_SIZE ||
3520 qla2x00_is_reserved_id(vha, dev->loop_id)) {
3521 dev->loop_id = FC_NO_LOOP_ID;
3522 rval = QLA_FUNCTION_FAILED;
3523 } else
3524 set_bit(dev->loop_id, ha->loop_id_map);
1da177e4 3525
5f16b331 3526 spin_unlock_irqrestore(&ha->vport_slock, flags);
1da177e4 3527
5f16b331
CD		 3528 if (rval == QLA_SUCCESS)
3529 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
3530 "Assigning new loopid=%x, portid=%x.\n",
3531 dev->loop_id, dev->d_id.b24);
3532 else
3533 ql_log(ql_log_warn, dev->vha, 0x2087,
3534 "No loop_id's available, portid=%x.\n",
3535 dev->d_id.b24);
1da177e4
LT		 3536
3537 return (rval);
3538}
3539
1da177e4
LT		 3540/*
3541 * qla2x00_fabric_dev_login
3542 * Login fabric target device and update FC port database.
3543 *
3544 * Input:
3545 * ha: adapter state pointer.
3546 * fcport: port structure list pointer.
3547 * next_loopid: contains value of a new loop ID that can be used
3548 * by the next login attempt.
3549 *
3550 * Returns:
3551 * qla2x00 local function return status code.
3552 *
3553 * Context:
3554 * Kernel context.
3555 */
3556static int
e315cd28 3557qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3558 uint16_t *next_loopid)
3559{
3560 int rval;
3561 int retry;
0107109e 3562 uint8_t opts;
e315cd28 3563 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3564
3565 rval = QLA_SUCCESS;
3566 retry = 0;
3567
ac280b67 3568 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584
AV		 3569 if (fcport->flags & FCF_ASYNC_SENT)
3570 return rval;
3571 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 3572 rval = qla2x00_post_async_login_work(vha, fcport, NULL);
3573 if (!rval)
3574 return rval;
3575 }
3576
5ff1d584 3577 fcport->flags &= ~FCF_ASYNC_SENT;
e315cd28 3578 rval = qla2x00_fabric_login(vha, fcport, next_loopid);
1da177e4 3579 if (rval == QLA_SUCCESS) {
f08b7251 3580 /* Send an ADISC to FCP2 devices.*/
0107109e 3581 opts = 0;
f08b7251 3582 if (fcport->flags & FCF_FCP2_DEVICE)
0107109e 3583 opts |= BIT_1;
e315cd28 3584 rval = qla2x00_get_port_database(vha, fcport, opts);
1da177e4 3585 if (rval != QLA_SUCCESS) {
e315cd28 3586 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3587 fcport->d_id.b.domain, fcport->d_id.b.area,
3588 fcport->d_id.b.al_pa);
e315cd28 3589 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4 3590 } else {
e315cd28 3591 qla2x00_update_fcport(vha, fcport);
1da177e4 3592 }
0b91d116
CD		 3593 } else {
3594 /* Retry Login. */
3595 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3596 }
3597
3598 return (rval);
3599}
3600
3601/*
3602 * qla2x00_fabric_login
3603 * Issue fabric login command.
3604 *
3605 * Input:
3606 * ha = adapter block pointer.
3607 * device = pointer to FC device type structure.
3608 *
3609 * Returns:
3610 * 0 - Login successfully
3611 * 1 - Login failed
3612 * 2 - Initiator device
3613 * 3 - Fatal error
3614 */
3615int
e315cd28 3616qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3617 uint16_t *next_loopid)
3618{
3619 int rval;
3620 int retry;
3621 uint16_t tmp_loopid;
3622 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 3623 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3624
3625 retry = 0;
3626 tmp_loopid = 0;
3627
3628 for (;;) {
7c3df132
SK		 3629 ql_dbg(ql_dbg_disc, vha, 0x2000,
3630 "Trying Fabric Login w/loop id 0x%04x for port "
3631 "%02x%02x%02x.\n",
3632 fcport->loop_id, fcport->d_id.b.domain,
3633 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3634
3635 /* Login fcport on switch. */
0b91d116 3636 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
1da177e4
LT		 3637 fcport->d_id.b.domain, fcport->d_id.b.area,
3638 fcport->d_id.b.al_pa, mb, BIT_0);
0b91d116
CD		 3639 if (rval != QLA_SUCCESS) {
3640 return rval;
3641 }
1da177e4
LT		 3642 if (mb[0] == MBS_PORT_ID_USED) {
3643 /*
3644 * Device has another loop ID. The firmware team
0107109e
AV		 3645 * recommends the driver perform an implicit login with
3646 * the specified ID again. The ID we just used is save
3647 * here so we return with an ID that can be tried by
3648 * the next login.
1da177e4
LT		 3649 */
3650 retry++;
3651 tmp_loopid = fcport->loop_id;
3652 fcport->loop_id = mb[1];
3653
7c3df132
SK		 3654 ql_dbg(ql_dbg_disc, vha, 0x2001,
3655 "Fabric Login: port in use - next loop "
3656 "id=0x%04x, port id= %02x%02x%02x.\n",
1da177e4 3657 fcport->loop_id, fcport->d_id.b.domain,
7c3df132 3658 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3659
3660 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
3661 /*
3662 * Login succeeded.
3663 */
3664 if (retry) {
3665 /* A retry occurred before. */
3666 *next_loopid = tmp_loopid;
3667 } else {
3668 /*
3669 * No retry occurred before. Just increment the
3670 * ID value for next login.
3671 */
3672 *next_loopid = (fcport->loop_id + 1);
3673 }
3674
3675 if (mb[1] & BIT_0) {
3676 fcport->port_type = FCT_INITIATOR;
3677 } else {
3678 fcport->port_type = FCT_TARGET;
3679 if (mb[1] & BIT_1) {
8474f3a0 3680 fcport->flags |= FCF_FCP2_DEVICE;
1da177e4
LT		 3681 }
3682 }
3683
ad3e0eda
AV		 3684 if (mb[10] & BIT_0)
3685 fcport->supported_classes |= FC_COS_CLASS2;
3686 if (mb[10] & BIT_1)
3687 fcport->supported_classes |= FC_COS_CLASS3;
3688
2d70c103
NB		 3689 if (IS_FWI2_CAPABLE(ha)) {
3690 if (mb[10] & BIT_7)
3691 fcport->flags |=
3692 FCF_CONF_COMP_SUPPORTED;
3693 }
3694
1da177e4
LT		 3695 rval = QLA_SUCCESS;
3696 break;
3697 } else if (mb[0] == MBS_LOOP_ID_USED) {
3698 /*
3699 * Loop ID already used, try next loop ID.
3700 */
3701 fcport->loop_id++;
e315cd28 3702 rval = qla2x00_find_new_loop_id(vha, fcport);
1da177e4
LT		 3703 if (rval != QLA_SUCCESS) {
3704 /* Ran out of loop IDs to use */
3705 break;
3706 }
3707 } else if (mb[0] == MBS_COMMAND_ERROR) {
3708 /*
3709 * Firmware possibly timed out during login. If NO
3710 * retries are left to do then the device is declared
3711 * dead.
3712 */
3713 *next_loopid = fcport->loop_id;
e315cd28 3714 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3715 fcport->d_id.b.domain, fcport->d_id.b.area,
3716 fcport->d_id.b.al_pa);
e315cd28 3717 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3718
3719 rval = 1;
3720 break;
3721 } else {
3722 /*
3723 * unrecoverable / not handled error
3724 */
7c3df132
SK		 3725 ql_dbg(ql_dbg_disc, vha, 0x2002,
3726 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
3727 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
3728 fcport->d_id.b.area, fcport->d_id.b.al_pa,
3729 fcport->loop_id, jiffies);
1da177e4
LT		 3730
3731 *next_loopid = fcport->loop_id;
e315cd28 3732 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3733 fcport->d_id.b.domain, fcport->d_id.b.area,
3734 fcport->d_id.b.al_pa);
5f16b331 3735 qla2x00_clear_loop_id(fcport);
0eedfcf0 3736 fcport->login_retry = 0;
1da177e4
LT		 3737
3738 rval = 3;
3739 break;
3740 }
3741 }
3742
3743 return (rval);
3744}
3745
3746/*
3747 * qla2x00_local_device_login
3748 * Issue local device login command.
3749 *
3750 * Input:
3751 * ha = adapter block pointer.
3752 * loop_id = loop id of device to login to.
3753 *
3754 * Returns (Where's the #define!!!!):
3755 * 0 - Login successfully
3756 * 1 - Login failed
3757 * 3 - Fatal error
3758 */
3759int
e315cd28 3760qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
1da177e4
LT		 3761{
3762 int rval;
3763 uint16_t mb[MAILBOX_REGISTER_COUNT];
3764
3765 memset(mb, 0, sizeof(mb));
e315cd28 3766 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
1da177e4
LT		 3767 if (rval == QLA_SUCCESS) {
3768 /* Interrogate mailbox registers for any errors */
3769 if (mb[0] == MBS_COMMAND_ERROR)
3770 rval = 1;
3771 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
3772 /* device not in PCB table */
3773 rval = 3;
3774 }
3775
3776 return (rval);
3777}
3778
3779/*
3780 * qla2x00_loop_resync
3781 * Resync with fibre channel devices.
3782 *
3783 * Input:
3784 * ha = adapter block pointer.
3785 *
3786 * Returns:
3787 * 0 = success
3788 */
3789int
e315cd28 3790qla2x00_loop_resync(scsi_qla_host_t *vha)
1da177e4 3791{
73208dfd 3792 int rval = QLA_SUCCESS;
1da177e4 3793 uint32_t wait_time;
67c2e93a
AC		 3794 struct req_que *req;
3795 struct rsp_que *rsp;
3796
7163ea81 3797 if (vha->hw->flags.cpu_affinity_enabled)
67c2e93a
AC		 3798 req = vha->hw->req_q_map[0];
3799 else
3800 req = vha->req;
3801 rsp = req->rsp;
1da177e4 3802
e315cd28
AC		 3803 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
3804 if (vha->flags.online) {
3805 if (!(rval = qla2x00_fw_ready(vha))) {
1da177e4
LT		 3806 /* Wait at most MAX_TARGET RSCNs for a stable link. */
3807 wait_time = 256;
3808 do {
0107109e 3809 /* Issue a marker after FW becomes ready. */
73208dfd
AC		 3810 qla2x00_marker(vha, req, rsp, 0, 0,
3811 MK_SYNC_ALL);
e315cd28 3812 vha->marker_needed = 0;
1da177e4
LT		 3813
3814 /* Remap devices on Loop. */
e315cd28 3815 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4 3816
e315cd28 3817 qla2x00_configure_loop(vha);
1da177e4 3818 wait_time--;
e315cd28
AC		 3819 } while (!atomic_read(&vha->loop_down_timer) &&
3820 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
3821 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
3822 &vha->dpc_flags)));
1da177e4 3823 }
1da177e4
LT		 3824 }
3825
e315cd28 3826 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
1da177e4 3827 return (QLA_FUNCTION_FAILED);
1da177e4 3828
e315cd28 3829 if (rval)
7c3df132
SK		 3830 ql_dbg(ql_dbg_disc, vha, 0x206c,
3831 "%s *** FAILED ***.\n", __func__);
1da177e4
LT		 3832
3833 return (rval);
3834}
3835
579d12b5
SK		 3836/*
3837* qla2x00_perform_loop_resync
3838* Description: This function will set the appropriate flags and call
3839* qla2x00_loop_resync. If successful loop will be resynced
3840* Arguments : scsi_qla_host_t pointer
3841* returm : Success or Failure
3842*/
3843
3844int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
3845{
3846 int32_t rval = 0;
3847
3848 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
3849 /*Configure the flags so that resync happens properly*/
3850 atomic_set(&ha->loop_down_timer, 0);
3851 if (!(ha->device_flags & DFLG_NO_CABLE)) {
3852 atomic_set(&ha->loop_state, LOOP_UP);
3853 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
3854 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
3855 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
3856
3857 rval = qla2x00_loop_resync(ha);
3858 } else
3859 atomic_set(&ha->loop_state, LOOP_DEAD);
3860
3861 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
3862 }
3863
3864 return rval;
3865}
3866
d97994dc 3867void
67becc00 3868qla2x00_update_fcports(scsi_qla_host_t *base_vha)
d97994dc 3869{
3870 fc_port_t *fcport;
feafb7b1
AE		 3871 struct scsi_qla_host *vha;
3872 struct qla_hw_data *ha = base_vha->hw;
3873 unsigned long flags;
d97994dc 3874
feafb7b1 3875 spin_lock_irqsave(&ha->vport_slock, flags);
d97994dc 3876 /* Go with deferred removal of rport references. */
feafb7b1
AE		 3877 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
3878 atomic_inc(&vha->vref_count);
3879 list_for_each_entry(fcport, &vha->vp_fcports, list) {
8ae598d0 3880 if (fcport->drport &&
feafb7b1
AE		 3881 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
3882 spin_unlock_irqrestore(&ha->vport_slock, flags);
3883
67becc00 3884 qla2x00_rport_del(fcport);
feafb7b1
AE		 3885
3886 spin_lock_irqsave(&ha->vport_slock, flags);
3887 }
3888 }
3889 atomic_dec(&vha->vref_count);
3890 }
3891 spin_unlock_irqrestore(&ha->vport_slock, flags);
d97994dc 3892}
3893
7d613ac6
SV		 3894/* Assumes idc_lock always held on entry */
3895void
3896qla83xx_reset_ownership(scsi_qla_host_t *vha)
3897{
3898 struct qla_hw_data *ha = vha->hw;
3899 uint32_t drv_presence, drv_presence_mask;
3900 uint32_t dev_part_info1, dev_part_info2, class_type;
3901 uint32_t class_type_mask = 0x3;
3902 uint16_t fcoe_other_function = 0xffff, i;
3903
3904 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
3905
3906 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
3907 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
3908 for (i = 0; i < 8; i++) {
3909 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
3910 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
3911 (i != ha->portnum)) {
3912 fcoe_other_function = i;
3913 break;
3914 }
3915 }
3916 if (fcoe_other_function == 0xffff) {
3917 for (i = 0; i < 8; i++) {
3918 class_type = ((dev_part_info2 >> (i * 4)) &
3919 class_type_mask);
3920 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
3921 ((i + 8) != ha->portnum)) {
3922 fcoe_other_function = i + 8;
3923 break;
3924 }
3925 }
3926 }
3927 /*
3928 * Prepare drv-presence mask based on fcoe functions present.
3929 * However consider only valid physical fcoe function numbers (0-15).
3930 */
3931 drv_presence_mask = ~((1 << (ha->portnum)) |
3932 ((fcoe_other_function == 0xffff) ?
3933 0 : (1 << (fcoe_other_function))));
3934
3935 /* We are the reset owner iff:
3936 * - No other protocol drivers present.
3937 * - This is the lowest among fcoe functions. */
3938 if (!(drv_presence & drv_presence_mask) &&
3939 (ha->portnum < fcoe_other_function)) {
3940 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
3941 "This host is Reset owner.\n");
3942 ha->flags.nic_core_reset_owner = 1;
3943 }
3944}
3945
fa492630 3946static int
7d613ac6
SV		 3947__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
3948{
3949 int rval = QLA_SUCCESS;
3950 struct qla_hw_data *ha = vha->hw;
3951 uint32_t drv_ack;
3952
3953 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
3954 if (rval == QLA_SUCCESS) {
3955 drv_ack |= (1 << ha->portnum);
3956 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
3957 }
3958
3959 return rval;
3960}
3961
fa492630 3962static int
7d613ac6
SV		 3963__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
3964{
3965 int rval = QLA_SUCCESS;
3966 struct qla_hw_data *ha = vha->hw;
3967 uint32_t drv_ack;
3968
3969 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
3970 if (rval == QLA_SUCCESS) {
3971 drv_ack &= ~(1 << ha->portnum);
3972 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
3973 }
3974
3975 return rval;
3976}
3977
fa492630 3978static const char *
7d613ac6
SV		 3979qla83xx_dev_state_to_string(uint32_t dev_state)
3980{
3981 switch (dev_state) {
3982 case QLA8XXX_DEV_COLD:
3983 return "COLD/RE-INIT";
3984 case QLA8XXX_DEV_INITIALIZING:
3985 return "INITIALIZING";
3986 case QLA8XXX_DEV_READY:
3987 return "READY";
3988 case QLA8XXX_DEV_NEED_RESET:
3989 return "NEED RESET";
3990 case QLA8XXX_DEV_NEED_QUIESCENT:
3991 return "NEED QUIESCENT";
3992 case QLA8XXX_DEV_FAILED:
3993 return "FAILED";
3994 case QLA8XXX_DEV_QUIESCENT:
3995 return "QUIESCENT";
3996 default:
3997 return "Unknown";
3998 }
3999}
4000
4001/* Assumes idc-lock always held on entry */
4002void
4003qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
4004{
4005 struct qla_hw_data *ha = vha->hw;
4006 uint32_t idc_audit_reg = 0, duration_secs = 0;
4007
4008 switch (audit_type) {
4009 case IDC_AUDIT_TIMESTAMP:
4010 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
4011 idc_audit_reg = (ha->portnum) |
4012 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
4013 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4014 break;
4015
4016 case IDC_AUDIT_COMPLETION:
4017 duration_secs = ((jiffies_to_msecs(jiffies) -
4018 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
4019 idc_audit_reg = (ha->portnum) |
4020 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
4021 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4022 break;
4023
4024 default:
4025 ql_log(ql_log_warn, vha, 0xb078,
4026 "Invalid audit type specified.\n");
4027 break;
4028 }
4029}
4030
4031/* Assumes idc_lock always held on entry */
fa492630 4032static int
7d613ac6
SV		 4033qla83xx_initiating_reset(scsi_qla_host_t *vha)
4034{
4035 struct qla_hw_data *ha = vha->hw;
4036 uint32_t idc_control, dev_state;
4037
4038 __qla83xx_get_idc_control(vha, &idc_control);
4039 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
4040 ql_log(ql_log_info, vha, 0xb080,
4041 "NIC Core reset has been disabled. idc-control=0x%x\n",
4042 idc_control);
4043 return QLA_FUNCTION_FAILED;
4044 }
4045
4046 /* Set NEED-RESET iff in READY state and we are the reset-owner */
4047 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4048 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
4049 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
4050 QLA8XXX_DEV_NEED_RESET);
4051 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
4052 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
4053 } else {
4054 const char *state = qla83xx_dev_state_to_string(dev_state);
4055 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
4056
4057 /* SV: XXX: Is timeout required here? */
4058 /* Wait for IDC state change READY -> NEED_RESET */
4059 while (dev_state == QLA8XXX_DEV_READY) {
4060 qla83xx_idc_unlock(vha, 0);
4061 msleep(200);
4062 qla83xx_idc_lock(vha, 0);
4063 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4064 }
4065 }
4066
4067 /* Send IDC ack by writing to drv-ack register */
4068 __qla83xx_set_drv_ack(vha);
4069
4070 return QLA_SUCCESS;
4071}
4072
4073int
4074__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
4075{
4076 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4077}
4078
7d613ac6
SV		 4079int
4080__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
4081{
4082 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4083}
4084
fa492630 4085static int
7d613ac6
SV		 4086qla83xx_check_driver_presence(scsi_qla_host_t *vha)
4087{
4088 uint32_t drv_presence = 0;
4089 struct qla_hw_data *ha = vha->hw;
4090
4091 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4092 if (drv_presence & (1 << ha->portnum))
4093 return QLA_SUCCESS;
4094 else
4095 return QLA_TEST_FAILED;
4096}
4097
4098int
4099qla83xx_nic_core_reset(scsi_qla_host_t *vha)
4100{
4101 int rval = QLA_SUCCESS;
4102 struct qla_hw_data *ha = vha->hw;
4103
4104 ql_dbg(ql_dbg_p3p, vha, 0xb058,
4105 "Entered %s().\n", __func__);
4106
4107 if (vha->device_flags & DFLG_DEV_FAILED) {
4108 ql_log(ql_log_warn, vha, 0xb059,
4109 "Device in unrecoverable FAILED state.\n");
4110 return QLA_FUNCTION_FAILED;
4111 }
4112
4113 qla83xx_idc_lock(vha, 0);
4114
4115 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
4116 ql_log(ql_log_warn, vha, 0xb05a,
4117 "Function=0x%x has been removed from IDC participation.\n",
4118 ha->portnum);
4119 rval = QLA_FUNCTION_FAILED;
4120 goto exit;
4121 }
4122
4123 qla83xx_reset_ownership(vha);
4124
4125 rval = qla83xx_initiating_reset(vha);
4126
4127 /*
4128 * Perform reset if we are the reset-owner,
4129 * else wait till IDC state changes to READY/FAILED.
4130 */
4131 if (rval == QLA_SUCCESS) {
4132 rval = qla83xx_idc_state_handler(vha);
4133
4134 if (rval == QLA_SUCCESS)
4135 ha->flags.nic_core_hung = 0;
4136 __qla83xx_clear_drv_ack(vha);
4137 }
4138
4139exit:
4140 qla83xx_idc_unlock(vha, 0);
4141
4142 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
4143
4144 return rval;
4145}
4146
81178772
SK		 4147int
4148qla2xxx_mctp_dump(scsi_qla_host_t *vha)
4149{
4150 struct qla_hw_data *ha = vha->hw;
4151 int rval = QLA_FUNCTION_FAILED;
4152
4153 if (!IS_MCTP_CAPABLE(ha)) {
4154 /* This message can be removed from the final version */
4155 ql_log(ql_log_info, vha, 0x506d,
4156 "This board is not MCTP capable\n");
4157 return rval;
4158 }
4159
4160 if (!ha->mctp_dump) {
4161 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
4162 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
4163
4164 if (!ha->mctp_dump) {
4165 ql_log(ql_log_warn, vha, 0x506e,
4166 "Failed to allocate memory for mctp dump\n");
4167 return rval;
4168 }
4169 }
4170
4171#define MCTP_DUMP_STR_ADDR 0x00000000
4172 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
4173 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
4174 if (rval != QLA_SUCCESS) {
4175 ql_log(ql_log_warn, vha, 0x506f,
4176 "Failed to capture mctp dump\n");
4177 } else {
4178 ql_log(ql_log_info, vha, 0x5070,
4179 "Mctp dump capture for host (%ld/%p).\n",
4180 vha->host_no, ha->mctp_dump);
4181 ha->mctp_dumped = 1;
4182 }
4183
409ee0fe 4184 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
81178772
SK		 4185 ha->flags.nic_core_reset_hdlr_active = 1;
4186 rval = qla83xx_restart_nic_firmware(vha);
4187 if (rval)
4188 /* NIC Core reset failed. */
4189 ql_log(ql_log_warn, vha, 0x5071,
4190 "Failed to restart nic firmware\n");
4191 else
4192 ql_dbg(ql_dbg_p3p, vha, 0xb084,
4193 "Restarted NIC firmware successfully.\n");
4194 ha->flags.nic_core_reset_hdlr_active = 0;
4195 }
4196
4197 return rval;
4198
4199}
4200
579d12b5 4201/*
8fcd6b8b 4202* qla2x00_quiesce_io
579d12b5
SK		 4203* Description: This function will block the new I/Os
4204* Its not aborting any I/Os as context
4205* is not destroyed during quiescence
4206* Arguments: scsi_qla_host_t
4207* return : void
4208*/
4209void
8fcd6b8b 4210qla2x00_quiesce_io(scsi_qla_host_t *vha)
579d12b5
SK		 4211{
4212 struct qla_hw_data *ha = vha->hw;
4213 struct scsi_qla_host *vp;
4214
8fcd6b8b
CD		 4215 ql_dbg(ql_dbg_dpc, vha, 0x401d,
4216 "Quiescing I/O - ha=%p.\n", ha);
579d12b5
SK		 4217
4218 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
4219 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4220 atomic_set(&vha->loop_state, LOOP_DOWN);
4221 qla2x00_mark_all_devices_lost(vha, 0);
4222 list_for_each_entry(vp, &ha->vp_list, list)
8fcd6b8b 4223 qla2x00_mark_all_devices_lost(vp, 0);
579d12b5
SK		 4224 } else {
4225 if (!atomic_read(&vha->loop_down_timer))
4226 atomic_set(&vha->loop_down_timer,
4227 LOOP_DOWN_TIME);
4228 }
4229 /* Wait for pending cmds to complete */
4230 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
4231}
4232
a9083016
GM		 4233void
4234qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
4235{
4236 struct qla_hw_data *ha = vha->hw;
579d12b5 4237 struct scsi_qla_host *vp;
feafb7b1 4238 unsigned long flags;
6aef87be 4239 fc_port_t *fcport;
a9083016 4240
e46ef004
SK		 4241 /* For ISP82XX, driver waits for completion of the commands.
4242 * online flag should be set.
4243 */
4244 if (!IS_QLA82XX(ha))
4245 vha->flags.online = 0;
a9083016
GM		 4246 ha->flags.chip_reset_done = 0;
4247 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2be21fa2 4248 vha->qla_stats.total_isp_aborts++;
a9083016 4249
7c3df132
SK		 4250 ql_log(ql_log_info, vha, 0x00af,
4251 "Performing ISP error recovery - ha=%p.\n", ha);
a9083016 4252
e46ef004
SK		 4253 /* For ISP82XX, reset_chip is just disabling interrupts.
4254 * Driver waits for the completion of the commands.
4255 * the interrupts need to be enabled.
4256 */
a9083016
GM		 4257 if (!IS_QLA82XX(ha))
4258 ha->isp_ops->reset_chip(vha);
4259
4260 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
4261 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4262 atomic_set(&vha->loop_state, LOOP_DOWN);
4263 qla2x00_mark_all_devices_lost(vha, 0);
feafb7b1
AE		 4264
4265 spin_lock_irqsave(&ha->vport_slock, flags);
579d12b5 4266 list_for_each_entry(vp, &ha->vp_list, list) {
feafb7b1
AE		 4267 atomic_inc(&vp->vref_count);
4268 spin_unlock_irqrestore(&ha->vport_slock, flags);
4269
a9083016 4270 qla2x00_mark_all_devices_lost(vp, 0);
feafb7b1
AE		 4271
4272 spin_lock_irqsave(&ha->vport_slock, flags);
4273 atomic_dec(&vp->vref_count);
4274 }
4275 spin_unlock_irqrestore(&ha->vport_slock, flags);
a9083016
GM		 4276 } else {
4277 if (!atomic_read(&vha->loop_down_timer))
4278 atomic_set(&vha->loop_down_timer,
4279 LOOP_DOWN_TIME);
4280 }
4281
6aef87be
AV		 4282 /* Clear all async request states across all VPs. */
4283 list_for_each_entry(fcport, &vha->vp_fcports, list)
4284 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4285 spin_lock_irqsave(&ha->vport_slock, flags);
4286 list_for_each_entry(vp, &ha->vp_list, list) {
4287 atomic_inc(&vp->vref_count);
4288 spin_unlock_irqrestore(&ha->vport_slock, flags);
4289
4290 list_for_each_entry(fcport, &vp->vp_fcports, list)
4291 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4292
4293 spin_lock_irqsave(&ha->vport_slock, flags);
4294 atomic_dec(&vp->vref_count);
4295 }
4296 spin_unlock_irqrestore(&ha->vport_slock, flags);
4297
bddd2d65
LC		 4298 if (!ha->flags.eeh_busy) {
4299 /* Make sure for ISP 82XX IO DMA is complete */
4300 if (IS_QLA82XX(ha)) {
7190575f 4301 qla82xx_chip_reset_cleanup(vha);
7c3df132
SK		 4302 ql_log(ql_log_info, vha, 0x00b4,
4303 "Done chip reset cleanup.\n");
a9083016 4304
e46ef004
SK		 4305 /* Done waiting for pending commands.
4306 * Reset the online flag.
4307 */
4308 vha->flags.online = 0;
4d78c973 4309 }
a9083016 4310
bddd2d65
LC		 4311 /* Requeue all commands in outstanding command list. */
4312 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
4313 }
a9083016
GM		 4314}
4315
1da177e4
LT		 4316/*
4317* qla2x00_abort_isp
4318* Resets ISP and aborts all outstanding commands.
4319*
4320* Input:
4321* ha = adapter block pointer.
4322*
4323* Returns:
4324* 0 = success
4325*/
4326int
e315cd28 4327qla2x00_abort_isp(scsi_qla_host_t *vha)
1da177e4 4328{
476e8978 4329 int rval;
1da177e4 4330 uint8_t status = 0;
e315cd28
AC		 4331 struct qla_hw_data *ha = vha->hw;
4332 struct scsi_qla_host *vp;
73208dfd 4333 struct req_que *req = ha->req_q_map[0];
feafb7b1 4334 unsigned long flags;
1da177e4 4335
e315cd28 4336 if (vha->flags.online) {
a9083016 4337 qla2x00_abort_isp_cleanup(vha);
1da177e4 4338
a6171297
SV		 4339 if (IS_QLA8031(ha)) {
4340 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
4341 "Clearing fcoe driver presence.\n");
4342 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
4343 ql_dbg(ql_dbg_p3p, vha, 0xb073,
4344 "Error while clearing DRV-Presence.\n");
4345 }
4346
85880801
AV		 4347 if (unlikely(pci_channel_offline(ha->pdev) &&
4348 ha->flags.pci_channel_io_perm_failure)) {
4349 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4350 status = 0;
4351 return status;
4352 }
4353
73208dfd 4354 ha->isp_ops->get_flash_version(vha, req->ring);
30c47662 4355
e315cd28 4356 ha->isp_ops->nvram_config(vha);
1da177e4 4357
e315cd28
AC		 4358 if (!qla2x00_restart_isp(vha)) {
4359 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4 4360
e315cd28 4361 if (!atomic_read(&vha->loop_down_timer)) {
1da177e4
LT		 4362 /*
4363 * Issue marker command only when we are going
4364 * to start the I/O .
4365 */
e315cd28 4366 vha->marker_needed = 1;
1da177e4
LT		 4367 }
4368
e315cd28 4369 vha->flags.online = 1;
1da177e4 4370
fd34f556 4371 ha->isp_ops->enable_intrs(ha);
1da177e4 4372
fa2a1ce5 4373 ha->isp_abort_cnt = 0;
e315cd28 4374 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
476e8978 4375
6246b8a1
GM		 4376 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
4377 qla2x00_get_fw_version(vha);
df613b96
AV		 4378 if (ha->fce) {
4379 ha->flags.fce_enabled = 1;
4380 memset(ha->fce, 0,
4381 fce_calc_size(ha->fce_bufs));
e315cd28 4382 rval = qla2x00_enable_fce_trace(vha,
df613b96
AV		 4383 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
4384 &ha->fce_bufs);
4385 if (rval) {
7c3df132 4386 ql_log(ql_log_warn, vha, 0x8033,
df613b96
AV		 4387 "Unable to reinitialize FCE "
4388 "(%d).\n", rval);
4389 ha->flags.fce_enabled = 0;
4390 }
4391 }
436a7b11
AV		 4392
4393 if (ha->eft) {
4394 memset(ha->eft, 0, EFT_SIZE);
e315cd28 4395 rval = qla2x00_enable_eft_trace(vha,
436a7b11
AV		 4396 ha->eft_dma, EFT_NUM_BUFFERS);
4397 if (rval) {
7c3df132 4398 ql_log(ql_log_warn, vha, 0x8034,
436a7b11
AV		 4399 "Unable to reinitialize EFT "
4400 "(%d).\n", rval);
4401 }
4402 }
1da177e4 4403 } else { /* failed the ISP abort */
e315cd28
AC		 4404 vha->flags.online = 1;
4405 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
1da177e4 4406 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 4407 ql_log(ql_log_fatal, vha, 0x8035,
4408 "ISP error recover failed - "
4409 "board disabled.\n");
fa2a1ce5 4410 /*
1da177e4
LT		 4411 * The next call disables the board
4412 * completely.
4413 */
e315cd28
AC		 4414 ha->isp_ops->reset_adapter(vha);
4415 vha->flags.online = 0;
1da177e4 4416 clear_bit(ISP_ABORT_RETRY,
e315cd28 4417 &vha->dpc_flags);
1da177e4
LT		 4418 status = 0;
4419 } else { /* schedule another ISP abort */
4420 ha->isp_abort_cnt--;
7c3df132
SK		 4421 ql_dbg(ql_dbg_taskm, vha, 0x8020,
4422 "ISP abort - retry remaining %d.\n",
4423 ha->isp_abort_cnt);
1da177e4
LT		 4424 status = 1;
4425 }
4426 } else {
4427 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 4428 ql_dbg(ql_dbg_taskm, vha, 0x8021,
4429 "ISP error recovery - retrying (%d) "
4430 "more times.\n", ha->isp_abort_cnt);
e315cd28 4431 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1da177e4
LT		 4432 status = 1;
4433 }
4434 }
fa2a1ce5 4435
1da177e4
LT		 4436 }
4437
e315cd28 4438 if (!status) {
7c3df132 4439 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
feafb7b1
AE		 4440
4441 spin_lock_irqsave(&ha->vport_slock, flags);
4442 list_for_each_entry(vp, &ha->vp_list, list) {
4443 if (vp->vp_idx) {
4444 atomic_inc(&vp->vref_count);
4445 spin_unlock_irqrestore(&ha->vport_slock, flags);
4446
e315cd28 4447 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 4448
4449 spin_lock_irqsave(&ha->vport_slock, flags);
4450 atomic_dec(&vp->vref_count);
4451 }
e315cd28 4452 }
feafb7b1
AE		 4453 spin_unlock_irqrestore(&ha->vport_slock, flags);
4454
7d613ac6
SV		 4455 if (IS_QLA8031(ha)) {
4456 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
4457 "Setting back fcoe driver presence.\n");
4458 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
4459 ql_dbg(ql_dbg_p3p, vha, 0xb074,
4460 "Error while setting DRV-Presence.\n");
4461 }
e315cd28 4462 } else {
d8424f68
JP		 4463 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
4464 __func__);
1da177e4
LT		 4465 }
4466
4467 return(status);
4468}
4469
4470/*
4471* qla2x00_restart_isp
4472* restarts the ISP after a reset
4473*
4474* Input:
4475* ha = adapter block pointer.
4476*
4477* Returns:
4478* 0 = success
4479*/
4480static int
e315cd28 4481qla2x00_restart_isp(scsi_qla_host_t *vha)
1da177e4 4482{
c6b2fca8 4483 int status = 0;
1da177e4 4484 uint32_t wait_time;
e315cd28 4485 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 4486 struct req_que *req = ha->req_q_map[0];
4487 struct rsp_que *rsp = ha->rsp_q_map[0];
2d70c103 4488 unsigned long flags;
1da177e4
LT		 4489
4490 /* If firmware needs to be loaded */
e315cd28
AC		 4491 if (qla2x00_isp_firmware(vha)) {
4492 vha->flags.online = 0;
4493 status = ha->isp_ops->chip_diag(vha);
4494 if (!status)
4495 status = qla2x00_setup_chip(vha);
1da177e4
LT		 4496 }
4497
e315cd28
AC		 4498 if (!status && !(status = qla2x00_init_rings(vha))) {
4499 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
2533cf67 4500 ha->flags.chip_reset_done = 1;
73208dfd
AC		 4501 /* Initialize the queues in use */
4502 qla25xx_init_queues(ha);
4503
e315cd28
AC		 4504 status = qla2x00_fw_ready(vha);
4505 if (!status) {
7c3df132
SK		 4506 ql_dbg(ql_dbg_taskm, vha, 0x8031,
4507 "Start configure loop status = %d.\n", status);
0107109e
AV		 4508
4509 /* Issue a marker after FW becomes ready. */
73208dfd 4510 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
0107109e 4511
e315cd28 4512 vha->flags.online = 1;
2d70c103
NB		 4513
4514 /*
4515 * Process any ATIO queue entries that came in
4516 * while we weren't online.
4517 */
4518 spin_lock_irqsave(&ha->hardware_lock, flags);
4519 if (qla_tgt_mode_enabled(vha))
4520 qlt_24xx_process_atio_queue(vha);
4521 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4522
1da177e4
LT		 4523 /* Wait at most MAX_TARGET RSCNs for a stable link. */
4524 wait_time = 256;
4525 do {
e315cd28
AC		 4526 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
4527 qla2x00_configure_loop(vha);
1da177e4 4528 wait_time--;
e315cd28
AC		 4529 } while (!atomic_read(&vha->loop_down_timer) &&
4530 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
4531 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
4532 &vha->dpc_flags)));
1da177e4
LT		 4533 }
4534
4535 /* if no cable then assume it's good */
e315cd28 4536 if ((vha->device_flags & DFLG_NO_CABLE))
1da177e4
LT		 4537 status = 0;
4538
7c3df132
SK		 4539 ql_dbg(ql_dbg_taskm, vha, 0x8032,
4540 "Configure loop done, status = 0x%x.\n", status);
1da177e4
LT		 4541 }
4542 return (status);
4543}
4544
73208dfd
AC		 4545static int
4546qla25xx_init_queues(struct qla_hw_data *ha)
4547{
4548 struct rsp_que *rsp = NULL;
4549 struct req_que *req = NULL;
4550 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
4551 int ret = -1;
4552 int i;
4553
2afa19a9 4554 for (i = 1; i < ha->max_rsp_queues; i++) {
73208dfd
AC		 4555 rsp = ha->rsp_q_map[i];
4556 if (rsp) {
4557 rsp->options &= ~BIT_0;
618a7523 4558 ret = qla25xx_init_rsp_que(base_vha, rsp);
73208dfd 4559 if (ret != QLA_SUCCESS)
7c3df132
SK		 4560 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
4561 "%s Rsp que: %d init failed.\n",
4562 __func__, rsp->id);
73208dfd 4563 else
7c3df132
SK		 4564 ql_dbg(ql_dbg_init, base_vha, 0x0100,
4565 "%s Rsp que: %d inited.\n",
4566 __func__, rsp->id);
73208dfd 4567 }
2afa19a9
AC		 4568 }
4569 for (i = 1; i < ha->max_req_queues; i++) {
73208dfd
AC		 4570 req = ha->req_q_map[i];
4571 if (req) {
29bdccbe 4572 /* Clear outstanding commands array. */
73208dfd 4573 req->options &= ~BIT_0;
618a7523 4574 ret = qla25xx_init_req_que(base_vha, req);
73208dfd 4575 if (ret != QLA_SUCCESS)
7c3df132
SK		 4576 ql_dbg(ql_dbg_init, base_vha, 0x0101,
4577 "%s Req que: %d init failed.\n",
4578 __func__, req->id);
73208dfd 4579 else
7c3df132
SK		 4580 ql_dbg(ql_dbg_init, base_vha, 0x0102,
4581 "%s Req que: %d inited.\n",
4582 __func__, req->id);
73208dfd
AC		 4583 }
4584 }
4585 return ret;
4586}
4587
1da177e4
LT		 4588/*
4589* qla2x00_reset_adapter
4590* Reset adapter.
4591*
4592* Input:
4593* ha = adapter block pointer.
4594*/
abbd8870 4595void
e315cd28 4596qla2x00_reset_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 4597{
4598 unsigned long flags = 0;
e315cd28 4599 struct qla_hw_data *ha = vha->hw;
3d71644c 4600 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 4601
e315cd28 4602 vha->flags.online = 0;
fd34f556 4603 ha->isp_ops->disable_intrs(ha);
1da177e4 4604
1da177e4
LT		 4605 spin_lock_irqsave(&ha->hardware_lock, flags);
4606 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
4607 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4608 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
4609 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4610 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4611}
0107109e
AV		 4612
4613void
e315cd28 4614qla24xx_reset_adapter(scsi_qla_host_t *vha)
0107109e
AV		 4615{
4616 unsigned long flags = 0;
e315cd28 4617 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 4618 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
4619
a9083016
GM		 4620 if (IS_QLA82XX(ha))
4621 return;
4622
e315cd28 4623 vha->flags.online = 0;
fd34f556 4624 ha->isp_ops->disable_intrs(ha);
0107109e
AV		 4625
4626 spin_lock_irqsave(&ha->hardware_lock, flags);
4627 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
4628 RD_REG_DWORD(&reg->hccr);
4629 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
4630 RD_REG_DWORD(&reg->hccr);
4631 spin_unlock_irqrestore(&ha->hardware_lock, flags);
09ff36d3
AV		 4632
4633 if (IS_NOPOLLING_TYPE(ha))
4634 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 4635}
4636
4e08df3f
DM		 4637/* On sparc systems, obtain port and node WWN from firmware
4638 * properties.
4639 */
e315cd28
AC		 4640static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
4641 struct nvram_24xx *nv)
4e08df3f
DM		 4642{
4643#ifdef CONFIG_SPARC
e315cd28 4644 struct qla_hw_data *ha = vha->hw;
4e08df3f 4645 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 4646 struct device_node *dp = pci_device_to_OF_node(pdev);
4647 const u8 *val;
4e08df3f
DM		 4648 int len;
4649
4650 val = of_get_property(dp, "port-wwn", &len);
4651 if (val && len >= WWN_SIZE)
4652 memcpy(nv->port_name, val, WWN_SIZE);
4653
4654 val = of_get_property(dp, "node-wwn", &len);
4655 if (val && len >= WWN_SIZE)
4656 memcpy(nv->node_name, val, WWN_SIZE);
4657#endif
4658}
4659
0107109e 4660int
e315cd28 4661qla24xx_nvram_config(scsi_qla_host_t *vha)
0107109e 4662{
4e08df3f 4663 int rval;
0107109e
AV		 4664 struct init_cb_24xx *icb;
4665 struct nvram_24xx *nv;
4666 uint32_t *dptr;
4667 uint8_t *dptr1, *dptr2;
4668 uint32_t chksum;
4669 uint16_t cnt;
e315cd28 4670 struct qla_hw_data *ha = vha->hw;
0107109e 4671
4e08df3f 4672 rval = QLA_SUCCESS;
0107109e 4673 icb = (struct init_cb_24xx *)ha->init_cb;
281afe19 4674 nv = ha->nvram;
0107109e
AV		 4675
4676 /* Determine NVRAM starting address. */
e5b68a61
AC		 4677 if (ha->flags.port0) {
4678 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
4679 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
4680 } else {
0107109e 4681 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
6f641790 4682 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
4683 }
e5b68a61
AC		 4684 ha->nvram_size = sizeof(struct nvram_24xx);
4685 ha->vpd_size = FA_NVRAM_VPD_SIZE;
a9083016
GM		 4686 if (IS_QLA82XX(ha))
4687 ha->vpd_size = FA_VPD_SIZE_82XX;
0107109e 4688
281afe19
SJ		 4689 /* Get VPD data into cache */
4690 ha->vpd = ha->nvram + VPD_OFFSET;
e315cd28 4691 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
281afe19
SJ		 4692 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
4693
4694 /* Get NVRAM data into cache and calculate checksum. */
0107109e 4695 dptr = (uint32_t *)nv;
e315cd28 4696 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
0107109e
AV		 4697 ha->nvram_size);
4698 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
4699 chksum += le32_to_cpu(*dptr++);
4700
7c3df132
SK		 4701 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
4702 "Contents of NVRAM\n");
4703 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
4704 (uint8_t *)nv, ha->nvram_size);
0107109e
AV		 4705
4706 /* Bad NVRAM data, set defaults parameters. */
4707 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
4708 || nv->id[3] != ' ' ||
4709 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
4710 /* Reset NVRAM data. */
7c3df132 4711 ql_log(ql_log_warn, vha, 0x006b,
9e336520 4712 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132
SK		 4713 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
4714 ql_log(ql_log_warn, vha, 0x006c,
4715 "Falling back to functioning (yet invalid -- WWPN) "
4716 "defaults.\n");
4e08df3f
DM		 4717
4718 /*
4719 * Set default initialization control block.
4720 */
4721 memset(nv, 0, ha->nvram_size);
4722 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
4723 nv->version = __constant_cpu_to_le16(ICB_VERSION);
4724 nv->frame_payload_size = __constant_cpu_to_le16(2048);
4725 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4726 nv->exchange_count = __constant_cpu_to_le16(0);
4727 nv->hard_address = __constant_cpu_to_le16(124);
4728 nv->port_name[0] = 0x21;
e5b68a61 4729 nv->port_name[1] = 0x00 + ha->port_no;
4e08df3f
DM		 4730 nv->port_name[2] = 0x00;
4731 nv->port_name[3] = 0xe0;
4732 nv->port_name[4] = 0x8b;
4733 nv->port_name[5] = 0x1c;
4734 nv->port_name[6] = 0x55;
4735 nv->port_name[7] = 0x86;
4736 nv->node_name[0] = 0x20;
4737 nv->node_name[1] = 0x00;
4738 nv->node_name[2] = 0x00;
4739 nv->node_name[3] = 0xe0;
4740 nv->node_name[4] = 0x8b;
4741 nv->node_name[5] = 0x1c;
4742 nv->node_name[6] = 0x55;
4743 nv->node_name[7] = 0x86;
e315cd28 4744 qla24xx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 4745 nv->login_retry_count = __constant_cpu_to_le16(8);
4746 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
4747 nv->login_timeout = __constant_cpu_to_le16(0);
4748 nv->firmware_options_1 =
4749 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
4750 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
4751 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
4752 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
4753 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
4754 nv->efi_parameters = __constant_cpu_to_le32(0);
4755 nv->reset_delay = 5;
4756 nv->max_luns_per_target = __constant_cpu_to_le16(128);
4757 nv->port_down_retry_count = __constant_cpu_to_le16(30);
4758 nv->link_down_timeout = __constant_cpu_to_le16(30);
4759
4760 rval = 1;
0107109e
AV		 4761 }
4762
2d70c103
NB		 4763 if (!qla_ini_mode_enabled(vha)) {
4764 /* Don't enable full login after initial LIP */
4765 nv->firmware_options_1 &= __constant_cpu_to_le32(~BIT_13);
4766 /* Don't enable LIP full login for initiator */
4767 nv->host_p &= __constant_cpu_to_le32(~BIT_10);
4768 }
4769
4770 qlt_24xx_config_nvram_stage1(vha, nv);
4771
0107109e 4772 /* Reset Initialization control block */
e315cd28 4773 memset(icb, 0, ha->init_cb_size);
0107109e
AV		 4774
4775 /* Copy 1st segment. */
4776 dptr1 = (uint8_t *)icb;
4777 dptr2 = (uint8_t *)&nv->version;
4778 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
4779 while (cnt--)
4780 *dptr1++ = *dptr2++;
4781
4782 icb->login_retry_count = nv->login_retry_count;
3ea66e28 4783 icb->link_down_on_nos = nv->link_down_on_nos;
0107109e
AV		 4784
4785 /* Copy 2nd segment. */
4786 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
4787 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
4788 cnt = (uint8_t *)&icb->reserved_3 -
4789 (uint8_t *)&icb->interrupt_delay_timer;
4790 while (cnt--)
4791 *dptr1++ = *dptr2++;
4792
4793 /*
4794 * Setup driver NVRAM options.
4795 */
e315cd28 4796 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9bb9fcf2 4797 "QLA2462");
0107109e 4798
2d70c103
NB		 4799 qlt_24xx_config_nvram_stage2(vha, icb);
4800
5341e868 4801 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
2d70c103 4802 /* Use alternate WWN? */
5341e868
AV		 4803 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
4804 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
4805 }
4806
0107109e 4807 /* Prepare nodename */
fd0e7e4d 4808 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
0107109e
AV		 4809 /*
4810 * Firmware will apply the following mask if the nodename was
4811 * not provided.
4812 */
4813 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
4814 icb->node_name[0] &= 0xF0;
4815 }
4816
4817 /* Set host adapter parameters. */
4818 ha->flags.disable_risc_code_load = 0;
0c8c39af
AV		 4819 ha->flags.enable_lip_reset = 0;
4820 ha->flags.enable_lip_full_login =
4821 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
4822 ha->flags.enable_target_reset =
4823 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
0107109e 4824 ha->flags.enable_led_scheme = 0;
d4c760c2 4825 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
0107109e 4826
fd0e7e4d
AV		 4827 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
4828 (BIT_6 | BIT_5 | BIT_4)) >> 4;
0107109e
AV		 4829
4830 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
4831 sizeof(ha->fw_seriallink_options24));
4832
4833 /* save HBA serial number */
4834 ha->serial0 = icb->port_name[5];
4835 ha->serial1 = icb->port_name[6];
4836 ha->serial2 = icb->port_name[7];
e315cd28
AC		 4837 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
4838 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
0107109e 4839
bc8fb3cb 4840 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4841
0107109e
AV		 4842 ha->retry_count = le16_to_cpu(nv->login_retry_count);
4843
4844 /* Set minimum login_timeout to 4 seconds. */
4845 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
4846 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
4847 if (le16_to_cpu(nv->login_timeout) < 4)
4848 nv->login_timeout = __constant_cpu_to_le16(4);
4849 ha->login_timeout = le16_to_cpu(nv->login_timeout);
c6852c4c 4850 icb->login_timeout = nv->login_timeout;
0107109e 4851
00a537b8
AV		 4852 /* Set minimum RATOV to 100 tenths of a second. */
4853 ha->r_a_tov = 100;
0107109e
AV		 4854
4855 ha->loop_reset_delay = nv->reset_delay;
4856
4857 /* Link Down Timeout = 0:
4858 *
4859 * When Port Down timer expires we will start returning
4860 * I/O's to OS with "DID_NO_CONNECT".
4861 *
4862 * Link Down Timeout != 0:
4863 *
4864 * The driver waits for the link to come up after link down
4865 * before returning I/Os to OS with "DID_NO_CONNECT".
4866 */
4867 if (le16_to_cpu(nv->link_down_timeout) == 0) {
4868 ha->loop_down_abort_time =
4869 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
4870 } else {
4871 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
4872 ha->loop_down_abort_time =
4873 (LOOP_DOWN_TIME - ha->link_down_timeout);
4874 }
4875
4876 /* Need enough time to try and get the port back. */
4877 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
4878 if (qlport_down_retry)
4879 ha->port_down_retry_count = qlport_down_retry;
4880
4881 /* Set login_retry_count */
4882 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
4883 if (ha->port_down_retry_count ==
4884 le16_to_cpu(nv->port_down_retry_count) &&
4885 ha->port_down_retry_count > 3)
4886 ha->login_retry_count = ha->port_down_retry_count;
4887 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
4888 ha->login_retry_count = ha->port_down_retry_count;
4889 if (ql2xloginretrycount)
4890 ha->login_retry_count = ql2xloginretrycount;
4891
4fdfefe5 4892 /* Enable ZIO. */
e315cd28 4893 if (!vha->flags.init_done) {
4fdfefe5
AV		 4894 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
4895 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
4896 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
4897 le16_to_cpu(icb->interrupt_delay_timer): 2;
4898 }
4899 icb->firmware_options_2 &= __constant_cpu_to_le32(
4900 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
e315cd28 4901 vha->flags.process_response_queue = 0;
4fdfefe5 4902 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d 4903 ha->zio_mode = QLA_ZIO_MODE_6;
4904
7c3df132 4905 ql_log(ql_log_info, vha, 0x006f,
4fdfefe5
AV		 4906 "ZIO mode %d enabled; timer delay (%d us).\n",
4907 ha->zio_mode, ha->zio_timer * 100);
4908
4909 icb->firmware_options_2 |= cpu_to_le32(
4910 (uint32_t)ha->zio_mode);
4911 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
e315cd28 4912 vha->flags.process_response_queue = 1;
4fdfefe5
AV		 4913 }
4914
4e08df3f 4915 if (rval) {
7c3df132
SK		 4916 ql_log(ql_log_warn, vha, 0x0070,
4917 "NVRAM configuration failed.\n");
4e08df3f
DM		 4918 }
4919 return (rval);
0107109e
AV		 4920}
4921
413975a0 4922static int
cbc8eb67
AV		 4923qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
4924 uint32_t faddr)
d1c61909 4925{
73208dfd 4926 int rval = QLA_SUCCESS;
d1c61909 4927 int segments, fragment;
d1c61909
AV		 4928 uint32_t *dcode, dlen;
4929 uint32_t risc_addr;
4930 uint32_t risc_size;
4931 uint32_t i;
e315cd28 4932 struct qla_hw_data *ha = vha->hw;
73208dfd 4933 struct req_que *req = ha->req_q_map[0];
eaac30be 4934
7c3df132 4935 ql_dbg(ql_dbg_init, vha, 0x008b,
cfb0919c 4936 "FW: Loading firmware from flash (%x).\n", faddr);
eaac30be 4937
d1c61909
AV		 4938 rval = QLA_SUCCESS;
4939
4940 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 4941 dcode = (uint32_t *)req->ring;
d1c61909
AV		 4942 *srisc_addr = 0;
4943
4944 /* Validate firmware image by checking version. */
e315cd28 4945 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
d1c61909
AV		 4946 for (i = 0; i < 4; i++)
4947 dcode[i] = be32_to_cpu(dcode[i]);
4948 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
4949 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
4950 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
4951 dcode[3] == 0)) {
7c3df132
SK		 4952 ql_log(ql_log_fatal, vha, 0x008c,
4953 "Unable to verify the integrity of flash firmware "
4954 "image.\n");
4955 ql_log(ql_log_fatal, vha, 0x008d,
4956 "Firmware data: %08x %08x %08x %08x.\n",
4957 dcode[0], dcode[1], dcode[2], dcode[3]);
d1c61909
AV		 4958
4959 return QLA_FUNCTION_FAILED;
4960 }
4961
4962 while (segments && rval == QLA_SUCCESS) {
4963 /* Read segment's load information. */
e315cd28 4964 qla24xx_read_flash_data(vha, dcode, faddr, 4);
d1c61909
AV		 4965
4966 risc_addr = be32_to_cpu(dcode[2]);
4967 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
4968 risc_size = be32_to_cpu(dcode[3]);
4969
4970 fragment = 0;
4971 while (risc_size > 0 && rval == QLA_SUCCESS) {
4972 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
4973 if (dlen > risc_size)
4974 dlen = risc_size;
4975
7c3df132
SK		 4976 ql_dbg(ql_dbg_init, vha, 0x008e,
4977 "Loading risc segment@ risc addr %x "
4978 "number of dwords 0x%x offset 0x%x.\n",
4979 risc_addr, dlen, faddr);
d1c61909 4980
e315cd28 4981 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
d1c61909
AV		 4982 for (i = 0; i < dlen; i++)
4983 dcode[i] = swab32(dcode[i]);
4984
73208dfd 4985 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
d1c61909
AV		 4986 dlen);
4987 if (rval) {
7c3df132
SK		 4988 ql_log(ql_log_fatal, vha, 0x008f,
4989 "Failed to load segment %d of firmware.\n",
4990 fragment);
d1c61909
AV		 4991 break;
4992 }
4993
4994 faddr += dlen;
4995 risc_addr += dlen;
4996 risc_size -= dlen;
4997 fragment++;
4998 }
4999
5000 /* Next segment. */
5001 segments--;
5002 }
5003
5004 return rval;
5005}
5006
d1c61909
AV		 5007#define QLA_FW_URL "ftp://ftp.qlogic.com/outgoing/linux/firmware/"
5008
0107109e 5009int
e315cd28 5010qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5433383e
AV		 5011{
5012 int rval;
5013 int i, fragment;
5014 uint16_t *wcode, *fwcode;
5015 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
5016 struct fw_blob *blob;
e315cd28 5017 struct qla_hw_data *ha = vha->hw;
73208dfd 5018 struct req_que *req = ha->req_q_map[0];
5433383e
AV		 5019
5020 /* Load firmware blob. */
e315cd28 5021 blob = qla2x00_request_firmware(vha);
5433383e 5022 if (!blob) {
7c3df132
SK		 5023 ql_log(ql_log_info, vha, 0x0083,
5024 "Fimware image unavailable.\n");
5025 ql_log(ql_log_info, vha, 0x0084,
5026 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5433383e
AV		 5027 return QLA_FUNCTION_FAILED;
5028 }
5029
5030 rval = QLA_SUCCESS;
5031
73208dfd 5032 wcode = (uint16_t *)req->ring;
5433383e
AV		 5033 *srisc_addr = 0;
5034 fwcode = (uint16_t *)blob->fw->data;
5035 fwclen = 0;
5036
5037 /* Validate firmware image by checking version. */
5038 if (blob->fw->size < 8 * sizeof(uint16_t)) {
7c3df132
SK		 5039 ql_log(ql_log_fatal, vha, 0x0085,
5040 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e
AV		 5041 blob->fw->size);
5042 goto fail_fw_integrity;
5043 }
5044 for (i = 0; i < 4; i++)
5045 wcode[i] = be16_to_cpu(fwcode[i + 4]);
5046 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
5047 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
5048 wcode[2] == 0 && wcode[3] == 0)) {
7c3df132
SK		 5049 ql_log(ql_log_fatal, vha, 0x0086,
5050 "Unable to verify integrity of firmware image.\n");
5051 ql_log(ql_log_fatal, vha, 0x0087,
5052 "Firmware data: %04x %04x %04x %04x.\n",
5053 wcode[0], wcode[1], wcode[2], wcode[3]);
5433383e
AV		 5054 goto fail_fw_integrity;
5055 }
5056
5057 seg = blob->segs;
5058 while (*seg && rval == QLA_SUCCESS) {
5059 risc_addr = *seg;
5060 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
5061 risc_size = be16_to_cpu(fwcode[3]);
5062
5063 /* Validate firmware image size. */
5064 fwclen += risc_size * sizeof(uint16_t);
5065 if (blob->fw->size < fwclen) {
7c3df132 5066 ql_log(ql_log_fatal, vha, 0x0088,
5433383e 5067 "Unable to verify integrity of firmware image "
7c3df132 5068 "(%Zd).\n", blob->fw->size);
5433383e
AV		 5069 goto fail_fw_integrity;
5070 }
5071
5072 fragment = 0;
5073 while (risc_size > 0 && rval == QLA_SUCCESS) {
5074 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
5075 if (wlen > risc_size)
5076 wlen = risc_size;
7c3df132
SK		 5077 ql_dbg(ql_dbg_init, vha, 0x0089,
5078 "Loading risc segment@ risc addr %x number of "
5079 "words 0x%x.\n", risc_addr, wlen);
5433383e
AV		 5080
5081 for (i = 0; i < wlen; i++)
5082 wcode[i] = swab16(fwcode[i]);
5083
73208dfd 5084 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5433383e
AV		 5085 wlen);
5086 if (rval) {
7c3df132
SK		 5087 ql_log(ql_log_fatal, vha, 0x008a,
5088 "Failed to load segment %d of firmware.\n",
5089 fragment);
5433383e
AV		 5090 break;
5091 }
5092
5093 fwcode += wlen;
5094 risc_addr += wlen;
5095 risc_size -= wlen;
5096 fragment++;
5097 }
5098
5099 /* Next segment. */
5100 seg++;
5101 }
5102 return rval;
5103
5104fail_fw_integrity:
5105 return QLA_FUNCTION_FAILED;
5106}
5107
eaac30be
AV		 5108static int
5109qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
0107109e
AV		 5110{
5111 int rval;
5112 int segments, fragment;
5113 uint32_t *dcode, dlen;
5114 uint32_t risc_addr;
5115 uint32_t risc_size;
5116 uint32_t i;
5433383e 5117 struct fw_blob *blob;
0107109e 5118 uint32_t *fwcode, fwclen;
e315cd28 5119 struct qla_hw_data *ha = vha->hw;
73208dfd 5120 struct req_que *req = ha->req_q_map[0];
0107109e 5121
5433383e 5122 /* Load firmware blob. */
e315cd28 5123 blob = qla2x00_request_firmware(vha);
5433383e 5124 if (!blob) {
7c3df132
SK		 5125 ql_log(ql_log_warn, vha, 0x0090,
5126 "Fimware image unavailable.\n");
5127 ql_log(ql_log_warn, vha, 0x0091,
5128 "Firmware images can be retrieved from: "
5129 QLA_FW_URL ".\n");
d1c61909 5130
eaac30be 5131 return QLA_FUNCTION_FAILED;
0107109e
AV		 5132 }
5133
cfb0919c
CD		 5134 ql_dbg(ql_dbg_init, vha, 0x0092,
5135 "FW: Loading via request-firmware.\n");
eaac30be 5136
0107109e
AV		 5137 rval = QLA_SUCCESS;
5138
5139 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5140 dcode = (uint32_t *)req->ring;
0107109e 5141 *srisc_addr = 0;
5433383e 5142 fwcode = (uint32_t *)blob->fw->data;
0107109e
AV		 5143 fwclen = 0;
5144
5145 /* Validate firmware image by checking version. */
5433383e 5146 if (blob->fw->size < 8 * sizeof(uint32_t)) {
7c3df132
SK		 5147 ql_log(ql_log_fatal, vha, 0x0093,
5148 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e 5149 blob->fw->size);
0107109e
AV		 5150 goto fail_fw_integrity;
5151 }
5152 for (i = 0; i < 4; i++)
5153 dcode[i] = be32_to_cpu(fwcode[i + 4]);
5154 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5155 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5156 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5157 dcode[3] == 0)) {
7c3df132
SK		 5158 ql_log(ql_log_fatal, vha, 0x0094,
5159 "Unable to verify integrity of firmware image (%Zd).\n",
5160 blob->fw->size);
5161 ql_log(ql_log_fatal, vha, 0x0095,
5162 "Firmware data: %08x %08x %08x %08x.\n",
5163 dcode[0], dcode[1], dcode[2], dcode[3]);
0107109e
AV		 5164 goto fail_fw_integrity;
5165 }
5166
5167 while (segments && rval == QLA_SUCCESS) {
5168 risc_addr = be32_to_cpu(fwcode[2]);
5169 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5170 risc_size = be32_to_cpu(fwcode[3]);
5171
5172 /* Validate firmware image size. */
5173 fwclen += risc_size * sizeof(uint32_t);
5433383e 5174 if (blob->fw->size < fwclen) {
7c3df132 5175 ql_log(ql_log_fatal, vha, 0x0096,
5433383e 5176 "Unable to verify integrity of firmware image "
7c3df132 5177 "(%Zd).\n", blob->fw->size);
5433383e 5178
0107109e
AV		 5179 goto fail_fw_integrity;
5180 }
5181
5182 fragment = 0;
5183 while (risc_size > 0 && rval == QLA_SUCCESS) {
5184 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5185 if (dlen > risc_size)
5186 dlen = risc_size;
5187
7c3df132
SK		 5188 ql_dbg(ql_dbg_init, vha, 0x0097,
5189 "Loading risc segment@ risc addr %x "
5190 "number of dwords 0x%x.\n", risc_addr, dlen);
0107109e
AV		 5191
5192 for (i = 0; i < dlen; i++)
5193 dcode[i] = swab32(fwcode[i]);
5194
73208dfd 5195 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
590f98e5 5196 dlen);
0107109e 5197 if (rval) {
7c3df132
SK		 5198 ql_log(ql_log_fatal, vha, 0x0098,
5199 "Failed to load segment %d of firmware.\n",
5200 fragment);
0107109e
AV		 5201 break;
5202 }
5203
5204 fwcode += dlen;
5205 risc_addr += dlen;
5206 risc_size -= dlen;
5207 fragment++;
5208 }
5209
5210 /* Next segment. */
5211 segments--;
5212 }
0107109e
AV		 5213 return rval;
5214
5215fail_fw_integrity:
0107109e 5216 return QLA_FUNCTION_FAILED;
0107109e 5217}
18c6c127 5218
eaac30be
AV		 5219int
5220qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5221{
5222 int rval;
5223
e337d907
AV		 5224 if (ql2xfwloadbin == 1)
5225 return qla81xx_load_risc(vha, srisc_addr);
5226
eaac30be
AV		 5227 /*
5228 * FW Load priority:
5229 * 1) Firmware via request-firmware interface (.bin file).
5230 * 2) Firmware residing in flash.
5231 */
5232 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5233 if (rval == QLA_SUCCESS)
5234 return rval;
5235
cbc8eb67
AV		 5236 return qla24xx_load_risc_flash(vha, srisc_addr,
5237 vha->hw->flt_region_fw);
eaac30be
AV		 5238}
5239
5240int
5241qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5242{
5243 int rval;
cbc8eb67 5244 struct qla_hw_data *ha = vha->hw;
eaac30be 5245
e337d907 5246 if (ql2xfwloadbin == 2)
cbc8eb67 5247 goto try_blob_fw;
e337d907 5248
eaac30be
AV		 5249 /*
5250 * FW Load priority:
5251 * 1) Firmware residing in flash.
5252 * 2) Firmware via request-firmware interface (.bin file).
cbc8eb67 5253 * 3) Golden-Firmware residing in flash -- limited operation.
eaac30be 5254 */
cbc8eb67 5255 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
eaac30be
AV		 5256 if (rval == QLA_SUCCESS)
5257 return rval;
5258
cbc8eb67
AV		 5259try_blob_fw:
5260 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5261 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
5262 return rval;
5263
7c3df132
SK		 5264 ql_log(ql_log_info, vha, 0x0099,
5265 "Attempting to fallback to golden firmware.\n");
cbc8eb67
AV		 5266 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
5267 if (rval != QLA_SUCCESS)
5268 return rval;
5269
7c3df132 5270 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
cbc8eb67 5271 ha->flags.running_gold_fw = 1;
cbc8eb67 5272 return rval;
eaac30be
AV		 5273}
5274
18c6c127 5275void
e315cd28 5276qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
18c6c127
AV		 5277{
5278 int ret, retries;
e315cd28 5279 struct qla_hw_data *ha = vha->hw;
18c6c127 5280
85880801
AV		 5281 if (ha->flags.pci_channel_io_perm_failure)
5282 return;
e428924c 5283 if (!IS_FWI2_CAPABLE(ha))
18c6c127 5284 return;
75edf81d
AV		 5285 if (!ha->fw_major_version)
5286 return;
18c6c127 5287
e315cd28 5288 ret = qla2x00_stop_firmware(vha);
7c7f1f29 5289 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
b469a7cb 5290 ret != QLA_INVALID_COMMAND && retries ; retries--) {
e315cd28
AC		 5291 ha->isp_ops->reset_chip(vha);
5292 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
18c6c127 5293 continue;
e315cd28 5294 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
18c6c127 5295 continue;
7c3df132
SK		 5296 ql_log(ql_log_info, vha, 0x8015,
5297 "Attempting retry of stop-firmware command.\n");
e315cd28 5298 ret = qla2x00_stop_firmware(vha);
18c6c127
AV		 5299 }
5300}
2c3dfe3f
SJ		 5301
5302int
e315cd28 5303qla24xx_configure_vhba(scsi_qla_host_t *vha)
2c3dfe3f
SJ		 5304{
5305 int rval = QLA_SUCCESS;
0b91d116 5306 int rval2;
2c3dfe3f 5307 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28
AC		 5308 struct qla_hw_data *ha = vha->hw;
5309 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
67c2e93a
AC		 5310 struct req_que *req;
5311 struct rsp_que *rsp;
2c3dfe3f 5312
e315cd28 5313 if (!vha->vp_idx)
2c3dfe3f
SJ		 5314 return -EINVAL;
5315
e315cd28 5316 rval = qla2x00_fw_ready(base_vha);
7163ea81 5317 if (ha->flags.cpu_affinity_enabled)
67c2e93a
AC		 5318 req = ha->req_q_map[0];
5319 else
5320 req = vha->req;
5321 rsp = req->rsp;
5322
2c3dfe3f 5323 if (rval == QLA_SUCCESS) {
e315cd28 5324 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
73208dfd 5325 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
2c3dfe3f
SJ		 5326 }
5327
e315cd28 5328 vha->flags.management_server_logged_in = 0;
2c3dfe3f
SJ		 5329
5330 /* Login to SNS first */
0b91d116
CD		 5331 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
5332 BIT_1);
5333 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
5334 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
5335 ql_dbg(ql_dbg_init, vha, 0x0120,
5336 "Failed SNS login: loop_id=%x, rval2=%d\n",
5337 NPH_SNS, rval2);
5338 else
5339 ql_dbg(ql_dbg_init, vha, 0x0103,
5340 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
5341 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
5342 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
2c3dfe3f
SJ		 5343 return (QLA_FUNCTION_FAILED);
5344 }
5345
e315cd28
AC		 5346 atomic_set(&vha->loop_down_timer, 0);
5347 atomic_set(&vha->loop_state, LOOP_UP);
5348 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5349 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5350 rval = qla2x00_loop_resync(base_vha);
2c3dfe3f
SJ		 5351
5352 return rval;
5353}
4d4df193
HK		 5354
5355/* 84XX Support **************************************************************/
5356
5357static LIST_HEAD(qla_cs84xx_list);
5358static DEFINE_MUTEX(qla_cs84xx_mutex);
5359
5360static struct qla_chip_state_84xx *
e315cd28 5361qla84xx_get_chip(struct scsi_qla_host *vha)
4d4df193
HK		 5362{
5363 struct qla_chip_state_84xx *cs84xx;
e315cd28 5364 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5365
5366 mutex_lock(&qla_cs84xx_mutex);
5367
5368 /* Find any shared 84xx chip. */
5369 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
5370 if (cs84xx->bus == ha->pdev->bus) {
5371 kref_get(&cs84xx->kref);
5372 goto done;
5373 }
5374 }
5375
5376 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
5377 if (!cs84xx)
5378 goto done;
5379
5380 kref_init(&cs84xx->kref);
5381 spin_lock_init(&cs84xx->access_lock);
5382 mutex_init(&cs84xx->fw_update_mutex);
5383 cs84xx->bus = ha->pdev->bus;
5384
5385 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
5386done:
5387 mutex_unlock(&qla_cs84xx_mutex);
5388 return cs84xx;
5389}
5390
5391static void
5392__qla84xx_chip_release(struct kref *kref)
5393{
5394 struct qla_chip_state_84xx *cs84xx =
5395 container_of(kref, struct qla_chip_state_84xx, kref);
5396
5397 mutex_lock(&qla_cs84xx_mutex);
5398 list_del(&cs84xx->list);
5399 mutex_unlock(&qla_cs84xx_mutex);
5400 kfree(cs84xx);
5401}
5402
5403void
e315cd28 5404qla84xx_put_chip(struct scsi_qla_host *vha)
4d4df193 5405{
e315cd28 5406 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5407 if (ha->cs84xx)
5408 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
5409}
5410
5411static int
e315cd28 5412qla84xx_init_chip(scsi_qla_host_t *vha)
4d4df193
HK		 5413{
5414 int rval;
5415 uint16_t status[2];
e315cd28 5416 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5417
5418 mutex_lock(&ha->cs84xx->fw_update_mutex);
5419
e315cd28 5420 rval = qla84xx_verify_chip(vha, status);
4d4df193
HK		 5421
5422 mutex_unlock(&ha->cs84xx->fw_update_mutex);
5423
5424 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
5425 QLA_SUCCESS;
5426}
3a03eb79
AV		 5427
5428/* 81XX Support **************************************************************/
5429
5430int
5431qla81xx_nvram_config(scsi_qla_host_t *vha)
5432{
5433 int rval;
5434 struct init_cb_81xx *icb;
5435 struct nvram_81xx *nv;
5436 uint32_t *dptr;
5437 uint8_t *dptr1, *dptr2;
5438 uint32_t chksum;
5439 uint16_t cnt;
5440 struct qla_hw_data *ha = vha->hw;
5441
5442 rval = QLA_SUCCESS;
5443 icb = (struct init_cb_81xx *)ha->init_cb;
5444 nv = ha->nvram;
5445
5446 /* Determine NVRAM starting address. */
5447 ha->nvram_size = sizeof(struct nvram_81xx);
3a03eb79 5448 ha->vpd_size = FA_NVRAM_VPD_SIZE;
3a03eb79
AV		 5449
5450 /* Get VPD data into cache */
5451 ha->vpd = ha->nvram + VPD_OFFSET;
3d79038f
AV		 5452 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
5453 ha->vpd_size);
3a03eb79
AV		 5454
5455 /* Get NVRAM data into cache and calculate checksum. */
3d79038f 5456 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
3a03eb79 5457 ha->nvram_size);
3d79038f 5458 dptr = (uint32_t *)nv;
3a03eb79
AV		 5459 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
5460 chksum += le32_to_cpu(*dptr++);
5461
7c3df132
SK		 5462 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
5463 "Contents of NVRAM:\n");
5464 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
5465 (uint8_t *)nv, ha->nvram_size);
3a03eb79
AV		 5466
5467 /* Bad NVRAM data, set defaults parameters. */
5468 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
5469 || nv->id[3] != ' ' ||
5470 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
5471 /* Reset NVRAM data. */
7c3df132 5472 ql_log(ql_log_info, vha, 0x0073,
9e336520 5473 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132 5474 "version=0x%x.\n", chksum, nv->id[0],
3a03eb79 5475 le16_to_cpu(nv->nvram_version));
7c3df132
SK		 5476 ql_log(ql_log_info, vha, 0x0074,
5477 "Falling back to functioning (yet invalid -- WWPN) "
5478 "defaults.\n");
3a03eb79
AV		 5479
5480 /*
5481 * Set default initialization control block.
5482 */
5483 memset(nv, 0, ha->nvram_size);
5484 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
5485 nv->version = __constant_cpu_to_le16(ICB_VERSION);
5486 nv->frame_payload_size = __constant_cpu_to_le16(2048);
5487 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5488 nv->exchange_count = __constant_cpu_to_le16(0);
5489 nv->port_name[0] = 0x21;
e5b68a61 5490 nv->port_name[1] = 0x00 + ha->port_no;
3a03eb79
AV		 5491 nv->port_name[2] = 0x00;
5492 nv->port_name[3] = 0xe0;
5493 nv->port_name[4] = 0x8b;
5494 nv->port_name[5] = 0x1c;
5495 nv->port_name[6] = 0x55;
5496 nv->port_name[7] = 0x86;
5497 nv->node_name[0] = 0x20;
5498 nv->node_name[1] = 0x00;
5499 nv->node_name[2] = 0x00;
5500 nv->node_name[3] = 0xe0;
5501 nv->node_name[4] = 0x8b;
5502 nv->node_name[5] = 0x1c;
5503 nv->node_name[6] = 0x55;
5504 nv->node_name[7] = 0x86;
5505 nv->login_retry_count = __constant_cpu_to_le16(8);
5506 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
5507 nv->login_timeout = __constant_cpu_to_le16(0);
5508 nv->firmware_options_1 =
5509 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
5510 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
5511 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
5512 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
5513 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
5514 nv->efi_parameters = __constant_cpu_to_le32(0);
5515 nv->reset_delay = 5;
5516 nv->max_luns_per_target = __constant_cpu_to_le16(128);
5517 nv->port_down_retry_count = __constant_cpu_to_le16(30);
6246b8a1 5518 nv->link_down_timeout = __constant_cpu_to_le16(180);
eeebcc92 5519 nv->enode_mac[0] = 0x00;
6246b8a1
GM		 5520 nv->enode_mac[1] = 0xC0;
5521 nv->enode_mac[2] = 0xDD;
3a03eb79
AV		 5522 nv->enode_mac[3] = 0x04;
5523 nv->enode_mac[4] = 0x05;
e5b68a61 5524 nv->enode_mac[5] = 0x06 + ha->port_no;
3a03eb79
AV		 5525
5526 rval = 1;
5527 }
5528
9e522cd8
AE		 5529 if (IS_T10_PI_CAPABLE(ha))
5530 nv->frame_payload_size &= ~7;
5531
3a03eb79 5532 /* Reset Initialization control block */
773120e4 5533 memset(icb, 0, ha->init_cb_size);
3a03eb79
AV		 5534
5535 /* Copy 1st segment. */
5536 dptr1 = (uint8_t *)icb;
5537 dptr2 = (uint8_t *)&nv->version;
5538 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
5539 while (cnt--)
5540 *dptr1++ = *dptr2++;
5541
5542 icb->login_retry_count = nv->login_retry_count;
5543
5544 /* Copy 2nd segment. */
5545 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
5546 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
5547 cnt = (uint8_t *)&icb->reserved_5 -
5548 (uint8_t *)&icb->interrupt_delay_timer;
5549 while (cnt--)
5550 *dptr1++ = *dptr2++;
5551
5552 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
5553 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
5554 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
69e5f1ea
AV		 5555 icb->enode_mac[0] = 0x00;
5556 icb->enode_mac[1] = 0xC0;
5557 icb->enode_mac[2] = 0xDD;
3a03eb79
AV		 5558 icb->enode_mac[3] = 0x04;
5559 icb->enode_mac[4] = 0x05;
e5b68a61 5560 icb->enode_mac[5] = 0x06 + ha->port_no;
3a03eb79
AV		 5561 }
5562
b64b0e8f
AV		 5563 /* Use extended-initialization control block. */
5564 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
5565
3a03eb79
AV		 5566 /*
5567 * Setup driver NVRAM options.
5568 */
5569 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
a9083016 5570 "QLE8XXX");
3a03eb79
AV		 5571
5572 /* Use alternate WWN? */
5573 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
5574 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
5575 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
5576 }
5577
5578 /* Prepare nodename */
5579 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
5580 /*
5581 * Firmware will apply the following mask if the nodename was
5582 * not provided.
5583 */
5584 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
5585 icb->node_name[0] &= 0xF0;
5586 }
5587
5588 /* Set host adapter parameters. */
5589 ha->flags.disable_risc_code_load = 0;
5590 ha->flags.enable_lip_reset = 0;
5591 ha->flags.enable_lip_full_login =
5592 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
5593 ha->flags.enable_target_reset =
5594 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
5595 ha->flags.enable_led_scheme = 0;
5596 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
5597
5598 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
5599 (BIT_6 | BIT_5 | BIT_4)) >> 4;
5600
5601 /* save HBA serial number */
5602 ha->serial0 = icb->port_name[5];
5603 ha->serial1 = icb->port_name[6];
5604 ha->serial2 = icb->port_name[7];
5605 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
5606 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
5607
5608 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5609
5610 ha->retry_count = le16_to_cpu(nv->login_retry_count);
5611
5612 /* Set minimum login_timeout to 4 seconds. */
5613 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
5614 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
5615 if (le16_to_cpu(nv->login_timeout) < 4)
5616 nv->login_timeout = __constant_cpu_to_le16(4);
5617 ha->login_timeout = le16_to_cpu(nv->login_timeout);
5618 icb->login_timeout = nv->login_timeout;
5619
5620 /* Set minimum RATOV to 100 tenths of a second. */
5621 ha->r_a_tov = 100;
5622
5623 ha->loop_reset_delay = nv->reset_delay;
5624
5625 /* Link Down Timeout = 0:
5626 *
5627 * When Port Down timer expires we will start returning
5628 * I/O's to OS with "DID_NO_CONNECT".
5629 *
5630 * Link Down Timeout != 0:
5631 *
5632 * The driver waits for the link to come up after link down
5633 * before returning I/Os to OS with "DID_NO_CONNECT".
5634 */
5635 if (le16_to_cpu(nv->link_down_timeout) == 0) {
5636 ha->loop_down_abort_time =
5637 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
5638 } else {
5639 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
5640 ha->loop_down_abort_time =
5641 (LOOP_DOWN_TIME - ha->link_down_timeout);
5642 }
5643
5644 /* Need enough time to try and get the port back. */
5645 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
5646 if (qlport_down_retry)
5647 ha->port_down_retry_count = qlport_down_retry;
5648
5649 /* Set login_retry_count */
5650 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
5651 if (ha->port_down_retry_count ==
5652 le16_to_cpu(nv->port_down_retry_count) &&
5653 ha->port_down_retry_count > 3)
5654 ha->login_retry_count = ha->port_down_retry_count;
5655 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
5656 ha->login_retry_count = ha->port_down_retry_count;
5657 if (ql2xloginretrycount)
5658 ha->login_retry_count = ql2xloginretrycount;
5659
6246b8a1
GM		 5660 /* if not running MSI-X we need handshaking on interrupts */
5661 if (!vha->hw->flags.msix_enabled && IS_QLA83XX(ha))
5662 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_22);
5663
3a03eb79
AV		 5664 /* Enable ZIO. */
5665 if (!vha->flags.init_done) {
5666 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
5667 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
5668 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
5669 le16_to_cpu(icb->interrupt_delay_timer): 2;
5670 }
5671 icb->firmware_options_2 &= __constant_cpu_to_le32(
5672 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
5673 vha->flags.process_response_queue = 0;
5674 if (ha->zio_mode != QLA_ZIO_DISABLED) {
5675 ha->zio_mode = QLA_ZIO_MODE_6;
5676
7c3df132 5677 ql_log(ql_log_info, vha, 0x0075,
3a03eb79 5678 "ZIO mode %d enabled; timer delay (%d us).\n",
7c3df132
SK		 5679 ha->zio_mode,
5680 ha->zio_timer * 100);
3a03eb79
AV		 5681
5682 icb->firmware_options_2 |= cpu_to_le32(
5683 (uint32_t)ha->zio_mode);
5684 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
5685 vha->flags.process_response_queue = 1;
5686 }
5687
5688 if (rval) {
7c3df132
SK		 5689 ql_log(ql_log_warn, vha, 0x0076,
5690 "NVRAM configuration failed.\n");
3a03eb79
AV		 5691 }
5692 return (rval);
5693}
5694
a9083016
GM		 5695int
5696qla82xx_restart_isp(scsi_qla_host_t *vha)
5697{
5698 int status, rval;
5699 uint32_t wait_time;
5700 struct qla_hw_data *ha = vha->hw;
5701 struct req_que *req = ha->req_q_map[0];
5702 struct rsp_que *rsp = ha->rsp_q_map[0];
5703 struct scsi_qla_host *vp;
feafb7b1 5704 unsigned long flags;
a9083016
GM		 5705
5706 status = qla2x00_init_rings(vha);
5707 if (!status) {
5708 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5709 ha->flags.chip_reset_done = 1;
5710
5711 status = qla2x00_fw_ready(vha);
5712 if (!status) {
7c3df132
SK		 5713 ql_log(ql_log_info, vha, 0x803c,
5714 "Start configure loop, status =%d.\n", status);
a9083016
GM		 5715
5716 /* Issue a marker after FW becomes ready. */
5717 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
5718
5719 vha->flags.online = 1;
5720 /* Wait at most MAX_TARGET RSCNs for a stable link. */
5721 wait_time = 256;
5722 do {
5723 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5724 qla2x00_configure_loop(vha);
5725 wait_time--;
5726 } while (!atomic_read(&vha->loop_down_timer) &&
5727 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) &&
5728 wait_time &&
5729 (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)));
5730 }
5731
5732 /* if no cable then assume it's good */
5733 if ((vha->device_flags & DFLG_NO_CABLE))
5734 status = 0;
5735
cfb0919c 5736 ql_log(ql_log_info, vha, 0x8000,
7c3df132 5737 "Configure loop done, status = 0x%x.\n", status);
a9083016
GM		 5738 }
5739
5740 if (!status) {
5741 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5742
5743 if (!atomic_read(&vha->loop_down_timer)) {
5744 /*
5745 * Issue marker command only when we are going
5746 * to start the I/O .
5747 */
5748 vha->marker_needed = 1;
5749 }
5750
5751 vha->flags.online = 1;
5752
5753 ha->isp_ops->enable_intrs(ha);
5754
5755 ha->isp_abort_cnt = 0;
5756 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
5757
53296788 5758 /* Update the firmware version */
3173167f 5759 status = qla82xx_check_md_needed(vha);
53296788 5760
a9083016
GM		 5761 if (ha->fce) {
5762 ha->flags.fce_enabled = 1;
5763 memset(ha->fce, 0,
5764 fce_calc_size(ha->fce_bufs));
5765 rval = qla2x00_enable_fce_trace(vha,
5766 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
5767 &ha->fce_bufs);
5768 if (rval) {
cfb0919c 5769 ql_log(ql_log_warn, vha, 0x8001,
7c3df132
SK		 5770 "Unable to reinitialize FCE (%d).\n",
5771 rval);
a9083016
GM		 5772 ha->flags.fce_enabled = 0;
5773 }
5774 }
5775
5776 if (ha->eft) {
5777 memset(ha->eft, 0, EFT_SIZE);
5778 rval = qla2x00_enable_eft_trace(vha,
5779 ha->eft_dma, EFT_NUM_BUFFERS);
5780 if (rval) {
cfb0919c 5781 ql_log(ql_log_warn, vha, 0x8010,
7c3df132
SK		 5782 "Unable to reinitialize EFT (%d).\n",
5783 rval);
a9083016
GM		 5784 }
5785 }
a9083016
GM		 5786 }
5787
5788 if (!status) {
cfb0919c 5789 ql_dbg(ql_dbg_taskm, vha, 0x8011,
7c3df132 5790 "qla82xx_restart_isp succeeded.\n");
feafb7b1
AE		 5791
5792 spin_lock_irqsave(&ha->vport_slock, flags);
5793 list_for_each_entry(vp, &ha->vp_list, list) {
5794 if (vp->vp_idx) {
5795 atomic_inc(&vp->vref_count);
5796 spin_unlock_irqrestore(&ha->vport_slock, flags);
5797
a9083016 5798 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 5799
5800 spin_lock_irqsave(&ha->vport_slock, flags);
5801 atomic_dec(&vp->vref_count);
5802 }
a9083016 5803 }
feafb7b1
AE		 5804 spin_unlock_irqrestore(&ha->vport_slock, flags);
5805
a9083016 5806 } else {
cfb0919c 5807 ql_log(ql_log_warn, vha, 0x8016,
7c3df132 5808 "qla82xx_restart_isp **** FAILED ****.\n");
a9083016
GM		 5809 }
5810
5811 return status;
5812}
5813
3a03eb79 5814void
ae97c91e 5815qla81xx_update_fw_options(scsi_qla_host_t *vha)
3a03eb79 5816{
ae97c91e
AV		 5817 struct qla_hw_data *ha = vha->hw;
5818
5819 if (!ql2xetsenable)
5820 return;
5821
5822 /* Enable ETS Burst. */
5823 memset(ha->fw_options, 0, sizeof(ha->fw_options));
5824 ha->fw_options[2] |= BIT_9;
5825 qla2x00_set_fw_options(vha, ha->fw_options);
3a03eb79 5826}
09ff701a
SR		 5827
5828/*
5829 * qla24xx_get_fcp_prio
5830 * Gets the fcp cmd priority value for the logged in port.
5831 * Looks for a match of the port descriptors within
5832 * each of the fcp prio config entries. If a match is found,
5833 * the tag (priority) value is returned.
5834 *
5835 * Input:
21090cbe 5836 * vha = scsi host structure pointer.
09ff701a
SR		 5837 * fcport = port structure pointer.
5838 *
5839 * Return:
6c452a45 5840 * non-zero (if found)
f28a0a96 5841 * -1 (if not found)
09ff701a
SR		 5842 *
5843 * Context:
5844 * Kernel context
5845 */
f28a0a96 5846static int
09ff701a
SR		 5847qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
5848{
5849 int i, entries;
5850 uint8_t pid_match, wwn_match;
f28a0a96 5851 int priority;
09ff701a
SR		 5852 uint32_t pid1, pid2;
5853 uint64_t wwn1, wwn2;
5854 struct qla_fcp_prio_entry *pri_entry;
5855 struct qla_hw_data *ha = vha->hw;
5856
5857 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
f28a0a96 5858 return -1;
09ff701a 5859
f28a0a96 5860 priority = -1;
09ff701a
SR		 5861 entries = ha->fcp_prio_cfg->num_entries;
5862 pri_entry = &ha->fcp_prio_cfg->entry[0];
5863
5864 for (i = 0; i < entries; i++) {
5865 pid_match = wwn_match = 0;
5866
5867 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
5868 pri_entry++;
5869 continue;
5870 }
5871
5872 /* check source pid for a match */
5873 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
5874 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
5875 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
5876 if (pid1 == INVALID_PORT_ID)
5877 pid_match++;
5878 else if (pid1 == pid2)
5879 pid_match++;
5880 }
5881
5882 /* check destination pid for a match */
5883 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
5884 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
5885 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
5886 if (pid1 == INVALID_PORT_ID)
5887 pid_match++;
5888 else if (pid1 == pid2)
5889 pid_match++;
5890 }
5891
5892 /* check source WWN for a match */
5893 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
5894 wwn1 = wwn_to_u64(vha->port_name);
5895 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
5896 if (wwn2 == (uint64_t)-1)
5897 wwn_match++;
5898 else if (wwn1 == wwn2)
5899 wwn_match++;
5900 }
5901
5902 /* check destination WWN for a match */
5903 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
5904 wwn1 = wwn_to_u64(fcport->port_name);
5905 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
5906 if (wwn2 == (uint64_t)-1)
5907 wwn_match++;
5908 else if (wwn1 == wwn2)
5909 wwn_match++;
5910 }
5911
5912 if (pid_match == 2 || wwn_match == 2) {
5913 /* Found a matching entry */
5914 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
5915 priority = pri_entry->tag;
5916 break;
5917 }
5918
5919 pri_entry++;
5920 }
5921
5922 return priority;
5923}
5924
5925/*
5926 * qla24xx_update_fcport_fcp_prio
5927 * Activates fcp priority for the logged in fc port
5928 *
5929 * Input:
21090cbe 5930 * vha = scsi host structure pointer.
09ff701a
SR		 5931 * fcp = port structure pointer.
5932 *
5933 * Return:
5934 * QLA_SUCCESS or QLA_FUNCTION_FAILED
5935 *
5936 * Context:
5937 * Kernel context.
5938 */
5939int
21090cbe 5940qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
09ff701a
SR		 5941{
5942 int ret;
f28a0a96 5943 int priority;
09ff701a
SR		 5944 uint16_t mb[5];
5945
21090cbe
MI		 5946 if (fcport->port_type != FCT_TARGET ||
5947 fcport->loop_id == FC_NO_LOOP_ID)
09ff701a
SR		 5948 return QLA_FUNCTION_FAILED;
5949
21090cbe 5950 priority = qla24xx_get_fcp_prio(vha, fcport);
f28a0a96
AV		 5951 if (priority < 0)
5952 return QLA_FUNCTION_FAILED;
5953
a00f6296
SK		 5954 if (IS_QLA82XX(vha->hw)) {
5955 fcport->fcp_prio = priority & 0xf;
5956 return QLA_SUCCESS;
5957 }
5958
21090cbe 5959 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
cfb0919c
CD		 5960 if (ret == QLA_SUCCESS) {
5961 if (fcport->fcp_prio != priority)
5962 ql_dbg(ql_dbg_user, vha, 0x709e,
5963 "Updated FCP_CMND priority - value=%d loop_id=%d "
5964 "port_id=%02x%02x%02x.\n", priority,
5965 fcport->loop_id, fcport->d_id.b.domain,
5966 fcport->d_id.b.area, fcport->d_id.b.al_pa);
a00f6296 5967 fcport->fcp_prio = priority & 0xf;
cfb0919c 5968 } else
7c3df132 5969 ql_dbg(ql_dbg_user, vha, 0x704f,
cfb0919c
CD		 5970 "Unable to update FCP_CMND priority - ret=0x%x for "
5971 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
5972 fcport->d_id.b.domain, fcport->d_id.b.area,
5973 fcport->d_id.b.al_pa);
09ff701a
SR		 5974 return ret;
5975}
5976
5977/*
5978 * qla24xx_update_all_fcp_prio
5979 * Activates fcp priority for all the logged in ports
5980 *
5981 * Input:
5982 * ha = adapter block pointer.
5983 *
5984 * Return:
5985 * QLA_SUCCESS or QLA_FUNCTION_FAILED
5986 *
5987 * Context:
5988 * Kernel context.
5989 */
5990int
5991qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
5992{
5993 int ret;
5994 fc_port_t *fcport;
5995
5996 ret = QLA_FUNCTION_FAILED;
5997 /* We need to set priority for all logged in ports */
5998 list_for_each_entry(fcport, &vha->vp_fcports, list)
5999 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
6000
6001 return ret;
6002}
Linux kernel - Deliverables
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