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Linux 3.10-rc1
[deliverable/linux.git] / drivers / scsi / qla2xxx / qla_nx.c
CommitLineData
a9083016
GM		 1/*
2 * QLogic Fibre Channel HBA Driver
1e63395c 3 * Copyright (c) 2003-2013 QLogic Corporation
a9083016
GM		 4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7#include "qla_def.h"
8#include <linux/delay.h>
9#include <linux/pci.h>
08de2844
GM		 10#include <linux/ratelimit.h>
11#include <linux/vmalloc.h>
ff2fc42e 12#include <scsi/scsi_tcq.h>
a9083016
GM		 13
14#define MASK(n) ((1ULL<<(n))-1)
15#define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \
16 ((addr >> 25) & 0x3ff))
17#define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \
18 ((addr >> 25) & 0x3ff))
19#define MS_WIN(addr) (addr & 0x0ffc0000)
20#define QLA82XX_PCI_MN_2M (0)
21#define QLA82XX_PCI_MS_2M (0x80000)
22#define QLA82XX_PCI_OCM0_2M (0xc0000)
23#define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
24#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
0547fb37 25#define BLOCK_PROTECT_BITS 0x0F
a9083016
GM		 26
27/* CRB window related */
28#define CRB_BLK(off) ((off >> 20) & 0x3f)
29#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
30#define CRB_WINDOW_2M (0x130060)
31#define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL)
32#define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
33 ((off) & 0xf0000))
34#define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL)
35#define CRB_INDIRECT_2M (0x1e0000UL)
36
a9083016
GM		 37#define MAX_CRB_XFORM 60
38static unsigned long crb_addr_xform[MAX_CRB_XFORM];
fa492630 39static int qla82xx_crb_table_initialized;
a9083016
GM		 40
41#define qla82xx_crb_addr_transform(name) \
42 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
43 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
44
45static void qla82xx_crb_addr_transform_setup(void)
46{
47 qla82xx_crb_addr_transform(XDMA);
48 qla82xx_crb_addr_transform(TIMR);
49 qla82xx_crb_addr_transform(SRE);
50 qla82xx_crb_addr_transform(SQN3);
51 qla82xx_crb_addr_transform(SQN2);
52 qla82xx_crb_addr_transform(SQN1);
53 qla82xx_crb_addr_transform(SQN0);
54 qla82xx_crb_addr_transform(SQS3);
55 qla82xx_crb_addr_transform(SQS2);
56 qla82xx_crb_addr_transform(SQS1);
57 qla82xx_crb_addr_transform(SQS0);
58 qla82xx_crb_addr_transform(RPMX7);
59 qla82xx_crb_addr_transform(RPMX6);
60 qla82xx_crb_addr_transform(RPMX5);
61 qla82xx_crb_addr_transform(RPMX4);
62 qla82xx_crb_addr_transform(RPMX3);
63 qla82xx_crb_addr_transform(RPMX2);
64 qla82xx_crb_addr_transform(RPMX1);
65 qla82xx_crb_addr_transform(RPMX0);
66 qla82xx_crb_addr_transform(ROMUSB);
67 qla82xx_crb_addr_transform(SN);
68 qla82xx_crb_addr_transform(QMN);
69 qla82xx_crb_addr_transform(QMS);
70 qla82xx_crb_addr_transform(PGNI);
71 qla82xx_crb_addr_transform(PGND);
72 qla82xx_crb_addr_transform(PGN3);
73 qla82xx_crb_addr_transform(PGN2);
74 qla82xx_crb_addr_transform(PGN1);
75 qla82xx_crb_addr_transform(PGN0);
76 qla82xx_crb_addr_transform(PGSI);
77 qla82xx_crb_addr_transform(PGSD);
78 qla82xx_crb_addr_transform(PGS3);
79 qla82xx_crb_addr_transform(PGS2);
80 qla82xx_crb_addr_transform(PGS1);
81 qla82xx_crb_addr_transform(PGS0);
82 qla82xx_crb_addr_transform(PS);
83 qla82xx_crb_addr_transform(PH);
84 qla82xx_crb_addr_transform(NIU);
85 qla82xx_crb_addr_transform(I2Q);
86 qla82xx_crb_addr_transform(EG);
87 qla82xx_crb_addr_transform(MN);
88 qla82xx_crb_addr_transform(MS);
89 qla82xx_crb_addr_transform(CAS2);
90 qla82xx_crb_addr_transform(CAS1);
91 qla82xx_crb_addr_transform(CAS0);
92 qla82xx_crb_addr_transform(CAM);
93 qla82xx_crb_addr_transform(C2C1);
94 qla82xx_crb_addr_transform(C2C0);
95 qla82xx_crb_addr_transform(SMB);
96 qla82xx_crb_addr_transform(OCM0);
97 /*
98 * Used only in P3 just define it for P2 also.
99 */
100 qla82xx_crb_addr_transform(I2C0);
101
102 qla82xx_crb_table_initialized = 1;
103}
104
fa492630 105static struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
a9083016
GM		 106 {{{0, 0, 0, 0} } },
107 {{{1, 0x0100000, 0x0102000, 0x120000},
108 {1, 0x0110000, 0x0120000, 0x130000},
109 {1, 0x0120000, 0x0122000, 0x124000},
110 {1, 0x0130000, 0x0132000, 0x126000},
111 {1, 0x0140000, 0x0142000, 0x128000},
112 {1, 0x0150000, 0x0152000, 0x12a000},
113 {1, 0x0160000, 0x0170000, 0x110000},
114 {1, 0x0170000, 0x0172000, 0x12e000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {1, 0x01e0000, 0x01e0800, 0x122000},
122 {0, 0x0000000, 0x0000000, 0x000000} } } ,
123 {{{1, 0x0200000, 0x0210000, 0x180000} } },
124 {{{0, 0, 0, 0} } },
125 {{{1, 0x0400000, 0x0401000, 0x169000} } },
126 {{{1, 0x0500000, 0x0510000, 0x140000} } },
127 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },
128 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },
129 {{{1, 0x0800000, 0x0802000, 0x170000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {1, 0x08f0000, 0x08f2000, 0x172000} } },
145 {{{1, 0x0900000, 0x0902000, 0x174000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {1, 0x09f0000, 0x09f2000, 0x176000} } },
161 {{{0, 0x0a00000, 0x0a02000, 0x178000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
177 {{{0, 0x0b00000, 0x0b02000, 0x17c000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000},
180 {0, 0x0000000, 0x0000000, 0x000000},
181 {0, 0x0000000, 0x0000000, 0x000000},
182 {0, 0x0000000, 0x0000000, 0x000000},
183 {0, 0x0000000, 0x0000000, 0x000000},
184 {0, 0x0000000, 0x0000000, 0x000000},
185 {0, 0x0000000, 0x0000000, 0x000000},
186 {0, 0x0000000, 0x0000000, 0x000000},
187 {0, 0x0000000, 0x0000000, 0x000000},
188 {0, 0x0000000, 0x0000000, 0x000000},
189 {0, 0x0000000, 0x0000000, 0x000000},
190 {0, 0x0000000, 0x0000000, 0x000000},
191 {0, 0x0000000, 0x0000000, 0x000000},
192 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
193 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },
194 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },
195 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },
196 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },
197 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },
198 {{{1, 0x1100000, 0x1101000, 0x160000} } },
199 {{{1, 0x1200000, 0x1201000, 0x161000} } },
200 {{{1, 0x1300000, 0x1301000, 0x162000} } },
201 {{{1, 0x1400000, 0x1401000, 0x163000} } },
202 {{{1, 0x1500000, 0x1501000, 0x165000} } },
203 {{{1, 0x1600000, 0x1601000, 0x166000} } },
204 {{{0, 0, 0, 0} } },
205 {{{0, 0, 0, 0} } },
206 {{{0, 0, 0, 0} } },
207 {{{0, 0, 0, 0} } },
208 {{{0, 0, 0, 0} } },
209 {{{0, 0, 0, 0} } },
210 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },
211 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },
212 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },
213 {{{0} } },
214 {{{1, 0x2100000, 0x2102000, 0x120000},
215 {1, 0x2110000, 0x2120000, 0x130000},
216 {1, 0x2120000, 0x2122000, 0x124000},
217 {1, 0x2130000, 0x2132000, 0x126000},
218 {1, 0x2140000, 0x2142000, 0x128000},
219 {1, 0x2150000, 0x2152000, 0x12a000},
220 {1, 0x2160000, 0x2170000, 0x110000},
221 {1, 0x2170000, 0x2172000, 0x12e000},
222 {0, 0x0000000, 0x0000000, 0x000000},
223 {0, 0x0000000, 0x0000000, 0x000000},
224 {0, 0x0000000, 0x0000000, 0x000000},
225 {0, 0x0000000, 0x0000000, 0x000000},
226 {0, 0x0000000, 0x0000000, 0x000000},
227 {0, 0x0000000, 0x0000000, 0x000000},
228 {0, 0x0000000, 0x0000000, 0x000000},
229 {0, 0x0000000, 0x0000000, 0x000000} } },
230 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },
231 {{{0} } },
232 {{{0} } },
233 {{{0} } },
234 {{{0} } },
235 {{{0} } },
236 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },
237 {{{1, 0x2900000, 0x2901000, 0x16b000} } },
238 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },
239 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },
240 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },
241 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },
242 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },
243 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },
244 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },
245 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },
246 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },
247 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },
248 {{{0} } },
249 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },
250 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },
251 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },
252 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },
253 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },
254 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },
255 {{{0} } },
256 {{{0} } },
257 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },
258 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },
259 {{{1, 0x3f00000, 0x3f01000, 0x168000} } }
260};
261
262/*
263 * top 12 bits of crb internal address (hub, agent)
264 */
fa492630 265static unsigned qla82xx_crb_hub_agt[64] = {
a9083016
GM		 266 0,
267 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
268 QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
269 QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
270 0,
271 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
272 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
273 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
274 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
275 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
276 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
277 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
278 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
279 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
280 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
281 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
282 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
283 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
284 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
285 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
286 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
287 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
288 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
293 0,
294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
295 QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
296 0,
297 QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
298 0,
299 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
300 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
301 0,
302 0,
303 0,
304 0,
305 0,
306 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
307 0,
308 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
309 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
310 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
311 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
312 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
313 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
314 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
315 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
316 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
317 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
318 0,
319 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
320 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
321 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
322 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
323 0,
324 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
325 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
326 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
327 0,
328 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
329 0,
330};
331
f1af6208 332/* Device states */
fa492630 333static char *q_dev_state[] = {
f1af6208
GM		 334 "Unknown",
335 "Cold",
336 "Initializing",
337 "Ready",
338 "Need Reset",
339 "Need Quiescent",
340 "Failed",
341 "Quiescent",
342};
343
08de2844
GM		 344char *qdev_state(uint32_t dev_state)
345{
346 return q_dev_state[dev_state];
347}
348
a9083016
GM		 349/*
350 * In: 'off' is offset from CRB space in 128M pci map
351 * Out: 'off' is 2M pci map addr
352 * side effect: lock crb window
353 */
354static void
355qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong *off)
356{
357 u32 win_read;
7c3df132 358 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 359
360 ha->crb_win = CRB_HI(*off);
361 writel(ha->crb_win,
fa492630 362 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
a9083016
GM		 363
364 /* Read back value to make sure write has gone through before trying
365 * to use it.
366 */
fa492630
SK		 367 win_read = RD_REG_DWORD((void __iomem *)
368 (CRB_WINDOW_2M + ha->nx_pcibase));
a9083016 369 if (win_read != ha->crb_win) {
7c3df132
SK		 370 ql_dbg(ql_dbg_p3p, vha, 0xb000,
371 "%s: Written crbwin (0x%x) "
372 "!= Read crbwin (0x%x), off=0x%lx.\n",
d8424f68 373 __func__, ha->crb_win, win_read, *off);
a9083016
GM		 374 }
375 *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
376}
377
378static inline unsigned long
379qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off)
380{
7c3df132 381 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 382 /* See if we are currently pointing to the region we want to use next */
383 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) {
384 /* No need to change window. PCIX and PCIEregs are in both
385 * regs are in both windows.
386 */
387 return off;
388 }
389
390 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) {
391 /* We are in first CRB window */
392 if (ha->curr_window != 0)
393 WARN_ON(1);
394 return off;
395 }
396
397 if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) {
398 /* We are in second CRB window */
399 off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST;
400
401 if (ha->curr_window != 1)
402 return off;
403
404 /* We are in the QM or direct access
405 * register region - do nothing
406 */
407 if ((off >= QLA82XX_PCI_DIRECT_CRB) &&
408 (off < QLA82XX_PCI_CAMQM_MAX))
409 return off;
410 }
411 /* strange address given */
7c3df132 412 ql_dbg(ql_dbg_p3p, vha, 0xb001,
d8424f68 413 "%s: Warning: unm_nic_pci_set_crbwindow "
7c3df132
SK		 414 "called with an unknown address(%llx).\n",
415 QLA2XXX_DRIVER_NAME, off);
a9083016
GM		 416 return off;
417}
418
77e334d2
GM		 419static int
420qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong *off)
421{
422 struct crb_128M_2M_sub_block_map *m;
423
424 if (*off >= QLA82XX_CRB_MAX)
425 return -1;
426
427 if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) {
428 *off = (*off - QLA82XX_PCI_CAMQM) +
429 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
430 return 0;
431 }
432
433 if (*off < QLA82XX_PCI_CRBSPACE)
434 return -1;
435
436 *off -= QLA82XX_PCI_CRBSPACE;
437
438 /* Try direct map */
439 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
440
441 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
442 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase;
443 return 0;
444 }
445 /* Not in direct map, use crb window */
446 return 1;
447}
448
449#define CRB_WIN_LOCK_TIMEOUT 100000000
450static int qla82xx_crb_win_lock(struct qla_hw_data *ha)
451{
452 int done = 0, timeout = 0;
453
454 while (!done) {
455 /* acquire semaphore3 from PCI HW block */
456 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
457 if (done == 1)
458 break;
459 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
460 return -1;
461 timeout++;
462 }
463 qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum);
464 return 0;
465}
466
a9083016
GM		 467int
468qla82xx_wr_32(struct qla_hw_data *ha, ulong off, u32 data)
469{
470 unsigned long flags = 0;
471 int rv;
472
473 rv = qla82xx_pci_get_crb_addr_2M(ha, &off);
474
475 BUG_ON(rv == -1);
476
477 if (rv == 1) {
478 write_lock_irqsave(&ha->hw_lock, flags);
479 qla82xx_crb_win_lock(ha);
480 qla82xx_pci_set_crbwindow_2M(ha, &off);
481 }
482
483 writel(data, (void __iomem *)off);
484
485 if (rv == 1) {
486 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
487 write_unlock_irqrestore(&ha->hw_lock, flags);
488 }
489 return 0;
490}
491
492int
493qla82xx_rd_32(struct qla_hw_data *ha, ulong off)
494{
495 unsigned long flags = 0;
496 int rv;
497 u32 data;
498
499 rv = qla82xx_pci_get_crb_addr_2M(ha, &off);
500
501 BUG_ON(rv == -1);
502
503 if (rv == 1) {
504 write_lock_irqsave(&ha->hw_lock, flags);
505 qla82xx_crb_win_lock(ha);
506 qla82xx_pci_set_crbwindow_2M(ha, &off);
507 }
508 data = RD_REG_DWORD((void __iomem *)off);
509
510 if (rv == 1) {
511 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
512 write_unlock_irqrestore(&ha->hw_lock, flags);
513 }
514 return data;
515}
516
a9083016
GM		 517#define IDC_LOCK_TIMEOUT 100000000
518int qla82xx_idc_lock(struct qla_hw_data *ha)
519{
520 int i;
521 int done = 0, timeout = 0;
522
523 while (!done) {
524 /* acquire semaphore5 from PCI HW block */
525 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
526 if (done == 1)
527 break;
528 if (timeout >= IDC_LOCK_TIMEOUT)
529 return -1;
530
531 timeout++;
532
533 /* Yield CPU */
534 if (!in_interrupt())
535 schedule();
536 else {
537 for (i = 0; i < 20; i++)
538 cpu_relax();
539 }
540 }
541
542 return 0;
543}
544
545void qla82xx_idc_unlock(struct qla_hw_data *ha)
546{
547 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
548}
549
a9083016
GM		 550/* PCI Windowing for DDR regions. */
551#define QLA82XX_ADDR_IN_RANGE(addr, low, high) \
552 (((addr) <= (high)) && ((addr) >= (low)))
553/*
554 * check memory access boundary.
555 * used by test agent. support ddr access only for now
556 */
557static unsigned long
558qla82xx_pci_mem_bound_check(struct qla_hw_data *ha,
559 unsigned long long addr, int size)
560{
561 if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
562 QLA82XX_ADDR_DDR_NET_MAX) ||
563 !QLA82XX_ADDR_IN_RANGE(addr + size - 1, QLA82XX_ADDR_DDR_NET,
564 QLA82XX_ADDR_DDR_NET_MAX) ||
565 ((size != 1) && (size != 2) && (size != 4) && (size != 8)))
566 return 0;
567 else
568 return 1;
569}
570
fa492630 571static int qla82xx_pci_set_window_warning_count;
a9083016 572
77e334d2 573static unsigned long
a9083016
GM		 574qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr)
575{
576 int window;
577 u32 win_read;
7c3df132 578 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 579
580 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
581 QLA82XX_ADDR_DDR_NET_MAX)) {
582 /* DDR network side */
583 window = MN_WIN(addr);
584 ha->ddr_mn_window = window;
585 qla82xx_wr_32(ha,
586 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
587 win_read = qla82xx_rd_32(ha,
588 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
589 if ((win_read << 17) != window) {
7c3df132
SK		 590 ql_dbg(ql_dbg_p3p, vha, 0xb003,
591 "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n",
a9083016
GM		 592 __func__, window, win_read);
593 }
594 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
595 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
596 QLA82XX_ADDR_OCM0_MAX)) {
597 unsigned int temp1;
598 if ((addr & 0x00ff800) == 0xff800) {
7c3df132 599 ql_log(ql_log_warn, vha, 0xb004,
a9083016
GM		 600 "%s: QM access not handled.\n", __func__);
601 addr = -1UL;
602 }
603 window = OCM_WIN(addr);
604 ha->ddr_mn_window = window;
605 qla82xx_wr_32(ha,
606 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
607 win_read = qla82xx_rd_32(ha,
608 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
609 temp1 = ((window & 0x1FF) << 7) |
610 ((window & 0x0FFFE0000) >> 17);
611 if (win_read != temp1) {
7c3df132
SK		 612 ql_log(ql_log_warn, vha, 0xb005,
613 "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n",
a9083016
GM		 614 __func__, temp1, win_read);
615 }
616 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
617
618 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET,
619 QLA82XX_P3_ADDR_QDR_NET_MAX)) {
620 /* QDR network side */
621 window = MS_WIN(addr);
622 ha->qdr_sn_window = window;
623 qla82xx_wr_32(ha,
624 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window);
625 win_read = qla82xx_rd_32(ha,
626 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
627 if (win_read != window) {
7c3df132
SK		 628 ql_log(ql_log_warn, vha, 0xb006,
629 "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n",
a9083016
GM		 630 __func__, window, win_read);
631 }
632 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
633 } else {
634 /*
635 * peg gdb frequently accesses memory that doesn't exist,
636 * this limits the chit chat so debugging isn't slowed down.
637 */
638 if ((qla82xx_pci_set_window_warning_count++ < 8) ||
639 (qla82xx_pci_set_window_warning_count%64 == 0)) {
7c3df132
SK		 640 ql_log(ql_log_warn, vha, 0xb007,
641 "%s: Warning:%s Unknown address range!.\n",
642 __func__, QLA2XXX_DRIVER_NAME);
a9083016
GM		 643 }
644 addr = -1UL;
645 }
646 return addr;
647}
648
649/* check if address is in the same windows as the previous access */
650static int qla82xx_pci_is_same_window(struct qla_hw_data *ha,
651 unsigned long long addr)
652{
653 int window;
654 unsigned long long qdr_max;
655
656 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
657
658 /* DDR network side */
659 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
660 QLA82XX_ADDR_DDR_NET_MAX))
661 BUG();
662 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
663 QLA82XX_ADDR_OCM0_MAX))
664 return 1;
665 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1,
666 QLA82XX_ADDR_OCM1_MAX))
667 return 1;
668 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) {
669 /* QDR network side */
670 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f;
671 if (ha->qdr_sn_window == window)
672 return 1;
673 }
674 return 0;
675}
676
677static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha,
678 u64 off, void *data, int size)
679{
680 unsigned long flags;
fa492630 681 void __iomem *addr = NULL;
a9083016
GM		 682 int ret = 0;
683 u64 start;
fa492630 684 uint8_t __iomem *mem_ptr = NULL;
a9083016
GM		 685 unsigned long mem_base;
686 unsigned long mem_page;
7c3df132 687 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 688
689 write_lock_irqsave(&ha->hw_lock, flags);
690
691 /*
692 * If attempting to access unknown address or straddle hw windows,
693 * do not access.
694 */
695 start = qla82xx_pci_set_window(ha, off);
696 if ((start == -1UL) ||
697 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
698 write_unlock_irqrestore(&ha->hw_lock, flags);
7c3df132
SK		 699 ql_log(ql_log_fatal, vha, 0xb008,
700 "%s out of bound pci memory "
701 "access, offset is 0x%llx.\n",
702 QLA2XXX_DRIVER_NAME, off);
a9083016
GM		 703 return -1;
704 }
705
f1af6208
GM		 706 write_unlock_irqrestore(&ha->hw_lock, flags);
707 mem_base = pci_resource_start(ha->pdev, 0);
708 mem_page = start & PAGE_MASK;
709 /* Map two pages whenever user tries to access addresses in two
710 * consecutive pages.
711 */
712 if (mem_page != ((start + size - 1) & PAGE_MASK))
713 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
714 else
715 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
fa492630 716 if (mem_ptr == NULL) {
f1af6208
GM		 717 *(u8 *)data = 0;
718 return -1;
a9083016 719 }
f1af6208
GM		 720 addr = mem_ptr;
721 addr += start & (PAGE_SIZE - 1);
722 write_lock_irqsave(&ha->hw_lock, flags);
a9083016
GM		 723
724 switch (size) {
725 case 1:
726 *(u8 *)data = readb(addr);
727 break;
728 case 2:
729 *(u16 *)data = readw(addr);
730 break;
731 case 4:
732 *(u32 *)data = readl(addr);
733 break;
734 case 8:
735 *(u64 *)data = readq(addr);
736 break;
737 default:
738 ret = -1;
739 break;
740 }
741 write_unlock_irqrestore(&ha->hw_lock, flags);
742
743 if (mem_ptr)
744 iounmap(mem_ptr);
745 return ret;
746}
747
748static int
749qla82xx_pci_mem_write_direct(struct qla_hw_data *ha,
750 u64 off, void *data, int size)
751{
752 unsigned long flags;
fa492630 753 void __iomem *addr = NULL;
a9083016
GM		 754 int ret = 0;
755 u64 start;
fa492630 756 uint8_t __iomem *mem_ptr = NULL;
a9083016
GM		 757 unsigned long mem_base;
758 unsigned long mem_page;
7c3df132 759 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 760
761 write_lock_irqsave(&ha->hw_lock, flags);
762
763 /*
764 * If attempting to access unknown address or straddle hw windows,
765 * do not access.
766 */
767 start = qla82xx_pci_set_window(ha, off);
768 if ((start == -1UL) ||
769 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
770 write_unlock_irqrestore(&ha->hw_lock, flags);
7c3df132
SK		 771 ql_log(ql_log_fatal, vha, 0xb009,
772 "%s out of bount memory "
773 "access, offset is 0x%llx.\n",
774 QLA2XXX_DRIVER_NAME, off);
a9083016
GM		 775 return -1;
776 }
777
f1af6208
GM		 778 write_unlock_irqrestore(&ha->hw_lock, flags);
779 mem_base = pci_resource_start(ha->pdev, 0);
780 mem_page = start & PAGE_MASK;
781 /* Map two pages whenever user tries to access addresses in two
782 * consecutive pages.
783 */
784 if (mem_page != ((start + size - 1) & PAGE_MASK))
785 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
786 else
787 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
fa492630 788 if (mem_ptr == NULL)
f1af6208 789 return -1;
a9083016 790
f1af6208
GM		 791 addr = mem_ptr;
792 addr += start & (PAGE_SIZE - 1);
793 write_lock_irqsave(&ha->hw_lock, flags);
a9083016
GM		 794
795 switch (size) {
796 case 1:
797 writeb(*(u8 *)data, addr);
798 break;
799 case 2:
800 writew(*(u16 *)data, addr);
801 break;
802 case 4:
803 writel(*(u32 *)data, addr);
804 break;
805 case 8:
806 writeq(*(u64 *)data, addr);
807 break;
808 default:
809 ret = -1;
810 break;
811 }
812 write_unlock_irqrestore(&ha->hw_lock, flags);
813 if (mem_ptr)
814 iounmap(mem_ptr);
815 return ret;
816}
817
a9083016 818#define MTU_FUDGE_FACTOR 100
77e334d2
GM		 819static unsigned long
820qla82xx_decode_crb_addr(unsigned long addr)
a9083016
GM		 821{
822 int i;
823 unsigned long base_addr, offset, pci_base;
824
825 if (!qla82xx_crb_table_initialized)
826 qla82xx_crb_addr_transform_setup();
827
828 pci_base = ADDR_ERROR;
829 base_addr = addr & 0xfff00000;
830 offset = addr & 0x000fffff;
831
832 for (i = 0; i < MAX_CRB_XFORM; i++) {
833 if (crb_addr_xform[i] == base_addr) {
834 pci_base = i << 20;
835 break;
836 }
837 }
838 if (pci_base == ADDR_ERROR)
839 return pci_base;
840 return pci_base + offset;
841}
842
843static long rom_max_timeout = 100;
844static long qla82xx_rom_lock_timeout = 100;
845
77e334d2 846static int
a9083016
GM		 847qla82xx_rom_lock(struct qla_hw_data *ha)
848{
849 int done = 0, timeout = 0;
6c315553
SK		 850 uint32_t lock_owner = 0;
851 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 852
853 while (!done) {
854 /* acquire semaphore2 from PCI HW block */
855 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
856 if (done == 1)
857 break;
6c315553
SK		 858 if (timeout >= qla82xx_rom_lock_timeout) {
859 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
860 ql_dbg(ql_dbg_p3p, vha, 0xb085,
861 "Failed to acquire rom lock, acquired by %d.\n",
862 lock_owner);
a9083016 863 return -1;
6c315553 864 }
a9083016
GM		 865 timeout++;
866 }
867 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER);
868 return 0;
869}
870
d652e093
CD		 871static void
872qla82xx_rom_unlock(struct qla_hw_data *ha)
873{
874 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
875}
876
77e334d2 877static int
a9083016
GM		 878qla82xx_wait_rom_busy(struct qla_hw_data *ha)
879{
880 long timeout = 0;
881 long done = 0 ;
7c3df132 882 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 883
884 while (done == 0) {
885 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
886 done &= 4;
887 timeout++;
888 if (timeout >= rom_max_timeout) {
7c3df132
SK		 889 ql_dbg(ql_dbg_p3p, vha, 0xb00a,
890 "%s: Timeout reached waiting for rom busy.\n",
891 QLA2XXX_DRIVER_NAME);
a9083016
GM		 892 return -1;
893 }
894 }
895 return 0;
896}
897
77e334d2 898static int
a9083016
GM		 899qla82xx_wait_rom_done(struct qla_hw_data *ha)
900{
901 long timeout = 0;
902 long done = 0 ;
7c3df132 903 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 904
905 while (done == 0) {
906 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
907 done &= 2;
908 timeout++;
909 if (timeout >= rom_max_timeout) {
7c3df132
SK		 910 ql_dbg(ql_dbg_p3p, vha, 0xb00b,
911 "%s: Timeout reached waiting for rom done.\n",
912 QLA2XXX_DRIVER_NAME);
a9083016
GM		 913 return -1;
914 }
915 }
916 return 0;
917}
918
fa492630 919static int
2b29d96d
CD		 920qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag)
921{
922 uint32_t off_value, rval = 0;
923
fa492630 924 WRT_REG_DWORD((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase),
2b29d96d
CD		 925 (off & 0xFFFF0000));
926
927 /* Read back value to make sure write has gone through */
fa492630 928 RD_REG_DWORD((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
2b29d96d
CD		 929 off_value = (off & 0x0000FFFF);
930
931 if (flag)
fa492630 932 WRT_REG_DWORD((void __iomem *)
2b29d96d
CD		 933 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase),
934 data);
935 else
fa492630 936 rval = RD_REG_DWORD((void __iomem *)
2b29d96d
CD		 937 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase));
938
939 return rval;
940}
941
77e334d2 942static int
a9083016
GM		 943qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
944{
2b29d96d
CD		 945 /* Dword reads to flash. */
946 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1);
947 *valp = qla82xx_md_rw_32(ha, MD_DIRECT_ROM_READ_BASE +
948 (addr & 0x0000FFFF), 0, 0);
7c3df132 949
a9083016
GM		 950 return 0;
951}
952
77e334d2 953static int
a9083016
GM		 954qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
955{
956 int ret, loops = 0;
7c3df132 957 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 958
959 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
960 udelay(100);
961 schedule();
962 loops++;
963 }
964 if (loops >= 50000) {
7c3df132 965 ql_log(ql_log_fatal, vha, 0x00b9,
a720101d 966 "Failed to acquire SEM2 lock.\n");
a9083016
GM		 967 return -1;
968 }
969 ret = qla82xx_do_rom_fast_read(ha, addr, valp);
d652e093 970 qla82xx_rom_unlock(ha);
a9083016
GM		 971 return ret;
972}
973
77e334d2 974static int
a9083016
GM		 975qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val)
976{
7c3df132 977 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 978 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR);
979 qla82xx_wait_rom_busy(ha);
980 if (qla82xx_wait_rom_done(ha)) {
7c3df132
SK		 981 ql_log(ql_log_warn, vha, 0xb00c,
982 "Error waiting for rom done.\n");
a9083016
GM		 983 return -1;
984 }
985 *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
986 return 0;
987}
988
77e334d2 989static int
a9083016
GM		 990qla82xx_flash_wait_write_finish(struct qla_hw_data *ha)
991{
992 long timeout = 0;
993 uint32_t done = 1 ;
994 uint32_t val;
995 int ret = 0;
7c3df132 996 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 997
998 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
999 while ((done != 0) && (ret == 0)) {
1000 ret = qla82xx_read_status_reg(ha, &val);
1001 done = val & 1;
1002 timeout++;
1003 udelay(10);
1004 cond_resched();
1005 if (timeout >= 50000) {
7c3df132
SK		 1006 ql_log(ql_log_warn, vha, 0xb00d,
1007 "Timeout reached waiting for write finish.\n");
a9083016
GM		 1008 return -1;
1009 }
1010 }
1011 return ret;
1012}
1013
77e334d2 1014static int
a9083016
GM		 1015qla82xx_flash_set_write_enable(struct qla_hw_data *ha)
1016{
1017 uint32_t val;
1018 qla82xx_wait_rom_busy(ha);
1019 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
1020 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN);
1021 qla82xx_wait_rom_busy(ha);
1022 if (qla82xx_wait_rom_done(ha))
1023 return -1;
1024 if (qla82xx_read_status_reg(ha, &val) != 0)
1025 return -1;
1026 if ((val & 2) != 2)
1027 return -1;
1028 return 0;
1029}
1030
77e334d2 1031static int
a9083016
GM		 1032qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val)
1033{
7c3df132 1034 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 1035 if (qla82xx_flash_set_write_enable(ha))
1036 return -1;
1037 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val);
1038 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1);
1039 if (qla82xx_wait_rom_done(ha)) {
7c3df132
SK		 1040 ql_log(ql_log_warn, vha, 0xb00e,
1041 "Error waiting for rom done.\n");
a9083016
GM		 1042 return -1;
1043 }
1044 return qla82xx_flash_wait_write_finish(ha);
1045}
1046
77e334d2 1047static int
a9083016
GM		 1048qla82xx_write_disable_flash(struct qla_hw_data *ha)
1049{
7c3df132 1050 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 1051 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI);
1052 if (qla82xx_wait_rom_done(ha)) {
7c3df132
SK		 1053 ql_log(ql_log_warn, vha, 0xb00f,
1054 "Error waiting for rom done.\n");
a9083016
GM		 1055 return -1;
1056 }
1057 return 0;
1058}
1059
77e334d2 1060static int
a9083016
GM		 1061ql82xx_rom_lock_d(struct qla_hw_data *ha)
1062{
1063 int loops = 0;
7c3df132
SK		 1064 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1065
a9083016
GM		 1066 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
1067 udelay(100);
1068 cond_resched();
1069 loops++;
1070 }
1071 if (loops >= 50000) {
7c3df132
SK		 1072 ql_log(ql_log_warn, vha, 0xb010,
1073 "ROM lock failed.\n");
a9083016
GM		 1074 return -1;
1075 }
cd6dbb03 1076 return 0;
a9083016
GM		 1077}
1078
77e334d2 1079static int
a9083016
GM		 1080qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr,
1081 uint32_t data)
1082{
1083 int ret = 0;
7c3df132 1084 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 1085
1086 ret = ql82xx_rom_lock_d(ha);
1087 if (ret < 0) {
7c3df132
SK		 1088 ql_log(ql_log_warn, vha, 0xb011,
1089 "ROM lock failed.\n");
a9083016
GM		 1090 return ret;
1091 }
1092
1093 if (qla82xx_flash_set_write_enable(ha))
1094 goto done_write;
1095
1096 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data);
1097 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr);
1098 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
1099 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP);
1100 qla82xx_wait_rom_busy(ha);
1101 if (qla82xx_wait_rom_done(ha)) {
7c3df132
SK		 1102 ql_log(ql_log_warn, vha, 0xb012,
1103 "Error waiting for rom done.\n");
a9083016
GM		 1104 ret = -1;
1105 goto done_write;
1106 }
1107
1108 ret = qla82xx_flash_wait_write_finish(ha);
1109
1110done_write:
d652e093 1111 qla82xx_rom_unlock(ha);
a9083016
GM		 1112 return ret;
1113}
1114
1115/* This routine does CRB initialize sequence
1116 * to put the ISP into operational state
1117 */
77e334d2
GM		 1118static int
1119qla82xx_pinit_from_rom(scsi_qla_host_t *vha)
a9083016
GM		 1120{
1121 int addr, val;
1122 int i ;
1123 struct crb_addr_pair *buf;
1124 unsigned long off;
1125 unsigned offset, n;
1126 struct qla_hw_data *ha = vha->hw;
1127
1128 struct crb_addr_pair {
1129 long addr;
1130 long data;
1131 };
1132
a720101d 1133 /* Halt all the individual PEGs and other blocks of the ISP */
a9083016 1134 qla82xx_rom_lock(ha);
c9e8fd5c 1135
02be2215
GM		 1136 /* disable all I2Q */
1137 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
1138 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
1139 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
1140 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
1141 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
1142 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
1143
1144 /* disable all niu interrupts */
c9e8fd5c
MI		 1145 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
1146 /* disable xge rx/tx */
1147 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
1148 /* disable xg1 rx/tx */
1149 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
02be2215
GM		 1150 /* disable sideband mac */
1151 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
1152 /* disable ap0 mac */
1153 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
1154 /* disable ap1 mac */
1155 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
c9e8fd5c
MI		 1156
1157 /* halt sre */
1158 val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
1159 qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
1160
1161 /* halt epg */
1162 qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
1163
1164 /* halt timers */
1165 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
1166 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
1167 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
1168 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
1169 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
02be2215 1170 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
c9e8fd5c
MI		 1171
1172 /* halt pegs */
1173 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
1174 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
1175 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
1176 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
1177 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
02be2215 1178 msleep(20);
c9e8fd5c
MI		 1179
1180 /* big hammer */
a9083016
GM		 1181 if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
1182 /* don't reset CAM block on reset */
1183 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
1184 else
1185 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
d652e093 1186 qla82xx_rom_unlock(ha);
a9083016
GM		 1187
1188 /* Read the signature value from the flash.
1189 * Offset 0: Contain signature (0xcafecafe)
1190 * Offset 4: Offset and number of addr/value pairs
1191 * that present in CRB initialize sequence
1192 */
1193 if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1194 qla82xx_rom_fast_read(ha, 4, &n) != 0) {
7c3df132
SK		 1195 ql_log(ql_log_fatal, vha, 0x006e,
1196 "Error Reading crb_init area: n: %08x.\n", n);
a9083016
GM		 1197 return -1;
1198 }
1199
1200 /* Offset in flash = lower 16 bits
00adc9a0 1201 * Number of entries = upper 16 bits
a9083016
GM		 1202 */
1203 offset = n & 0xffffU;
1204 n = (n >> 16) & 0xffffU;
1205
00adc9a0 1206 /* number of addr/value pair should not exceed 1024 entries */
a9083016 1207 if (n >= 1024) {
7c3df132
SK		 1208 ql_log(ql_log_fatal, vha, 0x0071,
1209 "Card flash not initialized:n=0x%x.\n", n);
a9083016
GM		 1210 return -1;
1211 }
1212
7c3df132
SK		 1213 ql_log(ql_log_info, vha, 0x0072,
1214 "%d CRB init values found in ROM.\n", n);
a9083016
GM		 1215
1216 buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL);
1217 if (buf == NULL) {
7c3df132
SK		 1218 ql_log(ql_log_fatal, vha, 0x010c,
1219 "Unable to allocate memory.\n");
a9083016
GM		 1220 return -1;
1221 }
1222
1223 for (i = 0; i < n; i++) {
1224 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1225 qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) {
1226 kfree(buf);
1227 return -1;
1228 }
1229
1230 buf[i].addr = addr;
1231 buf[i].data = val;
1232 }
1233
1234 for (i = 0; i < n; i++) {
1235 /* Translate internal CRB initialization
1236 * address to PCI bus address
1237 */
1238 off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) +
1239 QLA82XX_PCI_CRBSPACE;
1240 /* Not all CRB addr/value pair to be written,
1241 * some of them are skipped
1242 */
1243
1244 /* skipping cold reboot MAGIC */
1245 if (off == QLA82XX_CAM_RAM(0x1fc))
1246 continue;
1247
1248 /* do not reset PCI */
1249 if (off == (ROMUSB_GLB + 0xbc))
1250 continue;
1251
1252 /* skip core clock, so that firmware can increase the clock */
1253 if (off == (ROMUSB_GLB + 0xc8))
1254 continue;
1255
1256 /* skip the function enable register */
1257 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
1258 continue;
1259
1260 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
1261 continue;
1262
1263 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
1264 continue;
1265
1266 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
1267 continue;
1268
1269 if (off == ADDR_ERROR) {
7c3df132
SK		 1270 ql_log(ql_log_fatal, vha, 0x0116,
1271 "Unknow addr: 0x%08lx.\n", buf[i].addr);
a9083016
GM		 1272 continue;
1273 }
1274
a9083016
GM		 1275 qla82xx_wr_32(ha, off, buf[i].data);
1276
1277 /* ISP requires much bigger delay to settle down,
1278 * else crb_window returns 0xffffffff
1279 */
1280 if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1281 msleep(1000);
1282
1283 /* ISP requires millisec delay between
1284 * successive CRB register updation
1285 */
1286 msleep(1);
1287 }
1288
1289 kfree(buf);
1290
1291 /* Resetting the data and instruction cache */
1292 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1293 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1294 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
1295
1296 /* Clear all protocol processing engines */
1297 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1298 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1299 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1300 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1301 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1302 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1303 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1304 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
1305 return 0;
1306}
1307
77e334d2
GM		 1308static int
1309qla82xx_pci_mem_write_2M(struct qla_hw_data *ha,
1310 u64 off, void *data, int size)
1311{
1312 int i, j, ret = 0, loop, sz[2], off0;
1313 int scale, shift_amount, startword;
1314 uint32_t temp;
1315 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1316
1317 /*
1318 * If not MN, go check for MS or invalid.
1319 */
1320 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1321 mem_crb = QLA82XX_CRB_QDR_NET;
1322 else {
1323 mem_crb = QLA82XX_CRB_DDR_NET;
1324 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1325 return qla82xx_pci_mem_write_direct(ha,
1326 off, data, size);
1327 }
1328
1329 off0 = off & 0x7;
1330 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1331 sz[1] = size - sz[0];
1332
1333 off8 = off & 0xfffffff0;
1334 loop = (((off & 0xf) + size - 1) >> 4) + 1;
1335 shift_amount = 4;
1336 scale = 2;
1337 startword = (off & 0xf)/8;
1338
1339 for (i = 0; i < loop; i++) {
1340 if (qla82xx_pci_mem_read_2M(ha, off8 +
1341 (i << shift_amount), &word[i * scale], 8))
1342 return -1;
1343 }
1344
1345 switch (size) {
1346 case 1:
1347 tmpw = *((uint8_t *)data);
1348 break;
1349 case 2:
1350 tmpw = *((uint16_t *)data);
1351 break;
1352 case 4:
1353 tmpw = *((uint32_t *)data);
1354 break;
1355 case 8:
1356 default:
1357 tmpw = *((uint64_t *)data);
1358 break;
1359 }
1360
1361 if (sz[0] == 8) {
1362 word[startword] = tmpw;
1363 } else {
1364 word[startword] &=
1365 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1366 word[startword] |= tmpw << (off0 * 8);
1367 }
1368 if (sz[1] != 0) {
1369 word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1370 word[startword+1] |= tmpw >> (sz[0] * 8);
1371 }
1372
77e334d2
GM		 1373 for (i = 0; i < loop; i++) {
1374 temp = off8 + (i << shift_amount);
1375 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1376 temp = 0;
1377 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1378 temp = word[i * scale] & 0xffffffff;
1379 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1380 temp = (word[i * scale] >> 32) & 0xffffffff;
1381 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1382 temp = word[i*scale + 1] & 0xffffffff;
1383 qla82xx_wr_32(ha, mem_crb +
1384 MIU_TEST_AGT_WRDATA_UPPER_LO, temp);
1385 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1386 qla82xx_wr_32(ha, mem_crb +
1387 MIU_TEST_AGT_WRDATA_UPPER_HI, temp);
1388
1389 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1390 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1391 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1392 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1393
1394 for (j = 0; j < MAX_CTL_CHECK; j++) {
1395 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1396 if ((temp & MIU_TA_CTL_BUSY) == 0)
1397 break;
1398 }
1399
1400 if (j >= MAX_CTL_CHECK) {
1401 if (printk_ratelimit())
1402 dev_err(&ha->pdev->dev,
7c3df132 1403 "failed to write through agent.\n");
77e334d2
GM		 1404 ret = -1;
1405 break;
1406 }
1407 }
1408
1409 return ret;
1410}
1411
1412static int
a9083016
GM		 1413qla82xx_fw_load_from_flash(struct qla_hw_data *ha)
1414{
1415 int i;
1416 long size = 0;
9c2b2975
HZ		 1417 long flashaddr = ha->flt_region_bootload << 2;
1418 long memaddr = BOOTLD_START;
a9083016
GM		 1419 u64 data;
1420 u32 high, low;
1421 size = (IMAGE_START - BOOTLD_START) / 8;
1422
1423 for (i = 0; i < size; i++) {
1424 if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1425 (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) {
1426 return -1;
1427 }
1428 data = ((u64)high << 32) | low ;
1429 qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
1430 flashaddr += 8;
1431 memaddr += 8;
1432
1433 if (i % 0x1000 == 0)
1434 msleep(1);
1435 }
1436 udelay(100);
1437 read_lock(&ha->hw_lock);
3711333d
GM		 1438 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1439 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
a9083016
GM		 1440 read_unlock(&ha->hw_lock);
1441 return 0;
1442}
1443
1444int
1445qla82xx_pci_mem_read_2M(struct qla_hw_data *ha,
1446 u64 off, void *data, int size)
1447{
1448 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1449 int shift_amount;
1450 uint32_t temp;
1451 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1452
1453 /*
1454 * If not MN, go check for MS or invalid.
1455 */
1456
1457 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1458 mem_crb = QLA82XX_CRB_QDR_NET;
1459 else {
1460 mem_crb = QLA82XX_CRB_DDR_NET;
1461 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1462 return qla82xx_pci_mem_read_direct(ha,
1463 off, data, size);
1464 }
1465
3711333d
GM		 1466 off8 = off & 0xfffffff0;
1467 off0[0] = off & 0xf;
1468 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1469 shift_amount = 4;
a9083016
GM		 1470 loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1471 off0[1] = 0;
1472 sz[1] = size - sz[0];
1473
a9083016
GM		 1474 for (i = 0; i < loop; i++) {
1475 temp = off8 + (i << shift_amount);
1476 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1477 temp = 0;
1478 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1479 temp = MIU_TA_CTL_ENABLE;
1480 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1481 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1482 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1483
1484 for (j = 0; j < MAX_CTL_CHECK; j++) {
1485 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1486 if ((temp & MIU_TA_CTL_BUSY) == 0)
1487 break;
1488 }
1489
1490 if (j >= MAX_CTL_CHECK) {
1491 if (printk_ratelimit())
1492 dev_err(&ha->pdev->dev,
7c3df132 1493 "failed to read through agent.\n");
a9083016
GM		 1494 break;
1495 }
1496
1497 start = off0[i] >> 2;
1498 end = (off0[i] + sz[i] - 1) >> 2;
1499 for (k = start; k <= end; k++) {
1500 temp = qla82xx_rd_32(ha,
1501 mem_crb + MIU_TEST_AGT_RDDATA(k));
1502 word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1503 }
1504 }
1505
a9083016
GM		 1506 if (j >= MAX_CTL_CHECK)
1507 return -1;
1508
1509 if ((off0[0] & 7) == 0) {
1510 val = word[0];
1511 } else {
1512 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1513 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1514 }
1515
1516 switch (size) {
1517 case 1:
1518 *(uint8_t *)data = val;
1519 break;
1520 case 2:
1521 *(uint16_t *)data = val;
1522 break;
1523 case 4:
1524 *(uint32_t *)data = val;
1525 break;
1526 case 8:
1527 *(uint64_t *)data = val;
1528 break;
1529 }
1530 return 0;
1531}
1532
a9083016 1533
9c2b2975
HZ		 1534static struct qla82xx_uri_table_desc *
1535qla82xx_get_table_desc(const u8 *unirom, int section)
1536{
1537 uint32_t i;
1538 struct qla82xx_uri_table_desc *directory =
1539 (struct qla82xx_uri_table_desc *)&unirom[0];
1540 __le32 offset;
1541 __le32 tab_type;
1542 __le32 entries = cpu_to_le32(directory->num_entries);
1543
1544 for (i = 0; i < entries; i++) {
1545 offset = cpu_to_le32(directory->findex) +
1546 (i * cpu_to_le32(directory->entry_size));
1547 tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8));
1548
1549 if (tab_type == section)
1550 return (struct qla82xx_uri_table_desc *)&unirom[offset];
1551 }
1552
1553 return NULL;
1554}
1555
1556static struct qla82xx_uri_data_desc *
1557qla82xx_get_data_desc(struct qla_hw_data *ha,
1558 u32 section, u32 idx_offset)
1559{
1560 const u8 *unirom = ha->hablob->fw->data;
1561 int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset));
1562 struct qla82xx_uri_table_desc *tab_desc = NULL;
1563 __le32 offset;
1564
1565 tab_desc = qla82xx_get_table_desc(unirom, section);
1566 if (!tab_desc)
1567 return NULL;
1568
1569 offset = cpu_to_le32(tab_desc->findex) +
1570 (cpu_to_le32(tab_desc->entry_size) * idx);
1571
1572 return (struct qla82xx_uri_data_desc *)&unirom[offset];
1573}
1574
1575static u8 *
1576qla82xx_get_bootld_offset(struct qla_hw_data *ha)
1577{
1578 u32 offset = BOOTLD_START;
1579 struct qla82xx_uri_data_desc *uri_desc = NULL;
1580
1581 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1582 uri_desc = qla82xx_get_data_desc(ha,
1583 QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF);
1584 if (uri_desc)
1585 offset = cpu_to_le32(uri_desc->findex);
1586 }
1587
1588 return (u8 *)&ha->hablob->fw->data[offset];
1589}
1590
1591static __le32
1592qla82xx_get_fw_size(struct qla_hw_data *ha)
1593{
1594 struct qla82xx_uri_data_desc *uri_desc = NULL;
1595
1596 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1597 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
1598 QLA82XX_URI_FIRMWARE_IDX_OFF);
1599 if (uri_desc)
1600 return cpu_to_le32(uri_desc->size);
1601 }
1602
1603 return cpu_to_le32(*(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]);
1604}
1605
1606static u8 *
1607qla82xx_get_fw_offs(struct qla_hw_data *ha)
1608{
1609 u32 offset = IMAGE_START;
1610 struct qla82xx_uri_data_desc *uri_desc = NULL;
1611
1612 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1613 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
1614 QLA82XX_URI_FIRMWARE_IDX_OFF);
1615 if (uri_desc)
1616 offset = cpu_to_le32(uri_desc->findex);
1617 }
1618
1619 return (u8 *)&ha->hablob->fw->data[offset];
1620}
1621
a9083016 1622/* PCI related functions */
a9083016
GM		 1623int qla82xx_pci_region_offset(struct pci_dev *pdev, int region)
1624{
1625 unsigned long val = 0;
1626 u32 control;
1627
1628 switch (region) {
1629 case 0:
1630 val = 0;
1631 break;
1632 case 1:
1633 pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control);
1634 val = control + QLA82XX_MSIX_TBL_SPACE;
1635 break;
1636 }
1637 return val;
1638}
1639
a9083016
GM		 1640
1641int
1642qla82xx_iospace_config(struct qla_hw_data *ha)
1643{
1644 uint32_t len = 0;
1645
1646 if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) {
7c3df132
SK		 1647 ql_log_pci(ql_log_fatal, ha->pdev, 0x000c,
1648 "Failed to reserver selected regions.\n");
a9083016
GM		 1649 goto iospace_error_exit;
1650 }
1651
1652 /* Use MMIO operations for all accesses. */
1653 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
7c3df132
SK		 1654 ql_log_pci(ql_log_fatal, ha->pdev, 0x000d,
1655 "Region #0 not an MMIO resource, aborting.\n");
a9083016
GM		 1656 goto iospace_error_exit;
1657 }
1658
1659 len = pci_resource_len(ha->pdev, 0);
1660 ha->nx_pcibase =
1661 (unsigned long)ioremap(pci_resource_start(ha->pdev, 0), len);
1662 if (!ha->nx_pcibase) {
7c3df132
SK		 1663 ql_log_pci(ql_log_fatal, ha->pdev, 0x000e,
1664 "Cannot remap pcibase MMIO, aborting.\n");
a9083016
GM		 1665 goto iospace_error_exit;
1666 }
1667
1668 /* Mapping of IO base pointer */
1669 ha->iobase = (device_reg_t __iomem *)((uint8_t *)ha->nx_pcibase +
1670 0xbc000 + (ha->pdev->devfn << 11));
1671
1672 if (!ql2xdbwr) {
1673 ha->nxdb_wr_ptr =
1674 (unsigned long)ioremap((pci_resource_start(ha->pdev, 4) +
1675 (ha->pdev->devfn << 12)), 4);
1676 if (!ha->nxdb_wr_ptr) {
7c3df132
SK		 1677 ql_log_pci(ql_log_fatal, ha->pdev, 0x000f,
1678 "Cannot remap MMIO, aborting.\n");
a9083016
GM		 1679 goto iospace_error_exit;
1680 }
1681
1682 /* Mapping of IO base pointer,
1683 * door bell read and write pointer
1684 */
1685 ha->nxdb_rd_ptr = (uint8_t *) ha->nx_pcibase + (512 * 1024) +
1686 (ha->pdev->devfn * 8);
1687 } else {
1688 ha->nxdb_wr_ptr = (ha->pdev->devfn == 6 ?
1689 QLA82XX_CAMRAM_DB1 :
1690 QLA82XX_CAMRAM_DB2);
1691 }
1692
1693 ha->max_req_queues = ha->max_rsp_queues = 1;
1694 ha->msix_count = ha->max_rsp_queues + 1;
7c3df132
SK		 1695 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006,
1696 "nx_pci_base=%p iobase=%p "
1697 "max_req_queues=%d msix_count=%d.\n",
d8424f68 1698 (void *)ha->nx_pcibase, ha->iobase,
7c3df132
SK		 1699 ha->max_req_queues, ha->msix_count);
1700 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010,
1701 "nx_pci_base=%p iobase=%p "
1702 "max_req_queues=%d msix_count=%d.\n",
d8424f68 1703 (void *)ha->nx_pcibase, ha->iobase,
7c3df132 1704 ha->max_req_queues, ha->msix_count);
a9083016
GM		 1705 return 0;
1706
1707iospace_error_exit:
1708 return -ENOMEM;
1709}
1710
1711/* GS related functions */
1712
1713/* Initialization related functions */
1714
1715/**
1716 * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers.
1717 * @ha: HA context
1718 *
1719 * Returns 0 on success.
1720*/
1721int
1722qla82xx_pci_config(scsi_qla_host_t *vha)
1723{
1724 struct qla_hw_data *ha = vha->hw;
1725 int ret;
1726
1727 pci_set_master(ha->pdev);
1728 ret = pci_set_mwi(ha->pdev);
1729 ha->chip_revision = ha->pdev->revision;
7c3df132 1730 ql_dbg(ql_dbg_init, vha, 0x0043,
d8424f68 1731 "Chip revision:%d.\n",
7c3df132 1732 ha->chip_revision);
a9083016
GM		 1733 return 0;
1734}
1735
1736/**
1737 * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers.
1738 * @ha: HA context
1739 *
1740 * Returns 0 on success.
1741 */
1742void
1743qla82xx_reset_chip(scsi_qla_host_t *vha)
1744{
1745 struct qla_hw_data *ha = vha->hw;
1746 ha->isp_ops->disable_intrs(ha);
1747}
1748
1749void qla82xx_config_rings(struct scsi_qla_host *vha)
1750{
1751 struct qla_hw_data *ha = vha->hw;
1752 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
1753 struct init_cb_81xx *icb;
1754 struct req_que *req = ha->req_q_map[0];
1755 struct rsp_que *rsp = ha->rsp_q_map[0];
1756
1757 /* Setup ring parameters in initialization control block. */
1758 icb = (struct init_cb_81xx *)ha->init_cb;
1759 icb->request_q_outpointer = __constant_cpu_to_le16(0);
1760 icb->response_q_inpointer = __constant_cpu_to_le16(0);
1761 icb->request_q_length = cpu_to_le16(req->length);
1762 icb->response_q_length = cpu_to_le16(rsp->length);
1763 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1764 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1765 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1766 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
1767
a9083016
GM		 1768 WRT_REG_DWORD((unsigned long __iomem *)&reg->req_q_out[0], 0);
1769 WRT_REG_DWORD((unsigned long __iomem *)&reg->rsp_q_in[0], 0);
1770 WRT_REG_DWORD((unsigned long __iomem *)&reg->rsp_q_out[0], 0);
1771}
1772
77e334d2
GM		 1773static int
1774qla82xx_fw_load_from_blob(struct qla_hw_data *ha)
a9083016
GM		 1775{
1776 u64 *ptr64;
1777 u32 i, flashaddr, size;
1778 __le64 data;
1779
1780 size = (IMAGE_START - BOOTLD_START) / 8;
1781
9c2b2975 1782 ptr64 = (u64 *)qla82xx_get_bootld_offset(ha);
a9083016
GM		 1783 flashaddr = BOOTLD_START;
1784
1785 for (i = 0; i < size; i++) {
1786 data = cpu_to_le64(ptr64[i]);
9c2b2975
HZ		 1787 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1788 return -EIO;
a9083016
GM		 1789 flashaddr += 8;
1790 }
1791
a9083016 1792 flashaddr = FLASH_ADDR_START;
9c2b2975
HZ		 1793 size = (__force u32)qla82xx_get_fw_size(ha) / 8;
1794 ptr64 = (u64 *)qla82xx_get_fw_offs(ha);
a9083016
GM		 1795
1796 for (i = 0; i < size; i++) {
1797 data = cpu_to_le64(ptr64[i]);
1798
1799 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1800 return -EIO;
1801 flashaddr += 8;
1802 }
9c2b2975 1803 udelay(100);
a9083016
GM		 1804
1805 /* Write a magic value to CAMRAM register
1806 * at a specified offset to indicate
1807 * that all data is written and
1808 * ready for firmware to initialize.
1809 */
9c2b2975 1810 qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC);
a9083016 1811
9c2b2975 1812 read_lock(&ha->hw_lock);
3711333d
GM		 1813 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1814 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
9c2b2975
HZ		 1815 read_unlock(&ha->hw_lock);
1816 return 0;
1817}
1818
1819static int
1820qla82xx_set_product_offset(struct qla_hw_data *ha)
1821{
1822 struct qla82xx_uri_table_desc *ptab_desc = NULL;
1823 const uint8_t *unirom = ha->hablob->fw->data;
1824 uint32_t i;
1825 __le32 entries;
1826 __le32 flags, file_chiprev, offset;
1827 uint8_t chiprev = ha->chip_revision;
1828 /* Hardcoding mn_present flag for P3P */
1829 int mn_present = 0;
1830 uint32_t flagbit;
1831
1832 ptab_desc = qla82xx_get_table_desc(unirom,
1833 QLA82XX_URI_DIR_SECT_PRODUCT_TBL);
1834 if (!ptab_desc)
1835 return -1;
1836
1837 entries = cpu_to_le32(ptab_desc->num_entries);
1838
1839 for (i = 0; i < entries; i++) {
1840 offset = cpu_to_le32(ptab_desc->findex) +
1841 (i * cpu_to_le32(ptab_desc->entry_size));
1842 flags = cpu_to_le32(*((int *)&unirom[offset] +
1843 QLA82XX_URI_FLAGS_OFF));
1844 file_chiprev = cpu_to_le32(*((int *)&unirom[offset] +
1845 QLA82XX_URI_CHIP_REV_OFF));
1846
1847 flagbit = mn_present ? 1 : 2;
1848
1849 if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) {
1850 ha->file_prd_off = offset;
1851 return 0;
1852 }
1853 }
1854 return -1;
1855}
1856
fa492630 1857static int
9c2b2975
HZ		 1858qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type)
1859{
1860 __le32 val;
1861 uint32_t min_size;
1862 struct qla_hw_data *ha = vha->hw;
1863 const struct firmware *fw = ha->hablob->fw;
1864
1865 ha->fw_type = fw_type;
1866
1867 if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1868 if (qla82xx_set_product_offset(ha))
1869 return -EINVAL;
1870
1871 min_size = QLA82XX_URI_FW_MIN_SIZE;
1872 } else {
1873 val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]);
1874 if ((__force u32)val != QLA82XX_BDINFO_MAGIC)
1875 return -EINVAL;
1876
1877 min_size = QLA82XX_FW_MIN_SIZE;
1878 }
1879
1880 if (fw->size < min_size)
1881 return -EINVAL;
a9083016
GM		 1882 return 0;
1883}
1884
77e334d2
GM		 1885static int
1886qla82xx_check_cmdpeg_state(struct qla_hw_data *ha)
a9083016
GM		 1887{
1888 u32 val = 0;
1889 int retries = 60;
7c3df132 1890 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 1891
1892 do {
1893 read_lock(&ha->hw_lock);
1894 val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE);
1895 read_unlock(&ha->hw_lock);
1896
1897 switch (val) {
1898 case PHAN_INITIALIZE_COMPLETE:
1899 case PHAN_INITIALIZE_ACK:
1900 return QLA_SUCCESS;
1901 case PHAN_INITIALIZE_FAILED:
1902 break;
1903 default:
1904 break;
1905 }
7c3df132
SK		 1906 ql_log(ql_log_info, vha, 0x00a8,
1907 "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n",
1908 val, retries);
a9083016
GM		 1909
1910 msleep(500);
1911
1912 } while (--retries);
1913
7c3df132 1914 ql_log(ql_log_fatal, vha, 0x00a9,
a9083016
GM		 1915 "Cmd Peg initialization failed: 0x%x.\n", val);
1916
a9083016
GM		 1917 val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
1918 read_lock(&ha->hw_lock);
1919 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
1920 read_unlock(&ha->hw_lock);
1921 return QLA_FUNCTION_FAILED;
1922}
1923
77e334d2
GM		 1924static int
1925qla82xx_check_rcvpeg_state(struct qla_hw_data *ha)
a9083016
GM		 1926{
1927 u32 val = 0;
1928 int retries = 60;
7c3df132 1929 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 1930
1931 do {
1932 read_lock(&ha->hw_lock);
1933 val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE);
1934 read_unlock(&ha->hw_lock);
1935
1936 switch (val) {
1937 case PHAN_INITIALIZE_COMPLETE:
1938 case PHAN_INITIALIZE_ACK:
1939 return QLA_SUCCESS;
1940 case PHAN_INITIALIZE_FAILED:
1941 break;
1942 default:
1943 break;
1944 }
7c3df132
SK		 1945 ql_log(ql_log_info, vha, 0x00ab,
1946 "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n",
1947 val, retries);
a9083016
GM		 1948
1949 msleep(500);
1950
1951 } while (--retries);
1952
7c3df132
SK		 1953 ql_log(ql_log_fatal, vha, 0x00ac,
1954 "Rcv Peg initializatin failed: 0x%x.\n", val);
a9083016
GM		 1955 read_lock(&ha->hw_lock);
1956 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED);
1957 read_unlock(&ha->hw_lock);
1958 return QLA_FUNCTION_FAILED;
1959}
1960
1961/* ISR related functions */
a9083016
GM		 1962static struct qla82xx_legacy_intr_set legacy_intr[] = \
1963 QLA82XX_LEGACY_INTR_CONFIG;
1964
1965/*
1966 * qla82xx_mbx_completion() - Process mailbox command completions.
1967 * @ha: SCSI driver HA context
1968 * @mb0: Mailbox0 register
1969 */
77e334d2 1970static void
a9083016
GM		 1971qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
1972{
1973 uint16_t cnt;
1974 uint16_t __iomem *wptr;
1975 struct qla_hw_data *ha = vha->hw;
1976 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
1977 wptr = (uint16_t __iomem *)&reg->mailbox_out[1];
1978
1979 /* Load return mailbox registers. */
1980 ha->flags.mbox_int = 1;
1981 ha->mailbox_out[0] = mb0;
1982
1983 for (cnt = 1; cnt < ha->mbx_count; cnt++) {
1984 ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
1985 wptr++;
1986 }
1987
cfb0919c 1988 if (!ha->mcp)
7c3df132
SK		 1989 ql_dbg(ql_dbg_async, vha, 0x5053,
1990 "MBX pointer ERROR.\n");
a9083016
GM		 1991}
1992
1993/*
1994 * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
1995 * @irq:
1996 * @dev_id: SCSI driver HA context
1997 * @regs:
1998 *
1999 * Called by system whenever the host adapter generates an interrupt.
2000 *
2001 * Returns handled flag.
2002 */
2003irqreturn_t
2004qla82xx_intr_handler(int irq, void *dev_id)
2005{
2006 scsi_qla_host_t *vha;
2007 struct qla_hw_data *ha;
2008 struct rsp_que *rsp;
2009 struct device_reg_82xx __iomem *reg;
2010 int status = 0, status1 = 0;
2011 unsigned long flags;
2012 unsigned long iter;
7c3df132 2013 uint32_t stat = 0;
a9083016
GM		 2014 uint16_t mb[4];
2015
2016 rsp = (struct rsp_que *) dev_id;
2017 if (!rsp) {
b6d0d9d5 2018 ql_log(ql_log_info, NULL, 0xb053,
3256b435 2019 "%s: NULL response queue pointer.\n", __func__);
a9083016
GM		 2020 return IRQ_NONE;
2021 }
2022 ha = rsp->hw;
2023
2024 if (!ha->flags.msi_enabled) {
2025 status = qla82xx_rd_32(ha, ISR_INT_VECTOR);
2026 if (!(status & ha->nx_legacy_intr.int_vec_bit))
2027 return IRQ_NONE;
2028
2029 status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG);
2030 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1))
2031 return IRQ_NONE;
2032 }
2033
2034 /* clear the interrupt */
2035 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff);
2036
2037 /* read twice to ensure write is flushed */
2038 qla82xx_rd_32(ha, ISR_INT_VECTOR);
2039 qla82xx_rd_32(ha, ISR_INT_VECTOR);
2040
2041 reg = &ha->iobase->isp82;
2042
2043 spin_lock_irqsave(&ha->hardware_lock, flags);
2044 vha = pci_get_drvdata(ha->pdev);
2045 for (iter = 1; iter--; ) {
2046
2047 if (RD_REG_DWORD(&reg->host_int)) {
2048 stat = RD_REG_DWORD(&reg->host_status);
a9083016
GM		 2049
2050 switch (stat & 0xff) {
2051 case 0x1:
2052 case 0x2:
2053 case 0x10:
2054 case 0x11:
2055 qla82xx_mbx_completion(vha, MSW(stat));
2056 status |= MBX_INTERRUPT;
2057 break;
2058 case 0x12:
2059 mb[0] = MSW(stat);
2060 mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
2061 mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
2062 mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
2063 qla2x00_async_event(vha, rsp, mb);
2064 break;
2065 case 0x13:
2066 qla24xx_process_response_queue(vha, rsp);
2067 break;
2068 default:
7c3df132
SK		 2069 ql_dbg(ql_dbg_async, vha, 0x5054,
2070 "Unrecognized interrupt type (%d).\n",
2071 stat & 0xff);
a9083016
GM		 2072 break;
2073 }
2074 }
2075 WRT_REG_DWORD(&reg->host_int, 0);
2076 }
2077 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2078 if (!ha->flags.msi_enabled)
2079 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2080
2081#ifdef QL_DEBUG_LEVEL_17
2082 if (!irq && ha->flags.eeh_busy)
7c3df132
SK		 2083 ql_log(ql_log_warn, vha, 0x503d,
2084 "isr:status %x, cmd_flags %lx, mbox_int %x, stat %x.\n",
a9083016
GM		 2085 status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat);
2086#endif
2087
2088 if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
2089 (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
2090 set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
2091 complete(&ha->mbx_intr_comp);
2092 }
2093 return IRQ_HANDLED;
2094}
2095
2096irqreturn_t
2097qla82xx_msix_default(int irq, void *dev_id)
2098{
2099 scsi_qla_host_t *vha;
2100 struct qla_hw_data *ha;
2101 struct rsp_que *rsp;
2102 struct device_reg_82xx __iomem *reg;
2103 int status = 0;
2104 unsigned long flags;
7c3df132 2105 uint32_t stat = 0;
a9083016
GM		 2106 uint16_t mb[4];
2107
2108 rsp = (struct rsp_que *) dev_id;
2109 if (!rsp) {
2110 printk(KERN_INFO
7c3df132 2111 "%s(): NULL response queue pointer.\n", __func__);
a9083016
GM		 2112 return IRQ_NONE;
2113 }
2114 ha = rsp->hw;
2115
2116 reg = &ha->iobase->isp82;
2117
2118 spin_lock_irqsave(&ha->hardware_lock, flags);
2119 vha = pci_get_drvdata(ha->pdev);
2120 do {
2121 if (RD_REG_DWORD(&reg->host_int)) {
2122 stat = RD_REG_DWORD(&reg->host_status);
a9083016
GM		 2123
2124 switch (stat & 0xff) {
2125 case 0x1:
2126 case 0x2:
2127 case 0x10:
2128 case 0x11:
2129 qla82xx_mbx_completion(vha, MSW(stat));
2130 status |= MBX_INTERRUPT;
2131 break;
2132 case 0x12:
2133 mb[0] = MSW(stat);
2134 mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
2135 mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
2136 mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
2137 qla2x00_async_event(vha, rsp, mb);
2138 break;
2139 case 0x13:
2140 qla24xx_process_response_queue(vha, rsp);
2141 break;
2142 default:
7c3df132
SK		 2143 ql_dbg(ql_dbg_async, vha, 0x5041,
2144 "Unrecognized interrupt type (%d).\n",
2145 stat & 0xff);
a9083016
GM		 2146 break;
2147 }
2148 }
2149 WRT_REG_DWORD(&reg->host_int, 0);
2150 } while (0);
2151
2152 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2153
2154#ifdef QL_DEBUG_LEVEL_17
2155 if (!irq && ha->flags.eeh_busy)
7c3df132
SK		 2156 ql_log(ql_log_warn, vha, 0x5044,
2157 "isr:status %x, cmd_flags %lx, mbox_int %x, stat %x.\n",
2158 status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat);
a9083016
GM		 2159#endif
2160
2161 if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
2162 (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
2163 set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
2164 complete(&ha->mbx_intr_comp);
2165 }
2166 return IRQ_HANDLED;
2167}
2168
2169irqreturn_t
2170qla82xx_msix_rsp_q(int irq, void *dev_id)
2171{
2172 scsi_qla_host_t *vha;
2173 struct qla_hw_data *ha;
2174 struct rsp_que *rsp;
2175 struct device_reg_82xx __iomem *reg;
3553d343 2176 unsigned long flags;
a9083016
GM		 2177
2178 rsp = (struct rsp_que *) dev_id;
2179 if (!rsp) {
2180 printk(KERN_INFO
7c3df132 2181 "%s(): NULL response queue pointer.\n", __func__);
a9083016
GM		 2182 return IRQ_NONE;
2183 }
2184
2185 ha = rsp->hw;
2186 reg = &ha->iobase->isp82;
3553d343 2187 spin_lock_irqsave(&ha->hardware_lock, flags);
a9083016
GM		 2188 vha = pci_get_drvdata(ha->pdev);
2189 qla24xx_process_response_queue(vha, rsp);
2190 WRT_REG_DWORD(&reg->host_int, 0);
3553d343 2191 spin_unlock_irqrestore(&ha->hardware_lock, flags);
a9083016
GM		 2192 return IRQ_HANDLED;
2193}
2194
2195void
2196qla82xx_poll(int irq, void *dev_id)
2197{
2198 scsi_qla_host_t *vha;
2199 struct qla_hw_data *ha;
2200 struct rsp_que *rsp;
2201 struct device_reg_82xx __iomem *reg;
2202 int status = 0;
2203 uint32_t stat;
2204 uint16_t mb[4];
2205 unsigned long flags;
2206
2207 rsp = (struct rsp_que *) dev_id;
2208 if (!rsp) {
2209 printk(KERN_INFO
7c3df132 2210 "%s(): NULL response queue pointer.\n", __func__);
a9083016
GM		 2211 return;
2212 }
2213 ha = rsp->hw;
2214
2215 reg = &ha->iobase->isp82;
2216 spin_lock_irqsave(&ha->hardware_lock, flags);
2217 vha = pci_get_drvdata(ha->pdev);
2218
2219 if (RD_REG_DWORD(&reg->host_int)) {
2220 stat = RD_REG_DWORD(&reg->host_status);
2221 switch (stat & 0xff) {
2222 case 0x1:
2223 case 0x2:
2224 case 0x10:
2225 case 0x11:
2226 qla82xx_mbx_completion(vha, MSW(stat));
2227 status |= MBX_INTERRUPT;
2228 break;
2229 case 0x12:
2230 mb[0] = MSW(stat);
2231 mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
2232 mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
2233 mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
2234 qla2x00_async_event(vha, rsp, mb);
2235 break;
2236 case 0x13:
2237 qla24xx_process_response_queue(vha, rsp);
2238 break;
2239 default:
7c3df132
SK		 2240 ql_dbg(ql_dbg_p3p, vha, 0xb013,
2241 "Unrecognized interrupt type (%d).\n",
2242 stat * 0xff);
a9083016
GM		 2243 break;
2244 }
2245 }
2246 WRT_REG_DWORD(&reg->host_int, 0);
2247 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2248}
2249
2250void
2251qla82xx_enable_intrs(struct qla_hw_data *ha)
2252{
2253 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2254 qla82xx_mbx_intr_enable(vha);
2255 spin_lock_irq(&ha->hardware_lock);
2256 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2257 spin_unlock_irq(&ha->hardware_lock);
2258 ha->interrupts_on = 1;
2259}
2260
2261void
2262qla82xx_disable_intrs(struct qla_hw_data *ha)
2263{
2264 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2265 qla82xx_mbx_intr_disable(vha);
2266 spin_lock_irq(&ha->hardware_lock);
2267 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
2268 spin_unlock_irq(&ha->hardware_lock);
2269 ha->interrupts_on = 0;
2270}
2271
2272void qla82xx_init_flags(struct qla_hw_data *ha)
2273{
2274 struct qla82xx_legacy_intr_set *nx_legacy_intr;
2275
2276 /* ISP 8021 initializations */
2277 rwlock_init(&ha->hw_lock);
2278 ha->qdr_sn_window = -1;
2279 ha->ddr_mn_window = -1;
2280 ha->curr_window = 255;
2281 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2282 nx_legacy_intr = &legacy_intr[ha->portnum];
2283 ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit;
2284 ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg;
2285 ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg;
2286 ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg;
2287}
2288
0251ce8c
SK		 2289inline void
2290qla82xx_set_idc_version(scsi_qla_host_t *vha)
2291{
2292 int idc_ver;
2293 uint32_t drv_active;
2294 struct qla_hw_data *ha = vha->hw;
2295
2296 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2297 if (drv_active == (QLA82XX_DRV_ACTIVE << (ha->portnum * 4))) {
2298 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
2299 QLA82XX_IDC_VERSION);
2300 ql_log(ql_log_info, vha, 0xb082,
2301 "IDC version updated to %d\n", QLA82XX_IDC_VERSION);
2302 } else {
2303 idc_ver = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_IDC_VERSION);
2304 if (idc_ver != QLA82XX_IDC_VERSION)
2305 ql_log(ql_log_info, vha, 0xb083,
2306 "qla2xxx driver IDC version %d is not compatible "
2307 "with IDC version %d of the other drivers\n",
2308 QLA82XX_IDC_VERSION, idc_ver);
2309 }
2310}
2311
a5b36321 2312inline void
a9083016
GM		 2313qla82xx_set_drv_active(scsi_qla_host_t *vha)
2314{
2315 uint32_t drv_active;
2316 struct qla_hw_data *ha = vha->hw;
2317
2318 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2319
2320 /* If reset value is all FF's, initialize DRV_ACTIVE */
2321 if (drv_active == 0xffffffff) {
77e334d2
GM		 2322 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE,
2323 QLA82XX_DRV_NOT_ACTIVE);
a9083016
GM		 2324 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2325 }
77e334d2 2326 drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
a9083016
GM		 2327 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
2328}
2329
2330inline void
2331qla82xx_clear_drv_active(struct qla_hw_data *ha)
2332{
2333 uint32_t drv_active;
2334
2335 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
77e334d2 2336 drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
a9083016
GM		 2337 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
2338}
2339
2340static inline int
2341qla82xx_need_reset(struct qla_hw_data *ha)
2342{
2343 uint32_t drv_state;
2344 int rval;
2345
7d613ac6 2346 if (ha->flags.nic_core_reset_owner)
08de2844
GM		 2347 return 1;
2348 else {
2349 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2350 rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2351 return rval;
2352 }
a9083016
GM		 2353}
2354
2355static inline void
2356qla82xx_set_rst_ready(struct qla_hw_data *ha)
2357{
2358 uint32_t drv_state;
2359 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2360
2361 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2362
2363 /* If reset value is all FF's, initialize DRV_STATE */
2364 if (drv_state == 0xffffffff) {
77e334d2 2365 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY);
a9083016
GM		 2366 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2367 }
2368 drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
08de2844
GM		 2369 ql_dbg(ql_dbg_init, vha, 0x00bb,
2370 "drv_state = 0x%08x.\n", drv_state);
a9083016
GM		 2371 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
2372}
2373
2374static inline void
2375qla82xx_clear_rst_ready(struct qla_hw_data *ha)
2376{
2377 uint32_t drv_state;
2378
2379 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2380 drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2381 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
2382}
2383
2384static inline void
2385qla82xx_set_qsnt_ready(struct qla_hw_data *ha)
2386{
2387 uint32_t qsnt_state;
2388
2389 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2390 qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4));
2391 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
2392}
2393
579d12b5
SK		 2394void
2395qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha)
2396{
2397 struct qla_hw_data *ha = vha->hw;
2398 uint32_t qsnt_state;
2399
2400 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2401 qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4));
2402 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
2403}
2404
77e334d2
GM		 2405static int
2406qla82xx_load_fw(scsi_qla_host_t *vha)
a9083016
GM		 2407{
2408 int rst;
2409 struct fw_blob *blob;
2410 struct qla_hw_data *ha = vha->hw;
2411
a9083016 2412 if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) {
7c3df132
SK		 2413 ql_log(ql_log_fatal, vha, 0x009f,
2414 "Error during CRB initialization.\n");
a9083016
GM		 2415 return QLA_FUNCTION_FAILED;
2416 }
2417 udelay(500);
2418
2419 /* Bring QM and CAMRAM out of reset */
2420 rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
2421 rst &= ~((1 << 28) | (1 << 24));
2422 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
2423
2424 /*
2425 * FW Load priority:
2426 * 1) Operational firmware residing in flash.
2427 * 2) Firmware via request-firmware interface (.bin file).
2428 */
2429 if (ql2xfwloadbin == 2)
2430 goto try_blob_fw;
2431
7c3df132
SK		 2432 ql_log(ql_log_info, vha, 0x00a0,
2433 "Attempting to load firmware from flash.\n");
a9083016
GM		 2434
2435 if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) {
7c3df132 2436 ql_log(ql_log_info, vha, 0x00a1,
00adc9a0 2437 "Firmware loaded successfully from flash.\n");
a9083016 2438 return QLA_SUCCESS;
875efad7 2439 } else {
7c3df132
SK		 2440 ql_log(ql_log_warn, vha, 0x0108,
2441 "Firmware load from flash failed.\n");
a9083016 2442 }
875efad7 2443
a9083016 2444try_blob_fw:
7c3df132
SK		 2445 ql_log(ql_log_info, vha, 0x00a2,
2446 "Attempting to load firmware from blob.\n");
a9083016
GM		 2447
2448 /* Load firmware blob. */
2449 blob = ha->hablob = qla2x00_request_firmware(vha);
2450 if (!blob) {
7c3df132 2451 ql_log(ql_log_fatal, vha, 0x00a3,
00adc9a0 2452 "Firmware image not present.\n");
a9083016
GM		 2453 goto fw_load_failed;
2454 }
2455
9c2b2975
HZ		 2456 /* Validating firmware blob */
2457 if (qla82xx_validate_firmware_blob(vha,
2458 QLA82XX_FLASH_ROMIMAGE)) {
2459 /* Fallback to URI format */
2460 if (qla82xx_validate_firmware_blob(vha,
2461 QLA82XX_UNIFIED_ROMIMAGE)) {
7c3df132
SK		 2462 ql_log(ql_log_fatal, vha, 0x00a4,
2463 "No valid firmware image found.\n");
9c2b2975
HZ		 2464 return QLA_FUNCTION_FAILED;
2465 }
2466 }
2467
a9083016 2468 if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) {
7c3df132
SK		 2469 ql_log(ql_log_info, vha, 0x00a5,
2470 "Firmware loaded successfully from binary blob.\n");
a9083016
GM		 2471 return QLA_SUCCESS;
2472 } else {
7c3df132
SK		 2473 ql_log(ql_log_fatal, vha, 0x00a6,
2474 "Firmware load failed for binary blob.\n");
a9083016
GM		 2475 blob->fw = NULL;
2476 blob = NULL;
2477 goto fw_load_failed;
2478 }
2479 return QLA_SUCCESS;
2480
2481fw_load_failed:
2482 return QLA_FUNCTION_FAILED;
2483}
2484
a5b36321 2485int
a9083016
GM		 2486qla82xx_start_firmware(scsi_qla_host_t *vha)
2487{
a9083016
GM		 2488 uint16_t lnk;
2489 struct qla_hw_data *ha = vha->hw;
2490
2491 /* scrub dma mask expansion register */
77e334d2 2492 qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE);
a9083016 2493
3711333d
GM		 2494 /* Put both the PEG CMD and RCV PEG to default state
2495 * of 0 before resetting the hardware
2496 */
2497 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
2498 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0);
2499
a9083016
GM		 2500 /* Overwrite stale initialization register values */
2501 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
2502 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
2503
2504 if (qla82xx_load_fw(vha) != QLA_SUCCESS) {
7c3df132
SK		 2505 ql_log(ql_log_fatal, vha, 0x00a7,
2506 "Error trying to start fw.\n");
a9083016
GM		 2507 return QLA_FUNCTION_FAILED;
2508 }
2509
2510 /* Handshake with the card before we register the devices. */
2511 if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) {
7c3df132
SK		 2512 ql_log(ql_log_fatal, vha, 0x00aa,
2513 "Error during card handshake.\n");
a9083016
GM		 2514 return QLA_FUNCTION_FAILED;
2515 }
2516
2517 /* Negotiated Link width */
10092438 2518 pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk);
a9083016
GM		 2519 ha->link_width = (lnk >> 4) & 0x3f;
2520
2521 /* Synchronize with Receive peg */
2522 return qla82xx_check_rcvpeg_state(ha);
2523}
2524
77e334d2 2525static uint32_t *
a9083016
GM		 2526qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
2527 uint32_t length)
2528{
2529 uint32_t i;
2530 uint32_t val;
2531 struct qla_hw_data *ha = vha->hw;
2532
2533 /* Dword reads to flash. */
2534 for (i = 0; i < length/4; i++, faddr += 4) {
2535 if (qla82xx_rom_fast_read(ha, faddr, &val)) {
7c3df132
SK		 2536 ql_log(ql_log_warn, vha, 0x0106,
2537 "Do ROM fast read failed.\n");
a9083016
GM		 2538 goto done_read;
2539 }
2540 dwptr[i] = __constant_cpu_to_le32(val);
2541 }
2542done_read:
2543 return dwptr;
2544}
2545
77e334d2 2546static int
a9083016
GM		 2547qla82xx_unprotect_flash(struct qla_hw_data *ha)
2548{
2549 int ret;
2550 uint32_t val;
7c3df132 2551 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 2552
2553 ret = ql82xx_rom_lock_d(ha);
2554 if (ret < 0) {
7c3df132
SK		 2555 ql_log(ql_log_warn, vha, 0xb014,
2556 "ROM Lock failed.\n");
a9083016
GM		 2557 return ret;
2558 }
2559
2560 ret = qla82xx_read_status_reg(ha, &val);
2561 if (ret < 0)
2562 goto done_unprotect;
2563
0547fb37 2564 val &= ~(BLOCK_PROTECT_BITS << 2);
a9083016
GM		 2565 ret = qla82xx_write_status_reg(ha, val);
2566 if (ret < 0) {
0547fb37 2567 val |= (BLOCK_PROTECT_BITS << 2);
a9083016
GM		 2568 qla82xx_write_status_reg(ha, val);
2569 }
2570
2571 if (qla82xx_write_disable_flash(ha) != 0)
7c3df132
SK		 2572 ql_log(ql_log_warn, vha, 0xb015,
2573 "Write disable failed.\n");
a9083016
GM		 2574
2575done_unprotect:
d652e093 2576 qla82xx_rom_unlock(ha);
a9083016
GM		 2577 return ret;
2578}
2579
77e334d2 2580static int
a9083016
GM		 2581qla82xx_protect_flash(struct qla_hw_data *ha)
2582{
2583 int ret;
2584 uint32_t val;
7c3df132 2585 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 2586
2587 ret = ql82xx_rom_lock_d(ha);
2588 if (ret < 0) {
7c3df132
SK		 2589 ql_log(ql_log_warn, vha, 0xb016,
2590 "ROM Lock failed.\n");
a9083016
GM		 2591 return ret;
2592 }
2593
2594 ret = qla82xx_read_status_reg(ha, &val);
2595 if (ret < 0)
2596 goto done_protect;
2597
0547fb37 2598 val |= (BLOCK_PROTECT_BITS << 2);
a9083016
GM		 2599 /* LOCK all sectors */
2600 ret = qla82xx_write_status_reg(ha, val);
2601 if (ret < 0)
7c3df132
SK		 2602 ql_log(ql_log_warn, vha, 0xb017,
2603 "Write status register failed.\n");
a9083016
GM		 2604
2605 if (qla82xx_write_disable_flash(ha) != 0)
7c3df132
SK		 2606 ql_log(ql_log_warn, vha, 0xb018,
2607 "Write disable failed.\n");
a9083016 2608done_protect:
d652e093 2609 qla82xx_rom_unlock(ha);
a9083016
GM		 2610 return ret;
2611}
2612
77e334d2 2613static int
a9083016
GM		 2614qla82xx_erase_sector(struct qla_hw_data *ha, int addr)
2615{
2616 int ret = 0;
7c3df132 2617 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 2618
2619 ret = ql82xx_rom_lock_d(ha);
2620 if (ret < 0) {
7c3df132
SK		 2621 ql_log(ql_log_warn, vha, 0xb019,
2622 "ROM Lock failed.\n");
a9083016
GM		 2623 return ret;
2624 }
2625
2626 qla82xx_flash_set_write_enable(ha);
2627 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
2628 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
2629 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE);
2630
2631 if (qla82xx_wait_rom_done(ha)) {
7c3df132
SK		 2632 ql_log(ql_log_warn, vha, 0xb01a,
2633 "Error waiting for rom done.\n");
a9083016
GM		 2634 ret = -1;
2635 goto done;
2636 }
2637 ret = qla82xx_flash_wait_write_finish(ha);
2638done:
d652e093 2639 qla82xx_rom_unlock(ha);
a9083016
GM		 2640 return ret;
2641}
2642
2643/*
2644 * Address and length are byte address
2645 */
2646uint8_t *
2647qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2648 uint32_t offset, uint32_t length)
2649{
2650 scsi_block_requests(vha->host);
2651 qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length);
2652 scsi_unblock_requests(vha->host);
2653 return buf;
2654}
2655
2656static int
2657qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr,
2658 uint32_t faddr, uint32_t dwords)
2659{
2660 int ret;
2661 uint32_t liter;
2662 uint32_t sec_mask, rest_addr;
2663 dma_addr_t optrom_dma;
2664 void *optrom = NULL;
2665 int page_mode = 0;
2666 struct qla_hw_data *ha = vha->hw;
2667
2668 ret = -1;
2669
2670 /* Prepare burst-capable write on supported ISPs. */
2671 if (page_mode && !(faddr & 0xfff) &&
2672 dwords > OPTROM_BURST_DWORDS) {
2673 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2674 &optrom_dma, GFP_KERNEL);
2675 if (!optrom) {
7c3df132
SK		 2676 ql_log(ql_log_warn, vha, 0xb01b,
2677 "Unable to allocate memory "
00adc9a0 2678 "for optrom burst write (%x KB).\n",
7c3df132 2679 OPTROM_BURST_SIZE / 1024);
a9083016
GM		 2680 }
2681 }
2682
2683 rest_addr = ha->fdt_block_size - 1;
2684 sec_mask = ~rest_addr;
2685
2686 ret = qla82xx_unprotect_flash(ha);
2687 if (ret) {
7c3df132
SK		 2688 ql_log(ql_log_warn, vha, 0xb01c,
2689 "Unable to unprotect flash for update.\n");
a9083016
GM		 2690 goto write_done;
2691 }
2692
2693 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) {
2694 /* Are we at the beginning of a sector? */
2695 if ((faddr & rest_addr) == 0) {
2696
2697 ret = qla82xx_erase_sector(ha, faddr);
2698 if (ret) {
7c3df132
SK		 2699 ql_log(ql_log_warn, vha, 0xb01d,
2700 "Unable to erase sector: address=%x.\n",
2701 faddr);
a9083016
GM		 2702 break;
2703 }
2704 }
2705
2706 /* Go with burst-write. */
2707 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
2708 /* Copy data to DMA'ble buffer. */
2709 memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
2710
2711 ret = qla2x00_load_ram(vha, optrom_dma,
2712 (ha->flash_data_off | faddr),
2713 OPTROM_BURST_DWORDS);
2714 if (ret != QLA_SUCCESS) {
7c3df132 2715 ql_log(ql_log_warn, vha, 0xb01e,
a9083016
GM		 2716 "Unable to burst-write optrom segment "
2717 "(%x/%x/%llx).\n", ret,
2718 (ha->flash_data_off | faddr),
2719 (unsigned long long)optrom_dma);
7c3df132 2720 ql_log(ql_log_warn, vha, 0xb01f,
a9083016
GM		 2721 "Reverting to slow-write.\n");
2722
2723 dma_free_coherent(&ha->pdev->dev,
2724 OPTROM_BURST_SIZE, optrom, optrom_dma);
2725 optrom = NULL;
2726 } else {
2727 liter += OPTROM_BURST_DWORDS - 1;
2728 faddr += OPTROM_BURST_DWORDS - 1;
2729 dwptr += OPTROM_BURST_DWORDS - 1;
2730 continue;
2731 }
2732 }
2733
2734 ret = qla82xx_write_flash_dword(ha, faddr,
2735 cpu_to_le32(*dwptr));
2736 if (ret) {
7c3df132
SK		 2737 ql_dbg(ql_dbg_p3p, vha, 0xb020,
2738 "Unable to program flash address=%x data=%x.\n",
2739 faddr, *dwptr);
a9083016
GM		 2740 break;
2741 }
2742 }
2743
2744 ret = qla82xx_protect_flash(ha);
2745 if (ret)
7c3df132 2746 ql_log(ql_log_warn, vha, 0xb021,
a9083016
GM		 2747 "Unable to protect flash after update.\n");
2748write_done:
2749 if (optrom)
2750 dma_free_coherent(&ha->pdev->dev,
2751 OPTROM_BURST_SIZE, optrom, optrom_dma);
2752 return ret;
2753}
2754
2755int
2756qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2757 uint32_t offset, uint32_t length)
2758{
2759 int rval;
2760
2761 /* Suspend HBA. */
2762 scsi_block_requests(vha->host);
2763 rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset,
2764 length >> 2);
2765 scsi_unblock_requests(vha->host);
2766
2767 /* Convert return ISP82xx to generic */
2768 if (rval)
2769 rval = QLA_FUNCTION_FAILED;
2770 else
2771 rval = QLA_SUCCESS;
2772 return rval;
2773}
2774
2775void
5162cf0c 2776qla82xx_start_iocbs(scsi_qla_host_t *vha)
a9083016 2777{
5162cf0c 2778 struct qla_hw_data *ha = vha->hw;
a9083016
GM		 2779 struct req_que *req = ha->req_q_map[0];
2780 struct device_reg_82xx __iomem *reg;
2781 uint32_t dbval;
2782
2783 /* Adjust ring index. */
2784 req->ring_index++;
2785 if (req->ring_index == req->length) {
2786 req->ring_index = 0;
2787 req->ring_ptr = req->ring;
2788 } else
2789 req->ring_ptr++;
2790
2791 reg = &ha->iobase->isp82;
2792 dbval = 0x04 | (ha->portnum << 5);
2793
2794 dbval = dbval | (req->id << 8) | (req->ring_index << 16);
6907869d
GM		 2795 if (ql2xdbwr)
2796 qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval);
2797 else {
2798 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval);
a9083016 2799 wmb();
fa492630 2800 while (RD_REG_DWORD((void __iomem *)ha->nxdb_rd_ptr) != dbval) {
6907869d
GM		 2801 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr,
2802 dbval);
2803 wmb();
2804 }
a9083016
GM		 2805 }
2806}
2807
fa492630
SK		 2808static void
2809qla82xx_rom_lock_recovery(struct qla_hw_data *ha)
e6a4202a 2810{
7c3df132
SK		 2811 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2812
e6a4202a
SS		 2813 if (qla82xx_rom_lock(ha))
2814 /* Someone else is holding the lock. */
7c3df132
SK		 2815 ql_log(ql_log_info, vha, 0xb022,
2816 "Resetting rom_lock.\n");
e6a4202a
SS		 2817
2818 /*
2819 * Either we got the lock, or someone
2820 * else died while holding it.
2821 * In either case, unlock.
2822 */
d652e093 2823 qla82xx_rom_unlock(ha);
e6a4202a
SS		 2824}
2825
a9083016
GM		 2826/*
2827 * qla82xx_device_bootstrap
2828 * Initialize device, set DEV_READY, start fw
2829 *
2830 * Note:
2831 * IDC lock must be held upon entry
2832 *
2833 * Return:
2834 * Success : 0
2835 * Failed : 1
2836 */
2837static int
2838qla82xx_device_bootstrap(scsi_qla_host_t *vha)
2839{
e6a4202a
SS		 2840 int rval = QLA_SUCCESS;
2841 int i, timeout;
a9083016
GM		 2842 uint32_t old_count, count;
2843 struct qla_hw_data *ha = vha->hw;
e6a4202a 2844 int need_reset = 0, peg_stuck = 1;
a9083016 2845
e6a4202a 2846 need_reset = qla82xx_need_reset(ha);
a9083016
GM		 2847
2848 old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2849
2850 for (i = 0; i < 10; i++) {
2851 timeout = msleep_interruptible(200);
2852 if (timeout) {
2853 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 2854 QLA8XXX_DEV_FAILED);
a9083016
GM		 2855 return QLA_FUNCTION_FAILED;
2856 }
2857
2858 count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2859 if (count != old_count)
e6a4202a
SS		 2860 peg_stuck = 0;
2861 }
2862
2863 if (need_reset) {
2864 /* We are trying to perform a recovery here. */
2865 if (peg_stuck)
2866 qla82xx_rom_lock_recovery(ha);
2867 goto dev_initialize;
2868 } else {
2869 /* Start of day for this ha context. */
2870 if (peg_stuck) {
2871 /* Either we are the first or recovery in progress. */
2872 qla82xx_rom_lock_recovery(ha);
2873 goto dev_initialize;
2874 } else
2875 /* Firmware already running. */
a9083016
GM		 2876 goto dev_ready;
2877 }
2878
e6a4202a
SS		 2879 return rval;
2880
a9083016
GM		 2881dev_initialize:
2882 /* set to DEV_INITIALIZING */
7c3df132
SK		 2883 ql_log(ql_log_info, vha, 0x009e,
2884 "HW State: INITIALIZING.\n");
7d613ac6 2885 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
a9083016
GM		 2886
2887 qla82xx_idc_unlock(ha);
2888 rval = qla82xx_start_firmware(vha);
2889 qla82xx_idc_lock(ha);
2890
2891 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2892 ql_log(ql_log_fatal, vha, 0x00ad,
2893 "HW State: FAILED.\n");
a9083016 2894 qla82xx_clear_drv_active(ha);
7d613ac6 2895 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_FAILED);
a9083016
GM		 2896 return rval;
2897 }
2898
2899dev_ready:
7c3df132
SK		 2900 ql_log(ql_log_info, vha, 0x00ae,
2901 "HW State: READY.\n");
7d613ac6 2902 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_READY);
a9083016
GM		 2903
2904 return QLA_SUCCESS;
2905}
2906
579d12b5
SK		 2907/*
2908* qla82xx_need_qsnt_handler
2909* Code to start quiescence sequence
2910*
2911* Note:
2912* IDC lock must be held upon entry
2913*
2914* Return: void
2915*/
2916
2917static void
2918qla82xx_need_qsnt_handler(scsi_qla_host_t *vha)
2919{
2920 struct qla_hw_data *ha = vha->hw;
2921 uint32_t dev_state, drv_state, drv_active;
2922 unsigned long reset_timeout;
2923
2924 if (vha->flags.online) {
2925 /*Block any further I/O and wait for pending cmnds to complete*/
8fcd6b8b 2926 qla2x00_quiesce_io(vha);
579d12b5
SK		 2927 }
2928
2929 /* Set the quiescence ready bit */
2930 qla82xx_set_qsnt_ready(ha);
2931
2932 /*wait for 30 secs for other functions to ack */
2933 reset_timeout = jiffies + (30 * HZ);
2934
2935 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2936 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2937 /* Its 2 that is written when qsnt is acked, moving one bit */
2938 drv_active = drv_active << 0x01;
2939
2940 while (drv_state != drv_active) {
2941
2942 if (time_after_eq(jiffies, reset_timeout)) {
2943 /* quiescence timeout, other functions didn't ack
2944 * changing the state to DEV_READY
2945 */
7c3df132 2946 ql_log(ql_log_info, vha, 0xb023,
5f28d2d7
SK		 2947 "%s : QUIESCENT TIMEOUT DRV_ACTIVE:%d "
2948 "DRV_STATE:%d.\n", QLA2XXX_DRIVER_NAME,
7c3df132 2949 drv_active, drv_state);
579d12b5 2950 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 2951 QLA8XXX_DEV_READY);
7c3df132
SK		 2952 ql_log(ql_log_info, vha, 0xb025,
2953 "HW State: DEV_READY.\n");
579d12b5
SK		 2954 qla82xx_idc_unlock(ha);
2955 qla2x00_perform_loop_resync(vha);
2956 qla82xx_idc_lock(ha);
2957
2958 qla82xx_clear_qsnt_ready(vha);
2959 return;
2960 }
2961
2962 qla82xx_idc_unlock(ha);
2963 msleep(1000);
2964 qla82xx_idc_lock(ha);
2965
2966 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2967 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2968 drv_active = drv_active << 0x01;
2969 }
2970 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2971 /* everyone acked so set the state to DEV_QUIESCENCE */
7d613ac6 2972 if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
7c3df132
SK		 2973 ql_log(ql_log_info, vha, 0xb026,
2974 "HW State: DEV_QUIESCENT.\n");
7d613ac6 2975 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_QUIESCENT);
579d12b5
SK		 2976 }
2977}
2978
2979/*
2980* qla82xx_wait_for_state_change
2981* Wait for device state to change from given current state
2982*
2983* Note:
2984* IDC lock must not be held upon entry
2985*
2986* Return:
2987* Changed device state.
2988*/
2989uint32_t
2990qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state)
2991{
2992 struct qla_hw_data *ha = vha->hw;
2993 uint32_t dev_state;
2994
2995 do {
2996 msleep(1000);
2997 qla82xx_idc_lock(ha);
2998 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2999 qla82xx_idc_unlock(ha);
3000 } while (dev_state == curr_state);
3001
3002 return dev_state;
3003}
3004
7d613ac6
SV		 3005void
3006qla8xxx_dev_failed_handler(scsi_qla_host_t *vha)
a9083016
GM		 3007{
3008 struct qla_hw_data *ha = vha->hw;
3009
3010 /* Disable the board */
7c3df132
SK		 3011 ql_log(ql_log_fatal, vha, 0x00b8,
3012 "Disabling the board.\n");
a9083016 3013
1459c0e1
SK		 3014 if (IS_QLA82XX(ha)) {
3015 qla82xx_clear_drv_active(ha);
3016 qla82xx_idc_unlock(ha);
3017 }
b963752f 3018
a9083016
GM		 3019 /* Set DEV_FAILED flag to disable timer */
3020 vha->device_flags |= DFLG_DEV_FAILED;
3021 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3022 qla2x00_mark_all_devices_lost(vha, 0);
3023 vha->flags.online = 0;
3024 vha->flags.init_done = 0;
3025}
3026
3027/*
3028 * qla82xx_need_reset_handler
3029 * Code to start reset sequence
3030 *
3031 * Note:
3032 * IDC lock must be held upon entry
3033 *
3034 * Return:
3035 * Success : 0
3036 * Failed : 1
3037 */
3038static void
3039qla82xx_need_reset_handler(scsi_qla_host_t *vha)
3040{
e5fdae55
CD		 3041 uint32_t dev_state, drv_state, drv_active;
3042 uint32_t active_mask = 0;
a9083016
GM		 3043 unsigned long reset_timeout;
3044 struct qla_hw_data *ha = vha->hw;
3045 struct req_que *req = ha->req_q_map[0];
3046
3047 if (vha->flags.online) {
3048 qla82xx_idc_unlock(ha);
3049 qla2x00_abort_isp_cleanup(vha);
3050 ha->isp_ops->get_flash_version(vha, req->ring);
3051 ha->isp_ops->nvram_config(vha);
3052 qla82xx_idc_lock(ha);
3053 }
3054
08de2844 3055 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7d613ac6 3056 if (!ha->flags.nic_core_reset_owner) {
08de2844
GM		 3057 ql_dbg(ql_dbg_p3p, vha, 0xb028,
3058 "reset_acknowledged by 0x%x\n", ha->portnum);
3059 qla82xx_set_rst_ready(ha);
3060 } else {
3061 active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
3062 drv_active &= active_mask;
3063 ql_dbg(ql_dbg_p3p, vha, 0xb029,
3064 "active_mask: 0x%08x\n", active_mask);
3065 }
a9083016
GM		 3066
3067 /* wait for 10 seconds for reset ack from all functions */
7d613ac6 3068 reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
a9083016
GM		 3069
3070 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3071 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
08de2844 3072 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
a9083016 3073
08de2844
GM		 3074 ql_dbg(ql_dbg_p3p, vha, 0xb02a,
3075 "drv_state: 0x%08x, drv_active: 0x%08x, "
3076 "dev_state: 0x%08x, active_mask: 0x%08x\n",
3077 drv_state, drv_active, dev_state, active_mask);
3078
3079 while (drv_state != drv_active &&
7d613ac6 3080 dev_state != QLA8XXX_DEV_INITIALIZING) {
a9083016 3081 if (time_after_eq(jiffies, reset_timeout)) {
7c3df132
SK		 3082 ql_log(ql_log_warn, vha, 0x00b5,
3083 "Reset timeout.\n");
a9083016
GM		 3084 break;
3085 }
3086 qla82xx_idc_unlock(ha);
3087 msleep(1000);
3088 qla82xx_idc_lock(ha);
3089 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3090 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7d613ac6 3091 if (ha->flags.nic_core_reset_owner)
08de2844
GM		 3092 drv_active &= active_mask;
3093 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
a9083016
GM		 3094 }
3095
08de2844
GM		 3096 ql_dbg(ql_dbg_p3p, vha, 0xb02b,
3097 "drv_state: 0x%08x, drv_active: 0x%08x, "
3098 "dev_state: 0x%08x, active_mask: 0x%08x\n",
3099 drv_state, drv_active, dev_state, active_mask);
3100
7c3df132
SK		 3101 ql_log(ql_log_info, vha, 0x00b6,
3102 "Device state is 0x%x = %s.\n",
3103 dev_state,
08de2844 3104 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
f1af6208 3105
a9083016 3106 /* Force to DEV_COLD unless someone else is starting a reset */
7d613ac6
SV		 3107 if (dev_state != QLA8XXX_DEV_INITIALIZING &&
3108 dev_state != QLA8XXX_DEV_COLD) {
7c3df132
SK		 3109 ql_log(ql_log_info, vha, 0x00b7,
3110 "HW State: COLD/RE-INIT.\n");
7d613ac6 3111 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD);
f4e1648a 3112 qla82xx_set_rst_ready(ha);
08de2844
GM		 3113 if (ql2xmdenable) {
3114 if (qla82xx_md_collect(vha))
3115 ql_log(ql_log_warn, vha, 0xb02c,
b6d0d9d5 3116 "Minidump not collected.\n");
08de2844
GM		 3117 } else
3118 ql_log(ql_log_warn, vha, 0xb04f,
3119 "Minidump disabled.\n");
a9083016
GM		 3120 }
3121}
3122
3173167f 3123int
08de2844
GM		 3124qla82xx_check_md_needed(scsi_qla_host_t *vha)
3125{
3126 struct qla_hw_data *ha = vha->hw;
3127 uint16_t fw_major_version, fw_minor_version, fw_subminor_version;
3173167f
GM		 3128 int rval = QLA_SUCCESS;
3129
3130 fw_major_version = ha->fw_major_version;
3131 fw_minor_version = ha->fw_minor_version;
3132 fw_subminor_version = ha->fw_subminor_version;
3133
6246b8a1 3134 rval = qla2x00_get_fw_version(vha);
3173167f
GM		 3135 if (rval != QLA_SUCCESS)
3136 return rval;
3137
3138 if (ql2xmdenable) {
3139 if (!ha->fw_dumped) {
3140 if (fw_major_version != ha->fw_major_version ||
3141 fw_minor_version != ha->fw_minor_version ||
3142 fw_subminor_version != ha->fw_subminor_version) {
3173167f
GM		 3143 ql_log(ql_log_info, vha, 0xb02d,
3144 "Firmware version differs "
3145 "Previous version: %d:%d:%d - "
3146 "New version: %d:%d:%d\n",
9bc3bf27
GM		 3147 fw_major_version, fw_minor_version,
3148 fw_subminor_version,
3173167f
GM		 3149 ha->fw_major_version,
3150 ha->fw_minor_version,
9bc3bf27 3151 ha->fw_subminor_version);
3173167f
GM		 3152 /* Release MiniDump resources */
3153 qla82xx_md_free(vha);
3154 /* ALlocate MiniDump resources */
3155 qla82xx_md_prep(vha);
2e264269
GM		 3156 }
3157 } else
3158 ql_log(ql_log_info, vha, 0xb02e,
3159 "Firmware dump available to retrieve\n");
3173167f
GM		 3160 }
3161 return rval;
08de2844
GM		 3162}
3163
3164
fa492630 3165static int
a9083016
GM		 3166qla82xx_check_fw_alive(scsi_qla_host_t *vha)
3167{
7190575f
GM		 3168 uint32_t fw_heartbeat_counter;
3169 int status = 0;
a9083016 3170
7190575f
GM		 3171 fw_heartbeat_counter = qla82xx_rd_32(vha->hw,
3172 QLA82XX_PEG_ALIVE_COUNTER);
a5b36321 3173 /* all 0xff, assume AER/EEH in progress, ignore */
7c3df132
SK		 3174 if (fw_heartbeat_counter == 0xffffffff) {
3175 ql_dbg(ql_dbg_timer, vha, 0x6003,
3176 "FW heartbeat counter is 0xffffffff, "
3177 "returning status=%d.\n", status);
7190575f 3178 return status;
7c3df132 3179 }
a9083016
GM		 3180 if (vha->fw_heartbeat_counter == fw_heartbeat_counter) {
3181 vha->seconds_since_last_heartbeat++;
3182 /* FW not alive after 2 seconds */
3183 if (vha->seconds_since_last_heartbeat == 2) {
3184 vha->seconds_since_last_heartbeat = 0;
7190575f 3185 status = 1;
a9083016 3186 }
efa786cc
LC		 3187 } else
3188 vha->seconds_since_last_heartbeat = 0;
a9083016 3189 vha->fw_heartbeat_counter = fw_heartbeat_counter;
7c3df132
SK		 3190 if (status)
3191 ql_dbg(ql_dbg_timer, vha, 0x6004,
3192 "Returning status=%d.\n", status);
7190575f 3193 return status;
a9083016
GM		 3194}
3195
3196/*
3197 * qla82xx_device_state_handler
3198 * Main state handler
3199 *
3200 * Note:
3201 * IDC lock must be held upon entry
3202 *
3203 * Return:
3204 * Success : 0
3205 * Failed : 1
3206 */
3207int
3208qla82xx_device_state_handler(scsi_qla_host_t *vha)
3209{
3210 uint32_t dev_state;
92dbf273 3211 uint32_t old_dev_state;
a9083016
GM		 3212 int rval = QLA_SUCCESS;
3213 unsigned long dev_init_timeout;
3214 struct qla_hw_data *ha = vha->hw;
92dbf273 3215 int loopcount = 0;
a9083016
GM		 3216
3217 qla82xx_idc_lock(ha);
0251ce8c 3218 if (!vha->flags.init_done) {
a9083016 3219 qla82xx_set_drv_active(vha);
0251ce8c
SK		 3220 qla82xx_set_idc_version(vha);
3221 }
a9083016 3222
f1af6208 3223 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
92dbf273 3224 old_dev_state = dev_state;
7c3df132
SK		 3225 ql_log(ql_log_info, vha, 0x009b,
3226 "Device state is 0x%x = %s.\n",
3227 dev_state,
08de2844 3228 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
a9083016
GM		 3229
3230 /* wait for 30 seconds for device to go ready */
7d613ac6 3231 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
a9083016
GM		 3232
3233 while (1) {
3234
3235 if (time_after_eq(jiffies, dev_init_timeout)) {
7c3df132
SK		 3236 ql_log(ql_log_fatal, vha, 0x009c,
3237 "Device init failed.\n");
a9083016
GM		 3238 rval = QLA_FUNCTION_FAILED;
3239 break;
3240 }
3241 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
92dbf273
GM		 3242 if (old_dev_state != dev_state) {
3243 loopcount = 0;
3244 old_dev_state = dev_state;
3245 }
3246 if (loopcount < 5) {
7c3df132
SK		 3247 ql_log(ql_log_info, vha, 0x009d,
3248 "Device state is 0x%x = %s.\n",
3249 dev_state,
08de2844 3250 dev_state < MAX_STATES ? qdev_state(dev_state) :
7c3df132 3251 "Unknown");
92dbf273 3252 }
f1af6208 3253
a9083016 3254 switch (dev_state) {
7d613ac6
SV		 3255 case QLA8XXX_DEV_READY:
3256 ha->flags.nic_core_reset_owner = 0;
7916bb90 3257 goto rel_lock;
7d613ac6 3258 case QLA8XXX_DEV_COLD:
a9083016 3259 rval = qla82xx_device_bootstrap(vha);
08de2844 3260 break;
7d613ac6 3261 case QLA8XXX_DEV_INITIALIZING:
a9083016
GM		 3262 qla82xx_idc_unlock(ha);
3263 msleep(1000);
3264 qla82xx_idc_lock(ha);
3265 break;
7d613ac6 3266 case QLA8XXX_DEV_NEED_RESET:
c8582ad9
SK		 3267 if (!ql2xdontresethba)
3268 qla82xx_need_reset_handler(vha);
3269 else {
3270 qla82xx_idc_unlock(ha);
3271 msleep(1000);
3272 qla82xx_idc_lock(ha);
3273 }
0060ddf8 3274 dev_init_timeout = jiffies +
7d613ac6 3275 (ha->fcoe_dev_init_timeout * HZ);
a9083016 3276 break;
7d613ac6 3277 case QLA8XXX_DEV_NEED_QUIESCENT:
579d12b5
SK		 3278 qla82xx_need_qsnt_handler(vha);
3279 /* Reset timeout value after quiescence handler */
7d613ac6 3280 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\
579d12b5
SK		 3281 * HZ);
3282 break;
7d613ac6 3283 case QLA8XXX_DEV_QUIESCENT:
579d12b5
SK		 3284 /* Owner will exit and other will wait for the state
3285 * to get changed
3286 */
3287 if (ha->flags.quiesce_owner)
7916bb90 3288 goto rel_lock;
579d12b5 3289
a9083016
GM		 3290 qla82xx_idc_unlock(ha);
3291 msleep(1000);
3292 qla82xx_idc_lock(ha);
579d12b5
SK		 3293
3294 /* Reset timeout value after quiescence handler */
7d613ac6 3295 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\
579d12b5 3296 * HZ);
a9083016 3297 break;
7d613ac6
SV		 3298 case QLA8XXX_DEV_FAILED:
3299 qla8xxx_dev_failed_handler(vha);
a9083016
GM		 3300 rval = QLA_FUNCTION_FAILED;
3301 goto exit;
3302 default:
3303 qla82xx_idc_unlock(ha);
3304 msleep(1000);
3305 qla82xx_idc_lock(ha);
3306 }
92dbf273 3307 loopcount++;
a9083016 3308 }
7916bb90 3309rel_lock:
a9083016 3310 qla82xx_idc_unlock(ha);
7916bb90 3311exit:
a9083016
GM		 3312 return rval;
3313}
3314
5988aeb2
GM		 3315static int qla82xx_check_temp(scsi_qla_host_t *vha)
3316{
3317 uint32_t temp, temp_state, temp_val;
3318 struct qla_hw_data *ha = vha->hw;
3319
3320 temp = qla82xx_rd_32(ha, CRB_TEMP_STATE);
3321 temp_state = qla82xx_get_temp_state(temp);
3322 temp_val = qla82xx_get_temp_val(temp);
3323
3324 if (temp_state == QLA82XX_TEMP_PANIC) {
3325 ql_log(ql_log_warn, vha, 0x600e,
3326 "Device temperature %d degrees C exceeds "
3327 " maximum allowed. Hardware has been shut down.\n",
3328 temp_val);
3329 return 1;
3330 } else if (temp_state == QLA82XX_TEMP_WARN) {
3331 ql_log(ql_log_warn, vha, 0x600f,
3332 "Device temperature %d degrees C exceeds "
3333 "operating range. Immediate action needed.\n",
3334 temp_val);
3335 }
3336 return 0;
3337}
3338
c8f6544e
CD		 3339void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha)
3340{
3341 struct qla_hw_data *ha = vha->hw;
3342
3343 if (ha->flags.mbox_busy) {
3344 ha->flags.mbox_int = 1;
8937f2f1 3345 ha->flags.mbox_busy = 0;
c8f6544e
CD		 3346 ql_log(ql_log_warn, vha, 0x6010,
3347 "Doing premature completion of mbx command.\n");
3348 if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags))
3349 complete(&ha->mbx_intr_comp);
3350 }
3351}
3352
a9083016
GM		 3353void qla82xx_watchdog(scsi_qla_host_t *vha)
3354{
7190575f 3355 uint32_t dev_state, halt_status;
a9083016
GM		 3356 struct qla_hw_data *ha = vha->hw;
3357
a9083016 3358 /* don't poll if reset is going on */
7d613ac6 3359 if (!ha->flags.nic_core_reset_hdlr_active) {
7190575f 3360 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
5988aeb2
GM		 3361 if (qla82xx_check_temp(vha)) {
3362 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
3363 ha->flags.isp82xx_fw_hung = 1;
3364 qla82xx_clear_pending_mbx(vha);
7d613ac6 3365 } else if (dev_state == QLA8XXX_DEV_NEED_RESET &&
7190575f 3366 !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) {
7c3df132
SK		 3367 ql_log(ql_log_warn, vha, 0x6001,
3368 "Adapter reset needed.\n");
a9083016 3369 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
7d613ac6 3370 } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT &&
579d12b5 3371 !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) {
7c3df132
SK		 3372 ql_log(ql_log_warn, vha, 0x6002,
3373 "Quiescent needed.\n");
579d12b5 3374 set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
7d613ac6 3375 } else if (dev_state == QLA8XXX_DEV_FAILED &&
7916bb90
CD		 3376 !test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) &&
3377 vha->flags.online == 1) {
3378 ql_log(ql_log_warn, vha, 0xb055,
3379 "Adapter state is failed. Offlining.\n");
3380 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
3381 ha->flags.isp82xx_fw_hung = 1;
3382 qla82xx_clear_pending_mbx(vha);
a9083016 3383 } else {
7190575f 3384 if (qla82xx_check_fw_alive(vha)) {
63154916
GM		 3385 ql_dbg(ql_dbg_timer, vha, 0x6011,
3386 "disabling pause transmit on port 0 & 1.\n");
3387 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
3388 CRB_NIU_XG_PAUSE_CTL_P0|CRB_NIU_XG_PAUSE_CTL_P1);
7190575f
GM		 3389 halt_status = qla82xx_rd_32(ha,
3390 QLA82XX_PEG_HALT_STATUS1);
63154916 3391 ql_log(ql_log_info, vha, 0x6005,
7c3df132
SK		 3392 "dumping hw/fw registers:.\n "
3393 " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n "
3394 " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n "
3395 " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n "
3396 " PEG_NET_4_PC: 0x%x.\n", halt_status,
0e8edb03
GM		 3397 qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2),
3398 qla82xx_rd_32(ha,
3399 QLA82XX_CRB_PEG_NET_0 + 0x3c),
3400 qla82xx_rd_32(ha,
3401 QLA82XX_CRB_PEG_NET_1 + 0x3c),
3402 qla82xx_rd_32(ha,
3403 QLA82XX_CRB_PEG_NET_2 + 0x3c),
3404 qla82xx_rd_32(ha,
3405 QLA82XX_CRB_PEG_NET_3 + 0x3c),
3406 qla82xx_rd_32(ha,
3407 QLA82XX_CRB_PEG_NET_4 + 0x3c));
2cc97965 3408 if (((halt_status & 0x1fffff00) >> 8) == 0x67)
10a340e6
CD		 3409 ql_log(ql_log_warn, vha, 0xb052,
3410 "Firmware aborted with "
3411 "error code 0x00006700. Device is "
3412 "being reset.\n");
7190575f
GM		 3413 if (halt_status & HALT_STATUS_UNRECOVERABLE) {
3414 set_bit(ISP_UNRECOVERABLE,
3415 &vha->dpc_flags);
3416 } else {
7c3df132
SK		 3417 ql_log(ql_log_info, vha, 0x6006,
3418 "Detect abort needed.\n");
7190575f
GM		 3419 set_bit(ISP_ABORT_NEEDED,
3420 &vha->dpc_flags);
3421 }
7190575f 3422 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 3423 ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n");
3424 qla82xx_clear_pending_mbx(vha);
7190575f 3425 }
a9083016
GM		 3426 }
3427 }
3428}
3429
3430int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
3431{
3432 int rval;
3433 rval = qla82xx_device_state_handler(vha);
3434 return rval;
3435}
3436
08de2844
GM		 3437void
3438qla82xx_set_reset_owner(scsi_qla_host_t *vha)
3439{
3440 struct qla_hw_data *ha = vha->hw;
3441 uint32_t dev_state;
3442
3443 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
7d613ac6 3444 if (dev_state == QLA8XXX_DEV_READY) {
08de2844
GM		 3445 ql_log(ql_log_info, vha, 0xb02f,
3446 "HW State: NEED RESET\n");
3447 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6
SV		 3448 QLA8XXX_DEV_NEED_RESET);
3449 ha->flags.nic_core_reset_owner = 1;
08de2844
GM		 3450 ql_dbg(ql_dbg_p3p, vha, 0xb030,
3451 "reset_owner is 0x%x\n", ha->portnum);
3452 } else
3453 ql_log(ql_log_info, vha, 0xb031,
3454 "Device state is 0x%x = %s.\n",
3455 dev_state,
3456 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
3457}
3458
a9083016
GM		 3459/*
3460 * qla82xx_abort_isp
3461 * Resets ISP and aborts all outstanding commands.
3462 *
3463 * Input:
3464 * ha = adapter block pointer.
3465 *
3466 * Returns:
3467 * 0 = success
3468 */
3469int
3470qla82xx_abort_isp(scsi_qla_host_t *vha)
3471{
3472 int rval;
3473 struct qla_hw_data *ha = vha->hw;
a9083016
GM		 3474
3475 if (vha->device_flags & DFLG_DEV_FAILED) {
7c3df132
SK		 3476 ql_log(ql_log_warn, vha, 0x8024,
3477 "Device in failed state, exiting.\n");
a9083016
GM		 3478 return QLA_SUCCESS;
3479 }
7d613ac6 3480 ha->flags.nic_core_reset_hdlr_active = 1;
a9083016
GM		 3481
3482 qla82xx_idc_lock(ha);
08de2844 3483 qla82xx_set_reset_owner(vha);
a9083016
GM		 3484 qla82xx_idc_unlock(ha);
3485
3486 rval = qla82xx_device_state_handler(vha);
3487
3488 qla82xx_idc_lock(ha);
3489 qla82xx_clear_rst_ready(ha);
3490 qla82xx_idc_unlock(ha);
3491
cdbb0a4f 3492 if (rval == QLA_SUCCESS) {
7190575f 3493 ha->flags.isp82xx_fw_hung = 0;
7d613ac6 3494 ha->flags.nic_core_reset_hdlr_active = 0;
a9083016 3495 qla82xx_restart_isp(vha);
cdbb0a4f 3496 }
f1af6208
GM		 3497
3498 if (rval) {
3499 vha->flags.online = 1;
3500 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
3501 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 3502 ql_log(ql_log_warn, vha, 0x8027,
3503 "ISP error recover failed - board "
3504 "disabled.\n");
f1af6208
GM		 3505 /*
3506 * The next call disables the board
3507 * completely.
3508 */
3509 ha->isp_ops->reset_adapter(vha);
3510 vha->flags.online = 0;
3511 clear_bit(ISP_ABORT_RETRY,
3512 &vha->dpc_flags);
3513 rval = QLA_SUCCESS;
3514 } else { /* schedule another ISP abort */
3515 ha->isp_abort_cnt--;
7c3df132
SK		 3516 ql_log(ql_log_warn, vha, 0x8036,
3517 "ISP abort - retry remaining %d.\n",
3518 ha->isp_abort_cnt);
f1af6208
GM		 3519 rval = QLA_FUNCTION_FAILED;
3520 }
3521 } else {
3522 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 3523 ql_dbg(ql_dbg_taskm, vha, 0x8029,
3524 "ISP error recovery - retrying (%d) more times.\n",
3525 ha->isp_abort_cnt);
f1af6208
GM		 3526 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
3527 rval = QLA_FUNCTION_FAILED;
3528 }
3529 }
a9083016
GM		 3530 return rval;
3531}
3532
3533/*
3534 * qla82xx_fcoe_ctx_reset
3535 * Perform a quick reset and aborts all outstanding commands.
3536 * This will only perform an FCoE context reset and avoids a full blown
3537 * chip reset.
3538 *
3539 * Input:
3540 * ha = adapter block pointer.
3541 * is_reset_path = flag for identifying the reset path.
3542 *
3543 * Returns:
3544 * 0 = success
3545 */
3546int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha)
3547{
3548 int rval = QLA_FUNCTION_FAILED;
3549
3550 if (vha->flags.online) {
3551 /* Abort all outstanding commands, so as to be requeued later */
3552 qla2x00_abort_isp_cleanup(vha);
3553 }
3554
3555 /* Stop currently executing firmware.
3556 * This will destroy existing FCoE context at the F/W end.
3557 */
3558 qla2x00_try_to_stop_firmware(vha);
3559
3560 /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */
3561 rval = qla82xx_restart_isp(vha);
3562
3563 return rval;
3564}
3565
3566/*
3567 * qla2x00_wait_for_fcoe_ctx_reset
3568 * Wait till the FCoE context is reset.
3569 *
3570 * Note:
3571 * Does context switching here.
3572 * Release SPIN_LOCK (if any) before calling this routine.
3573 *
3574 * Return:
3575 * Success (fcoe_ctx reset is done) : 0
3576 * Failed (fcoe_ctx reset not completed within max loop timout ) : 1
3577 */
3578int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha)
3579{
3580 int status = QLA_FUNCTION_FAILED;
3581 unsigned long wait_reset;
3582
3583 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
3584 while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
3585 test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
3586 && time_before(jiffies, wait_reset)) {
3587
3588 set_current_state(TASK_UNINTERRUPTIBLE);
3589 schedule_timeout(HZ);
3590
3591 if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) &&
3592 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) {
3593 status = QLA_SUCCESS;
3594 break;
3595 }
3596 }
7c3df132 3597 ql_dbg(ql_dbg_p3p, vha, 0xb027,
d8424f68 3598 "%s: status=%d.\n", __func__, status);
a9083016
GM		 3599
3600 return status;
3601}
7190575f
GM		 3602
3603void
3604qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha)
3605{
3606 int i;
3607 unsigned long flags;
3608 struct qla_hw_data *ha = vha->hw;
3609
3610 /* Check if 82XX firmware is alive or not
3611 * We may have arrived here from NEED_RESET
3612 * detection only
3613 */
3614 if (!ha->flags.isp82xx_fw_hung) {
3615 for (i = 0; i < 2; i++) {
3616 msleep(1000);
3617 if (qla82xx_check_fw_alive(vha)) {
3618 ha->flags.isp82xx_fw_hung = 1;
c8f6544e 3619 qla82xx_clear_pending_mbx(vha);
7190575f
GM		 3620 break;
3621 }
3622 }
3623 }
7c3df132
SK		 3624 ql_dbg(ql_dbg_init, vha, 0x00b0,
3625 "Entered %s fw_hung=%d.\n",
3626 __func__, ha->flags.isp82xx_fw_hung);
7190575f
GM		 3627
3628 /* Abort all commands gracefully if fw NOT hung */
3629 if (!ha->flags.isp82xx_fw_hung) {
3630 int cnt, que;
3631 srb_t *sp;
3632 struct req_que *req;
3633
3634 spin_lock_irqsave(&ha->hardware_lock, flags);
3635 for (que = 0; que < ha->max_req_queues; que++) {
3636 req = ha->req_q_map[que];
3637 if (!req)
3638 continue;
8d93f550 3639 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
7190575f
GM		 3640 sp = req->outstanding_cmds[cnt];
3641 if (sp) {
9ba56b95 3642 if (!sp->u.scmd.ctx ||
7190575f
GM		 3643 (sp->flags & SRB_FCP_CMND_DMA_VALID)) {
3644 spin_unlock_irqrestore(
3645 &ha->hardware_lock, flags);
3646 if (ha->isp_ops->abort_command(sp)) {
7c3df132
SK		 3647 ql_log(ql_log_info, vha,
3648 0x00b1,
3649 "mbx abort failed.\n");
7190575f 3650 } else {
7c3df132
SK		 3651 ql_log(ql_log_info, vha,
3652 0x00b2,
3653 "mbx abort success.\n");
7190575f
GM		 3654 }
3655 spin_lock_irqsave(&ha->hardware_lock, flags);
3656 }
3657 }
3658 }
3659 }
3660 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3661
3662 /* Wait for pending cmds (physical and virtual) to complete */
3663 if (!qla2x00_eh_wait_for_pending_commands(vha, 0, 0,
3664 WAIT_HOST) == QLA_SUCCESS) {
7c3df132
SK		 3665 ql_dbg(ql_dbg_init, vha, 0x00b3,
3666 "Done wait for "
3667 "pending commands.\n");
7190575f
GM		 3668 }
3669 }
3670}
08de2844
GM		 3671
3672/* Minidump related functions */
08de2844
GM		 3673static int
3674qla82xx_minidump_process_control(scsi_qla_host_t *vha,
3675 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3676{
3677 struct qla_hw_data *ha = vha->hw;
3678 struct qla82xx_md_entry_crb *crb_entry;
3679 uint32_t read_value, opcode, poll_time;
3680 uint32_t addr, index, crb_addr;
3681 unsigned long wtime;
3682 struct qla82xx_md_template_hdr *tmplt_hdr;
3683 uint32_t rval = QLA_SUCCESS;
3684 int i;
3685
3686 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
3687 crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr;
3688 crb_addr = crb_entry->addr;
3689
3690 for (i = 0; i < crb_entry->op_count; i++) {
3691 opcode = crb_entry->crb_ctrl.opcode;
3692 if (opcode & QLA82XX_DBG_OPCODE_WR) {
3693 qla82xx_md_rw_32(ha, crb_addr,
3694 crb_entry->value_1, 1);
3695 opcode &= ~QLA82XX_DBG_OPCODE_WR;
3696 }
3697
3698 if (opcode & QLA82XX_DBG_OPCODE_RW) {
3699 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3700 qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3701 opcode &= ~QLA82XX_DBG_OPCODE_RW;
3702 }
3703
3704 if (opcode & QLA82XX_DBG_OPCODE_AND) {
3705 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3706 read_value &= crb_entry->value_2;
3707 opcode &= ~QLA82XX_DBG_OPCODE_AND;
3708 if (opcode & QLA82XX_DBG_OPCODE_OR) {
3709 read_value |= crb_entry->value_3;
3710 opcode &= ~QLA82XX_DBG_OPCODE_OR;
3711 }
3712 qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3713 }
3714
3715 if (opcode & QLA82XX_DBG_OPCODE_OR) {
3716 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3717 read_value |= crb_entry->value_3;
3718 qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3719 opcode &= ~QLA82XX_DBG_OPCODE_OR;
3720 }
3721
3722 if (opcode & QLA82XX_DBG_OPCODE_POLL) {
3723 poll_time = crb_entry->crb_strd.poll_timeout;
3724 wtime = jiffies + poll_time;
3725 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3726
3727 do {
3728 if ((read_value & crb_entry->value_2)
3729 == crb_entry->value_1)
3730 break;
3731 else if (time_after_eq(jiffies, wtime)) {
3732 /* capturing dump failed */
3733 rval = QLA_FUNCTION_FAILED;
3734 break;
3735 } else
3736 read_value = qla82xx_md_rw_32(ha,
3737 crb_addr, 0, 0);
3738 } while (1);
3739 opcode &= ~QLA82XX_DBG_OPCODE_POLL;
3740 }
3741
3742 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) {
3743 if (crb_entry->crb_strd.state_index_a) {
3744 index = crb_entry->crb_strd.state_index_a;
3745 addr = tmplt_hdr->saved_state_array[index];
3746 } else
3747 addr = crb_addr;
3748
3749 read_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3750 index = crb_entry->crb_ctrl.state_index_v;
3751 tmplt_hdr->saved_state_array[index] = read_value;
3752 opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE;
3753 }
3754
3755 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) {
3756 if (crb_entry->crb_strd.state_index_a) {
3757 index = crb_entry->crb_strd.state_index_a;
3758 addr = tmplt_hdr->saved_state_array[index];
3759 } else
3760 addr = crb_addr;
3761
3762 if (crb_entry->crb_ctrl.state_index_v) {
3763 index = crb_entry->crb_ctrl.state_index_v;
3764 read_value =
3765 tmplt_hdr->saved_state_array[index];
3766 } else
3767 read_value = crb_entry->value_1;
3768
3769 qla82xx_md_rw_32(ha, addr, read_value, 1);
3770 opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE;
3771 }
3772
3773 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) {
3774 index = crb_entry->crb_ctrl.state_index_v;
3775 read_value = tmplt_hdr->saved_state_array[index];
3776 read_value <<= crb_entry->crb_ctrl.shl;
3777 read_value >>= crb_entry->crb_ctrl.shr;
3778 if (crb_entry->value_2)
3779 read_value &= crb_entry->value_2;
3780 read_value |= crb_entry->value_3;
3781 read_value += crb_entry->value_1;
3782 tmplt_hdr->saved_state_array[index] = read_value;
3783 opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE;
3784 }
3785 crb_addr += crb_entry->crb_strd.addr_stride;
3786 }
3787 return rval;
3788}
3789
3790static void
3791qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha,
3792 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3793{
3794 struct qla_hw_data *ha = vha->hw;
3795 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
3796 struct qla82xx_md_entry_rdocm *ocm_hdr;
3797 uint32_t *data_ptr = *d_ptr;
3798
3799 ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr;
3800 r_addr = ocm_hdr->read_addr;
3801 r_stride = ocm_hdr->read_addr_stride;
3802 loop_cnt = ocm_hdr->op_count;
3803
3804 for (i = 0; i < loop_cnt; i++) {
fa492630
SK		 3805 r_value = RD_REG_DWORD((void __iomem *)
3806 (r_addr + ha->nx_pcibase));
08de2844
GM		 3807 *data_ptr++ = cpu_to_le32(r_value);
3808 r_addr += r_stride;
3809 }
3810 *d_ptr = data_ptr;
3811}
3812
3813static void
3814qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha,
3815 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3816{
3817 struct qla_hw_data *ha = vha->hw;
3818 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
3819 struct qla82xx_md_entry_mux *mux_hdr;
3820 uint32_t *data_ptr = *d_ptr;
3821
3822 mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr;
3823 r_addr = mux_hdr->read_addr;
3824 s_addr = mux_hdr->select_addr;
3825 s_stride = mux_hdr->select_value_stride;
3826 s_value = mux_hdr->select_value;
3827 loop_cnt = mux_hdr->op_count;
3828
3829 for (i = 0; i < loop_cnt; i++) {
3830 qla82xx_md_rw_32(ha, s_addr, s_value, 1);
3831 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3832 *data_ptr++ = cpu_to_le32(s_value);
3833 *data_ptr++ = cpu_to_le32(r_value);
3834 s_value += s_stride;
3835 }
3836 *d_ptr = data_ptr;
3837}
3838
3839static void
3840qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha,
3841 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3842{
3843 struct qla_hw_data *ha = vha->hw;
3844 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
3845 struct qla82xx_md_entry_crb *crb_hdr;
3846 uint32_t *data_ptr = *d_ptr;
3847
3848 crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr;
3849 r_addr = crb_hdr->addr;
3850 r_stride = crb_hdr->crb_strd.addr_stride;
3851 loop_cnt = crb_hdr->op_count;
3852
3853 for (i = 0; i < loop_cnt; i++) {
3854 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3855 *data_ptr++ = cpu_to_le32(r_addr);
3856 *data_ptr++ = cpu_to_le32(r_value);
3857 r_addr += r_stride;
3858 }
3859 *d_ptr = data_ptr;
3860}
3861
3862static int
3863qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha,
3864 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3865{
3866 struct qla_hw_data *ha = vha->hw;
3867 uint32_t addr, r_addr, c_addr, t_r_addr;
3868 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
3869 unsigned long p_wait, w_time, p_mask;
3870 uint32_t c_value_w, c_value_r;
3871 struct qla82xx_md_entry_cache *cache_hdr;
3872 int rval = QLA_FUNCTION_FAILED;
3873 uint32_t *data_ptr = *d_ptr;
3874
3875 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr;
3876 loop_count = cache_hdr->op_count;
3877 r_addr = cache_hdr->read_addr;
3878 c_addr = cache_hdr->control_addr;
3879 c_value_w = cache_hdr->cache_ctrl.write_value;
3880
3881 t_r_addr = cache_hdr->tag_reg_addr;
3882 t_value = cache_hdr->addr_ctrl.init_tag_value;
3883 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
3884 p_wait = cache_hdr->cache_ctrl.poll_wait;
3885 p_mask = cache_hdr->cache_ctrl.poll_mask;
3886
3887 for (i = 0; i < loop_count; i++) {
3888 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1);
3889 if (c_value_w)
3890 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1);
3891
3892 if (p_mask) {
3893 w_time = jiffies + p_wait;
3894 do {
3895 c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0);
3896 if ((c_value_r & p_mask) == 0)
3897 break;
3898 else if (time_after_eq(jiffies, w_time)) {
3899 /* capturing dump failed */
3900 ql_dbg(ql_dbg_p3p, vha, 0xb032,
3901 "c_value_r: 0x%x, poll_mask: 0x%lx, "
3902 "w_time: 0x%lx\n",
3903 c_value_r, p_mask, w_time);
3904 return rval;
3905 }
3906 } while (1);
3907 }
3908
3909 addr = r_addr;
3910 for (k = 0; k < r_cnt; k++) {
3911 r_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3912 *data_ptr++ = cpu_to_le32(r_value);
3913 addr += cache_hdr->read_ctrl.read_addr_stride;
3914 }
3915 t_value += cache_hdr->addr_ctrl.tag_value_stride;
3916 }
3917 *d_ptr = data_ptr;
3918 return QLA_SUCCESS;
3919}
3920
3921static void
3922qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha,
3923 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3924{
3925 struct qla_hw_data *ha = vha->hw;
3926 uint32_t addr, r_addr, c_addr, t_r_addr;
3927 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
3928 uint32_t c_value_w;
3929 struct qla82xx_md_entry_cache *cache_hdr;
3930 uint32_t *data_ptr = *d_ptr;
3931
3932 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr;
3933 loop_count = cache_hdr->op_count;
3934 r_addr = cache_hdr->read_addr;
3935 c_addr = cache_hdr->control_addr;
3936 c_value_w = cache_hdr->cache_ctrl.write_value;
3937
3938 t_r_addr = cache_hdr->tag_reg_addr;
3939 t_value = cache_hdr->addr_ctrl.init_tag_value;
3940 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
3941
3942 for (i = 0; i < loop_count; i++) {
3943 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1);
3944 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1);
3945 addr = r_addr;
3946 for (k = 0; k < r_cnt; k++) {
3947 r_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3948 *data_ptr++ = cpu_to_le32(r_value);
3949 addr += cache_hdr->read_ctrl.read_addr_stride;
3950 }
3951 t_value += cache_hdr->addr_ctrl.tag_value_stride;
3952 }
3953 *d_ptr = data_ptr;
3954}
3955
3956static void
3957qla82xx_minidump_process_queue(scsi_qla_host_t *vha,
3958 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3959{
3960 struct qla_hw_data *ha = vha->hw;
3961 uint32_t s_addr, r_addr;
3962 uint32_t r_stride, r_value, r_cnt, qid = 0;
3963 uint32_t i, k, loop_cnt;
3964 struct qla82xx_md_entry_queue *q_hdr;
3965 uint32_t *data_ptr = *d_ptr;
3966
3967 q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr;
3968 s_addr = q_hdr->select_addr;
3969 r_cnt = q_hdr->rd_strd.read_addr_cnt;
3970 r_stride = q_hdr->rd_strd.read_addr_stride;
3971 loop_cnt = q_hdr->op_count;
3972
3973 for (i = 0; i < loop_cnt; i++) {
3974 qla82xx_md_rw_32(ha, s_addr, qid, 1);
3975 r_addr = q_hdr->read_addr;
3976 for (k = 0; k < r_cnt; k++) {
3977 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3978 *data_ptr++ = cpu_to_le32(r_value);
3979 r_addr += r_stride;
3980 }
3981 qid += q_hdr->q_strd.queue_id_stride;
3982 }
3983 *d_ptr = data_ptr;
3984}
3985
3986static void
3987qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha,
3988 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3989{
3990 struct qla_hw_data *ha = vha->hw;
3991 uint32_t r_addr, r_value;
3992 uint32_t i, loop_cnt;
3993 struct qla82xx_md_entry_rdrom *rom_hdr;
3994 uint32_t *data_ptr = *d_ptr;
3995
3996 rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr;
3997 r_addr = rom_hdr->read_addr;
3998 loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t);
3999
4000 for (i = 0; i < loop_cnt; i++) {
4001 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW,
4002 (r_addr & 0xFFFF0000), 1);
4003 r_value = qla82xx_md_rw_32(ha,
4004 MD_DIRECT_ROM_READ_BASE +
4005 (r_addr & 0x0000FFFF), 0, 0);
4006 *data_ptr++ = cpu_to_le32(r_value);
4007 r_addr += sizeof(uint32_t);
4008 }
4009 *d_ptr = data_ptr;
4010}
4011
4012static int
4013qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha,
4014 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
4015{
4016 struct qla_hw_data *ha = vha->hw;
4017 uint32_t r_addr, r_value, r_data;
4018 uint32_t i, j, loop_cnt;
4019 struct qla82xx_md_entry_rdmem *m_hdr;
4020 unsigned long flags;
4021 int rval = QLA_FUNCTION_FAILED;
4022 uint32_t *data_ptr = *d_ptr;
4023
4024 m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr;
4025 r_addr = m_hdr->read_addr;
4026 loop_cnt = m_hdr->read_data_size/16;
4027
4028 if (r_addr & 0xf) {
4029 ql_log(ql_log_warn, vha, 0xb033,
d6a03581 4030 "Read addr 0x%x not 16 bytes aligned\n", r_addr);
08de2844
GM		 4031 return rval;
4032 }
4033
4034 if (m_hdr->read_data_size % 16) {
4035 ql_log(ql_log_warn, vha, 0xb034,
4036 "Read data[0x%x] not multiple of 16 bytes\n",
4037 m_hdr->read_data_size);
4038 return rval;
4039 }
4040
4041 ql_dbg(ql_dbg_p3p, vha, 0xb035,
4042 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
4043 __func__, r_addr, m_hdr->read_data_size, loop_cnt);
4044
4045 write_lock_irqsave(&ha->hw_lock, flags);
4046 for (i = 0; i < loop_cnt; i++) {
4047 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1);
4048 r_value = 0;
4049 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1);
4050 r_value = MIU_TA_CTL_ENABLE;
4051 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
4052 r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
4053 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
4054
4055 for (j = 0; j < MAX_CTL_CHECK; j++) {
4056 r_value = qla82xx_md_rw_32(ha,
4057 MD_MIU_TEST_AGT_CTRL, 0, 0);
4058 if ((r_value & MIU_TA_CTL_BUSY) == 0)
4059 break;
4060 }
4061
4062 if (j >= MAX_CTL_CHECK) {
4063 printk_ratelimited(KERN_ERR
4064 "failed to read through agent\n");
4065 write_unlock_irqrestore(&ha->hw_lock, flags);
4066 return rval;
4067 }
4068
4069 for (j = 0; j < 4; j++) {
4070 r_data = qla82xx_md_rw_32(ha,
4071 MD_MIU_TEST_AGT_RDDATA[j], 0, 0);
4072 *data_ptr++ = cpu_to_le32(r_data);
4073 }
4074 r_addr += 16;
4075 }
4076 write_unlock_irqrestore(&ha->hw_lock, flags);
4077 *d_ptr = data_ptr;
4078 return QLA_SUCCESS;
4079}
4080
4081static int
4082qla82xx_validate_template_chksum(scsi_qla_host_t *vha)
4083{
4084 struct qla_hw_data *ha = vha->hw;
4085 uint64_t chksum = 0;
4086 uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr;
4087 int count = ha->md_template_size/sizeof(uint32_t);
4088
4089 while (count-- > 0)
4090 chksum += *d_ptr++;
4091 while (chksum >> 32)
4092 chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32);
4093 return ~chksum;
4094}
4095
4096static void
4097qla82xx_mark_entry_skipped(scsi_qla_host_t *vha,
4098 qla82xx_md_entry_hdr_t *entry_hdr, int index)
4099{
4100 entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG;
4101 ql_dbg(ql_dbg_p3p, vha, 0xb036,
4102 "Skipping entry[%d]: "
4103 "ETYPE[0x%x]-ELEVEL[0x%x]\n",
4104 index, entry_hdr->entry_type,
4105 entry_hdr->d_ctrl.entry_capture_mask);
4106}
4107
4108int
4109qla82xx_md_collect(scsi_qla_host_t *vha)
4110{
4111 struct qla_hw_data *ha = vha->hw;
4112 int no_entry_hdr = 0;
4113 qla82xx_md_entry_hdr_t *entry_hdr;
4114 struct qla82xx_md_template_hdr *tmplt_hdr;
4115 uint32_t *data_ptr;
4116 uint32_t total_data_size = 0, f_capture_mask, data_collected = 0;
4117 int i = 0, rval = QLA_FUNCTION_FAILED;
4118
4119 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
4120 data_ptr = (uint32_t *)ha->md_dump;
4121
4122 if (ha->fw_dumped) {
a8faa263
GM		 4123 ql_log(ql_log_warn, vha, 0xb037,
4124 "Firmware has been previously dumped (%p) "
4125 "-- ignoring request.\n", ha->fw_dump);
08de2844
GM		 4126 goto md_failed;
4127 }
4128
4129 ha->fw_dumped = 0;
4130
4131 if (!ha->md_tmplt_hdr || !ha->md_dump) {
4132 ql_log(ql_log_warn, vha, 0xb038,
4133 "Memory not allocated for minidump capture\n");
4134 goto md_failed;
4135 }
4136
b6d0d9d5
GM		 4137 if (ha->flags.isp82xx_no_md_cap) {
4138 ql_log(ql_log_warn, vha, 0xb054,
4139 "Forced reset from application, "
4140 "ignore minidump capture\n");
4141 ha->flags.isp82xx_no_md_cap = 0;
4142 goto md_failed;
4143 }
4144
08de2844
GM		 4145 if (qla82xx_validate_template_chksum(vha)) {
4146 ql_log(ql_log_info, vha, 0xb039,
4147 "Template checksum validation error\n");
4148 goto md_failed;
4149 }
4150
4151 no_entry_hdr = tmplt_hdr->num_of_entries;
4152 ql_dbg(ql_dbg_p3p, vha, 0xb03a,
4153 "No of entry headers in Template: 0x%x\n", no_entry_hdr);
4154
4155 ql_dbg(ql_dbg_p3p, vha, 0xb03b,
4156 "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level);
4157
4158 f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF;
4159
4160 /* Validate whether required debug level is set */
4161 if ((f_capture_mask & 0x3) != 0x3) {
4162 ql_log(ql_log_warn, vha, 0xb03c,
4163 "Minimum required capture mask[0x%x] level not set\n",
4164 f_capture_mask);
4165 goto md_failed;
4166 }
4167 tmplt_hdr->driver_capture_mask = ql2xmdcapmask;
4168
4169 tmplt_hdr->driver_info[0] = vha->host_no;
4170 tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) |
4171 (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) |
4172 QLA_DRIVER_BETA_VER;
4173
4174 total_data_size = ha->md_dump_size;
4175
880fdedb 4176 ql_dbg(ql_dbg_p3p, vha, 0xb03d,
08de2844
GM		 4177 "Total minidump data_size 0x%x to be captured\n", total_data_size);
4178
4179 /* Check whether template obtained is valid */
4180 if (tmplt_hdr->entry_type != QLA82XX_TLHDR) {
4181 ql_log(ql_log_warn, vha, 0xb04e,
4182 "Bad template header entry type: 0x%x obtained\n",
4183 tmplt_hdr->entry_type);
4184 goto md_failed;
4185 }
4186
4187 entry_hdr = (qla82xx_md_entry_hdr_t *) \
4188 (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset);
4189
4190 /* Walk through the entry headers */
4191 for (i = 0; i < no_entry_hdr; i++) {
4192
4193 if (data_collected > total_data_size) {
4194 ql_log(ql_log_warn, vha, 0xb03e,
4195 "More MiniDump data collected: [0x%x]\n",
4196 data_collected);
4197 goto md_failed;
4198 }
4199
4200 if (!(entry_hdr->d_ctrl.entry_capture_mask &
4201 ql2xmdcapmask)) {
4202 entry_hdr->d_ctrl.driver_flags |=
4203 QLA82XX_DBG_SKIPPED_FLAG;
4204 ql_dbg(ql_dbg_p3p, vha, 0xb03f,
4205 "Skipping entry[%d]: "
4206 "ETYPE[0x%x]-ELEVEL[0x%x]\n",
4207 i, entry_hdr->entry_type,
4208 entry_hdr->d_ctrl.entry_capture_mask);
4209 goto skip_nxt_entry;
4210 }
4211
4212 ql_dbg(ql_dbg_p3p, vha, 0xb040,
4213 "[%s]: data ptr[%d]: %p, entry_hdr: %p\n"
4214 "entry_type: 0x%x, captrue_mask: 0x%x\n",
4215 __func__, i, data_ptr, entry_hdr,
4216 entry_hdr->entry_type,
4217 entry_hdr->d_ctrl.entry_capture_mask);
4218
4219 ql_dbg(ql_dbg_p3p, vha, 0xb041,
4220 "Data collected: [0x%x], Dump size left:[0x%x]\n",
4221 data_collected, (ha->md_dump_size - data_collected));
4222
4223 /* Decode the entry type and take
4224 * required action to capture debug data */
4225 switch (entry_hdr->entry_type) {
4226 case QLA82XX_RDEND:
4227 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4228 break;
4229 case QLA82XX_CNTRL:
4230 rval = qla82xx_minidump_process_control(vha,
4231 entry_hdr, &data_ptr);
4232 if (rval != QLA_SUCCESS) {
4233 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4234 goto md_failed;
4235 }
4236 break;
4237 case QLA82XX_RDCRB:
4238 qla82xx_minidump_process_rdcrb(vha,
4239 entry_hdr, &data_ptr);
4240 break;
4241 case QLA82XX_RDMEM:
4242 rval = qla82xx_minidump_process_rdmem(vha,
4243 entry_hdr, &data_ptr);
4244 if (rval != QLA_SUCCESS) {
4245 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4246 goto md_failed;
4247 }
4248 break;
4249 case QLA82XX_BOARD:
4250 case QLA82XX_RDROM:
4251 qla82xx_minidump_process_rdrom(vha,
4252 entry_hdr, &data_ptr);
4253 break;
4254 case QLA82XX_L2DTG:
4255 case QLA82XX_L2ITG:
4256 case QLA82XX_L2DAT:
4257 case QLA82XX_L2INS:
4258 rval = qla82xx_minidump_process_l2tag(vha,
4259 entry_hdr, &data_ptr);
4260 if (rval != QLA_SUCCESS) {
4261 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4262 goto md_failed;
4263 }
4264 break;
4265 case QLA82XX_L1DAT:
4266 case QLA82XX_L1INS:
4267 qla82xx_minidump_process_l1cache(vha,
4268 entry_hdr, &data_ptr);
4269 break;
4270 case QLA82XX_RDOCM:
4271 qla82xx_minidump_process_rdocm(vha,
4272 entry_hdr, &data_ptr);
4273 break;
4274 case QLA82XX_RDMUX:
4275 qla82xx_minidump_process_rdmux(vha,
4276 entry_hdr, &data_ptr);
4277 break;
4278 case QLA82XX_QUEUE:
4279 qla82xx_minidump_process_queue(vha,
4280 entry_hdr, &data_ptr);
4281 break;
4282 case QLA82XX_RDNOP:
4283 default:
4284 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4285 break;
4286 }
4287
4288 ql_dbg(ql_dbg_p3p, vha, 0xb042,
4289 "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr);
4290
4291 data_collected = (uint8_t *)data_ptr -
4292 (uint8_t *)ha->md_dump;
4293skip_nxt_entry:
4294 entry_hdr = (qla82xx_md_entry_hdr_t *) \
4295 (((uint8_t *)entry_hdr) + entry_hdr->entry_size);
4296 }
4297
4298 if (data_collected != total_data_size) {
880fdedb 4299 ql_dbg(ql_dbg_p3p, vha, 0xb043,
08de2844
GM		 4300 "MiniDump data mismatch: Data collected: [0x%x],"
4301 "total_data_size:[0x%x]\n",
4302 data_collected, total_data_size);
4303 goto md_failed;
4304 }
4305
4306 ql_log(ql_log_info, vha, 0xb044,
4307 "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n",
4308 vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump);
4309 ha->fw_dumped = 1;
4310 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
4311
4312md_failed:
4313 return rval;
4314}
4315
4316int
4317qla82xx_md_alloc(scsi_qla_host_t *vha)
4318{
4319 struct qla_hw_data *ha = vha->hw;
4320 int i, k;
4321 struct qla82xx_md_template_hdr *tmplt_hdr;
4322
4323 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
4324
4325 if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) {
4326 ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF;
4327 ql_log(ql_log_info, vha, 0xb045,
4328 "Forcing driver capture mask to firmware default capture mask: 0x%x.\n",
4329 ql2xmdcapmask);
4330 }
4331
4332 for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) {
4333 if (i & ql2xmdcapmask)
4334 ha->md_dump_size += tmplt_hdr->capture_size_array[k];
4335 }
4336
4337 if (ha->md_dump) {
4338 ql_log(ql_log_warn, vha, 0xb046,
4339 "Firmware dump previously allocated.\n");
4340 return 1;
4341 }
4342
4343 ha->md_dump = vmalloc(ha->md_dump_size);
4344 if (ha->md_dump == NULL) {
4345 ql_log(ql_log_warn, vha, 0xb047,
4346 "Unable to allocate memory for Minidump size "
4347 "(0x%x).\n", ha->md_dump_size);
4348 return 1;
4349 }
4350 return 0;
4351}
4352
4353void
4354qla82xx_md_free(scsi_qla_host_t *vha)
4355{
4356 struct qla_hw_data *ha = vha->hw;
4357
4358 /* Release the template header allocated */
4359 if (ha->md_tmplt_hdr) {
4360 ql_log(ql_log_info, vha, 0xb048,
4361 "Free MiniDump template: %p, size (%d KB)\n",
4362 ha->md_tmplt_hdr, ha->md_template_size / 1024);
4363 dma_free_coherent(&ha->pdev->dev, ha->md_template_size,
4364 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma);
fa492630 4365 ha->md_tmplt_hdr = NULL;
08de2844
GM		 4366 }
4367
4368 /* Release the template data buffer allocated */
4369 if (ha->md_dump) {
4370 ql_log(ql_log_info, vha, 0xb049,
4371 "Free MiniDump memory: %p, size (%d KB)\n",
4372 ha->md_dump, ha->md_dump_size / 1024);
4373 vfree(ha->md_dump);
4374 ha->md_dump_size = 0;
fa492630 4375 ha->md_dump = NULL;
08de2844
GM		 4376 }
4377}
4378
4379void
4380qla82xx_md_prep(scsi_qla_host_t *vha)
4381{
4382 struct qla_hw_data *ha = vha->hw;
4383 int rval;
4384
4385 /* Get Minidump template size */
4386 rval = qla82xx_md_get_template_size(vha);
4387 if (rval == QLA_SUCCESS) {
4388 ql_log(ql_log_info, vha, 0xb04a,
4389 "MiniDump Template size obtained (%d KB)\n",
4390 ha->md_template_size / 1024);
4391
4392 /* Get Minidump template */
4393 rval = qla82xx_md_get_template(vha);
4394 if (rval == QLA_SUCCESS) {
4395 ql_dbg(ql_dbg_p3p, vha, 0xb04b,
4396 "MiniDump Template obtained\n");
4397
4398 /* Allocate memory for minidump */
4399 rval = qla82xx_md_alloc(vha);
4400 if (rval == QLA_SUCCESS)
4401 ql_log(ql_log_info, vha, 0xb04c,
4402 "MiniDump memory allocated (%d KB)\n",
4403 ha->md_dump_size / 1024);
4404 else {
4405 ql_log(ql_log_info, vha, 0xb04d,
4406 "Free MiniDump template: %p, size: (%d KB)\n",
4407 ha->md_tmplt_hdr,
4408 ha->md_template_size / 1024);
4409 dma_free_coherent(&ha->pdev->dev,
4410 ha->md_template_size,
4411 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma);
fa492630 4412 ha->md_tmplt_hdr = NULL;
08de2844
GM		 4413 }
4414
4415 }
4416 }
4417}
999916dc
SK		 4418
4419int
4420qla82xx_beacon_on(struct scsi_qla_host *vha)
4421{
4422
4423 int rval;
4424 struct qla_hw_data *ha = vha->hw;
4425 qla82xx_idc_lock(ha);
4426 rval = qla82xx_mbx_beacon_ctl(vha, 1);
4427
4428 if (rval) {
4429 ql_log(ql_log_warn, vha, 0xb050,
4430 "mbx set led config failed in %s\n", __func__);
4431 goto exit;
4432 }
4433 ha->beacon_blink_led = 1;
4434exit:
4435 qla82xx_idc_unlock(ha);
4436 return rval;
4437}
4438
4439int
4440qla82xx_beacon_off(struct scsi_qla_host *vha)
4441{
4442
4443 int rval;
4444 struct qla_hw_data *ha = vha->hw;
4445 qla82xx_idc_lock(ha);
4446 rval = qla82xx_mbx_beacon_ctl(vha, 0);
4447
4448 if (rval) {
4449 ql_log(ql_log_warn, vha, 0xb051,
4450 "mbx set led config failed in %s\n", __func__);
4451 goto exit;
4452 }
4453 ha->beacon_blink_led = 0;
4454exit:
4455 qla82xx_idc_unlock(ha);
4456 return rval;
4457}
Linux kernel - Deliverables
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