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qla2xxx: Update entry type 270 to match spec update.
[deliverable/linux.git] / drivers / scsi / qla2xxx / qla_nx.c
CommitLineData
a9083016
GM		 1/*
2 * QLogic Fibre Channel HBA Driver
1e63395c 3 * Copyright (c) 2003-2013 QLogic Corporation
a9083016
GM		 4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7#include "qla_def.h"
8#include <linux/delay.h>
9#include <linux/pci.h>
08de2844
GM		 10#include <linux/ratelimit.h>
11#include <linux/vmalloc.h>
ff2fc42e 12#include <scsi/scsi_tcq.h>
a9083016
GM		 13
14#define MASK(n) ((1ULL<<(n))-1)
15#define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \
16 ((addr >> 25) & 0x3ff))
17#define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \
18 ((addr >> 25) & 0x3ff))
19#define MS_WIN(addr) (addr & 0x0ffc0000)
20#define QLA82XX_PCI_MN_2M (0)
21#define QLA82XX_PCI_MS_2M (0x80000)
22#define QLA82XX_PCI_OCM0_2M (0xc0000)
23#define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
24#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
0547fb37 25#define BLOCK_PROTECT_BITS 0x0F
a9083016
GM		 26
27/* CRB window related */
28#define CRB_BLK(off) ((off >> 20) & 0x3f)
29#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
30#define CRB_WINDOW_2M (0x130060)
31#define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL)
32#define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
33 ((off) & 0xf0000))
34#define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL)
35#define CRB_INDIRECT_2M (0x1e0000UL)
36
a9083016
GM		 37#define MAX_CRB_XFORM 60
38static unsigned long crb_addr_xform[MAX_CRB_XFORM];
fa492630 39static int qla82xx_crb_table_initialized;
a9083016
GM		 40
41#define qla82xx_crb_addr_transform(name) \
42 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
43 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
44
45static void qla82xx_crb_addr_transform_setup(void)
46{
47 qla82xx_crb_addr_transform(XDMA);
48 qla82xx_crb_addr_transform(TIMR);
49 qla82xx_crb_addr_transform(SRE);
50 qla82xx_crb_addr_transform(SQN3);
51 qla82xx_crb_addr_transform(SQN2);
52 qla82xx_crb_addr_transform(SQN1);
53 qla82xx_crb_addr_transform(SQN0);
54 qla82xx_crb_addr_transform(SQS3);
55 qla82xx_crb_addr_transform(SQS2);
56 qla82xx_crb_addr_transform(SQS1);
57 qla82xx_crb_addr_transform(SQS0);
58 qla82xx_crb_addr_transform(RPMX7);
59 qla82xx_crb_addr_transform(RPMX6);
60 qla82xx_crb_addr_transform(RPMX5);
61 qla82xx_crb_addr_transform(RPMX4);
62 qla82xx_crb_addr_transform(RPMX3);
63 qla82xx_crb_addr_transform(RPMX2);
64 qla82xx_crb_addr_transform(RPMX1);
65 qla82xx_crb_addr_transform(RPMX0);
66 qla82xx_crb_addr_transform(ROMUSB);
67 qla82xx_crb_addr_transform(SN);
68 qla82xx_crb_addr_transform(QMN);
69 qla82xx_crb_addr_transform(QMS);
70 qla82xx_crb_addr_transform(PGNI);
71 qla82xx_crb_addr_transform(PGND);
72 qla82xx_crb_addr_transform(PGN3);
73 qla82xx_crb_addr_transform(PGN2);
74 qla82xx_crb_addr_transform(PGN1);
75 qla82xx_crb_addr_transform(PGN0);
76 qla82xx_crb_addr_transform(PGSI);
77 qla82xx_crb_addr_transform(PGSD);
78 qla82xx_crb_addr_transform(PGS3);
79 qla82xx_crb_addr_transform(PGS2);
80 qla82xx_crb_addr_transform(PGS1);
81 qla82xx_crb_addr_transform(PGS0);
82 qla82xx_crb_addr_transform(PS);
83 qla82xx_crb_addr_transform(PH);
84 qla82xx_crb_addr_transform(NIU);
85 qla82xx_crb_addr_transform(I2Q);
86 qla82xx_crb_addr_transform(EG);
87 qla82xx_crb_addr_transform(MN);
88 qla82xx_crb_addr_transform(MS);
89 qla82xx_crb_addr_transform(CAS2);
90 qla82xx_crb_addr_transform(CAS1);
91 qla82xx_crb_addr_transform(CAS0);
92 qla82xx_crb_addr_transform(CAM);
93 qla82xx_crb_addr_transform(C2C1);
94 qla82xx_crb_addr_transform(C2C0);
95 qla82xx_crb_addr_transform(SMB);
96 qla82xx_crb_addr_transform(OCM0);
97 /*
98 * Used only in P3 just define it for P2 also.
99 */
100 qla82xx_crb_addr_transform(I2C0);
101
102 qla82xx_crb_table_initialized = 1;
103}
104
fa492630 105static struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
a9083016
GM		 106 {{{0, 0, 0, 0} } },
107 {{{1, 0x0100000, 0x0102000, 0x120000},
108 {1, 0x0110000, 0x0120000, 0x130000},
109 {1, 0x0120000, 0x0122000, 0x124000},
110 {1, 0x0130000, 0x0132000, 0x126000},
111 {1, 0x0140000, 0x0142000, 0x128000},
112 {1, 0x0150000, 0x0152000, 0x12a000},
113 {1, 0x0160000, 0x0170000, 0x110000},
114 {1, 0x0170000, 0x0172000, 0x12e000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {1, 0x01e0000, 0x01e0800, 0x122000},
122 {0, 0x0000000, 0x0000000, 0x000000} } } ,
123 {{{1, 0x0200000, 0x0210000, 0x180000} } },
124 {{{0, 0, 0, 0} } },
125 {{{1, 0x0400000, 0x0401000, 0x169000} } },
126 {{{1, 0x0500000, 0x0510000, 0x140000} } },
127 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },
128 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },
129 {{{1, 0x0800000, 0x0802000, 0x170000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {1, 0x08f0000, 0x08f2000, 0x172000} } },
145 {{{1, 0x0900000, 0x0902000, 0x174000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {1, 0x09f0000, 0x09f2000, 0x176000} } },
161 {{{0, 0x0a00000, 0x0a02000, 0x178000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
177 {{{0, 0x0b00000, 0x0b02000, 0x17c000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000},
180 {0, 0x0000000, 0x0000000, 0x000000},
181 {0, 0x0000000, 0x0000000, 0x000000},
182 {0, 0x0000000, 0x0000000, 0x000000},
183 {0, 0x0000000, 0x0000000, 0x000000},
184 {0, 0x0000000, 0x0000000, 0x000000},
185 {0, 0x0000000, 0x0000000, 0x000000},
186 {0, 0x0000000, 0x0000000, 0x000000},
187 {0, 0x0000000, 0x0000000, 0x000000},
188 {0, 0x0000000, 0x0000000, 0x000000},
189 {0, 0x0000000, 0x0000000, 0x000000},
190 {0, 0x0000000, 0x0000000, 0x000000},
191 {0, 0x0000000, 0x0000000, 0x000000},
192 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
193 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },
194 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },
195 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },
196 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },
197 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },
198 {{{1, 0x1100000, 0x1101000, 0x160000} } },
199 {{{1, 0x1200000, 0x1201000, 0x161000} } },
200 {{{1, 0x1300000, 0x1301000, 0x162000} } },
201 {{{1, 0x1400000, 0x1401000, 0x163000} } },
202 {{{1, 0x1500000, 0x1501000, 0x165000} } },
203 {{{1, 0x1600000, 0x1601000, 0x166000} } },
204 {{{0, 0, 0, 0} } },
205 {{{0, 0, 0, 0} } },
206 {{{0, 0, 0, 0} } },
207 {{{0, 0, 0, 0} } },
208 {{{0, 0, 0, 0} } },
209 {{{0, 0, 0, 0} } },
210 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },
211 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },
212 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },
213 {{{0} } },
214 {{{1, 0x2100000, 0x2102000, 0x120000},
215 {1, 0x2110000, 0x2120000, 0x130000},
216 {1, 0x2120000, 0x2122000, 0x124000},
217 {1, 0x2130000, 0x2132000, 0x126000},
218 {1, 0x2140000, 0x2142000, 0x128000},
219 {1, 0x2150000, 0x2152000, 0x12a000},
220 {1, 0x2160000, 0x2170000, 0x110000},
221 {1, 0x2170000, 0x2172000, 0x12e000},
222 {0, 0x0000000, 0x0000000, 0x000000},
223 {0, 0x0000000, 0x0000000, 0x000000},
224 {0, 0x0000000, 0x0000000, 0x000000},
225 {0, 0x0000000, 0x0000000, 0x000000},
226 {0, 0x0000000, 0x0000000, 0x000000},
227 {0, 0x0000000, 0x0000000, 0x000000},
228 {0, 0x0000000, 0x0000000, 0x000000},
229 {0, 0x0000000, 0x0000000, 0x000000} } },
230 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },
231 {{{0} } },
232 {{{0} } },
233 {{{0} } },
234 {{{0} } },
235 {{{0} } },
236 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },
237 {{{1, 0x2900000, 0x2901000, 0x16b000} } },
238 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },
239 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },
240 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },
241 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },
242 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },
243 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },
244 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },
245 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },
246 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },
247 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },
248 {{{0} } },
249 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },
250 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },
251 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },
252 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },
253 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },
254 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },
255 {{{0} } },
256 {{{0} } },
257 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },
258 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },
259 {{{1, 0x3f00000, 0x3f01000, 0x168000} } }
260};
261
262/*
263 * top 12 bits of crb internal address (hub, agent)
264 */
fa492630 265static unsigned qla82xx_crb_hub_agt[64] = {
a9083016
GM		 266 0,
267 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
268 QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
269 QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
270 0,
271 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
272 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
273 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
274 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
275 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
276 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
277 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
278 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
279 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
280 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
281 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
282 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
283 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
284 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
285 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
286 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
287 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
288 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
293 0,
294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
295 QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
296 0,
297 QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
298 0,
299 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
300 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
301 0,
302 0,
303 0,
304 0,
305 0,
306 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
307 0,
308 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
309 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
310 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
311 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
312 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
313 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
314 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
315 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
316 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
317 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
318 0,
319 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
320 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
321 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
322 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
323 0,
324 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
325 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
326 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
327 0,
328 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
329 0,
330};
331
f1af6208 332/* Device states */
fa492630 333static char *q_dev_state[] = {
f1af6208
GM		 334 "Unknown",
335 "Cold",
336 "Initializing",
337 "Ready",
338 "Need Reset",
339 "Need Quiescent",
340 "Failed",
341 "Quiescent",
342};
343
08de2844
GM		 344char *qdev_state(uint32_t dev_state)
345{
346 return q_dev_state[dev_state];
347}
348
a9083016
GM		 349/*
350 * In: 'off' is offset from CRB space in 128M pci map
351 * Out: 'off' is 2M pci map addr
352 * side effect: lock crb window
353 */
354static void
355qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong *off)
356{
357 u32 win_read;
7c3df132 358 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 359
360 ha->crb_win = CRB_HI(*off);
361 writel(ha->crb_win,
fa492630 362 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
a9083016
GM		 363
364 /* Read back value to make sure write has gone through before trying
365 * to use it.
366 */
fa492630
SK		 367 win_read = RD_REG_DWORD((void __iomem *)
368 (CRB_WINDOW_2M + ha->nx_pcibase));
a9083016 369 if (win_read != ha->crb_win) {
7c3df132
SK		 370 ql_dbg(ql_dbg_p3p, vha, 0xb000,
371 "%s: Written crbwin (0x%x) "
372 "!= Read crbwin (0x%x), off=0x%lx.\n",
d8424f68 373 __func__, ha->crb_win, win_read, *off);
a9083016
GM		 374 }
375 *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
376}
377
378static inline unsigned long
379qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off)
380{
7c3df132 381 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 382 /* See if we are currently pointing to the region we want to use next */
383 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) {
384 /* No need to change window. PCIX and PCIEregs are in both
385 * regs are in both windows.
386 */
387 return off;
388 }
389
390 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) {
391 /* We are in first CRB window */
392 if (ha->curr_window != 0)
393 WARN_ON(1);
394 return off;
395 }
396
397 if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) {
398 /* We are in second CRB window */
399 off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST;
400
401 if (ha->curr_window != 1)
402 return off;
403
404 /* We are in the QM or direct access
405 * register region - do nothing
406 */
407 if ((off >= QLA82XX_PCI_DIRECT_CRB) &&
408 (off < QLA82XX_PCI_CAMQM_MAX))
409 return off;
410 }
411 /* strange address given */
7c3df132 412 ql_dbg(ql_dbg_p3p, vha, 0xb001,
d8424f68 413 "%s: Warning: unm_nic_pci_set_crbwindow "
7c3df132
SK		 414 "called with an unknown address(%llx).\n",
415 QLA2XXX_DRIVER_NAME, off);
a9083016
GM		 416 return off;
417}
418
77e334d2
GM		 419static int
420qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong *off)
421{
422 struct crb_128M_2M_sub_block_map *m;
423
424 if (*off >= QLA82XX_CRB_MAX)
425 return -1;
426
427 if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) {
428 *off = (*off - QLA82XX_PCI_CAMQM) +
429 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
430 return 0;
431 }
432
433 if (*off < QLA82XX_PCI_CRBSPACE)
434 return -1;
435
436 *off -= QLA82XX_PCI_CRBSPACE;
437
438 /* Try direct map */
439 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
440
441 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
442 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase;
443 return 0;
444 }
445 /* Not in direct map, use crb window */
446 return 1;
447}
448
449#define CRB_WIN_LOCK_TIMEOUT 100000000
450static int qla82xx_crb_win_lock(struct qla_hw_data *ha)
451{
452 int done = 0, timeout = 0;
453
454 while (!done) {
455 /* acquire semaphore3 from PCI HW block */
456 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
457 if (done == 1)
458 break;
459 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
460 return -1;
461 timeout++;
462 }
463 qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum);
464 return 0;
465}
466
a9083016
GM		 467int
468qla82xx_wr_32(struct qla_hw_data *ha, ulong off, u32 data)
469{
470 unsigned long flags = 0;
471 int rv;
472
473 rv = qla82xx_pci_get_crb_addr_2M(ha, &off);
474
475 BUG_ON(rv == -1);
476
477 if (rv == 1) {
478 write_lock_irqsave(&ha->hw_lock, flags);
479 qla82xx_crb_win_lock(ha);
480 qla82xx_pci_set_crbwindow_2M(ha, &off);
481 }
482
483 writel(data, (void __iomem *)off);
484
485 if (rv == 1) {
486 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
487 write_unlock_irqrestore(&ha->hw_lock, flags);
488 }
489 return 0;
490}
491
492int
493qla82xx_rd_32(struct qla_hw_data *ha, ulong off)
494{
495 unsigned long flags = 0;
496 int rv;
497 u32 data;
498
499 rv = qla82xx_pci_get_crb_addr_2M(ha, &off);
500
501 BUG_ON(rv == -1);
502
503 if (rv == 1) {
504 write_lock_irqsave(&ha->hw_lock, flags);
505 qla82xx_crb_win_lock(ha);
506 qla82xx_pci_set_crbwindow_2M(ha, &off);
507 }
508 data = RD_REG_DWORD((void __iomem *)off);
509
510 if (rv == 1) {
511 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
512 write_unlock_irqrestore(&ha->hw_lock, flags);
513 }
514 return data;
515}
516
a9083016
GM		 517#define IDC_LOCK_TIMEOUT 100000000
518int qla82xx_idc_lock(struct qla_hw_data *ha)
519{
520 int i;
521 int done = 0, timeout = 0;
522
523 while (!done) {
524 /* acquire semaphore5 from PCI HW block */
525 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
526 if (done == 1)
527 break;
528 if (timeout >= IDC_LOCK_TIMEOUT)
529 return -1;
530
531 timeout++;
532
533 /* Yield CPU */
534 if (!in_interrupt())
535 schedule();
536 else {
537 for (i = 0; i < 20; i++)
538 cpu_relax();
539 }
540 }
541
542 return 0;
543}
544
545void qla82xx_idc_unlock(struct qla_hw_data *ha)
546{
547 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
548}
549
a9083016
GM		 550/* PCI Windowing for DDR regions. */
551#define QLA82XX_ADDR_IN_RANGE(addr, low, high) \
552 (((addr) <= (high)) && ((addr) >= (low)))
553/*
554 * check memory access boundary.
555 * used by test agent. support ddr access only for now
556 */
557static unsigned long
558qla82xx_pci_mem_bound_check(struct qla_hw_data *ha,
559 unsigned long long addr, int size)
560{
561 if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
562 QLA82XX_ADDR_DDR_NET_MAX) ||
563 !QLA82XX_ADDR_IN_RANGE(addr + size - 1, QLA82XX_ADDR_DDR_NET,
564 QLA82XX_ADDR_DDR_NET_MAX) ||
565 ((size != 1) && (size != 2) && (size != 4) && (size != 8)))
566 return 0;
567 else
568 return 1;
569}
570
fa492630 571static int qla82xx_pci_set_window_warning_count;
a9083016 572
77e334d2 573static unsigned long
a9083016
GM		 574qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr)
575{
576 int window;
577 u32 win_read;
7c3df132 578 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 579
580 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
581 QLA82XX_ADDR_DDR_NET_MAX)) {
582 /* DDR network side */
583 window = MN_WIN(addr);
584 ha->ddr_mn_window = window;
585 qla82xx_wr_32(ha,
586 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
587 win_read = qla82xx_rd_32(ha,
588 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
589 if ((win_read << 17) != window) {
7c3df132
SK		 590 ql_dbg(ql_dbg_p3p, vha, 0xb003,
591 "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n",
a9083016
GM		 592 __func__, window, win_read);
593 }
594 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
595 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
596 QLA82XX_ADDR_OCM0_MAX)) {
597 unsigned int temp1;
598 if ((addr & 0x00ff800) == 0xff800) {
7c3df132 599 ql_log(ql_log_warn, vha, 0xb004,
a9083016
GM		 600 "%s: QM access not handled.\n", __func__);
601 addr = -1UL;
602 }
603 window = OCM_WIN(addr);
604 ha->ddr_mn_window = window;
605 qla82xx_wr_32(ha,
606 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
607 win_read = qla82xx_rd_32(ha,
608 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
609 temp1 = ((window & 0x1FF) << 7) |
610 ((window & 0x0FFFE0000) >> 17);
611 if (win_read != temp1) {
7c3df132
SK		 612 ql_log(ql_log_warn, vha, 0xb005,
613 "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n",
a9083016
GM		 614 __func__, temp1, win_read);
615 }
616 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
617
618 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET,
619 QLA82XX_P3_ADDR_QDR_NET_MAX)) {
620 /* QDR network side */
621 window = MS_WIN(addr);
622 ha->qdr_sn_window = window;
623 qla82xx_wr_32(ha,
624 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window);
625 win_read = qla82xx_rd_32(ha,
626 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
627 if (win_read != window) {
7c3df132
SK		 628 ql_log(ql_log_warn, vha, 0xb006,
629 "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n",
a9083016
GM		 630 __func__, window, win_read);
631 }
632 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
633 } else {
634 /*
635 * peg gdb frequently accesses memory that doesn't exist,
636 * this limits the chit chat so debugging isn't slowed down.
637 */
638 if ((qla82xx_pci_set_window_warning_count++ < 8) ||
639 (qla82xx_pci_set_window_warning_count%64 == 0)) {
7c3df132
SK		 640 ql_log(ql_log_warn, vha, 0xb007,
641 "%s: Warning:%s Unknown address range!.\n",
642 __func__, QLA2XXX_DRIVER_NAME);
a9083016
GM		 643 }
644 addr = -1UL;
645 }
646 return addr;
647}
648
649/* check if address is in the same windows as the previous access */
650static int qla82xx_pci_is_same_window(struct qla_hw_data *ha,
651 unsigned long long addr)
652{
653 int window;
654 unsigned long long qdr_max;
655
656 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
657
658 /* DDR network side */
659 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
660 QLA82XX_ADDR_DDR_NET_MAX))
661 BUG();
662 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
663 QLA82XX_ADDR_OCM0_MAX))
664 return 1;
665 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1,
666 QLA82XX_ADDR_OCM1_MAX))
667 return 1;
668 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) {
669 /* QDR network side */
670 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f;
671 if (ha->qdr_sn_window == window)
672 return 1;
673 }
674 return 0;
675}
676
677static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha,
678 u64 off, void *data, int size)
679{
680 unsigned long flags;
fa492630 681 void __iomem *addr = NULL;
a9083016
GM		 682 int ret = 0;
683 u64 start;
fa492630 684 uint8_t __iomem *mem_ptr = NULL;
a9083016
GM		 685 unsigned long mem_base;
686 unsigned long mem_page;
7c3df132 687 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 688
689 write_lock_irqsave(&ha->hw_lock, flags);
690
691 /*
692 * If attempting to access unknown address or straddle hw windows,
693 * do not access.
694 */
695 start = qla82xx_pci_set_window(ha, off);
696 if ((start == -1UL) ||
697 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
698 write_unlock_irqrestore(&ha->hw_lock, flags);
7c3df132
SK		 699 ql_log(ql_log_fatal, vha, 0xb008,
700 "%s out of bound pci memory "
701 "access, offset is 0x%llx.\n",
702 QLA2XXX_DRIVER_NAME, off);
a9083016
GM		 703 return -1;
704 }
705
f1af6208
GM		 706 write_unlock_irqrestore(&ha->hw_lock, flags);
707 mem_base = pci_resource_start(ha->pdev, 0);
708 mem_page = start & PAGE_MASK;
709 /* Map two pages whenever user tries to access addresses in two
710 * consecutive pages.
711 */
712 if (mem_page != ((start + size - 1) & PAGE_MASK))
713 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
714 else
715 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
fa492630 716 if (mem_ptr == NULL) {
f1af6208
GM		 717 *(u8 *)data = 0;
718 return -1;
a9083016 719 }
f1af6208
GM		 720 addr = mem_ptr;
721 addr += start & (PAGE_SIZE - 1);
722 write_lock_irqsave(&ha->hw_lock, flags);
a9083016
GM		 723
724 switch (size) {
725 case 1:
726 *(u8 *)data = readb(addr);
727 break;
728 case 2:
729 *(u16 *)data = readw(addr);
730 break;
731 case 4:
732 *(u32 *)data = readl(addr);
733 break;
734 case 8:
735 *(u64 *)data = readq(addr);
736 break;
737 default:
738 ret = -1;
739 break;
740 }
741 write_unlock_irqrestore(&ha->hw_lock, flags);
742
743 if (mem_ptr)
744 iounmap(mem_ptr);
745 return ret;
746}
747
748static int
749qla82xx_pci_mem_write_direct(struct qla_hw_data *ha,
750 u64 off, void *data, int size)
751{
752 unsigned long flags;
fa492630 753 void __iomem *addr = NULL;
a9083016
GM		 754 int ret = 0;
755 u64 start;
fa492630 756 uint8_t __iomem *mem_ptr = NULL;
a9083016
GM		 757 unsigned long mem_base;
758 unsigned long mem_page;
7c3df132 759 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 760
761 write_lock_irqsave(&ha->hw_lock, flags);
762
763 /*
764 * If attempting to access unknown address or straddle hw windows,
765 * do not access.
766 */
767 start = qla82xx_pci_set_window(ha, off);
768 if ((start == -1UL) ||
769 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
770 write_unlock_irqrestore(&ha->hw_lock, flags);
7c3df132
SK		 771 ql_log(ql_log_fatal, vha, 0xb009,
772 "%s out of bount memory "
773 "access, offset is 0x%llx.\n",
774 QLA2XXX_DRIVER_NAME, off);
a9083016
GM		 775 return -1;
776 }
777
f1af6208
GM		 778 write_unlock_irqrestore(&ha->hw_lock, flags);
779 mem_base = pci_resource_start(ha->pdev, 0);
780 mem_page = start & PAGE_MASK;
781 /* Map two pages whenever user tries to access addresses in two
782 * consecutive pages.
783 */
784 if (mem_page != ((start + size - 1) & PAGE_MASK))
785 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
786 else
787 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
fa492630 788 if (mem_ptr == NULL)
f1af6208 789 return -1;
a9083016 790
f1af6208
GM		 791 addr = mem_ptr;
792 addr += start & (PAGE_SIZE - 1);
793 write_lock_irqsave(&ha->hw_lock, flags);
a9083016
GM		 794
795 switch (size) {
796 case 1:
797 writeb(*(u8 *)data, addr);
798 break;
799 case 2:
800 writew(*(u16 *)data, addr);
801 break;
802 case 4:
803 writel(*(u32 *)data, addr);
804 break;
805 case 8:
806 writeq(*(u64 *)data, addr);
807 break;
808 default:
809 ret = -1;
810 break;
811 }
812 write_unlock_irqrestore(&ha->hw_lock, flags);
813 if (mem_ptr)
814 iounmap(mem_ptr);
815 return ret;
816}
817
a9083016 818#define MTU_FUDGE_FACTOR 100
77e334d2
GM		 819static unsigned long
820qla82xx_decode_crb_addr(unsigned long addr)
a9083016
GM		 821{
822 int i;
823 unsigned long base_addr, offset, pci_base;
824
825 if (!qla82xx_crb_table_initialized)
826 qla82xx_crb_addr_transform_setup();
827
828 pci_base = ADDR_ERROR;
829 base_addr = addr & 0xfff00000;
830 offset = addr & 0x000fffff;
831
832 for (i = 0; i < MAX_CRB_XFORM; i++) {
833 if (crb_addr_xform[i] == base_addr) {
834 pci_base = i << 20;
835 break;
836 }
837 }
838 if (pci_base == ADDR_ERROR)
839 return pci_base;
840 return pci_base + offset;
841}
842
843static long rom_max_timeout = 100;
844static long qla82xx_rom_lock_timeout = 100;
845
77e334d2 846static int
a9083016
GM		 847qla82xx_rom_lock(struct qla_hw_data *ha)
848{
849 int done = 0, timeout = 0;
6c315553 850 uint32_t lock_owner = 0;
a9083016
GM		 851
852 while (!done) {
853 /* acquire semaphore2 from PCI HW block */
854 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
855 if (done == 1)
856 break;
6c315553
SK		 857 if (timeout >= qla82xx_rom_lock_timeout) {
858 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
a9083016 859 return -1;
6c315553 860 }
a9083016
GM		 861 timeout++;
862 }
4babb90e 863 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ha->portnum);
a9083016
GM		 864 return 0;
865}
866
d652e093
CD		 867static void
868qla82xx_rom_unlock(struct qla_hw_data *ha)
869{
4babb90e 870 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, 0xffffffff);
d652e093
CD		 871 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
872}
873
77e334d2 874static int
a9083016
GM		 875qla82xx_wait_rom_busy(struct qla_hw_data *ha)
876{
877 long timeout = 0;
878 long done = 0 ;
7c3df132 879 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 880
881 while (done == 0) {
882 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
883 done &= 4;
884 timeout++;
885 if (timeout >= rom_max_timeout) {
7c3df132
SK		 886 ql_dbg(ql_dbg_p3p, vha, 0xb00a,
887 "%s: Timeout reached waiting for rom busy.\n",
888 QLA2XXX_DRIVER_NAME);
a9083016
GM		 889 return -1;
890 }
891 }
892 return 0;
893}
894
77e334d2 895static int
a9083016
GM		 896qla82xx_wait_rom_done(struct qla_hw_data *ha)
897{
898 long timeout = 0;
899 long done = 0 ;
7c3df132 900 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 901
902 while (done == 0) {
903 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
904 done &= 2;
905 timeout++;
906 if (timeout >= rom_max_timeout) {
7c3df132
SK		 907 ql_dbg(ql_dbg_p3p, vha, 0xb00b,
908 "%s: Timeout reached waiting for rom done.\n",
909 QLA2XXX_DRIVER_NAME);
a9083016
GM		 910 return -1;
911 }
912 }
913 return 0;
914}
915
fa492630 916static int
2b29d96d
CD		 917qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag)
918{
919 uint32_t off_value, rval = 0;
920
fa492630 921 WRT_REG_DWORD((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase),
2b29d96d
CD		 922 (off & 0xFFFF0000));
923
924 /* Read back value to make sure write has gone through */
fa492630 925 RD_REG_DWORD((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
2b29d96d
CD		 926 off_value = (off & 0x0000FFFF);
927
928 if (flag)
fa492630 929 WRT_REG_DWORD((void __iomem *)
2b29d96d
CD		 930 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase),
931 data);
932 else
fa492630 933 rval = RD_REG_DWORD((void __iomem *)
2b29d96d
CD		 934 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase));
935
936 return rval;
937}
938
77e334d2 939static int
a9083016
GM		 940qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
941{
2b29d96d
CD		 942 /* Dword reads to flash. */
943 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1);
944 *valp = qla82xx_md_rw_32(ha, MD_DIRECT_ROM_READ_BASE +
945 (addr & 0x0000FFFF), 0, 0);
7c3df132 946
a9083016
GM		 947 return 0;
948}
949
77e334d2 950static int
a9083016
GM		 951qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
952{
953 int ret, loops = 0;
4babb90e 954 uint32_t lock_owner = 0;
7c3df132 955 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 956
957 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
958 udelay(100);
959 schedule();
960 loops++;
961 }
962 if (loops >= 50000) {
4babb90e 963 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
7c3df132 964 ql_log(ql_log_fatal, vha, 0x00b9,
4babb90e
HP		 965 "Failed to acquire SEM2 lock, Lock Owner %u.\n",
966 lock_owner);
a9083016
GM		 967 return -1;
968 }
969 ret = qla82xx_do_rom_fast_read(ha, addr, valp);
d652e093 970 qla82xx_rom_unlock(ha);
a9083016
GM		 971 return ret;
972}
973
77e334d2 974static int
a9083016
GM		 975qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val)
976{
7c3df132 977 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 978 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR);
979 qla82xx_wait_rom_busy(ha);
980 if (qla82xx_wait_rom_done(ha)) {
7c3df132
SK		 981 ql_log(ql_log_warn, vha, 0xb00c,
982 "Error waiting for rom done.\n");
a9083016
GM		 983 return -1;
984 }
985 *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
986 return 0;
987}
988
77e334d2 989static int
a9083016
GM		 990qla82xx_flash_wait_write_finish(struct qla_hw_data *ha)
991{
992 long timeout = 0;
993 uint32_t done = 1 ;
994 uint32_t val;
995 int ret = 0;
7c3df132 996 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 997
998 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
999 while ((done != 0) && (ret == 0)) {
1000 ret = qla82xx_read_status_reg(ha, &val);
1001 done = val & 1;
1002 timeout++;
1003 udelay(10);
1004 cond_resched();
1005 if (timeout >= 50000) {
7c3df132
SK		 1006 ql_log(ql_log_warn, vha, 0xb00d,
1007 "Timeout reached waiting for write finish.\n");
a9083016
GM		 1008 return -1;
1009 }
1010 }
1011 return ret;
1012}
1013
77e334d2 1014static int
a9083016
GM		 1015qla82xx_flash_set_write_enable(struct qla_hw_data *ha)
1016{
1017 uint32_t val;
1018 qla82xx_wait_rom_busy(ha);
1019 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
1020 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN);
1021 qla82xx_wait_rom_busy(ha);
1022 if (qla82xx_wait_rom_done(ha))
1023 return -1;
1024 if (qla82xx_read_status_reg(ha, &val) != 0)
1025 return -1;
1026 if ((val & 2) != 2)
1027 return -1;
1028 return 0;
1029}
1030
77e334d2 1031static int
a9083016
GM		 1032qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val)
1033{
7c3df132 1034 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 1035 if (qla82xx_flash_set_write_enable(ha))
1036 return -1;
1037 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val);
1038 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1);
1039 if (qla82xx_wait_rom_done(ha)) {
7c3df132
SK		 1040 ql_log(ql_log_warn, vha, 0xb00e,
1041 "Error waiting for rom done.\n");
a9083016
GM		 1042 return -1;
1043 }
1044 return qla82xx_flash_wait_write_finish(ha);
1045}
1046
77e334d2 1047static int
a9083016
GM		 1048qla82xx_write_disable_flash(struct qla_hw_data *ha)
1049{
7c3df132 1050 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 1051 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI);
1052 if (qla82xx_wait_rom_done(ha)) {
7c3df132
SK		 1053 ql_log(ql_log_warn, vha, 0xb00f,
1054 "Error waiting for rom done.\n");
a9083016
GM		 1055 return -1;
1056 }
1057 return 0;
1058}
1059
77e334d2 1060static int
a9083016
GM		 1061ql82xx_rom_lock_d(struct qla_hw_data *ha)
1062{
1063 int loops = 0;
4babb90e 1064 uint32_t lock_owner = 0;
7c3df132
SK		 1065 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1066
a9083016
GM		 1067 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
1068 udelay(100);
1069 cond_resched();
1070 loops++;
1071 }
1072 if (loops >= 50000) {
4babb90e 1073 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
7c3df132 1074 ql_log(ql_log_warn, vha, 0xb010,
4babb90e 1075 "ROM lock failed, Lock Owner %u.\n", lock_owner);
a9083016
GM		 1076 return -1;
1077 }
cd6dbb03 1078 return 0;
a9083016
GM		 1079}
1080
77e334d2 1081static int
a9083016
GM		 1082qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr,
1083 uint32_t data)
1084{
1085 int ret = 0;
7c3df132 1086 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 1087
1088 ret = ql82xx_rom_lock_d(ha);
1089 if (ret < 0) {
7c3df132
SK		 1090 ql_log(ql_log_warn, vha, 0xb011,
1091 "ROM lock failed.\n");
a9083016
GM		 1092 return ret;
1093 }
1094
1095 if (qla82xx_flash_set_write_enable(ha))
1096 goto done_write;
1097
1098 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data);
1099 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr);
1100 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
1101 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP);
1102 qla82xx_wait_rom_busy(ha);
1103 if (qla82xx_wait_rom_done(ha)) {
7c3df132
SK		 1104 ql_log(ql_log_warn, vha, 0xb012,
1105 "Error waiting for rom done.\n");
a9083016
GM		 1106 ret = -1;
1107 goto done_write;
1108 }
1109
1110 ret = qla82xx_flash_wait_write_finish(ha);
1111
1112done_write:
d652e093 1113 qla82xx_rom_unlock(ha);
a9083016
GM		 1114 return ret;
1115}
1116
1117/* This routine does CRB initialize sequence
1118 * to put the ISP into operational state
1119 */
77e334d2
GM		 1120static int
1121qla82xx_pinit_from_rom(scsi_qla_host_t *vha)
a9083016
GM		 1122{
1123 int addr, val;
1124 int i ;
1125 struct crb_addr_pair *buf;
1126 unsigned long off;
1127 unsigned offset, n;
1128 struct qla_hw_data *ha = vha->hw;
1129
1130 struct crb_addr_pair {
1131 long addr;
1132 long data;
1133 };
1134
a720101d 1135 /* Halt all the individual PEGs and other blocks of the ISP */
a9083016 1136 qla82xx_rom_lock(ha);
c9e8fd5c 1137
02be2215
GM		 1138 /* disable all I2Q */
1139 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
1140 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
1141 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
1142 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
1143 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
1144 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
1145
1146 /* disable all niu interrupts */
c9e8fd5c
MI		 1147 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
1148 /* disable xge rx/tx */
1149 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
1150 /* disable xg1 rx/tx */
1151 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
02be2215
GM		 1152 /* disable sideband mac */
1153 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
1154 /* disable ap0 mac */
1155 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
1156 /* disable ap1 mac */
1157 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
c9e8fd5c
MI		 1158
1159 /* halt sre */
1160 val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
1161 qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
1162
1163 /* halt epg */
1164 qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
1165
1166 /* halt timers */
1167 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
1168 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
1169 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
1170 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
1171 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
02be2215 1172 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
c9e8fd5c
MI		 1173
1174 /* halt pegs */
1175 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
1176 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
1177 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
1178 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
1179 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
02be2215 1180 msleep(20);
c9e8fd5c
MI		 1181
1182 /* big hammer */
a9083016
GM		 1183 if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
1184 /* don't reset CAM block on reset */
1185 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
1186 else
1187 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
d652e093 1188 qla82xx_rom_unlock(ha);
a9083016
GM		 1189
1190 /* Read the signature value from the flash.
1191 * Offset 0: Contain signature (0xcafecafe)
1192 * Offset 4: Offset and number of addr/value pairs
1193 * that present in CRB initialize sequence
1194 */
1195 if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1196 qla82xx_rom_fast_read(ha, 4, &n) != 0) {
7c3df132
SK		 1197 ql_log(ql_log_fatal, vha, 0x006e,
1198 "Error Reading crb_init area: n: %08x.\n", n);
a9083016
GM		 1199 return -1;
1200 }
1201
1202 /* Offset in flash = lower 16 bits
00adc9a0 1203 * Number of entries = upper 16 bits
a9083016
GM		 1204 */
1205 offset = n & 0xffffU;
1206 n = (n >> 16) & 0xffffU;
1207
00adc9a0 1208 /* number of addr/value pair should not exceed 1024 entries */
a9083016 1209 if (n >= 1024) {
7c3df132
SK		 1210 ql_log(ql_log_fatal, vha, 0x0071,
1211 "Card flash not initialized:n=0x%x.\n", n);
a9083016
GM		 1212 return -1;
1213 }
1214
7c3df132
SK		 1215 ql_log(ql_log_info, vha, 0x0072,
1216 "%d CRB init values found in ROM.\n", n);
a9083016
GM		 1217
1218 buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL);
1219 if (buf == NULL) {
7c3df132
SK		 1220 ql_log(ql_log_fatal, vha, 0x010c,
1221 "Unable to allocate memory.\n");
a9083016
GM		 1222 return -1;
1223 }
1224
1225 for (i = 0; i < n; i++) {
1226 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1227 qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) {
1228 kfree(buf);
1229 return -1;
1230 }
1231
1232 buf[i].addr = addr;
1233 buf[i].data = val;
1234 }
1235
1236 for (i = 0; i < n; i++) {
1237 /* Translate internal CRB initialization
1238 * address to PCI bus address
1239 */
1240 off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) +
1241 QLA82XX_PCI_CRBSPACE;
1242 /* Not all CRB addr/value pair to be written,
1243 * some of them are skipped
1244 */
1245
1246 /* skipping cold reboot MAGIC */
1247 if (off == QLA82XX_CAM_RAM(0x1fc))
1248 continue;
1249
1250 /* do not reset PCI */
1251 if (off == (ROMUSB_GLB + 0xbc))
1252 continue;
1253
1254 /* skip core clock, so that firmware can increase the clock */
1255 if (off == (ROMUSB_GLB + 0xc8))
1256 continue;
1257
1258 /* skip the function enable register */
1259 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
1260 continue;
1261
1262 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
1263 continue;
1264
1265 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
1266 continue;
1267
1268 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
1269 continue;
1270
1271 if (off == ADDR_ERROR) {
7c3df132
SK		 1272 ql_log(ql_log_fatal, vha, 0x0116,
1273 "Unknow addr: 0x%08lx.\n", buf[i].addr);
a9083016
GM		 1274 continue;
1275 }
1276
a9083016
GM		 1277 qla82xx_wr_32(ha, off, buf[i].data);
1278
1279 /* ISP requires much bigger delay to settle down,
1280 * else crb_window returns 0xffffffff
1281 */
1282 if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1283 msleep(1000);
1284
1285 /* ISP requires millisec delay between
1286 * successive CRB register updation
1287 */
1288 msleep(1);
1289 }
1290
1291 kfree(buf);
1292
1293 /* Resetting the data and instruction cache */
1294 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1295 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1296 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
1297
1298 /* Clear all protocol processing engines */
1299 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1300 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1301 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1302 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1303 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1304 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1305 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1306 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
1307 return 0;
1308}
1309
77e334d2
GM		 1310static int
1311qla82xx_pci_mem_write_2M(struct qla_hw_data *ha,
1312 u64 off, void *data, int size)
1313{
1314 int i, j, ret = 0, loop, sz[2], off0;
1315 int scale, shift_amount, startword;
1316 uint32_t temp;
1317 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1318
1319 /*
1320 * If not MN, go check for MS or invalid.
1321 */
1322 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1323 mem_crb = QLA82XX_CRB_QDR_NET;
1324 else {
1325 mem_crb = QLA82XX_CRB_DDR_NET;
1326 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1327 return qla82xx_pci_mem_write_direct(ha,
1328 off, data, size);
1329 }
1330
1331 off0 = off & 0x7;
1332 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1333 sz[1] = size - sz[0];
1334
1335 off8 = off & 0xfffffff0;
1336 loop = (((off & 0xf) + size - 1) >> 4) + 1;
1337 shift_amount = 4;
1338 scale = 2;
1339 startword = (off & 0xf)/8;
1340
1341 for (i = 0; i < loop; i++) {
1342 if (qla82xx_pci_mem_read_2M(ha, off8 +
1343 (i << shift_amount), &word[i * scale], 8))
1344 return -1;
1345 }
1346
1347 switch (size) {
1348 case 1:
1349 tmpw = *((uint8_t *)data);
1350 break;
1351 case 2:
1352 tmpw = *((uint16_t *)data);
1353 break;
1354 case 4:
1355 tmpw = *((uint32_t *)data);
1356 break;
1357 case 8:
1358 default:
1359 tmpw = *((uint64_t *)data);
1360 break;
1361 }
1362
1363 if (sz[0] == 8) {
1364 word[startword] = tmpw;
1365 } else {
1366 word[startword] &=
1367 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1368 word[startword] |= tmpw << (off0 * 8);
1369 }
1370 if (sz[1] != 0) {
1371 word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1372 word[startword+1] |= tmpw >> (sz[0] * 8);
1373 }
1374
77e334d2
GM		 1375 for (i = 0; i < loop; i++) {
1376 temp = off8 + (i << shift_amount);
1377 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1378 temp = 0;
1379 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1380 temp = word[i * scale] & 0xffffffff;
1381 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1382 temp = (word[i * scale] >> 32) & 0xffffffff;
1383 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1384 temp = word[i*scale + 1] & 0xffffffff;
1385 qla82xx_wr_32(ha, mem_crb +
1386 MIU_TEST_AGT_WRDATA_UPPER_LO, temp);
1387 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1388 qla82xx_wr_32(ha, mem_crb +
1389 MIU_TEST_AGT_WRDATA_UPPER_HI, temp);
1390
1391 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1392 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1393 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1394 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1395
1396 for (j = 0; j < MAX_CTL_CHECK; j++) {
1397 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1398 if ((temp & MIU_TA_CTL_BUSY) == 0)
1399 break;
1400 }
1401
1402 if (j >= MAX_CTL_CHECK) {
1403 if (printk_ratelimit())
1404 dev_err(&ha->pdev->dev,
7c3df132 1405 "failed to write through agent.\n");
77e334d2
GM		 1406 ret = -1;
1407 break;
1408 }
1409 }
1410
1411 return ret;
1412}
1413
1414static int
a9083016
GM		 1415qla82xx_fw_load_from_flash(struct qla_hw_data *ha)
1416{
1417 int i;
1418 long size = 0;
9c2b2975
HZ		 1419 long flashaddr = ha->flt_region_bootload << 2;
1420 long memaddr = BOOTLD_START;
a9083016
GM		 1421 u64 data;
1422 u32 high, low;
1423 size = (IMAGE_START - BOOTLD_START) / 8;
1424
1425 for (i = 0; i < size; i++) {
1426 if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1427 (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) {
1428 return -1;
1429 }
1430 data = ((u64)high << 32) | low ;
1431 qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
1432 flashaddr += 8;
1433 memaddr += 8;
1434
1435 if (i % 0x1000 == 0)
1436 msleep(1);
1437 }
1438 udelay(100);
1439 read_lock(&ha->hw_lock);
3711333d
GM		 1440 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1441 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
a9083016
GM		 1442 read_unlock(&ha->hw_lock);
1443 return 0;
1444}
1445
1446int
1447qla82xx_pci_mem_read_2M(struct qla_hw_data *ha,
1448 u64 off, void *data, int size)
1449{
1450 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1451 int shift_amount;
1452 uint32_t temp;
1453 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1454
1455 /*
1456 * If not MN, go check for MS or invalid.
1457 */
1458
1459 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1460 mem_crb = QLA82XX_CRB_QDR_NET;
1461 else {
1462 mem_crb = QLA82XX_CRB_DDR_NET;
1463 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1464 return qla82xx_pci_mem_read_direct(ha,
1465 off, data, size);
1466 }
1467
3711333d
GM		 1468 off8 = off & 0xfffffff0;
1469 off0[0] = off & 0xf;
1470 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1471 shift_amount = 4;
a9083016
GM		 1472 loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1473 off0[1] = 0;
1474 sz[1] = size - sz[0];
1475
a9083016
GM		 1476 for (i = 0; i < loop; i++) {
1477 temp = off8 + (i << shift_amount);
1478 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1479 temp = 0;
1480 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1481 temp = MIU_TA_CTL_ENABLE;
1482 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1483 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1484 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1485
1486 for (j = 0; j < MAX_CTL_CHECK; j++) {
1487 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1488 if ((temp & MIU_TA_CTL_BUSY) == 0)
1489 break;
1490 }
1491
1492 if (j >= MAX_CTL_CHECK) {
1493 if (printk_ratelimit())
1494 dev_err(&ha->pdev->dev,
7c3df132 1495 "failed to read through agent.\n");
a9083016
GM		 1496 break;
1497 }
1498
1499 start = off0[i] >> 2;
1500 end = (off0[i] + sz[i] - 1) >> 2;
1501 for (k = start; k <= end; k++) {
1502 temp = qla82xx_rd_32(ha,
1503 mem_crb + MIU_TEST_AGT_RDDATA(k));
1504 word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1505 }
1506 }
1507
a9083016
GM		 1508 if (j >= MAX_CTL_CHECK)
1509 return -1;
1510
1511 if ((off0[0] & 7) == 0) {
1512 val = word[0];
1513 } else {
1514 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1515 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1516 }
1517
1518 switch (size) {
1519 case 1:
1520 *(uint8_t *)data = val;
1521 break;
1522 case 2:
1523 *(uint16_t *)data = val;
1524 break;
1525 case 4:
1526 *(uint32_t *)data = val;
1527 break;
1528 case 8:
1529 *(uint64_t *)data = val;
1530 break;
1531 }
1532 return 0;
1533}
1534
a9083016 1535
9c2b2975
HZ		 1536static struct qla82xx_uri_table_desc *
1537qla82xx_get_table_desc(const u8 *unirom, int section)
1538{
1539 uint32_t i;
1540 struct qla82xx_uri_table_desc *directory =
1541 (struct qla82xx_uri_table_desc *)&unirom[0];
1542 __le32 offset;
1543 __le32 tab_type;
1544 __le32 entries = cpu_to_le32(directory->num_entries);
1545
1546 for (i = 0; i < entries; i++) {
1547 offset = cpu_to_le32(directory->findex) +
1548 (i * cpu_to_le32(directory->entry_size));
1549 tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8));
1550
1551 if (tab_type == section)
1552 return (struct qla82xx_uri_table_desc *)&unirom[offset];
1553 }
1554
1555 return NULL;
1556}
1557
1558static struct qla82xx_uri_data_desc *
1559qla82xx_get_data_desc(struct qla_hw_data *ha,
1560 u32 section, u32 idx_offset)
1561{
1562 const u8 *unirom = ha->hablob->fw->data;
1563 int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset));
1564 struct qla82xx_uri_table_desc *tab_desc = NULL;
1565 __le32 offset;
1566
1567 tab_desc = qla82xx_get_table_desc(unirom, section);
1568 if (!tab_desc)
1569 return NULL;
1570
1571 offset = cpu_to_le32(tab_desc->findex) +
1572 (cpu_to_le32(tab_desc->entry_size) * idx);
1573
1574 return (struct qla82xx_uri_data_desc *)&unirom[offset];
1575}
1576
1577static u8 *
1578qla82xx_get_bootld_offset(struct qla_hw_data *ha)
1579{
1580 u32 offset = BOOTLD_START;
1581 struct qla82xx_uri_data_desc *uri_desc = NULL;
1582
1583 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1584 uri_desc = qla82xx_get_data_desc(ha,
1585 QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF);
1586 if (uri_desc)
1587 offset = cpu_to_le32(uri_desc->findex);
1588 }
1589
1590 return (u8 *)&ha->hablob->fw->data[offset];
1591}
1592
1593static __le32
1594qla82xx_get_fw_size(struct qla_hw_data *ha)
1595{
1596 struct qla82xx_uri_data_desc *uri_desc = NULL;
1597
1598 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1599 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
1600 QLA82XX_URI_FIRMWARE_IDX_OFF);
1601 if (uri_desc)
1602 return cpu_to_le32(uri_desc->size);
1603 }
1604
1605 return cpu_to_le32(*(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]);
1606}
1607
1608static u8 *
1609qla82xx_get_fw_offs(struct qla_hw_data *ha)
1610{
1611 u32 offset = IMAGE_START;
1612 struct qla82xx_uri_data_desc *uri_desc = NULL;
1613
1614 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1615 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
1616 QLA82XX_URI_FIRMWARE_IDX_OFF);
1617 if (uri_desc)
1618 offset = cpu_to_le32(uri_desc->findex);
1619 }
1620
1621 return (u8 *)&ha->hablob->fw->data[offset];
1622}
1623
a9083016 1624/* PCI related functions */
a9083016
GM		 1625int qla82xx_pci_region_offset(struct pci_dev *pdev, int region)
1626{
1627 unsigned long val = 0;
1628 u32 control;
1629
1630 switch (region) {
1631 case 0:
1632 val = 0;
1633 break;
1634 case 1:
1635 pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control);
1636 val = control + QLA82XX_MSIX_TBL_SPACE;
1637 break;
1638 }
1639 return val;
1640}
1641
a9083016
GM		 1642
1643int
1644qla82xx_iospace_config(struct qla_hw_data *ha)
1645{
1646 uint32_t len = 0;
1647
1648 if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) {
7c3df132
SK		 1649 ql_log_pci(ql_log_fatal, ha->pdev, 0x000c,
1650 "Failed to reserver selected regions.\n");
a9083016
GM		 1651 goto iospace_error_exit;
1652 }
1653
1654 /* Use MMIO operations for all accesses. */
1655 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
7c3df132
SK		 1656 ql_log_pci(ql_log_fatal, ha->pdev, 0x000d,
1657 "Region #0 not an MMIO resource, aborting.\n");
a9083016
GM		 1658 goto iospace_error_exit;
1659 }
1660
1661 len = pci_resource_len(ha->pdev, 0);
1662 ha->nx_pcibase =
1663 (unsigned long)ioremap(pci_resource_start(ha->pdev, 0), len);
1664 if (!ha->nx_pcibase) {
7c3df132
SK		 1665 ql_log_pci(ql_log_fatal, ha->pdev, 0x000e,
1666 "Cannot remap pcibase MMIO, aborting.\n");
a9083016
GM		 1667 goto iospace_error_exit;
1668 }
1669
1670 /* Mapping of IO base pointer */
7ec0effd
AD		 1671 if (IS_QLA8044(ha)) {
1672 ha->iobase =
f73cb695 1673 (device_reg_t *)((uint8_t *)ha->nx_pcibase);
7ec0effd
AD		 1674 } else if (IS_QLA82XX(ha)) {
1675 ha->iobase =
f73cb695 1676 (device_reg_t *)((uint8_t *)ha->nx_pcibase +
7ec0effd
AD		 1677 0xbc000 + (ha->pdev->devfn << 11));
1678 }
a9083016
GM		 1679
1680 if (!ql2xdbwr) {
1681 ha->nxdb_wr_ptr =
1682 (unsigned long)ioremap((pci_resource_start(ha->pdev, 4) +
1683 (ha->pdev->devfn << 12)), 4);
1684 if (!ha->nxdb_wr_ptr) {
7c3df132
SK		 1685 ql_log_pci(ql_log_fatal, ha->pdev, 0x000f,
1686 "Cannot remap MMIO, aborting.\n");
a9083016
GM		 1687 goto iospace_error_exit;
1688 }
1689
1690 /* Mapping of IO base pointer,
1691 * door bell read and write pointer
1692 */
1693 ha->nxdb_rd_ptr = (uint8_t *) ha->nx_pcibase + (512 * 1024) +
1694 (ha->pdev->devfn * 8);
1695 } else {
1696 ha->nxdb_wr_ptr = (ha->pdev->devfn == 6 ?
1697 QLA82XX_CAMRAM_DB1 :
1698 QLA82XX_CAMRAM_DB2);
1699 }
1700
1701 ha->max_req_queues = ha->max_rsp_queues = 1;
1702 ha->msix_count = ha->max_rsp_queues + 1;
7c3df132
SK		 1703 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006,
1704 "nx_pci_base=%p iobase=%p "
1705 "max_req_queues=%d msix_count=%d.\n",
d8424f68 1706 (void *)ha->nx_pcibase, ha->iobase,
7c3df132
SK		 1707 ha->max_req_queues, ha->msix_count);
1708 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010,
1709 "nx_pci_base=%p iobase=%p "
1710 "max_req_queues=%d msix_count=%d.\n",
d8424f68 1711 (void *)ha->nx_pcibase, ha->iobase,
7c3df132 1712 ha->max_req_queues, ha->msix_count);
a9083016
GM		 1713 return 0;
1714
1715iospace_error_exit:
1716 return -ENOMEM;
1717}
1718
1719/* GS related functions */
1720
1721/* Initialization related functions */
1722
1723/**
1724 * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers.
1725 * @ha: HA context
1726 *
1727 * Returns 0 on success.
1728*/
1729int
1730qla82xx_pci_config(scsi_qla_host_t *vha)
1731{
1732 struct qla_hw_data *ha = vha->hw;
1733 int ret;
1734
1735 pci_set_master(ha->pdev);
1736 ret = pci_set_mwi(ha->pdev);
1737 ha->chip_revision = ha->pdev->revision;
7c3df132 1738 ql_dbg(ql_dbg_init, vha, 0x0043,
d8424f68 1739 "Chip revision:%d.\n",
7c3df132 1740 ha->chip_revision);
a9083016
GM		 1741 return 0;
1742}
1743
1744/**
1745 * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers.
1746 * @ha: HA context
1747 *
1748 * Returns 0 on success.
1749 */
1750void
1751qla82xx_reset_chip(scsi_qla_host_t *vha)
1752{
1753 struct qla_hw_data *ha = vha->hw;
1754 ha->isp_ops->disable_intrs(ha);
1755}
1756
1757void qla82xx_config_rings(struct scsi_qla_host *vha)
1758{
1759 struct qla_hw_data *ha = vha->hw;
1760 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
1761 struct init_cb_81xx *icb;
1762 struct req_que *req = ha->req_q_map[0];
1763 struct rsp_que *rsp = ha->rsp_q_map[0];
1764
1765 /* Setup ring parameters in initialization control block. */
1766 icb = (struct init_cb_81xx *)ha->init_cb;
1767 icb->request_q_outpointer = __constant_cpu_to_le16(0);
1768 icb->response_q_inpointer = __constant_cpu_to_le16(0);
1769 icb->request_q_length = cpu_to_le16(req->length);
1770 icb->response_q_length = cpu_to_le16(rsp->length);
1771 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1772 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1773 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1774 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
1775
a9083016
GM		 1776 WRT_REG_DWORD((unsigned long __iomem *)&reg->req_q_out[0], 0);
1777 WRT_REG_DWORD((unsigned long __iomem *)&reg->rsp_q_in[0], 0);
1778 WRT_REG_DWORD((unsigned long __iomem *)&reg->rsp_q_out[0], 0);
1779}
1780
77e334d2
GM		 1781static int
1782qla82xx_fw_load_from_blob(struct qla_hw_data *ha)
a9083016
GM		 1783{
1784 u64 *ptr64;
1785 u32 i, flashaddr, size;
1786 __le64 data;
1787
1788 size = (IMAGE_START - BOOTLD_START) / 8;
1789
9c2b2975 1790 ptr64 = (u64 *)qla82xx_get_bootld_offset(ha);
a9083016
GM		 1791 flashaddr = BOOTLD_START;
1792
1793 for (i = 0; i < size; i++) {
1794 data = cpu_to_le64(ptr64[i]);
9c2b2975
HZ		 1795 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1796 return -EIO;
a9083016
GM		 1797 flashaddr += 8;
1798 }
1799
a9083016 1800 flashaddr = FLASH_ADDR_START;
9c2b2975
HZ		 1801 size = (__force u32)qla82xx_get_fw_size(ha) / 8;
1802 ptr64 = (u64 *)qla82xx_get_fw_offs(ha);
a9083016
GM		 1803
1804 for (i = 0; i < size; i++) {
1805 data = cpu_to_le64(ptr64[i]);
1806
1807 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1808 return -EIO;
1809 flashaddr += 8;
1810 }
9c2b2975 1811 udelay(100);
a9083016
GM		 1812
1813 /* Write a magic value to CAMRAM register
1814 * at a specified offset to indicate
1815 * that all data is written and
1816 * ready for firmware to initialize.
1817 */
9c2b2975 1818 qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC);
a9083016 1819
9c2b2975 1820 read_lock(&ha->hw_lock);
3711333d
GM		 1821 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1822 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
9c2b2975
HZ		 1823 read_unlock(&ha->hw_lock);
1824 return 0;
1825}
1826
1827static int
1828qla82xx_set_product_offset(struct qla_hw_data *ha)
1829{
1830 struct qla82xx_uri_table_desc *ptab_desc = NULL;
1831 const uint8_t *unirom = ha->hablob->fw->data;
1832 uint32_t i;
1833 __le32 entries;
1834 __le32 flags, file_chiprev, offset;
1835 uint8_t chiprev = ha->chip_revision;
1836 /* Hardcoding mn_present flag for P3P */
1837 int mn_present = 0;
1838 uint32_t flagbit;
1839
1840 ptab_desc = qla82xx_get_table_desc(unirom,
1841 QLA82XX_URI_DIR_SECT_PRODUCT_TBL);
1842 if (!ptab_desc)
1843 return -1;
1844
1845 entries = cpu_to_le32(ptab_desc->num_entries);
1846
1847 for (i = 0; i < entries; i++) {
1848 offset = cpu_to_le32(ptab_desc->findex) +
1849 (i * cpu_to_le32(ptab_desc->entry_size));
1850 flags = cpu_to_le32(*((int *)&unirom[offset] +
1851 QLA82XX_URI_FLAGS_OFF));
1852 file_chiprev = cpu_to_le32(*((int *)&unirom[offset] +
1853 QLA82XX_URI_CHIP_REV_OFF));
1854
1855 flagbit = mn_present ? 1 : 2;
1856
1857 if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) {
1858 ha->file_prd_off = offset;
1859 return 0;
1860 }
1861 }
1862 return -1;
1863}
1864
fa492630 1865static int
9c2b2975
HZ		 1866qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type)
1867{
1868 __le32 val;
1869 uint32_t min_size;
1870 struct qla_hw_data *ha = vha->hw;
1871 const struct firmware *fw = ha->hablob->fw;
1872
1873 ha->fw_type = fw_type;
1874
1875 if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1876 if (qla82xx_set_product_offset(ha))
1877 return -EINVAL;
1878
1879 min_size = QLA82XX_URI_FW_MIN_SIZE;
1880 } else {
1881 val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]);
1882 if ((__force u32)val != QLA82XX_BDINFO_MAGIC)
1883 return -EINVAL;
1884
1885 min_size = QLA82XX_FW_MIN_SIZE;
1886 }
1887
1888 if (fw->size < min_size)
1889 return -EINVAL;
a9083016
GM		 1890 return 0;
1891}
1892
77e334d2
GM		 1893static int
1894qla82xx_check_cmdpeg_state(struct qla_hw_data *ha)
a9083016
GM		 1895{
1896 u32 val = 0;
1897 int retries = 60;
7c3df132 1898 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 1899
1900 do {
1901 read_lock(&ha->hw_lock);
1902 val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE);
1903 read_unlock(&ha->hw_lock);
1904
1905 switch (val) {
1906 case PHAN_INITIALIZE_COMPLETE:
1907 case PHAN_INITIALIZE_ACK:
1908 return QLA_SUCCESS;
1909 case PHAN_INITIALIZE_FAILED:
1910 break;
1911 default:
1912 break;
1913 }
7c3df132
SK		 1914 ql_log(ql_log_info, vha, 0x00a8,
1915 "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n",
1916 val, retries);
a9083016
GM		 1917
1918 msleep(500);
1919
1920 } while (--retries);
1921
7c3df132 1922 ql_log(ql_log_fatal, vha, 0x00a9,
a9083016
GM		 1923 "Cmd Peg initialization failed: 0x%x.\n", val);
1924
a9083016
GM		 1925 val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
1926 read_lock(&ha->hw_lock);
1927 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
1928 read_unlock(&ha->hw_lock);
1929 return QLA_FUNCTION_FAILED;
1930}
1931
77e334d2
GM		 1932static int
1933qla82xx_check_rcvpeg_state(struct qla_hw_data *ha)
a9083016
GM		 1934{
1935 u32 val = 0;
1936 int retries = 60;
7c3df132 1937 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 1938
1939 do {
1940 read_lock(&ha->hw_lock);
1941 val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE);
1942 read_unlock(&ha->hw_lock);
1943
1944 switch (val) {
1945 case PHAN_INITIALIZE_COMPLETE:
1946 case PHAN_INITIALIZE_ACK:
1947 return QLA_SUCCESS;
1948 case PHAN_INITIALIZE_FAILED:
1949 break;
1950 default:
1951 break;
1952 }
7c3df132
SK		 1953 ql_log(ql_log_info, vha, 0x00ab,
1954 "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n",
1955 val, retries);
a9083016
GM		 1956
1957 msleep(500);
1958
1959 } while (--retries);
1960
7c3df132
SK		 1961 ql_log(ql_log_fatal, vha, 0x00ac,
1962 "Rcv Peg initializatin failed: 0x%x.\n", val);
a9083016
GM		 1963 read_lock(&ha->hw_lock);
1964 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED);
1965 read_unlock(&ha->hw_lock);
1966 return QLA_FUNCTION_FAILED;
1967}
1968
1969/* ISR related functions */
a9083016
GM		 1970static struct qla82xx_legacy_intr_set legacy_intr[] = \
1971 QLA82XX_LEGACY_INTR_CONFIG;
1972
1973/*
1974 * qla82xx_mbx_completion() - Process mailbox command completions.
1975 * @ha: SCSI driver HA context
1976 * @mb0: Mailbox0 register
1977 */
7ec0effd 1978void
a9083016
GM		 1979qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
1980{
1981 uint16_t cnt;
1982 uint16_t __iomem *wptr;
1983 struct qla_hw_data *ha = vha->hw;
1984 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
1985 wptr = (uint16_t __iomem *)&reg->mailbox_out[1];
1986
1987 /* Load return mailbox registers. */
1988 ha->flags.mbox_int = 1;
1989 ha->mailbox_out[0] = mb0;
1990
1991 for (cnt = 1; cnt < ha->mbx_count; cnt++) {
1992 ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
1993 wptr++;
1994 }
1995
cfb0919c 1996 if (!ha->mcp)
7c3df132
SK		 1997 ql_dbg(ql_dbg_async, vha, 0x5053,
1998 "MBX pointer ERROR.\n");
a9083016
GM		 1999}
2000
2001/*
2002 * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
2003 * @irq:
2004 * @dev_id: SCSI driver HA context
2005 * @regs:
2006 *
2007 * Called by system whenever the host adapter generates an interrupt.
2008 *
2009 * Returns handled flag.
2010 */
2011irqreturn_t
2012qla82xx_intr_handler(int irq, void *dev_id)
2013{
2014 scsi_qla_host_t *vha;
2015 struct qla_hw_data *ha;
2016 struct rsp_que *rsp;
2017 struct device_reg_82xx __iomem *reg;
2018 int status = 0, status1 = 0;
2019 unsigned long flags;
2020 unsigned long iter;
7c3df132 2021 uint32_t stat = 0;
a9083016
GM		 2022 uint16_t mb[4];
2023
2024 rsp = (struct rsp_que *) dev_id;
2025 if (!rsp) {
b6d0d9d5 2026 ql_log(ql_log_info, NULL, 0xb053,
3256b435 2027 "%s: NULL response queue pointer.\n", __func__);
a9083016
GM		 2028 return IRQ_NONE;
2029 }
2030 ha = rsp->hw;
2031
2032 if (!ha->flags.msi_enabled) {
2033 status = qla82xx_rd_32(ha, ISR_INT_VECTOR);
2034 if (!(status & ha->nx_legacy_intr.int_vec_bit))
2035 return IRQ_NONE;
2036
2037 status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG);
2038 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1))
2039 return IRQ_NONE;
2040 }
2041
2042 /* clear the interrupt */
2043 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff);
2044
2045 /* read twice to ensure write is flushed */
2046 qla82xx_rd_32(ha, ISR_INT_VECTOR);
2047 qla82xx_rd_32(ha, ISR_INT_VECTOR);
2048
2049 reg = &ha->iobase->isp82;
2050
2051 spin_lock_irqsave(&ha->hardware_lock, flags);
2052 vha = pci_get_drvdata(ha->pdev);
2053 for (iter = 1; iter--; ) {
2054
2055 if (RD_REG_DWORD(&reg->host_int)) {
2056 stat = RD_REG_DWORD(&reg->host_status);
a9083016
GM		 2057
2058 switch (stat & 0xff) {
2059 case 0x1:
2060 case 0x2:
2061 case 0x10:
2062 case 0x11:
2063 qla82xx_mbx_completion(vha, MSW(stat));
2064 status |= MBX_INTERRUPT;
2065 break;
2066 case 0x12:
2067 mb[0] = MSW(stat);
2068 mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
2069 mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
2070 mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
2071 qla2x00_async_event(vha, rsp, mb);
2072 break;
2073 case 0x13:
2074 qla24xx_process_response_queue(vha, rsp);
2075 break;
2076 default:
7c3df132
SK		 2077 ql_dbg(ql_dbg_async, vha, 0x5054,
2078 "Unrecognized interrupt type (%d).\n",
2079 stat & 0xff);
a9083016
GM		 2080 break;
2081 }
2082 }
2083 WRT_REG_DWORD(&reg->host_int, 0);
2084 }
a9083016 2085
36439832 2086 qla2x00_handle_mbx_completion(ha, status);
2087 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2088
2089 if (!ha->flags.msi_enabled)
2090 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2091
a9083016
GM		 2092 return IRQ_HANDLED;
2093}
2094
2095irqreturn_t
2096qla82xx_msix_default(int irq, void *dev_id)
2097{
2098 scsi_qla_host_t *vha;
2099 struct qla_hw_data *ha;
2100 struct rsp_que *rsp;
2101 struct device_reg_82xx __iomem *reg;
2102 int status = 0;
2103 unsigned long flags;
7c3df132 2104 uint32_t stat = 0;
f3ddac19 2105 uint32_t host_int = 0;
a9083016
GM		 2106 uint16_t mb[4];
2107
2108 rsp = (struct rsp_que *) dev_id;
2109 if (!rsp) {
2110 printk(KERN_INFO
7c3df132 2111 "%s(): NULL response queue pointer.\n", __func__);
a9083016
GM		 2112 return IRQ_NONE;
2113 }
2114 ha = rsp->hw;
2115
2116 reg = &ha->iobase->isp82;
2117
2118 spin_lock_irqsave(&ha->hardware_lock, flags);
2119 vha = pci_get_drvdata(ha->pdev);
2120 do {
f3ddac19
CD		 2121 host_int = RD_REG_DWORD(&reg->host_int);
2122 if (qla2x00_check_reg_for_disconnect(vha, host_int))
2123 break;
2124 if (host_int) {
a9083016 2125 stat = RD_REG_DWORD(&reg->host_status);
a9083016
GM		 2126
2127 switch (stat & 0xff) {
2128 case 0x1:
2129 case 0x2:
2130 case 0x10:
2131 case 0x11:
2132 qla82xx_mbx_completion(vha, MSW(stat));
2133 status |= MBX_INTERRUPT;
2134 break;
2135 case 0x12:
2136 mb[0] = MSW(stat);
2137 mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
2138 mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
2139 mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
2140 qla2x00_async_event(vha, rsp, mb);
2141 break;
2142 case 0x13:
2143 qla24xx_process_response_queue(vha, rsp);
2144 break;
2145 default:
7c3df132
SK		 2146 ql_dbg(ql_dbg_async, vha, 0x5041,
2147 "Unrecognized interrupt type (%d).\n",
2148 stat & 0xff);
a9083016
GM		 2149 break;
2150 }
2151 }
2152 WRT_REG_DWORD(&reg->host_int, 0);
2153 } while (0);
2154
36439832 2155 qla2x00_handle_mbx_completion(ha, status);
2156 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2157
a9083016
GM		 2158 return IRQ_HANDLED;
2159}
2160
2161irqreturn_t
2162qla82xx_msix_rsp_q(int irq, void *dev_id)
2163{
2164 scsi_qla_host_t *vha;
2165 struct qla_hw_data *ha;
2166 struct rsp_que *rsp;
2167 struct device_reg_82xx __iomem *reg;
3553d343 2168 unsigned long flags;
f3ddac19 2169 uint32_t host_int = 0;
a9083016
GM		 2170
2171 rsp = (struct rsp_que *) dev_id;
2172 if (!rsp) {
2173 printk(KERN_INFO
7c3df132 2174 "%s(): NULL response queue pointer.\n", __func__);
a9083016
GM		 2175 return IRQ_NONE;
2176 }
2177
2178 ha = rsp->hw;
2179 reg = &ha->iobase->isp82;
3553d343 2180 spin_lock_irqsave(&ha->hardware_lock, flags);
a9083016 2181 vha = pci_get_drvdata(ha->pdev);
f3ddac19
CD		 2182 host_int = RD_REG_DWORD(&reg->host_int);
2183 if (qla2x00_check_reg_for_disconnect(vha, host_int))
2184 goto out;
a9083016
GM		 2185 qla24xx_process_response_queue(vha, rsp);
2186 WRT_REG_DWORD(&reg->host_int, 0);
f3ddac19 2187out:
3553d343 2188 spin_unlock_irqrestore(&ha->hardware_lock, flags);
a9083016
GM		 2189 return IRQ_HANDLED;
2190}
2191
2192void
2193qla82xx_poll(int irq, void *dev_id)
2194{
2195 scsi_qla_host_t *vha;
2196 struct qla_hw_data *ha;
2197 struct rsp_que *rsp;
2198 struct device_reg_82xx __iomem *reg;
2199 int status = 0;
2200 uint32_t stat;
f3ddac19 2201 uint32_t host_int = 0;
a9083016
GM		 2202 uint16_t mb[4];
2203 unsigned long flags;
2204
2205 rsp = (struct rsp_que *) dev_id;
2206 if (!rsp) {
2207 printk(KERN_INFO
7c3df132 2208 "%s(): NULL response queue pointer.\n", __func__);
a9083016
GM		 2209 return;
2210 }
2211 ha = rsp->hw;
2212
2213 reg = &ha->iobase->isp82;
2214 spin_lock_irqsave(&ha->hardware_lock, flags);
2215 vha = pci_get_drvdata(ha->pdev);
2216
f3ddac19
CD		 2217 host_int = RD_REG_DWORD(&reg->host_int);
2218 if (qla2x00_check_reg_for_disconnect(vha, host_int))
2219 goto out;
2220 if (host_int) {
a9083016
GM		 2221 stat = RD_REG_DWORD(&reg->host_status);
2222 switch (stat & 0xff) {
2223 case 0x1:
2224 case 0x2:
2225 case 0x10:
2226 case 0x11:
2227 qla82xx_mbx_completion(vha, MSW(stat));
2228 status |= MBX_INTERRUPT;
2229 break;
2230 case 0x12:
2231 mb[0] = MSW(stat);
2232 mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
2233 mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
2234 mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
2235 qla2x00_async_event(vha, rsp, mb);
2236 break;
2237 case 0x13:
2238 qla24xx_process_response_queue(vha, rsp);
2239 break;
2240 default:
7c3df132
SK		 2241 ql_dbg(ql_dbg_p3p, vha, 0xb013,
2242 "Unrecognized interrupt type (%d).\n",
2243 stat * 0xff);
a9083016
GM		 2244 break;
2245 }
02a9ae6e 2246 WRT_REG_DWORD(&reg->host_int, 0);
a9083016 2247 }
f3ddac19 2248out:
a9083016
GM		 2249 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2250}
2251
2252void
2253qla82xx_enable_intrs(struct qla_hw_data *ha)
2254{
2255 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2256 qla82xx_mbx_intr_enable(vha);
2257 spin_lock_irq(&ha->hardware_lock);
7ec0effd
AD		 2258 if (IS_QLA8044(ha))
2259 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 0);
2260 else
2261 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
a9083016
GM		 2262 spin_unlock_irq(&ha->hardware_lock);
2263 ha->interrupts_on = 1;
2264}
2265
2266void
2267qla82xx_disable_intrs(struct qla_hw_data *ha)
2268{
2269 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2270 qla82xx_mbx_intr_disable(vha);
2271 spin_lock_irq(&ha->hardware_lock);
7ec0effd
AD		 2272 if (IS_QLA8044(ha))
2273 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 1);
2274 else
2275 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
a9083016
GM		 2276 spin_unlock_irq(&ha->hardware_lock);
2277 ha->interrupts_on = 0;
2278}
2279
2280void qla82xx_init_flags(struct qla_hw_data *ha)
2281{
2282 struct qla82xx_legacy_intr_set *nx_legacy_intr;
2283
2284 /* ISP 8021 initializations */
2285 rwlock_init(&ha->hw_lock);
2286 ha->qdr_sn_window = -1;
2287 ha->ddr_mn_window = -1;
2288 ha->curr_window = 255;
2289 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2290 nx_legacy_intr = &legacy_intr[ha->portnum];
2291 ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit;
2292 ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg;
2293 ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg;
2294 ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg;
2295}
2296
0251ce8c
SK		 2297inline void
2298qla82xx_set_idc_version(scsi_qla_host_t *vha)
2299{
2300 int idc_ver;
2301 uint32_t drv_active;
2302 struct qla_hw_data *ha = vha->hw;
2303
2304 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2305 if (drv_active == (QLA82XX_DRV_ACTIVE << (ha->portnum * 4))) {
2306 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
2307 QLA82XX_IDC_VERSION);
2308 ql_log(ql_log_info, vha, 0xb082,
2309 "IDC version updated to %d\n", QLA82XX_IDC_VERSION);
2310 } else {
2311 idc_ver = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_IDC_VERSION);
2312 if (idc_ver != QLA82XX_IDC_VERSION)
2313 ql_log(ql_log_info, vha, 0xb083,
2314 "qla2xxx driver IDC version %d is not compatible "
2315 "with IDC version %d of the other drivers\n",
2316 QLA82XX_IDC_VERSION, idc_ver);
2317 }
2318}
2319
a5b36321 2320inline void
a9083016
GM		 2321qla82xx_set_drv_active(scsi_qla_host_t *vha)
2322{
2323 uint32_t drv_active;
2324 struct qla_hw_data *ha = vha->hw;
2325
2326 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2327
2328 /* If reset value is all FF's, initialize DRV_ACTIVE */
2329 if (drv_active == 0xffffffff) {
77e334d2
GM		 2330 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE,
2331 QLA82XX_DRV_NOT_ACTIVE);
a9083016
GM		 2332 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2333 }
77e334d2 2334 drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
a9083016
GM		 2335 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
2336}
2337
2338inline void
2339qla82xx_clear_drv_active(struct qla_hw_data *ha)
2340{
2341 uint32_t drv_active;
2342
2343 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
77e334d2 2344 drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
a9083016
GM		 2345 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
2346}
2347
2348static inline int
2349qla82xx_need_reset(struct qla_hw_data *ha)
2350{
2351 uint32_t drv_state;
2352 int rval;
2353
7d613ac6 2354 if (ha->flags.nic_core_reset_owner)
08de2844
GM		 2355 return 1;
2356 else {
2357 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2358 rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2359 return rval;
2360 }
a9083016
GM		 2361}
2362
2363static inline void
2364qla82xx_set_rst_ready(struct qla_hw_data *ha)
2365{
2366 uint32_t drv_state;
2367 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2368
2369 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2370
2371 /* If reset value is all FF's, initialize DRV_STATE */
2372 if (drv_state == 0xffffffff) {
77e334d2 2373 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY);
a9083016
GM		 2374 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2375 }
2376 drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
08de2844
GM		 2377 ql_dbg(ql_dbg_init, vha, 0x00bb,
2378 "drv_state = 0x%08x.\n", drv_state);
a9083016
GM		 2379 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
2380}
2381
2382static inline void
2383qla82xx_clear_rst_ready(struct qla_hw_data *ha)
2384{
2385 uint32_t drv_state;
2386
2387 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2388 drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2389 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
2390}
2391
2392static inline void
2393qla82xx_set_qsnt_ready(struct qla_hw_data *ha)
2394{
2395 uint32_t qsnt_state;
2396
2397 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2398 qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4));
2399 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
2400}
2401
579d12b5
SK		 2402void
2403qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha)
2404{
2405 struct qla_hw_data *ha = vha->hw;
2406 uint32_t qsnt_state;
2407
2408 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2409 qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4));
2410 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
2411}
2412
77e334d2
GM		 2413static int
2414qla82xx_load_fw(scsi_qla_host_t *vha)
a9083016
GM		 2415{
2416 int rst;
2417 struct fw_blob *blob;
2418 struct qla_hw_data *ha = vha->hw;
2419
a9083016 2420 if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) {
7c3df132
SK		 2421 ql_log(ql_log_fatal, vha, 0x009f,
2422 "Error during CRB initialization.\n");
a9083016
GM		 2423 return QLA_FUNCTION_FAILED;
2424 }
2425 udelay(500);
2426
2427 /* Bring QM and CAMRAM out of reset */
2428 rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
2429 rst &= ~((1 << 28) | (1 << 24));
2430 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
2431
2432 /*
2433 * FW Load priority:
2434 * 1) Operational firmware residing in flash.
2435 * 2) Firmware via request-firmware interface (.bin file).
2436 */
2437 if (ql2xfwloadbin == 2)
2438 goto try_blob_fw;
2439
7c3df132
SK		 2440 ql_log(ql_log_info, vha, 0x00a0,
2441 "Attempting to load firmware from flash.\n");
a9083016
GM		 2442
2443 if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) {
7c3df132 2444 ql_log(ql_log_info, vha, 0x00a1,
00adc9a0 2445 "Firmware loaded successfully from flash.\n");
a9083016 2446 return QLA_SUCCESS;
875efad7 2447 } else {
7c3df132
SK		 2448 ql_log(ql_log_warn, vha, 0x0108,
2449 "Firmware load from flash failed.\n");
a9083016 2450 }
875efad7 2451
a9083016 2452try_blob_fw:
7c3df132
SK		 2453 ql_log(ql_log_info, vha, 0x00a2,
2454 "Attempting to load firmware from blob.\n");
a9083016
GM		 2455
2456 /* Load firmware blob. */
2457 blob = ha->hablob = qla2x00_request_firmware(vha);
2458 if (!blob) {
7c3df132 2459 ql_log(ql_log_fatal, vha, 0x00a3,
00adc9a0 2460 "Firmware image not present.\n");
a9083016
GM		 2461 goto fw_load_failed;
2462 }
2463
9c2b2975
HZ		 2464 /* Validating firmware blob */
2465 if (qla82xx_validate_firmware_blob(vha,
2466 QLA82XX_FLASH_ROMIMAGE)) {
2467 /* Fallback to URI format */
2468 if (qla82xx_validate_firmware_blob(vha,
2469 QLA82XX_UNIFIED_ROMIMAGE)) {
7c3df132
SK		 2470 ql_log(ql_log_fatal, vha, 0x00a4,
2471 "No valid firmware image found.\n");
9c2b2975
HZ		 2472 return QLA_FUNCTION_FAILED;
2473 }
2474 }
2475
a9083016 2476 if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) {
7c3df132
SK		 2477 ql_log(ql_log_info, vha, 0x00a5,
2478 "Firmware loaded successfully from binary blob.\n");
a9083016
GM		 2479 return QLA_SUCCESS;
2480 } else {
7c3df132
SK		 2481 ql_log(ql_log_fatal, vha, 0x00a6,
2482 "Firmware load failed for binary blob.\n");
a9083016
GM		 2483 blob->fw = NULL;
2484 blob = NULL;
2485 goto fw_load_failed;
2486 }
2487 return QLA_SUCCESS;
2488
2489fw_load_failed:
2490 return QLA_FUNCTION_FAILED;
2491}
2492
a5b36321 2493int
a9083016
GM		 2494qla82xx_start_firmware(scsi_qla_host_t *vha)
2495{
a9083016
GM		 2496 uint16_t lnk;
2497 struct qla_hw_data *ha = vha->hw;
2498
2499 /* scrub dma mask expansion register */
77e334d2 2500 qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE);
a9083016 2501
3711333d
GM		 2502 /* Put both the PEG CMD and RCV PEG to default state
2503 * of 0 before resetting the hardware
2504 */
2505 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
2506 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0);
2507
a9083016
GM		 2508 /* Overwrite stale initialization register values */
2509 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
2510 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
2511
2512 if (qla82xx_load_fw(vha) != QLA_SUCCESS) {
7c3df132
SK		 2513 ql_log(ql_log_fatal, vha, 0x00a7,
2514 "Error trying to start fw.\n");
a9083016
GM		 2515 return QLA_FUNCTION_FAILED;
2516 }
2517
2518 /* Handshake with the card before we register the devices. */
2519 if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) {
7c3df132
SK		 2520 ql_log(ql_log_fatal, vha, 0x00aa,
2521 "Error during card handshake.\n");
a9083016
GM		 2522 return QLA_FUNCTION_FAILED;
2523 }
2524
2525 /* Negotiated Link width */
10092438 2526 pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk);
a9083016
GM		 2527 ha->link_width = (lnk >> 4) & 0x3f;
2528
2529 /* Synchronize with Receive peg */
2530 return qla82xx_check_rcvpeg_state(ha);
2531}
2532
77e334d2 2533static uint32_t *
a9083016
GM		 2534qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
2535 uint32_t length)
2536{
2537 uint32_t i;
2538 uint32_t val;
2539 struct qla_hw_data *ha = vha->hw;
2540
2541 /* Dword reads to flash. */
2542 for (i = 0; i < length/4; i++, faddr += 4) {
2543 if (qla82xx_rom_fast_read(ha, faddr, &val)) {
7c3df132
SK		 2544 ql_log(ql_log_warn, vha, 0x0106,
2545 "Do ROM fast read failed.\n");
a9083016
GM		 2546 goto done_read;
2547 }
2548 dwptr[i] = __constant_cpu_to_le32(val);
2549 }
2550done_read:
2551 return dwptr;
2552}
2553
77e334d2 2554static int
a9083016
GM		 2555qla82xx_unprotect_flash(struct qla_hw_data *ha)
2556{
2557 int ret;
2558 uint32_t val;
7c3df132 2559 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 2560
2561 ret = ql82xx_rom_lock_d(ha);
2562 if (ret < 0) {
7c3df132
SK		 2563 ql_log(ql_log_warn, vha, 0xb014,
2564 "ROM Lock failed.\n");
a9083016
GM		 2565 return ret;
2566 }
2567
2568 ret = qla82xx_read_status_reg(ha, &val);
2569 if (ret < 0)
2570 goto done_unprotect;
2571
0547fb37 2572 val &= ~(BLOCK_PROTECT_BITS << 2);
a9083016
GM		 2573 ret = qla82xx_write_status_reg(ha, val);
2574 if (ret < 0) {
0547fb37 2575 val |= (BLOCK_PROTECT_BITS << 2);
a9083016
GM		 2576 qla82xx_write_status_reg(ha, val);
2577 }
2578
2579 if (qla82xx_write_disable_flash(ha) != 0)
7c3df132
SK		 2580 ql_log(ql_log_warn, vha, 0xb015,
2581 "Write disable failed.\n");
a9083016
GM		 2582
2583done_unprotect:
d652e093 2584 qla82xx_rom_unlock(ha);
a9083016
GM		 2585 return ret;
2586}
2587
77e334d2 2588static int
a9083016
GM		 2589qla82xx_protect_flash(struct qla_hw_data *ha)
2590{
2591 int ret;
2592 uint32_t val;
7c3df132 2593 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 2594
2595 ret = ql82xx_rom_lock_d(ha);
2596 if (ret < 0) {
7c3df132
SK		 2597 ql_log(ql_log_warn, vha, 0xb016,
2598 "ROM Lock failed.\n");
a9083016
GM		 2599 return ret;
2600 }
2601
2602 ret = qla82xx_read_status_reg(ha, &val);
2603 if (ret < 0)
2604 goto done_protect;
2605
0547fb37 2606 val |= (BLOCK_PROTECT_BITS << 2);
a9083016
GM		 2607 /* LOCK all sectors */
2608 ret = qla82xx_write_status_reg(ha, val);
2609 if (ret < 0)
7c3df132
SK		 2610 ql_log(ql_log_warn, vha, 0xb017,
2611 "Write status register failed.\n");
a9083016
GM		 2612
2613 if (qla82xx_write_disable_flash(ha) != 0)
7c3df132
SK		 2614 ql_log(ql_log_warn, vha, 0xb018,
2615 "Write disable failed.\n");
a9083016 2616done_protect:
d652e093 2617 qla82xx_rom_unlock(ha);
a9083016
GM		 2618 return ret;
2619}
2620
77e334d2 2621static int
a9083016
GM		 2622qla82xx_erase_sector(struct qla_hw_data *ha, int addr)
2623{
2624 int ret = 0;
7c3df132 2625 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 2626
2627 ret = ql82xx_rom_lock_d(ha);
2628 if (ret < 0) {
7c3df132
SK		 2629 ql_log(ql_log_warn, vha, 0xb019,
2630 "ROM Lock failed.\n");
a9083016
GM		 2631 return ret;
2632 }
2633
2634 qla82xx_flash_set_write_enable(ha);
2635 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
2636 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
2637 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE);
2638
2639 if (qla82xx_wait_rom_done(ha)) {
7c3df132
SK		 2640 ql_log(ql_log_warn, vha, 0xb01a,
2641 "Error waiting for rom done.\n");
a9083016
GM		 2642 ret = -1;
2643 goto done;
2644 }
2645 ret = qla82xx_flash_wait_write_finish(ha);
2646done:
d652e093 2647 qla82xx_rom_unlock(ha);
a9083016
GM		 2648 return ret;
2649}
2650
2651/*
2652 * Address and length are byte address
2653 */
2654uint8_t *
2655qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2656 uint32_t offset, uint32_t length)
2657{
2658 scsi_block_requests(vha->host);
2659 qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length);
2660 scsi_unblock_requests(vha->host);
2661 return buf;
2662}
2663
2664static int
2665qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr,
2666 uint32_t faddr, uint32_t dwords)
2667{
2668 int ret;
2669 uint32_t liter;
2670 uint32_t sec_mask, rest_addr;
2671 dma_addr_t optrom_dma;
2672 void *optrom = NULL;
2673 int page_mode = 0;
2674 struct qla_hw_data *ha = vha->hw;
2675
2676 ret = -1;
2677
2678 /* Prepare burst-capable write on supported ISPs. */
2679 if (page_mode && !(faddr & 0xfff) &&
2680 dwords > OPTROM_BURST_DWORDS) {
2681 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2682 &optrom_dma, GFP_KERNEL);
2683 if (!optrom) {
7c3df132
SK		 2684 ql_log(ql_log_warn, vha, 0xb01b,
2685 "Unable to allocate memory "
00adc9a0 2686 "for optrom burst write (%x KB).\n",
7c3df132 2687 OPTROM_BURST_SIZE / 1024);
a9083016
GM		 2688 }
2689 }
2690
2691 rest_addr = ha->fdt_block_size - 1;
2692 sec_mask = ~rest_addr;
2693
2694 ret = qla82xx_unprotect_flash(ha);
2695 if (ret) {
7c3df132
SK		 2696 ql_log(ql_log_warn, vha, 0xb01c,
2697 "Unable to unprotect flash for update.\n");
a9083016
GM		 2698 goto write_done;
2699 }
2700
2701 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) {
2702 /* Are we at the beginning of a sector? */
2703 if ((faddr & rest_addr) == 0) {
2704
2705 ret = qla82xx_erase_sector(ha, faddr);
2706 if (ret) {
7c3df132
SK		 2707 ql_log(ql_log_warn, vha, 0xb01d,
2708 "Unable to erase sector: address=%x.\n",
2709 faddr);
a9083016
GM		 2710 break;
2711 }
2712 }
2713
2714 /* Go with burst-write. */
2715 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
2716 /* Copy data to DMA'ble buffer. */
2717 memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
2718
2719 ret = qla2x00_load_ram(vha, optrom_dma,
2720 (ha->flash_data_off | faddr),
2721 OPTROM_BURST_DWORDS);
2722 if (ret != QLA_SUCCESS) {
7c3df132 2723 ql_log(ql_log_warn, vha, 0xb01e,
a9083016
GM		 2724 "Unable to burst-write optrom segment "
2725 "(%x/%x/%llx).\n", ret,
2726 (ha->flash_data_off | faddr),
2727 (unsigned long long)optrom_dma);
7c3df132 2728 ql_log(ql_log_warn, vha, 0xb01f,
a9083016
GM		 2729 "Reverting to slow-write.\n");
2730
2731 dma_free_coherent(&ha->pdev->dev,
2732 OPTROM_BURST_SIZE, optrom, optrom_dma);
2733 optrom = NULL;
2734 } else {
2735 liter += OPTROM_BURST_DWORDS - 1;
2736 faddr += OPTROM_BURST_DWORDS - 1;
2737 dwptr += OPTROM_BURST_DWORDS - 1;
2738 continue;
2739 }
2740 }
2741
2742 ret = qla82xx_write_flash_dword(ha, faddr,
2743 cpu_to_le32(*dwptr));
2744 if (ret) {
7c3df132
SK		 2745 ql_dbg(ql_dbg_p3p, vha, 0xb020,
2746 "Unable to program flash address=%x data=%x.\n",
2747 faddr, *dwptr);
a9083016
GM		 2748 break;
2749 }
2750 }
2751
2752 ret = qla82xx_protect_flash(ha);
2753 if (ret)
7c3df132 2754 ql_log(ql_log_warn, vha, 0xb021,
a9083016
GM		 2755 "Unable to protect flash after update.\n");
2756write_done:
2757 if (optrom)
2758 dma_free_coherent(&ha->pdev->dev,
2759 OPTROM_BURST_SIZE, optrom, optrom_dma);
2760 return ret;
2761}
2762
2763int
2764qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2765 uint32_t offset, uint32_t length)
2766{
2767 int rval;
2768
2769 /* Suspend HBA. */
2770 scsi_block_requests(vha->host);
2771 rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset,
2772 length >> 2);
2773 scsi_unblock_requests(vha->host);
2774
2775 /* Convert return ISP82xx to generic */
2776 if (rval)
2777 rval = QLA_FUNCTION_FAILED;
2778 else
2779 rval = QLA_SUCCESS;
2780 return rval;
2781}
2782
2783void
5162cf0c 2784qla82xx_start_iocbs(scsi_qla_host_t *vha)
a9083016 2785{
5162cf0c 2786 struct qla_hw_data *ha = vha->hw;
a9083016
GM		 2787 struct req_que *req = ha->req_q_map[0];
2788 struct device_reg_82xx __iomem *reg;
2789 uint32_t dbval;
2790
2791 /* Adjust ring index. */
2792 req->ring_index++;
2793 if (req->ring_index == req->length) {
2794 req->ring_index = 0;
2795 req->ring_ptr = req->ring;
2796 } else
2797 req->ring_ptr++;
2798
2799 reg = &ha->iobase->isp82;
2800 dbval = 0x04 | (ha->portnum << 5);
2801
2802 dbval = dbval | (req->id << 8) | (req->ring_index << 16);
6907869d
GM		 2803 if (ql2xdbwr)
2804 qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval);
2805 else {
2806 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval);
a9083016 2807 wmb();
fa492630 2808 while (RD_REG_DWORD((void __iomem *)ha->nxdb_rd_ptr) != dbval) {
6907869d
GM		 2809 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr,
2810 dbval);
2811 wmb();
2812 }
a9083016
GM		 2813 }
2814}
2815
fa492630
SK		 2816static void
2817qla82xx_rom_lock_recovery(struct qla_hw_data *ha)
e6a4202a 2818{
7c3df132 2819 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
4babb90e 2820 uint32_t lock_owner = 0;
7c3df132 2821
4babb90e
HP		 2822 if (qla82xx_rom_lock(ha)) {
2823 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
e6a4202a 2824 /* Someone else is holding the lock. */
7c3df132 2825 ql_log(ql_log_info, vha, 0xb022,
4babb90e
HP		 2826 "Resetting rom_lock, Lock Owner %u.\n", lock_owner);
2827 }
e6a4202a
SS		 2828 /*
2829 * Either we got the lock, or someone
2830 * else died while holding it.
2831 * In either case, unlock.
2832 */
d652e093 2833 qla82xx_rom_unlock(ha);
e6a4202a
SS		 2834}
2835
a9083016
GM		 2836/*
2837 * qla82xx_device_bootstrap
2838 * Initialize device, set DEV_READY, start fw
2839 *
2840 * Note:
2841 * IDC lock must be held upon entry
2842 *
2843 * Return:
2844 * Success : 0
2845 * Failed : 1
2846 */
2847static int
2848qla82xx_device_bootstrap(scsi_qla_host_t *vha)
2849{
e6a4202a
SS		 2850 int rval = QLA_SUCCESS;
2851 int i, timeout;
a9083016
GM		 2852 uint32_t old_count, count;
2853 struct qla_hw_data *ha = vha->hw;
e6a4202a 2854 int need_reset = 0, peg_stuck = 1;
a9083016 2855
e6a4202a 2856 need_reset = qla82xx_need_reset(ha);
a9083016
GM		 2857
2858 old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2859
2860 for (i = 0; i < 10; i++) {
2861 timeout = msleep_interruptible(200);
2862 if (timeout) {
2863 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 2864 QLA8XXX_DEV_FAILED);
a9083016
GM		 2865 return QLA_FUNCTION_FAILED;
2866 }
2867
2868 count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2869 if (count != old_count)
e6a4202a
SS		 2870 peg_stuck = 0;
2871 }
2872
2873 if (need_reset) {
2874 /* We are trying to perform a recovery here. */
2875 if (peg_stuck)
2876 qla82xx_rom_lock_recovery(ha);
2877 goto dev_initialize;
2878 } else {
2879 /* Start of day for this ha context. */
2880 if (peg_stuck) {
2881 /* Either we are the first or recovery in progress. */
2882 qla82xx_rom_lock_recovery(ha);
2883 goto dev_initialize;
2884 } else
2885 /* Firmware already running. */
a9083016
GM		 2886 goto dev_ready;
2887 }
2888
e6a4202a
SS		 2889 return rval;
2890
a9083016
GM		 2891dev_initialize:
2892 /* set to DEV_INITIALIZING */
7c3df132
SK		 2893 ql_log(ql_log_info, vha, 0x009e,
2894 "HW State: INITIALIZING.\n");
7d613ac6 2895 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
a9083016
GM		 2896
2897 qla82xx_idc_unlock(ha);
2898 rval = qla82xx_start_firmware(vha);
2899 qla82xx_idc_lock(ha);
2900
2901 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2902 ql_log(ql_log_fatal, vha, 0x00ad,
2903 "HW State: FAILED.\n");
a9083016 2904 qla82xx_clear_drv_active(ha);
7d613ac6 2905 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_FAILED);
a9083016
GM		 2906 return rval;
2907 }
2908
2909dev_ready:
7c3df132
SK		 2910 ql_log(ql_log_info, vha, 0x00ae,
2911 "HW State: READY.\n");
7d613ac6 2912 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_READY);
a9083016
GM		 2913
2914 return QLA_SUCCESS;
2915}
2916
579d12b5
SK		 2917/*
2918* qla82xx_need_qsnt_handler
2919* Code to start quiescence sequence
2920*
2921* Note:
2922* IDC lock must be held upon entry
2923*
2924* Return: void
2925*/
2926
2927static void
2928qla82xx_need_qsnt_handler(scsi_qla_host_t *vha)
2929{
2930 struct qla_hw_data *ha = vha->hw;
2931 uint32_t dev_state, drv_state, drv_active;
2932 unsigned long reset_timeout;
2933
2934 if (vha->flags.online) {
2935 /*Block any further I/O and wait for pending cmnds to complete*/
8fcd6b8b 2936 qla2x00_quiesce_io(vha);
579d12b5
SK		 2937 }
2938
2939 /* Set the quiescence ready bit */
2940 qla82xx_set_qsnt_ready(ha);
2941
2942 /*wait for 30 secs for other functions to ack */
2943 reset_timeout = jiffies + (30 * HZ);
2944
2945 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2946 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2947 /* Its 2 that is written when qsnt is acked, moving one bit */
2948 drv_active = drv_active << 0x01;
2949
2950 while (drv_state != drv_active) {
2951
2952 if (time_after_eq(jiffies, reset_timeout)) {
2953 /* quiescence timeout, other functions didn't ack
2954 * changing the state to DEV_READY
2955 */
7c3df132 2956 ql_log(ql_log_info, vha, 0xb023,
5f28d2d7
SK		 2957 "%s : QUIESCENT TIMEOUT DRV_ACTIVE:%d "
2958 "DRV_STATE:%d.\n", QLA2XXX_DRIVER_NAME,
7c3df132 2959 drv_active, drv_state);
579d12b5 2960 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 2961 QLA8XXX_DEV_READY);
7c3df132
SK		 2962 ql_log(ql_log_info, vha, 0xb025,
2963 "HW State: DEV_READY.\n");
579d12b5
SK		 2964 qla82xx_idc_unlock(ha);
2965 qla2x00_perform_loop_resync(vha);
2966 qla82xx_idc_lock(ha);
2967
2968 qla82xx_clear_qsnt_ready(vha);
2969 return;
2970 }
2971
2972 qla82xx_idc_unlock(ha);
2973 msleep(1000);
2974 qla82xx_idc_lock(ha);
2975
2976 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2977 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2978 drv_active = drv_active << 0x01;
2979 }
2980 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2981 /* everyone acked so set the state to DEV_QUIESCENCE */
7d613ac6 2982 if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
7c3df132
SK		 2983 ql_log(ql_log_info, vha, 0xb026,
2984 "HW State: DEV_QUIESCENT.\n");
7d613ac6 2985 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_QUIESCENT);
579d12b5
SK		 2986 }
2987}
2988
2989/*
2990* qla82xx_wait_for_state_change
2991* Wait for device state to change from given current state
2992*
2993* Note:
2994* IDC lock must not be held upon entry
2995*
2996* Return:
2997* Changed device state.
2998*/
2999uint32_t
3000qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state)
3001{
3002 struct qla_hw_data *ha = vha->hw;
3003 uint32_t dev_state;
3004
3005 do {
3006 msleep(1000);
3007 qla82xx_idc_lock(ha);
3008 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3009 qla82xx_idc_unlock(ha);
3010 } while (dev_state == curr_state);
3011
3012 return dev_state;
3013}
3014
7d613ac6
SV		 3015void
3016qla8xxx_dev_failed_handler(scsi_qla_host_t *vha)
a9083016
GM		 3017{
3018 struct qla_hw_data *ha = vha->hw;
3019
3020 /* Disable the board */
7c3df132
SK		 3021 ql_log(ql_log_fatal, vha, 0x00b8,
3022 "Disabling the board.\n");
a9083016 3023
1459c0e1
SK		 3024 if (IS_QLA82XX(ha)) {
3025 qla82xx_clear_drv_active(ha);
3026 qla82xx_idc_unlock(ha);
7ec0effd 3027 } else if (IS_QLA8044(ha)) {
c41afc9a 3028 qla8044_clear_drv_active(ha);
7ec0effd 3029 qla8044_idc_unlock(ha);
1459c0e1 3030 }
b963752f 3031
a9083016
GM		 3032 /* Set DEV_FAILED flag to disable timer */
3033 vha->device_flags |= DFLG_DEV_FAILED;
3034 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3035 qla2x00_mark_all_devices_lost(vha, 0);
3036 vha->flags.online = 0;
3037 vha->flags.init_done = 0;
3038}
3039
3040/*
3041 * qla82xx_need_reset_handler
3042 * Code to start reset sequence
3043 *
3044 * Note:
3045 * IDC lock must be held upon entry
3046 *
3047 * Return:
3048 * Success : 0
3049 * Failed : 1
3050 */
3051static void
3052qla82xx_need_reset_handler(scsi_qla_host_t *vha)
3053{
e5fdae55
CD		 3054 uint32_t dev_state, drv_state, drv_active;
3055 uint32_t active_mask = 0;
a9083016
GM		 3056 unsigned long reset_timeout;
3057 struct qla_hw_data *ha = vha->hw;
3058 struct req_que *req = ha->req_q_map[0];
3059
3060 if (vha->flags.online) {
3061 qla82xx_idc_unlock(ha);
3062 qla2x00_abort_isp_cleanup(vha);
3063 ha->isp_ops->get_flash_version(vha, req->ring);
3064 ha->isp_ops->nvram_config(vha);
3065 qla82xx_idc_lock(ha);
3066 }
3067
08de2844 3068 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7d613ac6 3069 if (!ha->flags.nic_core_reset_owner) {
08de2844
GM		 3070 ql_dbg(ql_dbg_p3p, vha, 0xb028,
3071 "reset_acknowledged by 0x%x\n", ha->portnum);
3072 qla82xx_set_rst_ready(ha);
3073 } else {
3074 active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
3075 drv_active &= active_mask;
3076 ql_dbg(ql_dbg_p3p, vha, 0xb029,
3077 "active_mask: 0x%08x\n", active_mask);
3078 }
a9083016
GM		 3079
3080 /* wait for 10 seconds for reset ack from all functions */
7d613ac6 3081 reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
a9083016
GM		 3082
3083 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3084 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
08de2844 3085 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
a9083016 3086
08de2844
GM		 3087 ql_dbg(ql_dbg_p3p, vha, 0xb02a,
3088 "drv_state: 0x%08x, drv_active: 0x%08x, "
3089 "dev_state: 0x%08x, active_mask: 0x%08x\n",
3090 drv_state, drv_active, dev_state, active_mask);
3091
3092 while (drv_state != drv_active &&
7d613ac6 3093 dev_state != QLA8XXX_DEV_INITIALIZING) {
a9083016 3094 if (time_after_eq(jiffies, reset_timeout)) {
7c3df132
SK		 3095 ql_log(ql_log_warn, vha, 0x00b5,
3096 "Reset timeout.\n");
a9083016
GM		 3097 break;
3098 }
3099 qla82xx_idc_unlock(ha);
3100 msleep(1000);
3101 qla82xx_idc_lock(ha);
3102 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3103 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7d613ac6 3104 if (ha->flags.nic_core_reset_owner)
08de2844
GM		 3105 drv_active &= active_mask;
3106 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
a9083016
GM		 3107 }
3108
08de2844
GM		 3109 ql_dbg(ql_dbg_p3p, vha, 0xb02b,
3110 "drv_state: 0x%08x, drv_active: 0x%08x, "
3111 "dev_state: 0x%08x, active_mask: 0x%08x\n",
3112 drv_state, drv_active, dev_state, active_mask);
3113
7c3df132
SK		 3114 ql_log(ql_log_info, vha, 0x00b6,
3115 "Device state is 0x%x = %s.\n",
3116 dev_state,
08de2844 3117 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
f1af6208 3118
a9083016 3119 /* Force to DEV_COLD unless someone else is starting a reset */
7d613ac6
SV		 3120 if (dev_state != QLA8XXX_DEV_INITIALIZING &&
3121 dev_state != QLA8XXX_DEV_COLD) {
7c3df132
SK		 3122 ql_log(ql_log_info, vha, 0x00b7,
3123 "HW State: COLD/RE-INIT.\n");
7d613ac6 3124 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD);
f4e1648a 3125 qla82xx_set_rst_ready(ha);
08de2844
GM		 3126 if (ql2xmdenable) {
3127 if (qla82xx_md_collect(vha))
3128 ql_log(ql_log_warn, vha, 0xb02c,
b6d0d9d5 3129 "Minidump not collected.\n");
08de2844
GM		 3130 } else
3131 ql_log(ql_log_warn, vha, 0xb04f,
3132 "Minidump disabled.\n");
a9083016
GM		 3133 }
3134}
3135
3173167f 3136int
08de2844
GM		 3137qla82xx_check_md_needed(scsi_qla_host_t *vha)
3138{
3139 struct qla_hw_data *ha = vha->hw;
3140 uint16_t fw_major_version, fw_minor_version, fw_subminor_version;
3173167f
GM		 3141 int rval = QLA_SUCCESS;
3142
3143 fw_major_version = ha->fw_major_version;
3144 fw_minor_version = ha->fw_minor_version;
3145 fw_subminor_version = ha->fw_subminor_version;
3146
6246b8a1 3147 rval = qla2x00_get_fw_version(vha);
3173167f
GM		 3148 if (rval != QLA_SUCCESS)
3149 return rval;
3150
3151 if (ql2xmdenable) {
3152 if (!ha->fw_dumped) {
edaa5c74 3153 if ((fw_major_version != ha->fw_major_version ||
3173167f 3154 fw_minor_version != ha->fw_minor_version ||
edaa5c74
SK		 3155 fw_subminor_version != ha->fw_subminor_version) ||
3156 (ha->prev_minidump_failed)) {
7ec0effd 3157 ql_dbg(ql_dbg_p3p, vha, 0xb02d,
edaa5c74 3158 "Firmware version differs Previous version: %d:%d:%d - New version: %d:%d:%d, prev_minidump_failed: %d.\n",
9bc3bf27
GM		 3159 fw_major_version, fw_minor_version,
3160 fw_subminor_version,
3173167f
GM		 3161 ha->fw_major_version,
3162 ha->fw_minor_version,
edaa5c74
SK		 3163 ha->fw_subminor_version,
3164 ha->prev_minidump_failed);
3173167f
GM		 3165 /* Release MiniDump resources */
3166 qla82xx_md_free(vha);
3167 /* ALlocate MiniDump resources */
3168 qla82xx_md_prep(vha);
2e264269
GM		 3169 }
3170 } else
3171 ql_log(ql_log_info, vha, 0xb02e,
3172 "Firmware dump available to retrieve\n");
3173167f
GM		 3173 }
3174 return rval;
08de2844
GM		 3175}
3176
3177
fa492630 3178static int
a9083016
GM		 3179qla82xx_check_fw_alive(scsi_qla_host_t *vha)
3180{
7190575f
GM		 3181 uint32_t fw_heartbeat_counter;
3182 int status = 0;
a9083016 3183
7190575f
GM		 3184 fw_heartbeat_counter = qla82xx_rd_32(vha->hw,
3185 QLA82XX_PEG_ALIVE_COUNTER);
a5b36321 3186 /* all 0xff, assume AER/EEH in progress, ignore */
7c3df132
SK		 3187 if (fw_heartbeat_counter == 0xffffffff) {
3188 ql_dbg(ql_dbg_timer, vha, 0x6003,
3189 "FW heartbeat counter is 0xffffffff, "
3190 "returning status=%d.\n", status);
7190575f 3191 return status;
7c3df132 3192 }
a9083016
GM		 3193 if (vha->fw_heartbeat_counter == fw_heartbeat_counter) {
3194 vha->seconds_since_last_heartbeat++;
3195 /* FW not alive after 2 seconds */
3196 if (vha->seconds_since_last_heartbeat == 2) {
3197 vha->seconds_since_last_heartbeat = 0;
7190575f 3198 status = 1;
a9083016 3199 }
efa786cc
LC		 3200 } else
3201 vha->seconds_since_last_heartbeat = 0;
a9083016 3202 vha->fw_heartbeat_counter = fw_heartbeat_counter;
7c3df132
SK		 3203 if (status)
3204 ql_dbg(ql_dbg_timer, vha, 0x6004,
3205 "Returning status=%d.\n", status);
7190575f 3206 return status;
a9083016
GM		 3207}
3208
3209/*
3210 * qla82xx_device_state_handler
3211 * Main state handler
3212 *
3213 * Note:
3214 * IDC lock must be held upon entry
3215 *
3216 * Return:
3217 * Success : 0
3218 * Failed : 1
3219 */
3220int
3221qla82xx_device_state_handler(scsi_qla_host_t *vha)
3222{
3223 uint32_t dev_state;
92dbf273 3224 uint32_t old_dev_state;
a9083016
GM		 3225 int rval = QLA_SUCCESS;
3226 unsigned long dev_init_timeout;
3227 struct qla_hw_data *ha = vha->hw;
92dbf273 3228 int loopcount = 0;
a9083016
GM		 3229
3230 qla82xx_idc_lock(ha);
0251ce8c 3231 if (!vha->flags.init_done) {
a9083016 3232 qla82xx_set_drv_active(vha);
0251ce8c
SK		 3233 qla82xx_set_idc_version(vha);
3234 }
a9083016 3235
f1af6208 3236 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
92dbf273 3237 old_dev_state = dev_state;
7c3df132
SK		 3238 ql_log(ql_log_info, vha, 0x009b,
3239 "Device state is 0x%x = %s.\n",
3240 dev_state,
08de2844 3241 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
a9083016
GM		 3242
3243 /* wait for 30 seconds for device to go ready */
7d613ac6 3244 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
a9083016
GM		 3245
3246 while (1) {
3247
3248 if (time_after_eq(jiffies, dev_init_timeout)) {
7c3df132
SK		 3249 ql_log(ql_log_fatal, vha, 0x009c,
3250 "Device init failed.\n");
a9083016
GM		 3251 rval = QLA_FUNCTION_FAILED;
3252 break;
3253 }
3254 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
92dbf273
GM		 3255 if (old_dev_state != dev_state) {
3256 loopcount = 0;
3257 old_dev_state = dev_state;
3258 }
3259 if (loopcount < 5) {
7c3df132
SK		 3260 ql_log(ql_log_info, vha, 0x009d,
3261 "Device state is 0x%x = %s.\n",
3262 dev_state,
08de2844 3263 dev_state < MAX_STATES ? qdev_state(dev_state) :
7c3df132 3264 "Unknown");
92dbf273 3265 }
f1af6208 3266
a9083016 3267 switch (dev_state) {
7d613ac6
SV		 3268 case QLA8XXX_DEV_READY:
3269 ha->flags.nic_core_reset_owner = 0;
7916bb90 3270 goto rel_lock;
7d613ac6 3271 case QLA8XXX_DEV_COLD:
a9083016 3272 rval = qla82xx_device_bootstrap(vha);
08de2844 3273 break;
7d613ac6 3274 case QLA8XXX_DEV_INITIALIZING:
a9083016
GM		 3275 qla82xx_idc_unlock(ha);
3276 msleep(1000);
3277 qla82xx_idc_lock(ha);
3278 break;
7d613ac6 3279 case QLA8XXX_DEV_NEED_RESET:
c8582ad9
SK		 3280 if (!ql2xdontresethba)
3281 qla82xx_need_reset_handler(vha);
3282 else {
3283 qla82xx_idc_unlock(ha);
3284 msleep(1000);
3285 qla82xx_idc_lock(ha);
3286 }
0060ddf8 3287 dev_init_timeout = jiffies +
7d613ac6 3288 (ha->fcoe_dev_init_timeout * HZ);
a9083016 3289 break;
7d613ac6 3290 case QLA8XXX_DEV_NEED_QUIESCENT:
579d12b5
SK		 3291 qla82xx_need_qsnt_handler(vha);
3292 /* Reset timeout value after quiescence handler */
7d613ac6 3293 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\
579d12b5
SK		 3294 * HZ);
3295 break;
7d613ac6 3296 case QLA8XXX_DEV_QUIESCENT:
579d12b5
SK		 3297 /* Owner will exit and other will wait for the state
3298 * to get changed
3299 */
3300 if (ha->flags.quiesce_owner)
7916bb90 3301 goto rel_lock;
579d12b5 3302
a9083016
GM		 3303 qla82xx_idc_unlock(ha);
3304 msleep(1000);
3305 qla82xx_idc_lock(ha);
579d12b5
SK		 3306
3307 /* Reset timeout value after quiescence handler */
7d613ac6 3308 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\
579d12b5 3309 * HZ);
a9083016 3310 break;
7d613ac6
SV		 3311 case QLA8XXX_DEV_FAILED:
3312 qla8xxx_dev_failed_handler(vha);
a9083016
GM		 3313 rval = QLA_FUNCTION_FAILED;
3314 goto exit;
3315 default:
3316 qla82xx_idc_unlock(ha);
3317 msleep(1000);
3318 qla82xx_idc_lock(ha);
3319 }
92dbf273 3320 loopcount++;
a9083016 3321 }
7916bb90 3322rel_lock:
a9083016 3323 qla82xx_idc_unlock(ha);
7916bb90 3324exit:
a9083016
GM		 3325 return rval;
3326}
3327
5988aeb2
GM		 3328static int qla82xx_check_temp(scsi_qla_host_t *vha)
3329{
3330 uint32_t temp, temp_state, temp_val;
3331 struct qla_hw_data *ha = vha->hw;
3332
3333 temp = qla82xx_rd_32(ha, CRB_TEMP_STATE);
3334 temp_state = qla82xx_get_temp_state(temp);
3335 temp_val = qla82xx_get_temp_val(temp);
3336
3337 if (temp_state == QLA82XX_TEMP_PANIC) {
3338 ql_log(ql_log_warn, vha, 0x600e,
3339 "Device temperature %d degrees C exceeds "
3340 " maximum allowed. Hardware has been shut down.\n",
3341 temp_val);
3342 return 1;
3343 } else if (temp_state == QLA82XX_TEMP_WARN) {
3344 ql_log(ql_log_warn, vha, 0x600f,
3345 "Device temperature %d degrees C exceeds "
3346 "operating range. Immediate action needed.\n",
3347 temp_val);
3348 }
3349 return 0;
3350}
3351
1ae47cf3
JC		 3352int qla82xx_read_temperature(scsi_qla_host_t *vha)
3353{
3354 uint32_t temp;
3355
3356 temp = qla82xx_rd_32(vha->hw, CRB_TEMP_STATE);
3357 return qla82xx_get_temp_val(temp);
3358}
3359
c8f6544e
CD		 3360void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha)
3361{
3362 struct qla_hw_data *ha = vha->hw;
3363
3364 if (ha->flags.mbox_busy) {
3365 ha->flags.mbox_int = 1;
8937f2f1 3366 ha->flags.mbox_busy = 0;
c8f6544e
CD		 3367 ql_log(ql_log_warn, vha, 0x6010,
3368 "Doing premature completion of mbx command.\n");
36439832 3369 if (test_and_clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags))
c8f6544e
CD		 3370 complete(&ha->mbx_intr_comp);
3371 }
3372}
3373
a9083016
GM		 3374void qla82xx_watchdog(scsi_qla_host_t *vha)
3375{
7190575f 3376 uint32_t dev_state, halt_status;
a9083016
GM		 3377 struct qla_hw_data *ha = vha->hw;
3378
a9083016 3379 /* don't poll if reset is going on */
7d613ac6 3380 if (!ha->flags.nic_core_reset_hdlr_active) {
7190575f 3381 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
5988aeb2
GM		 3382 if (qla82xx_check_temp(vha)) {
3383 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
3384 ha->flags.isp82xx_fw_hung = 1;
3385 qla82xx_clear_pending_mbx(vha);
7d613ac6 3386 } else if (dev_state == QLA8XXX_DEV_NEED_RESET &&
7190575f 3387 !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) {
7c3df132
SK		 3388 ql_log(ql_log_warn, vha, 0x6001,
3389 "Adapter reset needed.\n");
a9083016 3390 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
7d613ac6 3391 } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT &&
579d12b5 3392 !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) {
7c3df132
SK		 3393 ql_log(ql_log_warn, vha, 0x6002,
3394 "Quiescent needed.\n");
579d12b5 3395 set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
7d613ac6 3396 } else if (dev_state == QLA8XXX_DEV_FAILED &&
7916bb90
CD		 3397 !test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) &&
3398 vha->flags.online == 1) {
3399 ql_log(ql_log_warn, vha, 0xb055,
3400 "Adapter state is failed. Offlining.\n");
3401 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
3402 ha->flags.isp82xx_fw_hung = 1;
3403 qla82xx_clear_pending_mbx(vha);
a9083016 3404 } else {
7190575f 3405 if (qla82xx_check_fw_alive(vha)) {
63154916
GM		 3406 ql_dbg(ql_dbg_timer, vha, 0x6011,
3407 "disabling pause transmit on port 0 & 1.\n");
3408 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
3409 CRB_NIU_XG_PAUSE_CTL_P0|CRB_NIU_XG_PAUSE_CTL_P1);
7190575f
GM		 3410 halt_status = qla82xx_rd_32(ha,
3411 QLA82XX_PEG_HALT_STATUS1);
63154916 3412 ql_log(ql_log_info, vha, 0x6005,
7c3df132
SK		 3413 "dumping hw/fw registers:.\n "
3414 " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n "
3415 " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n "
3416 " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n "
3417 " PEG_NET_4_PC: 0x%x.\n", halt_status,
0e8edb03
GM		 3418 qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2),
3419 qla82xx_rd_32(ha,
3420 QLA82XX_CRB_PEG_NET_0 + 0x3c),
3421 qla82xx_rd_32(ha,
3422 QLA82XX_CRB_PEG_NET_1 + 0x3c),
3423 qla82xx_rd_32(ha,
3424 QLA82XX_CRB_PEG_NET_2 + 0x3c),
3425 qla82xx_rd_32(ha,
3426 QLA82XX_CRB_PEG_NET_3 + 0x3c),
3427 qla82xx_rd_32(ha,
3428 QLA82XX_CRB_PEG_NET_4 + 0x3c));
2cc97965 3429 if (((halt_status & 0x1fffff00) >> 8) == 0x67)
10a340e6
CD		 3430 ql_log(ql_log_warn, vha, 0xb052,
3431 "Firmware aborted with "
3432 "error code 0x00006700. Device is "
3433 "being reset.\n");
7190575f
GM		 3434 if (halt_status & HALT_STATUS_UNRECOVERABLE) {
3435 set_bit(ISP_UNRECOVERABLE,
3436 &vha->dpc_flags);
3437 } else {
7c3df132
SK		 3438 ql_log(ql_log_info, vha, 0x6006,
3439 "Detect abort needed.\n");
7190575f
GM		 3440 set_bit(ISP_ABORT_NEEDED,
3441 &vha->dpc_flags);
3442 }
7190575f 3443 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 3444 ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n");
3445 qla82xx_clear_pending_mbx(vha);
7190575f 3446 }
a9083016
GM		 3447 }
3448 }
3449}
3450
3451int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
3452{
7ec0effd
AD		 3453 int rval = -1;
3454 struct qla_hw_data *ha = vha->hw;
3455
3456 if (IS_QLA82XX(ha))
3457 rval = qla82xx_device_state_handler(vha);
3458 else if (IS_QLA8044(ha)) {
3459 qla8044_idc_lock(ha);
3460 /* Decide the reset ownership */
3461 qla83xx_reset_ownership(vha);
3462 qla8044_idc_unlock(ha);
3463 rval = qla8044_device_state_handler(vha);
3464 }
a9083016
GM		 3465 return rval;
3466}
3467
08de2844
GM		 3468void
3469qla82xx_set_reset_owner(scsi_qla_host_t *vha)
3470{
3471 struct qla_hw_data *ha = vha->hw;
7ec0effd
AD		 3472 uint32_t dev_state = 0;
3473
3474 if (IS_QLA82XX(ha))
3475 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3476 else if (IS_QLA8044(ha))
3477 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
08de2844 3478
7d613ac6 3479 if (dev_state == QLA8XXX_DEV_READY) {
08de2844
GM		 3480 ql_log(ql_log_info, vha, 0xb02f,
3481 "HW State: NEED RESET\n");
7ec0effd
AD		 3482 if (IS_QLA82XX(ha)) {
3483 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3484 QLA8XXX_DEV_NEED_RESET);
3485 ha->flags.nic_core_reset_owner = 1;
3486 ql_dbg(ql_dbg_p3p, vha, 0xb030,
3487 "reset_owner is 0x%x\n", ha->portnum);
3488 } else if (IS_QLA8044(ha))
3489 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
3490 QLA8XXX_DEV_NEED_RESET);
08de2844
GM		 3491 } else
3492 ql_log(ql_log_info, vha, 0xb031,
3493 "Device state is 0x%x = %s.\n",
3494 dev_state,
3495 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
3496}
3497
a9083016
GM		 3498/*
3499 * qla82xx_abort_isp
3500 * Resets ISP and aborts all outstanding commands.
3501 *
3502 * Input:
3503 * ha = adapter block pointer.
3504 *
3505 * Returns:
3506 * 0 = success
3507 */
3508int
3509qla82xx_abort_isp(scsi_qla_host_t *vha)
3510{
7ec0effd 3511 int rval = -1;
a9083016 3512 struct qla_hw_data *ha = vha->hw;
a9083016
GM		 3513
3514 if (vha->device_flags & DFLG_DEV_FAILED) {
7c3df132
SK		 3515 ql_log(ql_log_warn, vha, 0x8024,
3516 "Device in failed state, exiting.\n");
a9083016
GM		 3517 return QLA_SUCCESS;
3518 }
7d613ac6 3519 ha->flags.nic_core_reset_hdlr_active = 1;
a9083016
GM		 3520
3521 qla82xx_idc_lock(ha);
08de2844 3522 qla82xx_set_reset_owner(vha);
a9083016
GM		 3523 qla82xx_idc_unlock(ha);
3524
7ec0effd
AD		 3525 if (IS_QLA82XX(ha))
3526 rval = qla82xx_device_state_handler(vha);
3527 else if (IS_QLA8044(ha)) {
3528 qla8044_idc_lock(ha);
3529 /* Decide the reset ownership */
3530 qla83xx_reset_ownership(vha);
3531 qla8044_idc_unlock(ha);
3532 rval = qla8044_device_state_handler(vha);
3533 }
a9083016
GM		 3534
3535 qla82xx_idc_lock(ha);
3536 qla82xx_clear_rst_ready(ha);
3537 qla82xx_idc_unlock(ha);
3538
cdbb0a4f 3539 if (rval == QLA_SUCCESS) {
7190575f 3540 ha->flags.isp82xx_fw_hung = 0;
7d613ac6 3541 ha->flags.nic_core_reset_hdlr_active = 0;
a9083016 3542 qla82xx_restart_isp(vha);
cdbb0a4f 3543 }
f1af6208
GM		 3544
3545 if (rval) {
3546 vha->flags.online = 1;
3547 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
3548 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 3549 ql_log(ql_log_warn, vha, 0x8027,
3550 "ISP error recover failed - board "
3551 "disabled.\n");
f1af6208
GM		 3552 /*
3553 * The next call disables the board
3554 * completely.
3555 */
3556 ha->isp_ops->reset_adapter(vha);
3557 vha->flags.online = 0;
3558 clear_bit(ISP_ABORT_RETRY,
3559 &vha->dpc_flags);
3560 rval = QLA_SUCCESS;
3561 } else { /* schedule another ISP abort */
3562 ha->isp_abort_cnt--;
7c3df132
SK		 3563 ql_log(ql_log_warn, vha, 0x8036,
3564 "ISP abort - retry remaining %d.\n",
3565 ha->isp_abort_cnt);
f1af6208
GM		 3566 rval = QLA_FUNCTION_FAILED;
3567 }
3568 } else {
3569 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 3570 ql_dbg(ql_dbg_taskm, vha, 0x8029,
3571 "ISP error recovery - retrying (%d) more times.\n",
3572 ha->isp_abort_cnt);
f1af6208
GM		 3573 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
3574 rval = QLA_FUNCTION_FAILED;
3575 }
3576 }
a9083016
GM		 3577 return rval;
3578}
3579
3580/*
3581 * qla82xx_fcoe_ctx_reset
3582 * Perform a quick reset and aborts all outstanding commands.
3583 * This will only perform an FCoE context reset and avoids a full blown
3584 * chip reset.
3585 *
3586 * Input:
3587 * ha = adapter block pointer.
3588 * is_reset_path = flag for identifying the reset path.
3589 *
3590 * Returns:
3591 * 0 = success
3592 */
3593int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha)
3594{
3595 int rval = QLA_FUNCTION_FAILED;
3596
3597 if (vha->flags.online) {
3598 /* Abort all outstanding commands, so as to be requeued later */
3599 qla2x00_abort_isp_cleanup(vha);
3600 }
3601
3602 /* Stop currently executing firmware.
3603 * This will destroy existing FCoE context at the F/W end.
3604 */
3605 qla2x00_try_to_stop_firmware(vha);
3606
3607 /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */
3608 rval = qla82xx_restart_isp(vha);
3609
3610 return rval;
3611}
3612
3613/*
3614 * qla2x00_wait_for_fcoe_ctx_reset
3615 * Wait till the FCoE context is reset.
3616 *
3617 * Note:
3618 * Does context switching here.
3619 * Release SPIN_LOCK (if any) before calling this routine.
3620 *
3621 * Return:
3622 * Success (fcoe_ctx reset is done) : 0
3623 * Failed (fcoe_ctx reset not completed within max loop timout ) : 1
3624 */
3625int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha)
3626{
3627 int status = QLA_FUNCTION_FAILED;
3628 unsigned long wait_reset;
3629
3630 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
3631 while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
3632 test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
3633 && time_before(jiffies, wait_reset)) {
3634
3635 set_current_state(TASK_UNINTERRUPTIBLE);
3636 schedule_timeout(HZ);
3637
3638 if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) &&
3639 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) {
3640 status = QLA_SUCCESS;
3641 break;
3642 }
3643 }
7c3df132 3644 ql_dbg(ql_dbg_p3p, vha, 0xb027,
d8424f68 3645 "%s: status=%d.\n", __func__, status);
a9083016
GM		 3646
3647 return status;
3648}
7190575f
GM		 3649
3650void
3651qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha)
3652{
7ec0effd 3653 int i, fw_state = 0;
7190575f
GM		 3654 unsigned long flags;
3655 struct qla_hw_data *ha = vha->hw;
3656
3657 /* Check if 82XX firmware is alive or not
3658 * We may have arrived here from NEED_RESET
3659 * detection only
3660 */
3661 if (!ha->flags.isp82xx_fw_hung) {
3662 for (i = 0; i < 2; i++) {
3663 msleep(1000);
7ec0effd
AD		 3664 if (IS_QLA82XX(ha))
3665 fw_state = qla82xx_check_fw_alive(vha);
3666 else if (IS_QLA8044(ha))
3667 fw_state = qla8044_check_fw_alive(vha);
3668 if (fw_state) {
7190575f 3669 ha->flags.isp82xx_fw_hung = 1;
c8f6544e 3670 qla82xx_clear_pending_mbx(vha);
7190575f
GM		 3671 break;
3672 }
3673 }
3674 }
7c3df132
SK		 3675 ql_dbg(ql_dbg_init, vha, 0x00b0,
3676 "Entered %s fw_hung=%d.\n",
3677 __func__, ha->flags.isp82xx_fw_hung);
7190575f
GM		 3678
3679 /* Abort all commands gracefully if fw NOT hung */
3680 if (!ha->flags.isp82xx_fw_hung) {
3681 int cnt, que;
3682 srb_t *sp;
3683 struct req_que *req;
3684
3685 spin_lock_irqsave(&ha->hardware_lock, flags);
3686 for (que = 0; que < ha->max_req_queues; que++) {
3687 req = ha->req_q_map[que];
3688 if (!req)
3689 continue;
8d93f550 3690 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
7190575f
GM		 3691 sp = req->outstanding_cmds[cnt];
3692 if (sp) {
af13b700
GM		 3693 if ((!sp->u.scmd.ctx ||
3694 (sp->flags &
3695 SRB_FCP_CMND_DMA_VALID)) &&
3696 !ha->flags.isp82xx_fw_hung) {
7190575f
GM		 3697 spin_unlock_irqrestore(
3698 &ha->hardware_lock, flags);
3699 if (ha->isp_ops->abort_command(sp)) {
7c3df132
SK		 3700 ql_log(ql_log_info, vha,
3701 0x00b1,
3702 "mbx abort failed.\n");
7190575f 3703 } else {
7c3df132
SK		 3704 ql_log(ql_log_info, vha,
3705 0x00b2,
3706 "mbx abort success.\n");
7190575f
GM		 3707 }
3708 spin_lock_irqsave(&ha->hardware_lock, flags);
3709 }
3710 }
3711 }
3712 }
3713 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3714
3715 /* Wait for pending cmds (physical and virtual) to complete */
3716 if (!qla2x00_eh_wait_for_pending_commands(vha, 0, 0,
3717 WAIT_HOST) == QLA_SUCCESS) {
7c3df132
SK		 3718 ql_dbg(ql_dbg_init, vha, 0x00b3,
3719 "Done wait for "
3720 "pending commands.\n");
7190575f
GM		 3721 }
3722 }
3723}
08de2844
GM		 3724
3725/* Minidump related functions */
08de2844
GM		 3726static int
3727qla82xx_minidump_process_control(scsi_qla_host_t *vha,
3728 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3729{
3730 struct qla_hw_data *ha = vha->hw;
3731 struct qla82xx_md_entry_crb *crb_entry;
3732 uint32_t read_value, opcode, poll_time;
3733 uint32_t addr, index, crb_addr;
3734 unsigned long wtime;
3735 struct qla82xx_md_template_hdr *tmplt_hdr;
3736 uint32_t rval = QLA_SUCCESS;
3737 int i;
3738
3739 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
3740 crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr;
3741 crb_addr = crb_entry->addr;
3742
3743 for (i = 0; i < crb_entry->op_count; i++) {
3744 opcode = crb_entry->crb_ctrl.opcode;
3745 if (opcode & QLA82XX_DBG_OPCODE_WR) {
3746 qla82xx_md_rw_32(ha, crb_addr,
3747 crb_entry->value_1, 1);
3748 opcode &= ~QLA82XX_DBG_OPCODE_WR;
3749 }
3750
3751 if (opcode & QLA82XX_DBG_OPCODE_RW) {
3752 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3753 qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3754 opcode &= ~QLA82XX_DBG_OPCODE_RW;
3755 }
3756
3757 if (opcode & QLA82XX_DBG_OPCODE_AND) {
3758 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3759 read_value &= crb_entry->value_2;
3760 opcode &= ~QLA82XX_DBG_OPCODE_AND;
3761 if (opcode & QLA82XX_DBG_OPCODE_OR) {
3762 read_value |= crb_entry->value_3;
3763 opcode &= ~QLA82XX_DBG_OPCODE_OR;
3764 }
3765 qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3766 }
3767
3768 if (opcode & QLA82XX_DBG_OPCODE_OR) {
3769 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3770 read_value |= crb_entry->value_3;
3771 qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3772 opcode &= ~QLA82XX_DBG_OPCODE_OR;
3773 }
3774
3775 if (opcode & QLA82XX_DBG_OPCODE_POLL) {
3776 poll_time = crb_entry->crb_strd.poll_timeout;
3777 wtime = jiffies + poll_time;
3778 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3779
3780 do {
3781 if ((read_value & crb_entry->value_2)
3782 == crb_entry->value_1)
3783 break;
3784 else if (time_after_eq(jiffies, wtime)) {
3785 /* capturing dump failed */
3786 rval = QLA_FUNCTION_FAILED;
3787 break;
3788 } else
3789 read_value = qla82xx_md_rw_32(ha,
3790 crb_addr, 0, 0);
3791 } while (1);
3792 opcode &= ~QLA82XX_DBG_OPCODE_POLL;
3793 }
3794
3795 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) {
3796 if (crb_entry->crb_strd.state_index_a) {
3797 index = crb_entry->crb_strd.state_index_a;
3798 addr = tmplt_hdr->saved_state_array[index];
3799 } else
3800 addr = crb_addr;
3801
3802 read_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3803 index = crb_entry->crb_ctrl.state_index_v;
3804 tmplt_hdr->saved_state_array[index] = read_value;
3805 opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE;
3806 }
3807
3808 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) {
3809 if (crb_entry->crb_strd.state_index_a) {
3810 index = crb_entry->crb_strd.state_index_a;
3811 addr = tmplt_hdr->saved_state_array[index];
3812 } else
3813 addr = crb_addr;
3814
3815 if (crb_entry->crb_ctrl.state_index_v) {
3816 index = crb_entry->crb_ctrl.state_index_v;
3817 read_value =
3818 tmplt_hdr->saved_state_array[index];
3819 } else
3820 read_value = crb_entry->value_1;
3821
3822 qla82xx_md_rw_32(ha, addr, read_value, 1);
3823 opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE;
3824 }
3825
3826 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) {
3827 index = crb_entry->crb_ctrl.state_index_v;
3828 read_value = tmplt_hdr->saved_state_array[index];
3829 read_value <<= crb_entry->crb_ctrl.shl;
3830 read_value >>= crb_entry->crb_ctrl.shr;
3831 if (crb_entry->value_2)
3832 read_value &= crb_entry->value_2;
3833 read_value |= crb_entry->value_3;
3834 read_value += crb_entry->value_1;
3835 tmplt_hdr->saved_state_array[index] = read_value;
3836 opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE;
3837 }
3838 crb_addr += crb_entry->crb_strd.addr_stride;
3839 }
3840 return rval;
3841}
3842
3843static void
3844qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha,
3845 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3846{
3847 struct qla_hw_data *ha = vha->hw;
3848 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
3849 struct qla82xx_md_entry_rdocm *ocm_hdr;
3850 uint32_t *data_ptr = *d_ptr;
3851
3852 ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr;
3853 r_addr = ocm_hdr->read_addr;
3854 r_stride = ocm_hdr->read_addr_stride;
3855 loop_cnt = ocm_hdr->op_count;
3856
3857 for (i = 0; i < loop_cnt; i++) {
fa492630
SK		 3858 r_value = RD_REG_DWORD((void __iomem *)
3859 (r_addr + ha->nx_pcibase));
08de2844
GM		 3860 *data_ptr++ = cpu_to_le32(r_value);
3861 r_addr += r_stride;
3862 }
3863 *d_ptr = data_ptr;
3864}
3865
3866static void
3867qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha,
3868 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3869{
3870 struct qla_hw_data *ha = vha->hw;
3871 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
3872 struct qla82xx_md_entry_mux *mux_hdr;
3873 uint32_t *data_ptr = *d_ptr;
3874
3875 mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr;
3876 r_addr = mux_hdr->read_addr;
3877 s_addr = mux_hdr->select_addr;
3878 s_stride = mux_hdr->select_value_stride;
3879 s_value = mux_hdr->select_value;
3880 loop_cnt = mux_hdr->op_count;
3881
3882 for (i = 0; i < loop_cnt; i++) {
3883 qla82xx_md_rw_32(ha, s_addr, s_value, 1);
3884 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3885 *data_ptr++ = cpu_to_le32(s_value);
3886 *data_ptr++ = cpu_to_le32(r_value);
3887 s_value += s_stride;
3888 }
3889 *d_ptr = data_ptr;
3890}
3891
3892static void
3893qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha,
3894 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3895{
3896 struct qla_hw_data *ha = vha->hw;
3897 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
3898 struct qla82xx_md_entry_crb *crb_hdr;
3899 uint32_t *data_ptr = *d_ptr;
3900
3901 crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr;
3902 r_addr = crb_hdr->addr;
3903 r_stride = crb_hdr->crb_strd.addr_stride;
3904 loop_cnt = crb_hdr->op_count;
3905
3906 for (i = 0; i < loop_cnt; i++) {
3907 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3908 *data_ptr++ = cpu_to_le32(r_addr);
3909 *data_ptr++ = cpu_to_le32(r_value);
3910 r_addr += r_stride;
3911 }
3912 *d_ptr = data_ptr;
3913}
3914
3915static int
3916qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha,
3917 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3918{
3919 struct qla_hw_data *ha = vha->hw;
3920 uint32_t addr, r_addr, c_addr, t_r_addr;
3921 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
3922 unsigned long p_wait, w_time, p_mask;
3923 uint32_t c_value_w, c_value_r;
3924 struct qla82xx_md_entry_cache *cache_hdr;
3925 int rval = QLA_FUNCTION_FAILED;
3926 uint32_t *data_ptr = *d_ptr;
3927
3928 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr;
3929 loop_count = cache_hdr->op_count;
3930 r_addr = cache_hdr->read_addr;
3931 c_addr = cache_hdr->control_addr;
3932 c_value_w = cache_hdr->cache_ctrl.write_value;
3933
3934 t_r_addr = cache_hdr->tag_reg_addr;
3935 t_value = cache_hdr->addr_ctrl.init_tag_value;
3936 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
3937 p_wait = cache_hdr->cache_ctrl.poll_wait;
3938 p_mask = cache_hdr->cache_ctrl.poll_mask;
3939
3940 for (i = 0; i < loop_count; i++) {
3941 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1);
3942 if (c_value_w)
3943 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1);
3944
3945 if (p_mask) {
3946 w_time = jiffies + p_wait;
3947 do {
3948 c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0);
3949 if ((c_value_r & p_mask) == 0)
3950 break;
3951 else if (time_after_eq(jiffies, w_time)) {
3952 /* capturing dump failed */
3953 ql_dbg(ql_dbg_p3p, vha, 0xb032,
3954 "c_value_r: 0x%x, poll_mask: 0x%lx, "
3955 "w_time: 0x%lx\n",
3956 c_value_r, p_mask, w_time);
3957 return rval;
3958 }
3959 } while (1);
3960 }
3961
3962 addr = r_addr;
3963 for (k = 0; k < r_cnt; k++) {
3964 r_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3965 *data_ptr++ = cpu_to_le32(r_value);
3966 addr += cache_hdr->read_ctrl.read_addr_stride;
3967 }
3968 t_value += cache_hdr->addr_ctrl.tag_value_stride;
3969 }
3970 *d_ptr = data_ptr;
3971 return QLA_SUCCESS;
3972}
3973
3974static void
3975qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha,
3976 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3977{
3978 struct qla_hw_data *ha = vha->hw;
3979 uint32_t addr, r_addr, c_addr, t_r_addr;
3980 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
3981 uint32_t c_value_w;
3982 struct qla82xx_md_entry_cache *cache_hdr;
3983 uint32_t *data_ptr = *d_ptr;
3984
3985 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr;
3986 loop_count = cache_hdr->op_count;
3987 r_addr = cache_hdr->read_addr;
3988 c_addr = cache_hdr->control_addr;
3989 c_value_w = cache_hdr->cache_ctrl.write_value;
3990
3991 t_r_addr = cache_hdr->tag_reg_addr;
3992 t_value = cache_hdr->addr_ctrl.init_tag_value;
3993 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
3994
3995 for (i = 0; i < loop_count; i++) {
3996 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1);
3997 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1);
3998 addr = r_addr;
3999 for (k = 0; k < r_cnt; k++) {
4000 r_value = qla82xx_md_rw_32(ha, addr, 0, 0);
4001 *data_ptr++ = cpu_to_le32(r_value);
4002 addr += cache_hdr->read_ctrl.read_addr_stride;
4003 }
4004 t_value += cache_hdr->addr_ctrl.tag_value_stride;
4005 }
4006 *d_ptr = data_ptr;
4007}
4008
4009static void
4010qla82xx_minidump_process_queue(scsi_qla_host_t *vha,
4011 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
4012{
4013 struct qla_hw_data *ha = vha->hw;
4014 uint32_t s_addr, r_addr;
4015 uint32_t r_stride, r_value, r_cnt, qid = 0;
4016 uint32_t i, k, loop_cnt;
4017 struct qla82xx_md_entry_queue *q_hdr;
4018 uint32_t *data_ptr = *d_ptr;
4019
4020 q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr;
4021 s_addr = q_hdr->select_addr;
4022 r_cnt = q_hdr->rd_strd.read_addr_cnt;
4023 r_stride = q_hdr->rd_strd.read_addr_stride;
4024 loop_cnt = q_hdr->op_count;
4025
4026 for (i = 0; i < loop_cnt; i++) {
4027 qla82xx_md_rw_32(ha, s_addr, qid, 1);
4028 r_addr = q_hdr->read_addr;
4029 for (k = 0; k < r_cnt; k++) {
4030 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
4031 *data_ptr++ = cpu_to_le32(r_value);
4032 r_addr += r_stride;
4033 }
4034 qid += q_hdr->q_strd.queue_id_stride;
4035 }
4036 *d_ptr = data_ptr;
4037}
4038
4039static void
4040qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha,
4041 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
4042{
4043 struct qla_hw_data *ha = vha->hw;
4044 uint32_t r_addr, r_value;
4045 uint32_t i, loop_cnt;
4046 struct qla82xx_md_entry_rdrom *rom_hdr;
4047 uint32_t *data_ptr = *d_ptr;
4048
4049 rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr;
4050 r_addr = rom_hdr->read_addr;
4051 loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t);
4052
4053 for (i = 0; i < loop_cnt; i++) {
4054 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW,
4055 (r_addr & 0xFFFF0000), 1);
4056 r_value = qla82xx_md_rw_32(ha,
4057 MD_DIRECT_ROM_READ_BASE +
4058 (r_addr & 0x0000FFFF), 0, 0);
4059 *data_ptr++ = cpu_to_le32(r_value);
4060 r_addr += sizeof(uint32_t);
4061 }
4062 *d_ptr = data_ptr;
4063}
4064
4065static int
4066qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha,
4067 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
4068{
4069 struct qla_hw_data *ha = vha->hw;
4070 uint32_t r_addr, r_value, r_data;
4071 uint32_t i, j, loop_cnt;
4072 struct qla82xx_md_entry_rdmem *m_hdr;
4073 unsigned long flags;
4074 int rval = QLA_FUNCTION_FAILED;
4075 uint32_t *data_ptr = *d_ptr;
4076
4077 m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr;
4078 r_addr = m_hdr->read_addr;
4079 loop_cnt = m_hdr->read_data_size/16;
4080
4081 if (r_addr & 0xf) {
4082 ql_log(ql_log_warn, vha, 0xb033,
d6a03581 4083 "Read addr 0x%x not 16 bytes aligned\n", r_addr);
08de2844
GM		 4084 return rval;
4085 }
4086
4087 if (m_hdr->read_data_size % 16) {
4088 ql_log(ql_log_warn, vha, 0xb034,
4089 "Read data[0x%x] not multiple of 16 bytes\n",
4090 m_hdr->read_data_size);
4091 return rval;
4092 }
4093
4094 ql_dbg(ql_dbg_p3p, vha, 0xb035,
4095 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
4096 __func__, r_addr, m_hdr->read_data_size, loop_cnt);
4097
4098 write_lock_irqsave(&ha->hw_lock, flags);
4099 for (i = 0; i < loop_cnt; i++) {
4100 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1);
4101 r_value = 0;
4102 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1);
4103 r_value = MIU_TA_CTL_ENABLE;
4104 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
4105 r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
4106 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
4107
4108 for (j = 0; j < MAX_CTL_CHECK; j++) {
4109 r_value = qla82xx_md_rw_32(ha,
4110 MD_MIU_TEST_AGT_CTRL, 0, 0);
4111 if ((r_value & MIU_TA_CTL_BUSY) == 0)
4112 break;
4113 }
4114
4115 if (j >= MAX_CTL_CHECK) {
4116 printk_ratelimited(KERN_ERR
4117 "failed to read through agent\n");
4118 write_unlock_irqrestore(&ha->hw_lock, flags);
4119 return rval;
4120 }
4121
4122 for (j = 0; j < 4; j++) {
4123 r_data = qla82xx_md_rw_32(ha,
4124 MD_MIU_TEST_AGT_RDDATA[j], 0, 0);
4125 *data_ptr++ = cpu_to_le32(r_data);
4126 }
4127 r_addr += 16;
4128 }
4129 write_unlock_irqrestore(&ha->hw_lock, flags);
4130 *d_ptr = data_ptr;
4131 return QLA_SUCCESS;
4132}
4133
7ec0effd 4134int
08de2844
GM		 4135qla82xx_validate_template_chksum(scsi_qla_host_t *vha)
4136{
4137 struct qla_hw_data *ha = vha->hw;
4138 uint64_t chksum = 0;
4139 uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr;
4140 int count = ha->md_template_size/sizeof(uint32_t);
4141
4142 while (count-- > 0)
4143 chksum += *d_ptr++;
4144 while (chksum >> 32)
4145 chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32);
4146 return ~chksum;
4147}
4148
4149static void
4150qla82xx_mark_entry_skipped(scsi_qla_host_t *vha,
4151 qla82xx_md_entry_hdr_t *entry_hdr, int index)
4152{
4153 entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG;
4154 ql_dbg(ql_dbg_p3p, vha, 0xb036,
4155 "Skipping entry[%d]: "
4156 "ETYPE[0x%x]-ELEVEL[0x%x]\n",
4157 index, entry_hdr->entry_type,
4158 entry_hdr->d_ctrl.entry_capture_mask);
4159}
4160
4161int
4162qla82xx_md_collect(scsi_qla_host_t *vha)
4163{
4164 struct qla_hw_data *ha = vha->hw;
4165 int no_entry_hdr = 0;
4166 qla82xx_md_entry_hdr_t *entry_hdr;
4167 struct qla82xx_md_template_hdr *tmplt_hdr;
4168 uint32_t *data_ptr;
4169 uint32_t total_data_size = 0, f_capture_mask, data_collected = 0;
4170 int i = 0, rval = QLA_FUNCTION_FAILED;
4171
4172 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
4173 data_ptr = (uint32_t *)ha->md_dump;
4174
4175 if (ha->fw_dumped) {
a8faa263
GM		 4176 ql_log(ql_log_warn, vha, 0xb037,
4177 "Firmware has been previously dumped (%p) "
4178 "-- ignoring request.\n", ha->fw_dump);
08de2844
GM		 4179 goto md_failed;
4180 }
4181
4182 ha->fw_dumped = 0;
4183
4184 if (!ha->md_tmplt_hdr || !ha->md_dump) {
4185 ql_log(ql_log_warn, vha, 0xb038,
4186 "Memory not allocated for minidump capture\n");
4187 goto md_failed;
4188 }
4189
b6d0d9d5
GM		 4190 if (ha->flags.isp82xx_no_md_cap) {
4191 ql_log(ql_log_warn, vha, 0xb054,
4192 "Forced reset from application, "
4193 "ignore minidump capture\n");
4194 ha->flags.isp82xx_no_md_cap = 0;
4195 goto md_failed;
4196 }
4197
08de2844
GM		 4198 if (qla82xx_validate_template_chksum(vha)) {
4199 ql_log(ql_log_info, vha, 0xb039,
4200 "Template checksum validation error\n");
4201 goto md_failed;
4202 }
4203
4204 no_entry_hdr = tmplt_hdr->num_of_entries;
4205 ql_dbg(ql_dbg_p3p, vha, 0xb03a,
4206 "No of entry headers in Template: 0x%x\n", no_entry_hdr);
4207
4208 ql_dbg(ql_dbg_p3p, vha, 0xb03b,
4209 "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level);
4210
4211 f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF;
4212
4213 /* Validate whether required debug level is set */
4214 if ((f_capture_mask & 0x3) != 0x3) {
4215 ql_log(ql_log_warn, vha, 0xb03c,
4216 "Minimum required capture mask[0x%x] level not set\n",
4217 f_capture_mask);
4218 goto md_failed;
4219 }
4220 tmplt_hdr->driver_capture_mask = ql2xmdcapmask;
4221
4222 tmplt_hdr->driver_info[0] = vha->host_no;
4223 tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) |
4224 (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) |
4225 QLA_DRIVER_BETA_VER;
4226
4227 total_data_size = ha->md_dump_size;
4228
880fdedb 4229 ql_dbg(ql_dbg_p3p, vha, 0xb03d,
08de2844
GM		 4230 "Total minidump data_size 0x%x to be captured\n", total_data_size);
4231
4232 /* Check whether template obtained is valid */
4233 if (tmplt_hdr->entry_type != QLA82XX_TLHDR) {
4234 ql_log(ql_log_warn, vha, 0xb04e,
4235 "Bad template header entry type: 0x%x obtained\n",
4236 tmplt_hdr->entry_type);
4237 goto md_failed;
4238 }
4239
4240 entry_hdr = (qla82xx_md_entry_hdr_t *) \
4241 (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset);
4242
4243 /* Walk through the entry headers */
4244 for (i = 0; i < no_entry_hdr; i++) {
4245
4246 if (data_collected > total_data_size) {
4247 ql_log(ql_log_warn, vha, 0xb03e,
4248 "More MiniDump data collected: [0x%x]\n",
4249 data_collected);
4250 goto md_failed;
4251 }
4252
4253 if (!(entry_hdr->d_ctrl.entry_capture_mask &
4254 ql2xmdcapmask)) {
4255 entry_hdr->d_ctrl.driver_flags |=
4256 QLA82XX_DBG_SKIPPED_FLAG;
4257 ql_dbg(ql_dbg_p3p, vha, 0xb03f,
4258 "Skipping entry[%d]: "
4259 "ETYPE[0x%x]-ELEVEL[0x%x]\n",
4260 i, entry_hdr->entry_type,
4261 entry_hdr->d_ctrl.entry_capture_mask);
4262 goto skip_nxt_entry;
4263 }
4264
4265 ql_dbg(ql_dbg_p3p, vha, 0xb040,
4266 "[%s]: data ptr[%d]: %p, entry_hdr: %p\n"
4267 "entry_type: 0x%x, captrue_mask: 0x%x\n",
4268 __func__, i, data_ptr, entry_hdr,
4269 entry_hdr->entry_type,
4270 entry_hdr->d_ctrl.entry_capture_mask);
4271
4272 ql_dbg(ql_dbg_p3p, vha, 0xb041,
4273 "Data collected: [0x%x], Dump size left:[0x%x]\n",
4274 data_collected, (ha->md_dump_size - data_collected));
4275
4276 /* Decode the entry type and take
4277 * required action to capture debug data */
4278 switch (entry_hdr->entry_type) {
4279 case QLA82XX_RDEND:
4280 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4281 break;
4282 case QLA82XX_CNTRL:
4283 rval = qla82xx_minidump_process_control(vha,
4284 entry_hdr, &data_ptr);
4285 if (rval != QLA_SUCCESS) {
4286 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4287 goto md_failed;
4288 }
4289 break;
4290 case QLA82XX_RDCRB:
4291 qla82xx_minidump_process_rdcrb(vha,
4292 entry_hdr, &data_ptr);
4293 break;
4294 case QLA82XX_RDMEM:
4295 rval = qla82xx_minidump_process_rdmem(vha,
4296 entry_hdr, &data_ptr);
4297 if (rval != QLA_SUCCESS) {
4298 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4299 goto md_failed;
4300 }
4301 break;
4302 case QLA82XX_BOARD:
4303 case QLA82XX_RDROM:
4304 qla82xx_minidump_process_rdrom(vha,
4305 entry_hdr, &data_ptr);
4306 break;
4307 case QLA82XX_L2DTG:
4308 case QLA82XX_L2ITG:
4309 case QLA82XX_L2DAT:
4310 case QLA82XX_L2INS:
4311 rval = qla82xx_minidump_process_l2tag(vha,
4312 entry_hdr, &data_ptr);
4313 if (rval != QLA_SUCCESS) {
4314 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4315 goto md_failed;
4316 }
4317 break;
4318 case QLA82XX_L1DAT:
4319 case QLA82XX_L1INS:
4320 qla82xx_minidump_process_l1cache(vha,
4321 entry_hdr, &data_ptr);
4322 break;
4323 case QLA82XX_RDOCM:
4324 qla82xx_minidump_process_rdocm(vha,
4325 entry_hdr, &data_ptr);
4326 break;
4327 case QLA82XX_RDMUX:
4328 qla82xx_minidump_process_rdmux(vha,
4329 entry_hdr, &data_ptr);
4330 break;
4331 case QLA82XX_QUEUE:
4332 qla82xx_minidump_process_queue(vha,
4333 entry_hdr, &data_ptr);
4334 break;
4335 case QLA82XX_RDNOP:
4336 default:
4337 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4338 break;
4339 }
4340
4341 ql_dbg(ql_dbg_p3p, vha, 0xb042,
4342 "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr);
4343
4344 data_collected = (uint8_t *)data_ptr -
4345 (uint8_t *)ha->md_dump;
4346skip_nxt_entry:
4347 entry_hdr = (qla82xx_md_entry_hdr_t *) \
4348 (((uint8_t *)entry_hdr) + entry_hdr->entry_size);
4349 }
4350
4351 if (data_collected != total_data_size) {
880fdedb 4352 ql_dbg(ql_dbg_p3p, vha, 0xb043,
08de2844
GM		 4353 "MiniDump data mismatch: Data collected: [0x%x],"
4354 "total_data_size:[0x%x]\n",
4355 data_collected, total_data_size);
4356 goto md_failed;
4357 }
4358
4359 ql_log(ql_log_info, vha, 0xb044,
4360 "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n",
4361 vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump);
4362 ha->fw_dumped = 1;
4363 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
4364
4365md_failed:
4366 return rval;
4367}
4368
4369int
4370qla82xx_md_alloc(scsi_qla_host_t *vha)
4371{
4372 struct qla_hw_data *ha = vha->hw;
4373 int i, k;
4374 struct qla82xx_md_template_hdr *tmplt_hdr;
4375
4376 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
4377
4378 if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) {
4379 ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF;
4380 ql_log(ql_log_info, vha, 0xb045,
4381 "Forcing driver capture mask to firmware default capture mask: 0x%x.\n",
4382 ql2xmdcapmask);
4383 }
4384
4385 for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) {
4386 if (i & ql2xmdcapmask)
4387 ha->md_dump_size += tmplt_hdr->capture_size_array[k];
4388 }
4389
4390 if (ha->md_dump) {
4391 ql_log(ql_log_warn, vha, 0xb046,
4392 "Firmware dump previously allocated.\n");
4393 return 1;
4394 }
4395
4396 ha->md_dump = vmalloc(ha->md_dump_size);
4397 if (ha->md_dump == NULL) {
4398 ql_log(ql_log_warn, vha, 0xb047,
4399 "Unable to allocate memory for Minidump size "
4400 "(0x%x).\n", ha->md_dump_size);
4401 return 1;
4402 }
4403 return 0;
4404}
4405
4406void
4407qla82xx_md_free(scsi_qla_host_t *vha)
4408{
4409 struct qla_hw_data *ha = vha->hw;
4410
4411 /* Release the template header allocated */
4412 if (ha->md_tmplt_hdr) {
4413 ql_log(ql_log_info, vha, 0xb048,
4414 "Free MiniDump template: %p, size (%d KB)\n",
4415 ha->md_tmplt_hdr, ha->md_template_size / 1024);
4416 dma_free_coherent(&ha->pdev->dev, ha->md_template_size,
4417 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma);
fa492630 4418 ha->md_tmplt_hdr = NULL;
08de2844
GM		 4419 }
4420
4421 /* Release the template data buffer allocated */
4422 if (ha->md_dump) {
4423 ql_log(ql_log_info, vha, 0xb049,
4424 "Free MiniDump memory: %p, size (%d KB)\n",
4425 ha->md_dump, ha->md_dump_size / 1024);
4426 vfree(ha->md_dump);
4427 ha->md_dump_size = 0;
fa492630 4428 ha->md_dump = NULL;
08de2844
GM		 4429 }
4430}
4431
4432void
4433qla82xx_md_prep(scsi_qla_host_t *vha)
4434{
4435 struct qla_hw_data *ha = vha->hw;
4436 int rval;
4437
4438 /* Get Minidump template size */
4439 rval = qla82xx_md_get_template_size(vha);
4440 if (rval == QLA_SUCCESS) {
4441 ql_log(ql_log_info, vha, 0xb04a,
4442 "MiniDump Template size obtained (%d KB)\n",
4443 ha->md_template_size / 1024);
4444
4445 /* Get Minidump template */
7ec0effd
AD		 4446 if (IS_QLA8044(ha))
4447 rval = qla8044_md_get_template(vha);
4448 else
4449 rval = qla82xx_md_get_template(vha);
4450
08de2844
GM		 4451 if (rval == QLA_SUCCESS) {
4452 ql_dbg(ql_dbg_p3p, vha, 0xb04b,
4453 "MiniDump Template obtained\n");
4454
4455 /* Allocate memory for minidump */
4456 rval = qla82xx_md_alloc(vha);
4457 if (rval == QLA_SUCCESS)
4458 ql_log(ql_log_info, vha, 0xb04c,
4459 "MiniDump memory allocated (%d KB)\n",
4460 ha->md_dump_size / 1024);
4461 else {
4462 ql_log(ql_log_info, vha, 0xb04d,
4463 "Free MiniDump template: %p, size: (%d KB)\n",
4464 ha->md_tmplt_hdr,
4465 ha->md_template_size / 1024);
4466 dma_free_coherent(&ha->pdev->dev,
4467 ha->md_template_size,
4468 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma);
fa492630 4469 ha->md_tmplt_hdr = NULL;
08de2844
GM		 4470 }
4471
4472 }
4473 }
4474}
999916dc
SK		 4475
4476int
4477qla82xx_beacon_on(struct scsi_qla_host *vha)
4478{
4479
4480 int rval;
4481 struct qla_hw_data *ha = vha->hw;
4482 qla82xx_idc_lock(ha);
4483 rval = qla82xx_mbx_beacon_ctl(vha, 1);
4484
4485 if (rval) {
4486 ql_log(ql_log_warn, vha, 0xb050,
4487 "mbx set led config failed in %s\n", __func__);
4488 goto exit;
4489 }
4490 ha->beacon_blink_led = 1;
4491exit:
4492 qla82xx_idc_unlock(ha);
4493 return rval;
4494}
4495
4496int
4497qla82xx_beacon_off(struct scsi_qla_host *vha)
4498{
4499
4500 int rval;
4501 struct qla_hw_data *ha = vha->hw;
4502 qla82xx_idc_lock(ha);
4503 rval = qla82xx_mbx_beacon_ctl(vha, 0);
4504
4505 if (rval) {
4506 ql_log(ql_log_warn, vha, 0xb051,
4507 "mbx set led config failed in %s\n", __func__);
4508 goto exit;
4509 }
4510 ha->beacon_blink_led = 0;
4511exit:
4512 qla82xx_idc_unlock(ha);
4513 return rval;
4514}
a1b23c5a
CD		 4515
4516void
4517qla82xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
4518{
4519 struct qla_hw_data *ha = vha->hw;
4520
4521 if (!ha->allow_cna_fw_dump)
4522 return;
4523
4524 scsi_block_requests(vha->host);
4525 ha->flags.isp82xx_no_md_cap = 1;
4526 qla82xx_idc_lock(ha);
4527 qla82xx_set_reset_owner(vha);
4528 qla82xx_idc_unlock(ha);
4529 qla2x00_wait_for_chip_reset(vha);
4530 scsi_unblock_requests(vha->host);
4531}
Linux kernel - Deliverables
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