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[SCSI] hpsa: fix physical device lun and target numbering problem
[deliverable/linux.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
07e264b7 3 * Copyright (c) 2003-2011 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16
17#include <scsi/scsi_tcq.h>
18#include <scsi/scsicam.h>
19#include <scsi/scsi_transport.h>
20#include <scsi/scsi_transport_fc.h>
21
22/*
23 * Driver version
24 */
25char qla2x00_version_str[40];
26
6a03b4cd
HZ		 27static int apidev_major;
28
1da177e4
LT		 29/*
30 * SRB allocation cache
31 */
e18b890b 32static struct kmem_cache *srb_cachep;
1da177e4 33
a9083016
GM		 34/*
35 * CT6 CTX allocation cache
36 */
37static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 38/*
39 * error level for logging
40 */
41int ql_errlev = ql_log_all;
a9083016 42
1da177e4 43int ql2xlogintimeout = 20;
f2019cb1 44module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 45MODULE_PARM_DESC(ql2xlogintimeout,
46 "Login timeout value in seconds.");
47
a7b61842 48int qlport_down_retry;
f2019cb1 49module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 50MODULE_PARM_DESC(qlport_down_retry,
900d9f98 51 "Maximum number of command retries to a port that returns "
1da177e4
LT		 52 "a PORT-DOWN status.");
53
1da177e4
LT		 54int ql2xplogiabsentdevice;
55module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
56MODULE_PARM_DESC(ql2xplogiabsentdevice,
57 "Option to enable PLOGI to devices that are not present after "
900d9f98 58 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 59 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
60
1da177e4 61int ql2xloginretrycount = 0;
f2019cb1 62module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 63MODULE_PARM_DESC(ql2xloginretrycount,
64 "Specify an alternate value for the NVRAM login retry count.");
65
a7a167bf 66int ql2xallocfwdump = 1;
f2019cb1 67module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 68MODULE_PARM_DESC(ql2xallocfwdump,
69 "Option to enable allocation of memory for a firmware dump "
70 "during HBA initialization. Memory allocation requirements "
71 "vary by ISP type. Default is 1 - allocate memory.");
72
11010fec 73int ql2xextended_error_logging;
27d94035 74module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 75MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 76 "Option to enable extended error logging,\n"
77 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
78 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
79 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
80 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
81 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
82 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
83 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
84 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
85 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
86 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 87
a9083016 88int ql2xshiftctondsd = 6;
f2019cb1 89module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 90MODULE_PARM_DESC(ql2xshiftctondsd,
91 "Set to control shifting of command type processing "
92 "based on total number of SG elements.");
93
1da177e4
LT		 94static void qla2x00_free_device(scsi_qla_host_t *);
95
7e47e5ca 96int ql2xfdmienable=1;
f2019cb1 97module_param(ql2xfdmienable, int, S_IRUGO);
cca5335c 98MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 99 "Enables FDMI registrations. "
100 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 101
df7baa50
AV		 102#define MAX_Q_DEPTH 32
103static int ql2xmaxqdepth = MAX_Q_DEPTH;
104module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
105MODULE_PARM_DESC(ql2xmaxqdepth,
106 "Maximum queue depth to report for target devices.");
107
bad75002
AE		 108/* Do not change the value of this after module load */
109int ql2xenabledif = 1;
110module_param(ql2xenabledif, int, S_IRUGO|S_IWUSR);
111MODULE_PARM_DESC(ql2xenabledif,
112 " Enable T10-CRC-DIF "
113 " Default is 0 - No DIF Support. 1 - Enable it");
114
115int ql2xenablehba_err_chk;
116module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
117MODULE_PARM_DESC(ql2xenablehba_err_chk,
118 " Enable T10-CRC-DIF Error isolation by HBA"
119 " Default is 0 - Error isolation disabled, 1 - Enable it");
120
e5896bd5 121int ql2xiidmaenable=1;
f2019cb1 122module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 123MODULE_PARM_DESC(ql2xiidmaenable,
124 "Enables iIDMA settings "
125 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
126
73208dfd 127int ql2xmaxqueues = 1;
f2019cb1 128module_param(ql2xmaxqueues, int, S_IRUGO);
73208dfd
AC		 129MODULE_PARM_DESC(ql2xmaxqueues,
130 "Enables MQ settings "
ae68230c
JP		 131 "Default is 1 for single queue. Set it to number "
132 "of queues in MQ mode.");
68ca949c
AC		 133
134int ql2xmultique_tag;
f2019cb1 135module_param(ql2xmultique_tag, int, S_IRUGO);
68ca949c
AC		 136MODULE_PARM_DESC(ql2xmultique_tag,
137 "Enables CPU affinity settings for the driver "
138 "Default is 0 for no affinity of request and response IO. "
139 "Set it to 1 to turn on the cpu affinity.");
e337d907
AV		 140
141int ql2xfwloadbin;
f2019cb1 142module_param(ql2xfwloadbin, int, S_IRUGO);
e337d907 143MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 144 "Option to specify location from which to load ISP firmware:.\n"
145 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 146 " interface.\n"
147 " 1 -- load firmware from flash.\n"
148 " 0 -- use default semantics.\n");
149
ae97c91e 150int ql2xetsenable;
f2019cb1 151module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 152MODULE_PARM_DESC(ql2xetsenable,
153 "Enables firmware ETS burst."
154 "Default is 0 - skip ETS enablement.");
155
6907869d 156int ql2xdbwr = 1;
f2019cb1 157module_param(ql2xdbwr, int, S_IRUGO);
a9083016 158MODULE_PARM_DESC(ql2xdbwr,
7c3df132 159 "Option to specify scheme for request queue posting.\n"
a9083016
GM		 160 " 0 -- Regular doorbell.\n"
161 " 1 -- CAMRAM doorbell (faster).\n");
162
f4c496c1 163int ql2xtargetreset = 1;
f2019cb1 164module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 165MODULE_PARM_DESC(ql2xtargetreset,
166 "Enable target reset."
167 "Default is 1 - use hw defaults.");
168
4da26e16 169int ql2xgffidenable;
f2019cb1 170module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 171MODULE_PARM_DESC(ql2xgffidenable,
172 "Enables GFF_ID checks of port type. "
173 "Default is 0 - Do not use GFF_ID information.");
a9083016 174
3822263e 175int ql2xasynctmfenable;
f2019cb1 176module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 177MODULE_PARM_DESC(ql2xasynctmfenable,
178 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
179 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 180
181int ql2xdontresethba;
182module_param(ql2xdontresethba, int, S_IRUGO);
183MODULE_PARM_DESC(ql2xdontresethba,
7c3df132 184 "Option to specify reset behaviour.\n"
ed0de87c
GM		 185 " 0 (Default) -- Reset on failure.\n"
186 " 1 -- Do not reset on failure.\n");
187
82515920
AV		 188uint ql2xmaxlun = MAX_LUNS;
189module_param(ql2xmaxlun, uint, S_IRUGO);
190MODULE_PARM_DESC(ql2xmaxlun,
191 "Defines the maximum LU number to register with the SCSI "
192 "midlayer. Default is 65535.");
193
1da177e4 194/*
fa2a1ce5 195 * SCSI host template entry points
1da177e4
LT		 196 */
197static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 198static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 199static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
200static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 201static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 202static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 203static int qla2xxx_eh_abort(struct scsi_cmnd *);
204static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 205static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 206static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
207static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 208
e881a172 209static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
ce7e4af7
AV		 210static int qla2x00_change_queue_type(struct scsi_device *, int);
211
a5326f86 212struct scsi_host_template qla2xxx_driver_template = {
1da177e4 213 .module = THIS_MODULE,
cb63067a 214 .name = QLA2XXX_DRIVER_NAME,
a5326f86 215 .queuecommand = qla2xxx_queuecommand,
fca29703
AV		 216
217 .eh_abort_handler = qla2xxx_eh_abort,
218 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 219 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 220 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
221 .eh_host_reset_handler = qla2xxx_eh_host_reset,
222
223 .slave_configure = qla2xxx_slave_configure,
224
225 .slave_alloc = qla2xxx_slave_alloc,
226 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 227 .scan_finished = qla2xxx_scan_finished,
228 .scan_start = qla2xxx_scan_start,
ce7e4af7
AV		 229 .change_queue_depth = qla2x00_change_queue_depth,
230 .change_queue_type = qla2x00_change_queue_type,
fca29703
AV		 231 .this_id = -1,
232 .cmd_per_lun = 3,
233 .use_clustering = ENABLE_CLUSTERING,
234 .sg_tablesize = SG_ALL,
235
236 .max_sectors = 0xFFFF,
afb046e2 237 .shost_attrs = qla2x00_host_attrs,
fca29703
AV		 238};
239
1da177e4 240static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 241struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 242
1da177e4
LT		 243/* TODO Convert to inlines
244 *
245 * Timer routines
246 */
1da177e4 247
2c3dfe3f 248__inline__ void
e315cd28 249qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 250{
e315cd28
AC		 251 init_timer(&vha->timer);
252 vha->timer.expires = jiffies + interval * HZ;
253 vha->timer.data = (unsigned long)vha;
254 vha->timer.function = (void (*)(unsigned long))func;
255 add_timer(&vha->timer);
256 vha->timer_active = 1;
1da177e4
LT		 257}
258
259static inline void
e315cd28 260qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 261{
a9083016 262 /* Currently used for 82XX only. */
7c3df132
SK		 263 if (vha->device_flags & DFLG_DEV_FAILED) {
264 ql_dbg(ql_dbg_timer, vha, 0x600d,
265 "Device in a failed state, returning.\n");
a9083016 266 return;
7c3df132 267 }
a9083016 268
e315cd28 269 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 270}
271
a824ebb3 272static __inline__ void
e315cd28 273qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 274{
e315cd28
AC		 275 del_timer_sync(&vha->timer);
276 vha->timer_active = 0;
1da177e4
LT		 277}
278
1da177e4
LT		 279static int qla2x00_do_dpc(void *data);
280
281static void qla2x00_rst_aen(scsi_qla_host_t *);
282
73208dfd
AC		 283static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
284 struct req_que **, struct rsp_que **);
e30d1756 285static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28
AC		 286static void qla2x00_mem_free(struct qla_hw_data *);
287static void qla2x00_sp_free_dma(srb_t *);
1da177e4 288
1da177e4 289/* -------------------------------------------------------------------------- */
73208dfd
AC		 290static int qla2x00_alloc_queues(struct qla_hw_data *ha)
291{
7c3df132 292 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 293 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 294 GFP_KERNEL);
295 if (!ha->req_q_map) {
7c3df132
SK		 296 ql_log(ql_log_fatal, vha, 0x003b,
297 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 298 goto fail_req_map;
299 }
300
2afa19a9 301 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 302 GFP_KERNEL);
303 if (!ha->rsp_q_map) {
7c3df132
SK		 304 ql_log(ql_log_fatal, vha, 0x003c,
305 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 306 goto fail_rsp_map;
307 }
308 set_bit(0, ha->rsp_qid_map);
309 set_bit(0, ha->req_qid_map);
310 return 1;
311
312fail_rsp_map:
313 kfree(ha->req_q_map);
314 ha->req_q_map = NULL;
315fail_req_map:
316 return -ENOMEM;
317}
318
2afa19a9 319static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 320{
73208dfd
AC		 321 if (req && req->ring)
322 dma_free_coherent(&ha->pdev->dev,
323 (req->length + 1) * sizeof(request_t),
324 req->ring, req->dma);
325
326 kfree(req);
327 req = NULL;
328}
329
2afa19a9
AC		 330static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
331{
332 if (rsp && rsp->ring)
333 dma_free_coherent(&ha->pdev->dev,
334 (rsp->length + 1) * sizeof(response_t),
335 rsp->ring, rsp->dma);
336
337 kfree(rsp);
338 rsp = NULL;
339}
340
73208dfd
AC		 341static void qla2x00_free_queues(struct qla_hw_data *ha)
342{
343 struct req_que *req;
344 struct rsp_que *rsp;
345 int cnt;
346
2afa19a9 347 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
73208dfd 348 req = ha->req_q_map[cnt];
2afa19a9 349 qla2x00_free_req_que(ha, req);
73208dfd 350 }
73208dfd
AC		 351 kfree(ha->req_q_map);
352 ha->req_q_map = NULL;
2afa19a9
AC		 353
354 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
355 rsp = ha->rsp_q_map[cnt];
356 qla2x00_free_rsp_que(ha, rsp);
357 }
358 kfree(ha->rsp_q_map);
359 ha->rsp_q_map = NULL;
73208dfd
AC		 360}
361
68ca949c
AC		 362static int qla25xx_setup_mode(struct scsi_qla_host *vha)
363{
364 uint16_t options = 0;
365 int ques, req, ret;
366 struct qla_hw_data *ha = vha->hw;
367
7163ea81 368 if (!(ha->fw_attributes & BIT_6)) {
7c3df132
SK		 369 ql_log(ql_log_warn, vha, 0x00d8,
370 "Firmware is not multi-queue capable.\n");
7163ea81
AC		 371 goto fail;
372 }
68ca949c 373 if (ql2xmultique_tag) {
68ca949c
AC		 374 /* create a request queue for IO */
375 options |= BIT_7;
376 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
377 QLA_DEFAULT_QUE_QOS);
378 if (!req) {
7c3df132
SK		 379 ql_log(ql_log_warn, vha, 0x00e0,
380 "Failed to create request queue.\n");
68ca949c
AC		 381 goto fail;
382 }
278274d5 383 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
68ca949c
AC		 384 vha->req = ha->req_q_map[req];
385 options |= BIT_1;
386 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
387 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
388 if (!ret) {
7c3df132
SK		 389 ql_log(ql_log_warn, vha, 0x00e8,
390 "Failed to create response queue.\n");
68ca949c
AC		 391 goto fail2;
392 }
393 }
7163ea81 394 ha->flags.cpu_affinity_enabled = 1;
7c3df132
SK		 395 ql_dbg(ql_dbg_multiq, vha, 0xc007,
396 "CPU affinity mode enalbed, "
397 "no. of response queues:%d no. of request queues:%d.\n",
398 ha->max_rsp_queues, ha->max_req_queues);
399 ql_dbg(ql_dbg_init, vha, 0x00e9,
400 "CPU affinity mode enalbed, "
401 "no. of response queues:%d no. of request queues:%d.\n",
402 ha->max_rsp_queues, ha->max_req_queues);
68ca949c
AC		 403 }
404 return 0;
405fail2:
406 qla25xx_delete_queues(vha);
7163ea81
AC		 407 destroy_workqueue(ha->wq);
408 ha->wq = NULL;
68ca949c
AC		 409fail:
410 ha->mqenable = 0;
7163ea81
AC		 411 kfree(ha->req_q_map);
412 kfree(ha->rsp_q_map);
413 ha->max_req_queues = ha->max_rsp_queues = 1;
68ca949c
AC		 414 return 1;
415}
416
1da177e4 417static char *
e315cd28 418qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 419{
e315cd28 420 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 421 static char *pci_bus_modes[] = {
422 "33", "66", "100", "133",
423 };
424 uint16_t pci_bus;
425
426 strcpy(str, "PCI");
427 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
428 if (pci_bus) {
429 strcat(str, "-X (");
430 strcat(str, pci_bus_modes[pci_bus]);
431 } else {
432 pci_bus = (ha->pci_attr & BIT_8) >> 8;
433 strcat(str, " (");
434 strcat(str, pci_bus_modes[pci_bus]);
435 }
436 strcat(str, " MHz)");
437
438 return (str);
439}
440
fca29703 441static char *
e315cd28 442qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 443{
444 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 445 struct qla_hw_data *ha = vha->hw;
fca29703
AV		 446 uint32_t pci_bus;
447 int pcie_reg;
448
449 pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
450 if (pcie_reg) {
451 char lwstr[6];
452 uint16_t pcie_lstat, lspeed, lwidth;
453
454 pcie_reg += 0x12;
455 pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat);
456 lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
457 lwidth = (pcie_lstat &
458 (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4;
459
460 strcpy(str, "PCIe (");
461 if (lspeed == 1)
c87a0d8c 462 strcat(str, "2.5GT/s ");
c3a2f0df 463 else if (lspeed == 2)
c87a0d8c 464 strcat(str, "5.0GT/s ");
fca29703
AV		 465 else
466 strcat(str, "<unknown> ");
467 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
468 strcat(str, lwstr);
469
470 return str;
471 }
472
473 strcpy(str, "PCI");
474 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
475 if (pci_bus == 0 || pci_bus == 8) {
476 strcat(str, " (");
477 strcat(str, pci_bus_modes[pci_bus >> 3]);
478 } else {
479 strcat(str, "-X ");
480 if (pci_bus & BIT_2)
481 strcat(str, "Mode 2");
482 else
483 strcat(str, "Mode 1");
484 strcat(str, " (");
485 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
486 }
487 strcat(str, " MHz)");
488
489 return str;
490}
491
e5f82ab8 492static char *
e315cd28 493qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str)
1da177e4
LT		 494{
495 char un_str[10];
e315cd28 496 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 497
1da177e4
LT		 498 sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
499 ha->fw_minor_version,
500 ha->fw_subminor_version);
501
502 if (ha->fw_attributes & BIT_9) {
503 strcat(str, "FLX");
504 return (str);
505 }
506
507 switch (ha->fw_attributes & 0xFF) {
508 case 0x7:
509 strcat(str, "EF");
510 break;
511 case 0x17:
512 strcat(str, "TP");
513 break;
514 case 0x37:
515 strcat(str, "IP");
516 break;
517 case 0x77:
518 strcat(str, "VI");
519 break;
520 default:
521 sprintf(un_str, "(%x)", ha->fw_attributes);
522 strcat(str, un_str);
523 break;
524 }
525 if (ha->fw_attributes & 0x100)
526 strcat(str, "X");
527
528 return (str);
529}
530
e5f82ab8 531static char *
e315cd28 532qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
fca29703 533{
e315cd28 534 struct qla_hw_data *ha = vha->hw;
f0883ac6 535
3a03eb79
AV		 536 sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
537 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 538 return str;
fca29703
AV		 539}
540
541static inline srb_t *
e315cd28 542qla2x00_get_new_sp(scsi_qla_host_t *vha, fc_port_t *fcport,
f5e3e40b 543 struct scsi_cmnd *cmd)
fca29703
AV		 544{
545 srb_t *sp;
e315cd28 546 struct qla_hw_data *ha = vha->hw;
fca29703
AV		 547
548 sp = mempool_alloc(ha->srb_mempool, GFP_ATOMIC);
7c3df132
SK		 549 if (!sp) {
550 ql_log(ql_log_warn, vha, 0x3006,
551 "Memory allocation failed for sp.\n");
fca29703 552 return sp;
7c3df132 553 }
fca29703 554
083a469d 555 atomic_set(&sp->ref_count, 1);
fca29703
AV		 556 sp->fcport = fcport;
557 sp->cmd = cmd;
558 sp->flags = 0;
559 CMD_SP(cmd) = (void *)sp;
cf53b069 560 sp->ctx = NULL;
fca29703
AV		 561
562 return sp;
563}
564
1da177e4 565static int
f5e3e40b 566qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 567{
134ae078 568 scsi_qla_host_t *vha = shost_priv(host);
fca29703 569 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 570 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 571 struct qla_hw_data *ha = vha->hw;
572 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 573 srb_t *sp;
574 int rval;
575
85880801 576 if (ha->flags.eeh_busy) {
7c3df132
SK		 577 if (ha->flags.pci_channel_io_perm_failure) {
578 ql_dbg(ql_dbg_io, vha, 0x3001,
579 "PCI Channel IO permanent failure, exiting "
580 "cmd=%p.\n", cmd);
b9b12f73 581 cmd->result = DID_NO_CONNECT << 16;
7c3df132
SK		 582 } else {
583 ql_dbg(ql_dbg_io, vha, 0x3002,
584 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 585 cmd->result = DID_REQUEUE << 16;
7c3df132 586 }
14e660e6
SJ		 587 goto qc24_fail_command;
588 }
589
19a7b4ae
JSEC		 590 rval = fc_remote_port_chkready(rport);
591 if (rval) {
592 cmd->result = rval;
7c3df132
SK		 593 ql_dbg(ql_dbg_io, vha, 0x3003,
594 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
595 cmd, rval);
fca29703
AV		 596 goto qc24_fail_command;
597 }
598
bad75002
AE		 599 if (!vha->flags.difdix_supported &&
600 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 601 ql_dbg(ql_dbg_io, vha, 0x3004,
602 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
603 cmd);
bad75002
AE		 604 cmd->result = DID_NO_CONNECT << 16;
605 goto qc24_fail_command;
606 }
fca29703
AV		 607 if (atomic_read(&fcport->state) != FCS_ONLINE) {
608 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 609 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 610 ql_dbg(ql_dbg_io, vha, 0x3005,
611 "Returning DNC, fcport_state=%d loop_state=%d.\n",
612 atomic_read(&fcport->state),
613 atomic_read(&base_vha->loop_state));
fca29703
AV		 614 cmd->result = DID_NO_CONNECT << 16;
615 goto qc24_fail_command;
616 }
7b594131 617 goto qc24_target_busy;
fca29703
AV		 618 }
619
f5e3e40b 620 sp = qla2x00_get_new_sp(base_vha, fcport, cmd);
fca29703 621 if (!sp)
f5e3e40b 622 goto qc24_host_busy;
fca29703 623
e315cd28 624 rval = ha->isp_ops->start_scsi(sp);
7c3df132
SK		 625 if (rval != QLA_SUCCESS) {
626 ql_dbg(ql_dbg_io, vha, 0x3013,
627 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 628 goto qc24_host_busy_free_sp;
7c3df132 629 }
fca29703 630
fca29703
AV		 631 return 0;
632
633qc24_host_busy_free_sp:
e315cd28
AC		 634 qla2x00_sp_free_dma(sp);
635 mempool_free(sp, ha->srb_mempool);
fca29703 636
f5e3e40b 637qc24_host_busy:
fca29703
AV		 638 return SCSI_MLQUEUE_HOST_BUSY;
639
7b594131
MC		 640qc24_target_busy:
641 return SCSI_MLQUEUE_TARGET_BUSY;
642
fca29703 643qc24_fail_command:
f5e3e40b 644 cmd->scsi_done(cmd);
fca29703
AV		 645
646 return 0;
647}
648
1da177e4
LT		 649/*
650 * qla2x00_eh_wait_on_command
651 * Waits for the command to be returned by the Firmware for some
652 * max time.
653 *
654 * Input:
1da177e4 655 * cmd = Scsi Command to wait on.
1da177e4
LT		 656 *
657 * Return:
658 * Not Found : 0
659 * Found : 1
660 */
661static int
e315cd28 662qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 663{
fe74c71f
AV		 664#define ABORT_POLLING_PERIOD 1000
665#define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 666 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 667 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
668 struct qla_hw_data *ha = vha->hw;
f4f051eb 669 int ret = QLA_SUCCESS;
1da177e4 670
85880801 671 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 672 ql_dbg(ql_dbg_taskm, vha, 0x8005,
673 "Return:eh_wait.\n");
85880801
AV		 674 return ret;
675 }
676
d970432c 677 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 678 msleep(ABORT_POLLING_PERIOD);
f4f051eb 679 }
680 if (CMD_SP(cmd))
681 ret = QLA_FUNCTION_FAILED;
1da177e4 682
f4f051eb 683 return ret;
1da177e4
LT		 684}
685
686/*
687 * qla2x00_wait_for_hba_online
fa2a1ce5 688 * Wait till the HBA is online after going through
1da177e4
LT		 689 * <= MAX_RETRIES_OF_ISP_ABORT or
690 * finally HBA is disabled ie marked offline
691 *
692 * Input:
693 * ha - pointer to host adapter structure
fa2a1ce5
AV		 694 *
695 * Note:
1da177e4
LT		 696 * Does context switching-Release SPIN_LOCK
697 * (if any) before calling this routine.
698 *
699 * Return:
700 * Success (Adapter is online) : 0
701 * Failed (Adapter is offline/disabled) : 1
702 */
854165f4 703int
e315cd28 704qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 705{
fca29703
AV		 706 int return_status;
707 unsigned long wait_online;
e315cd28
AC		 708 struct qla_hw_data *ha = vha->hw;
709 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 710
fa2a1ce5 711 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 712 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
713 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
714 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
715 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 716
717 msleep(1000);
718 }
e315cd28 719 if (base_vha->flags.online)
fa2a1ce5 720 return_status = QLA_SUCCESS;
1da177e4
LT		 721 else
722 return_status = QLA_FUNCTION_FAILED;
723
1da177e4
LT		 724 return (return_status);
725}
726
86fbee86
LC		 727/*
728 * qla2x00_wait_for_reset_ready
729 * Wait till the HBA is online after going through
730 * <= MAX_RETRIES_OF_ISP_ABORT or
731 * finally HBA is disabled ie marked offline or flash
732 * operations are in progress.
733 *
734 * Input:
735 * ha - pointer to host adapter structure
736 *
737 * Note:
738 * Does context switching-Release SPIN_LOCK
739 * (if any) before calling this routine.
740 *
741 * Return:
742 * Success (Adapter is online/no flash ops) : 0
743 * Failed (Adapter is offline/disabled/flash ops in progress) : 1
744 */
3dbe756a 745static int
86fbee86
LC		 746qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha)
747{
748 int return_status;
749 unsigned long wait_online;
750 struct qla_hw_data *ha = vha->hw;
751 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
752
753 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
754 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
755 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
756 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
757 ha->optrom_state != QLA_SWAITING ||
758 ha->dpc_active) && time_before(jiffies, wait_online))
759 msleep(1000);
760
761 if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING)
762 return_status = QLA_SUCCESS;
763 else
764 return_status = QLA_FUNCTION_FAILED;
765
7c3df132
SK		 766 ql_dbg(ql_dbg_taskm, vha, 0x8019,
767 "%s return status=%d.\n", __func__, return_status);
86fbee86
LC		 768
769 return return_status;
770}
771
2533cf67
LC		 772int
773qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
774{
775 int return_status;
776 unsigned long wait_reset;
777 struct qla_hw_data *ha = vha->hw;
778 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
779
780 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
781 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
782 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
783 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
784 ha->dpc_active) && time_before(jiffies, wait_reset)) {
785
786 msleep(1000);
787
788 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
789 ha->flags.chip_reset_done)
790 break;
791 }
792 if (ha->flags.chip_reset_done)
793 return_status = QLA_SUCCESS;
794 else
795 return_status = QLA_FUNCTION_FAILED;
796
797 return return_status;
798}
799
1da177e4
LT		 800/*
801 * qla2x00_wait_for_loop_ready
802 * Wait for MAX_LOOP_TIMEOUT(5 min) value for loop
fa2a1ce5 803 * to be in LOOP_READY state.
1da177e4
LT		 804 * Input:
805 * ha - pointer to host adapter structure
fa2a1ce5
AV		 806 *
807 * Note:
1da177e4
LT		 808 * Does context switching-Release SPIN_LOCK
809 * (if any) before calling this routine.
fa2a1ce5 810 *
1da177e4
LT		 811 *
812 * Return:
813 * Success (LOOP_READY) : 0
814 * Failed (LOOP_NOT_READY) : 1
815 */
fa2a1ce5 816static inline int
e315cd28 817qla2x00_wait_for_loop_ready(scsi_qla_host_t *vha)
1da177e4
LT		 818{
819 int return_status = QLA_SUCCESS;
820 unsigned long loop_timeout ;
e315cd28
AC		 821 struct qla_hw_data *ha = vha->hw;
822 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 823
824 /* wait for 5 min at the max for loop to be ready */
fa2a1ce5 825 loop_timeout = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1da177e4 826
e315cd28
AC		 827 while ((!atomic_read(&base_vha->loop_down_timer) &&
828 atomic_read(&base_vha->loop_state) == LOOP_DOWN) ||
829 atomic_read(&base_vha->loop_state) != LOOP_READY) {
830 if (atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
57680080
RA		 831 return_status = QLA_FUNCTION_FAILED;
832 break;
833 }
1da177e4
LT		 834 msleep(1000);
835 if (time_after_eq(jiffies, loop_timeout)) {
836 return_status = QLA_FUNCTION_FAILED;
837 break;
838 }
839 }
fa2a1ce5 840 return (return_status);
1da177e4
LT		 841}
842
083a469d
GM		 843static void
844sp_get(struct srb *sp)
845{
846 atomic_inc(&sp->ref_count);
847}
848
1da177e4
LT		 849/**************************************************************************
850* qla2xxx_eh_abort
851*
852* Description:
853* The abort function will abort the specified command.
854*
855* Input:
856* cmd = Linux SCSI command packet to be aborted.
857*
858* Returns:
859* Either SUCCESS or FAILED.
860*
861* Note:
2ea00202 862* Only return FAILED if command not returned by firmware.
1da177e4 863**************************************************************************/
e5f82ab8 864static int
1da177e4
LT		 865qla2xxx_eh_abort(struct scsi_cmnd *cmd)
866{
e315cd28 867 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 868 srb_t *sp;
4e98d3b8 869 int ret;
f4f051eb 870 unsigned int id, lun;
18e144d3 871 unsigned long flags;
2ea00202 872 int wait = 0;
e315cd28 873 struct qla_hw_data *ha = vha->hw;
1da177e4 874
7c3df132
SK		 875 ql_dbg(ql_dbg_taskm, vha, 0x8000,
876 "Entered %s for cmd=%p.\n", __func__, cmd);
f4f051eb 877 if (!CMD_SP(cmd))
2ea00202 878 return SUCCESS;
1da177e4 879
4e98d3b8 880 ret = fc_block_scsi_eh(cmd);
7c3df132
SK		 881 ql_dbg(ql_dbg_taskm, vha, 0x8001,
882 "Return value of fc_block_scsi_eh=%d.\n", ret);
4e98d3b8
AV		 883 if (ret != 0)
884 return ret;
885 ret = SUCCESS;
886
f4f051eb 887 id = cmd->device->id;
888 lun = cmd->device->lun;
1da177e4 889
e315cd28 890 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 891 sp = (srb_t *) CMD_SP(cmd);
892 if (!sp) {
893 spin_unlock_irqrestore(&ha->hardware_lock, flags);
894 return SUCCESS;
895 }
1da177e4 896
7c3df132
SK		 897 ql_dbg(ql_dbg_taskm, vha, 0x8002,
898 "Aborting sp=%p cmd=%p from RISC ", sp, cmd);
17d98630 899
170babc3
MC		 900 /* Get a reference to the sp and drop the lock.*/
901 sp_get(sp);
083a469d 902
e315cd28 903 spin_unlock_irqrestore(&ha->hardware_lock, flags);
170babc3 904 if (ha->isp_ops->abort_command(sp)) {
7c3df132
SK		 905 ql_dbg(ql_dbg_taskm, vha, 0x8003,
906 "Abort command mbx failed for cmd=%p.\n", cmd);
170babc3 907 } else {
7c3df132
SK		 908 ql_dbg(ql_dbg_taskm, vha, 0x8004,
909 "Abort command mbx success.\n");
170babc3
MC		 910 wait = 1;
911 }
912 qla2x00_sp_compl(ha, sp);
1da177e4 913
f4f051eb 914 /* Wait for the command to be returned. */
2ea00202 915 if (wait) {
e315cd28 916 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132
SK		 917 ql_log(ql_log_warn, vha, 0x8006,
918 "Abort handler timed out for cmd=%p.\n", cmd);
2ea00202 919 ret = FAILED;
f4f051eb 920 }
1da177e4 921 }
1da177e4 922
7c3df132
SK		 923 ql_log(ql_log_info, vha, 0x801c,
924 "Abort command issued -- %d %x.\n", wait, ret);
1da177e4 925
f4f051eb 926 return ret;
927}
1da177e4 928
4d78c973 929int
e315cd28 930qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
4d78c973 931 unsigned int l, enum nexus_wait_type type)
f4f051eb 932{
17d98630 933 int cnt, match, status;
18e144d3 934 unsigned long flags;
e315cd28 935 struct qla_hw_data *ha = vha->hw;
73208dfd 936 struct req_que *req;
4d78c973 937 srb_t *sp;
1da177e4 938
523ec773 939 status = QLA_SUCCESS;
17d98630 940
e315cd28 941 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 942 req = vha->req;
17d98630
AC		 943 for (cnt = 1; status == QLA_SUCCESS &&
944 cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
945 sp = req->outstanding_cmds[cnt];
946 if (!sp)
523ec773 947 continue;
bad75002 948 if ((sp->ctx) && !IS_PROT_IO(sp))
cf53b069 949 continue;
17d98630
AC		 950 if (vha->vp_idx != sp->fcport->vha->vp_idx)
951 continue;
952 match = 0;
953 switch (type) {
954 case WAIT_HOST:
955 match = 1;
956 break;
957 case WAIT_TARGET:
958 match = sp->cmd->device->id == t;
959 break;
960 case WAIT_LUN:
961 match = (sp->cmd->device->id == t &&
962 sp->cmd->device->lun == l);
963 break;
73208dfd 964 }
17d98630
AC		 965 if (!match)
966 continue;
967
968 spin_unlock_irqrestore(&ha->hardware_lock, flags);
969 status = qla2x00_eh_wait_on_command(sp->cmd);
970 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 971 }
e315cd28 972 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 973
974 return status;
1da177e4
LT		 975}
976
523ec773
AV		 977static char *reset_errors[] = {
978 "HBA not online",
979 "HBA not ready",
980 "Task management failed",
981 "Waiting for command completions",
982};
1da177e4 983
e5f82ab8 984static int
523ec773 985__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
2afa19a9 986 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int))
1da177e4 987{
e315cd28 988 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 989 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 990 int err;
1da177e4 991
7c3df132
SK		 992 if (!fcport) {
993 ql_log(ql_log_warn, vha, 0x8007,
994 "fcport is NULL.\n");
523ec773 995 return FAILED;
7c3df132 996 }
1da177e4 997
4e98d3b8 998 err = fc_block_scsi_eh(cmd);
7c3df132
SK		 999 ql_dbg(ql_dbg_taskm, vha, 0x8008,
1000 "fc_block_scsi_eh ret=%d.\n", err);
4e98d3b8
AV		 1001 if (err != 0)
1002 return err;
1003
7c3df132
SK		 1004 ql_log(ql_log_info, vha, 0x8009,
1005 "%s RESET ISSUED for id %d lun %d cmd=%p.\n", name,
1006 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1007
523ec773 1008 err = 0;
7c3df132
SK		 1009 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1010 ql_log(ql_log_warn, vha, 0x800a,
1011 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1012 goto eh_reset_failed;
7c3df132 1013 }
523ec773 1014 err = 1;
7c3df132
SK		 1015 if (qla2x00_wait_for_loop_ready(vha) != QLA_SUCCESS) {
1016 ql_log(ql_log_warn, vha, 0x800b,
1017 "Wait for loop ready failed for cmd=%p.\n", cmd);
523ec773 1018 goto eh_reset_failed;
7c3df132 1019 }
523ec773 1020 err = 2;
2afa19a9 1021 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1022 != QLA_SUCCESS) {
1023 ql_log(ql_log_warn, vha, 0x800c,
1024 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1025 goto eh_reset_failed;
7c3df132 1026 }
523ec773 1027 err = 3;
e315cd28 1028 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1029 cmd->device->lun, type) != QLA_SUCCESS) {
1030 ql_log(ql_log_warn, vha, 0x800d,
1031 "wait for peding cmds failed for cmd=%p.\n", cmd);
523ec773 1032 goto eh_reset_failed;
7c3df132 1033 }
523ec773 1034
7c3df132
SK		 1035 ql_log(ql_log_info, vha, 0x800e,
1036 "%s RESET SUCCEEDED for id %d lun %d cmd=%p.\n", name,
1037 cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1038
1039 return SUCCESS;
1040
4d78c973 1041eh_reset_failed:
7c3df132
SK		 1042 ql_log(ql_log_info, vha, 0x800f,
1043 "%s RESET FAILED: %s for id %d lun %d cmd=%p.\n", name,
1044 reset_errors[err], cmd->device->id, cmd->device->lun);
523ec773
AV		 1045 return FAILED;
1046}
1da177e4 1047
523ec773
AV		 1048static int
1049qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1050{
e315cd28
AC		 1051 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1052 struct qla_hw_data *ha = vha->hw;
1da177e4 1053
523ec773
AV		 1054 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1055 ha->isp_ops->lun_reset);
1da177e4
LT		 1056}
1057
1da177e4 1058static int
523ec773 1059qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1060{
e315cd28
AC		 1061 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1062 struct qla_hw_data *ha = vha->hw;
1da177e4 1063
523ec773
AV		 1064 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1065 ha->isp_ops->target_reset);
1da177e4
LT		 1066}
1067
1da177e4
LT		 1068/**************************************************************************
1069* qla2xxx_eh_bus_reset
1070*
1071* Description:
1072* The bus reset function will reset the bus and abort any executing
1073* commands.
1074*
1075* Input:
1076* cmd = Linux SCSI command packet of the command that cause the
1077* bus reset.
1078*
1079* Returns:
1080* SUCCESS/FAILURE (defined as macro in scsi.h).
1081*
1082**************************************************************************/
e5f82ab8 1083static int
1da177e4
LT		 1084qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1085{
e315cd28 1086 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1087 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1088 int ret = FAILED;
f4f051eb 1089 unsigned int id, lun;
f4f051eb 1090
f4f051eb 1091 id = cmd->device->id;
1092 lun = cmd->device->lun;
1da177e4 1093
7c3df132
SK		 1094 if (!fcport) {
1095 ql_log(ql_log_warn, vha, 0x8010,
1096 "fcport is NULL.\n");
f4f051eb 1097 return ret;
7c3df132 1098 }
1da177e4 1099
4e98d3b8 1100 ret = fc_block_scsi_eh(cmd);
7c3df132
SK		 1101 ql_dbg(ql_dbg_taskm, vha, 0x8011,
1102 "fc_block_scsi_eh ret=%d.\n", ret);
4e98d3b8
AV		 1103 if (ret != 0)
1104 return ret;
1105 ret = FAILED;
1106
7c3df132
SK		 1107 ql_log(ql_log_info, vha, 0x8012,
1108 "BUS RESET ISSUED for id %d lun %d.\n", id, lun);
1da177e4 1109
e315cd28 1110 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1111 ql_log(ql_log_fatal, vha, 0x8013,
1112 "Wait for hba online failed board disabled.\n");
f4f051eb 1113 goto eh_bus_reset_done;
1da177e4
LT		 1114 }
1115
e315cd28
AC		 1116 if (qla2x00_wait_for_loop_ready(vha) == QLA_SUCCESS) {
1117 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
f4f051eb 1118 ret = SUCCESS;
1da177e4 1119 }
f4f051eb 1120 if (ret == FAILED)
1121 goto eh_bus_reset_done;
1da177e4 1122
9a41a62b 1123 /* Flush outstanding commands. */
4d78c973 1124 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1125 QLA_SUCCESS) {
1126 ql_log(ql_log_warn, vha, 0x8014,
1127 "Wait for pending commands failed.\n");
9a41a62b 1128 ret = FAILED;
7c3df132 1129 }
1da177e4 1130
f4f051eb 1131eh_bus_reset_done:
7c3df132
SK		 1132 ql_log(ql_log_warn, vha, 0x802b,
1133 "BUS RESET %s.\n", (ret == FAILED) ? "FAILED" : "SUCCEDED");
1da177e4 1134
f4f051eb 1135 return ret;
1da177e4
LT		 1136}
1137
1138/**************************************************************************
1139* qla2xxx_eh_host_reset
1140*
1141* Description:
1142* The reset function will reset the Adapter.
1143*
1144* Input:
1145* cmd = Linux SCSI command packet of the command that cause the
1146* adapter reset.
1147*
1148* Returns:
1149* Either SUCCESS or FAILED.
1150*
1151* Note:
1152**************************************************************************/
e5f82ab8 1153static int
1da177e4
LT		 1154qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1155{
e315cd28 1156 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1157 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
e315cd28 1158 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1159 int ret = FAILED;
f4f051eb 1160 unsigned int id, lun;
e315cd28 1161 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1162
f4f051eb 1163 id = cmd->device->id;
1164 lun = cmd->device->lun;
f4f051eb 1165
7c3df132
SK		 1166 if (!fcport) {
1167 ql_log(ql_log_warn, vha, 0x8016,
1168 "fcport is NULL.\n");
f4f051eb 1169 return ret;
7c3df132 1170 }
1da177e4 1171
4e98d3b8 1172 ret = fc_block_scsi_eh(cmd);
7c3df132
SK		 1173 ql_dbg(ql_dbg_taskm, vha, 0x8017,
1174 "fc_block_scsi_eh ret=%d.\n", ret);
4e98d3b8
AV		 1175 if (ret != 0)
1176 return ret;
1177 ret = FAILED;
1178
7c3df132
SK		 1179 ql_log(ql_log_info, vha, 0x8018,
1180 "ADAPTER RESET ISSUED for id %d lun %d.\n", id, lun);
1da177e4 1181
86fbee86 1182 if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS)
f4f051eb 1183 goto eh_host_reset_lock;
1da177e4
LT		 1184
1185 /*
1186 * Fixme-may be dpc thread is active and processing
fa2a1ce5 1187 * loop_resync,so wait a while for it to
1da177e4
LT		 1188 * be completed and then issue big hammer.Otherwise
1189 * it may cause I/O failure as big hammer marks the
1190 * devices as lost kicking of the port_down_timer
1191 * while dpc is stuck for the mailbox to complete.
1192 */
e315cd28
AC		 1193 qla2x00_wait_for_loop_ready(vha);
1194 if (vha != base_vha) {
1195 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1196 goto eh_host_reset_lock;
e315cd28 1197 } else {
a9083016
GM		 1198 if (IS_QLA82XX(vha->hw)) {
1199 if (!qla82xx_fcoe_ctx_reset(vha)) {
1200 /* Ctx reset success */
1201 ret = SUCCESS;
1202 goto eh_host_reset_lock;
1203 }
1204 /* fall thru if ctx reset failed */
1205 }
68ca949c
AC		 1206 if (ha->wq)
1207 flush_workqueue(ha->wq);
1208
e315cd28 1209 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1210 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1211 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1212 /* failed. schedule dpc to try */
1213 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1214
7c3df132
SK		 1215 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1216 ql_log(ql_log_warn, vha, 0x802a,
1217 "wait for hba online failed.\n");
e315cd28 1218 goto eh_host_reset_lock;
7c3df132 1219 }
e315cd28
AC		 1220 }
1221 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1222 }
1da177e4 1223
e315cd28 1224 /* Waiting for command to be returned to OS.*/
4d78c973 1225 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1226 QLA_SUCCESS)
f4f051eb 1227 ret = SUCCESS;
1da177e4 1228
f4f051eb 1229eh_host_reset_lock:
7c3df132 1230 qla_printk(KERN_INFO, ha, "%s: reset %s.\n", __func__,
25985edc 1231 (ret == FAILED) ? "failed" : "succeeded");
1da177e4 1232
f4f051eb 1233 return ret;
1234}
1da177e4
LT		 1235
1236/*
1237* qla2x00_loop_reset
1238* Issue loop reset.
1239*
1240* Input:
1241* ha = adapter block pointer.
1242*
1243* Returns:
1244* 0 = success
1245*/
a4722cf2 1246int
e315cd28 1247qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1248{
0c8c39af 1249 int ret;
bdf79621 1250 struct fc_port *fcport;
e315cd28 1251 struct qla_hw_data *ha = vha->hw;
1da177e4 1252
f4c496c1 1253 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1254 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1255 if (fcport->port_type != FCT_TARGET)
1256 continue;
1257
1258 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1259 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1260 ql_dbg(ql_dbg_taskm, vha, 0x802c,
1261 "Bus Reset failed: Target Reset=%d "
1262 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1263 }
1264 }
1265 }
1266
a9083016 1267 if (ha->flags.enable_lip_full_login && !IS_QLA8XXX_TYPE(ha)) {
e315cd28 1268 ret = qla2x00_full_login_lip(vha);
0c8c39af 1269 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1270 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1271 "full_login_lip=%d.\n", ret);
749af3d5
AC		 1272 }
1273 atomic_set(&vha->loop_state, LOOP_DOWN);
1274 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1275 qla2x00_mark_all_devices_lost(vha, 0);
1276 qla2x00_wait_for_loop_ready(vha);
0c8c39af
AV		 1277 }
1278
0d6e61bc 1279 if (ha->flags.enable_lip_reset) {
e315cd28 1280 ret = qla2x00_lip_reset(vha);
0c8c39af 1281 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1282 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1283 "lip_reset failed (%d).\n", ret);
e315cd28
AC		 1284 } else
1285 qla2x00_wait_for_loop_ready(vha);
1da177e4
LT		 1286 }
1287
1da177e4 1288 /* Issue marker command only when we are going to start the I/O */
e315cd28 1289 vha->marker_needed = 1;
1da177e4 1290
0c8c39af 1291 return QLA_SUCCESS;
1da177e4
LT		 1292}
1293
df4bf0bb 1294void
e315cd28 1295qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1296{
73208dfd 1297 int que, cnt;
df4bf0bb
AV		 1298 unsigned long flags;
1299 srb_t *sp;
ac280b67 1300 struct srb_ctx *ctx;
e315cd28 1301 struct qla_hw_data *ha = vha->hw;
73208dfd 1302 struct req_que *req;
df4bf0bb
AV		 1303
1304 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1305 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1306 req = ha->req_q_map[que];
73208dfd
AC		 1307 if (!req)
1308 continue;
1309 for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
1310 sp = req->outstanding_cmds[cnt];
e612d465 1311 if (sp) {
73208dfd 1312 req->outstanding_cmds[cnt] = NULL;
a9083016 1313 if (!sp->ctx ||
bad75002
AE		 1314 (sp->flags & SRB_FCP_CMND_DMA_VALID) ||
1315 IS_PROT_IO(sp)) {
ac280b67
AV		 1316 sp->cmd->result = res;
1317 qla2x00_sp_compl(ha, sp);
1318 } else {
1319 ctx = sp->ctx;
6c452a45
AV		 1320 if (ctx->type == SRB_LOGIN_CMD ||
1321 ctx->type == SRB_LOGOUT_CMD) {
4916392b 1322 ctx->u.iocb_cmd->free(sp);
db3ad7f8 1323 } else {
6c452a45 1324 struct fc_bsg_job *bsg_job =
4916392b 1325 ctx->u.bsg_job;
6c452a45
AV		 1326 if (bsg_job->request->msgcode
1327 == FC_BSG_HST_CT)
db3ad7f8 1328 kfree(sp->fcport);
6c452a45
AV		 1329 bsg_job->req->errors = 0;
1330 bsg_job->reply->result = res;
4916392b 1331 bsg_job->job_done(bsg_job);
db3ad7f8 1332 kfree(sp->ctx);
6c452a45 1333 mempool_free(sp,
4916392b 1334 ha->srb_mempool);
db3ad7f8 1335 }
ac280b67 1336 }
73208dfd 1337 }
df4bf0bb
AV		 1338 }
1339 }
1340 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1341}
1342
f4f051eb 1343static int
1344qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1345{
bdf79621 1346 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1347
19a7b4ae 1348 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1349 return -ENXIO;
bdf79621 1350
19a7b4ae 1351 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1352
f4f051eb 1353 return 0;
1354}
1da177e4 1355
f4f051eb 1356static int
1357qla2xxx_slave_configure(struct scsi_device *sdev)
1358{
e315cd28 1359 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1360 struct req_que *req = vha->req;
8482e118 1361
f4f051eb 1362 if (sdev->tagged_supported)
73208dfd 1363 scsi_activate_tcq(sdev, req->max_q_depth);
f4f051eb 1364 else
73208dfd 1365 scsi_deactivate_tcq(sdev, req->max_q_depth);
f4f051eb 1366 return 0;
1367}
1da177e4 1368
f4f051eb 1369static void
1370qla2xxx_slave_destroy(struct scsi_device *sdev)
1371{
1372 sdev->hostdata = NULL;
1da177e4
LT		 1373}
1374
c45dd305
GM		 1375static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
1376{
1377 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1378
1379 if (!scsi_track_queue_full(sdev, qdepth))
1380 return;
1381
7c3df132
SK		 1382 ql_dbg(ql_dbg_io, fcport->vha, 0x3029,
1383 "Queue depth adjusted-down "
1384 "to %d for scsi(%ld:%d:%d:%d).\n",
1385 sdev->queue_depth, fcport->vha->host_no,
1386 sdev->channel, sdev->id, sdev->lun);
c45dd305
GM		 1387}
1388
1389static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
1390{
1391 fc_port_t *fcport = sdev->hostdata;
1392 struct scsi_qla_host *vha = fcport->vha;
c45dd305
GM		 1393 struct req_que *req = NULL;
1394
1395 req = vha->req;
1396 if (!req)
1397 return;
1398
1399 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
1400 return;
1401
1402 if (sdev->ordered_tags)
1403 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
1404 else
1405 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
1406
7c3df132
SK		 1407 ql_dbg(ql_dbg_io, vha, 0x302a,
1408 "Queue depth adjusted-up to %d for "
1409 "scsi(%ld:%d:%d:%d).\n",
1410 sdev->queue_depth, fcport->vha->host_no,
1411 sdev->channel, sdev->id, sdev->lun);
c45dd305
GM		 1412}
1413
ce7e4af7 1414static int
e881a172 1415qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
ce7e4af7 1416{
c45dd305
GM		 1417 switch (reason) {
1418 case SCSI_QDEPTH_DEFAULT:
1419 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
1420 break;
1421 case SCSI_QDEPTH_QFULL:
1422 qla2x00_handle_queue_full(sdev, qdepth);
1423 break;
1424 case SCSI_QDEPTH_RAMP_UP:
1425 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
1426 break;
1427 default:
08002af2 1428 return -EOPNOTSUPP;
c45dd305 1429 }
e881a172 1430
ce7e4af7
AV		 1431 return sdev->queue_depth;
1432}
1433
1434static int
1435qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
1436{
1437 if (sdev->tagged_supported) {
1438 scsi_set_tag_type(sdev, tag_type);
1439 if (tag_type)
1440 scsi_activate_tcq(sdev, sdev->queue_depth);
1441 else
1442 scsi_deactivate_tcq(sdev, sdev->queue_depth);
1443 } else
1444 tag_type = 0;
1445
1446 return tag_type;
1447}
1448
1da177e4
LT		 1449/**
1450 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1451 * @ha: HA context
1452 *
1453 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1454 * supported addressing method.
1455 */
1456static void
53303c42 1457qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1458{
7524f9b9 1459 /* Assume a 32bit DMA mask. */
1da177e4 1460 ha->flags.enable_64bit_addressing = 0;
1da177e4 1461
6a35528a 1462 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1463 /* Any upper-dword bits set? */
1464 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1465 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1466 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1467 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1468 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1469 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1470 return;
1da177e4 1471 }
1da177e4 1472 }
7524f9b9 1473
284901a9
YH		 1474 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1475 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1476}
1477
fd34f556 1478static void
e315cd28 1479qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1480{
1481 unsigned long flags = 0;
1482 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1483
1484 spin_lock_irqsave(&ha->hardware_lock, flags);
1485 ha->interrupts_on = 1;
1486 /* enable risc and host interrupts */
1487 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1488 RD_REG_WORD(&reg->ictrl);
1489 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1490
1491}
1492
1493static void
e315cd28 1494qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1495{
1496 unsigned long flags = 0;
1497 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1498
1499 spin_lock_irqsave(&ha->hardware_lock, flags);
1500 ha->interrupts_on = 0;
1501 /* disable risc and host interrupts */
1502 WRT_REG_WORD(&reg->ictrl, 0);
1503 RD_REG_WORD(&reg->ictrl);
1504 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1505}
1506
1507static void
e315cd28 1508qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1509{
1510 unsigned long flags = 0;
1511 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1512
1513 spin_lock_irqsave(&ha->hardware_lock, flags);
1514 ha->interrupts_on = 1;
1515 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1516 RD_REG_DWORD(&reg->ictrl);
1517 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1518}
1519
1520static void
e315cd28 1521qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1522{
1523 unsigned long flags = 0;
1524 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1525
124f85e6
AV		 1526 if (IS_NOPOLLING_TYPE(ha))
1527 return;
fd34f556
AV		 1528 spin_lock_irqsave(&ha->hardware_lock, flags);
1529 ha->interrupts_on = 0;
1530 WRT_REG_DWORD(&reg->ictrl, 0);
1531 RD_REG_DWORD(&reg->ictrl);
1532 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1533}
1534
1535static struct isp_operations qla2100_isp_ops = {
1536 .pci_config = qla2100_pci_config,
1537 .reset_chip = qla2x00_reset_chip,
1538 .chip_diag = qla2x00_chip_diag,
1539 .config_rings = qla2x00_config_rings,
1540 .reset_adapter = qla2x00_reset_adapter,
1541 .nvram_config = qla2x00_nvram_config,
1542 .update_fw_options = qla2x00_update_fw_options,
1543 .load_risc = qla2x00_load_risc,
1544 .pci_info_str = qla2x00_pci_info_str,
1545 .fw_version_str = qla2x00_fw_version_str,
1546 .intr_handler = qla2100_intr_handler,
1547 .enable_intrs = qla2x00_enable_intrs,
1548 .disable_intrs = qla2x00_disable_intrs,
1549 .abort_command = qla2x00_abort_command,
523ec773
AV		 1550 .target_reset = qla2x00_abort_target,
1551 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1552 .fabric_login = qla2x00_login_fabric,
1553 .fabric_logout = qla2x00_fabric_logout,
1554 .calc_req_entries = qla2x00_calc_iocbs_32,
1555 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1556 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1557 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1558 .read_nvram = qla2x00_read_nvram_data,
1559 .write_nvram = qla2x00_write_nvram_data,
1560 .fw_dump = qla2100_fw_dump,
1561 .beacon_on = NULL,
1562 .beacon_off = NULL,
1563 .beacon_blink = NULL,
1564 .read_optrom = qla2x00_read_optrom_data,
1565 .write_optrom = qla2x00_write_optrom_data,
1566 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1567 .start_scsi = qla2x00_start_scsi,
a9083016 1568 .abort_isp = qla2x00_abort_isp,
fd34f556
AV		 1569};
1570
1571static struct isp_operations qla2300_isp_ops = {
1572 .pci_config = qla2300_pci_config,
1573 .reset_chip = qla2x00_reset_chip,
1574 .chip_diag = qla2x00_chip_diag,
1575 .config_rings = qla2x00_config_rings,
1576 .reset_adapter = qla2x00_reset_adapter,
1577 .nvram_config = qla2x00_nvram_config,
1578 .update_fw_options = qla2x00_update_fw_options,
1579 .load_risc = qla2x00_load_risc,
1580 .pci_info_str = qla2x00_pci_info_str,
1581 .fw_version_str = qla2x00_fw_version_str,
1582 .intr_handler = qla2300_intr_handler,
1583 .enable_intrs = qla2x00_enable_intrs,
1584 .disable_intrs = qla2x00_disable_intrs,
1585 .abort_command = qla2x00_abort_command,
523ec773
AV		 1586 .target_reset = qla2x00_abort_target,
1587 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1588 .fabric_login = qla2x00_login_fabric,
1589 .fabric_logout = qla2x00_fabric_logout,
1590 .calc_req_entries = qla2x00_calc_iocbs_32,
1591 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1592 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1593 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1594 .read_nvram = qla2x00_read_nvram_data,
1595 .write_nvram = qla2x00_write_nvram_data,
1596 .fw_dump = qla2300_fw_dump,
1597 .beacon_on = qla2x00_beacon_on,
1598 .beacon_off = qla2x00_beacon_off,
1599 .beacon_blink = qla2x00_beacon_blink,
1600 .read_optrom = qla2x00_read_optrom_data,
1601 .write_optrom = qla2x00_write_optrom_data,
1602 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1603 .start_scsi = qla2x00_start_scsi,
a9083016 1604 .abort_isp = qla2x00_abort_isp,
fd34f556
AV		 1605};
1606
1607static struct isp_operations qla24xx_isp_ops = {
1608 .pci_config = qla24xx_pci_config,
1609 .reset_chip = qla24xx_reset_chip,
1610 .chip_diag = qla24xx_chip_diag,
1611 .config_rings = qla24xx_config_rings,
1612 .reset_adapter = qla24xx_reset_adapter,
1613 .nvram_config = qla24xx_nvram_config,
1614 .update_fw_options = qla24xx_update_fw_options,
1615 .load_risc = qla24xx_load_risc,
1616 .pci_info_str = qla24xx_pci_info_str,
1617 .fw_version_str = qla24xx_fw_version_str,
1618 .intr_handler = qla24xx_intr_handler,
1619 .enable_intrs = qla24xx_enable_intrs,
1620 .disable_intrs = qla24xx_disable_intrs,
1621 .abort_command = qla24xx_abort_command,
523ec773
AV		 1622 .target_reset = qla24xx_abort_target,
1623 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 1624 .fabric_login = qla24xx_login_fabric,
1625 .fabric_logout = qla24xx_fabric_logout,
1626 .calc_req_entries = NULL,
1627 .build_iocbs = NULL,
1628 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1629 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1630 .read_nvram = qla24xx_read_nvram_data,
1631 .write_nvram = qla24xx_write_nvram_data,
1632 .fw_dump = qla24xx_fw_dump,
1633 .beacon_on = qla24xx_beacon_on,
1634 .beacon_off = qla24xx_beacon_off,
1635 .beacon_blink = qla24xx_beacon_blink,
1636 .read_optrom = qla24xx_read_optrom_data,
1637 .write_optrom = qla24xx_write_optrom_data,
1638 .get_flash_version = qla24xx_get_flash_version,
e315cd28 1639 .start_scsi = qla24xx_start_scsi,
a9083016 1640 .abort_isp = qla2x00_abort_isp,
fd34f556
AV		 1641};
1642
c3a2f0df
AV		 1643static struct isp_operations qla25xx_isp_ops = {
1644 .pci_config = qla25xx_pci_config,
1645 .reset_chip = qla24xx_reset_chip,
1646 .chip_diag = qla24xx_chip_diag,
1647 .config_rings = qla24xx_config_rings,
1648 .reset_adapter = qla24xx_reset_adapter,
1649 .nvram_config = qla24xx_nvram_config,
1650 .update_fw_options = qla24xx_update_fw_options,
1651 .load_risc = qla24xx_load_risc,
1652 .pci_info_str = qla24xx_pci_info_str,
1653 .fw_version_str = qla24xx_fw_version_str,
1654 .intr_handler = qla24xx_intr_handler,
1655 .enable_intrs = qla24xx_enable_intrs,
1656 .disable_intrs = qla24xx_disable_intrs,
1657 .abort_command = qla24xx_abort_command,
523ec773
AV		 1658 .target_reset = qla24xx_abort_target,
1659 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 1660 .fabric_login = qla24xx_login_fabric,
1661 .fabric_logout = qla24xx_fabric_logout,
1662 .calc_req_entries = NULL,
1663 .build_iocbs = NULL,
1664 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1665 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1666 .read_nvram = qla25xx_read_nvram_data,
1667 .write_nvram = qla25xx_write_nvram_data,
1668 .fw_dump = qla25xx_fw_dump,
1669 .beacon_on = qla24xx_beacon_on,
1670 .beacon_off = qla24xx_beacon_off,
1671 .beacon_blink = qla24xx_beacon_blink,
338c9161 1672 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 1673 .write_optrom = qla24xx_write_optrom_data,
1674 .get_flash_version = qla24xx_get_flash_version,
bad75002 1675 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1676 .abort_isp = qla2x00_abort_isp,
c3a2f0df
AV		 1677};
1678
3a03eb79
AV		 1679static struct isp_operations qla81xx_isp_ops = {
1680 .pci_config = qla25xx_pci_config,
1681 .reset_chip = qla24xx_reset_chip,
1682 .chip_diag = qla24xx_chip_diag,
1683 .config_rings = qla24xx_config_rings,
1684 .reset_adapter = qla24xx_reset_adapter,
1685 .nvram_config = qla81xx_nvram_config,
1686 .update_fw_options = qla81xx_update_fw_options,
eaac30be 1687 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 1688 .pci_info_str = qla24xx_pci_info_str,
1689 .fw_version_str = qla24xx_fw_version_str,
1690 .intr_handler = qla24xx_intr_handler,
1691 .enable_intrs = qla24xx_enable_intrs,
1692 .disable_intrs = qla24xx_disable_intrs,
1693 .abort_command = qla24xx_abort_command,
1694 .target_reset = qla24xx_abort_target,
1695 .lun_reset = qla24xx_lun_reset,
1696 .fabric_login = qla24xx_login_fabric,
1697 .fabric_logout = qla24xx_fabric_logout,
1698 .calc_req_entries = NULL,
1699 .build_iocbs = NULL,
1700 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1701 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 1702 .read_nvram = NULL,
1703 .write_nvram = NULL,
3a03eb79
AV		 1704 .fw_dump = qla81xx_fw_dump,
1705 .beacon_on = qla24xx_beacon_on,
1706 .beacon_off = qla24xx_beacon_off,
1707 .beacon_blink = qla24xx_beacon_blink,
1708 .read_optrom = qla25xx_read_optrom_data,
1709 .write_optrom = qla24xx_write_optrom_data,
1710 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 1711 .start_scsi = qla24xx_dif_start_scsi,
a9083016
GM		 1712 .abort_isp = qla2x00_abort_isp,
1713};
1714
1715static struct isp_operations qla82xx_isp_ops = {
1716 .pci_config = qla82xx_pci_config,
1717 .reset_chip = qla82xx_reset_chip,
1718 .chip_diag = qla24xx_chip_diag,
1719 .config_rings = qla82xx_config_rings,
1720 .reset_adapter = qla24xx_reset_adapter,
1721 .nvram_config = qla81xx_nvram_config,
1722 .update_fw_options = qla24xx_update_fw_options,
1723 .load_risc = qla82xx_load_risc,
1724 .pci_info_str = qla82xx_pci_info_str,
1725 .fw_version_str = qla24xx_fw_version_str,
1726 .intr_handler = qla82xx_intr_handler,
1727 .enable_intrs = qla82xx_enable_intrs,
1728 .disable_intrs = qla82xx_disable_intrs,
1729 .abort_command = qla24xx_abort_command,
1730 .target_reset = qla24xx_abort_target,
1731 .lun_reset = qla24xx_lun_reset,
1732 .fabric_login = qla24xx_login_fabric,
1733 .fabric_logout = qla24xx_fabric_logout,
1734 .calc_req_entries = NULL,
1735 .build_iocbs = NULL,
1736 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1737 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1738 .read_nvram = qla24xx_read_nvram_data,
1739 .write_nvram = qla24xx_write_nvram_data,
1740 .fw_dump = qla24xx_fw_dump,
1741 .beacon_on = qla24xx_beacon_on,
1742 .beacon_off = qla24xx_beacon_off,
1743 .beacon_blink = qla24xx_beacon_blink,
1744 .read_optrom = qla82xx_read_optrom_data,
1745 .write_optrom = qla82xx_write_optrom_data,
1746 .get_flash_version = qla24xx_get_flash_version,
1747 .start_scsi = qla82xx_start_scsi,
1748 .abort_isp = qla82xx_abort_isp,
3a03eb79
AV		 1749};
1750
ea5b6382 1751static inline void
e315cd28 1752qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382 1753{
1754 ha->device_type = DT_EXTENDED_IDS;
1755 switch (ha->pdev->device) {
1756 case PCI_DEVICE_ID_QLOGIC_ISP2100:
1757 ha->device_type |= DT_ISP2100;
1758 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 1759 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 1760 break;
1761 case PCI_DEVICE_ID_QLOGIC_ISP2200:
1762 ha->device_type |= DT_ISP2200;
1763 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 1764 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 1765 break;
1766 case PCI_DEVICE_ID_QLOGIC_ISP2300:
1767 ha->device_type |= DT_ISP2300;
4a59f71d 1768 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 1769 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 1770 break;
1771 case PCI_DEVICE_ID_QLOGIC_ISP2312:
1772 ha->device_type |= DT_ISP2312;
4a59f71d 1773 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 1774 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 1775 break;
1776 case PCI_DEVICE_ID_QLOGIC_ISP2322:
1777 ha->device_type |= DT_ISP2322;
4a59f71d 1778 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382 1779 if (ha->pdev->subsystem_vendor == 0x1028 &&
1780 ha->pdev->subsystem_device == 0x0170)
1781 ha->device_type |= DT_OEM_001;
441d1072 1782 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 1783 break;
1784 case PCI_DEVICE_ID_QLOGIC_ISP6312:
1785 ha->device_type |= DT_ISP6312;
441d1072 1786 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 1787 break;
1788 case PCI_DEVICE_ID_QLOGIC_ISP6322:
1789 ha->device_type |= DT_ISP6322;
441d1072 1790 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 1791 break;
1792 case PCI_DEVICE_ID_QLOGIC_ISP2422:
1793 ha->device_type |= DT_ISP2422;
4a59f71d 1794 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 1795 ha->device_type |= DT_FWI2;
c76f2c01 1796 ha->device_type |= DT_IIDMA;
441d1072 1797 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 1798 break;
1799 case PCI_DEVICE_ID_QLOGIC_ISP2432:
1800 ha->device_type |= DT_ISP2432;
4a59f71d 1801 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 1802 ha->device_type |= DT_FWI2;
c76f2c01 1803 ha->device_type |= DT_IIDMA;
441d1072 1804 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 1805 break;
4d4df193
HK		 1806 case PCI_DEVICE_ID_QLOGIC_ISP8432:
1807 ha->device_type |= DT_ISP8432;
1808 ha->device_type |= DT_ZIO_SUPPORTED;
1809 ha->device_type |= DT_FWI2;
1810 ha->device_type |= DT_IIDMA;
1811 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1812 break;
044cc6c8 1813 case PCI_DEVICE_ID_QLOGIC_ISP5422:
1814 ha->device_type |= DT_ISP5422;
e428924c 1815 ha->device_type |= DT_FWI2;
441d1072 1816 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 1817 break;
044cc6c8 1818 case PCI_DEVICE_ID_QLOGIC_ISP5432:
1819 ha->device_type |= DT_ISP5432;
e428924c 1820 ha->device_type |= DT_FWI2;
441d1072 1821 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 1822 break;
c3a2f0df
AV		 1823 case PCI_DEVICE_ID_QLOGIC_ISP2532:
1824 ha->device_type |= DT_ISP2532;
1825 ha->device_type |= DT_ZIO_SUPPORTED;
1826 ha->device_type |= DT_FWI2;
1827 ha->device_type |= DT_IIDMA;
441d1072 1828 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 1829 break;
3a03eb79
AV		 1830 case PCI_DEVICE_ID_QLOGIC_ISP8001:
1831 ha->device_type |= DT_ISP8001;
1832 ha->device_type |= DT_ZIO_SUPPORTED;
1833 ha->device_type |= DT_FWI2;
1834 ha->device_type |= DT_IIDMA;
1835 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1836 break;
a9083016
GM		 1837 case PCI_DEVICE_ID_QLOGIC_ISP8021:
1838 ha->device_type |= DT_ISP8021;
1839 ha->device_type |= DT_ZIO_SUPPORTED;
1840 ha->device_type |= DT_FWI2;
1841 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1842 /* Initialize 82XX ISP flags */
1843 qla82xx_init_flags(ha);
1844 break;
ea5b6382 1845 }
e5b68a61 1846
a9083016
GM		 1847 if (IS_QLA82XX(ha))
1848 ha->port_no = !(ha->portnum & 1);
1849 else
1850 /* Get adapter physical port no from interrupt pin register. */
1851 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
1852
e5b68a61
AC		 1853 if (ha->port_no & 1)
1854 ha->flags.port0 = 1;
1855 else
1856 ha->flags.port0 = 0;
7c3df132
SK		 1857 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
1858 "device_type=0x%x port=%d fw_srisc_address=%p.\n",
1859 ha->device_type, ha->flags.port0, ha->fw_srisc_address);
ea5b6382 1860}
1861
1da177e4 1862static int
e315cd28 1863qla2x00_iospace_config(struct qla_hw_data *ha)
1da177e4 1864{
3776541d 1865 resource_size_t pio;
73208dfd 1866 uint16_t msix;
68ca949c 1867 int cpus;
1da177e4 1868
a9083016
GM		 1869 if (IS_QLA82XX(ha))
1870 return qla82xx_iospace_config(ha);
1871
285d0321
AV		 1872 if (pci_request_selected_regions(ha->pdev, ha->bars,
1873 QLA2XXX_DRIVER_NAME)) {
7c3df132
SK		 1874 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1875 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
285d0321 1876 pci_name(ha->pdev));
285d0321
AV		 1877 goto iospace_error_exit;
1878 }
1879 if (!(ha->bars & 1))
1880 goto skip_pio;
1881
1da177e4
LT		 1882 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1883 pio = pci_resource_start(ha->pdev, 0);
3776541d
AV		 1884 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1885 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
7c3df132
SK		 1886 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1887 "Invalid pci I/O region size (%s).\n",
1888 pci_name(ha->pdev));
1da177e4
LT		 1889 pio = 0;
1890 }
1891 } else {
7c3df132
SK		 1892 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1893 "Region #0 no a PIO resource (%s).\n",
1da177e4
LT		 1894 pci_name(ha->pdev));
1895 pio = 0;
1896 }
285d0321 1897 ha->pio_address = pio;
7c3df132
SK		 1898 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1899 "PIO address=%p.\n",
1900 ha->pio_address);
1da177e4 1901
285d0321 1902skip_pio:
1da177e4 1903 /* Use MMIO operations for all accesses. */
3776541d 1904 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
7c3df132
SK		 1905 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1906 "Region #1 not an MMIO resource (%s), aborting.\n",
1da177e4
LT		 1907 pci_name(ha->pdev));
1908 goto iospace_error_exit;
1909 }
3776541d 1910 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
7c3df132
SK		 1911 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1912 "Invalid PCI mem region size (%s), aborting.\n",
1913 pci_name(ha->pdev));
1da177e4
LT		 1914 goto iospace_error_exit;
1915 }
1916
3776541d 1917 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1da177e4 1918 if (!ha->iobase) {
7c3df132
SK		 1919 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1920 "Cannot remap MMIO (%s), aborting.\n",
1921 pci_name(ha->pdev));
1da177e4
LT		 1922 goto iospace_error_exit;
1923 }
1924
73208dfd 1925 /* Determine queue resources */
2afa19a9 1926 ha->max_req_queues = ha->max_rsp_queues = 1;
d84a47c2
MH		 1927 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1928 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
2afa19a9 1929 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
17d98630 1930 goto mqiobase_exit;
d84a47c2 1931
17d98630
AC		 1932 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1933 pci_resource_len(ha->pdev, 3));
1934 if (ha->mqiobase) {
7c3df132
SK		 1935 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1936 "MQIO Base=%p.\n", ha->mqiobase);
17d98630
AC		 1937 /* Read MSIX vector size of the board */
1938 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1939 ha->msix_count = msix;
68ca949c
AC		 1940 /* Max queues are bounded by available msix vectors */
1941 /* queue 0 uses two msix vectors */
1942 if (ql2xmultique_tag) {
1943 cpus = num_online_cpus();
27dc9c5a 1944 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
68ca949c
AC		 1945 (cpus + 1) : (ha->msix_count - 1);
1946 ha->max_req_queues = 2;
1947 } else if (ql2xmaxqueues > 1) {
2afa19a9 1948 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
7c3df132
SK		 1949 QLA_MQ_SIZE : ql2xmaxqueues;
1950 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1951 "QoS mode set, max no of request queues:%d.\n",
1952 ha->max_req_queues);
1953 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1954 "QoS mode set, max no of request queues:%d.\n",
1955 ha->max_req_queues);
2afa19a9 1956 }
7c3df132
SK		 1957 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1958 "MSI-X vector count: %d.\n", msix);
2afa19a9 1959 } else
7c3df132
SK		 1960 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1961 "BAR 3 not enabled.\n");
17d98630
AC		 1962
1963mqiobase_exit:
2afa19a9 1964 ha->msix_count = ha->max_rsp_queues + 1;
7c3df132
SK		 1965 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1966 "MSIX Count:%d.\n", ha->msix_count);
1da177e4
LT		 1967 return (0);
1968
1969iospace_error_exit:
1970 return (-ENOMEM);
1971}
1972
1e99e33a
AV		 1973static void
1974qla2xxx_scan_start(struct Scsi_Host *shost)
1975{
e315cd28 1976 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 1977
cbc8eb67
AV		 1978 if (vha->hw->flags.running_gold_fw)
1979 return;
1980
e315cd28
AC		 1981 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1982 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1983 set_bit(RSCN_UPDATE, &vha->dpc_flags);
1984 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 1985}
1986
1987static int
1988qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
1989{
e315cd28 1990 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 1991
e315cd28 1992 if (!vha->host)
1e99e33a 1993 return 1;
e315cd28 1994 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 1995 return 1;
1996
e315cd28 1997 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 1998}
1999
1da177e4
LT		 2000/*
2001 * PCI driver interface
2002 */
7ee61397
AV		 2003static int __devinit
2004qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2005{
a1541d5a 2006 int ret = -ENODEV;
1da177e4 2007 struct Scsi_Host *host;
e315cd28
AC		 2008 scsi_qla_host_t *base_vha = NULL;
2009 struct qla_hw_data *ha;
29856e28 2010 char pci_info[30];
1da177e4 2011 char fw_str[30];
5433383e 2012 struct scsi_host_template *sht;
c51da4ec 2013 int bars, max_id, mem_only = 0;
e315cd28 2014 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2015 struct req_que *req = NULL;
2016 struct rsp_que *rsp = NULL;
1da177e4 2017
285d0321 2018 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2019 sht = &qla2xxx_driver_template;
5433383e 2020 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2021 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2022 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2023 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2024 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2025 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016
GM		 2026 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2027 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021) {
285d0321 2028 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2029 mem_only = 1;
7c3df132
SK		 2030 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2031 "Mem only adapter.\n");
285d0321 2032 }
7c3df132
SK		 2033 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2034 "Bars=%d.\n", bars);
285d0321 2035
09483916
BH		 2036 if (mem_only) {
2037 if (pci_enable_device_mem(pdev))
2038 goto probe_out;
2039 } else {
2040 if (pci_enable_device(pdev))
2041 goto probe_out;
2042 }
285d0321 2043
0927678f
JB		 2044 /* This may fail but that's ok */
2045 pci_enable_pcie_error_reporting(pdev);
285d0321 2046
e315cd28
AC		 2047 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2048 if (!ha) {
7c3df132
SK		 2049 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2050 "Unable to allocate memory for ha.\n");
e315cd28 2051 goto probe_out;
1da177e4 2052 }
7c3df132
SK		 2053 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2054 "Memory allocated for ha=%p.\n", ha);
e315cd28 2055 ha->pdev = pdev;
1da177e4
LT		 2056
2057 /* Clear our data area */
285d0321 2058 ha->bars = bars;
09483916 2059 ha->mem_only = mem_only;
df4bf0bb 2060 spin_lock_init(&ha->hardware_lock);
339aa70e 2061 spin_lock_init(&ha->vport_slock);
1da177e4 2062
ea5b6382 2063 /* Set ISP-type information. */
2064 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2065
2066 /* Set EEH reset type to fundamental if required by hba */
2067 if ( IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha)) {
2068 pdev->needs_freset = 1;
ca79cf66
DG		 2069 }
2070
1da177e4
LT		 2071 /* Configure PCI I/O space */
2072 ret = qla2x00_iospace_config(ha);
a1541d5a 2073 if (ret)
e315cd28 2074 goto probe_hw_failed;
1da177e4 2075
7c3df132
SK		 2076 ql_log_pci(ql_log_info, pdev, 0x001d,
2077 "Found an ISP%04X irq %d iobase 0x%p.\n",
2078 pdev->device, pdev->irq, ha->iobase);
1da177e4 2079 ha->prev_topology = 0;
fca29703 2080 ha->init_cb_size = sizeof(init_cb_t);
d8b45213 2081 ha->link_data_rate = PORT_SPEED_UNKNOWN;
854165f4 2082 ha->optrom_size = OPTROM_SIZE_2300;
1da177e4 2083
abbd8870 2084 /* Assign ISP specific operations. */
e315cd28 2085 max_id = MAX_TARGETS_2200;
1da177e4 2086 if (IS_QLA2100(ha)) {
e315cd28 2087 max_id = MAX_TARGETS_2100;
1da177e4 2088 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2089 req_length = REQUEST_ENTRY_CNT_2100;
2090 rsp_length = RESPONSE_ENTRY_CNT_2100;
2091 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2092 ha->gid_list_info_size = 4;
3a03eb79
AV		 2093 ha->flash_conf_off = ~0;
2094 ha->flash_data_off = ~0;
2095 ha->nvram_conf_off = ~0;
2096 ha->nvram_data_off = ~0;
fd34f556 2097 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2098 } else if (IS_QLA2200(ha)) {
1da177e4 2099 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2100 req_length = REQUEST_ENTRY_CNT_2200;
2101 rsp_length = RESPONSE_ENTRY_CNT_2100;
2102 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2103 ha->gid_list_info_size = 4;
3a03eb79
AV		 2104 ha->flash_conf_off = ~0;
2105 ha->flash_data_off = ~0;
2106 ha->nvram_conf_off = ~0;
2107 ha->nvram_data_off = ~0;
fd34f556 2108 ha->isp_ops = &qla2100_isp_ops;
fca29703 2109 } else if (IS_QLA23XX(ha)) {
1da177e4 2110 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2111 req_length = REQUEST_ENTRY_CNT_2200;
2112 rsp_length = RESPONSE_ENTRY_CNT_2300;
2113 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2114 ha->gid_list_info_size = 6;
854165f4 2115 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2116 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2117 ha->flash_conf_off = ~0;
2118 ha->flash_data_off = ~0;
2119 ha->nvram_conf_off = ~0;
2120 ha->nvram_data_off = ~0;
fd34f556 2121 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2122 } else if (IS_QLA24XX_TYPE(ha)) {
fca29703 2123 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2124 req_length = REQUEST_ENTRY_CNT_24XX;
2125 rsp_length = RESPONSE_ENTRY_CNT_2300;
2126 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2127 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2128 ha->gid_list_info_size = 8;
854165f4 2129 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2130 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2131 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2132 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2133 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2134 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2135 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2136 } else if (IS_QLA25XX(ha)) {
c3a2f0df 2137 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2138 req_length = REQUEST_ENTRY_CNT_24XX;
2139 rsp_length = RESPONSE_ENTRY_CNT_2300;
2140 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2141 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2142 ha->gid_list_info_size = 8;
2143 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2144 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2145 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2146 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2147 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2148 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2149 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2150 } else if (IS_QLA81XX(ha)) {
2151 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2152 req_length = REQUEST_ENTRY_CNT_24XX;
2153 rsp_length = RESPONSE_ENTRY_CNT_2300;
2154 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2155 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2156 ha->gid_list_info_size = 8;
2157 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2158 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2159 ha->isp_ops = &qla81xx_isp_ops;
2160 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2161 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2162 ha->nvram_conf_off = ~0;
2163 ha->nvram_data_off = ~0;
a9083016
GM		 2164 } else if (IS_QLA82XX(ha)) {
2165 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2166 req_length = REQUEST_ENTRY_CNT_82XX;
2167 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2168 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2169 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2170 ha->gid_list_info_size = 8;
2171 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2172 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2173 ha->isp_ops = &qla82xx_isp_ops;
2174 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2175 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2176 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2177 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
1da177e4 2178 }
7c3df132
SK		 2179 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2180 "mbx_count=%d, req_length=%d, "
2181 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
2182 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, .\n",
2183 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2184 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
2185 ha->nvram_npiv_size);
2186 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2187 "isp_ops=%p, flash_conf_off=%d, "
2188 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2189 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2190 ha->nvram_conf_off, ha->nvram_data_off);
6c2f527c 2191 mutex_init(&ha->vport_lock);
0b05a1f0
MB		 2192 init_completion(&ha->mbx_cmd_comp);
2193 complete(&ha->mbx_cmd_comp);
2194 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2195 init_completion(&ha->dcbx_comp);
1da177e4 2196
2c3dfe3f 2197 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2198
53303c42 2199 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2200 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2201 "64 Bit addressing is %s.\n",
2202 ha->flags.enable_64bit_addressing ? "enable" :
2203 "disable");
73208dfd 2204 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
e315cd28 2205 if (!ret) {
7c3df132
SK		 2206 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2207 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2208
e315cd28
AC		 2209 goto probe_hw_failed;
2210 }
2211
73208dfd 2212 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2213 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2214 req->max_q_depth = ql2xmaxqdepth;
2215
e315cd28
AC		 2216
2217 base_vha = qla2x00_create_host(sht, ha);
2218 if (!base_vha) {
a1541d5a 2219 ret = -ENOMEM;
6e9f21f3 2220 qla2x00_mem_free(ha);
2afa19a9
AC		 2221 qla2x00_free_req_que(ha, req);
2222 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2223 goto probe_hw_failed;
1da177e4
LT		 2224 }
2225
e315cd28
AC		 2226 pci_set_drvdata(pdev, base_vha);
2227
e315cd28 2228 host = base_vha->host;
2afa19a9 2229 base_vha->req = req;
73208dfd
AC		 2230 host->can_queue = req->length + 128;
2231 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2232 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2233 else
e315cd28
AC		 2234 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2235 base_vha->vp_idx;
58548cb5
GM		 2236
2237 /* Set the SG table size based on ISP type */
2238 if (!IS_FWI2_CAPABLE(ha)) {
2239 if (IS_QLA2100(ha))
2240 host->sg_tablesize = 32;
2241 } else {
2242 if (!IS_QLA82XX(ha))
2243 host->sg_tablesize = QLA_SG_ALL;
2244 }
7c3df132
SK		 2245 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2246 "can_queue=%d, req=%p, "
2247 "mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2248 host->can_queue, base_vha->req,
2249 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
e315cd28
AC		 2250 host->max_id = max_id;
2251 host->this_id = 255;
2252 host->cmd_per_lun = 3;
2253 host->unique_id = host->host_no;
0c470874
AE		 2254 if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && ql2xenabledif)
2255 host->max_cmd_len = 32;
2256 else
2257 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2258 host->max_channel = MAX_BUSES - 1;
82515920 2259 host->max_lun = ql2xmaxlun;
e315cd28 2260 host->transportt = qla2xxx_transport_template;
9a069e19 2261 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2262
7c3df132
SK		 2263 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2264 "max_id=%d this_id=%d "
2265 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
2266 "max_lun=%d transportt=%p, vendor_id=%d.\n", host->max_id,
2267 host->this_id, host->cmd_per_lun, host->unique_id,
2268 host->max_cmd_len, host->max_channel, host->max_lun,
2269 host->transportt, sht->vendor_id);
2270
73208dfd
AC		 2271 /* Set up the irqs */
2272 ret = qla2x00_request_irqs(ha, rsp);
2273 if (ret)
6e9f21f3 2274 goto probe_init_failed;
90a86fc0
JC		 2275
2276 pci_save_state(pdev);
2277
73208dfd 2278 /* Alloc arrays of request and response ring ptrs */
7163ea81 2279que_init:
73208dfd 2280 if (!qla2x00_alloc_queues(ha)) {
7c3df132
SK		 2281 ql_log(ql_log_fatal, base_vha, 0x003d,
2282 "Failed to allocate memory for queue pointers.. aborting.\n");
6e9f21f3 2283 goto probe_init_failed;
73208dfd 2284 }
a9083016 2285
73208dfd
AC		 2286 ha->rsp_q_map[0] = rsp;
2287 ha->req_q_map[0] = req;
2afa19a9
AC		 2288 rsp->req = req;
2289 req->rsp = rsp;
2290 set_bit(0, ha->req_qid_map);
2291 set_bit(0, ha->rsp_qid_map);
08029990
AV		 2292 /* FWI2-capable only. */
2293 req->req_q_in = &ha->iobase->isp24.req_q_in;
2294 req->req_q_out = &ha->iobase->isp24.req_q_out;
2295 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2296 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
17d98630 2297 if (ha->mqenable) {
08029990
AV		 2298 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2299 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2300 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2301 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2302 }
2303
a9083016
GM		 2304 if (IS_QLA82XX(ha)) {
2305 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2306 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2307 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2308 }
2309
7c3df132
SK		 2310 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2311 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2312 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2313 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2314 "req->req_q_in=%p req->req_q_out=%p "
2315 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2316 req->req_q_in, req->req_q_out,
2317 rsp->rsp_q_in, rsp->rsp_q_out);
2318 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2319 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2320 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2321 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2322 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2323 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2324
7c3df132
SK		 2325 if (qla2x00_initialize_adapter(base_vha)) {
2326 ql_log(ql_log_fatal, base_vha, 0x00d6,
2327 "Failed to initialize adapter - Adapter flags %x.\n",
2328 base_vha->device_flags);
1da177e4 2329
a9083016
GM		 2330 if (IS_QLA82XX(ha)) {
2331 qla82xx_idc_lock(ha);
2332 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2333 QLA82XX_DEV_FAILED);
2334 qla82xx_idc_unlock(ha);
7c3df132
SK		 2335 ql_log(ql_log_fatal, base_vha, 0x00d7,
2336 "HW State: FAILED.\n");
a9083016
GM		 2337 }
2338
a1541d5a 2339 ret = -ENODEV;
1da177e4
LT		 2340 goto probe_failed;
2341 }
2342
7163ea81
AC		 2343 if (ha->mqenable) {
2344 if (qla25xx_setup_mode(base_vha)) {
7c3df132
SK		 2345 ql_log(ql_log_warn, base_vha, 0x00ec,
2346 "Failed to create queues, falling back to single queue mode.\n");
7163ea81
AC		 2347 goto que_init;
2348 }
2349 }
68ca949c 2350
cbc8eb67
AV		 2351 if (ha->flags.running_gold_fw)
2352 goto skip_dpc;
2353
1da177e4
LT		 2354 /*
2355 * Startup the kernel thread for this host adapter
2356 */
39a11240 2357 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 2358 "%s_dpc", base_vha->host_str);
39a11240 2359 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 2360 ql_log(ql_log_fatal, base_vha, 0x00ed,
2361 "Failed to start DPC thread.\n");
39a11240 2362 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 2363 goto probe_failed;
2364 }
7c3df132
SK		 2365 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2366 "DPC thread started successfully.\n");
1da177e4 2367
cbc8eb67 2368skip_dpc:
e315cd28
AC		 2369 list_add_tail(&base_vha->list, &ha->vp_list);
2370 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 2371
2372 /* Initialized the timer */
e315cd28 2373 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 2374 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2375 "Started qla2x00_timer with "
2376 "interval=%d.\n", WATCH_INTERVAL);
2377 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2378 "Detected hba at address=%p.\n",
2379 ha);
d19044c3 2380
ba77ef53 2381 if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && ql2xenabledif) {
bad75002
AE		 2382 if (ha->fw_attributes & BIT_4) {
2383 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 2384 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2385 "Registering for DIF/DIX type 1 and 3 protection.\n");
bad75002
AE		 2386 scsi_host_set_prot(host,
2387 SHOST_DIF_TYPE1_PROTECTION
0c470874 2388 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 2389 | SHOST_DIF_TYPE3_PROTECTION
2390 | SHOST_DIX_TYPE1_PROTECTION
0c470874 2391 | SHOST_DIX_TYPE2_PROTECTION
bad75002
AE		 2392 | SHOST_DIX_TYPE3_PROTECTION);
2393 scsi_host_set_guard(host, SHOST_DIX_GUARD_CRC);
2394 } else
2395 base_vha->flags.difdix_supported = 0;
2396 }
2397
a9083016
GM		 2398 ha->isp_ops->enable_intrs(ha);
2399
a1541d5a
AV		 2400 ret = scsi_add_host(host, &pdev->dev);
2401 if (ret)
2402 goto probe_failed;
2403
1486400f
MR		 2404 base_vha->flags.init_done = 1;
2405 base_vha->flags.online = 1;
2406
7c3df132
SK		 2407 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2408 "Init done and hba is online.\n");
2409
1e99e33a
AV		 2410 scsi_scan_host(host);
2411
e315cd28 2412 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 2413
e315cd28 2414 qla2x00_init_host_attr(base_vha);
a1541d5a 2415
e315cd28 2416 qla2x00_dfs_setup(base_vha);
df613b96 2417
7c3df132
SK		 2418 ql_log(ql_log_info, base_vha, 0x00fa,
2419 "QLogic Fibre Channed HBA Driver: %s.\n",
2420 qla2x00_version_str);
2421 ql_log(ql_log_info, base_vha, 0x00fb,
2422 "QLogic %s - %s.\n",
2423 ha->model_number, ha->model_desc ? ha->model_desc : "");
2424 ql_log(ql_log_info, base_vha, 0x00fc,
2425 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2426 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2427 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2428 base_vha->host_no,
e315cd28 2429 ha->isp_ops->fw_version_str(base_vha, fw_str));
1da177e4 2430
1da177e4
LT		 2431 return 0;
2432
6e9f21f3 2433probe_init_failed:
2afa19a9
AC		 2434 qla2x00_free_req_que(ha, req);
2435 qla2x00_free_rsp_que(ha, rsp);
2436 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 2437
1da177e4 2438probe_failed:
b9978769
AV		 2439 if (base_vha->timer_active)
2440 qla2x00_stop_timer(base_vha);
2441 base_vha->flags.online = 0;
2442 if (ha->dpc_thread) {
2443 struct task_struct *t = ha->dpc_thread;
2444
2445 ha->dpc_thread = NULL;
2446 kthread_stop(t);
2447 }
2448
e315cd28 2449 qla2x00_free_device(base_vha);
1da177e4 2450
e315cd28 2451 scsi_host_put(base_vha->host);
1da177e4 2452
e315cd28 2453probe_hw_failed:
a9083016
GM		 2454 if (IS_QLA82XX(ha)) {
2455 qla82xx_idc_lock(ha);
2456 qla82xx_clear_drv_active(ha);
2457 qla82xx_idc_unlock(ha);
2458 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
2459 if (!ql2xdbwr)
2460 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2461 } else {
2462 if (ha->iobase)
2463 iounmap(ha->iobase);
2464 }
e315cd28
AC		 2465 pci_release_selected_regions(ha->pdev, ha->bars);
2466 kfree(ha);
2467 ha = NULL;
1da177e4 2468
a1541d5a 2469probe_out:
e315cd28 2470 pci_disable_device(pdev);
a1541d5a 2471 return ret;
1da177e4 2472}
1da177e4 2473
e30d1756
MI		 2474static void
2475qla2x00_shutdown(struct pci_dev *pdev)
2476{
2477 scsi_qla_host_t *vha;
2478 struct qla_hw_data *ha;
2479
2480 vha = pci_get_drvdata(pdev);
2481 ha = vha->hw;
2482
2483 /* Turn-off FCE trace */
2484 if (ha->flags.fce_enabled) {
2485 qla2x00_disable_fce_trace(vha, NULL, NULL);
2486 ha->flags.fce_enabled = 0;
2487 }
2488
2489 /* Turn-off EFT trace */
2490 if (ha->eft)
2491 qla2x00_disable_eft_trace(vha);
2492
2493 /* Stop currently executing firmware. */
2494 qla2x00_try_to_stop_firmware(vha);
2495
2496 /* Turn adapter off line */
2497 vha->flags.online = 0;
2498
2499 /* turn-off interrupts on the card */
2500 if (ha->interrupts_on) {
2501 vha->flags.init_done = 0;
2502 ha->isp_ops->disable_intrs(ha);
2503 }
2504
2505 qla2x00_free_irqs(vha);
2506
2507 qla2x00_free_fw_dump(ha);
2508}
2509
4c993f76 2510static void
7ee61397 2511qla2x00_remove_one(struct pci_dev *pdev)
1da177e4 2512{
feafb7b1 2513 scsi_qla_host_t *base_vha, *vha;
e315cd28 2514 struct qla_hw_data *ha;
feafb7b1 2515 unsigned long flags;
e315cd28
AC		 2516
2517 base_vha = pci_get_drvdata(pdev);
2518 ha = base_vha->hw;
2519
43ebf16d
AE		 2520 mutex_lock(&ha->vport_lock);
2521 while (ha->cur_vport_count) {
2522 struct Scsi_Host *scsi_host;
feafb7b1 2523
43ebf16d 2524 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 2525
43ebf16d
AE		 2526 BUG_ON(base_vha->list.next == &ha->vp_list);
2527 /* This assumes first entry in ha->vp_list is always base vha */
2528 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
2529 scsi_host = scsi_host_get(vha->host);
feafb7b1 2530
43ebf16d
AE		 2531 spin_unlock_irqrestore(&ha->vport_slock, flags);
2532 mutex_unlock(&ha->vport_lock);
2533
2534 fc_vport_terminate(vha->fc_vport);
2535 scsi_host_put(vha->host);
feafb7b1 2536
43ebf16d 2537 mutex_lock(&ha->vport_lock);
e315cd28 2538 }
43ebf16d 2539 mutex_unlock(&ha->vport_lock);
1da177e4 2540
e315cd28 2541 set_bit(UNLOADING, &base_vha->dpc_flags);
1da177e4 2542
b9978769
AV		 2543 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
2544
e315cd28 2545 qla2x00_dfs_remove(base_vha);
c795c1e4 2546
e315cd28 2547 qla84xx_put_chip(base_vha);
c795c1e4 2548
b9978769
AV		 2549 /* Disable timer */
2550 if (base_vha->timer_active)
2551 qla2x00_stop_timer(base_vha);
2552
2553 base_vha->flags.online = 0;
2554
68ca949c
AC		 2555 /* Flush the work queue and remove it */
2556 if (ha->wq) {
2557 flush_workqueue(ha->wq);
2558 destroy_workqueue(ha->wq);
2559 ha->wq = NULL;
2560 }
2561
b9978769
AV		 2562 /* Kill the kernel thread for this host */
2563 if (ha->dpc_thread) {
2564 struct task_struct *t = ha->dpc_thread;
2565
2566 /*
2567 * qla2xxx_wake_dpc checks for ->dpc_thread
2568 * so we need to zero it out.
2569 */
2570 ha->dpc_thread = NULL;
2571 kthread_stop(t);
2572 }
2573
e315cd28 2574 qla2x00_free_sysfs_attr(base_vha);
df613b96 2575
e315cd28 2576 fc_remove_host(base_vha->host);
4d4df193 2577
e315cd28 2578 scsi_remove_host(base_vha->host);
1da177e4 2579
e315cd28 2580 qla2x00_free_device(base_vha);
bdf79621 2581
e315cd28 2582 scsi_host_put(base_vha->host);
1da177e4 2583
a9083016 2584 if (IS_QLA82XX(ha)) {
b963752f
GM		 2585 qla82xx_idc_lock(ha);
2586 qla82xx_clear_drv_active(ha);
2587 qla82xx_idc_unlock(ha);
2588
a9083016
GM		 2589 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
2590 if (!ql2xdbwr)
2591 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2592 } else {
2593 if (ha->iobase)
2594 iounmap(ha->iobase);
1da177e4 2595
a9083016
GM		 2596 if (ha->mqiobase)
2597 iounmap(ha->mqiobase);
2598 }
73208dfd 2599
e315cd28
AC		 2600 pci_release_selected_regions(ha->pdev, ha->bars);
2601 kfree(ha);
2602 ha = NULL;
1da177e4 2603
90a86fc0
JC		 2604 pci_disable_pcie_error_reporting(pdev);
2605
665db93b 2606 pci_disable_device(pdev);
1da177e4
LT		 2607 pci_set_drvdata(pdev, NULL);
2608}
1da177e4
LT		 2609
2610static void
e315cd28 2611qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 2612{
e315cd28 2613 struct qla_hw_data *ha = vha->hw;
1da177e4 2614
85880801
AV		 2615 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
2616
2617 /* Disable timer */
2618 if (vha->timer_active)
2619 qla2x00_stop_timer(vha);
2620
2621 /* Kill the kernel thread for this host */
2622 if (ha->dpc_thread) {
2623 struct task_struct *t = ha->dpc_thread;
2624
2625 /*
2626 * qla2xxx_wake_dpc checks for ->dpc_thread
2627 * so we need to zero it out.
2628 */
2629 ha->dpc_thread = NULL;
2630 kthread_stop(t);
2631 }
2632
2afa19a9
AC		 2633 qla25xx_delete_queues(vha);
2634
df613b96 2635 if (ha->flags.fce_enabled)
e315cd28 2636 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 2637
a7a167bf 2638 if (ha->eft)
e315cd28 2639 qla2x00_disable_eft_trace(vha);
a7a167bf 2640
f6ef3b18 2641 /* Stop currently executing firmware. */
e315cd28 2642 qla2x00_try_to_stop_firmware(vha);
1da177e4 2643
85880801
AV		 2644 vha->flags.online = 0;
2645
f6ef3b18 2646 /* turn-off interrupts on the card */
a9083016
GM		 2647 if (ha->interrupts_on) {
2648 vha->flags.init_done = 0;
fd34f556 2649 ha->isp_ops->disable_intrs(ha);
a9083016 2650 }
f6ef3b18 2651
e315cd28 2652 qla2x00_free_irqs(vha);
1da177e4 2653
8867048b
CD		 2654 qla2x00_free_fcports(vha);
2655
e315cd28 2656 qla2x00_mem_free(ha);
73208dfd
AC		 2657
2658 qla2x00_free_queues(ha);
1da177e4
LT		 2659}
2660
8867048b
CD		 2661void qla2x00_free_fcports(struct scsi_qla_host *vha)
2662{
2663 fc_port_t *fcport, *tfcport;
2664
2665 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
2666 list_del(&fcport->list);
2667 kfree(fcport);
2668 fcport = NULL;
2669 }
2670}
2671
d97994dc 2672static inline void
e315cd28 2673qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc 2674 int defer)
2675{
d97994dc 2676 struct fc_rport *rport;
67becc00 2677 scsi_qla_host_t *base_vha;
044d78e1 2678 unsigned long flags;
d97994dc 2679
2680 if (!fcport->rport)
2681 return;
2682
2683 rport = fcport->rport;
2684 if (defer) {
67becc00 2685 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 2686 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 2687 fcport->drport = rport;
044d78e1 2688 spin_unlock_irqrestore(vha->host->host_lock, flags);
67becc00
AV		 2689 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
2690 qla2xxx_wake_dpc(base_vha);
5f3a9a20 2691 } else
d97994dc 2692 fc_remote_port_delete(rport);
d97994dc 2693}
2694
1da177e4
LT		 2695/*
2696 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
2697 *
2698 * Input: ha = adapter block pointer. fcport = port structure pointer.
2699 *
2700 * Return: None.
2701 *
2702 * Context:
2703 */
e315cd28 2704void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 2705 int do_login, int defer)
1da177e4 2706{
2c3dfe3f 2707 if (atomic_read(&fcport->state) == FCS_ONLINE &&
e315cd28 2708 vha->vp_idx == fcport->vp_idx) {
ec426e10 2709 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 2710 qla2x00_schedule_rport_del(vha, fcport, defer);
2711 }
fa2a1ce5 2712 /*
1da177e4
LT		 2713 * We may need to retry the login, so don't change the state of the
2714 * port but do the retries.
2715 */
2716 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 2717 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 2718
2719 if (!do_login)
2720 return;
2721
2722 if (fcport->login_retry == 0) {
e315cd28
AC		 2723 fcport->login_retry = vha->hw->login_retry_count;
2724 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4 2725
7c3df132
SK		 2726 ql_dbg(ql_dbg_disc, vha, 0x2067,
2727 "Port login retry "
1da177e4 2728 "%02x%02x%02x%02x%02x%02x%02x%02x, "
7c3df132
SK		 2729 "id = 0x%04x retry cnt=%d.\n",
2730 fcport->port_name[0], fcport->port_name[1],
2731 fcport->port_name[2], fcport->port_name[3],
2732 fcport->port_name[4], fcport->port_name[5],
2733 fcport->port_name[6], fcport->port_name[7],
2734 fcport->loop_id, fcport->login_retry);
1da177e4
LT		 2735 }
2736}
2737
2738/*
2739 * qla2x00_mark_all_devices_lost
2740 * Updates fcport state when device goes offline.
2741 *
2742 * Input:
2743 * ha = adapter block pointer.
2744 * fcport = port structure pointer.
2745 *
2746 * Return:
2747 * None.
2748 *
2749 * Context:
2750 */
2751void
e315cd28 2752qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 2753{
2754 fc_port_t *fcport;
2755
e315cd28 2756 list_for_each_entry(fcport, &vha->vp_fcports, list) {
0d6e61bc 2757 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vp_idx)
1da177e4 2758 continue;
0d6e61bc 2759
1da177e4
LT		 2760 /*
2761 * No point in marking the device as lost, if the device is
2762 * already DEAD.
2763 */
2764 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
2765 continue;
e315cd28 2766 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 2767 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 2768 if (defer)
2769 qla2x00_schedule_rport_del(vha, fcport, defer);
2770 else if (vha->vp_idx == fcport->vp_idx)
2771 qla2x00_schedule_rport_del(vha, fcport, defer);
2772 }
1da177e4
LT		 2773 }
2774}
2775
2776/*
2777* qla2x00_mem_alloc
2778* Allocates adapter memory.
2779*
2780* Returns:
2781* 0 = success.
e8711085 2782* !0 = failure.
1da177e4 2783*/
e8711085 2784static int
73208dfd
AC		 2785qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
2786 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 2787{
2788 char name[16];
1da177e4 2789
e8711085 2790 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 2791 &ha->init_cb_dma, GFP_KERNEL);
e8711085 2792 if (!ha->init_cb)
e315cd28 2793 goto fail;
e8711085 2794
e315cd28
AC		 2795 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, GID_LIST_SIZE,
2796 &ha->gid_list_dma, GFP_KERNEL);
2797 if (!ha->gid_list)
e8711085 2798 goto fail_free_init_cb;
1da177e4 2799
e8711085
AV		 2800 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
2801 if (!ha->srb_mempool)
e315cd28 2802 goto fail_free_gid_list;
e8711085 2803
a9083016
GM		 2804 if (IS_QLA82XX(ha)) {
2805 /* Allocate cache for CT6 Ctx. */
2806 if (!ctx_cachep) {
2807 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
2808 sizeof(struct ct6_dsd), 0,
2809 SLAB_HWCACHE_ALIGN, NULL);
2810 if (!ctx_cachep)
2811 goto fail_free_gid_list;
2812 }
2813 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
2814 ctx_cachep);
2815 if (!ha->ctx_mempool)
2816 goto fail_free_srb_mempool;
7c3df132
SK		 2817 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
2818 "ctx_cachep=%p ctx_mempool=%p.\n",
2819 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 2820 }
2821
e8711085
AV		 2822 /* Get memory for cached NVRAM */
2823 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
2824 if (!ha->nvram)
a9083016 2825 goto fail_free_ctx_mempool;
e8711085 2826
e315cd28
AC		 2827 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
2828 ha->pdev->device);
2829 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
2830 DMA_POOL_SIZE, 8, 0);
2831 if (!ha->s_dma_pool)
2832 goto fail_free_nvram;
2833
7c3df132
SK		 2834 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
2835 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
2836 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
2837
bad75002 2838 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 2839 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
2840 DSD_LIST_DMA_POOL_SIZE, 8, 0);
2841 if (!ha->dl_dma_pool) {
7c3df132
SK		 2842 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
2843 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 2844 goto fail_s_dma_pool;
2845 }
2846
2847 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
2848 FCP_CMND_DMA_POOL_SIZE, 8, 0);
2849 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 2850 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
2851 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 2852 goto fail_dl_dma_pool;
2853 }
7c3df132
SK		 2854 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
2855 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
2856 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 2857 }
2858
e8711085
AV		 2859 /* Allocate memory for SNS commands */
2860 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 2861 /* Get consistent memory allocated for SNS commands */
e8711085 2862 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 2863 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 2864 if (!ha->sns_cmd)
e315cd28 2865 goto fail_dma_pool;
7c3df132
SK		 2866 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
2867 "sns_cmd.\n", ha->sns_cmd);
e8711085 2868 } else {
e315cd28 2869 /* Get consistent memory allocated for MS IOCB */
e8711085 2870 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 2871 &ha->ms_iocb_dma);
e8711085 2872 if (!ha->ms_iocb)
e315cd28
AC		 2873 goto fail_dma_pool;
2874 /* Get consistent memory allocated for CT SNS commands */
e8711085 2875 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 2876 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 2877 if (!ha->ct_sns)
2878 goto fail_free_ms_iocb;
7c3df132
SK		 2879 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
2880 "ms_iocb=%p ct_sns=%p.\n",
2881 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 2882 }
2883
e315cd28 2884 /* Allocate memory for request ring */
73208dfd
AC		 2885 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
2886 if (!*req) {
7c3df132
SK		 2887 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
2888 "Failed to allocate memory for req.\n");
e315cd28
AC		 2889 goto fail_req;
2890 }
73208dfd
AC		 2891 (*req)->length = req_len;
2892 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
2893 ((*req)->length + 1) * sizeof(request_t),
2894 &(*req)->dma, GFP_KERNEL);
2895 if (!(*req)->ring) {
7c3df132
SK		 2896 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
2897 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 2898 goto fail_req_ring;
2899 }
2900 /* Allocate memory for response ring */
73208dfd
AC		 2901 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
2902 if (!*rsp) {
7c3df132
SK		 2903 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
2904 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 2905 goto fail_rsp;
2906 }
73208dfd
AC		 2907 (*rsp)->hw = ha;
2908 (*rsp)->length = rsp_len;
2909 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
2910 ((*rsp)->length + 1) * sizeof(response_t),
2911 &(*rsp)->dma, GFP_KERNEL);
2912 if (!(*rsp)->ring) {
7c3df132
SK		 2913 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
2914 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 2915 goto fail_rsp_ring;
2916 }
73208dfd
AC		 2917 (*req)->rsp = *rsp;
2918 (*rsp)->req = *req;
7c3df132
SK		 2919 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
2920 "req=%p req->length=%d req->ring=%p rsp=%p "
2921 "rsp->length=%d rsp->ring=%p.\n",
2922 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
2923 (*rsp)->ring);
73208dfd
AC		 2924 /* Allocate memory for NVRAM data for vports */
2925 if (ha->nvram_npiv_size) {
2926 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 2927 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 2928 if (!ha->npiv_info) {
7c3df132
SK		 2929 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
2930 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 2931 goto fail_npiv_info;
2932 }
2933 } else
2934 ha->npiv_info = NULL;
e8711085 2935
b64b0e8f 2936 /* Get consistent memory allocated for EX-INIT-CB. */
a9083016 2937 if (IS_QLA8XXX_TYPE(ha)) {
b64b0e8f
AV		 2938 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
2939 &ha->ex_init_cb_dma);
2940 if (!ha->ex_init_cb)
2941 goto fail_ex_init_cb;
7c3df132
SK		 2942 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
2943 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 2944 }
2945
a9083016
GM		 2946 INIT_LIST_HEAD(&ha->gbl_dsd_list);
2947
5ff1d584
AV		 2948 /* Get consistent memory allocated for Async Port-Database. */
2949 if (!IS_FWI2_CAPABLE(ha)) {
2950 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
2951 &ha->async_pd_dma);
2952 if (!ha->async_pd)
2953 goto fail_async_pd;
7c3df132
SK		 2954 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
2955 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 2956 }
2957
e315cd28
AC		 2958 INIT_LIST_HEAD(&ha->vp_list);
2959 return 1;
2960
5ff1d584
AV		 2961fail_async_pd:
2962 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 2963fail_ex_init_cb:
2964 kfree(ha->npiv_info);
73208dfd
AC		 2965fail_npiv_info:
2966 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
2967 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
2968 (*rsp)->ring = NULL;
2969 (*rsp)->dma = 0;
e315cd28 2970fail_rsp_ring:
73208dfd 2971 kfree(*rsp);
e315cd28 2972fail_rsp:
73208dfd
AC		 2973 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
2974 sizeof(request_t), (*req)->ring, (*req)->dma);
2975 (*req)->ring = NULL;
2976 (*req)->dma = 0;
e315cd28 2977fail_req_ring:
73208dfd 2978 kfree(*req);
e315cd28
AC		 2979fail_req:
2980 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
2981 ha->ct_sns, ha->ct_sns_dma);
2982 ha->ct_sns = NULL;
2983 ha->ct_sns_dma = 0;
e8711085
AV		 2984fail_free_ms_iocb:
2985 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
2986 ha->ms_iocb = NULL;
2987 ha->ms_iocb_dma = 0;
e315cd28 2988fail_dma_pool:
bad75002 2989 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 2990 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
2991 ha->fcp_cmnd_dma_pool = NULL;
2992 }
2993fail_dl_dma_pool:
bad75002 2994 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 2995 dma_pool_destroy(ha->dl_dma_pool);
2996 ha->dl_dma_pool = NULL;
2997 }
2998fail_s_dma_pool:
e315cd28
AC		 2999 dma_pool_destroy(ha->s_dma_pool);
3000 ha->s_dma_pool = NULL;
e8711085
AV		 3001fail_free_nvram:
3002 kfree(ha->nvram);
3003 ha->nvram = NULL;
a9083016
GM		 3004fail_free_ctx_mempool:
3005 mempool_destroy(ha->ctx_mempool);
3006 ha->ctx_mempool = NULL;
e8711085
AV		 3007fail_free_srb_mempool:
3008 mempool_destroy(ha->srb_mempool);
3009 ha->srb_mempool = NULL;
e8711085
AV		 3010fail_free_gid_list:
3011 dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list,
e315cd28 3012 ha->gid_list_dma);
e8711085
AV		 3013 ha->gid_list = NULL;
3014 ha->gid_list_dma = 0;
e315cd28
AC		 3015fail_free_init_cb:
3016 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3017 ha->init_cb_dma);
3018 ha->init_cb = NULL;
3019 ha->init_cb_dma = 0;
e8711085 3020fail:
7c3df132
SK		 3021 ql_log(ql_log_fatal, NULL, 0x0030,
3022 "Memory allocation failure.\n");
e8711085 3023 return -ENOMEM;
1da177e4
LT		 3024}
3025
3026/*
e30d1756
MI		 3027* qla2x00_free_fw_dump
3028* Frees fw dump stuff.
1da177e4
LT		 3029*
3030* Input:
e30d1756 3031* ha = adapter block pointer.
1da177e4 3032*/
a824ebb3 3033static void
e30d1756 3034qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 3035{
df613b96
AV		 3036 if (ha->fce)
3037 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
e30d1756 3038 ha->fce_dma);
df613b96 3039
a7a167bf
AV		 3040 if (ha->fw_dump) {
3041 if (ha->eft)
3042 dma_free_coherent(&ha->pdev->dev,
e30d1756 3043 ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma);
a7a167bf
AV		 3044 vfree(ha->fw_dump);
3045 }
e30d1756
MI		 3046 ha->fce = NULL;
3047 ha->fce_dma = 0;
3048 ha->eft = NULL;
3049 ha->eft_dma = 0;
3050 ha->fw_dump = NULL;
3051 ha->fw_dumped = 0;
3052 ha->fw_dump_reading = 0;
3053}
3054
3055/*
3056* qla2x00_mem_free
3057* Frees all adapter allocated memory.
3058*
3059* Input:
3060* ha = adapter block pointer.
3061*/
3062static void
3063qla2x00_mem_free(struct qla_hw_data *ha)
3064{
3065 qla2x00_free_fw_dump(ha);
3066
3067 if (ha->srb_mempool)
3068 mempool_destroy(ha->srb_mempool);
a7a167bf 3069
11bbc1d8
AV		 3070 if (ha->dcbx_tlv)
3071 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3072 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3073
ce0423f4
AV		 3074 if (ha->xgmac_data)
3075 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3076 ha->xgmac_data, ha->xgmac_data_dma);
3077
1da177e4
LT		 3078 if (ha->sns_cmd)
3079 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 3080 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 3081
3082 if (ha->ct_sns)
3083 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 3084 ha->ct_sns, ha->ct_sns_dma);
1da177e4 3085
88729e53
AV		 3086 if (ha->sfp_data)
3087 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3088
ad0ecd61
JC		 3089 if (ha->edc_data)
3090 dma_pool_free(ha->s_dma_pool, ha->edc_data, ha->edc_data_dma);
3091
1da177e4
LT		 3092 if (ha->ms_iocb)
3093 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3094
b64b0e8f 3095 if (ha->ex_init_cb)
a9083016
GM		 3096 dma_pool_free(ha->s_dma_pool,
3097 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 3098
5ff1d584
AV		 3099 if (ha->async_pd)
3100 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3101
1da177e4
LT		 3102 if (ha->s_dma_pool)
3103 dma_pool_destroy(ha->s_dma_pool);
3104
1da177e4
LT		 3105 if (ha->gid_list)
3106 dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list,
e315cd28 3107 ha->gid_list_dma);
1da177e4 3108
a9083016
GM		 3109 if (IS_QLA82XX(ha)) {
3110 if (!list_empty(&ha->gbl_dsd_list)) {
3111 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3112
3113 /* clean up allocated prev pool */
3114 list_for_each_entry_safe(dsd_ptr,
3115 tdsd_ptr, &ha->gbl_dsd_list, list) {
3116 dma_pool_free(ha->dl_dma_pool,
3117 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3118 list_del(&dsd_ptr->list);
3119 kfree(dsd_ptr);
3120 }
3121 }
3122 }
3123
3124 if (ha->dl_dma_pool)
3125 dma_pool_destroy(ha->dl_dma_pool);
3126
3127 if (ha->fcp_cmnd_dma_pool)
3128 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3129
3130 if (ha->ctx_mempool)
3131 mempool_destroy(ha->ctx_mempool);
3132
e315cd28
AC		 3133 if (ha->init_cb)
3134 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 3135 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 3136 vfree(ha->optrom_buffer);
3137 kfree(ha->nvram);
73208dfd 3138 kfree(ha->npiv_info);
1da177e4 3139
e8711085 3140 ha->srb_mempool = NULL;
a9083016 3141 ha->ctx_mempool = NULL;
1da177e4
LT		 3142 ha->sns_cmd = NULL;
3143 ha->sns_cmd_dma = 0;
3144 ha->ct_sns = NULL;
3145 ha->ct_sns_dma = 0;
3146 ha->ms_iocb = NULL;
3147 ha->ms_iocb_dma = 0;
1da177e4
LT		 3148 ha->init_cb = NULL;
3149 ha->init_cb_dma = 0;
b64b0e8f
AV		 3150 ha->ex_init_cb = NULL;
3151 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 3152 ha->async_pd = NULL;
3153 ha->async_pd_dma = 0;
1da177e4
LT		 3154
3155 ha->s_dma_pool = NULL;
a9083016
GM		 3156 ha->dl_dma_pool = NULL;
3157 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 3158
1da177e4
LT		 3159 ha->gid_list = NULL;
3160 ha->gid_list_dma = 0;
e315cd28 3161}
1da177e4 3162
e315cd28
AC		 3163struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3164 struct qla_hw_data *ha)
3165{
3166 struct Scsi_Host *host;
3167 struct scsi_qla_host *vha = NULL;
854165f4 3168
e315cd28
AC		 3169 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3170 if (host == NULL) {
7c3df132
SK		 3171 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3172 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 3173 goto fail;
3174 }
3175
3176 /* Clear our data area */
3177 vha = shost_priv(host);
3178 memset(vha, 0, sizeof(scsi_qla_host_t));
3179
3180 vha->host = host;
3181 vha->host_no = host->host_no;
3182 vha->hw = ha;
3183
3184 INIT_LIST_HEAD(&vha->vp_fcports);
3185 INIT_LIST_HEAD(&vha->work_list);
3186 INIT_LIST_HEAD(&vha->list);
3187
f999f4c1
AV		 3188 spin_lock_init(&vha->work_lock);
3189
e315cd28 3190 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 3191 ql_dbg(ql_dbg_init, vha, 0x0041,
3192 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3193 vha->host, vha->hw, vha,
3194 dev_name(&(ha->pdev->dev)));
3195
e315cd28
AC		 3196 return vha;
3197
3198fail:
3199 return vha;
1da177e4
LT		 3200}
3201
01ef66bb 3202static struct qla_work_evt *
f999f4c1 3203qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 3204{
3205 struct qla_work_evt *e;
feafb7b1
AE		 3206 uint8_t bail;
3207
3208 QLA_VHA_MARK_BUSY(vha, bail);
3209 if (bail)
3210 return NULL;
0971de7f 3211
f999f4c1 3212 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 3213 if (!e) {
3214 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 3215 return NULL;
feafb7b1 3216 }
0971de7f
AV		 3217
3218 INIT_LIST_HEAD(&e->list);
3219 e->type = type;
3220 e->flags = QLA_EVT_FLAG_FREE;
3221 return e;
3222}
3223
01ef66bb 3224static int
f999f4c1 3225qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 3226{
f999f4c1 3227 unsigned long flags;
0971de7f 3228
f999f4c1 3229 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 3230 list_add_tail(&e->list, &vha->work_list);
f999f4c1 3231 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 3232 qla2xxx_wake_dpc(vha);
f999f4c1 3233
0971de7f
AV		 3234 return QLA_SUCCESS;
3235}
3236
3237int
e315cd28 3238qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 3239 u32 data)
3240{
3241 struct qla_work_evt *e;
3242
f999f4c1 3243 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 3244 if (!e)
3245 return QLA_FUNCTION_FAILED;
3246
3247 e->u.aen.code = code;
3248 e->u.aen.data = data;
f999f4c1 3249 return qla2x00_post_work(vha, e);
0971de7f
AV		 3250}
3251
8a659571
AV		 3252int
3253qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3254{
3255 struct qla_work_evt *e;
3256
f999f4c1 3257 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 3258 if (!e)
3259 return QLA_FUNCTION_FAILED;
3260
3261 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 3262 return qla2x00_post_work(vha, e);
8a659571
AV		 3263}
3264
ac280b67
AV		 3265#define qla2x00_post_async_work(name, type) \
3266int qla2x00_post_async_##name##_work( \
3267 struct scsi_qla_host *vha, \
3268 fc_port_t *fcport, uint16_t *data) \
3269{ \
3270 struct qla_work_evt *e; \
3271 \
3272 e = qla2x00_alloc_work(vha, type); \
3273 if (!e) \
3274 return QLA_FUNCTION_FAILED; \
3275 \
3276 e->u.logio.fcport = fcport; \
3277 if (data) { \
3278 e->u.logio.data[0] = data[0]; \
3279 e->u.logio.data[1] = data[1]; \
3280 } \
3281 return qla2x00_post_work(vha, e); \
3282}
3283
3284qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3285qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3286qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3287qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 3288qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3289qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 3290
3420d36c
AV		 3291int
3292qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3293{
3294 struct qla_work_evt *e;
3295
3296 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3297 if (!e)
3298 return QLA_FUNCTION_FAILED;
3299
3300 e->u.uevent.code = code;
3301 return qla2x00_post_work(vha, e);
3302}
3303
3304static void
3305qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3306{
3307 char event_string[40];
3308 char *envp[] = { event_string, NULL };
3309
3310 switch (code) {
3311 case QLA_UEVENT_CODE_FW_DUMP:
3312 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3313 vha->host_no);
3314 break;
3315 default:
3316 /* do nothing */
3317 break;
3318 }
3319 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3320}
3321
ac280b67 3322void
e315cd28 3323qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 3324{
f999f4c1
AV		 3325 struct qla_work_evt *e, *tmp;
3326 unsigned long flags;
3327 LIST_HEAD(work);
0971de7f 3328
f999f4c1
AV		 3329 spin_lock_irqsave(&vha->work_lock, flags);
3330 list_splice_init(&vha->work_list, &work);
3331 spin_unlock_irqrestore(&vha->work_lock, flags);
3332
3333 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 3334 list_del_init(&e->list);
0971de7f
AV		 3335
3336 switch (e->type) {
3337 case QLA_EVT_AEN:
e315cd28 3338 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 3339 e->u.aen.code, e->u.aen.data);
3340 break;
8a659571
AV		 3341 case QLA_EVT_IDC_ACK:
3342 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3343 break;
ac280b67
AV		 3344 case QLA_EVT_ASYNC_LOGIN:
3345 qla2x00_async_login(vha, e->u.logio.fcport,
3346 e->u.logio.data);
3347 break;
3348 case QLA_EVT_ASYNC_LOGIN_DONE:
3349 qla2x00_async_login_done(vha, e->u.logio.fcport,
3350 e->u.logio.data);
3351 break;
3352 case QLA_EVT_ASYNC_LOGOUT:
3353 qla2x00_async_logout(vha, e->u.logio.fcport);
3354 break;
3355 case QLA_EVT_ASYNC_LOGOUT_DONE:
3356 qla2x00_async_logout_done(vha, e->u.logio.fcport,
3357 e->u.logio.data);
3358 break;
5ff1d584
AV		 3359 case QLA_EVT_ASYNC_ADISC:
3360 qla2x00_async_adisc(vha, e->u.logio.fcport,
3361 e->u.logio.data);
3362 break;
3363 case QLA_EVT_ASYNC_ADISC_DONE:
3364 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
3365 e->u.logio.data);
3366 break;
3420d36c
AV		 3367 case QLA_EVT_UEVENT:
3368 qla2x00_uevent_emit(vha, e->u.uevent.code);
3369 break;
0971de7f
AV		 3370 }
3371 if (e->flags & QLA_EVT_FLAG_FREE)
3372 kfree(e);
feafb7b1
AE		 3373
3374 /* For each work completed decrement vha ref count */
3375 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 3376 }
e315cd28 3377}
f999f4c1 3378
e315cd28
AC		 3379/* Relogins all the fcports of a vport
3380 * Context: dpc thread
3381 */
3382void qla2x00_relogin(struct scsi_qla_host *vha)
3383{
3384 fc_port_t *fcport;
c6b2fca8 3385 int status;
e315cd28
AC		 3386 uint16_t next_loopid = 0;
3387 struct qla_hw_data *ha = vha->hw;
ac280b67 3388 uint16_t data[2];
e315cd28
AC		 3389
3390 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3391 /*
3392 * If the port is not ONLINE then try to login
3393 * to it if we haven't run out of retries.
3394 */
5ff1d584
AV		 3395 if (atomic_read(&fcport->state) != FCS_ONLINE &&
3396 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 3397 fcport->login_retry--;
e315cd28 3398 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 3399 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 3400 ha->isp_ops->fabric_logout(vha,
3401 fcport->loop_id,
3402 fcport->d_id.b.domain,
3403 fcport->d_id.b.area,
3404 fcport->d_id.b.al_pa);
3405
03bcfb57
JC		 3406 if (fcport->loop_id == FC_NO_LOOP_ID) {
3407 fcport->loop_id = next_loopid =
3408 ha->min_external_loopid;
3409 status = qla2x00_find_new_loop_id(
3410 vha, fcport);
3411 if (status != QLA_SUCCESS) {
3412 /* Ran out of IDs to use */
3413 break;
3414 }
3415 }
3416
ac280b67 3417 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 3418 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 3419 data[0] = 0;
3420 data[1] = QLA_LOGIO_LOGIN_RETRIED;
3421 status = qla2x00_post_async_login_work(
3422 vha, fcport, data);
3423 if (status == QLA_SUCCESS)
3424 continue;
3425 /* Attempt a retry. */
3426 status = 1;
3427 } else
3428 status = qla2x00_fabric_login(vha,
3429 fcport, &next_loopid);
e315cd28
AC		 3430 } else
3431 status = qla2x00_local_device_login(vha,
3432 fcport);
3433
e315cd28
AC		 3434 if (status == QLA_SUCCESS) {
3435 fcport->old_loop_id = fcport->loop_id;
3436
7c3df132
SK		 3437 ql_dbg(ql_dbg_disc, vha, 0x2003,
3438 "Port login OK: logged in ID 0x%x.\n",
3439 fcport->loop_id);
e315cd28
AC		 3440
3441 qla2x00_update_fcport(vha, fcport);
3442
3443 } else if (status == 1) {
3444 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3445 /* retry the login again */
7c3df132
SK		 3446 ql_dbg(ql_dbg_disc, vha, 0x2007,
3447 "Retrying %d login again loop_id 0x%x.\n",
3448 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 3449 } else {
3450 fcport->login_retry = 0;
3451 }
3452
3453 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
3454 fcport->loop_id = FC_NO_LOOP_ID;
3455 }
3456 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3457 break;
0971de7f 3458 }
0971de7f
AV		 3459}
3460
1da177e4
LT		 3461/**************************************************************************
3462* qla2x00_do_dpc
3463* This kernel thread is a task that is schedule by the interrupt handler
3464* to perform the background processing for interrupts.
3465*
3466* Notes:
3467* This task always run in the context of a kernel thread. It
3468* is kick-off by the driver's detect code and starts up
3469* up one per adapter. It immediately goes to sleep and waits for
3470* some fibre event. When either the interrupt handler or
3471* the timer routine detects a event it will one of the task
3472* bits then wake us up.
3473**************************************************************************/
3474static int
3475qla2x00_do_dpc(void *data)
3476{
2c3dfe3f 3477 int rval;
e315cd28
AC		 3478 scsi_qla_host_t *base_vha;
3479 struct qla_hw_data *ha;
1da177e4 3480
e315cd28
AC		 3481 ha = (struct qla_hw_data *)data;
3482 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 3483
1da177e4
LT		 3484 set_user_nice(current, -20);
3485
563585ec 3486 set_current_state(TASK_INTERRUPTIBLE);
39a11240 3487 while (!kthread_should_stop()) {
7c3df132
SK		 3488 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
3489 "DPC handler sleeping.\n");
1da177e4 3490
39a11240
CH		 3491 schedule();
3492 __set_current_state(TASK_RUNNING);
1da177e4 3493
7c3df132
SK		 3494 ql_dbg(ql_dbg_dpc, base_vha, 0x4001,
3495 "DPC handler waking up.\n");
3496 ql_dbg(ql_dbg_dpc, base_vha, 0x4002,
3497 "dpc_flags=0x%lx.\n", base_vha->dpc_flags);
1da177e4
LT		 3498
3499 /* Initialization not yet finished. Don't do anything yet. */
e315cd28 3500 if (!base_vha->flags.init_done)
1da177e4
LT		 3501 continue;
3502
85880801 3503 if (ha->flags.eeh_busy) {
7c3df132
SK		 3504 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
3505 "eeh_busy=%d.\n", ha->flags.eeh_busy);
85880801
AV		 3506 continue;
3507 }
3508
1da177e4
LT		 3509 ha->dpc_active = 1;
3510
1da177e4 3511 if (ha->flags.mbox_busy) {
1da177e4
LT		 3512 ha->dpc_active = 0;
3513 continue;
3514 }
3515
e315cd28 3516 qla2x00_do_work(base_vha);
0971de7f 3517
a9083016
GM		 3518 if (IS_QLA82XX(ha)) {
3519 if (test_and_clear_bit(ISP_UNRECOVERABLE,
3520 &base_vha->dpc_flags)) {
3521 qla82xx_idc_lock(ha);
3522 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3523 QLA82XX_DEV_FAILED);
3524 qla82xx_idc_unlock(ha);
7c3df132
SK		 3525 ql_log(ql_log_info, base_vha, 0x4004,
3526 "HW State: FAILED.\n");
a9083016
GM		 3527 qla82xx_device_state_handler(base_vha);
3528 continue;
3529 }
3530
3531 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
3532 &base_vha->dpc_flags)) {
3533
7c3df132
SK		 3534 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
3535 "FCoE context reset scheduled.\n");
a9083016
GM		 3536 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
3537 &base_vha->dpc_flags))) {
3538 if (qla82xx_fcoe_ctx_reset(base_vha)) {
3539 /* FCoE-ctx reset failed.
3540 * Escalate to chip-reset
3541 */
3542 set_bit(ISP_ABORT_NEEDED,
3543 &base_vha->dpc_flags);
3544 }
3545 clear_bit(ABORT_ISP_ACTIVE,
3546 &base_vha->dpc_flags);
3547 }
3548
7c3df132
SK		 3549 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
3550 "FCoE context reset end.\n");
a9083016
GM		 3551 }
3552 }
3553
e315cd28
AC		 3554 if (test_and_clear_bit(ISP_ABORT_NEEDED,
3555 &base_vha->dpc_flags)) {
1da177e4 3556
7c3df132
SK		 3557 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
3558 "ISP abort scheduled.\n");
1da177e4 3559 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 3560 &base_vha->dpc_flags))) {
1da177e4 3561
a9083016 3562 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 3563 /* failed. retry later */
3564 set_bit(ISP_ABORT_NEEDED,
e315cd28 3565 &base_vha->dpc_flags);
99363ef8 3566 }
e315cd28
AC		 3567 clear_bit(ABORT_ISP_ACTIVE,
3568 &base_vha->dpc_flags);
99363ef8
SJ		 3569 }
3570
7c3df132
SK		 3571 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
3572 "ISP abort end.\n");
1da177e4
LT		 3573 }
3574
e315cd28
AC		 3575 if (test_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags)) {
3576 qla2x00_update_fcports(base_vha);
3577 clear_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
c9c5ced9 3578 }
d97994dc 3579
579d12b5 3580 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 3581 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
3582 "Quiescence mode scheduled.\n");
579d12b5
SK		 3583 qla82xx_device_state_handler(base_vha);
3584 clear_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags);
3585 if (!ha->flags.quiesce_owner) {
3586 qla2x00_perform_loop_resync(base_vha);
3587
3588 qla82xx_idc_lock(ha);
3589 qla82xx_clear_qsnt_ready(base_vha);
3590 qla82xx_idc_unlock(ha);
3591 }
7c3df132
SK		 3592 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
3593 "Quiescence mode end.\n");
579d12b5
SK		 3594 }
3595
e315cd28
AC		 3596 if (test_and_clear_bit(RESET_MARKER_NEEDED,
3597 &base_vha->dpc_flags) &&
3598 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 3599
7c3df132
SK		 3600 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
3601 "Reset marker scheduled.\n");
e315cd28
AC		 3602 qla2x00_rst_aen(base_vha);
3603 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 3604 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
3605 "Reset marker end.\n");
1da177e4
LT		 3606 }
3607
3608 /* Retry each device up to login retry count */
e315cd28
AC		 3609 if ((test_and_clear_bit(RELOGIN_NEEDED,
3610 &base_vha->dpc_flags)) &&
3611 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
3612 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 3613
7c3df132
SK		 3614 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
3615 "Relogin scheduled.\n");
e315cd28 3616 qla2x00_relogin(base_vha);
7c3df132
SK		 3617 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
3618 "Relogin end.\n");
1da177e4
LT		 3619 }
3620
e315cd28
AC		 3621 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
3622 &base_vha->dpc_flags)) {
1da177e4 3623
7c3df132
SK		 3624 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
3625 "Loop resync scheduled.\n");
1da177e4
LT		 3626
3627 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 3628 &base_vha->dpc_flags))) {
1da177e4 3629
e315cd28 3630 rval = qla2x00_loop_resync(base_vha);
1da177e4 3631
e315cd28
AC		 3632 clear_bit(LOOP_RESYNC_ACTIVE,
3633 &base_vha->dpc_flags);
1da177e4
LT		 3634 }
3635
7c3df132
SK		 3636 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
3637 "Loop resync end.\n");
1da177e4
LT		 3638 }
3639
e315cd28
AC		 3640 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
3641 atomic_read(&base_vha->loop_state) == LOOP_READY) {
3642 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
3643 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 3644 }
3645
1da177e4 3646 if (!ha->interrupts_on)
fd34f556 3647 ha->isp_ops->enable_intrs(ha);
1da177e4 3648
e315cd28
AC		 3649 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
3650 &base_vha->dpc_flags))
3651 ha->isp_ops->beacon_blink(base_vha);
f6df144c 3652
e315cd28 3653 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 3654
1da177e4 3655 ha->dpc_active = 0;
563585ec 3656 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 3657 } /* End of while(1) */
563585ec 3658 __set_current_state(TASK_RUNNING);
1da177e4 3659
7c3df132
SK		 3660 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
3661 "DPC handler exiting.\n");
1da177e4
LT		 3662
3663 /*
3664 * Make sure that nobody tries to wake us up again.
3665 */
1da177e4
LT		 3666 ha->dpc_active = 0;
3667
ac280b67
AV		 3668 /* Cleanup any residual CTX SRBs. */
3669 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3670
39a11240
CH		 3671 return 0;
3672}
3673
3674void
e315cd28 3675qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 3676{
e315cd28 3677 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 3678 struct task_struct *t = ha->dpc_thread;
3679
e315cd28 3680 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 3681 wake_up_process(t);
1da177e4
LT		 3682}
3683
1da177e4
LT		 3684/*
3685* qla2x00_rst_aen
3686* Processes asynchronous reset.
3687*
3688* Input:
3689* ha = adapter block pointer.
3690*/
3691static void
e315cd28 3692qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 3693{
e315cd28
AC		 3694 if (vha->flags.online && !vha->flags.reset_active &&
3695 !atomic_read(&vha->loop_down_timer) &&
3696 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 3697 do {
e315cd28 3698 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 3699
3700 /*
3701 * Issue marker command only when we are going to start
3702 * the I/O.
3703 */
e315cd28
AC		 3704 vha->marker_needed = 1;
3705 } while (!atomic_read(&vha->loop_down_timer) &&
3706 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 3707 }
3708}
3709
f4f051eb 3710static void
e315cd28 3711qla2x00_sp_free_dma(srb_t *sp)
f4f051eb 3712{
3713 struct scsi_cmnd *cmd = sp->cmd;
bad75002 3714 struct qla_hw_data *ha = sp->fcport->vha->hw;
f4f051eb 3715
3716 if (sp->flags & SRB_DMA_VALID) {
385d70b4 3717 scsi_dma_unmap(cmd);
f4f051eb 3718 sp->flags &= ~SRB_DMA_VALID;
3719 }
bad75002
AE		 3720
3721 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
3722 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
3723 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
3724 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
3725 }
3726
3727 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
3728 /* List assured to be having elements */
3729 qla2x00_clean_dsd_pool(ha, sp);
3730 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
3731 }
3732
3733 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
3734 dma_pool_free(ha->dl_dma_pool, sp->ctx,
3735 ((struct crc_context *)sp->ctx)->crc_ctx_dma);
3736 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
3737 }
3738
fca29703 3739 CMD_SP(cmd) = NULL;
f4f051eb 3740}
3741
3dbe756a 3742static void
083a469d 3743qla2x00_sp_final_compl(struct qla_hw_data *ha, srb_t *sp)
f4f051eb 3744{
3745 struct scsi_cmnd *cmd = sp->cmd;
3746
e315cd28 3747 qla2x00_sp_free_dma(sp);
f4f051eb 3748
a9083016
GM		 3749 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
3750 struct ct6_dsd *ctx = sp->ctx;
3751 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx->fcp_cmnd,
3752 ctx->fcp_cmnd_dma);
3753 list_splice(&ctx->dsd_list, &ha->gbl_dsd_list);
3754 ha->gbl_dsd_inuse -= ctx->dsd_use_cnt;
3755 ha->gbl_dsd_avail += ctx->dsd_use_cnt;
3756 mempool_free(sp->ctx, ha->ctx_mempool);
3757 sp->ctx = NULL;
3758 }
f4f051eb 3759
a9083016 3760 mempool_free(sp, ha->srb_mempool);
f4f051eb 3761 cmd->scsi_done(cmd);
3762}
bdf79621 3763
083a469d
GM		 3764void
3765qla2x00_sp_compl(struct qla_hw_data *ha, srb_t *sp)
3766{
3767 if (atomic_read(&sp->ref_count) == 0) {
7c3df132
SK		 3768 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
3769 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
3770 sp, sp->cmd);
3771 if (ql2xextended_error_logging & ql_dbg_io)
3772 BUG();
083a469d
GM		 3773 return;
3774 }
3775 if (!atomic_dec_and_test(&sp->ref_count))
3776 return;
3777 qla2x00_sp_final_compl(ha, sp);
3778}
3779
1da177e4
LT		 3780/**************************************************************************
3781* qla2x00_timer
3782*
3783* Description:
3784* One second timer
3785*
3786* Context: Interrupt
3787***************************************************************************/
2c3dfe3f 3788void
e315cd28 3789qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 3790{
1da177e4 3791 unsigned long cpu_flags = 0;
1da177e4
LT		 3792 int start_dpc = 0;
3793 int index;
3794 srb_t *sp;
85880801 3795 uint16_t w;
e315cd28 3796 struct qla_hw_data *ha = vha->hw;
73208dfd 3797 struct req_que *req;
85880801 3798
a5b36321 3799 if (ha->flags.eeh_busy) {
7c3df132
SK		 3800 ql_dbg(ql_dbg_timer, vha, 0x6000,
3801 "EEH = %d, restarting timer.\n",
3802 ha->flags.eeh_busy);
a5b36321
LC		 3803 qla2x00_restart_timer(vha, WATCH_INTERVAL);
3804 return;
3805 }
3806
85880801
AV		 3807 /* Hardware read to raise pending EEH errors during mailbox waits. */
3808 if (!pci_channel_offline(ha->pdev))
3809 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
1da177e4 3810
cefcaba6
SK		 3811 /* Make sure qla82xx_watchdog is run only for physical port */
3812 if (!vha->vp_idx && IS_QLA82XX(ha)) {
579d12b5
SK		 3813 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
3814 start_dpc++;
3815 qla82xx_watchdog(vha);
3816 }
3817
1da177e4 3818 /* Loop down handler. */
e315cd28 3819 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 3820 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
3821 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 3822 && vha->flags.online) {
1da177e4 3823
e315cd28
AC		 3824 if (atomic_read(&vha->loop_down_timer) ==
3825 vha->loop_down_abort_time) {
1da177e4 3826
7c3df132
SK		 3827 ql_log(ql_log_info, vha, 0x6008,
3828 "Loop down - aborting the queues before time expires.\n");
1da177e4 3829
e315cd28
AC		 3830 if (!IS_QLA2100(ha) && vha->link_down_timeout)
3831 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 3832
f08b7251
AV		 3833 /*
3834 * Schedule an ISP abort to return any FCP2-device
3835 * commands.
3836 */
2c3dfe3f 3837 /* NPIV - scan physical port only */
e315cd28 3838 if (!vha->vp_idx) {
2c3dfe3f
SJ		 3839 spin_lock_irqsave(&ha->hardware_lock,
3840 cpu_flags);
73208dfd 3841 req = ha->req_q_map[0];
2c3dfe3f
SJ		 3842 for (index = 1;
3843 index < MAX_OUTSTANDING_COMMANDS;
3844 index++) {
3845 fc_port_t *sfcp;
3846
e315cd28 3847 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 3848 if (!sp)
3849 continue;
bad75002 3850 if (sp->ctx && !IS_PROT_IO(sp))
cf53b069 3851 continue;
2c3dfe3f 3852 sfcp = sp->fcport;
f08b7251 3853 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 3854 continue;
bdf79621 3855
8f7daead
GM		 3856 if (IS_QLA82XX(ha))
3857 set_bit(FCOE_CTX_RESET_NEEDED,
3858 &vha->dpc_flags);
3859 else
3860 set_bit(ISP_ABORT_NEEDED,
e315cd28 3861 &vha->dpc_flags);
2c3dfe3f
SJ		 3862 break;
3863 }
3864 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 3865 cpu_flags);
1da177e4 3866 }
1da177e4
LT		 3867 start_dpc++;
3868 }
3869
3870 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 3871 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 3872 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 3873 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 3874 "Loop down - aborting ISP.\n");
3875
8f7daead
GM		 3876 if (IS_QLA82XX(ha))
3877 set_bit(FCOE_CTX_RESET_NEEDED,
3878 &vha->dpc_flags);
3879 else
3880 set_bit(ISP_ABORT_NEEDED,
3881 &vha->dpc_flags);
1da177e4
LT		 3882 }
3883 }
7c3df132
SK		 3884 ql_dbg(ql_dbg_timer, vha, 0x600a,
3885 "Loop down - seconds remaining %d.\n",
3886 atomic_read(&vha->loop_down_timer));
1da177e4
LT		 3887 }
3888
cefcaba6
SK		 3889 /* Check if beacon LED needs to be blinked for physical host only */
3890 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
e315cd28 3891 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
f6df144c 3892 start_dpc++;
3893 }
3894
550bf57d 3895 /* Process any deferred work. */
e315cd28 3896 if (!list_empty(&vha->work_list))
550bf57d
AV		 3897 start_dpc++;
3898
1da177e4 3899 /* Schedule the DPC routine if needed */
e315cd28
AC		 3900 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
3901 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
3902 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 3903 start_dpc ||
e315cd28
AC		 3904 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
3905 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 3906 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
3907 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 3908 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
7c3df132
SK		 3909 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
3910 ql_dbg(ql_dbg_timer, vha, 0x600b,
3911 "isp_abort_needed=%d loop_resync_needed=%d "
3912 "fcport_update_needed=%d start_dpc=%d "
3913 "reset_marker_needed=%d",
3914 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
3915 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
3916 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
3917 start_dpc,
3918 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
3919 ql_dbg(ql_dbg_timer, vha, 0x600c,
3920 "beacon_blink_needed=%d isp_unrecoverable=%d "
3921 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
3922 "relogin_needed=%d.\n",
3923 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
3924 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
3925 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
3926 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
3927 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 3928 qla2xxx_wake_dpc(vha);
7c3df132 3929 }
1da177e4 3930
e315cd28 3931 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 3932}
3933
5433383e
AV		 3934/* Firmware interface routines. */
3935
a9083016 3936#define FW_BLOBS 8
5433383e
AV		 3937#define FW_ISP21XX 0
3938#define FW_ISP22XX 1
3939#define FW_ISP2300 2
3940#define FW_ISP2322 3
48c02fde 3941#define FW_ISP24XX 4
c3a2f0df 3942#define FW_ISP25XX 5
3a03eb79 3943#define FW_ISP81XX 6
a9083016 3944#define FW_ISP82XX 7
5433383e 3945
bb8ee499
AV		 3946#define FW_FILE_ISP21XX "ql2100_fw.bin"
3947#define FW_FILE_ISP22XX "ql2200_fw.bin"
3948#define FW_FILE_ISP2300 "ql2300_fw.bin"
3949#define FW_FILE_ISP2322 "ql2322_fw.bin"
3950#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 3951#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 3952#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 3953#define FW_FILE_ISP82XX "ql8200_fw.bin"
bb8ee499 3954
e1e82b6f 3955static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 3956
3957static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 3958 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
3959 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
3960 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
3961 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
3962 { .name = FW_FILE_ISP24XX, },
c3a2f0df 3963 { .name = FW_FILE_ISP25XX, },
3a03eb79 3964 { .name = FW_FILE_ISP81XX, },
a9083016 3965 { .name = FW_FILE_ISP82XX, },
5433383e
AV		 3966};
3967
3968struct fw_blob *
e315cd28 3969qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 3970{
e315cd28 3971 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 3972 struct fw_blob *blob;
3973
3974 blob = NULL;
3975 if (IS_QLA2100(ha)) {
3976 blob = &qla_fw_blobs[FW_ISP21XX];
3977 } else if (IS_QLA2200(ha)) {
3978 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 3979 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 3980 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 3981 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 3982 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 3983 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 3984 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 3985 } else if (IS_QLA25XX(ha)) {
3986 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 3987 } else if (IS_QLA81XX(ha)) {
3988 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 3989 } else if (IS_QLA82XX(ha)) {
3990 blob = &qla_fw_blobs[FW_ISP82XX];
5433383e
AV		 3991 }
3992
e1e82b6f 3993 mutex_lock(&qla_fw_lock);
5433383e
AV		 3994 if (blob->fw)
3995 goto out;
3996
3997 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 3998 ql_log(ql_log_warn, vha, 0x0063,
3999 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 4000 blob->fw = NULL;
4001 blob = NULL;
4002 goto out;
4003 }
4004
4005out:
e1e82b6f 4006 mutex_unlock(&qla_fw_lock);
5433383e
AV		 4007 return blob;
4008}
4009
4010static void
4011qla2x00_release_firmware(void)
4012{
4013 int idx;
4014
e1e82b6f 4015 mutex_lock(&qla_fw_lock);
5433383e
AV		 4016 for (idx = 0; idx < FW_BLOBS; idx++)
4017 if (qla_fw_blobs[idx].fw)
4018 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 4019 mutex_unlock(&qla_fw_lock);
5433383e
AV		 4020}
4021
14e660e6
SJ		 4022static pci_ers_result_t
4023qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
4024{
85880801
AV		 4025 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
4026 struct qla_hw_data *ha = vha->hw;
4027
7c3df132
SK		 4028 ql_dbg(ql_dbg_aer, vha, 0x9000,
4029 "PCI error detected, state %x.\n", state);
b9b12f73 4030
14e660e6
SJ		 4031 switch (state) {
4032 case pci_channel_io_normal:
85880801 4033 ha->flags.eeh_busy = 0;
14e660e6
SJ		 4034 return PCI_ERS_RESULT_CAN_RECOVER;
4035 case pci_channel_io_frozen:
85880801 4036 ha->flags.eeh_busy = 1;
a5b36321
LC		 4037 /* For ISP82XX complete any pending mailbox cmd */
4038 if (IS_QLA82XX(ha)) {
7190575f 4039 ha->flags.isp82xx_fw_hung = 1;
a5b36321
LC		 4040 if (ha->flags.mbox_busy) {
4041 ha->flags.mbox_int = 1;
7c3df132
SK		 4042 ql_dbg(ql_dbg_aer, vha, 0x9001,
4043 "Due to pci channel io frozen, doing premature "
4044 "completion of mbx command.\n");
a5b36321
LC		 4045 complete(&ha->mbx_intr_comp);
4046 }
4047 }
90a86fc0 4048 qla2x00_free_irqs(vha);
14e660e6 4049 pci_disable_device(pdev);
bddd2d65
LC		 4050 /* Return back all IOs */
4051 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
14e660e6
SJ		 4052 return PCI_ERS_RESULT_NEED_RESET;
4053 case pci_channel_io_perm_failure:
85880801
AV		 4054 ha->flags.pci_channel_io_perm_failure = 1;
4055 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
14e660e6
SJ		 4056 return PCI_ERS_RESULT_DISCONNECT;
4057 }
4058 return PCI_ERS_RESULT_NEED_RESET;
4059}
4060
4061static pci_ers_result_t
4062qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
4063{
4064 int risc_paused = 0;
4065 uint32_t stat;
4066 unsigned long flags;
e315cd28
AC		 4067 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
4068 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 4069 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
4070 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
4071
bcc5b6d3
SK		 4072 if (IS_QLA82XX(ha))
4073 return PCI_ERS_RESULT_RECOVERED;
4074
14e660e6
SJ		 4075 spin_lock_irqsave(&ha->hardware_lock, flags);
4076 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
4077 stat = RD_REG_DWORD(&reg->hccr);
4078 if (stat & HCCR_RISC_PAUSE)
4079 risc_paused = 1;
4080 } else if (IS_QLA23XX(ha)) {
4081 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
4082 if (stat & HSR_RISC_PAUSED)
4083 risc_paused = 1;
4084 } else if (IS_FWI2_CAPABLE(ha)) {
4085 stat = RD_REG_DWORD(&reg24->host_status);
4086 if (stat & HSRX_RISC_PAUSED)
4087 risc_paused = 1;
4088 }
4089 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4090
4091 if (risc_paused) {
7c3df132
SK		 4092 ql_log(ql_log_info, base_vha, 0x9003,
4093 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 4094 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 4095
4096 return PCI_ERS_RESULT_NEED_RESET;
4097 } else
4098 return PCI_ERS_RESULT_RECOVERED;
4099}
4100
a5b36321
LC		 4101uint32_t qla82xx_error_recovery(scsi_qla_host_t *base_vha)
4102{
4103 uint32_t rval = QLA_FUNCTION_FAILED;
4104 uint32_t drv_active = 0;
4105 struct qla_hw_data *ha = base_vha->hw;
4106 int fn;
4107 struct pci_dev *other_pdev = NULL;
4108
7c3df132
SK		 4109 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
4110 "Entered %s.\n", __func__);
a5b36321
LC		 4111
4112 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
4113
4114 if (base_vha->flags.online) {
4115 /* Abort all outstanding commands,
4116 * so as to be requeued later */
4117 qla2x00_abort_isp_cleanup(base_vha);
4118 }
4119
4120
4121 fn = PCI_FUNC(ha->pdev->devfn);
4122 while (fn > 0) {
4123 fn--;
7c3df132
SK		 4124 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
4125 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 4126 other_pdev =
4127 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
4128 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
4129 fn));
4130
4131 if (!other_pdev)
4132 continue;
4133 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 4134 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
4135 "Found PCI func available and enable at 0x%x.\n",
4136 fn);
a5b36321
LC		 4137 pci_dev_put(other_pdev);
4138 break;
4139 }
4140 pci_dev_put(other_pdev);
4141 }
4142
4143 if (!fn) {
4144 /* Reset owner */
7c3df132
SK		 4145 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
4146 "This devfn is reset owner = 0x%x.\n",
4147 ha->pdev->devfn);
a5b36321
LC		 4148 qla82xx_idc_lock(ha);
4149
4150 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4151 QLA82XX_DEV_INITIALIZING);
4152
4153 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
4154 QLA82XX_IDC_VERSION);
4155
4156 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 4157 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
4158 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 4159
4160 qla82xx_idc_unlock(ha);
4161 /* Reset if device is not already reset
4162 * drv_active would be 0 if a reset has already been done
4163 */
4164 if (drv_active)
4165 rval = qla82xx_start_firmware(base_vha);
4166 else
4167 rval = QLA_SUCCESS;
4168 qla82xx_idc_lock(ha);
4169
4170 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4171 ql_log(ql_log_info, base_vha, 0x900b,
4172 "HW State: FAILED.\n");
a5b36321
LC		 4173 qla82xx_clear_drv_active(ha);
4174 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4175 QLA82XX_DEV_FAILED);
4176 } else {
7c3df132
SK		 4177 ql_log(ql_log_info, base_vha, 0x900c,
4178 "HW State: READY.\n");
a5b36321
LC		 4179 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4180 QLA82XX_DEV_READY);
4181 qla82xx_idc_unlock(ha);
7190575f 4182 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 4183 rval = qla82xx_restart_isp(base_vha);
4184 qla82xx_idc_lock(ha);
4185 /* Clear driver state register */
4186 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
4187 qla82xx_set_drv_active(base_vha);
4188 }
4189 qla82xx_idc_unlock(ha);
4190 } else {
7c3df132
SK		 4191 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
4192 "This devfn is not reset owner = 0x%x.\n",
4193 ha->pdev->devfn);
a5b36321
LC		 4194 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
4195 QLA82XX_DEV_READY)) {
7190575f 4196 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 4197 rval = qla82xx_restart_isp(base_vha);
4198 qla82xx_idc_lock(ha);
4199 qla82xx_set_drv_active(base_vha);
4200 qla82xx_idc_unlock(ha);
4201 }
4202 }
4203 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
4204
4205 return rval;
4206}
4207
14e660e6
SJ		 4208static pci_ers_result_t
4209qla2xxx_pci_slot_reset(struct pci_dev *pdev)
4210{
4211 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 4212 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
4213 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 4214 struct rsp_que *rsp;
4215 int rc, retries = 10;
09483916 4216
7c3df132
SK		 4217 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
4218 "Slot Reset.\n");
85880801 4219
90a86fc0
JC		 4220 /* Workaround: qla2xxx driver which access hardware earlier
4221 * needs error state to be pci_channel_io_online.
4222 * Otherwise mailbox command timesout.
4223 */
4224 pdev->error_state = pci_channel_io_normal;
4225
4226 pci_restore_state(pdev);
4227
8c1496bd
RL		 4228 /* pci_restore_state() clears the saved_state flag of the device
4229 * save restored state which resets saved_state flag
4230 */
4231 pci_save_state(pdev);
4232
09483916
BH		 4233 if (ha->mem_only)
4234 rc = pci_enable_device_mem(pdev);
4235 else
4236 rc = pci_enable_device(pdev);
14e660e6 4237
09483916 4238 if (rc) {
7c3df132 4239 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 4240 "Can't re-enable PCI device after reset.\n");
a5b36321 4241 goto exit_slot_reset;
14e660e6 4242 }
14e660e6 4243
90a86fc0
JC		 4244 rsp = ha->rsp_q_map[0];
4245 if (qla2x00_request_irqs(ha, rsp))
a5b36321 4246 goto exit_slot_reset;
90a86fc0 4247
e315cd28 4248 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 4249 goto exit_slot_reset;
4250
4251 if (IS_QLA82XX(ha)) {
4252 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
4253 ret = PCI_ERS_RESULT_RECOVERED;
4254 goto exit_slot_reset;
4255 } else
4256 goto exit_slot_reset;
4257 }
14e660e6 4258
90a86fc0
JC		 4259 while (ha->flags.mbox_busy && retries--)
4260 msleep(1000);
85880801 4261
e315cd28 4262 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 4263 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 4264 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 4265 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 4266
90a86fc0 4267
a5b36321 4268exit_slot_reset:
7c3df132
SK		 4269 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
4270 "slot_reset return %x.\n", ret);
85880801 4271
14e660e6
SJ		 4272 return ret;
4273}
4274
4275static void
4276qla2xxx_pci_resume(struct pci_dev *pdev)
4277{
e315cd28
AC		 4278 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
4279 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 4280 int ret;
4281
7c3df132
SK		 4282 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
4283 "pci_resume.\n");
85880801 4284
e315cd28 4285 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 4286 if (ret != QLA_SUCCESS) {
7c3df132
SK		 4287 ql_log(ql_log_fatal, base_vha, 0x9002,
4288 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 4289 }
85880801 4290
3e46f031
LC		 4291 pci_cleanup_aer_uncorrect_error_status(pdev);
4292
85880801 4293 ha->flags.eeh_busy = 0;
14e660e6
SJ		 4294}
4295
4296static struct pci_error_handlers qla2xxx_err_handler = {
4297 .error_detected = qla2xxx_pci_error_detected,
4298 .mmio_enabled = qla2xxx_pci_mmio_enabled,
4299 .slot_reset = qla2xxx_pci_slot_reset,
4300 .resume = qla2xxx_pci_resume,
4301};
4302
5433383e 4303static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 4304 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
4305 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
4306 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
4307 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
4308 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
4309 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
4310 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
4311 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
4312 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 4313 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 4314 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
4315 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 4316 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
3a03eb79 4317 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 4318 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
5433383e
AV		 4319 { 0 },
4320};
4321MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
4322
fca29703 4323static struct pci_driver qla2xxx_pci_driver = {
cb63067a 4324 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 4325 .driver = {
4326 .owner = THIS_MODULE,
4327 },
fca29703 4328 .id_table = qla2xxx_pci_tbl,
7ee61397 4329 .probe = qla2x00_probe_one,
4c993f76 4330 .remove = qla2x00_remove_one,
e30d1756 4331 .shutdown = qla2x00_shutdown,
14e660e6 4332 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 4333};
4334
6a03b4cd
HZ		 4335static struct file_operations apidev_fops = {
4336 .owner = THIS_MODULE,
6038f373 4337 .llseek = noop_llseek,
6a03b4cd
HZ		 4338};
4339
1da177e4
LT		 4340/**
4341 * qla2x00_module_init - Module initialization.
4342 **/
4343static int __init
4344qla2x00_module_init(void)
4345{
fca29703
AV		 4346 int ret = 0;
4347
1da177e4 4348 /* Allocate cache for SRBs. */
354d6b21 4349 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 4350 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 4351 if (srb_cachep == NULL) {
7c3df132
SK		 4352 ql_log(ql_log_fatal, NULL, 0x0001,
4353 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 4354 return -ENOMEM;
4355 }
4356
4357 /* Derive version string. */
4358 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 4359 if (ql2xextended_error_logging)
0181944f
AV		 4360 strcat(qla2x00_version_str, "-debug");
4361
1c97a12a
AV		 4362 qla2xxx_transport_template =
4363 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 4364 if (!qla2xxx_transport_template) {
4365 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 4366 ql_log(ql_log_fatal, NULL, 0x0002,
4367 "fc_attach_transport failed...Failing load!.\n");
1da177e4 4368 return -ENODEV;
2c3dfe3f 4369 }
6a03b4cd
HZ		 4370
4371 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
4372 if (apidev_major < 0) {
7c3df132
SK		 4373 ql_log(ql_log_fatal, NULL, 0x0003,
4374 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 4375 }
4376
2c3dfe3f
SJ		 4377 qla2xxx_transport_vport_template =
4378 fc_attach_transport(&qla2xxx_transport_vport_functions);
4379 if (!qla2xxx_transport_vport_template) {
4380 kmem_cache_destroy(srb_cachep);
4381 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 4382 ql_log(ql_log_fatal, NULL, 0x0004,
4383 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 4384 return -ENODEV;
2c3dfe3f 4385 }
7c3df132
SK		 4386 ql_log(ql_log_info, NULL, 0x0005,
4387 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 4388 qla2x00_version_str);
7ee61397 4389 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 4390 if (ret) {
4391 kmem_cache_destroy(srb_cachep);
4392 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 4393 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 4394 ql_log(ql_log_fatal, NULL, 0x0006,
4395 "pci_register_driver failed...ret=%d Failing load!.\n",
4396 ret);
fca29703
AV		 4397 }
4398 return ret;
1da177e4
LT		 4399}
4400
4401/**
4402 * qla2x00_module_exit - Module cleanup.
4403 **/
4404static void __exit
4405qla2x00_module_exit(void)
4406{
6a03b4cd 4407 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 4408 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 4409 qla2x00_release_firmware();
354d6b21 4410 kmem_cache_destroy(srb_cachep);
a9083016
GM		 4411 if (ctx_cachep)
4412 kmem_cache_destroy(ctx_cachep);
1da177e4 4413 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 4414 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 4415}
4416
4417module_init(qla2x00_module_init);
4418module_exit(qla2x00_module_exit);
4419
4420MODULE_AUTHOR("QLogic Corporation");
4421MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
4422MODULE_LICENSE("GPL");
4423MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 4424MODULE_FIRMWARE(FW_FILE_ISP21XX);
4425MODULE_FIRMWARE(FW_FILE_ISP22XX);
4426MODULE_FIRMWARE(FW_FILE_ISP2300);
4427MODULE_FIRMWARE(FW_FILE_ISP2322);
4428MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 4429MODULE_FIRMWARE(FW_FILE_ISP25XX);
Linux kernel - Deliverables
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