Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
fa90c54f | 2 | * QLogic Fibre Channel HBA Driver |
07e264b7 | 3 | * Copyright (c) 2003-2011 QLogic Corporation |
1da177e4 | 4 | * |
fa90c54f | 5 | * See LICENSE.qla2xxx for copyright and licensing details. |
1da177e4 LT |
6 | */ |
7 | #include "qla_def.h" | |
8 | ||
9 | #include <linux/moduleparam.h> | |
10 | #include <linux/vmalloc.h> | |
1da177e4 | 11 | #include <linux/delay.h> |
39a11240 | 12 | #include <linux/kthread.h> |
e1e82b6f | 13 | #include <linux/mutex.h> |
3420d36c | 14 | #include <linux/kobject.h> |
5a0e3ad6 | 15 | #include <linux/slab.h> |
1da177e4 LT |
16 | #include <scsi/scsi_tcq.h> |
17 | #include <scsi/scsicam.h> | |
18 | #include <scsi/scsi_transport.h> | |
19 | #include <scsi/scsi_transport_fc.h> | |
20 | ||
2d70c103 NB |
21 | #include "qla_target.h" |
22 | ||
1da177e4 LT |
23 | /* |
24 | * Driver version | |
25 | */ | |
26 | char qla2x00_version_str[40]; | |
27 | ||
6a03b4cd HZ |
28 | static int apidev_major; |
29 | ||
1da177e4 LT |
30 | /* |
31 | * SRB allocation cache | |
32 | */ | |
e18b890b | 33 | static struct kmem_cache *srb_cachep; |
1da177e4 | 34 | |
a9083016 GM |
35 | /* |
36 | * CT6 CTX allocation cache | |
37 | */ | |
38 | static struct kmem_cache *ctx_cachep; | |
3ce8866c SK |
39 | /* |
40 | * error level for logging | |
41 | */ | |
42 | int ql_errlev = ql_log_all; | |
a9083016 | 43 | |
2d70c103 NB |
44 | int ql2xenableclass2; |
45 | module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); | |
46 | MODULE_PARM_DESC(ql2xenableclass2, | |
47 | "Specify if Class 2 operations are supported from the very " | |
48 | "beginning. Default is 0 - class 2 not supported."); | |
49 | ||
1da177e4 | 50 | int ql2xlogintimeout = 20; |
f2019cb1 | 51 | module_param(ql2xlogintimeout, int, S_IRUGO); |
1da177e4 LT |
52 | MODULE_PARM_DESC(ql2xlogintimeout, |
53 | "Login timeout value in seconds."); | |
54 | ||
a7b61842 | 55 | int qlport_down_retry; |
f2019cb1 | 56 | module_param(qlport_down_retry, int, S_IRUGO); |
1da177e4 | 57 | MODULE_PARM_DESC(qlport_down_retry, |
900d9f98 | 58 | "Maximum number of command retries to a port that returns " |
1da177e4 LT |
59 | "a PORT-DOWN status."); |
60 | ||
1da177e4 LT |
61 | int ql2xplogiabsentdevice; |
62 | module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); | |
63 | MODULE_PARM_DESC(ql2xplogiabsentdevice, | |
64 | "Option to enable PLOGI to devices that are not present after " | |
900d9f98 | 65 | "a Fabric scan. This is needed for several broken switches. " |
1da177e4 LT |
66 | "Default is 0 - no PLOGI. 1 - perfom PLOGI."); |
67 | ||
1da177e4 | 68 | int ql2xloginretrycount = 0; |
f2019cb1 | 69 | module_param(ql2xloginretrycount, int, S_IRUGO); |
1da177e4 LT |
70 | MODULE_PARM_DESC(ql2xloginretrycount, |
71 | "Specify an alternate value for the NVRAM login retry count."); | |
72 | ||
a7a167bf | 73 | int ql2xallocfwdump = 1; |
f2019cb1 | 74 | module_param(ql2xallocfwdump, int, S_IRUGO); |
a7a167bf AV |
75 | MODULE_PARM_DESC(ql2xallocfwdump, |
76 | "Option to enable allocation of memory for a firmware dump " | |
77 | "during HBA initialization. Memory allocation requirements " | |
78 | "vary by ISP type. Default is 1 - allocate memory."); | |
79 | ||
11010fec | 80 | int ql2xextended_error_logging; |
27d94035 | 81 | module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); |
11010fec | 82 | MODULE_PARM_DESC(ql2xextended_error_logging, |
3ce8866c SK |
83 | "Option to enable extended error logging,\n" |
84 | "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" | |
85 | "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" | |
86 | "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" | |
87 | "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" | |
88 | "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" | |
89 | "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" | |
90 | "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" | |
91 | "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" | |
92 | "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" | |
cfb0919c CD |
93 | "\t\t0x1e400000 - Preferred value for capturing essential " |
94 | "debug information (equivalent to old " | |
95 | "ql2xextended_error_logging=1).\n" | |
3ce8866c | 96 | "\t\tDo LOGICAL OR of the value to enable more than one level"); |
0181944f | 97 | |
a9083016 | 98 | int ql2xshiftctondsd = 6; |
f2019cb1 | 99 | module_param(ql2xshiftctondsd, int, S_IRUGO); |
a9083016 GM |
100 | MODULE_PARM_DESC(ql2xshiftctondsd, |
101 | "Set to control shifting of command type processing " | |
102 | "based on total number of SG elements."); | |
103 | ||
1da177e4 LT |
104 | static void qla2x00_free_device(scsi_qla_host_t *); |
105 | ||
7e47e5ca | 106 | int ql2xfdmienable=1; |
f2019cb1 | 107 | module_param(ql2xfdmienable, int, S_IRUGO); |
cca5335c | 108 | MODULE_PARM_DESC(ql2xfdmienable, |
7794a5af FW |
109 | "Enables FDMI registrations. " |
110 | "0 - no FDMI. Default is 1 - perform FDMI."); | |
cca5335c | 111 | |
df7baa50 AV |
112 | #define MAX_Q_DEPTH 32 |
113 | static int ql2xmaxqdepth = MAX_Q_DEPTH; | |
114 | module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); | |
115 | MODULE_PARM_DESC(ql2xmaxqdepth, | |
116 | "Maximum queue depth to report for target devices."); | |
117 | ||
bad75002 | 118 | /* Do not change the value of this after module load */ |
8cb2049c | 119 | int ql2xenabledif = 0; |
bad75002 AE |
120 | module_param(ql2xenabledif, int, S_IRUGO|S_IWUSR); |
121 | MODULE_PARM_DESC(ql2xenabledif, | |
122 | " Enable T10-CRC-DIF " | |
8cb2049c AE |
123 | " Default is 0 - No DIF Support. 1 - Enable it" |
124 | ", 2 - Enable DIF for all types, except Type 0."); | |
bad75002 | 125 | |
8cb2049c | 126 | int ql2xenablehba_err_chk = 2; |
bad75002 AE |
127 | module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); |
128 | MODULE_PARM_DESC(ql2xenablehba_err_chk, | |
8cb2049c AE |
129 | " Enable T10-CRC-DIF Error isolation by HBA:\n" |
130 | " Default is 1.\n" | |
131 | " 0 -- Error isolation disabled\n" | |
132 | " 1 -- Error isolation enabled only for DIX Type 0\n" | |
133 | " 2 -- Error isolation enabled for all Types\n"); | |
bad75002 | 134 | |
e5896bd5 | 135 | int ql2xiidmaenable=1; |
f2019cb1 | 136 | module_param(ql2xiidmaenable, int, S_IRUGO); |
e5896bd5 AV |
137 | MODULE_PARM_DESC(ql2xiidmaenable, |
138 | "Enables iIDMA settings " | |
139 | "Default is 1 - perform iIDMA. 0 - no iIDMA."); | |
140 | ||
73208dfd | 141 | int ql2xmaxqueues = 1; |
f2019cb1 | 142 | module_param(ql2xmaxqueues, int, S_IRUGO); |
73208dfd AC |
143 | MODULE_PARM_DESC(ql2xmaxqueues, |
144 | "Enables MQ settings " | |
ae68230c JP |
145 | "Default is 1 for single queue. Set it to number " |
146 | "of queues in MQ mode."); | |
68ca949c AC |
147 | |
148 | int ql2xmultique_tag; | |
f2019cb1 | 149 | module_param(ql2xmultique_tag, int, S_IRUGO); |
68ca949c AC |
150 | MODULE_PARM_DESC(ql2xmultique_tag, |
151 | "Enables CPU affinity settings for the driver " | |
152 | "Default is 0 for no affinity of request and response IO. " | |
153 | "Set it to 1 to turn on the cpu affinity."); | |
e337d907 AV |
154 | |
155 | int ql2xfwloadbin; | |
86e45bf6 | 156 | module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); |
e337d907 | 157 | MODULE_PARM_DESC(ql2xfwloadbin, |
7c3df132 SK |
158 | "Option to specify location from which to load ISP firmware:.\n" |
159 | " 2 -- load firmware via the request_firmware() (hotplug).\n" | |
e337d907 AV |
160 | " interface.\n" |
161 | " 1 -- load firmware from flash.\n" | |
162 | " 0 -- use default semantics.\n"); | |
163 | ||
ae97c91e | 164 | int ql2xetsenable; |
f2019cb1 | 165 | module_param(ql2xetsenable, int, S_IRUGO); |
ae97c91e AV |
166 | MODULE_PARM_DESC(ql2xetsenable, |
167 | "Enables firmware ETS burst." | |
168 | "Default is 0 - skip ETS enablement."); | |
169 | ||
6907869d | 170 | int ql2xdbwr = 1; |
86e45bf6 | 171 | module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); |
a9083016 | 172 | MODULE_PARM_DESC(ql2xdbwr, |
08de2844 GM |
173 | "Option to specify scheme for request queue posting.\n" |
174 | " 0 -- Regular doorbell.\n" | |
175 | " 1 -- CAMRAM doorbell (faster).\n"); | |
a9083016 | 176 | |
f4c496c1 | 177 | int ql2xtargetreset = 1; |
f2019cb1 | 178 | module_param(ql2xtargetreset, int, S_IRUGO); |
f4c496c1 GM |
179 | MODULE_PARM_DESC(ql2xtargetreset, |
180 | "Enable target reset." | |
181 | "Default is 1 - use hw defaults."); | |
182 | ||
4da26e16 | 183 | int ql2xgffidenable; |
f2019cb1 | 184 | module_param(ql2xgffidenable, int, S_IRUGO); |
4da26e16 CD |
185 | MODULE_PARM_DESC(ql2xgffidenable, |
186 | "Enables GFF_ID checks of port type. " | |
187 | "Default is 0 - Do not use GFF_ID information."); | |
a9083016 | 188 | |
3822263e | 189 | int ql2xasynctmfenable; |
f2019cb1 | 190 | module_param(ql2xasynctmfenable, int, S_IRUGO); |
3822263e MI |
191 | MODULE_PARM_DESC(ql2xasynctmfenable, |
192 | "Enables issue of TM IOCBs asynchronously via IOCB mechanism" | |
193 | "Default is 0 - Issue TM IOCBs via mailbox mechanism."); | |
ed0de87c GM |
194 | |
195 | int ql2xdontresethba; | |
86e45bf6 | 196 | module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); |
ed0de87c | 197 | MODULE_PARM_DESC(ql2xdontresethba, |
08de2844 GM |
198 | "Option to specify reset behaviour.\n" |
199 | " 0 (Default) -- Reset on failure.\n" | |
200 | " 1 -- Do not reset on failure.\n"); | |
ed0de87c | 201 | |
82515920 AV |
202 | uint ql2xmaxlun = MAX_LUNS; |
203 | module_param(ql2xmaxlun, uint, S_IRUGO); | |
204 | MODULE_PARM_DESC(ql2xmaxlun, | |
205 | "Defines the maximum LU number to register with the SCSI " | |
206 | "midlayer. Default is 65535."); | |
207 | ||
08de2844 GM |
208 | int ql2xmdcapmask = 0x1F; |
209 | module_param(ql2xmdcapmask, int, S_IRUGO); | |
210 | MODULE_PARM_DESC(ql2xmdcapmask, | |
211 | "Set the Minidump driver capture mask level. " | |
6e96fa7b | 212 | "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); |
08de2844 | 213 | |
3aadff35 | 214 | int ql2xmdenable = 1; |
08de2844 GM |
215 | module_param(ql2xmdenable, int, S_IRUGO); |
216 | MODULE_PARM_DESC(ql2xmdenable, | |
217 | "Enable/disable MiniDump. " | |
3aadff35 GM |
218 | "0 - MiniDump disabled. " |
219 | "1 (Default) - MiniDump enabled."); | |
08de2844 | 220 | |
1da177e4 | 221 | /* |
fa2a1ce5 | 222 | * SCSI host template entry points |
1da177e4 LT |
223 | */ |
224 | static int qla2xxx_slave_configure(struct scsi_device * device); | |
f4f051eb | 225 | static int qla2xxx_slave_alloc(struct scsi_device *); |
1e99e33a AV |
226 | static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time); |
227 | static void qla2xxx_scan_start(struct Scsi_Host *); | |
f4f051eb | 228 | static void qla2xxx_slave_destroy(struct scsi_device *); |
f281233d | 229 | static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd); |
1da177e4 LT |
230 | static int qla2xxx_eh_abort(struct scsi_cmnd *); |
231 | static int qla2xxx_eh_device_reset(struct scsi_cmnd *); | |
523ec773 | 232 | static int qla2xxx_eh_target_reset(struct scsi_cmnd *); |
1da177e4 LT |
233 | static int qla2xxx_eh_bus_reset(struct scsi_cmnd *); |
234 | static int qla2xxx_eh_host_reset(struct scsi_cmnd *); | |
1da177e4 | 235 | |
e881a172 | 236 | static int qla2x00_change_queue_depth(struct scsi_device *, int, int); |
ce7e4af7 AV |
237 | static int qla2x00_change_queue_type(struct scsi_device *, int); |
238 | ||
a5326f86 | 239 | struct scsi_host_template qla2xxx_driver_template = { |
1da177e4 | 240 | .module = THIS_MODULE, |
cb63067a | 241 | .name = QLA2XXX_DRIVER_NAME, |
a5326f86 | 242 | .queuecommand = qla2xxx_queuecommand, |
fca29703 AV |
243 | |
244 | .eh_abort_handler = qla2xxx_eh_abort, | |
245 | .eh_device_reset_handler = qla2xxx_eh_device_reset, | |
523ec773 | 246 | .eh_target_reset_handler = qla2xxx_eh_target_reset, |
fca29703 AV |
247 | .eh_bus_reset_handler = qla2xxx_eh_bus_reset, |
248 | .eh_host_reset_handler = qla2xxx_eh_host_reset, | |
249 | ||
250 | .slave_configure = qla2xxx_slave_configure, | |
251 | ||
252 | .slave_alloc = qla2xxx_slave_alloc, | |
253 | .slave_destroy = qla2xxx_slave_destroy, | |
ed677086 AV |
254 | .scan_finished = qla2xxx_scan_finished, |
255 | .scan_start = qla2xxx_scan_start, | |
ce7e4af7 AV |
256 | .change_queue_depth = qla2x00_change_queue_depth, |
257 | .change_queue_type = qla2x00_change_queue_type, | |
fca29703 AV |
258 | .this_id = -1, |
259 | .cmd_per_lun = 3, | |
260 | .use_clustering = ENABLE_CLUSTERING, | |
261 | .sg_tablesize = SG_ALL, | |
262 | ||
263 | .max_sectors = 0xFFFF, | |
afb046e2 | 264 | .shost_attrs = qla2x00_host_attrs, |
2d70c103 NB |
265 | |
266 | .supported_mode = MODE_INITIATOR, | |
fca29703 AV |
267 | }; |
268 | ||
1da177e4 | 269 | static struct scsi_transport_template *qla2xxx_transport_template = NULL; |
2c3dfe3f | 270 | struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; |
1da177e4 | 271 | |
1da177e4 LT |
272 | /* TODO Convert to inlines |
273 | * | |
274 | * Timer routines | |
275 | */ | |
1da177e4 | 276 | |
2c3dfe3f | 277 | __inline__ void |
e315cd28 | 278 | qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval) |
1da177e4 | 279 | { |
e315cd28 AC |
280 | init_timer(&vha->timer); |
281 | vha->timer.expires = jiffies + interval * HZ; | |
282 | vha->timer.data = (unsigned long)vha; | |
283 | vha->timer.function = (void (*)(unsigned long))func; | |
284 | add_timer(&vha->timer); | |
285 | vha->timer_active = 1; | |
1da177e4 LT |
286 | } |
287 | ||
288 | static inline void | |
e315cd28 | 289 | qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) |
1da177e4 | 290 | { |
a9083016 | 291 | /* Currently used for 82XX only. */ |
7c3df132 SK |
292 | if (vha->device_flags & DFLG_DEV_FAILED) { |
293 | ql_dbg(ql_dbg_timer, vha, 0x600d, | |
294 | "Device in a failed state, returning.\n"); | |
a9083016 | 295 | return; |
7c3df132 | 296 | } |
a9083016 | 297 | |
e315cd28 | 298 | mod_timer(&vha->timer, jiffies + interval * HZ); |
1da177e4 LT |
299 | } |
300 | ||
a824ebb3 | 301 | static __inline__ void |
e315cd28 | 302 | qla2x00_stop_timer(scsi_qla_host_t *vha) |
1da177e4 | 303 | { |
e315cd28 AC |
304 | del_timer_sync(&vha->timer); |
305 | vha->timer_active = 0; | |
1da177e4 LT |
306 | } |
307 | ||
1da177e4 LT |
308 | static int qla2x00_do_dpc(void *data); |
309 | ||
310 | static void qla2x00_rst_aen(scsi_qla_host_t *); | |
311 | ||
73208dfd AC |
312 | static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, |
313 | struct req_que **, struct rsp_que **); | |
e30d1756 | 314 | static void qla2x00_free_fw_dump(struct qla_hw_data *); |
e315cd28 | 315 | static void qla2x00_mem_free(struct qla_hw_data *); |
1da177e4 | 316 | |
1da177e4 | 317 | /* -------------------------------------------------------------------------- */ |
9a347ff4 CD |
318 | static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, |
319 | struct rsp_que *rsp) | |
73208dfd | 320 | { |
7c3df132 | 321 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); |
2afa19a9 | 322 | ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues, |
73208dfd AC |
323 | GFP_KERNEL); |
324 | if (!ha->req_q_map) { | |
7c3df132 SK |
325 | ql_log(ql_log_fatal, vha, 0x003b, |
326 | "Unable to allocate memory for request queue ptrs.\n"); | |
73208dfd AC |
327 | goto fail_req_map; |
328 | } | |
329 | ||
2afa19a9 | 330 | ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues, |
73208dfd AC |
331 | GFP_KERNEL); |
332 | if (!ha->rsp_q_map) { | |
7c3df132 SK |
333 | ql_log(ql_log_fatal, vha, 0x003c, |
334 | "Unable to allocate memory for response queue ptrs.\n"); | |
73208dfd AC |
335 | goto fail_rsp_map; |
336 | } | |
9a347ff4 CD |
337 | /* |
338 | * Make sure we record at least the request and response queue zero in | |
339 | * case we need to free them if part of the probe fails. | |
340 | */ | |
341 | ha->rsp_q_map[0] = rsp; | |
342 | ha->req_q_map[0] = req; | |
73208dfd AC |
343 | set_bit(0, ha->rsp_qid_map); |
344 | set_bit(0, ha->req_qid_map); | |
345 | return 1; | |
346 | ||
347 | fail_rsp_map: | |
348 | kfree(ha->req_q_map); | |
349 | ha->req_q_map = NULL; | |
350 | fail_req_map: | |
351 | return -ENOMEM; | |
352 | } | |
353 | ||
2afa19a9 | 354 | static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) |
73208dfd | 355 | { |
73208dfd AC |
356 | if (req && req->ring) |
357 | dma_free_coherent(&ha->pdev->dev, | |
358 | (req->length + 1) * sizeof(request_t), | |
359 | req->ring, req->dma); | |
360 | ||
361 | kfree(req); | |
362 | req = NULL; | |
363 | } | |
364 | ||
2afa19a9 AC |
365 | static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) |
366 | { | |
367 | if (rsp && rsp->ring) | |
368 | dma_free_coherent(&ha->pdev->dev, | |
369 | (rsp->length + 1) * sizeof(response_t), | |
370 | rsp->ring, rsp->dma); | |
371 | ||
372 | kfree(rsp); | |
373 | rsp = NULL; | |
374 | } | |
375 | ||
73208dfd AC |
376 | static void qla2x00_free_queues(struct qla_hw_data *ha) |
377 | { | |
378 | struct req_que *req; | |
379 | struct rsp_que *rsp; | |
380 | int cnt; | |
381 | ||
2afa19a9 | 382 | for (cnt = 0; cnt < ha->max_req_queues; cnt++) { |
73208dfd | 383 | req = ha->req_q_map[cnt]; |
2afa19a9 | 384 | qla2x00_free_req_que(ha, req); |
73208dfd | 385 | } |
73208dfd AC |
386 | kfree(ha->req_q_map); |
387 | ha->req_q_map = NULL; | |
2afa19a9 AC |
388 | |
389 | for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { | |
390 | rsp = ha->rsp_q_map[cnt]; | |
391 | qla2x00_free_rsp_que(ha, rsp); | |
392 | } | |
393 | kfree(ha->rsp_q_map); | |
394 | ha->rsp_q_map = NULL; | |
73208dfd AC |
395 | } |
396 | ||
68ca949c AC |
397 | static int qla25xx_setup_mode(struct scsi_qla_host *vha) |
398 | { | |
399 | uint16_t options = 0; | |
400 | int ques, req, ret; | |
401 | struct qla_hw_data *ha = vha->hw; | |
402 | ||
7163ea81 | 403 | if (!(ha->fw_attributes & BIT_6)) { |
7c3df132 SK |
404 | ql_log(ql_log_warn, vha, 0x00d8, |
405 | "Firmware is not multi-queue capable.\n"); | |
7163ea81 AC |
406 | goto fail; |
407 | } | |
68ca949c | 408 | if (ql2xmultique_tag) { |
68ca949c AC |
409 | /* create a request queue for IO */ |
410 | options |= BIT_7; | |
411 | req = qla25xx_create_req_que(ha, options, 0, 0, -1, | |
412 | QLA_DEFAULT_QUE_QOS); | |
413 | if (!req) { | |
7c3df132 SK |
414 | ql_log(ql_log_warn, vha, 0x00e0, |
415 | "Failed to create request queue.\n"); | |
68ca949c AC |
416 | goto fail; |
417 | } | |
278274d5 | 418 | ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1); |
68ca949c AC |
419 | vha->req = ha->req_q_map[req]; |
420 | options |= BIT_1; | |
421 | for (ques = 1; ques < ha->max_rsp_queues; ques++) { | |
422 | ret = qla25xx_create_rsp_que(ha, options, 0, 0, req); | |
423 | if (!ret) { | |
7c3df132 SK |
424 | ql_log(ql_log_warn, vha, 0x00e8, |
425 | "Failed to create response queue.\n"); | |
68ca949c AC |
426 | goto fail2; |
427 | } | |
428 | } | |
7163ea81 | 429 | ha->flags.cpu_affinity_enabled = 1; |
7c3df132 SK |
430 | ql_dbg(ql_dbg_multiq, vha, 0xc007, |
431 | "CPU affinity mode enalbed, " | |
432 | "no. of response queues:%d no. of request queues:%d.\n", | |
433 | ha->max_rsp_queues, ha->max_req_queues); | |
434 | ql_dbg(ql_dbg_init, vha, 0x00e9, | |
435 | "CPU affinity mode enalbed, " | |
436 | "no. of response queues:%d no. of request queues:%d.\n", | |
437 | ha->max_rsp_queues, ha->max_req_queues); | |
68ca949c AC |
438 | } |
439 | return 0; | |
440 | fail2: | |
441 | qla25xx_delete_queues(vha); | |
7163ea81 AC |
442 | destroy_workqueue(ha->wq); |
443 | ha->wq = NULL; | |
0cd33fcf | 444 | vha->req = ha->req_q_map[0]; |
68ca949c AC |
445 | fail: |
446 | ha->mqenable = 0; | |
7163ea81 AC |
447 | kfree(ha->req_q_map); |
448 | kfree(ha->rsp_q_map); | |
449 | ha->max_req_queues = ha->max_rsp_queues = 1; | |
68ca949c AC |
450 | return 1; |
451 | } | |
452 | ||
1da177e4 | 453 | static char * |
e315cd28 | 454 | qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str) |
1da177e4 | 455 | { |
e315cd28 | 456 | struct qla_hw_data *ha = vha->hw; |
1da177e4 LT |
457 | static char *pci_bus_modes[] = { |
458 | "33", "66", "100", "133", | |
459 | }; | |
460 | uint16_t pci_bus; | |
461 | ||
462 | strcpy(str, "PCI"); | |
463 | pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; | |
464 | if (pci_bus) { | |
465 | strcat(str, "-X ("); | |
466 | strcat(str, pci_bus_modes[pci_bus]); | |
467 | } else { | |
468 | pci_bus = (ha->pci_attr & BIT_8) >> 8; | |
469 | strcat(str, " ("); | |
470 | strcat(str, pci_bus_modes[pci_bus]); | |
471 | } | |
472 | strcat(str, " MHz)"); | |
473 | ||
474 | return (str); | |
475 | } | |
476 | ||
fca29703 | 477 | static char * |
e315cd28 | 478 | qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str) |
fca29703 AV |
479 | { |
480 | static char *pci_bus_modes[] = { "33", "66", "100", "133", }; | |
e315cd28 | 481 | struct qla_hw_data *ha = vha->hw; |
fca29703 AV |
482 | uint32_t pci_bus; |
483 | int pcie_reg; | |
484 | ||
e67f1321 | 485 | pcie_reg = pci_pcie_cap(ha->pdev); |
fca29703 AV |
486 | if (pcie_reg) { |
487 | char lwstr[6]; | |
488 | uint16_t pcie_lstat, lspeed, lwidth; | |
489 | ||
e67f1321 | 490 | pcie_reg += PCI_EXP_LNKCAP; |
fca29703 AV |
491 | pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat); |
492 | lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3); | |
493 | lwidth = (pcie_lstat & | |
494 | (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4; | |
495 | ||
496 | strcpy(str, "PCIe ("); | |
497 | if (lspeed == 1) | |
c87a0d8c | 498 | strcat(str, "2.5GT/s "); |
c3a2f0df | 499 | else if (lspeed == 2) |
c87a0d8c | 500 | strcat(str, "5.0GT/s "); |
fca29703 AV |
501 | else |
502 | strcat(str, "<unknown> "); | |
503 | snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth); | |
504 | strcat(str, lwstr); | |
505 | ||
506 | return str; | |
507 | } | |
508 | ||
509 | strcpy(str, "PCI"); | |
510 | pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; | |
511 | if (pci_bus == 0 || pci_bus == 8) { | |
512 | strcat(str, " ("); | |
513 | strcat(str, pci_bus_modes[pci_bus >> 3]); | |
514 | } else { | |
515 | strcat(str, "-X "); | |
516 | if (pci_bus & BIT_2) | |
517 | strcat(str, "Mode 2"); | |
518 | else | |
519 | strcat(str, "Mode 1"); | |
520 | strcat(str, " ("); | |
521 | strcat(str, pci_bus_modes[pci_bus & ~BIT_2]); | |
522 | } | |
523 | strcat(str, " MHz)"); | |
524 | ||
525 | return str; | |
526 | } | |
527 | ||
e5f82ab8 | 528 | static char * |
e315cd28 | 529 | qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str) |
1da177e4 LT |
530 | { |
531 | char un_str[10]; | |
e315cd28 | 532 | struct qla_hw_data *ha = vha->hw; |
fa2a1ce5 | 533 | |
1da177e4 LT |
534 | sprintf(str, "%d.%02d.%02d ", ha->fw_major_version, |
535 | ha->fw_minor_version, | |
536 | ha->fw_subminor_version); | |
537 | ||
538 | if (ha->fw_attributes & BIT_9) { | |
539 | strcat(str, "FLX"); | |
540 | return (str); | |
541 | } | |
542 | ||
543 | switch (ha->fw_attributes & 0xFF) { | |
544 | case 0x7: | |
545 | strcat(str, "EF"); | |
546 | break; | |
547 | case 0x17: | |
548 | strcat(str, "TP"); | |
549 | break; | |
550 | case 0x37: | |
551 | strcat(str, "IP"); | |
552 | break; | |
553 | case 0x77: | |
554 | strcat(str, "VI"); | |
555 | break; | |
556 | default: | |
557 | sprintf(un_str, "(%x)", ha->fw_attributes); | |
558 | strcat(str, un_str); | |
559 | break; | |
560 | } | |
561 | if (ha->fw_attributes & 0x100) | |
562 | strcat(str, "X"); | |
563 | ||
564 | return (str); | |
565 | } | |
566 | ||
e5f82ab8 | 567 | static char * |
e315cd28 | 568 | qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str) |
fca29703 | 569 | { |
e315cd28 | 570 | struct qla_hw_data *ha = vha->hw; |
f0883ac6 | 571 | |
3a03eb79 AV |
572 | sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version, |
573 | ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); | |
fca29703 | 574 | return str; |
fca29703 AV |
575 | } |
576 | ||
9ba56b95 GM |
577 | void |
578 | qla2x00_sp_free_dma(void *vha, void *ptr) | |
fca29703 | 579 | { |
9ba56b95 GM |
580 | srb_t *sp = (srb_t *)ptr; |
581 | struct scsi_cmnd *cmd = GET_CMD_SP(sp); | |
582 | struct qla_hw_data *ha = sp->fcport->vha->hw; | |
583 | void *ctx = GET_CMD_CTX_SP(sp); | |
fca29703 | 584 | |
9ba56b95 GM |
585 | if (sp->flags & SRB_DMA_VALID) { |
586 | scsi_dma_unmap(cmd); | |
587 | sp->flags &= ~SRB_DMA_VALID; | |
7c3df132 | 588 | } |
fca29703 | 589 | |
9ba56b95 GM |
590 | if (sp->flags & SRB_CRC_PROT_DMA_VALID) { |
591 | dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), | |
592 | scsi_prot_sg_count(cmd), cmd->sc_data_direction); | |
593 | sp->flags &= ~SRB_CRC_PROT_DMA_VALID; | |
594 | } | |
595 | ||
596 | if (sp->flags & SRB_CRC_CTX_DSD_VALID) { | |
597 | /* List assured to be having elements */ | |
598 | qla2x00_clean_dsd_pool(ha, sp); | |
599 | sp->flags &= ~SRB_CRC_CTX_DSD_VALID; | |
600 | } | |
601 | ||
602 | if (sp->flags & SRB_CRC_CTX_DMA_VALID) { | |
603 | dma_pool_free(ha->dl_dma_pool, ctx, | |
604 | ((struct crc_context *)ctx)->crc_ctx_dma); | |
605 | sp->flags &= ~SRB_CRC_CTX_DMA_VALID; | |
606 | } | |
607 | ||
608 | if (sp->flags & SRB_FCP_CMND_DMA_VALID) { | |
609 | struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx; | |
fca29703 | 610 | |
9ba56b95 GM |
611 | dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, |
612 | ctx1->fcp_cmnd_dma); | |
613 | list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); | |
614 | ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; | |
615 | ha->gbl_dsd_avail += ctx1->dsd_use_cnt; | |
616 | mempool_free(ctx1, ha->ctx_mempool); | |
617 | ctx1 = NULL; | |
618 | } | |
619 | ||
620 | CMD_SP(cmd) = NULL; | |
621 | mempool_free(sp, ha->srb_mempool); | |
622 | } | |
623 | ||
624 | static void | |
625 | qla2x00_sp_compl(void *data, void *ptr, int res) | |
626 | { | |
627 | struct qla_hw_data *ha = (struct qla_hw_data *)data; | |
628 | srb_t *sp = (srb_t *)ptr; | |
629 | struct scsi_cmnd *cmd = GET_CMD_SP(sp); | |
630 | ||
631 | cmd->result = res; | |
632 | ||
633 | if (atomic_read(&sp->ref_count) == 0) { | |
634 | ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015, | |
635 | "SP reference-count to ZERO -- sp=%p cmd=%p.\n", | |
636 | sp, GET_CMD_SP(sp)); | |
637 | if (ql2xextended_error_logging & ql_dbg_io) | |
638 | BUG(); | |
639 | return; | |
640 | } | |
641 | if (!atomic_dec_and_test(&sp->ref_count)) | |
642 | return; | |
643 | ||
644 | qla2x00_sp_free_dma(ha, sp); | |
645 | cmd->scsi_done(cmd); | |
fca29703 AV |
646 | } |
647 | ||
1da177e4 | 648 | static int |
f5e3e40b | 649 | qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) |
fca29703 | 650 | { |
134ae078 | 651 | scsi_qla_host_t *vha = shost_priv(host); |
fca29703 | 652 | fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; |
19a7b4ae | 653 | struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); |
e315cd28 AC |
654 | struct qla_hw_data *ha = vha->hw; |
655 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); | |
fca29703 AV |
656 | srb_t *sp; |
657 | int rval; | |
658 | ||
85880801 | 659 | if (ha->flags.eeh_busy) { |
7c3df132 | 660 | if (ha->flags.pci_channel_io_perm_failure) { |
5f28d2d7 | 661 | ql_dbg(ql_dbg_aer, vha, 0x9010, |
7c3df132 SK |
662 | "PCI Channel IO permanent failure, exiting " |
663 | "cmd=%p.\n", cmd); | |
b9b12f73 | 664 | cmd->result = DID_NO_CONNECT << 16; |
7c3df132 | 665 | } else { |
5f28d2d7 | 666 | ql_dbg(ql_dbg_aer, vha, 0x9011, |
7c3df132 | 667 | "EEH_Busy, Requeuing the cmd=%p.\n", cmd); |
85880801 | 668 | cmd->result = DID_REQUEUE << 16; |
7c3df132 | 669 | } |
14e660e6 SJ |
670 | goto qc24_fail_command; |
671 | } | |
672 | ||
19a7b4ae JSEC |
673 | rval = fc_remote_port_chkready(rport); |
674 | if (rval) { | |
675 | cmd->result = rval; | |
5f28d2d7 | 676 | ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, |
7c3df132 SK |
677 | "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", |
678 | cmd, rval); | |
fca29703 AV |
679 | goto qc24_fail_command; |
680 | } | |
681 | ||
bad75002 AE |
682 | if (!vha->flags.difdix_supported && |
683 | scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { | |
7c3df132 SK |
684 | ql_dbg(ql_dbg_io, vha, 0x3004, |
685 | "DIF Cap not reg, fail DIF capable cmd's:%p.\n", | |
686 | cmd); | |
bad75002 AE |
687 | cmd->result = DID_NO_CONNECT << 16; |
688 | goto qc24_fail_command; | |
689 | } | |
aa651be8 CD |
690 | |
691 | if (!fcport) { | |
692 | cmd->result = DID_NO_CONNECT << 16; | |
693 | goto qc24_fail_command; | |
694 | } | |
695 | ||
fca29703 AV |
696 | if (atomic_read(&fcport->state) != FCS_ONLINE) { |
697 | if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || | |
38170fa8 | 698 | atomic_read(&base_vha->loop_state) == LOOP_DEAD) { |
7c3df132 SK |
699 | ql_dbg(ql_dbg_io, vha, 0x3005, |
700 | "Returning DNC, fcport_state=%d loop_state=%d.\n", | |
701 | atomic_read(&fcport->state), | |
702 | atomic_read(&base_vha->loop_state)); | |
fca29703 AV |
703 | cmd->result = DID_NO_CONNECT << 16; |
704 | goto qc24_fail_command; | |
705 | } | |
7b594131 | 706 | goto qc24_target_busy; |
fca29703 AV |
707 | } |
708 | ||
9ba56b95 | 709 | sp = qla2x00_get_sp(base_vha, fcport, GFP_ATOMIC); |
fca29703 | 710 | if (!sp) |
f5e3e40b | 711 | goto qc24_host_busy; |
fca29703 | 712 | |
9ba56b95 GM |
713 | sp->u.scmd.cmd = cmd; |
714 | sp->type = SRB_SCSI_CMD; | |
715 | atomic_set(&sp->ref_count, 1); | |
716 | CMD_SP(cmd) = (void *)sp; | |
717 | sp->free = qla2x00_sp_free_dma; | |
718 | sp->done = qla2x00_sp_compl; | |
719 | ||
e315cd28 | 720 | rval = ha->isp_ops->start_scsi(sp); |
7c3df132 SK |
721 | if (rval != QLA_SUCCESS) { |
722 | ql_dbg(ql_dbg_io, vha, 0x3013, | |
723 | "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); | |
fca29703 | 724 | goto qc24_host_busy_free_sp; |
7c3df132 | 725 | } |
fca29703 | 726 | |
fca29703 AV |
727 | return 0; |
728 | ||
729 | qc24_host_busy_free_sp: | |
9ba56b95 | 730 | qla2x00_sp_free_dma(ha, sp); |
fca29703 | 731 | |
f5e3e40b | 732 | qc24_host_busy: |
fca29703 AV |
733 | return SCSI_MLQUEUE_HOST_BUSY; |
734 | ||
7b594131 MC |
735 | qc24_target_busy: |
736 | return SCSI_MLQUEUE_TARGET_BUSY; | |
737 | ||
fca29703 | 738 | qc24_fail_command: |
f5e3e40b | 739 | cmd->scsi_done(cmd); |
fca29703 AV |
740 | |
741 | return 0; | |
742 | } | |
743 | ||
1da177e4 LT |
744 | /* |
745 | * qla2x00_eh_wait_on_command | |
746 | * Waits for the command to be returned by the Firmware for some | |
747 | * max time. | |
748 | * | |
749 | * Input: | |
1da177e4 | 750 | * cmd = Scsi Command to wait on. |
1da177e4 LT |
751 | * |
752 | * Return: | |
753 | * Not Found : 0 | |
754 | * Found : 1 | |
755 | */ | |
756 | static int | |
e315cd28 | 757 | qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) |
1da177e4 | 758 | { |
fe74c71f AV |
759 | #define ABORT_POLLING_PERIOD 1000 |
760 | #define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD)) | |
f4f051eb | 761 | unsigned long wait_iter = ABORT_WAIT_ITER; |
85880801 AV |
762 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
763 | struct qla_hw_data *ha = vha->hw; | |
f4f051eb | 764 | int ret = QLA_SUCCESS; |
1da177e4 | 765 | |
85880801 | 766 | if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { |
7c3df132 SK |
767 | ql_dbg(ql_dbg_taskm, vha, 0x8005, |
768 | "Return:eh_wait.\n"); | |
85880801 AV |
769 | return ret; |
770 | } | |
771 | ||
d970432c | 772 | while (CMD_SP(cmd) && wait_iter--) { |
fe74c71f | 773 | msleep(ABORT_POLLING_PERIOD); |
f4f051eb | 774 | } |
775 | if (CMD_SP(cmd)) | |
776 | ret = QLA_FUNCTION_FAILED; | |
1da177e4 | 777 | |
f4f051eb | 778 | return ret; |
1da177e4 LT |
779 | } |
780 | ||
781 | /* | |
782 | * qla2x00_wait_for_hba_online | |
fa2a1ce5 | 783 | * Wait till the HBA is online after going through |
1da177e4 LT |
784 | * <= MAX_RETRIES_OF_ISP_ABORT or |
785 | * finally HBA is disabled ie marked offline | |
786 | * | |
787 | * Input: | |
788 | * ha - pointer to host adapter structure | |
fa2a1ce5 AV |
789 | * |
790 | * Note: | |
1da177e4 LT |
791 | * Does context switching-Release SPIN_LOCK |
792 | * (if any) before calling this routine. | |
793 | * | |
794 | * Return: | |
795 | * Success (Adapter is online) : 0 | |
796 | * Failed (Adapter is offline/disabled) : 1 | |
797 | */ | |
854165f4 | 798 | int |
e315cd28 | 799 | qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) |
1da177e4 | 800 | { |
fca29703 AV |
801 | int return_status; |
802 | unsigned long wait_online; | |
e315cd28 AC |
803 | struct qla_hw_data *ha = vha->hw; |
804 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); | |
1da177e4 | 805 | |
fa2a1ce5 | 806 | wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); |
e315cd28 AC |
807 | while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || |
808 | test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || | |
809 | test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || | |
810 | ha->dpc_active) && time_before(jiffies, wait_online)) { | |
1da177e4 LT |
811 | |
812 | msleep(1000); | |
813 | } | |
e315cd28 | 814 | if (base_vha->flags.online) |
fa2a1ce5 | 815 | return_status = QLA_SUCCESS; |
1da177e4 LT |
816 | else |
817 | return_status = QLA_FUNCTION_FAILED; | |
818 | ||
1da177e4 LT |
819 | return (return_status); |
820 | } | |
821 | ||
86fbee86 LC |
822 | /* |
823 | * qla2x00_wait_for_reset_ready | |
824 | * Wait till the HBA is online after going through | |
825 | * <= MAX_RETRIES_OF_ISP_ABORT or | |
826 | * finally HBA is disabled ie marked offline or flash | |
827 | * operations are in progress. | |
828 | * | |
829 | * Input: | |
830 | * ha - pointer to host adapter structure | |
831 | * | |
832 | * Note: | |
833 | * Does context switching-Release SPIN_LOCK | |
834 | * (if any) before calling this routine. | |
835 | * | |
836 | * Return: | |
837 | * Success (Adapter is online/no flash ops) : 0 | |
838 | * Failed (Adapter is offline/disabled/flash ops in progress) : 1 | |
839 | */ | |
3dbe756a | 840 | static int |
86fbee86 LC |
841 | qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha) |
842 | { | |
843 | int return_status; | |
844 | unsigned long wait_online; | |
845 | struct qla_hw_data *ha = vha->hw; | |
846 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); | |
847 | ||
848 | wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); | |
849 | while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || | |
850 | test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || | |
851 | test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || | |
852 | ha->optrom_state != QLA_SWAITING || | |
853 | ha->dpc_active) && time_before(jiffies, wait_online)) | |
854 | msleep(1000); | |
855 | ||
856 | if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING) | |
857 | return_status = QLA_SUCCESS; | |
858 | else | |
859 | return_status = QLA_FUNCTION_FAILED; | |
860 | ||
7c3df132 SK |
861 | ql_dbg(ql_dbg_taskm, vha, 0x8019, |
862 | "%s return status=%d.\n", __func__, return_status); | |
86fbee86 LC |
863 | |
864 | return return_status; | |
865 | } | |
866 | ||
2533cf67 LC |
867 | int |
868 | qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) | |
869 | { | |
870 | int return_status; | |
871 | unsigned long wait_reset; | |
872 | struct qla_hw_data *ha = vha->hw; | |
873 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); | |
874 | ||
875 | wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); | |
876 | while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || | |
877 | test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || | |
878 | test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || | |
879 | ha->dpc_active) && time_before(jiffies, wait_reset)) { | |
880 | ||
881 | msleep(1000); | |
882 | ||
883 | if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && | |
884 | ha->flags.chip_reset_done) | |
885 | break; | |
886 | } | |
887 | if (ha->flags.chip_reset_done) | |
888 | return_status = QLA_SUCCESS; | |
889 | else | |
890 | return_status = QLA_FUNCTION_FAILED; | |
891 | ||
892 | return return_status; | |
893 | } | |
894 | ||
083a469d GM |
895 | static void |
896 | sp_get(struct srb *sp) | |
897 | { | |
898 | atomic_inc(&sp->ref_count); | |
899 | } | |
900 | ||
1da177e4 LT |
901 | /************************************************************************** |
902 | * qla2xxx_eh_abort | |
903 | * | |
904 | * Description: | |
905 | * The abort function will abort the specified command. | |
906 | * | |
907 | * Input: | |
908 | * cmd = Linux SCSI command packet to be aborted. | |
909 | * | |
910 | * Returns: | |
911 | * Either SUCCESS or FAILED. | |
912 | * | |
913 | * Note: | |
2ea00202 | 914 | * Only return FAILED if command not returned by firmware. |
1da177e4 | 915 | **************************************************************************/ |
e5f82ab8 | 916 | static int |
1da177e4 LT |
917 | qla2xxx_eh_abort(struct scsi_cmnd *cmd) |
918 | { | |
e315cd28 | 919 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
f4f051eb | 920 | srb_t *sp; |
4e98d3b8 | 921 | int ret; |
f4f051eb | 922 | unsigned int id, lun; |
18e144d3 | 923 | unsigned long flags; |
2ea00202 | 924 | int wait = 0; |
e315cd28 | 925 | struct qla_hw_data *ha = vha->hw; |
1da177e4 | 926 | |
f4f051eb | 927 | if (!CMD_SP(cmd)) |
2ea00202 | 928 | return SUCCESS; |
1da177e4 | 929 | |
4e98d3b8 AV |
930 | ret = fc_block_scsi_eh(cmd); |
931 | if (ret != 0) | |
932 | return ret; | |
933 | ret = SUCCESS; | |
934 | ||
f4f051eb | 935 | id = cmd->device->id; |
936 | lun = cmd->device->lun; | |
1da177e4 | 937 | |
e315cd28 | 938 | spin_lock_irqsave(&ha->hardware_lock, flags); |
170babc3 MC |
939 | sp = (srb_t *) CMD_SP(cmd); |
940 | if (!sp) { | |
941 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
942 | return SUCCESS; | |
943 | } | |
1da177e4 | 944 | |
7c3df132 | 945 | ql_dbg(ql_dbg_taskm, vha, 0x8002, |
cfb0919c CD |
946 | "Aborting from RISC nexus=%ld:%d:%d sp=%p cmd=%p\n", |
947 | vha->host_no, id, lun, sp, cmd); | |
17d98630 | 948 | |
170babc3 MC |
949 | /* Get a reference to the sp and drop the lock.*/ |
950 | sp_get(sp); | |
083a469d | 951 | |
e315cd28 | 952 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
170babc3 | 953 | if (ha->isp_ops->abort_command(sp)) { |
a55aac79 | 954 | ret = FAILED; |
7c3df132 | 955 | ql_dbg(ql_dbg_taskm, vha, 0x8003, |
cfb0919c | 956 | "Abort command mbx failed cmd=%p.\n", cmd); |
170babc3 | 957 | } else { |
7c3df132 | 958 | ql_dbg(ql_dbg_taskm, vha, 0x8004, |
cfb0919c | 959 | "Abort command mbx success cmd=%p.\n", cmd); |
170babc3 MC |
960 | wait = 1; |
961 | } | |
75942064 SK |
962 | |
963 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
9ba56b95 | 964 | sp->done(ha, sp, 0); |
75942064 | 965 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
1da177e4 | 966 | |
bc91ade9 CD |
967 | /* Did the command return during mailbox execution? */ |
968 | if (ret == FAILED && !CMD_SP(cmd)) | |
969 | ret = SUCCESS; | |
970 | ||
f4f051eb | 971 | /* Wait for the command to be returned. */ |
2ea00202 | 972 | if (wait) { |
e315cd28 | 973 | if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) { |
7c3df132 | 974 | ql_log(ql_log_warn, vha, 0x8006, |
cfb0919c | 975 | "Abort handler timed out cmd=%p.\n", cmd); |
2ea00202 | 976 | ret = FAILED; |
f4f051eb | 977 | } |
1da177e4 | 978 | } |
1da177e4 | 979 | |
7c3df132 | 980 | ql_log(ql_log_info, vha, 0x801c, |
cfb0919c CD |
981 | "Abort command issued nexus=%ld:%d:%d -- %d %x.\n", |
982 | vha->host_no, id, lun, wait, ret); | |
1da177e4 | 983 | |
f4f051eb | 984 | return ret; |
985 | } | |
1da177e4 | 986 | |
4d78c973 | 987 | int |
e315cd28 | 988 | qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, |
4d78c973 | 989 | unsigned int l, enum nexus_wait_type type) |
f4f051eb | 990 | { |
17d98630 | 991 | int cnt, match, status; |
18e144d3 | 992 | unsigned long flags; |
e315cd28 | 993 | struct qla_hw_data *ha = vha->hw; |
73208dfd | 994 | struct req_que *req; |
4d78c973 | 995 | srb_t *sp; |
9ba56b95 | 996 | struct scsi_cmnd *cmd; |
1da177e4 | 997 | |
523ec773 | 998 | status = QLA_SUCCESS; |
17d98630 | 999 | |
e315cd28 | 1000 | spin_lock_irqsave(&ha->hardware_lock, flags); |
67c2e93a | 1001 | req = vha->req; |
17d98630 AC |
1002 | for (cnt = 1; status == QLA_SUCCESS && |
1003 | cnt < MAX_OUTSTANDING_COMMANDS; cnt++) { | |
1004 | sp = req->outstanding_cmds[cnt]; | |
1005 | if (!sp) | |
523ec773 | 1006 | continue; |
9ba56b95 | 1007 | if (sp->type != SRB_SCSI_CMD) |
cf53b069 | 1008 | continue; |
17d98630 AC |
1009 | if (vha->vp_idx != sp->fcport->vha->vp_idx) |
1010 | continue; | |
1011 | match = 0; | |
9ba56b95 | 1012 | cmd = GET_CMD_SP(sp); |
17d98630 AC |
1013 | switch (type) { |
1014 | case WAIT_HOST: | |
1015 | match = 1; | |
1016 | break; | |
1017 | case WAIT_TARGET: | |
9ba56b95 | 1018 | match = cmd->device->id == t; |
17d98630 AC |
1019 | break; |
1020 | case WAIT_LUN: | |
9ba56b95 GM |
1021 | match = (cmd->device->id == t && |
1022 | cmd->device->lun == l); | |
17d98630 | 1023 | break; |
73208dfd | 1024 | } |
17d98630 AC |
1025 | if (!match) |
1026 | continue; | |
1027 | ||
1028 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
9ba56b95 | 1029 | status = qla2x00_eh_wait_on_command(cmd); |
17d98630 | 1030 | spin_lock_irqsave(&ha->hardware_lock, flags); |
1da177e4 | 1031 | } |
e315cd28 | 1032 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
523ec773 AV |
1033 | |
1034 | return status; | |
1da177e4 LT |
1035 | } |
1036 | ||
523ec773 AV |
1037 | static char *reset_errors[] = { |
1038 | "HBA not online", | |
1039 | "HBA not ready", | |
1040 | "Task management failed", | |
1041 | "Waiting for command completions", | |
1042 | }; | |
1da177e4 | 1043 | |
e5f82ab8 | 1044 | static int |
523ec773 | 1045 | __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, |
2afa19a9 | 1046 | struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int)) |
1da177e4 | 1047 | { |
e315cd28 | 1048 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
bdf79621 | 1049 | fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; |
523ec773 | 1050 | int err; |
1da177e4 | 1051 | |
7c3df132 | 1052 | if (!fcport) { |
523ec773 | 1053 | return FAILED; |
7c3df132 | 1054 | } |
1da177e4 | 1055 | |
4e98d3b8 AV |
1056 | err = fc_block_scsi_eh(cmd); |
1057 | if (err != 0) | |
1058 | return err; | |
1059 | ||
7c3df132 | 1060 | ql_log(ql_log_info, vha, 0x8009, |
cfb0919c | 1061 | "%s RESET ISSUED nexus=%ld:%d:%d cmd=%p.\n", name, vha->host_no, |
7c3df132 | 1062 | cmd->device->id, cmd->device->lun, cmd); |
1da177e4 | 1063 | |
523ec773 | 1064 | err = 0; |
7c3df132 SK |
1065 | if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { |
1066 | ql_log(ql_log_warn, vha, 0x800a, | |
1067 | "Wait for hba online failed for cmd=%p.\n", cmd); | |
523ec773 | 1068 | goto eh_reset_failed; |
7c3df132 | 1069 | } |
523ec773 | 1070 | err = 2; |
2afa19a9 | 1071 | if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1) |
7c3df132 SK |
1072 | != QLA_SUCCESS) { |
1073 | ql_log(ql_log_warn, vha, 0x800c, | |
1074 | "do_reset failed for cmd=%p.\n", cmd); | |
523ec773 | 1075 | goto eh_reset_failed; |
7c3df132 | 1076 | } |
523ec773 | 1077 | err = 3; |
e315cd28 | 1078 | if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, |
7c3df132 SK |
1079 | cmd->device->lun, type) != QLA_SUCCESS) { |
1080 | ql_log(ql_log_warn, vha, 0x800d, | |
1081 | "wait for peding cmds failed for cmd=%p.\n", cmd); | |
523ec773 | 1082 | goto eh_reset_failed; |
7c3df132 | 1083 | } |
523ec773 | 1084 | |
7c3df132 | 1085 | ql_log(ql_log_info, vha, 0x800e, |
cfb0919c CD |
1086 | "%s RESET SUCCEEDED nexus:%ld:%d:%d cmd=%p.\n", name, |
1087 | vha->host_no, cmd->device->id, cmd->device->lun, cmd); | |
523ec773 AV |
1088 | |
1089 | return SUCCESS; | |
1090 | ||
4d78c973 | 1091 | eh_reset_failed: |
7c3df132 | 1092 | ql_log(ql_log_info, vha, 0x800f, |
cfb0919c CD |
1093 | "%s RESET FAILED: %s nexus=%ld:%d:%d cmd=%p.\n", name, |
1094 | reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, | |
1095 | cmd); | |
523ec773 AV |
1096 | return FAILED; |
1097 | } | |
1da177e4 | 1098 | |
523ec773 AV |
1099 | static int |
1100 | qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) | |
1101 | { | |
e315cd28 AC |
1102 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
1103 | struct qla_hw_data *ha = vha->hw; | |
1da177e4 | 1104 | |
523ec773 AV |
1105 | return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, |
1106 | ha->isp_ops->lun_reset); | |
1da177e4 LT |
1107 | } |
1108 | ||
1da177e4 | 1109 | static int |
523ec773 | 1110 | qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) |
1da177e4 | 1111 | { |
e315cd28 AC |
1112 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
1113 | struct qla_hw_data *ha = vha->hw; | |
1da177e4 | 1114 | |
523ec773 AV |
1115 | return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, |
1116 | ha->isp_ops->target_reset); | |
1da177e4 LT |
1117 | } |
1118 | ||
1da177e4 LT |
1119 | /************************************************************************** |
1120 | * qla2xxx_eh_bus_reset | |
1121 | * | |
1122 | * Description: | |
1123 | * The bus reset function will reset the bus and abort any executing | |
1124 | * commands. | |
1125 | * | |
1126 | * Input: | |
1127 | * cmd = Linux SCSI command packet of the command that cause the | |
1128 | * bus reset. | |
1129 | * | |
1130 | * Returns: | |
1131 | * SUCCESS/FAILURE (defined as macro in scsi.h). | |
1132 | * | |
1133 | **************************************************************************/ | |
e5f82ab8 | 1134 | static int |
1da177e4 LT |
1135 | qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) |
1136 | { | |
e315cd28 | 1137 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
bdf79621 | 1138 | fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; |
2c3dfe3f | 1139 | int ret = FAILED; |
f4f051eb | 1140 | unsigned int id, lun; |
f4f051eb | 1141 | |
f4f051eb | 1142 | id = cmd->device->id; |
1143 | lun = cmd->device->lun; | |
1da177e4 | 1144 | |
7c3df132 | 1145 | if (!fcport) { |
f4f051eb | 1146 | return ret; |
7c3df132 | 1147 | } |
1da177e4 | 1148 | |
4e98d3b8 AV |
1149 | ret = fc_block_scsi_eh(cmd); |
1150 | if (ret != 0) | |
1151 | return ret; | |
1152 | ret = FAILED; | |
1153 | ||
7c3df132 | 1154 | ql_log(ql_log_info, vha, 0x8012, |
46270afe | 1155 | "BUS RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun); |
1da177e4 | 1156 | |
e315cd28 | 1157 | if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { |
7c3df132 SK |
1158 | ql_log(ql_log_fatal, vha, 0x8013, |
1159 | "Wait for hba online failed board disabled.\n"); | |
f4f051eb | 1160 | goto eh_bus_reset_done; |
1da177e4 LT |
1161 | } |
1162 | ||
ad537689 SK |
1163 | if (qla2x00_loop_reset(vha) == QLA_SUCCESS) |
1164 | ret = SUCCESS; | |
1165 | ||
f4f051eb | 1166 | if (ret == FAILED) |
1167 | goto eh_bus_reset_done; | |
1da177e4 | 1168 | |
9a41a62b | 1169 | /* Flush outstanding commands. */ |
4d78c973 | 1170 | if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != |
7c3df132 SK |
1171 | QLA_SUCCESS) { |
1172 | ql_log(ql_log_warn, vha, 0x8014, | |
1173 | "Wait for pending commands failed.\n"); | |
9a41a62b | 1174 | ret = FAILED; |
7c3df132 | 1175 | } |
1da177e4 | 1176 | |
f4f051eb | 1177 | eh_bus_reset_done: |
7c3df132 | 1178 | ql_log(ql_log_warn, vha, 0x802b, |
cfb0919c CD |
1179 | "BUS RESET %s nexus=%ld:%d:%d.\n", |
1180 | (ret == FAILED) ? "FAILED" : "SUCCEDED", vha->host_no, id, lun); | |
1da177e4 | 1181 | |
f4f051eb | 1182 | return ret; |
1da177e4 LT |
1183 | } |
1184 | ||
1185 | /************************************************************************** | |
1186 | * qla2xxx_eh_host_reset | |
1187 | * | |
1188 | * Description: | |
1189 | * The reset function will reset the Adapter. | |
1190 | * | |
1191 | * Input: | |
1192 | * cmd = Linux SCSI command packet of the command that cause the | |
1193 | * adapter reset. | |
1194 | * | |
1195 | * Returns: | |
1196 | * Either SUCCESS or FAILED. | |
1197 | * | |
1198 | * Note: | |
1199 | **************************************************************************/ | |
e5f82ab8 | 1200 | static int |
1da177e4 LT |
1201 | qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) |
1202 | { | |
e315cd28 | 1203 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
e315cd28 | 1204 | struct qla_hw_data *ha = vha->hw; |
2c3dfe3f | 1205 | int ret = FAILED; |
f4f051eb | 1206 | unsigned int id, lun; |
e315cd28 | 1207 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); |
1da177e4 | 1208 | |
f4f051eb | 1209 | id = cmd->device->id; |
1210 | lun = cmd->device->lun; | |
f4f051eb | 1211 | |
7c3df132 | 1212 | ql_log(ql_log_info, vha, 0x8018, |
cfb0919c | 1213 | "ADAPTER RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun); |
1da177e4 | 1214 | |
86fbee86 | 1215 | if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS) |
f4f051eb | 1216 | goto eh_host_reset_lock; |
1da177e4 | 1217 | |
e315cd28 AC |
1218 | if (vha != base_vha) { |
1219 | if (qla2x00_vp_abort_isp(vha)) | |
f4f051eb | 1220 | goto eh_host_reset_lock; |
e315cd28 | 1221 | } else { |
a9083016 GM |
1222 | if (IS_QLA82XX(vha->hw)) { |
1223 | if (!qla82xx_fcoe_ctx_reset(vha)) { | |
1224 | /* Ctx reset success */ | |
1225 | ret = SUCCESS; | |
1226 | goto eh_host_reset_lock; | |
1227 | } | |
1228 | /* fall thru if ctx reset failed */ | |
1229 | } | |
68ca949c AC |
1230 | if (ha->wq) |
1231 | flush_workqueue(ha->wq); | |
1232 | ||
e315cd28 | 1233 | set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); |
a9083016 | 1234 | if (ha->isp_ops->abort_isp(base_vha)) { |
e315cd28 AC |
1235 | clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); |
1236 | /* failed. schedule dpc to try */ | |
1237 | set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); | |
1238 | ||
7c3df132 SK |
1239 | if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { |
1240 | ql_log(ql_log_warn, vha, 0x802a, | |
1241 | "wait for hba online failed.\n"); | |
e315cd28 | 1242 | goto eh_host_reset_lock; |
7c3df132 | 1243 | } |
e315cd28 AC |
1244 | } |
1245 | clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); | |
fa2a1ce5 | 1246 | } |
1da177e4 | 1247 | |
e315cd28 | 1248 | /* Waiting for command to be returned to OS.*/ |
4d78c973 | 1249 | if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == |
e315cd28 | 1250 | QLA_SUCCESS) |
f4f051eb | 1251 | ret = SUCCESS; |
1da177e4 | 1252 | |
f4f051eb | 1253 | eh_host_reset_lock: |
cfb0919c CD |
1254 | ql_log(ql_log_info, vha, 0x8017, |
1255 | "ADAPTER RESET %s nexus=%ld:%d:%d.\n", | |
1256 | (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); | |
1da177e4 | 1257 | |
f4f051eb | 1258 | return ret; |
1259 | } | |
1da177e4 LT |
1260 | |
1261 | /* | |
1262 | * qla2x00_loop_reset | |
1263 | * Issue loop reset. | |
1264 | * | |
1265 | * Input: | |
1266 | * ha = adapter block pointer. | |
1267 | * | |
1268 | * Returns: | |
1269 | * 0 = success | |
1270 | */ | |
a4722cf2 | 1271 | int |
e315cd28 | 1272 | qla2x00_loop_reset(scsi_qla_host_t *vha) |
1da177e4 | 1273 | { |
0c8c39af | 1274 | int ret; |
bdf79621 | 1275 | struct fc_port *fcport; |
e315cd28 | 1276 | struct qla_hw_data *ha = vha->hw; |
1da177e4 | 1277 | |
f4c496c1 | 1278 | if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { |
55e5ed27 AV |
1279 | list_for_each_entry(fcport, &vha->vp_fcports, list) { |
1280 | if (fcport->port_type != FCT_TARGET) | |
1281 | continue; | |
1282 | ||
1283 | ret = ha->isp_ops->target_reset(fcport, 0, 0); | |
1284 | if (ret != QLA_SUCCESS) { | |
7c3df132 SK |
1285 | ql_dbg(ql_dbg_taskm, vha, 0x802c, |
1286 | "Bus Reset failed: Target Reset=%d " | |
1287 | "d_id=%x.\n", ret, fcport->d_id.b24); | |
55e5ed27 AV |
1288 | } |
1289 | } | |
1290 | } | |
1291 | ||
6246b8a1 | 1292 | if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { |
e315cd28 | 1293 | ret = qla2x00_full_login_lip(vha); |
0c8c39af | 1294 | if (ret != QLA_SUCCESS) { |
7c3df132 SK |
1295 | ql_dbg(ql_dbg_taskm, vha, 0x802d, |
1296 | "full_login_lip=%d.\n", ret); | |
749af3d5 AC |
1297 | } |
1298 | atomic_set(&vha->loop_state, LOOP_DOWN); | |
1299 | atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); | |
1300 | qla2x00_mark_all_devices_lost(vha, 0); | |
0c8c39af AV |
1301 | } |
1302 | ||
0d6e61bc | 1303 | if (ha->flags.enable_lip_reset) { |
e315cd28 | 1304 | ret = qla2x00_lip_reset(vha); |
ad537689 | 1305 | if (ret != QLA_SUCCESS) |
7c3df132 SK |
1306 | ql_dbg(ql_dbg_taskm, vha, 0x802e, |
1307 | "lip_reset failed (%d).\n", ret); | |
1da177e4 LT |
1308 | } |
1309 | ||
1da177e4 | 1310 | /* Issue marker command only when we are going to start the I/O */ |
e315cd28 | 1311 | vha->marker_needed = 1; |
1da177e4 | 1312 | |
0c8c39af | 1313 | return QLA_SUCCESS; |
1da177e4 LT |
1314 | } |
1315 | ||
df4bf0bb | 1316 | void |
e315cd28 | 1317 | qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) |
df4bf0bb | 1318 | { |
73208dfd | 1319 | int que, cnt; |
df4bf0bb AV |
1320 | unsigned long flags; |
1321 | srb_t *sp; | |
e315cd28 | 1322 | struct qla_hw_data *ha = vha->hw; |
73208dfd | 1323 | struct req_que *req; |
df4bf0bb AV |
1324 | |
1325 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
2afa19a9 | 1326 | for (que = 0; que < ha->max_req_queues; que++) { |
29bdccbe | 1327 | req = ha->req_q_map[que]; |
73208dfd AC |
1328 | if (!req) |
1329 | continue; | |
1330 | for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) { | |
1331 | sp = req->outstanding_cmds[cnt]; | |
e612d465 | 1332 | if (sp) { |
73208dfd | 1333 | req->outstanding_cmds[cnt] = NULL; |
9ba56b95 | 1334 | sp->done(vha, sp, res); |
73208dfd | 1335 | } |
df4bf0bb AV |
1336 | } |
1337 | } | |
1338 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1339 | } | |
1340 | ||
f4f051eb | 1341 | static int |
1342 | qla2xxx_slave_alloc(struct scsi_device *sdev) | |
1da177e4 | 1343 | { |
bdf79621 | 1344 | struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); |
1da177e4 | 1345 | |
19a7b4ae | 1346 | if (!rport || fc_remote_port_chkready(rport)) |
f4f051eb | 1347 | return -ENXIO; |
bdf79621 | 1348 | |
19a7b4ae | 1349 | sdev->hostdata = *(fc_port_t **)rport->dd_data; |
1da177e4 | 1350 | |
f4f051eb | 1351 | return 0; |
1352 | } | |
1da177e4 | 1353 | |
f4f051eb | 1354 | static int |
1355 | qla2xxx_slave_configure(struct scsi_device *sdev) | |
1356 | { | |
e315cd28 | 1357 | scsi_qla_host_t *vha = shost_priv(sdev->host); |
2afa19a9 | 1358 | struct req_que *req = vha->req; |
8482e118 | 1359 | |
f4f051eb | 1360 | if (sdev->tagged_supported) |
73208dfd | 1361 | scsi_activate_tcq(sdev, req->max_q_depth); |
f4f051eb | 1362 | else |
73208dfd | 1363 | scsi_deactivate_tcq(sdev, req->max_q_depth); |
f4f051eb | 1364 | return 0; |
1365 | } | |
1da177e4 | 1366 | |
f4f051eb | 1367 | static void |
1368 | qla2xxx_slave_destroy(struct scsi_device *sdev) | |
1369 | { | |
1370 | sdev->hostdata = NULL; | |
1da177e4 LT |
1371 | } |
1372 | ||
c45dd305 GM |
1373 | static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth) |
1374 | { | |
1375 | fc_port_t *fcport = (struct fc_port *) sdev->hostdata; | |
1376 | ||
1377 | if (!scsi_track_queue_full(sdev, qdepth)) | |
1378 | return; | |
1379 | ||
7c3df132 | 1380 | ql_dbg(ql_dbg_io, fcport->vha, 0x3029, |
cfb0919c CD |
1381 | "Queue depth adjusted-down to %d for nexus=%ld:%d:%d.\n", |
1382 | sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun); | |
c45dd305 GM |
1383 | } |
1384 | ||
1385 | static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth) | |
1386 | { | |
1387 | fc_port_t *fcport = sdev->hostdata; | |
1388 | struct scsi_qla_host *vha = fcport->vha; | |
c45dd305 GM |
1389 | struct req_que *req = NULL; |
1390 | ||
1391 | req = vha->req; | |
1392 | if (!req) | |
1393 | return; | |
1394 | ||
1395 | if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth) | |
1396 | return; | |
1397 | ||
1398 | if (sdev->ordered_tags) | |
1399 | scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth); | |
1400 | else | |
1401 | scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth); | |
1402 | ||
7c3df132 | 1403 | ql_dbg(ql_dbg_io, vha, 0x302a, |
cfb0919c CD |
1404 | "Queue depth adjusted-up to %d for nexus=%ld:%d:%d.\n", |
1405 | sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun); | |
c45dd305 GM |
1406 | } |
1407 | ||
ce7e4af7 | 1408 | static int |
e881a172 | 1409 | qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason) |
ce7e4af7 | 1410 | { |
c45dd305 GM |
1411 | switch (reason) { |
1412 | case SCSI_QDEPTH_DEFAULT: | |
1413 | scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth); | |
1414 | break; | |
1415 | case SCSI_QDEPTH_QFULL: | |
1416 | qla2x00_handle_queue_full(sdev, qdepth); | |
1417 | break; | |
1418 | case SCSI_QDEPTH_RAMP_UP: | |
1419 | qla2x00_adjust_sdev_qdepth_up(sdev, qdepth); | |
1420 | break; | |
1421 | default: | |
08002af2 | 1422 | return -EOPNOTSUPP; |
c45dd305 | 1423 | } |
e881a172 | 1424 | |
ce7e4af7 AV |
1425 | return sdev->queue_depth; |
1426 | } | |
1427 | ||
1428 | static int | |
1429 | qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type) | |
1430 | { | |
1431 | if (sdev->tagged_supported) { | |
1432 | scsi_set_tag_type(sdev, tag_type); | |
1433 | if (tag_type) | |
1434 | scsi_activate_tcq(sdev, sdev->queue_depth); | |
1435 | else | |
1436 | scsi_deactivate_tcq(sdev, sdev->queue_depth); | |
1437 | } else | |
1438 | tag_type = 0; | |
1439 | ||
1440 | return tag_type; | |
1441 | } | |
1442 | ||
1da177e4 LT |
1443 | /** |
1444 | * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. | |
1445 | * @ha: HA context | |
1446 | * | |
1447 | * At exit, the @ha's flags.enable_64bit_addressing set to indicated | |
1448 | * supported addressing method. | |
1449 | */ | |
1450 | static void | |
53303c42 | 1451 | qla2x00_config_dma_addressing(struct qla_hw_data *ha) |
1da177e4 | 1452 | { |
7524f9b9 | 1453 | /* Assume a 32bit DMA mask. */ |
1da177e4 | 1454 | ha->flags.enable_64bit_addressing = 0; |
1da177e4 | 1455 | |
6a35528a | 1456 | if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { |
7524f9b9 AV |
1457 | /* Any upper-dword bits set? */ |
1458 | if (MSD(dma_get_required_mask(&ha->pdev->dev)) && | |
6a35528a | 1459 | !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { |
7524f9b9 | 1460 | /* Ok, a 64bit DMA mask is applicable. */ |
1da177e4 | 1461 | ha->flags.enable_64bit_addressing = 1; |
fd34f556 AV |
1462 | ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; |
1463 | ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; | |
7524f9b9 | 1464 | return; |
1da177e4 | 1465 | } |
1da177e4 | 1466 | } |
7524f9b9 | 1467 | |
284901a9 YH |
1468 | dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); |
1469 | pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); | |
1da177e4 LT |
1470 | } |
1471 | ||
fd34f556 | 1472 | static void |
e315cd28 | 1473 | qla2x00_enable_intrs(struct qla_hw_data *ha) |
fd34f556 AV |
1474 | { |
1475 | unsigned long flags = 0; | |
1476 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
1477 | ||
1478 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1479 | ha->interrupts_on = 1; | |
1480 | /* enable risc and host interrupts */ | |
1481 | WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); | |
1482 | RD_REG_WORD(®->ictrl); | |
1483 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1484 | ||
1485 | } | |
1486 | ||
1487 | static void | |
e315cd28 | 1488 | qla2x00_disable_intrs(struct qla_hw_data *ha) |
fd34f556 AV |
1489 | { |
1490 | unsigned long flags = 0; | |
1491 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
1492 | ||
1493 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1494 | ha->interrupts_on = 0; | |
1495 | /* disable risc and host interrupts */ | |
1496 | WRT_REG_WORD(®->ictrl, 0); | |
1497 | RD_REG_WORD(®->ictrl); | |
1498 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1499 | } | |
1500 | ||
1501 | static void | |
e315cd28 | 1502 | qla24xx_enable_intrs(struct qla_hw_data *ha) |
fd34f556 AV |
1503 | { |
1504 | unsigned long flags = 0; | |
1505 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
1506 | ||
1507 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1508 | ha->interrupts_on = 1; | |
1509 | WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); | |
1510 | RD_REG_DWORD(®->ictrl); | |
1511 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1512 | } | |
1513 | ||
1514 | static void | |
e315cd28 | 1515 | qla24xx_disable_intrs(struct qla_hw_data *ha) |
fd34f556 AV |
1516 | { |
1517 | unsigned long flags = 0; | |
1518 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
1519 | ||
124f85e6 AV |
1520 | if (IS_NOPOLLING_TYPE(ha)) |
1521 | return; | |
fd34f556 AV |
1522 | spin_lock_irqsave(&ha->hardware_lock, flags); |
1523 | ha->interrupts_on = 0; | |
1524 | WRT_REG_DWORD(®->ictrl, 0); | |
1525 | RD_REG_DWORD(®->ictrl); | |
1526 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1527 | } | |
1528 | ||
706f457d GM |
1529 | static int |
1530 | qla2x00_iospace_config(struct qla_hw_data *ha) | |
1531 | { | |
1532 | resource_size_t pio; | |
1533 | uint16_t msix; | |
1534 | int cpus; | |
1535 | ||
706f457d GM |
1536 | if (pci_request_selected_regions(ha->pdev, ha->bars, |
1537 | QLA2XXX_DRIVER_NAME)) { | |
1538 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, | |
1539 | "Failed to reserve PIO/MMIO regions (%s), aborting.\n", | |
1540 | pci_name(ha->pdev)); | |
1541 | goto iospace_error_exit; | |
1542 | } | |
1543 | if (!(ha->bars & 1)) | |
1544 | goto skip_pio; | |
1545 | ||
1546 | /* We only need PIO for Flash operations on ISP2312 v2 chips. */ | |
1547 | pio = pci_resource_start(ha->pdev, 0); | |
1548 | if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { | |
1549 | if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { | |
1550 | ql_log_pci(ql_log_warn, ha->pdev, 0x0012, | |
1551 | "Invalid pci I/O region size (%s).\n", | |
1552 | pci_name(ha->pdev)); | |
1553 | pio = 0; | |
1554 | } | |
1555 | } else { | |
1556 | ql_log_pci(ql_log_warn, ha->pdev, 0x0013, | |
1557 | "Region #0 no a PIO resource (%s).\n", | |
1558 | pci_name(ha->pdev)); | |
1559 | pio = 0; | |
1560 | } | |
1561 | ha->pio_address = pio; | |
1562 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, | |
1563 | "PIO address=%llu.\n", | |
1564 | (unsigned long long)ha->pio_address); | |
1565 | ||
1566 | skip_pio: | |
1567 | /* Use MMIO operations for all accesses. */ | |
1568 | if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { | |
1569 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, | |
1570 | "Region #1 not an MMIO resource (%s), aborting.\n", | |
1571 | pci_name(ha->pdev)); | |
1572 | goto iospace_error_exit; | |
1573 | } | |
1574 | if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { | |
1575 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, | |
1576 | "Invalid PCI mem region size (%s), aborting.\n", | |
1577 | pci_name(ha->pdev)); | |
1578 | goto iospace_error_exit; | |
1579 | } | |
1580 | ||
1581 | ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); | |
1582 | if (!ha->iobase) { | |
1583 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, | |
1584 | "Cannot remap MMIO (%s), aborting.\n", | |
1585 | pci_name(ha->pdev)); | |
1586 | goto iospace_error_exit; | |
1587 | } | |
1588 | ||
1589 | /* Determine queue resources */ | |
1590 | ha->max_req_queues = ha->max_rsp_queues = 1; | |
1591 | if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) || | |
1592 | (ql2xmaxqueues > 1 && ql2xmultique_tag) || | |
1593 | (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) | |
1594 | goto mqiobase_exit; | |
1595 | ||
1596 | ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), | |
1597 | pci_resource_len(ha->pdev, 3)); | |
1598 | if (ha->mqiobase) { | |
1599 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, | |
1600 | "MQIO Base=%p.\n", ha->mqiobase); | |
1601 | /* Read MSIX vector size of the board */ | |
1602 | pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); | |
1603 | ha->msix_count = msix; | |
1604 | /* Max queues are bounded by available msix vectors */ | |
1605 | /* queue 0 uses two msix vectors */ | |
1606 | if (ql2xmultique_tag) { | |
1607 | cpus = num_online_cpus(); | |
1608 | ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ? | |
1609 | (cpus + 1) : (ha->msix_count - 1); | |
1610 | ha->max_req_queues = 2; | |
1611 | } else if (ql2xmaxqueues > 1) { | |
1612 | ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ? | |
1613 | QLA_MQ_SIZE : ql2xmaxqueues; | |
1614 | ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008, | |
1615 | "QoS mode set, max no of request queues:%d.\n", | |
1616 | ha->max_req_queues); | |
1617 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019, | |
1618 | "QoS mode set, max no of request queues:%d.\n", | |
1619 | ha->max_req_queues); | |
1620 | } | |
1621 | ql_log_pci(ql_log_info, ha->pdev, 0x001a, | |
1622 | "MSI-X vector count: %d.\n", msix); | |
1623 | } else | |
1624 | ql_log_pci(ql_log_info, ha->pdev, 0x001b, | |
1625 | "BAR 3 not enabled.\n"); | |
1626 | ||
1627 | mqiobase_exit: | |
1628 | ha->msix_count = ha->max_rsp_queues + 1; | |
1629 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, | |
1630 | "MSIX Count:%d.\n", ha->msix_count); | |
1631 | return (0); | |
1632 | ||
1633 | iospace_error_exit: | |
1634 | return (-ENOMEM); | |
1635 | } | |
1636 | ||
1637 | ||
6246b8a1 GM |
1638 | static int |
1639 | qla83xx_iospace_config(struct qla_hw_data *ha) | |
1640 | { | |
1641 | uint16_t msix; | |
1642 | int cpus; | |
1643 | ||
1644 | if (pci_request_selected_regions(ha->pdev, ha->bars, | |
1645 | QLA2XXX_DRIVER_NAME)) { | |
1646 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, | |
1647 | "Failed to reserve PIO/MMIO regions (%s), aborting.\n", | |
1648 | pci_name(ha->pdev)); | |
1649 | ||
1650 | goto iospace_error_exit; | |
1651 | } | |
1652 | ||
1653 | /* Use MMIO operations for all accesses. */ | |
1654 | if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { | |
1655 | ql_log_pci(ql_log_warn, ha->pdev, 0x0118, | |
1656 | "Invalid pci I/O region size (%s).\n", | |
1657 | pci_name(ha->pdev)); | |
1658 | goto iospace_error_exit; | |
1659 | } | |
1660 | if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { | |
1661 | ql_log_pci(ql_log_warn, ha->pdev, 0x0119, | |
1662 | "Invalid PCI mem region size (%s), aborting\n", | |
1663 | pci_name(ha->pdev)); | |
1664 | goto iospace_error_exit; | |
1665 | } | |
1666 | ||
1667 | ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); | |
1668 | if (!ha->iobase) { | |
1669 | ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, | |
1670 | "Cannot remap MMIO (%s), aborting.\n", | |
1671 | pci_name(ha->pdev)); | |
1672 | goto iospace_error_exit; | |
1673 | } | |
1674 | ||
1675 | /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ | |
1676 | /* 83XX 26XX always use MQ type access for queues | |
1677 | * - mbar 2, a.k.a region 4 */ | |
1678 | ha->max_req_queues = ha->max_rsp_queues = 1; | |
1679 | ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), | |
1680 | pci_resource_len(ha->pdev, 4)); | |
1681 | ||
1682 | if (!ha->mqiobase) { | |
1683 | ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, | |
1684 | "BAR2/region4 not enabled\n"); | |
1685 | goto mqiobase_exit; | |
1686 | } | |
1687 | ||
1688 | ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), | |
1689 | pci_resource_len(ha->pdev, 2)); | |
1690 | if (ha->msixbase) { | |
1691 | /* Read MSIX vector size of the board */ | |
1692 | pci_read_config_word(ha->pdev, | |
1693 | QLA_83XX_PCI_MSIX_CONTROL, &msix); | |
1694 | ha->msix_count = msix; | |
1695 | /* Max queues are bounded by available msix vectors */ | |
1696 | /* queue 0 uses two msix vectors */ | |
1697 | if (ql2xmultique_tag) { | |
1698 | cpus = num_online_cpus(); | |
1699 | ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ? | |
1700 | (cpus + 1) : (ha->msix_count - 1); | |
1701 | ha->max_req_queues = 2; | |
1702 | } else if (ql2xmaxqueues > 1) { | |
1703 | ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ? | |
1704 | QLA_MQ_SIZE : ql2xmaxqueues; | |
1705 | ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c, | |
1706 | "QoS mode set, max no of request queues:%d.\n", | |
1707 | ha->max_req_queues); | |
1708 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, | |
1709 | "QoS mode set, max no of request queues:%d.\n", | |
1710 | ha->max_req_queues); | |
1711 | } | |
1712 | ql_log_pci(ql_log_info, ha->pdev, 0x011c, | |
1713 | "MSI-X vector count: %d.\n", msix); | |
1714 | } else | |
1715 | ql_log_pci(ql_log_info, ha->pdev, 0x011e, | |
1716 | "BAR 1 not enabled.\n"); | |
1717 | ||
1718 | mqiobase_exit: | |
1719 | ha->msix_count = ha->max_rsp_queues + 1; | |
1720 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, | |
1721 | "MSIX Count:%d.\n", ha->msix_count); | |
1722 | return 0; | |
1723 | ||
1724 | iospace_error_exit: | |
1725 | return -ENOMEM; | |
1726 | } | |
1727 | ||
fd34f556 AV |
1728 | static struct isp_operations qla2100_isp_ops = { |
1729 | .pci_config = qla2100_pci_config, | |
1730 | .reset_chip = qla2x00_reset_chip, | |
1731 | .chip_diag = qla2x00_chip_diag, | |
1732 | .config_rings = qla2x00_config_rings, | |
1733 | .reset_adapter = qla2x00_reset_adapter, | |
1734 | .nvram_config = qla2x00_nvram_config, | |
1735 | .update_fw_options = qla2x00_update_fw_options, | |
1736 | .load_risc = qla2x00_load_risc, | |
1737 | .pci_info_str = qla2x00_pci_info_str, | |
1738 | .fw_version_str = qla2x00_fw_version_str, | |
1739 | .intr_handler = qla2100_intr_handler, | |
1740 | .enable_intrs = qla2x00_enable_intrs, | |
1741 | .disable_intrs = qla2x00_disable_intrs, | |
1742 | .abort_command = qla2x00_abort_command, | |
523ec773 AV |
1743 | .target_reset = qla2x00_abort_target, |
1744 | .lun_reset = qla2x00_lun_reset, | |
fd34f556 AV |
1745 | .fabric_login = qla2x00_login_fabric, |
1746 | .fabric_logout = qla2x00_fabric_logout, | |
1747 | .calc_req_entries = qla2x00_calc_iocbs_32, | |
1748 | .build_iocbs = qla2x00_build_scsi_iocbs_32, | |
1749 | .prep_ms_iocb = qla2x00_prep_ms_iocb, | |
1750 | .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, | |
1751 | .read_nvram = qla2x00_read_nvram_data, | |
1752 | .write_nvram = qla2x00_write_nvram_data, | |
1753 | .fw_dump = qla2100_fw_dump, | |
1754 | .beacon_on = NULL, | |
1755 | .beacon_off = NULL, | |
1756 | .beacon_blink = NULL, | |
1757 | .read_optrom = qla2x00_read_optrom_data, | |
1758 | .write_optrom = qla2x00_write_optrom_data, | |
1759 | .get_flash_version = qla2x00_get_flash_version, | |
e315cd28 | 1760 | .start_scsi = qla2x00_start_scsi, |
a9083016 | 1761 | .abort_isp = qla2x00_abort_isp, |
706f457d | 1762 | .iospace_config = qla2x00_iospace_config, |
fd34f556 AV |
1763 | }; |
1764 | ||
1765 | static struct isp_operations qla2300_isp_ops = { | |
1766 | .pci_config = qla2300_pci_config, | |
1767 | .reset_chip = qla2x00_reset_chip, | |
1768 | .chip_diag = qla2x00_chip_diag, | |
1769 | .config_rings = qla2x00_config_rings, | |
1770 | .reset_adapter = qla2x00_reset_adapter, | |
1771 | .nvram_config = qla2x00_nvram_config, | |
1772 | .update_fw_options = qla2x00_update_fw_options, | |
1773 | .load_risc = qla2x00_load_risc, | |
1774 | .pci_info_str = qla2x00_pci_info_str, | |
1775 | .fw_version_str = qla2x00_fw_version_str, | |
1776 | .intr_handler = qla2300_intr_handler, | |
1777 | .enable_intrs = qla2x00_enable_intrs, | |
1778 | .disable_intrs = qla2x00_disable_intrs, | |
1779 | .abort_command = qla2x00_abort_command, | |
523ec773 AV |
1780 | .target_reset = qla2x00_abort_target, |
1781 | .lun_reset = qla2x00_lun_reset, | |
fd34f556 AV |
1782 | .fabric_login = qla2x00_login_fabric, |
1783 | .fabric_logout = qla2x00_fabric_logout, | |
1784 | .calc_req_entries = qla2x00_calc_iocbs_32, | |
1785 | .build_iocbs = qla2x00_build_scsi_iocbs_32, | |
1786 | .prep_ms_iocb = qla2x00_prep_ms_iocb, | |
1787 | .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, | |
1788 | .read_nvram = qla2x00_read_nvram_data, | |
1789 | .write_nvram = qla2x00_write_nvram_data, | |
1790 | .fw_dump = qla2300_fw_dump, | |
1791 | .beacon_on = qla2x00_beacon_on, | |
1792 | .beacon_off = qla2x00_beacon_off, | |
1793 | .beacon_blink = qla2x00_beacon_blink, | |
1794 | .read_optrom = qla2x00_read_optrom_data, | |
1795 | .write_optrom = qla2x00_write_optrom_data, | |
1796 | .get_flash_version = qla2x00_get_flash_version, | |
e315cd28 | 1797 | .start_scsi = qla2x00_start_scsi, |
a9083016 | 1798 | .abort_isp = qla2x00_abort_isp, |
706f457d | 1799 | .iospace_config = qla2x00_iospace_config, |
fd34f556 AV |
1800 | }; |
1801 | ||
1802 | static struct isp_operations qla24xx_isp_ops = { | |
1803 | .pci_config = qla24xx_pci_config, | |
1804 | .reset_chip = qla24xx_reset_chip, | |
1805 | .chip_diag = qla24xx_chip_diag, | |
1806 | .config_rings = qla24xx_config_rings, | |
1807 | .reset_adapter = qla24xx_reset_adapter, | |
1808 | .nvram_config = qla24xx_nvram_config, | |
1809 | .update_fw_options = qla24xx_update_fw_options, | |
1810 | .load_risc = qla24xx_load_risc, | |
1811 | .pci_info_str = qla24xx_pci_info_str, | |
1812 | .fw_version_str = qla24xx_fw_version_str, | |
1813 | .intr_handler = qla24xx_intr_handler, | |
1814 | .enable_intrs = qla24xx_enable_intrs, | |
1815 | .disable_intrs = qla24xx_disable_intrs, | |
1816 | .abort_command = qla24xx_abort_command, | |
523ec773 AV |
1817 | .target_reset = qla24xx_abort_target, |
1818 | .lun_reset = qla24xx_lun_reset, | |
fd34f556 AV |
1819 | .fabric_login = qla24xx_login_fabric, |
1820 | .fabric_logout = qla24xx_fabric_logout, | |
1821 | .calc_req_entries = NULL, | |
1822 | .build_iocbs = NULL, | |
1823 | .prep_ms_iocb = qla24xx_prep_ms_iocb, | |
1824 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, | |
1825 | .read_nvram = qla24xx_read_nvram_data, | |
1826 | .write_nvram = qla24xx_write_nvram_data, | |
1827 | .fw_dump = qla24xx_fw_dump, | |
1828 | .beacon_on = qla24xx_beacon_on, | |
1829 | .beacon_off = qla24xx_beacon_off, | |
1830 | .beacon_blink = qla24xx_beacon_blink, | |
1831 | .read_optrom = qla24xx_read_optrom_data, | |
1832 | .write_optrom = qla24xx_write_optrom_data, | |
1833 | .get_flash_version = qla24xx_get_flash_version, | |
e315cd28 | 1834 | .start_scsi = qla24xx_start_scsi, |
a9083016 | 1835 | .abort_isp = qla2x00_abort_isp, |
706f457d | 1836 | .iospace_config = qla2x00_iospace_config, |
fd34f556 AV |
1837 | }; |
1838 | ||
c3a2f0df AV |
1839 | static struct isp_operations qla25xx_isp_ops = { |
1840 | .pci_config = qla25xx_pci_config, | |
1841 | .reset_chip = qla24xx_reset_chip, | |
1842 | .chip_diag = qla24xx_chip_diag, | |
1843 | .config_rings = qla24xx_config_rings, | |
1844 | .reset_adapter = qla24xx_reset_adapter, | |
1845 | .nvram_config = qla24xx_nvram_config, | |
1846 | .update_fw_options = qla24xx_update_fw_options, | |
1847 | .load_risc = qla24xx_load_risc, | |
1848 | .pci_info_str = qla24xx_pci_info_str, | |
1849 | .fw_version_str = qla24xx_fw_version_str, | |
1850 | .intr_handler = qla24xx_intr_handler, | |
1851 | .enable_intrs = qla24xx_enable_intrs, | |
1852 | .disable_intrs = qla24xx_disable_intrs, | |
1853 | .abort_command = qla24xx_abort_command, | |
523ec773 AV |
1854 | .target_reset = qla24xx_abort_target, |
1855 | .lun_reset = qla24xx_lun_reset, | |
c3a2f0df AV |
1856 | .fabric_login = qla24xx_login_fabric, |
1857 | .fabric_logout = qla24xx_fabric_logout, | |
1858 | .calc_req_entries = NULL, | |
1859 | .build_iocbs = NULL, | |
1860 | .prep_ms_iocb = qla24xx_prep_ms_iocb, | |
1861 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, | |
1862 | .read_nvram = qla25xx_read_nvram_data, | |
1863 | .write_nvram = qla25xx_write_nvram_data, | |
1864 | .fw_dump = qla25xx_fw_dump, | |
1865 | .beacon_on = qla24xx_beacon_on, | |
1866 | .beacon_off = qla24xx_beacon_off, | |
1867 | .beacon_blink = qla24xx_beacon_blink, | |
338c9161 | 1868 | .read_optrom = qla25xx_read_optrom_data, |
c3a2f0df AV |
1869 | .write_optrom = qla24xx_write_optrom_data, |
1870 | .get_flash_version = qla24xx_get_flash_version, | |
bad75002 | 1871 | .start_scsi = qla24xx_dif_start_scsi, |
a9083016 | 1872 | .abort_isp = qla2x00_abort_isp, |
706f457d | 1873 | .iospace_config = qla2x00_iospace_config, |
c3a2f0df AV |
1874 | }; |
1875 | ||
3a03eb79 AV |
1876 | static struct isp_operations qla81xx_isp_ops = { |
1877 | .pci_config = qla25xx_pci_config, | |
1878 | .reset_chip = qla24xx_reset_chip, | |
1879 | .chip_diag = qla24xx_chip_diag, | |
1880 | .config_rings = qla24xx_config_rings, | |
1881 | .reset_adapter = qla24xx_reset_adapter, | |
1882 | .nvram_config = qla81xx_nvram_config, | |
1883 | .update_fw_options = qla81xx_update_fw_options, | |
eaac30be | 1884 | .load_risc = qla81xx_load_risc, |
3a03eb79 AV |
1885 | .pci_info_str = qla24xx_pci_info_str, |
1886 | .fw_version_str = qla24xx_fw_version_str, | |
1887 | .intr_handler = qla24xx_intr_handler, | |
1888 | .enable_intrs = qla24xx_enable_intrs, | |
1889 | .disable_intrs = qla24xx_disable_intrs, | |
1890 | .abort_command = qla24xx_abort_command, | |
1891 | .target_reset = qla24xx_abort_target, | |
1892 | .lun_reset = qla24xx_lun_reset, | |
1893 | .fabric_login = qla24xx_login_fabric, | |
1894 | .fabric_logout = qla24xx_fabric_logout, | |
1895 | .calc_req_entries = NULL, | |
1896 | .build_iocbs = NULL, | |
1897 | .prep_ms_iocb = qla24xx_prep_ms_iocb, | |
1898 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, | |
3d79038f AV |
1899 | .read_nvram = NULL, |
1900 | .write_nvram = NULL, | |
3a03eb79 AV |
1901 | .fw_dump = qla81xx_fw_dump, |
1902 | .beacon_on = qla24xx_beacon_on, | |
1903 | .beacon_off = qla24xx_beacon_off, | |
6246b8a1 | 1904 | .beacon_blink = qla83xx_beacon_blink, |
3a03eb79 AV |
1905 | .read_optrom = qla25xx_read_optrom_data, |
1906 | .write_optrom = qla24xx_write_optrom_data, | |
1907 | .get_flash_version = qla24xx_get_flash_version, | |
ba77ef53 | 1908 | .start_scsi = qla24xx_dif_start_scsi, |
a9083016 | 1909 | .abort_isp = qla2x00_abort_isp, |
706f457d | 1910 | .iospace_config = qla2x00_iospace_config, |
a9083016 GM |
1911 | }; |
1912 | ||
1913 | static struct isp_operations qla82xx_isp_ops = { | |
1914 | .pci_config = qla82xx_pci_config, | |
1915 | .reset_chip = qla82xx_reset_chip, | |
1916 | .chip_diag = qla24xx_chip_diag, | |
1917 | .config_rings = qla82xx_config_rings, | |
1918 | .reset_adapter = qla24xx_reset_adapter, | |
1919 | .nvram_config = qla81xx_nvram_config, | |
1920 | .update_fw_options = qla24xx_update_fw_options, | |
1921 | .load_risc = qla82xx_load_risc, | |
1922 | .pci_info_str = qla82xx_pci_info_str, | |
1923 | .fw_version_str = qla24xx_fw_version_str, | |
1924 | .intr_handler = qla82xx_intr_handler, | |
1925 | .enable_intrs = qla82xx_enable_intrs, | |
1926 | .disable_intrs = qla82xx_disable_intrs, | |
1927 | .abort_command = qla24xx_abort_command, | |
1928 | .target_reset = qla24xx_abort_target, | |
1929 | .lun_reset = qla24xx_lun_reset, | |
1930 | .fabric_login = qla24xx_login_fabric, | |
1931 | .fabric_logout = qla24xx_fabric_logout, | |
1932 | .calc_req_entries = NULL, | |
1933 | .build_iocbs = NULL, | |
1934 | .prep_ms_iocb = qla24xx_prep_ms_iocb, | |
1935 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, | |
1936 | .read_nvram = qla24xx_read_nvram_data, | |
1937 | .write_nvram = qla24xx_write_nvram_data, | |
1938 | .fw_dump = qla24xx_fw_dump, | |
999916dc SK |
1939 | .beacon_on = qla82xx_beacon_on, |
1940 | .beacon_off = qla82xx_beacon_off, | |
1941 | .beacon_blink = NULL, | |
a9083016 GM |
1942 | .read_optrom = qla82xx_read_optrom_data, |
1943 | .write_optrom = qla82xx_write_optrom_data, | |
1944 | .get_flash_version = qla24xx_get_flash_version, | |
1945 | .start_scsi = qla82xx_start_scsi, | |
1946 | .abort_isp = qla82xx_abort_isp, | |
706f457d | 1947 | .iospace_config = qla82xx_iospace_config, |
3a03eb79 AV |
1948 | }; |
1949 | ||
6246b8a1 GM |
1950 | static struct isp_operations qla83xx_isp_ops = { |
1951 | .pci_config = qla25xx_pci_config, | |
1952 | .reset_chip = qla24xx_reset_chip, | |
1953 | .chip_diag = qla24xx_chip_diag, | |
1954 | .config_rings = qla24xx_config_rings, | |
1955 | .reset_adapter = qla24xx_reset_adapter, | |
1956 | .nvram_config = qla81xx_nvram_config, | |
1957 | .update_fw_options = qla81xx_update_fw_options, | |
1958 | .load_risc = qla81xx_load_risc, | |
1959 | .pci_info_str = qla24xx_pci_info_str, | |
1960 | .fw_version_str = qla24xx_fw_version_str, | |
1961 | .intr_handler = qla24xx_intr_handler, | |
1962 | .enable_intrs = qla24xx_enable_intrs, | |
1963 | .disable_intrs = qla24xx_disable_intrs, | |
1964 | .abort_command = qla24xx_abort_command, | |
1965 | .target_reset = qla24xx_abort_target, | |
1966 | .lun_reset = qla24xx_lun_reset, | |
1967 | .fabric_login = qla24xx_login_fabric, | |
1968 | .fabric_logout = qla24xx_fabric_logout, | |
1969 | .calc_req_entries = NULL, | |
1970 | .build_iocbs = NULL, | |
1971 | .prep_ms_iocb = qla24xx_prep_ms_iocb, | |
1972 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, | |
1973 | .read_nvram = NULL, | |
1974 | .write_nvram = NULL, | |
1975 | .fw_dump = qla83xx_fw_dump, | |
1976 | .beacon_on = qla24xx_beacon_on, | |
1977 | .beacon_off = qla24xx_beacon_off, | |
1978 | .beacon_blink = qla83xx_beacon_blink, | |
1979 | .read_optrom = qla25xx_read_optrom_data, | |
1980 | .write_optrom = qla24xx_write_optrom_data, | |
1981 | .get_flash_version = qla24xx_get_flash_version, | |
1982 | .start_scsi = qla24xx_dif_start_scsi, | |
1983 | .abort_isp = qla2x00_abort_isp, | |
1984 | .iospace_config = qla83xx_iospace_config, | |
1985 | }; | |
1986 | ||
ea5b6382 | 1987 | static inline void |
e315cd28 | 1988 | qla2x00_set_isp_flags(struct qla_hw_data *ha) |
ea5b6382 | 1989 | { |
1990 | ha->device_type = DT_EXTENDED_IDS; | |
1991 | switch (ha->pdev->device) { | |
1992 | case PCI_DEVICE_ID_QLOGIC_ISP2100: | |
1993 | ha->device_type |= DT_ISP2100; | |
1994 | ha->device_type &= ~DT_EXTENDED_IDS; | |
441d1072 | 1995 | ha->fw_srisc_address = RISC_START_ADDRESS_2100; |
ea5b6382 | 1996 | break; |
1997 | case PCI_DEVICE_ID_QLOGIC_ISP2200: | |
1998 | ha->device_type |= DT_ISP2200; | |
1999 | ha->device_type &= ~DT_EXTENDED_IDS; | |
441d1072 | 2000 | ha->fw_srisc_address = RISC_START_ADDRESS_2100; |
ea5b6382 | 2001 | break; |
2002 | case PCI_DEVICE_ID_QLOGIC_ISP2300: | |
2003 | ha->device_type |= DT_ISP2300; | |
4a59f71d | 2004 | ha->device_type |= DT_ZIO_SUPPORTED; |
441d1072 | 2005 | ha->fw_srisc_address = RISC_START_ADDRESS_2300; |
ea5b6382 | 2006 | break; |
2007 | case PCI_DEVICE_ID_QLOGIC_ISP2312: | |
2008 | ha->device_type |= DT_ISP2312; | |
4a59f71d | 2009 | ha->device_type |= DT_ZIO_SUPPORTED; |
441d1072 | 2010 | ha->fw_srisc_address = RISC_START_ADDRESS_2300; |
ea5b6382 | 2011 | break; |
2012 | case PCI_DEVICE_ID_QLOGIC_ISP2322: | |
2013 | ha->device_type |= DT_ISP2322; | |
4a59f71d | 2014 | ha->device_type |= DT_ZIO_SUPPORTED; |
ea5b6382 | 2015 | if (ha->pdev->subsystem_vendor == 0x1028 && |
2016 | ha->pdev->subsystem_device == 0x0170) | |
2017 | ha->device_type |= DT_OEM_001; | |
441d1072 | 2018 | ha->fw_srisc_address = RISC_START_ADDRESS_2300; |
ea5b6382 | 2019 | break; |
2020 | case PCI_DEVICE_ID_QLOGIC_ISP6312: | |
2021 | ha->device_type |= DT_ISP6312; | |
441d1072 | 2022 | ha->fw_srisc_address = RISC_START_ADDRESS_2300; |
ea5b6382 | 2023 | break; |
2024 | case PCI_DEVICE_ID_QLOGIC_ISP6322: | |
2025 | ha->device_type |= DT_ISP6322; | |
441d1072 | 2026 | ha->fw_srisc_address = RISC_START_ADDRESS_2300; |
ea5b6382 | 2027 | break; |
2028 | case PCI_DEVICE_ID_QLOGIC_ISP2422: | |
2029 | ha->device_type |= DT_ISP2422; | |
4a59f71d | 2030 | ha->device_type |= DT_ZIO_SUPPORTED; |
e428924c | 2031 | ha->device_type |= DT_FWI2; |
c76f2c01 | 2032 | ha->device_type |= DT_IIDMA; |
441d1072 | 2033 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; |
ea5b6382 | 2034 | break; |
2035 | case PCI_DEVICE_ID_QLOGIC_ISP2432: | |
2036 | ha->device_type |= DT_ISP2432; | |
4a59f71d | 2037 | ha->device_type |= DT_ZIO_SUPPORTED; |
e428924c | 2038 | ha->device_type |= DT_FWI2; |
c76f2c01 | 2039 | ha->device_type |= DT_IIDMA; |
441d1072 | 2040 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; |
ea5b6382 | 2041 | break; |
4d4df193 HK |
2042 | case PCI_DEVICE_ID_QLOGIC_ISP8432: |
2043 | ha->device_type |= DT_ISP8432; | |
2044 | ha->device_type |= DT_ZIO_SUPPORTED; | |
2045 | ha->device_type |= DT_FWI2; | |
2046 | ha->device_type |= DT_IIDMA; | |
2047 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
2048 | break; | |
044cc6c8 | 2049 | case PCI_DEVICE_ID_QLOGIC_ISP5422: |
2050 | ha->device_type |= DT_ISP5422; | |
e428924c | 2051 | ha->device_type |= DT_FWI2; |
441d1072 | 2052 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; |
ea5b6382 | 2053 | break; |
044cc6c8 | 2054 | case PCI_DEVICE_ID_QLOGIC_ISP5432: |
2055 | ha->device_type |= DT_ISP5432; | |
e428924c | 2056 | ha->device_type |= DT_FWI2; |
441d1072 | 2057 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; |
ea5b6382 | 2058 | break; |
c3a2f0df AV |
2059 | case PCI_DEVICE_ID_QLOGIC_ISP2532: |
2060 | ha->device_type |= DT_ISP2532; | |
2061 | ha->device_type |= DT_ZIO_SUPPORTED; | |
2062 | ha->device_type |= DT_FWI2; | |
2063 | ha->device_type |= DT_IIDMA; | |
441d1072 | 2064 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; |
ea5b6382 | 2065 | break; |
3a03eb79 AV |
2066 | case PCI_DEVICE_ID_QLOGIC_ISP8001: |
2067 | ha->device_type |= DT_ISP8001; | |
2068 | ha->device_type |= DT_ZIO_SUPPORTED; | |
2069 | ha->device_type |= DT_FWI2; | |
2070 | ha->device_type |= DT_IIDMA; | |
2071 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
2072 | break; | |
a9083016 GM |
2073 | case PCI_DEVICE_ID_QLOGIC_ISP8021: |
2074 | ha->device_type |= DT_ISP8021; | |
2075 | ha->device_type |= DT_ZIO_SUPPORTED; | |
2076 | ha->device_type |= DT_FWI2; | |
2077 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
2078 | /* Initialize 82XX ISP flags */ | |
2079 | qla82xx_init_flags(ha); | |
2080 | break; | |
6246b8a1 GM |
2081 | case PCI_DEVICE_ID_QLOGIC_ISP2031: |
2082 | ha->device_type |= DT_ISP2031; | |
2083 | ha->device_type |= DT_ZIO_SUPPORTED; | |
2084 | ha->device_type |= DT_FWI2; | |
2085 | ha->device_type |= DT_IIDMA; | |
2086 | ha->device_type |= DT_T10_PI; | |
2087 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
2088 | break; | |
2089 | case PCI_DEVICE_ID_QLOGIC_ISP8031: | |
2090 | ha->device_type |= DT_ISP8031; | |
2091 | ha->device_type |= DT_ZIO_SUPPORTED; | |
2092 | ha->device_type |= DT_FWI2; | |
2093 | ha->device_type |= DT_IIDMA; | |
2094 | ha->device_type |= DT_T10_PI; | |
2095 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
2096 | break; | |
ea5b6382 | 2097 | } |
e5b68a61 | 2098 | |
a9083016 GM |
2099 | if (IS_QLA82XX(ha)) |
2100 | ha->port_no = !(ha->portnum & 1); | |
2101 | else | |
2102 | /* Get adapter physical port no from interrupt pin register. */ | |
2103 | pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); | |
2104 | ||
e5b68a61 AC |
2105 | if (ha->port_no & 1) |
2106 | ha->flags.port0 = 1; | |
2107 | else | |
2108 | ha->flags.port0 = 0; | |
7c3df132 | 2109 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, |
d8424f68 | 2110 | "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", |
7c3df132 | 2111 | ha->device_type, ha->flags.port0, ha->fw_srisc_address); |
ea5b6382 | 2112 | } |
2113 | ||
1e99e33a AV |
2114 | static void |
2115 | qla2xxx_scan_start(struct Scsi_Host *shost) | |
2116 | { | |
e315cd28 | 2117 | scsi_qla_host_t *vha = shost_priv(shost); |
1e99e33a | 2118 | |
cbc8eb67 AV |
2119 | if (vha->hw->flags.running_gold_fw) |
2120 | return; | |
2121 | ||
e315cd28 AC |
2122 | set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); |
2123 | set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); | |
2124 | set_bit(RSCN_UPDATE, &vha->dpc_flags); | |
2125 | set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); | |
1e99e33a AV |
2126 | } |
2127 | ||
2128 | static int | |
2129 | qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) | |
2130 | { | |
e315cd28 | 2131 | scsi_qla_host_t *vha = shost_priv(shost); |
1e99e33a | 2132 | |
e315cd28 | 2133 | if (!vha->host) |
1e99e33a | 2134 | return 1; |
e315cd28 | 2135 | if (time > vha->hw->loop_reset_delay * HZ) |
1e99e33a AV |
2136 | return 1; |
2137 | ||
e315cd28 | 2138 | return atomic_read(&vha->loop_state) == LOOP_READY; |
1e99e33a AV |
2139 | } |
2140 | ||
1da177e4 LT |
2141 | /* |
2142 | * PCI driver interface | |
2143 | */ | |
7ee61397 AV |
2144 | static int __devinit |
2145 | qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) | |
1da177e4 | 2146 | { |
a1541d5a | 2147 | int ret = -ENODEV; |
1da177e4 | 2148 | struct Scsi_Host *host; |
e315cd28 AC |
2149 | scsi_qla_host_t *base_vha = NULL; |
2150 | struct qla_hw_data *ha; | |
29856e28 | 2151 | char pci_info[30]; |
1da177e4 | 2152 | char fw_str[30]; |
5433383e | 2153 | struct scsi_host_template *sht; |
642ef983 | 2154 | int bars, mem_only = 0; |
e315cd28 | 2155 | uint16_t req_length = 0, rsp_length = 0; |
73208dfd AC |
2156 | struct req_que *req = NULL; |
2157 | struct rsp_que *rsp = NULL; | |
1da177e4 | 2158 | |
285d0321 | 2159 | bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); |
a5326f86 | 2160 | sht = &qla2xxx_driver_template; |
5433383e | 2161 | if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || |
8bc69e7d | 2162 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || |
4d4df193 | 2163 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || |
8bc69e7d | 2164 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || |
c3a2f0df | 2165 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || |
3a03eb79 | 2166 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || |
a9083016 | 2167 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || |
6246b8a1 GM |
2168 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || |
2169 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || | |
2170 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031) { | |
285d0321 | 2171 | bars = pci_select_bars(pdev, IORESOURCE_MEM); |
09483916 | 2172 | mem_only = 1; |
7c3df132 SK |
2173 | ql_dbg_pci(ql_dbg_init, pdev, 0x0007, |
2174 | "Mem only adapter.\n"); | |
285d0321 | 2175 | } |
7c3df132 SK |
2176 | ql_dbg_pci(ql_dbg_init, pdev, 0x0008, |
2177 | "Bars=%d.\n", bars); | |
285d0321 | 2178 | |
09483916 BH |
2179 | if (mem_only) { |
2180 | if (pci_enable_device_mem(pdev)) | |
2181 | goto probe_out; | |
2182 | } else { | |
2183 | if (pci_enable_device(pdev)) | |
2184 | goto probe_out; | |
2185 | } | |
285d0321 | 2186 | |
0927678f JB |
2187 | /* This may fail but that's ok */ |
2188 | pci_enable_pcie_error_reporting(pdev); | |
285d0321 | 2189 | |
e315cd28 AC |
2190 | ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); |
2191 | if (!ha) { | |
7c3df132 SK |
2192 | ql_log_pci(ql_log_fatal, pdev, 0x0009, |
2193 | "Unable to allocate memory for ha.\n"); | |
e315cd28 | 2194 | goto probe_out; |
1da177e4 | 2195 | } |
7c3df132 SK |
2196 | ql_dbg_pci(ql_dbg_init, pdev, 0x000a, |
2197 | "Memory allocated for ha=%p.\n", ha); | |
e315cd28 | 2198 | ha->pdev = pdev; |
2d70c103 | 2199 | ha->tgt.enable_class_2 = ql2xenableclass2; |
1da177e4 LT |
2200 | |
2201 | /* Clear our data area */ | |
285d0321 | 2202 | ha->bars = bars; |
09483916 | 2203 | ha->mem_only = mem_only; |
df4bf0bb | 2204 | spin_lock_init(&ha->hardware_lock); |
339aa70e | 2205 | spin_lock_init(&ha->vport_slock); |
1da177e4 | 2206 | |
ea5b6382 | 2207 | /* Set ISP-type information. */ |
2208 | qla2x00_set_isp_flags(ha); | |
ca79cf66 DG |
2209 | |
2210 | /* Set EEH reset type to fundamental if required by hba */ | |
6246b8a1 | 2211 | if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha)) |
ca79cf66 | 2212 | pdev->needs_freset = 1; |
ca79cf66 | 2213 | |
cba1e47f CD |
2214 | ha->prev_topology = 0; |
2215 | ha->init_cb_size = sizeof(init_cb_t); | |
2216 | ha->link_data_rate = PORT_SPEED_UNKNOWN; | |
2217 | ha->optrom_size = OPTROM_SIZE_2300; | |
2218 | ||
abbd8870 | 2219 | /* Assign ISP specific operations. */ |
1da177e4 | 2220 | if (IS_QLA2100(ha)) { |
642ef983 | 2221 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; |
1da177e4 | 2222 | ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; |
e315cd28 AC |
2223 | req_length = REQUEST_ENTRY_CNT_2100; |
2224 | rsp_length = RESPONSE_ENTRY_CNT_2100; | |
2225 | ha->max_loop_id = SNS_LAST_LOOP_ID_2100; | |
abbd8870 | 2226 | ha->gid_list_info_size = 4; |
3a03eb79 AV |
2227 | ha->flash_conf_off = ~0; |
2228 | ha->flash_data_off = ~0; | |
2229 | ha->nvram_conf_off = ~0; | |
2230 | ha->nvram_data_off = ~0; | |
fd34f556 | 2231 | ha->isp_ops = &qla2100_isp_ops; |
1da177e4 | 2232 | } else if (IS_QLA2200(ha)) { |
642ef983 | 2233 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; |
67ddda35 | 2234 | ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; |
e315cd28 AC |
2235 | req_length = REQUEST_ENTRY_CNT_2200; |
2236 | rsp_length = RESPONSE_ENTRY_CNT_2100; | |
2237 | ha->max_loop_id = SNS_LAST_LOOP_ID_2100; | |
abbd8870 | 2238 | ha->gid_list_info_size = 4; |
3a03eb79 AV |
2239 | ha->flash_conf_off = ~0; |
2240 | ha->flash_data_off = ~0; | |
2241 | ha->nvram_conf_off = ~0; | |
2242 | ha->nvram_data_off = ~0; | |
fd34f556 | 2243 | ha->isp_ops = &qla2100_isp_ops; |
fca29703 | 2244 | } else if (IS_QLA23XX(ha)) { |
642ef983 | 2245 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; |
1da177e4 | 2246 | ha->mbx_count = MAILBOX_REGISTER_COUNT; |
e315cd28 AC |
2247 | req_length = REQUEST_ENTRY_CNT_2200; |
2248 | rsp_length = RESPONSE_ENTRY_CNT_2300; | |
2249 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; | |
abbd8870 | 2250 | ha->gid_list_info_size = 6; |
854165f4 | 2251 | if (IS_QLA2322(ha) || IS_QLA6322(ha)) |
2252 | ha->optrom_size = OPTROM_SIZE_2322; | |
3a03eb79 AV |
2253 | ha->flash_conf_off = ~0; |
2254 | ha->flash_data_off = ~0; | |
2255 | ha->nvram_conf_off = ~0; | |
2256 | ha->nvram_data_off = ~0; | |
fd34f556 | 2257 | ha->isp_ops = &qla2300_isp_ops; |
4d4df193 | 2258 | } else if (IS_QLA24XX_TYPE(ha)) { |
642ef983 | 2259 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; |
fca29703 | 2260 | ha->mbx_count = MAILBOX_REGISTER_COUNT; |
e315cd28 AC |
2261 | req_length = REQUEST_ENTRY_CNT_24XX; |
2262 | rsp_length = RESPONSE_ENTRY_CNT_2300; | |
2d70c103 | 2263 | ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; |
e315cd28 | 2264 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; |
2c3dfe3f | 2265 | ha->init_cb_size = sizeof(struct mid_init_cb_24xx); |
fca29703 | 2266 | ha->gid_list_info_size = 8; |
854165f4 | 2267 | ha->optrom_size = OPTROM_SIZE_24XX; |
73208dfd | 2268 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; |
fd34f556 | 2269 | ha->isp_ops = &qla24xx_isp_ops; |
3a03eb79 AV |
2270 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; |
2271 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA; | |
2272 | ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; | |
2273 | ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; | |
c3a2f0df | 2274 | } else if (IS_QLA25XX(ha)) { |
642ef983 | 2275 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; |
c3a2f0df | 2276 | ha->mbx_count = MAILBOX_REGISTER_COUNT; |
e315cd28 AC |
2277 | req_length = REQUEST_ENTRY_CNT_24XX; |
2278 | rsp_length = RESPONSE_ENTRY_CNT_2300; | |
2d70c103 | 2279 | ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; |
e315cd28 | 2280 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; |
c3a2f0df | 2281 | ha->init_cb_size = sizeof(struct mid_init_cb_24xx); |
c3a2f0df AV |
2282 | ha->gid_list_info_size = 8; |
2283 | ha->optrom_size = OPTROM_SIZE_25XX; | |
73208dfd | 2284 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; |
c3a2f0df | 2285 | ha->isp_ops = &qla25xx_isp_ops; |
3a03eb79 AV |
2286 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; |
2287 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA; | |
2288 | ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; | |
2289 | ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; | |
2290 | } else if (IS_QLA81XX(ha)) { | |
642ef983 | 2291 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; |
3a03eb79 AV |
2292 | ha->mbx_count = MAILBOX_REGISTER_COUNT; |
2293 | req_length = REQUEST_ENTRY_CNT_24XX; | |
2294 | rsp_length = RESPONSE_ENTRY_CNT_2300; | |
2295 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; | |
2296 | ha->init_cb_size = sizeof(struct mid_init_cb_81xx); | |
2297 | ha->gid_list_info_size = 8; | |
2298 | ha->optrom_size = OPTROM_SIZE_81XX; | |
40859ae5 | 2299 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; |
3a03eb79 AV |
2300 | ha->isp_ops = &qla81xx_isp_ops; |
2301 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; | |
2302 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; | |
2303 | ha->nvram_conf_off = ~0; | |
2304 | ha->nvram_data_off = ~0; | |
a9083016 | 2305 | } else if (IS_QLA82XX(ha)) { |
642ef983 | 2306 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; |
a9083016 GM |
2307 | ha->mbx_count = MAILBOX_REGISTER_COUNT; |
2308 | req_length = REQUEST_ENTRY_CNT_82XX; | |
2309 | rsp_length = RESPONSE_ENTRY_CNT_82XX; | |
2310 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; | |
2311 | ha->init_cb_size = sizeof(struct mid_init_cb_81xx); | |
2312 | ha->gid_list_info_size = 8; | |
2313 | ha->optrom_size = OPTROM_SIZE_82XX; | |
087c621e | 2314 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; |
a9083016 GM |
2315 | ha->isp_ops = &qla82xx_isp_ops; |
2316 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; | |
2317 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA; | |
2318 | ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; | |
2319 | ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; | |
6246b8a1 | 2320 | } else if (IS_QLA83XX(ha)) { |
642ef983 | 2321 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; |
6246b8a1 GM |
2322 | ha->mbx_count = MAILBOX_REGISTER_COUNT; |
2323 | req_length = REQUEST_ENTRY_CNT_24XX; | |
2324 | rsp_length = RESPONSE_ENTRY_CNT_2300; | |
2325 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; | |
2326 | ha->init_cb_size = sizeof(struct mid_init_cb_81xx); | |
2327 | ha->gid_list_info_size = 8; | |
2328 | ha->optrom_size = OPTROM_SIZE_83XX; | |
2329 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; | |
2330 | ha->isp_ops = &qla83xx_isp_ops; | |
2331 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; | |
2332 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; | |
2333 | ha->nvram_conf_off = ~0; | |
2334 | ha->nvram_data_off = ~0; | |
1da177e4 | 2335 | } |
6246b8a1 | 2336 | |
7c3df132 SK |
2337 | ql_dbg_pci(ql_dbg_init, pdev, 0x001e, |
2338 | "mbx_count=%d, req_length=%d, " | |
2339 | "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " | |
642ef983 CD |
2340 | "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " |
2341 | "max_fibre_devices=%d.\n", | |
7c3df132 SK |
2342 | ha->mbx_count, req_length, rsp_length, ha->max_loop_id, |
2343 | ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, | |
642ef983 | 2344 | ha->nvram_npiv_size, ha->max_fibre_devices); |
7c3df132 SK |
2345 | ql_dbg_pci(ql_dbg_init, pdev, 0x001f, |
2346 | "isp_ops=%p, flash_conf_off=%d, " | |
2347 | "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", | |
2348 | ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, | |
2349 | ha->nvram_conf_off, ha->nvram_data_off); | |
706f457d GM |
2350 | |
2351 | /* Configure PCI I/O space */ | |
2352 | ret = ha->isp_ops->iospace_config(ha); | |
2353 | if (ret) | |
2354 | goto probe_hw_failed; | |
2355 | ||
2356 | ql_log_pci(ql_log_info, pdev, 0x001d, | |
2357 | "Found an ISP%04X irq %d iobase 0x%p.\n", | |
2358 | pdev->device, pdev->irq, ha->iobase); | |
6c2f527c | 2359 | mutex_init(&ha->vport_lock); |
0b05a1f0 MB |
2360 | init_completion(&ha->mbx_cmd_comp); |
2361 | complete(&ha->mbx_cmd_comp); | |
2362 | init_completion(&ha->mbx_intr_comp); | |
23f2ebd1 | 2363 | init_completion(&ha->dcbx_comp); |
1da177e4 | 2364 | |
2c3dfe3f | 2365 | set_bit(0, (unsigned long *) ha->vp_idx_map); |
1da177e4 | 2366 | |
53303c42 | 2367 | qla2x00_config_dma_addressing(ha); |
7c3df132 SK |
2368 | ql_dbg_pci(ql_dbg_init, pdev, 0x0020, |
2369 | "64 Bit addressing is %s.\n", | |
2370 | ha->flags.enable_64bit_addressing ? "enable" : | |
2371 | "disable"); | |
73208dfd | 2372 | ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); |
e315cd28 | 2373 | if (!ret) { |
7c3df132 SK |
2374 | ql_log_pci(ql_log_fatal, pdev, 0x0031, |
2375 | "Failed to allocate memory for adapter, aborting.\n"); | |
1da177e4 | 2376 | |
e315cd28 AC |
2377 | goto probe_hw_failed; |
2378 | } | |
2379 | ||
73208dfd | 2380 | req->max_q_depth = MAX_Q_DEPTH; |
e315cd28 | 2381 | if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) |
73208dfd AC |
2382 | req->max_q_depth = ql2xmaxqdepth; |
2383 | ||
e315cd28 AC |
2384 | |
2385 | base_vha = qla2x00_create_host(sht, ha); | |
2386 | if (!base_vha) { | |
a1541d5a | 2387 | ret = -ENOMEM; |
6e9f21f3 | 2388 | qla2x00_mem_free(ha); |
2afa19a9 AC |
2389 | qla2x00_free_req_que(ha, req); |
2390 | qla2x00_free_rsp_que(ha, rsp); | |
e315cd28 | 2391 | goto probe_hw_failed; |
1da177e4 LT |
2392 | } |
2393 | ||
e315cd28 AC |
2394 | pci_set_drvdata(pdev, base_vha); |
2395 | ||
e315cd28 | 2396 | host = base_vha->host; |
2afa19a9 | 2397 | base_vha->req = req; |
73208dfd AC |
2398 | host->can_queue = req->length + 128; |
2399 | if (IS_QLA2XXX_MIDTYPE(ha)) | |
e315cd28 | 2400 | base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx; |
73208dfd | 2401 | else |
e315cd28 AC |
2402 | base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + |
2403 | base_vha->vp_idx; | |
58548cb5 GM |
2404 | |
2405 | /* Set the SG table size based on ISP type */ | |
2406 | if (!IS_FWI2_CAPABLE(ha)) { | |
2407 | if (IS_QLA2100(ha)) | |
2408 | host->sg_tablesize = 32; | |
2409 | } else { | |
2410 | if (!IS_QLA82XX(ha)) | |
2411 | host->sg_tablesize = QLA_SG_ALL; | |
2412 | } | |
7c3df132 SK |
2413 | ql_dbg(ql_dbg_init, base_vha, 0x0032, |
2414 | "can_queue=%d, req=%p, " | |
2415 | "mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", | |
2416 | host->can_queue, base_vha->req, | |
2417 | base_vha->mgmt_svr_loop_id, host->sg_tablesize); | |
642ef983 | 2418 | host->max_id = ha->max_fibre_devices; |
e315cd28 AC |
2419 | host->this_id = 255; |
2420 | host->cmd_per_lun = 3; | |
2421 | host->unique_id = host->host_no; | |
e02587d7 | 2422 | if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) |
0c470874 AE |
2423 | host->max_cmd_len = 32; |
2424 | else | |
2425 | host->max_cmd_len = MAX_CMDSZ; | |
e315cd28 | 2426 | host->max_channel = MAX_BUSES - 1; |
82515920 | 2427 | host->max_lun = ql2xmaxlun; |
e315cd28 | 2428 | host->transportt = qla2xxx_transport_template; |
9a069e19 | 2429 | sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); |
e315cd28 | 2430 | |
7c3df132 SK |
2431 | ql_dbg(ql_dbg_init, base_vha, 0x0033, |
2432 | "max_id=%d this_id=%d " | |
2433 | "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " | |
d8424f68 | 2434 | "max_lun=%d transportt=%p, vendor_id=%llu.\n", host->max_id, |
7c3df132 SK |
2435 | host->this_id, host->cmd_per_lun, host->unique_id, |
2436 | host->max_cmd_len, host->max_channel, host->max_lun, | |
2437 | host->transportt, sht->vendor_id); | |
2438 | ||
9a347ff4 CD |
2439 | que_init: |
2440 | /* Alloc arrays of request and response ring ptrs */ | |
2441 | if (!qla2x00_alloc_queues(ha, req, rsp)) { | |
2442 | ql_log(ql_log_fatal, base_vha, 0x003d, | |
2443 | "Failed to allocate memory for queue pointers..." | |
2444 | "aborting.\n"); | |
2445 | goto probe_init_failed; | |
2446 | } | |
2447 | ||
2d70c103 | 2448 | qlt_probe_one_stage1(base_vha, ha); |
9a347ff4 | 2449 | |
73208dfd AC |
2450 | /* Set up the irqs */ |
2451 | ret = qla2x00_request_irqs(ha, rsp); | |
2452 | if (ret) | |
6e9f21f3 | 2453 | goto probe_init_failed; |
90a86fc0 JC |
2454 | |
2455 | pci_save_state(pdev); | |
2456 | ||
9a347ff4 | 2457 | /* Assign back pointers */ |
2afa19a9 AC |
2458 | rsp->req = req; |
2459 | req->rsp = rsp; | |
9a347ff4 | 2460 | |
08029990 AV |
2461 | /* FWI2-capable only. */ |
2462 | req->req_q_in = &ha->iobase->isp24.req_q_in; | |
2463 | req->req_q_out = &ha->iobase->isp24.req_q_out; | |
2464 | rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; | |
2465 | rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; | |
6246b8a1 | 2466 | if (ha->mqenable || IS_QLA83XX(ha)) { |
08029990 AV |
2467 | req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; |
2468 | req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; | |
2469 | rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; | |
2470 | rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; | |
17d98630 AC |
2471 | } |
2472 | ||
a9083016 GM |
2473 | if (IS_QLA82XX(ha)) { |
2474 | req->req_q_out = &ha->iobase->isp82.req_q_out[0]; | |
2475 | rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; | |
2476 | rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; | |
2477 | } | |
2478 | ||
7c3df132 SK |
2479 | ql_dbg(ql_dbg_multiq, base_vha, 0xc009, |
2480 | "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", | |
2481 | ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); | |
2482 | ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, | |
2483 | "req->req_q_in=%p req->req_q_out=%p " | |
2484 | "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", | |
2485 | req->req_q_in, req->req_q_out, | |
2486 | rsp->rsp_q_in, rsp->rsp_q_out); | |
2487 | ql_dbg(ql_dbg_init, base_vha, 0x003e, | |
2488 | "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", | |
2489 | ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); | |
2490 | ql_dbg(ql_dbg_init, base_vha, 0x003f, | |
2491 | "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", | |
2492 | req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); | |
1da177e4 | 2493 | |
7c3df132 SK |
2494 | if (qla2x00_initialize_adapter(base_vha)) { |
2495 | ql_log(ql_log_fatal, base_vha, 0x00d6, | |
2496 | "Failed to initialize adapter - Adapter flags %x.\n", | |
2497 | base_vha->device_flags); | |
1da177e4 | 2498 | |
a9083016 GM |
2499 | if (IS_QLA82XX(ha)) { |
2500 | qla82xx_idc_lock(ha); | |
2501 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | |
2502 | QLA82XX_DEV_FAILED); | |
2503 | qla82xx_idc_unlock(ha); | |
7c3df132 SK |
2504 | ql_log(ql_log_fatal, base_vha, 0x00d7, |
2505 | "HW State: FAILED.\n"); | |
a9083016 GM |
2506 | } |
2507 | ||
a1541d5a | 2508 | ret = -ENODEV; |
1da177e4 LT |
2509 | goto probe_failed; |
2510 | } | |
2511 | ||
7163ea81 AC |
2512 | if (ha->mqenable) { |
2513 | if (qla25xx_setup_mode(base_vha)) { | |
7c3df132 SK |
2514 | ql_log(ql_log_warn, base_vha, 0x00ec, |
2515 | "Failed to create queues, falling back to single queue mode.\n"); | |
7163ea81 AC |
2516 | goto que_init; |
2517 | } | |
2518 | } | |
68ca949c | 2519 | |
cbc8eb67 AV |
2520 | if (ha->flags.running_gold_fw) |
2521 | goto skip_dpc; | |
2522 | ||
1da177e4 LT |
2523 | /* |
2524 | * Startup the kernel thread for this host adapter | |
2525 | */ | |
39a11240 | 2526 | ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, |
7c3df132 | 2527 | "%s_dpc", base_vha->host_str); |
39a11240 | 2528 | if (IS_ERR(ha->dpc_thread)) { |
7c3df132 SK |
2529 | ql_log(ql_log_fatal, base_vha, 0x00ed, |
2530 | "Failed to start DPC thread.\n"); | |
39a11240 | 2531 | ret = PTR_ERR(ha->dpc_thread); |
1da177e4 LT |
2532 | goto probe_failed; |
2533 | } | |
7c3df132 SK |
2534 | ql_dbg(ql_dbg_init, base_vha, 0x00ee, |
2535 | "DPC thread started successfully.\n"); | |
1da177e4 | 2536 | |
2d70c103 NB |
2537 | /* |
2538 | * If we're not coming up in initiator mode, we might sit for | |
2539 | * a while without waking up the dpc thread, which leads to a | |
2540 | * stuck process warning. So just kick the dpc once here and | |
2541 | * let the kthread start (and go back to sleep in qla2x00_do_dpc). | |
2542 | */ | |
2543 | qla2xxx_wake_dpc(base_vha); | |
2544 | ||
cbc8eb67 | 2545 | skip_dpc: |
e315cd28 AC |
2546 | list_add_tail(&base_vha->list, &ha->vp_list); |
2547 | base_vha->host->irq = ha->pdev->irq; | |
1da177e4 LT |
2548 | |
2549 | /* Initialized the timer */ | |
e315cd28 | 2550 | qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL); |
7c3df132 SK |
2551 | ql_dbg(ql_dbg_init, base_vha, 0x00ef, |
2552 | "Started qla2x00_timer with " | |
2553 | "interval=%d.\n", WATCH_INTERVAL); | |
2554 | ql_dbg(ql_dbg_init, base_vha, 0x00f0, | |
2555 | "Detected hba at address=%p.\n", | |
2556 | ha); | |
d19044c3 | 2557 | |
e02587d7 | 2558 | if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { |
bad75002 | 2559 | if (ha->fw_attributes & BIT_4) { |
8cb2049c | 2560 | int prot = 0; |
bad75002 | 2561 | base_vha->flags.difdix_supported = 1; |
7c3df132 SK |
2562 | ql_dbg(ql_dbg_init, base_vha, 0x00f1, |
2563 | "Registering for DIF/DIX type 1 and 3 protection.\n"); | |
8cb2049c AE |
2564 | if (ql2xenabledif == 1) |
2565 | prot = SHOST_DIX_TYPE0_PROTECTION; | |
bad75002 | 2566 | scsi_host_set_prot(host, |
8cb2049c | 2567 | prot | SHOST_DIF_TYPE1_PROTECTION |
0c470874 | 2568 | | SHOST_DIF_TYPE2_PROTECTION |
bad75002 AE |
2569 | | SHOST_DIF_TYPE3_PROTECTION |
2570 | | SHOST_DIX_TYPE1_PROTECTION | |
0c470874 | 2571 | | SHOST_DIX_TYPE2_PROTECTION |
bad75002 AE |
2572 | | SHOST_DIX_TYPE3_PROTECTION); |
2573 | scsi_host_set_guard(host, SHOST_DIX_GUARD_CRC); | |
2574 | } else | |
2575 | base_vha->flags.difdix_supported = 0; | |
2576 | } | |
2577 | ||
a9083016 GM |
2578 | ha->isp_ops->enable_intrs(ha); |
2579 | ||
a1541d5a AV |
2580 | ret = scsi_add_host(host, &pdev->dev); |
2581 | if (ret) | |
2582 | goto probe_failed; | |
2583 | ||
1486400f MR |
2584 | base_vha->flags.init_done = 1; |
2585 | base_vha->flags.online = 1; | |
2586 | ||
7c3df132 SK |
2587 | ql_dbg(ql_dbg_init, base_vha, 0x00f2, |
2588 | "Init done and hba is online.\n"); | |
2589 | ||
2d70c103 NB |
2590 | if (qla_ini_mode_enabled(base_vha)) |
2591 | scsi_scan_host(host); | |
2592 | else | |
2593 | ql_dbg(ql_dbg_init, base_vha, 0x0122, | |
2594 | "skipping scsi_scan_host() for non-initiator port\n"); | |
1e99e33a | 2595 | |
e315cd28 | 2596 | qla2x00_alloc_sysfs_attr(base_vha); |
a1541d5a | 2597 | |
e315cd28 | 2598 | qla2x00_init_host_attr(base_vha); |
a1541d5a | 2599 | |
e315cd28 | 2600 | qla2x00_dfs_setup(base_vha); |
df613b96 | 2601 | |
7c3df132 SK |
2602 | ql_log(ql_log_info, base_vha, 0x00fb, |
2603 | "QLogic %s - %s.\n", | |
2604 | ha->model_number, ha->model_desc ? ha->model_desc : ""); | |
2605 | ql_log(ql_log_info, base_vha, 0x00fc, | |
2606 | "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", | |
2607 | pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info), | |
2608 | pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', | |
2609 | base_vha->host_no, | |
e315cd28 | 2610 | ha->isp_ops->fw_version_str(base_vha, fw_str)); |
1da177e4 | 2611 | |
2d70c103 NB |
2612 | qlt_add_target(ha, base_vha); |
2613 | ||
1da177e4 LT |
2614 | return 0; |
2615 | ||
6e9f21f3 | 2616 | probe_init_failed: |
2afa19a9 | 2617 | qla2x00_free_req_que(ha, req); |
9a347ff4 CD |
2618 | ha->req_q_map[0] = NULL; |
2619 | clear_bit(0, ha->req_qid_map); | |
2afa19a9 | 2620 | qla2x00_free_rsp_que(ha, rsp); |
9a347ff4 CD |
2621 | ha->rsp_q_map[0] = NULL; |
2622 | clear_bit(0, ha->rsp_qid_map); | |
2afa19a9 | 2623 | ha->max_req_queues = ha->max_rsp_queues = 0; |
6e9f21f3 | 2624 | |
1da177e4 | 2625 | probe_failed: |
b9978769 AV |
2626 | if (base_vha->timer_active) |
2627 | qla2x00_stop_timer(base_vha); | |
2628 | base_vha->flags.online = 0; | |
2629 | if (ha->dpc_thread) { | |
2630 | struct task_struct *t = ha->dpc_thread; | |
2631 | ||
2632 | ha->dpc_thread = NULL; | |
2633 | kthread_stop(t); | |
2634 | } | |
2635 | ||
e315cd28 | 2636 | qla2x00_free_device(base_vha); |
1da177e4 | 2637 | |
e315cd28 | 2638 | scsi_host_put(base_vha->host); |
1da177e4 | 2639 | |
e315cd28 | 2640 | probe_hw_failed: |
a9083016 GM |
2641 | if (IS_QLA82XX(ha)) { |
2642 | qla82xx_idc_lock(ha); | |
2643 | qla82xx_clear_drv_active(ha); | |
2644 | qla82xx_idc_unlock(ha); | |
2645 | iounmap((device_reg_t __iomem *)ha->nx_pcibase); | |
2646 | if (!ql2xdbwr) | |
2647 | iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr); | |
2648 | } else { | |
2649 | if (ha->iobase) | |
2650 | iounmap(ha->iobase); | |
2651 | } | |
e315cd28 AC |
2652 | pci_release_selected_regions(ha->pdev, ha->bars); |
2653 | kfree(ha); | |
2654 | ha = NULL; | |
1da177e4 | 2655 | |
a1541d5a | 2656 | probe_out: |
e315cd28 | 2657 | pci_disable_device(pdev); |
a1541d5a | 2658 | return ret; |
1da177e4 | 2659 | } |
1da177e4 | 2660 | |
2d70c103 NB |
2661 | static void |
2662 | qla2x00_stop_dpc_thread(scsi_qla_host_t *vha) | |
2663 | { | |
2664 | struct qla_hw_data *ha = vha->hw; | |
2665 | struct task_struct *t = ha->dpc_thread; | |
2666 | ||
2667 | if (ha->dpc_thread == NULL) | |
2668 | return; | |
2669 | /* | |
2670 | * qla2xxx_wake_dpc checks for ->dpc_thread | |
2671 | * so we need to zero it out. | |
2672 | */ | |
2673 | ha->dpc_thread = NULL; | |
2674 | kthread_stop(t); | |
2675 | } | |
2676 | ||
e30d1756 MI |
2677 | static void |
2678 | qla2x00_shutdown(struct pci_dev *pdev) | |
2679 | { | |
2680 | scsi_qla_host_t *vha; | |
2681 | struct qla_hw_data *ha; | |
2682 | ||
2683 | vha = pci_get_drvdata(pdev); | |
2684 | ha = vha->hw; | |
2685 | ||
2686 | /* Turn-off FCE trace */ | |
2687 | if (ha->flags.fce_enabled) { | |
2688 | qla2x00_disable_fce_trace(vha, NULL, NULL); | |
2689 | ha->flags.fce_enabled = 0; | |
2690 | } | |
2691 | ||
2692 | /* Turn-off EFT trace */ | |
2693 | if (ha->eft) | |
2694 | qla2x00_disable_eft_trace(vha); | |
2695 | ||
2696 | /* Stop currently executing firmware. */ | |
2697 | qla2x00_try_to_stop_firmware(vha); | |
2698 | ||
2699 | /* Turn adapter off line */ | |
2700 | vha->flags.online = 0; | |
2701 | ||
2702 | /* turn-off interrupts on the card */ | |
2703 | if (ha->interrupts_on) { | |
2704 | vha->flags.init_done = 0; | |
2705 | ha->isp_ops->disable_intrs(ha); | |
2706 | } | |
2707 | ||
2708 | qla2x00_free_irqs(vha); | |
2709 | ||
2710 | qla2x00_free_fw_dump(ha); | |
2711 | } | |
2712 | ||
4c993f76 | 2713 | static void |
7ee61397 | 2714 | qla2x00_remove_one(struct pci_dev *pdev) |
1da177e4 | 2715 | { |
feafb7b1 | 2716 | scsi_qla_host_t *base_vha, *vha; |
e315cd28 | 2717 | struct qla_hw_data *ha; |
feafb7b1 | 2718 | unsigned long flags; |
e315cd28 | 2719 | |
9a347ff4 CD |
2720 | /* |
2721 | * If the PCI device is disabled that means that probe failed and any | |
2722 | * resources should be have cleaned up on probe exit. | |
2723 | */ | |
2724 | if (!atomic_read(&pdev->enable_cnt)) | |
2725 | return; | |
2726 | ||
e315cd28 AC |
2727 | base_vha = pci_get_drvdata(pdev); |
2728 | ha = base_vha->hw; | |
2729 | ||
2d70c103 NB |
2730 | ha->flags.host_shutting_down = 1; |
2731 | ||
43ebf16d AE |
2732 | mutex_lock(&ha->vport_lock); |
2733 | while (ha->cur_vport_count) { | |
2734 | struct Scsi_Host *scsi_host; | |
feafb7b1 | 2735 | |
43ebf16d | 2736 | spin_lock_irqsave(&ha->vport_slock, flags); |
feafb7b1 | 2737 | |
43ebf16d AE |
2738 | BUG_ON(base_vha->list.next == &ha->vp_list); |
2739 | /* This assumes first entry in ha->vp_list is always base vha */ | |
2740 | vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); | |
2741 | scsi_host = scsi_host_get(vha->host); | |
feafb7b1 | 2742 | |
43ebf16d AE |
2743 | spin_unlock_irqrestore(&ha->vport_slock, flags); |
2744 | mutex_unlock(&ha->vport_lock); | |
2745 | ||
2746 | fc_vport_terminate(vha->fc_vport); | |
2747 | scsi_host_put(vha->host); | |
feafb7b1 | 2748 | |
43ebf16d | 2749 | mutex_lock(&ha->vport_lock); |
e315cd28 | 2750 | } |
43ebf16d | 2751 | mutex_unlock(&ha->vport_lock); |
1da177e4 | 2752 | |
e315cd28 | 2753 | set_bit(UNLOADING, &base_vha->dpc_flags); |
1da177e4 | 2754 | |
b9978769 AV |
2755 | qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); |
2756 | ||
e315cd28 | 2757 | qla2x00_dfs_remove(base_vha); |
c795c1e4 | 2758 | |
e315cd28 | 2759 | qla84xx_put_chip(base_vha); |
c795c1e4 | 2760 | |
b9978769 AV |
2761 | /* Disable timer */ |
2762 | if (base_vha->timer_active) | |
2763 | qla2x00_stop_timer(base_vha); | |
2764 | ||
2765 | base_vha->flags.online = 0; | |
2766 | ||
68ca949c AC |
2767 | /* Flush the work queue and remove it */ |
2768 | if (ha->wq) { | |
2769 | flush_workqueue(ha->wq); | |
2770 | destroy_workqueue(ha->wq); | |
2771 | ha->wq = NULL; | |
2772 | } | |
2773 | ||
b9978769 AV |
2774 | /* Kill the kernel thread for this host */ |
2775 | if (ha->dpc_thread) { | |
2776 | struct task_struct *t = ha->dpc_thread; | |
2777 | ||
2778 | /* | |
2779 | * qla2xxx_wake_dpc checks for ->dpc_thread | |
2780 | * so we need to zero it out. | |
2781 | */ | |
2782 | ha->dpc_thread = NULL; | |
2783 | kthread_stop(t); | |
2784 | } | |
2d70c103 | 2785 | qlt_remove_target(ha, base_vha); |
b9978769 | 2786 | |
e315cd28 | 2787 | qla2x00_free_sysfs_attr(base_vha); |
df613b96 | 2788 | |
e315cd28 | 2789 | fc_remove_host(base_vha->host); |
4d4df193 | 2790 | |
e315cd28 | 2791 | scsi_remove_host(base_vha->host); |
1da177e4 | 2792 | |
e315cd28 | 2793 | qla2x00_free_device(base_vha); |
bdf79621 | 2794 | |
e315cd28 | 2795 | scsi_host_put(base_vha->host); |
1da177e4 | 2796 | |
a9083016 | 2797 | if (IS_QLA82XX(ha)) { |
b963752f GM |
2798 | qla82xx_idc_lock(ha); |
2799 | qla82xx_clear_drv_active(ha); | |
2800 | qla82xx_idc_unlock(ha); | |
2801 | ||
a9083016 GM |
2802 | iounmap((device_reg_t __iomem *)ha->nx_pcibase); |
2803 | if (!ql2xdbwr) | |
2804 | iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr); | |
2805 | } else { | |
2806 | if (ha->iobase) | |
2807 | iounmap(ha->iobase); | |
1da177e4 | 2808 | |
a9083016 GM |
2809 | if (ha->mqiobase) |
2810 | iounmap(ha->mqiobase); | |
6246b8a1 GM |
2811 | |
2812 | if (IS_QLA83XX(ha) && ha->msixbase) | |
2813 | iounmap(ha->msixbase); | |
a9083016 | 2814 | } |
73208dfd | 2815 | |
e315cd28 AC |
2816 | pci_release_selected_regions(ha->pdev, ha->bars); |
2817 | kfree(ha); | |
2818 | ha = NULL; | |
1da177e4 | 2819 | |
90a86fc0 JC |
2820 | pci_disable_pcie_error_reporting(pdev); |
2821 | ||
665db93b | 2822 | pci_disable_device(pdev); |
1da177e4 LT |
2823 | pci_set_drvdata(pdev, NULL); |
2824 | } | |
1da177e4 LT |
2825 | |
2826 | static void | |
e315cd28 | 2827 | qla2x00_free_device(scsi_qla_host_t *vha) |
1da177e4 | 2828 | { |
e315cd28 | 2829 | struct qla_hw_data *ha = vha->hw; |
1da177e4 | 2830 | |
85880801 AV |
2831 | qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); |
2832 | ||
2833 | /* Disable timer */ | |
2834 | if (vha->timer_active) | |
2835 | qla2x00_stop_timer(vha); | |
2836 | ||
2d70c103 | 2837 | qla2x00_stop_dpc_thread(vha); |
85880801 | 2838 | |
2afa19a9 AC |
2839 | qla25xx_delete_queues(vha); |
2840 | ||
df613b96 | 2841 | if (ha->flags.fce_enabled) |
e315cd28 | 2842 | qla2x00_disable_fce_trace(vha, NULL, NULL); |
df613b96 | 2843 | |
a7a167bf | 2844 | if (ha->eft) |
e315cd28 | 2845 | qla2x00_disable_eft_trace(vha); |
a7a167bf | 2846 | |
f6ef3b18 | 2847 | /* Stop currently executing firmware. */ |
e315cd28 | 2848 | qla2x00_try_to_stop_firmware(vha); |
1da177e4 | 2849 | |
85880801 AV |
2850 | vha->flags.online = 0; |
2851 | ||
f6ef3b18 | 2852 | /* turn-off interrupts on the card */ |
a9083016 GM |
2853 | if (ha->interrupts_on) { |
2854 | vha->flags.init_done = 0; | |
fd34f556 | 2855 | ha->isp_ops->disable_intrs(ha); |
a9083016 | 2856 | } |
f6ef3b18 | 2857 | |
e315cd28 | 2858 | qla2x00_free_irqs(vha); |
1da177e4 | 2859 | |
8867048b CD |
2860 | qla2x00_free_fcports(vha); |
2861 | ||
e315cd28 | 2862 | qla2x00_mem_free(ha); |
73208dfd | 2863 | |
08de2844 GM |
2864 | qla82xx_md_free(vha); |
2865 | ||
73208dfd | 2866 | qla2x00_free_queues(ha); |
1da177e4 LT |
2867 | } |
2868 | ||
8867048b CD |
2869 | void qla2x00_free_fcports(struct scsi_qla_host *vha) |
2870 | { | |
2871 | fc_port_t *fcport, *tfcport; | |
2872 | ||
2873 | list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) { | |
2874 | list_del(&fcport->list); | |
2875 | kfree(fcport); | |
2876 | fcport = NULL; | |
2877 | } | |
2878 | } | |
2879 | ||
d97994dc | 2880 | static inline void |
e315cd28 | 2881 | qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport, |
d97994dc | 2882 | int defer) |
2883 | { | |
d97994dc | 2884 | struct fc_rport *rport; |
67becc00 | 2885 | scsi_qla_host_t *base_vha; |
044d78e1 | 2886 | unsigned long flags; |
d97994dc | 2887 | |
2888 | if (!fcport->rport) | |
2889 | return; | |
2890 | ||
2891 | rport = fcport->rport; | |
2892 | if (defer) { | |
67becc00 | 2893 | base_vha = pci_get_drvdata(vha->hw->pdev); |
044d78e1 | 2894 | spin_lock_irqsave(vha->host->host_lock, flags); |
d97994dc | 2895 | fcport->drport = rport; |
044d78e1 | 2896 | spin_unlock_irqrestore(vha->host->host_lock, flags); |
67becc00 AV |
2897 | set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); |
2898 | qla2xxx_wake_dpc(base_vha); | |
2d70c103 | 2899 | } else { |
d97994dc | 2900 | fc_remote_port_delete(rport); |
2d70c103 NB |
2901 | qlt_fc_port_deleted(vha, fcport); |
2902 | } | |
d97994dc | 2903 | } |
2904 | ||
1da177e4 LT |
2905 | /* |
2906 | * qla2x00_mark_device_lost Updates fcport state when device goes offline. | |
2907 | * | |
2908 | * Input: ha = adapter block pointer. fcport = port structure pointer. | |
2909 | * | |
2910 | * Return: None. | |
2911 | * | |
2912 | * Context: | |
2913 | */ | |
e315cd28 | 2914 | void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, |
d97994dc | 2915 | int do_login, int defer) |
1da177e4 | 2916 | { |
2c3dfe3f | 2917 | if (atomic_read(&fcport->state) == FCS_ONLINE && |
c6d39e23 | 2918 | vha->vp_idx == fcport->vha->vp_idx) { |
ec426e10 | 2919 | qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); |
e315cd28 AC |
2920 | qla2x00_schedule_rport_del(vha, fcport, defer); |
2921 | } | |
fa2a1ce5 | 2922 | /* |
1da177e4 LT |
2923 | * We may need to retry the login, so don't change the state of the |
2924 | * port but do the retries. | |
2925 | */ | |
2926 | if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) | |
ec426e10 | 2927 | qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); |
1da177e4 LT |
2928 | |
2929 | if (!do_login) | |
2930 | return; | |
2931 | ||
2932 | if (fcport->login_retry == 0) { | |
e315cd28 AC |
2933 | fcport->login_retry = vha->hw->login_retry_count; |
2934 | set_bit(RELOGIN_NEEDED, &vha->dpc_flags); | |
1da177e4 | 2935 | |
7c3df132 SK |
2936 | ql_dbg(ql_dbg_disc, vha, 0x2067, |
2937 | "Port login retry " | |
1da177e4 | 2938 | "%02x%02x%02x%02x%02x%02x%02x%02x, " |
7c3df132 SK |
2939 | "id = 0x%04x retry cnt=%d.\n", |
2940 | fcport->port_name[0], fcport->port_name[1], | |
2941 | fcport->port_name[2], fcport->port_name[3], | |
2942 | fcport->port_name[4], fcport->port_name[5], | |
2943 | fcport->port_name[6], fcport->port_name[7], | |
2944 | fcport->loop_id, fcport->login_retry); | |
1da177e4 LT |
2945 | } |
2946 | } | |
2947 | ||
2948 | /* | |
2949 | * qla2x00_mark_all_devices_lost | |
2950 | * Updates fcport state when device goes offline. | |
2951 | * | |
2952 | * Input: | |
2953 | * ha = adapter block pointer. | |
2954 | * fcport = port structure pointer. | |
2955 | * | |
2956 | * Return: | |
2957 | * None. | |
2958 | * | |
2959 | * Context: | |
2960 | */ | |
2961 | void | |
e315cd28 | 2962 | qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer) |
1da177e4 LT |
2963 | { |
2964 | fc_port_t *fcport; | |
2965 | ||
e315cd28 | 2966 | list_for_each_entry(fcport, &vha->vp_fcports, list) { |
c6d39e23 | 2967 | if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx) |
1da177e4 | 2968 | continue; |
0d6e61bc | 2969 | |
1da177e4 LT |
2970 | /* |
2971 | * No point in marking the device as lost, if the device is | |
2972 | * already DEAD. | |
2973 | */ | |
2974 | if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD) | |
2975 | continue; | |
e315cd28 | 2976 | if (atomic_read(&fcport->state) == FCS_ONLINE) { |
ec426e10 | 2977 | qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); |
0d6e61bc AV |
2978 | if (defer) |
2979 | qla2x00_schedule_rport_del(vha, fcport, defer); | |
c6d39e23 | 2980 | else if (vha->vp_idx == fcport->vha->vp_idx) |
0d6e61bc AV |
2981 | qla2x00_schedule_rport_del(vha, fcport, defer); |
2982 | } | |
1da177e4 LT |
2983 | } |
2984 | } | |
2985 | ||
2986 | /* | |
2987 | * qla2x00_mem_alloc | |
2988 | * Allocates adapter memory. | |
2989 | * | |
2990 | * Returns: | |
2991 | * 0 = success. | |
e8711085 | 2992 | * !0 = failure. |
1da177e4 | 2993 | */ |
e8711085 | 2994 | static int |
73208dfd AC |
2995 | qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, |
2996 | struct req_que **req, struct rsp_que **rsp) | |
1da177e4 LT |
2997 | { |
2998 | char name[16]; | |
1da177e4 | 2999 | |
e8711085 | 3000 | ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, |
e315cd28 | 3001 | &ha->init_cb_dma, GFP_KERNEL); |
e8711085 | 3002 | if (!ha->init_cb) |
e315cd28 | 3003 | goto fail; |
e8711085 | 3004 | |
2d70c103 NB |
3005 | if (qlt_mem_alloc(ha) < 0) |
3006 | goto fail_free_init_cb; | |
3007 | ||
642ef983 CD |
3008 | ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, |
3009 | qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); | |
e315cd28 | 3010 | if (!ha->gid_list) |
2d70c103 | 3011 | goto fail_free_tgt_mem; |
1da177e4 | 3012 | |
e8711085 AV |
3013 | ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); |
3014 | if (!ha->srb_mempool) | |
e315cd28 | 3015 | goto fail_free_gid_list; |
e8711085 | 3016 | |
a9083016 GM |
3017 | if (IS_QLA82XX(ha)) { |
3018 | /* Allocate cache for CT6 Ctx. */ | |
3019 | if (!ctx_cachep) { | |
3020 | ctx_cachep = kmem_cache_create("qla2xxx_ctx", | |
3021 | sizeof(struct ct6_dsd), 0, | |
3022 | SLAB_HWCACHE_ALIGN, NULL); | |
3023 | if (!ctx_cachep) | |
3024 | goto fail_free_gid_list; | |
3025 | } | |
3026 | ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, | |
3027 | ctx_cachep); | |
3028 | if (!ha->ctx_mempool) | |
3029 | goto fail_free_srb_mempool; | |
7c3df132 SK |
3030 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, |
3031 | "ctx_cachep=%p ctx_mempool=%p.\n", | |
3032 | ctx_cachep, ha->ctx_mempool); | |
a9083016 GM |
3033 | } |
3034 | ||
e8711085 AV |
3035 | /* Get memory for cached NVRAM */ |
3036 | ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); | |
3037 | if (!ha->nvram) | |
a9083016 | 3038 | goto fail_free_ctx_mempool; |
e8711085 | 3039 | |
e315cd28 AC |
3040 | snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, |
3041 | ha->pdev->device); | |
3042 | ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, | |
3043 | DMA_POOL_SIZE, 8, 0); | |
3044 | if (!ha->s_dma_pool) | |
3045 | goto fail_free_nvram; | |
3046 | ||
7c3df132 SK |
3047 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, |
3048 | "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", | |
3049 | ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); | |
3050 | ||
bad75002 | 3051 | if (IS_QLA82XX(ha) || ql2xenabledif) { |
a9083016 GM |
3052 | ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, |
3053 | DSD_LIST_DMA_POOL_SIZE, 8, 0); | |
3054 | if (!ha->dl_dma_pool) { | |
7c3df132 SK |
3055 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, |
3056 | "Failed to allocate memory for dl_dma_pool.\n"); | |
a9083016 GM |
3057 | goto fail_s_dma_pool; |
3058 | } | |
3059 | ||
3060 | ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, | |
3061 | FCP_CMND_DMA_POOL_SIZE, 8, 0); | |
3062 | if (!ha->fcp_cmnd_dma_pool) { | |
7c3df132 SK |
3063 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, |
3064 | "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); | |
a9083016 GM |
3065 | goto fail_dl_dma_pool; |
3066 | } | |
7c3df132 SK |
3067 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, |
3068 | "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n", | |
3069 | ha->dl_dma_pool, ha->fcp_cmnd_dma_pool); | |
a9083016 GM |
3070 | } |
3071 | ||
e8711085 AV |
3072 | /* Allocate memory for SNS commands */ |
3073 | if (IS_QLA2100(ha) || IS_QLA2200(ha)) { | |
e315cd28 | 3074 | /* Get consistent memory allocated for SNS commands */ |
e8711085 | 3075 | ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, |
e315cd28 | 3076 | sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); |
e8711085 | 3077 | if (!ha->sns_cmd) |
e315cd28 | 3078 | goto fail_dma_pool; |
7c3df132 | 3079 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, |
d8424f68 | 3080 | "sns_cmd: %p.\n", ha->sns_cmd); |
e8711085 | 3081 | } else { |
e315cd28 | 3082 | /* Get consistent memory allocated for MS IOCB */ |
e8711085 | 3083 | ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, |
e315cd28 | 3084 | &ha->ms_iocb_dma); |
e8711085 | 3085 | if (!ha->ms_iocb) |
e315cd28 AC |
3086 | goto fail_dma_pool; |
3087 | /* Get consistent memory allocated for CT SNS commands */ | |
e8711085 | 3088 | ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, |
e315cd28 | 3089 | sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); |
e8711085 AV |
3090 | if (!ha->ct_sns) |
3091 | goto fail_free_ms_iocb; | |
7c3df132 SK |
3092 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, |
3093 | "ms_iocb=%p ct_sns=%p.\n", | |
3094 | ha->ms_iocb, ha->ct_sns); | |
1da177e4 LT |
3095 | } |
3096 | ||
e315cd28 | 3097 | /* Allocate memory for request ring */ |
73208dfd AC |
3098 | *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); |
3099 | if (!*req) { | |
7c3df132 SK |
3100 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, |
3101 | "Failed to allocate memory for req.\n"); | |
e315cd28 AC |
3102 | goto fail_req; |
3103 | } | |
73208dfd AC |
3104 | (*req)->length = req_len; |
3105 | (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, | |
3106 | ((*req)->length + 1) * sizeof(request_t), | |
3107 | &(*req)->dma, GFP_KERNEL); | |
3108 | if (!(*req)->ring) { | |
7c3df132 SK |
3109 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, |
3110 | "Failed to allocate memory for req_ring.\n"); | |
e315cd28 AC |
3111 | goto fail_req_ring; |
3112 | } | |
3113 | /* Allocate memory for response ring */ | |
73208dfd AC |
3114 | *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); |
3115 | if (!*rsp) { | |
7c3df132 SK |
3116 | ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, |
3117 | "Failed to allocate memory for rsp.\n"); | |
e315cd28 AC |
3118 | goto fail_rsp; |
3119 | } | |
73208dfd AC |
3120 | (*rsp)->hw = ha; |
3121 | (*rsp)->length = rsp_len; | |
3122 | (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, | |
3123 | ((*rsp)->length + 1) * sizeof(response_t), | |
3124 | &(*rsp)->dma, GFP_KERNEL); | |
3125 | if (!(*rsp)->ring) { | |
7c3df132 SK |
3126 | ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, |
3127 | "Failed to allocate memory for rsp_ring.\n"); | |
e315cd28 AC |
3128 | goto fail_rsp_ring; |
3129 | } | |
73208dfd AC |
3130 | (*req)->rsp = *rsp; |
3131 | (*rsp)->req = *req; | |
7c3df132 SK |
3132 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, |
3133 | "req=%p req->length=%d req->ring=%p rsp=%p " | |
3134 | "rsp->length=%d rsp->ring=%p.\n", | |
3135 | *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, | |
3136 | (*rsp)->ring); | |
73208dfd AC |
3137 | /* Allocate memory for NVRAM data for vports */ |
3138 | if (ha->nvram_npiv_size) { | |
3139 | ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) * | |
7c3df132 | 3140 | ha->nvram_npiv_size, GFP_KERNEL); |
73208dfd | 3141 | if (!ha->npiv_info) { |
7c3df132 SK |
3142 | ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, |
3143 | "Failed to allocate memory for npiv_info.\n"); | |
73208dfd AC |
3144 | goto fail_npiv_info; |
3145 | } | |
3146 | } else | |
3147 | ha->npiv_info = NULL; | |
e8711085 | 3148 | |
b64b0e8f | 3149 | /* Get consistent memory allocated for EX-INIT-CB. */ |
6246b8a1 | 3150 | if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) { |
b64b0e8f AV |
3151 | ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, |
3152 | &ha->ex_init_cb_dma); | |
3153 | if (!ha->ex_init_cb) | |
3154 | goto fail_ex_init_cb; | |
7c3df132 SK |
3155 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, |
3156 | "ex_init_cb=%p.\n", ha->ex_init_cb); | |
b64b0e8f AV |
3157 | } |
3158 | ||
a9083016 GM |
3159 | INIT_LIST_HEAD(&ha->gbl_dsd_list); |
3160 | ||
5ff1d584 AV |
3161 | /* Get consistent memory allocated for Async Port-Database. */ |
3162 | if (!IS_FWI2_CAPABLE(ha)) { | |
3163 | ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, | |
3164 | &ha->async_pd_dma); | |
3165 | if (!ha->async_pd) | |
3166 | goto fail_async_pd; | |
7c3df132 SK |
3167 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, |
3168 | "async_pd=%p.\n", ha->async_pd); | |
5ff1d584 AV |
3169 | } |
3170 | ||
e315cd28 AC |
3171 | INIT_LIST_HEAD(&ha->vp_list); |
3172 | return 1; | |
3173 | ||
5ff1d584 AV |
3174 | fail_async_pd: |
3175 | dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); | |
b64b0e8f AV |
3176 | fail_ex_init_cb: |
3177 | kfree(ha->npiv_info); | |
73208dfd AC |
3178 | fail_npiv_info: |
3179 | dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * | |
3180 | sizeof(response_t), (*rsp)->ring, (*rsp)->dma); | |
3181 | (*rsp)->ring = NULL; | |
3182 | (*rsp)->dma = 0; | |
e315cd28 | 3183 | fail_rsp_ring: |
73208dfd | 3184 | kfree(*rsp); |
e315cd28 | 3185 | fail_rsp: |
73208dfd AC |
3186 | dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * |
3187 | sizeof(request_t), (*req)->ring, (*req)->dma); | |
3188 | (*req)->ring = NULL; | |
3189 | (*req)->dma = 0; | |
e315cd28 | 3190 | fail_req_ring: |
73208dfd | 3191 | kfree(*req); |
e315cd28 AC |
3192 | fail_req: |
3193 | dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), | |
3194 | ha->ct_sns, ha->ct_sns_dma); | |
3195 | ha->ct_sns = NULL; | |
3196 | ha->ct_sns_dma = 0; | |
e8711085 AV |
3197 | fail_free_ms_iocb: |
3198 | dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); | |
3199 | ha->ms_iocb = NULL; | |
3200 | ha->ms_iocb_dma = 0; | |
e315cd28 | 3201 | fail_dma_pool: |
bad75002 | 3202 | if (IS_QLA82XX(ha) || ql2xenabledif) { |
a9083016 GM |
3203 | dma_pool_destroy(ha->fcp_cmnd_dma_pool); |
3204 | ha->fcp_cmnd_dma_pool = NULL; | |
3205 | } | |
3206 | fail_dl_dma_pool: | |
bad75002 | 3207 | if (IS_QLA82XX(ha) || ql2xenabledif) { |
a9083016 GM |
3208 | dma_pool_destroy(ha->dl_dma_pool); |
3209 | ha->dl_dma_pool = NULL; | |
3210 | } | |
3211 | fail_s_dma_pool: | |
e315cd28 AC |
3212 | dma_pool_destroy(ha->s_dma_pool); |
3213 | ha->s_dma_pool = NULL; | |
e8711085 AV |
3214 | fail_free_nvram: |
3215 | kfree(ha->nvram); | |
3216 | ha->nvram = NULL; | |
a9083016 GM |
3217 | fail_free_ctx_mempool: |
3218 | mempool_destroy(ha->ctx_mempool); | |
3219 | ha->ctx_mempool = NULL; | |
e8711085 AV |
3220 | fail_free_srb_mempool: |
3221 | mempool_destroy(ha->srb_mempool); | |
3222 | ha->srb_mempool = NULL; | |
e8711085 | 3223 | fail_free_gid_list: |
642ef983 CD |
3224 | dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), |
3225 | ha->gid_list, | |
e315cd28 | 3226 | ha->gid_list_dma); |
e8711085 AV |
3227 | ha->gid_list = NULL; |
3228 | ha->gid_list_dma = 0; | |
2d70c103 NB |
3229 | fail_free_tgt_mem: |
3230 | qlt_mem_free(ha); | |
e315cd28 AC |
3231 | fail_free_init_cb: |
3232 | dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, | |
3233 | ha->init_cb_dma); | |
3234 | ha->init_cb = NULL; | |
3235 | ha->init_cb_dma = 0; | |
e8711085 | 3236 | fail: |
7c3df132 SK |
3237 | ql_log(ql_log_fatal, NULL, 0x0030, |
3238 | "Memory allocation failure.\n"); | |
e8711085 | 3239 | return -ENOMEM; |
1da177e4 LT |
3240 | } |
3241 | ||
3242 | /* | |
e30d1756 MI |
3243 | * qla2x00_free_fw_dump |
3244 | * Frees fw dump stuff. | |
1da177e4 LT |
3245 | * |
3246 | * Input: | |
e30d1756 | 3247 | * ha = adapter block pointer. |
1da177e4 | 3248 | */ |
a824ebb3 | 3249 | static void |
e30d1756 | 3250 | qla2x00_free_fw_dump(struct qla_hw_data *ha) |
1da177e4 | 3251 | { |
df613b96 AV |
3252 | if (ha->fce) |
3253 | dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce, | |
e30d1756 | 3254 | ha->fce_dma); |
df613b96 | 3255 | |
a7a167bf AV |
3256 | if (ha->fw_dump) { |
3257 | if (ha->eft) | |
3258 | dma_free_coherent(&ha->pdev->dev, | |
e30d1756 | 3259 | ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma); |
a7a167bf AV |
3260 | vfree(ha->fw_dump); |
3261 | } | |
e30d1756 MI |
3262 | ha->fce = NULL; |
3263 | ha->fce_dma = 0; | |
3264 | ha->eft = NULL; | |
3265 | ha->eft_dma = 0; | |
3266 | ha->fw_dump = NULL; | |
3267 | ha->fw_dumped = 0; | |
3268 | ha->fw_dump_reading = 0; | |
3269 | } | |
3270 | ||
3271 | /* | |
3272 | * qla2x00_mem_free | |
3273 | * Frees all adapter allocated memory. | |
3274 | * | |
3275 | * Input: | |
3276 | * ha = adapter block pointer. | |
3277 | */ | |
3278 | static void | |
3279 | qla2x00_mem_free(struct qla_hw_data *ha) | |
3280 | { | |
3281 | qla2x00_free_fw_dump(ha); | |
3282 | ||
3283 | if (ha->srb_mempool) | |
3284 | mempool_destroy(ha->srb_mempool); | |
a7a167bf | 3285 | |
11bbc1d8 AV |
3286 | if (ha->dcbx_tlv) |
3287 | dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, | |
3288 | ha->dcbx_tlv, ha->dcbx_tlv_dma); | |
3289 | ||
ce0423f4 AV |
3290 | if (ha->xgmac_data) |
3291 | dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, | |
3292 | ha->xgmac_data, ha->xgmac_data_dma); | |
3293 | ||
1da177e4 LT |
3294 | if (ha->sns_cmd) |
3295 | dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), | |
e315cd28 | 3296 | ha->sns_cmd, ha->sns_cmd_dma); |
1da177e4 LT |
3297 | |
3298 | if (ha->ct_sns) | |
3299 | dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), | |
e315cd28 | 3300 | ha->ct_sns, ha->ct_sns_dma); |
1da177e4 | 3301 | |
88729e53 AV |
3302 | if (ha->sfp_data) |
3303 | dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma); | |
3304 | ||
1da177e4 LT |
3305 | if (ha->ms_iocb) |
3306 | dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); | |
3307 | ||
b64b0e8f | 3308 | if (ha->ex_init_cb) |
a9083016 GM |
3309 | dma_pool_free(ha->s_dma_pool, |
3310 | ha->ex_init_cb, ha->ex_init_cb_dma); | |
b64b0e8f | 3311 | |
5ff1d584 AV |
3312 | if (ha->async_pd) |
3313 | dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); | |
3314 | ||
1da177e4 LT |
3315 | if (ha->s_dma_pool) |
3316 | dma_pool_destroy(ha->s_dma_pool); | |
3317 | ||
1da177e4 | 3318 | if (ha->gid_list) |
642ef983 CD |
3319 | dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), |
3320 | ha->gid_list, ha->gid_list_dma); | |
1da177e4 | 3321 | |
a9083016 GM |
3322 | if (IS_QLA82XX(ha)) { |
3323 | if (!list_empty(&ha->gbl_dsd_list)) { | |
3324 | struct dsd_dma *dsd_ptr, *tdsd_ptr; | |
3325 | ||
3326 | /* clean up allocated prev pool */ | |
3327 | list_for_each_entry_safe(dsd_ptr, | |
3328 | tdsd_ptr, &ha->gbl_dsd_list, list) { | |
3329 | dma_pool_free(ha->dl_dma_pool, | |
3330 | dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); | |
3331 | list_del(&dsd_ptr->list); | |
3332 | kfree(dsd_ptr); | |
3333 | } | |
3334 | } | |
3335 | } | |
3336 | ||
3337 | if (ha->dl_dma_pool) | |
3338 | dma_pool_destroy(ha->dl_dma_pool); | |
3339 | ||
3340 | if (ha->fcp_cmnd_dma_pool) | |
3341 | dma_pool_destroy(ha->fcp_cmnd_dma_pool); | |
3342 | ||
3343 | if (ha->ctx_mempool) | |
3344 | mempool_destroy(ha->ctx_mempool); | |
3345 | ||
2d70c103 NB |
3346 | qlt_mem_free(ha); |
3347 | ||
e315cd28 AC |
3348 | if (ha->init_cb) |
3349 | dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, | |
a9083016 | 3350 | ha->init_cb, ha->init_cb_dma); |
e315cd28 AC |
3351 | vfree(ha->optrom_buffer); |
3352 | kfree(ha->nvram); | |
73208dfd | 3353 | kfree(ha->npiv_info); |
7a67735b | 3354 | kfree(ha->swl); |
1da177e4 | 3355 | |
e8711085 | 3356 | ha->srb_mempool = NULL; |
a9083016 | 3357 | ha->ctx_mempool = NULL; |
1da177e4 LT |
3358 | ha->sns_cmd = NULL; |
3359 | ha->sns_cmd_dma = 0; | |
3360 | ha->ct_sns = NULL; | |
3361 | ha->ct_sns_dma = 0; | |
3362 | ha->ms_iocb = NULL; | |
3363 | ha->ms_iocb_dma = 0; | |
1da177e4 LT |
3364 | ha->init_cb = NULL; |
3365 | ha->init_cb_dma = 0; | |
b64b0e8f AV |
3366 | ha->ex_init_cb = NULL; |
3367 | ha->ex_init_cb_dma = 0; | |
5ff1d584 AV |
3368 | ha->async_pd = NULL; |
3369 | ha->async_pd_dma = 0; | |
1da177e4 LT |
3370 | |
3371 | ha->s_dma_pool = NULL; | |
a9083016 GM |
3372 | ha->dl_dma_pool = NULL; |
3373 | ha->fcp_cmnd_dma_pool = NULL; | |
1da177e4 | 3374 | |
1da177e4 LT |
3375 | ha->gid_list = NULL; |
3376 | ha->gid_list_dma = 0; | |
2d70c103 NB |
3377 | |
3378 | ha->tgt.atio_ring = NULL; | |
3379 | ha->tgt.atio_dma = 0; | |
3380 | ha->tgt.tgt_vp_map = NULL; | |
e315cd28 | 3381 | } |
1da177e4 | 3382 | |
e315cd28 AC |
3383 | struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, |
3384 | struct qla_hw_data *ha) | |
3385 | { | |
3386 | struct Scsi_Host *host; | |
3387 | struct scsi_qla_host *vha = NULL; | |
854165f4 | 3388 | |
e315cd28 AC |
3389 | host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); |
3390 | if (host == NULL) { | |
7c3df132 SK |
3391 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, |
3392 | "Failed to allocate host from the scsi layer, aborting.\n"); | |
e315cd28 AC |
3393 | goto fail; |
3394 | } | |
3395 | ||
3396 | /* Clear our data area */ | |
3397 | vha = shost_priv(host); | |
3398 | memset(vha, 0, sizeof(scsi_qla_host_t)); | |
3399 | ||
3400 | vha->host = host; | |
3401 | vha->host_no = host->host_no; | |
3402 | vha->hw = ha; | |
3403 | ||
3404 | INIT_LIST_HEAD(&vha->vp_fcports); | |
3405 | INIT_LIST_HEAD(&vha->work_list); | |
3406 | INIT_LIST_HEAD(&vha->list); | |
3407 | ||
f999f4c1 AV |
3408 | spin_lock_init(&vha->work_lock); |
3409 | ||
e315cd28 | 3410 | sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); |
7c3df132 SK |
3411 | ql_dbg(ql_dbg_init, vha, 0x0041, |
3412 | "Allocated the host=%p hw=%p vha=%p dev_name=%s", | |
3413 | vha->host, vha->hw, vha, | |
3414 | dev_name(&(ha->pdev->dev))); | |
3415 | ||
e315cd28 AC |
3416 | return vha; |
3417 | ||
3418 | fail: | |
3419 | return vha; | |
1da177e4 LT |
3420 | } |
3421 | ||
01ef66bb | 3422 | static struct qla_work_evt * |
f999f4c1 | 3423 | qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) |
0971de7f AV |
3424 | { |
3425 | struct qla_work_evt *e; | |
feafb7b1 AE |
3426 | uint8_t bail; |
3427 | ||
3428 | QLA_VHA_MARK_BUSY(vha, bail); | |
3429 | if (bail) | |
3430 | return NULL; | |
0971de7f | 3431 | |
f999f4c1 | 3432 | e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); |
feafb7b1 AE |
3433 | if (!e) { |
3434 | QLA_VHA_MARK_NOT_BUSY(vha); | |
0971de7f | 3435 | return NULL; |
feafb7b1 | 3436 | } |
0971de7f AV |
3437 | |
3438 | INIT_LIST_HEAD(&e->list); | |
3439 | e->type = type; | |
3440 | e->flags = QLA_EVT_FLAG_FREE; | |
3441 | return e; | |
3442 | } | |
3443 | ||
01ef66bb | 3444 | static int |
f999f4c1 | 3445 | qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) |
0971de7f | 3446 | { |
f999f4c1 | 3447 | unsigned long flags; |
0971de7f | 3448 | |
f999f4c1 | 3449 | spin_lock_irqsave(&vha->work_lock, flags); |
e315cd28 | 3450 | list_add_tail(&e->list, &vha->work_list); |
f999f4c1 | 3451 | spin_unlock_irqrestore(&vha->work_lock, flags); |
e315cd28 | 3452 | qla2xxx_wake_dpc(vha); |
f999f4c1 | 3453 | |
0971de7f AV |
3454 | return QLA_SUCCESS; |
3455 | } | |
3456 | ||
3457 | int | |
e315cd28 | 3458 | qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, |
0971de7f AV |
3459 | u32 data) |
3460 | { | |
3461 | struct qla_work_evt *e; | |
3462 | ||
f999f4c1 | 3463 | e = qla2x00_alloc_work(vha, QLA_EVT_AEN); |
0971de7f AV |
3464 | if (!e) |
3465 | return QLA_FUNCTION_FAILED; | |
3466 | ||
3467 | e->u.aen.code = code; | |
3468 | e->u.aen.data = data; | |
f999f4c1 | 3469 | return qla2x00_post_work(vha, e); |
0971de7f AV |
3470 | } |
3471 | ||
8a659571 AV |
3472 | int |
3473 | qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) | |
3474 | { | |
3475 | struct qla_work_evt *e; | |
3476 | ||
f999f4c1 | 3477 | e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); |
8a659571 AV |
3478 | if (!e) |
3479 | return QLA_FUNCTION_FAILED; | |
3480 | ||
3481 | memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); | |
f999f4c1 | 3482 | return qla2x00_post_work(vha, e); |
8a659571 AV |
3483 | } |
3484 | ||
ac280b67 AV |
3485 | #define qla2x00_post_async_work(name, type) \ |
3486 | int qla2x00_post_async_##name##_work( \ | |
3487 | struct scsi_qla_host *vha, \ | |
3488 | fc_port_t *fcport, uint16_t *data) \ | |
3489 | { \ | |
3490 | struct qla_work_evt *e; \ | |
3491 | \ | |
3492 | e = qla2x00_alloc_work(vha, type); \ | |
3493 | if (!e) \ | |
3494 | return QLA_FUNCTION_FAILED; \ | |
3495 | \ | |
3496 | e->u.logio.fcport = fcport; \ | |
3497 | if (data) { \ | |
3498 | e->u.logio.data[0] = data[0]; \ | |
3499 | e->u.logio.data[1] = data[1]; \ | |
3500 | } \ | |
3501 | return qla2x00_post_work(vha, e); \ | |
3502 | } | |
3503 | ||
3504 | qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); | |
3505 | qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE); | |
3506 | qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); | |
3507 | qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE); | |
5ff1d584 AV |
3508 | qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); |
3509 | qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE); | |
ac280b67 | 3510 | |
3420d36c AV |
3511 | int |
3512 | qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) | |
3513 | { | |
3514 | struct qla_work_evt *e; | |
3515 | ||
3516 | e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); | |
3517 | if (!e) | |
3518 | return QLA_FUNCTION_FAILED; | |
3519 | ||
3520 | e->u.uevent.code = code; | |
3521 | return qla2x00_post_work(vha, e); | |
3522 | } | |
3523 | ||
3524 | static void | |
3525 | qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) | |
3526 | { | |
3527 | char event_string[40]; | |
3528 | char *envp[] = { event_string, NULL }; | |
3529 | ||
3530 | switch (code) { | |
3531 | case QLA_UEVENT_CODE_FW_DUMP: | |
3532 | snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", | |
3533 | vha->host_no); | |
3534 | break; | |
3535 | default: | |
3536 | /* do nothing */ | |
3537 | break; | |
3538 | } | |
3539 | kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); | |
3540 | } | |
3541 | ||
ac280b67 | 3542 | void |
e315cd28 | 3543 | qla2x00_do_work(struct scsi_qla_host *vha) |
0971de7f | 3544 | { |
f999f4c1 AV |
3545 | struct qla_work_evt *e, *tmp; |
3546 | unsigned long flags; | |
3547 | LIST_HEAD(work); | |
0971de7f | 3548 | |
f999f4c1 AV |
3549 | spin_lock_irqsave(&vha->work_lock, flags); |
3550 | list_splice_init(&vha->work_list, &work); | |
3551 | spin_unlock_irqrestore(&vha->work_lock, flags); | |
3552 | ||
3553 | list_for_each_entry_safe(e, tmp, &work, list) { | |
0971de7f | 3554 | list_del_init(&e->list); |
0971de7f AV |
3555 | |
3556 | switch (e->type) { | |
3557 | case QLA_EVT_AEN: | |
e315cd28 | 3558 | fc_host_post_event(vha->host, fc_get_event_number(), |
0971de7f AV |
3559 | e->u.aen.code, e->u.aen.data); |
3560 | break; | |
8a659571 AV |
3561 | case QLA_EVT_IDC_ACK: |
3562 | qla81xx_idc_ack(vha, e->u.idc_ack.mb); | |
3563 | break; | |
ac280b67 AV |
3564 | case QLA_EVT_ASYNC_LOGIN: |
3565 | qla2x00_async_login(vha, e->u.logio.fcport, | |
3566 | e->u.logio.data); | |
3567 | break; | |
3568 | case QLA_EVT_ASYNC_LOGIN_DONE: | |
3569 | qla2x00_async_login_done(vha, e->u.logio.fcport, | |
3570 | e->u.logio.data); | |
3571 | break; | |
3572 | case QLA_EVT_ASYNC_LOGOUT: | |
3573 | qla2x00_async_logout(vha, e->u.logio.fcport); | |
3574 | break; | |
3575 | case QLA_EVT_ASYNC_LOGOUT_DONE: | |
3576 | qla2x00_async_logout_done(vha, e->u.logio.fcport, | |
3577 | e->u.logio.data); | |
3578 | break; | |
5ff1d584 AV |
3579 | case QLA_EVT_ASYNC_ADISC: |
3580 | qla2x00_async_adisc(vha, e->u.logio.fcport, | |
3581 | e->u.logio.data); | |
3582 | break; | |
3583 | case QLA_EVT_ASYNC_ADISC_DONE: | |
3584 | qla2x00_async_adisc_done(vha, e->u.logio.fcport, | |
3585 | e->u.logio.data); | |
3586 | break; | |
3420d36c AV |
3587 | case QLA_EVT_UEVENT: |
3588 | qla2x00_uevent_emit(vha, e->u.uevent.code); | |
3589 | break; | |
0971de7f AV |
3590 | } |
3591 | if (e->flags & QLA_EVT_FLAG_FREE) | |
3592 | kfree(e); | |
feafb7b1 AE |
3593 | |
3594 | /* For each work completed decrement vha ref count */ | |
3595 | QLA_VHA_MARK_NOT_BUSY(vha); | |
e315cd28 | 3596 | } |
e315cd28 | 3597 | } |
f999f4c1 | 3598 | |
e315cd28 AC |
3599 | /* Relogins all the fcports of a vport |
3600 | * Context: dpc thread | |
3601 | */ | |
3602 | void qla2x00_relogin(struct scsi_qla_host *vha) | |
3603 | { | |
3604 | fc_port_t *fcport; | |
c6b2fca8 | 3605 | int status; |
e315cd28 AC |
3606 | uint16_t next_loopid = 0; |
3607 | struct qla_hw_data *ha = vha->hw; | |
ac280b67 | 3608 | uint16_t data[2]; |
e315cd28 AC |
3609 | |
3610 | list_for_each_entry(fcport, &vha->vp_fcports, list) { | |
3611 | /* | |
3612 | * If the port is not ONLINE then try to login | |
3613 | * to it if we haven't run out of retries. | |
3614 | */ | |
5ff1d584 AV |
3615 | if (atomic_read(&fcport->state) != FCS_ONLINE && |
3616 | fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) { | |
ac280b67 | 3617 | fcport->login_retry--; |
e315cd28 | 3618 | if (fcport->flags & FCF_FABRIC_DEVICE) { |
f08b7251 | 3619 | if (fcport->flags & FCF_FCP2_DEVICE) |
e315cd28 AC |
3620 | ha->isp_ops->fabric_logout(vha, |
3621 | fcport->loop_id, | |
3622 | fcport->d_id.b.domain, | |
3623 | fcport->d_id.b.area, | |
3624 | fcport->d_id.b.al_pa); | |
3625 | ||
03bcfb57 JC |
3626 | if (fcport->loop_id == FC_NO_LOOP_ID) { |
3627 | fcport->loop_id = next_loopid = | |
3628 | ha->min_external_loopid; | |
3629 | status = qla2x00_find_new_loop_id( | |
3630 | vha, fcport); | |
3631 | if (status != QLA_SUCCESS) { | |
3632 | /* Ran out of IDs to use */ | |
3633 | break; | |
3634 | } | |
3635 | } | |
3636 | ||
ac280b67 | 3637 | if (IS_ALOGIO_CAPABLE(ha)) { |
5ff1d584 | 3638 | fcport->flags |= FCF_ASYNC_SENT; |
ac280b67 AV |
3639 | data[0] = 0; |
3640 | data[1] = QLA_LOGIO_LOGIN_RETRIED; | |
3641 | status = qla2x00_post_async_login_work( | |
3642 | vha, fcport, data); | |
3643 | if (status == QLA_SUCCESS) | |
3644 | continue; | |
3645 | /* Attempt a retry. */ | |
3646 | status = 1; | |
aaf4d3e2 | 3647 | } else { |
ac280b67 AV |
3648 | status = qla2x00_fabric_login(vha, |
3649 | fcport, &next_loopid); | |
aaf4d3e2 SK |
3650 | if (status == QLA_SUCCESS) { |
3651 | int status2; | |
3652 | uint8_t opts; | |
3653 | ||
3654 | opts = 0; | |
3655 | if (fcport->flags & | |
3656 | FCF_FCP2_DEVICE) | |
3657 | opts |= BIT_1; | |
3658 | status2 = | |
3659 | qla2x00_get_port_database( | |
3660 | vha, fcport, | |
3661 | opts); | |
3662 | if (status2 != QLA_SUCCESS) | |
3663 | status = 1; | |
3664 | } | |
3665 | } | |
e315cd28 AC |
3666 | } else |
3667 | status = qla2x00_local_device_login(vha, | |
3668 | fcport); | |
3669 | ||
e315cd28 AC |
3670 | if (status == QLA_SUCCESS) { |
3671 | fcport->old_loop_id = fcport->loop_id; | |
3672 | ||
7c3df132 SK |
3673 | ql_dbg(ql_dbg_disc, vha, 0x2003, |
3674 | "Port login OK: logged in ID 0x%x.\n", | |
3675 | fcport->loop_id); | |
e315cd28 AC |
3676 | |
3677 | qla2x00_update_fcport(vha, fcport); | |
3678 | ||
3679 | } else if (status == 1) { | |
3680 | set_bit(RELOGIN_NEEDED, &vha->dpc_flags); | |
3681 | /* retry the login again */ | |
7c3df132 SK |
3682 | ql_dbg(ql_dbg_disc, vha, 0x2007, |
3683 | "Retrying %d login again loop_id 0x%x.\n", | |
3684 | fcport->login_retry, fcport->loop_id); | |
e315cd28 AC |
3685 | } else { |
3686 | fcport->login_retry = 0; | |
3687 | } | |
3688 | ||
3689 | if (fcport->login_retry == 0 && status != QLA_SUCCESS) | |
3690 | fcport->loop_id = FC_NO_LOOP_ID; | |
3691 | } | |
3692 | if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) | |
3693 | break; | |
0971de7f | 3694 | } |
0971de7f AV |
3695 | } |
3696 | ||
1da177e4 LT |
3697 | /************************************************************************** |
3698 | * qla2x00_do_dpc | |
3699 | * This kernel thread is a task that is schedule by the interrupt handler | |
3700 | * to perform the background processing for interrupts. | |
3701 | * | |
3702 | * Notes: | |
3703 | * This task always run in the context of a kernel thread. It | |
3704 | * is kick-off by the driver's detect code and starts up | |
3705 | * up one per adapter. It immediately goes to sleep and waits for | |
3706 | * some fibre event. When either the interrupt handler or | |
3707 | * the timer routine detects a event it will one of the task | |
3708 | * bits then wake us up. | |
3709 | **************************************************************************/ | |
3710 | static int | |
3711 | qla2x00_do_dpc(void *data) | |
3712 | { | |
2c3dfe3f | 3713 | int rval; |
e315cd28 AC |
3714 | scsi_qla_host_t *base_vha; |
3715 | struct qla_hw_data *ha; | |
1da177e4 | 3716 | |
e315cd28 AC |
3717 | ha = (struct qla_hw_data *)data; |
3718 | base_vha = pci_get_drvdata(ha->pdev); | |
1da177e4 | 3719 | |
1da177e4 LT |
3720 | set_user_nice(current, -20); |
3721 | ||
563585ec | 3722 | set_current_state(TASK_INTERRUPTIBLE); |
39a11240 | 3723 | while (!kthread_should_stop()) { |
7c3df132 SK |
3724 | ql_dbg(ql_dbg_dpc, base_vha, 0x4000, |
3725 | "DPC handler sleeping.\n"); | |
1da177e4 | 3726 | |
39a11240 CH |
3727 | schedule(); |
3728 | __set_current_state(TASK_RUNNING); | |
1da177e4 | 3729 | |
c142caf0 AV |
3730 | if (!base_vha->flags.init_done || ha->flags.mbox_busy) |
3731 | goto end_loop; | |
1da177e4 | 3732 | |
85880801 | 3733 | if (ha->flags.eeh_busy) { |
7c3df132 SK |
3734 | ql_dbg(ql_dbg_dpc, base_vha, 0x4003, |
3735 | "eeh_busy=%d.\n", ha->flags.eeh_busy); | |
c142caf0 | 3736 | goto end_loop; |
85880801 AV |
3737 | } |
3738 | ||
1da177e4 LT |
3739 | ha->dpc_active = 1; |
3740 | ||
5f28d2d7 SK |
3741 | ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, |
3742 | "DPC handler waking up, dpc_flags=0x%lx.\n", | |
3743 | base_vha->dpc_flags); | |
1da177e4 | 3744 | |
e315cd28 | 3745 | qla2x00_do_work(base_vha); |
0971de7f | 3746 | |
a9083016 GM |
3747 | if (IS_QLA82XX(ha)) { |
3748 | if (test_and_clear_bit(ISP_UNRECOVERABLE, | |
3749 | &base_vha->dpc_flags)) { | |
3750 | qla82xx_idc_lock(ha); | |
3751 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | |
3752 | QLA82XX_DEV_FAILED); | |
3753 | qla82xx_idc_unlock(ha); | |
7c3df132 SK |
3754 | ql_log(ql_log_info, base_vha, 0x4004, |
3755 | "HW State: FAILED.\n"); | |
a9083016 GM |
3756 | qla82xx_device_state_handler(base_vha); |
3757 | continue; | |
3758 | } | |
3759 | ||
3760 | if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, | |
3761 | &base_vha->dpc_flags)) { | |
3762 | ||
7c3df132 SK |
3763 | ql_dbg(ql_dbg_dpc, base_vha, 0x4005, |
3764 | "FCoE context reset scheduled.\n"); | |
a9083016 GM |
3765 | if (!(test_and_set_bit(ABORT_ISP_ACTIVE, |
3766 | &base_vha->dpc_flags))) { | |
3767 | if (qla82xx_fcoe_ctx_reset(base_vha)) { | |
3768 | /* FCoE-ctx reset failed. | |
3769 | * Escalate to chip-reset | |
3770 | */ | |
3771 | set_bit(ISP_ABORT_NEEDED, | |
3772 | &base_vha->dpc_flags); | |
3773 | } | |
3774 | clear_bit(ABORT_ISP_ACTIVE, | |
3775 | &base_vha->dpc_flags); | |
3776 | } | |
3777 | ||
7c3df132 SK |
3778 | ql_dbg(ql_dbg_dpc, base_vha, 0x4006, |
3779 | "FCoE context reset end.\n"); | |
a9083016 GM |
3780 | } |
3781 | } | |
3782 | ||
e315cd28 AC |
3783 | if (test_and_clear_bit(ISP_ABORT_NEEDED, |
3784 | &base_vha->dpc_flags)) { | |
1da177e4 | 3785 | |
7c3df132 SK |
3786 | ql_dbg(ql_dbg_dpc, base_vha, 0x4007, |
3787 | "ISP abort scheduled.\n"); | |
1da177e4 | 3788 | if (!(test_and_set_bit(ABORT_ISP_ACTIVE, |
e315cd28 | 3789 | &base_vha->dpc_flags))) { |
1da177e4 | 3790 | |
a9083016 | 3791 | if (ha->isp_ops->abort_isp(base_vha)) { |
1da177e4 LT |
3792 | /* failed. retry later */ |
3793 | set_bit(ISP_ABORT_NEEDED, | |
e315cd28 | 3794 | &base_vha->dpc_flags); |
99363ef8 | 3795 | } |
e315cd28 AC |
3796 | clear_bit(ABORT_ISP_ACTIVE, |
3797 | &base_vha->dpc_flags); | |
99363ef8 SJ |
3798 | } |
3799 | ||
7c3df132 SK |
3800 | ql_dbg(ql_dbg_dpc, base_vha, 0x4008, |
3801 | "ISP abort end.\n"); | |
1da177e4 LT |
3802 | } |
3803 | ||
e315cd28 AC |
3804 | if (test_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags)) { |
3805 | qla2x00_update_fcports(base_vha); | |
3806 | clear_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); | |
c9c5ced9 | 3807 | } |
d97994dc | 3808 | |
2d70c103 NB |
3809 | if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) { |
3810 | int ret; | |
3811 | ret = qla2x00_send_change_request(base_vha, 0x3, 0); | |
3812 | if (ret != QLA_SUCCESS) | |
3813 | ql_log(ql_log_warn, base_vha, 0x121, | |
3814 | "Failed to enable receiving of RSCN " | |
3815 | "requests: 0x%x.\n", ret); | |
3816 | clear_bit(SCR_PENDING, &base_vha->dpc_flags); | |
3817 | } | |
3818 | ||
579d12b5 | 3819 | if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { |
7c3df132 SK |
3820 | ql_dbg(ql_dbg_dpc, base_vha, 0x4009, |
3821 | "Quiescence mode scheduled.\n"); | |
579d12b5 SK |
3822 | qla82xx_device_state_handler(base_vha); |
3823 | clear_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags); | |
3824 | if (!ha->flags.quiesce_owner) { | |
3825 | qla2x00_perform_loop_resync(base_vha); | |
3826 | ||
3827 | qla82xx_idc_lock(ha); | |
3828 | qla82xx_clear_qsnt_ready(base_vha); | |
3829 | qla82xx_idc_unlock(ha); | |
3830 | } | |
7c3df132 SK |
3831 | ql_dbg(ql_dbg_dpc, base_vha, 0x400a, |
3832 | "Quiescence mode end.\n"); | |
579d12b5 SK |
3833 | } |
3834 | ||
e315cd28 AC |
3835 | if (test_and_clear_bit(RESET_MARKER_NEEDED, |
3836 | &base_vha->dpc_flags) && | |
3837 | (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { | |
1da177e4 | 3838 | |
7c3df132 SK |
3839 | ql_dbg(ql_dbg_dpc, base_vha, 0x400b, |
3840 | "Reset marker scheduled.\n"); | |
e315cd28 AC |
3841 | qla2x00_rst_aen(base_vha); |
3842 | clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); | |
7c3df132 SK |
3843 | ql_dbg(ql_dbg_dpc, base_vha, 0x400c, |
3844 | "Reset marker end.\n"); | |
1da177e4 LT |
3845 | } |
3846 | ||
3847 | /* Retry each device up to login retry count */ | |
e315cd28 AC |
3848 | if ((test_and_clear_bit(RELOGIN_NEEDED, |
3849 | &base_vha->dpc_flags)) && | |
3850 | !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && | |
3851 | atomic_read(&base_vha->loop_state) != LOOP_DOWN) { | |
1da177e4 | 3852 | |
7c3df132 SK |
3853 | ql_dbg(ql_dbg_dpc, base_vha, 0x400d, |
3854 | "Relogin scheduled.\n"); | |
e315cd28 | 3855 | qla2x00_relogin(base_vha); |
7c3df132 SK |
3856 | ql_dbg(ql_dbg_dpc, base_vha, 0x400e, |
3857 | "Relogin end.\n"); | |
1da177e4 LT |
3858 | } |
3859 | ||
e315cd28 AC |
3860 | if (test_and_clear_bit(LOOP_RESYNC_NEEDED, |
3861 | &base_vha->dpc_flags)) { | |
1da177e4 | 3862 | |
7c3df132 SK |
3863 | ql_dbg(ql_dbg_dpc, base_vha, 0x400f, |
3864 | "Loop resync scheduled.\n"); | |
1da177e4 LT |
3865 | |
3866 | if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, | |
e315cd28 | 3867 | &base_vha->dpc_flags))) { |
1da177e4 | 3868 | |
e315cd28 | 3869 | rval = qla2x00_loop_resync(base_vha); |
1da177e4 | 3870 | |
e315cd28 AC |
3871 | clear_bit(LOOP_RESYNC_ACTIVE, |
3872 | &base_vha->dpc_flags); | |
1da177e4 LT |
3873 | } |
3874 | ||
7c3df132 SK |
3875 | ql_dbg(ql_dbg_dpc, base_vha, 0x4010, |
3876 | "Loop resync end.\n"); | |
1da177e4 LT |
3877 | } |
3878 | ||
e315cd28 AC |
3879 | if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && |
3880 | atomic_read(&base_vha->loop_state) == LOOP_READY) { | |
3881 | clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); | |
3882 | qla2xxx_flash_npiv_conf(base_vha); | |
272976ca AV |
3883 | } |
3884 | ||
1da177e4 | 3885 | if (!ha->interrupts_on) |
fd34f556 | 3886 | ha->isp_ops->enable_intrs(ha); |
1da177e4 | 3887 | |
e315cd28 AC |
3888 | if (test_and_clear_bit(BEACON_BLINK_NEEDED, |
3889 | &base_vha->dpc_flags)) | |
3890 | ha->isp_ops->beacon_blink(base_vha); | |
f6df144c | 3891 | |
e315cd28 | 3892 | qla2x00_do_dpc_all_vps(base_vha); |
2c3dfe3f | 3893 | |
1da177e4 | 3894 | ha->dpc_active = 0; |
c142caf0 | 3895 | end_loop: |
563585ec | 3896 | set_current_state(TASK_INTERRUPTIBLE); |
1da177e4 | 3897 | } /* End of while(1) */ |
563585ec | 3898 | __set_current_state(TASK_RUNNING); |
1da177e4 | 3899 | |
7c3df132 SK |
3900 | ql_dbg(ql_dbg_dpc, base_vha, 0x4011, |
3901 | "DPC handler exiting.\n"); | |
1da177e4 LT |
3902 | |
3903 | /* | |
3904 | * Make sure that nobody tries to wake us up again. | |
3905 | */ | |
1da177e4 LT |
3906 | ha->dpc_active = 0; |
3907 | ||
ac280b67 AV |
3908 | /* Cleanup any residual CTX SRBs. */ |
3909 | qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); | |
3910 | ||
39a11240 CH |
3911 | return 0; |
3912 | } | |
3913 | ||
3914 | void | |
e315cd28 | 3915 | qla2xxx_wake_dpc(struct scsi_qla_host *vha) |
39a11240 | 3916 | { |
e315cd28 | 3917 | struct qla_hw_data *ha = vha->hw; |
c795c1e4 AV |
3918 | struct task_struct *t = ha->dpc_thread; |
3919 | ||
e315cd28 | 3920 | if (!test_bit(UNLOADING, &vha->dpc_flags) && t) |
c795c1e4 | 3921 | wake_up_process(t); |
1da177e4 LT |
3922 | } |
3923 | ||
1da177e4 LT |
3924 | /* |
3925 | * qla2x00_rst_aen | |
3926 | * Processes asynchronous reset. | |
3927 | * | |
3928 | * Input: | |
3929 | * ha = adapter block pointer. | |
3930 | */ | |
3931 | static void | |
e315cd28 | 3932 | qla2x00_rst_aen(scsi_qla_host_t *vha) |
1da177e4 | 3933 | { |
e315cd28 AC |
3934 | if (vha->flags.online && !vha->flags.reset_active && |
3935 | !atomic_read(&vha->loop_down_timer) && | |
3936 | !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { | |
1da177e4 | 3937 | do { |
e315cd28 | 3938 | clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); |
1da177e4 LT |
3939 | |
3940 | /* | |
3941 | * Issue marker command only when we are going to start | |
3942 | * the I/O. | |
3943 | */ | |
e315cd28 AC |
3944 | vha->marker_needed = 1; |
3945 | } while (!atomic_read(&vha->loop_down_timer) && | |
3946 | (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); | |
1da177e4 LT |
3947 | } |
3948 | } | |
3949 | ||
1da177e4 LT |
3950 | /************************************************************************** |
3951 | * qla2x00_timer | |
3952 | * | |
3953 | * Description: | |
3954 | * One second timer | |
3955 | * | |
3956 | * Context: Interrupt | |
3957 | ***************************************************************************/ | |
2c3dfe3f | 3958 | void |
e315cd28 | 3959 | qla2x00_timer(scsi_qla_host_t *vha) |
1da177e4 | 3960 | { |
1da177e4 | 3961 | unsigned long cpu_flags = 0; |
1da177e4 LT |
3962 | int start_dpc = 0; |
3963 | int index; | |
3964 | srb_t *sp; | |
85880801 | 3965 | uint16_t w; |
e315cd28 | 3966 | struct qla_hw_data *ha = vha->hw; |
73208dfd | 3967 | struct req_que *req; |
85880801 | 3968 | |
a5b36321 | 3969 | if (ha->flags.eeh_busy) { |
7c3df132 SK |
3970 | ql_dbg(ql_dbg_timer, vha, 0x6000, |
3971 | "EEH = %d, restarting timer.\n", | |
3972 | ha->flags.eeh_busy); | |
a5b36321 LC |
3973 | qla2x00_restart_timer(vha, WATCH_INTERVAL); |
3974 | return; | |
3975 | } | |
3976 | ||
85880801 AV |
3977 | /* Hardware read to raise pending EEH errors during mailbox waits. */ |
3978 | if (!pci_channel_offline(ha->pdev)) | |
3979 | pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); | |
1da177e4 | 3980 | |
cefcaba6 SK |
3981 | /* Make sure qla82xx_watchdog is run only for physical port */ |
3982 | if (!vha->vp_idx && IS_QLA82XX(ha)) { | |
579d12b5 SK |
3983 | if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) |
3984 | start_dpc++; | |
3985 | qla82xx_watchdog(vha); | |
3986 | } | |
3987 | ||
1da177e4 | 3988 | /* Loop down handler. */ |
e315cd28 | 3989 | if (atomic_read(&vha->loop_down_timer) > 0 && |
8f7daead GM |
3990 | !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && |
3991 | !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) | |
e315cd28 | 3992 | && vha->flags.online) { |
1da177e4 | 3993 | |
e315cd28 AC |
3994 | if (atomic_read(&vha->loop_down_timer) == |
3995 | vha->loop_down_abort_time) { | |
1da177e4 | 3996 | |
7c3df132 SK |
3997 | ql_log(ql_log_info, vha, 0x6008, |
3998 | "Loop down - aborting the queues before time expires.\n"); | |
1da177e4 | 3999 | |
e315cd28 AC |
4000 | if (!IS_QLA2100(ha) && vha->link_down_timeout) |
4001 | atomic_set(&vha->loop_state, LOOP_DEAD); | |
1da177e4 | 4002 | |
f08b7251 AV |
4003 | /* |
4004 | * Schedule an ISP abort to return any FCP2-device | |
4005 | * commands. | |
4006 | */ | |
2c3dfe3f | 4007 | /* NPIV - scan physical port only */ |
e315cd28 | 4008 | if (!vha->vp_idx) { |
2c3dfe3f SJ |
4009 | spin_lock_irqsave(&ha->hardware_lock, |
4010 | cpu_flags); | |
73208dfd | 4011 | req = ha->req_q_map[0]; |
2c3dfe3f SJ |
4012 | for (index = 1; |
4013 | index < MAX_OUTSTANDING_COMMANDS; | |
4014 | index++) { | |
4015 | fc_port_t *sfcp; | |
4016 | ||
e315cd28 | 4017 | sp = req->outstanding_cmds[index]; |
2c3dfe3f SJ |
4018 | if (!sp) |
4019 | continue; | |
9ba56b95 | 4020 | if (sp->type != SRB_SCSI_CMD) |
cf53b069 | 4021 | continue; |
2c3dfe3f | 4022 | sfcp = sp->fcport; |
f08b7251 | 4023 | if (!(sfcp->flags & FCF_FCP2_DEVICE)) |
2c3dfe3f | 4024 | continue; |
bdf79621 | 4025 | |
8f7daead GM |
4026 | if (IS_QLA82XX(ha)) |
4027 | set_bit(FCOE_CTX_RESET_NEEDED, | |
4028 | &vha->dpc_flags); | |
4029 | else | |
4030 | set_bit(ISP_ABORT_NEEDED, | |
e315cd28 | 4031 | &vha->dpc_flags); |
2c3dfe3f SJ |
4032 | break; |
4033 | } | |
4034 | spin_unlock_irqrestore(&ha->hardware_lock, | |
e315cd28 | 4035 | cpu_flags); |
1da177e4 | 4036 | } |
1da177e4 LT |
4037 | start_dpc++; |
4038 | } | |
4039 | ||
4040 | /* if the loop has been down for 4 minutes, reinit adapter */ | |
e315cd28 | 4041 | if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { |
0d6e61bc | 4042 | if (!(vha->device_flags & DFLG_NO_CABLE)) { |
7c3df132 | 4043 | ql_log(ql_log_warn, vha, 0x6009, |
1da177e4 LT |
4044 | "Loop down - aborting ISP.\n"); |
4045 | ||
8f7daead GM |
4046 | if (IS_QLA82XX(ha)) |
4047 | set_bit(FCOE_CTX_RESET_NEEDED, | |
4048 | &vha->dpc_flags); | |
4049 | else | |
4050 | set_bit(ISP_ABORT_NEEDED, | |
4051 | &vha->dpc_flags); | |
1da177e4 LT |
4052 | } |
4053 | } | |
7c3df132 SK |
4054 | ql_dbg(ql_dbg_timer, vha, 0x600a, |
4055 | "Loop down - seconds remaining %d.\n", | |
4056 | atomic_read(&vha->loop_down_timer)); | |
1da177e4 LT |
4057 | } |
4058 | ||
cefcaba6 SK |
4059 | /* Check if beacon LED needs to be blinked for physical host only */ |
4060 | if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { | |
999916dc SK |
4061 | /* There is no beacon_blink function for ISP82xx */ |
4062 | if (!IS_QLA82XX(ha)) { | |
4063 | set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); | |
4064 | start_dpc++; | |
4065 | } | |
f6df144c | 4066 | } |
4067 | ||
550bf57d | 4068 | /* Process any deferred work. */ |
e315cd28 | 4069 | if (!list_empty(&vha->work_list)) |
550bf57d AV |
4070 | start_dpc++; |
4071 | ||
1da177e4 | 4072 | /* Schedule the DPC routine if needed */ |
e315cd28 AC |
4073 | if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || |
4074 | test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || | |
4075 | test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || | |
1da177e4 | 4076 | start_dpc || |
e315cd28 AC |
4077 | test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || |
4078 | test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || | |
a9083016 GM |
4079 | test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || |
4080 | test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || | |
e315cd28 | 4081 | test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || |
7c3df132 SK |
4082 | test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) { |
4083 | ql_dbg(ql_dbg_timer, vha, 0x600b, | |
4084 | "isp_abort_needed=%d loop_resync_needed=%d " | |
4085 | "fcport_update_needed=%d start_dpc=%d " | |
4086 | "reset_marker_needed=%d", | |
4087 | test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), | |
4088 | test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), | |
4089 | test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), | |
4090 | start_dpc, | |
4091 | test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); | |
4092 | ql_dbg(ql_dbg_timer, vha, 0x600c, | |
4093 | "beacon_blink_needed=%d isp_unrecoverable=%d " | |
4094 | "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " | |
4095 | "relogin_needed=%d.\n", | |
4096 | test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), | |
4097 | test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), | |
4098 | test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), | |
4099 | test_bit(VP_DPC_NEEDED, &vha->dpc_flags), | |
4100 | test_bit(RELOGIN_NEEDED, &vha->dpc_flags)); | |
e315cd28 | 4101 | qla2xxx_wake_dpc(vha); |
7c3df132 | 4102 | } |
1da177e4 | 4103 | |
e315cd28 | 4104 | qla2x00_restart_timer(vha, WATCH_INTERVAL); |
1da177e4 LT |
4105 | } |
4106 | ||
5433383e AV |
4107 | /* Firmware interface routines. */ |
4108 | ||
6246b8a1 | 4109 | #define FW_BLOBS 10 |
5433383e AV |
4110 | #define FW_ISP21XX 0 |
4111 | #define FW_ISP22XX 1 | |
4112 | #define FW_ISP2300 2 | |
4113 | #define FW_ISP2322 3 | |
48c02fde | 4114 | #define FW_ISP24XX 4 |
c3a2f0df | 4115 | #define FW_ISP25XX 5 |
3a03eb79 | 4116 | #define FW_ISP81XX 6 |
a9083016 | 4117 | #define FW_ISP82XX 7 |
6246b8a1 GM |
4118 | #define FW_ISP2031 8 |
4119 | #define FW_ISP8031 9 | |
5433383e | 4120 | |
bb8ee499 AV |
4121 | #define FW_FILE_ISP21XX "ql2100_fw.bin" |
4122 | #define FW_FILE_ISP22XX "ql2200_fw.bin" | |
4123 | #define FW_FILE_ISP2300 "ql2300_fw.bin" | |
4124 | #define FW_FILE_ISP2322 "ql2322_fw.bin" | |
4125 | #define FW_FILE_ISP24XX "ql2400_fw.bin" | |
c3a2f0df | 4126 | #define FW_FILE_ISP25XX "ql2500_fw.bin" |
3a03eb79 | 4127 | #define FW_FILE_ISP81XX "ql8100_fw.bin" |
a9083016 | 4128 | #define FW_FILE_ISP82XX "ql8200_fw.bin" |
6246b8a1 GM |
4129 | #define FW_FILE_ISP2031 "ql2600_fw.bin" |
4130 | #define FW_FILE_ISP8031 "ql8300_fw.bin" | |
bb8ee499 | 4131 | |
e1e82b6f | 4132 | static DEFINE_MUTEX(qla_fw_lock); |
5433383e AV |
4133 | |
4134 | static struct fw_blob qla_fw_blobs[FW_BLOBS] = { | |
bb8ee499 AV |
4135 | { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, |
4136 | { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, | |
4137 | { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, | |
4138 | { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, | |
4139 | { .name = FW_FILE_ISP24XX, }, | |
c3a2f0df | 4140 | { .name = FW_FILE_ISP25XX, }, |
3a03eb79 | 4141 | { .name = FW_FILE_ISP81XX, }, |
a9083016 | 4142 | { .name = FW_FILE_ISP82XX, }, |
6246b8a1 GM |
4143 | { .name = FW_FILE_ISP2031, }, |
4144 | { .name = FW_FILE_ISP8031, }, | |
5433383e AV |
4145 | }; |
4146 | ||
4147 | struct fw_blob * | |
e315cd28 | 4148 | qla2x00_request_firmware(scsi_qla_host_t *vha) |
5433383e | 4149 | { |
e315cd28 | 4150 | struct qla_hw_data *ha = vha->hw; |
5433383e AV |
4151 | struct fw_blob *blob; |
4152 | ||
5433383e AV |
4153 | if (IS_QLA2100(ha)) { |
4154 | blob = &qla_fw_blobs[FW_ISP21XX]; | |
4155 | } else if (IS_QLA2200(ha)) { | |
4156 | blob = &qla_fw_blobs[FW_ISP22XX]; | |
48c02fde | 4157 | } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { |
5433383e | 4158 | blob = &qla_fw_blobs[FW_ISP2300]; |
48c02fde | 4159 | } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { |
5433383e | 4160 | blob = &qla_fw_blobs[FW_ISP2322]; |
4d4df193 | 4161 | } else if (IS_QLA24XX_TYPE(ha)) { |
5433383e | 4162 | blob = &qla_fw_blobs[FW_ISP24XX]; |
c3a2f0df AV |
4163 | } else if (IS_QLA25XX(ha)) { |
4164 | blob = &qla_fw_blobs[FW_ISP25XX]; | |
3a03eb79 AV |
4165 | } else if (IS_QLA81XX(ha)) { |
4166 | blob = &qla_fw_blobs[FW_ISP81XX]; | |
a9083016 GM |
4167 | } else if (IS_QLA82XX(ha)) { |
4168 | blob = &qla_fw_blobs[FW_ISP82XX]; | |
6246b8a1 GM |
4169 | } else if (IS_QLA2031(ha)) { |
4170 | blob = &qla_fw_blobs[FW_ISP2031]; | |
4171 | } else if (IS_QLA8031(ha)) { | |
4172 | blob = &qla_fw_blobs[FW_ISP8031]; | |
8a655229 DC |
4173 | } else { |
4174 | return NULL; | |
5433383e AV |
4175 | } |
4176 | ||
e1e82b6f | 4177 | mutex_lock(&qla_fw_lock); |
5433383e AV |
4178 | if (blob->fw) |
4179 | goto out; | |
4180 | ||
4181 | if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { | |
7c3df132 SK |
4182 | ql_log(ql_log_warn, vha, 0x0063, |
4183 | "Failed to load firmware image (%s).\n", blob->name); | |
5433383e AV |
4184 | blob->fw = NULL; |
4185 | blob = NULL; | |
4186 | goto out; | |
4187 | } | |
4188 | ||
4189 | out: | |
e1e82b6f | 4190 | mutex_unlock(&qla_fw_lock); |
5433383e AV |
4191 | return blob; |
4192 | } | |
4193 | ||
4194 | static void | |
4195 | qla2x00_release_firmware(void) | |
4196 | { | |
4197 | int idx; | |
4198 | ||
e1e82b6f | 4199 | mutex_lock(&qla_fw_lock); |
5433383e | 4200 | for (idx = 0; idx < FW_BLOBS; idx++) |
cf92549f | 4201 | release_firmware(qla_fw_blobs[idx].fw); |
e1e82b6f | 4202 | mutex_unlock(&qla_fw_lock); |
5433383e AV |
4203 | } |
4204 | ||
14e660e6 SJ |
4205 | static pci_ers_result_t |
4206 | qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) | |
4207 | { | |
85880801 AV |
4208 | scsi_qla_host_t *vha = pci_get_drvdata(pdev); |
4209 | struct qla_hw_data *ha = vha->hw; | |
4210 | ||
7c3df132 SK |
4211 | ql_dbg(ql_dbg_aer, vha, 0x9000, |
4212 | "PCI error detected, state %x.\n", state); | |
b9b12f73 | 4213 | |
14e660e6 SJ |
4214 | switch (state) { |
4215 | case pci_channel_io_normal: | |
85880801 | 4216 | ha->flags.eeh_busy = 0; |
14e660e6 SJ |
4217 | return PCI_ERS_RESULT_CAN_RECOVER; |
4218 | case pci_channel_io_frozen: | |
85880801 | 4219 | ha->flags.eeh_busy = 1; |
a5b36321 LC |
4220 | /* For ISP82XX complete any pending mailbox cmd */ |
4221 | if (IS_QLA82XX(ha)) { | |
7190575f | 4222 | ha->flags.isp82xx_fw_hung = 1; |
c8f6544e CD |
4223 | ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n"); |
4224 | qla82xx_clear_pending_mbx(vha); | |
a5b36321 | 4225 | } |
90a86fc0 | 4226 | qla2x00_free_irqs(vha); |
14e660e6 | 4227 | pci_disable_device(pdev); |
bddd2d65 LC |
4228 | /* Return back all IOs */ |
4229 | qla2x00_abort_all_cmds(vha, DID_RESET << 16); | |
14e660e6 SJ |
4230 | return PCI_ERS_RESULT_NEED_RESET; |
4231 | case pci_channel_io_perm_failure: | |
85880801 AV |
4232 | ha->flags.pci_channel_io_perm_failure = 1; |
4233 | qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); | |
14e660e6 SJ |
4234 | return PCI_ERS_RESULT_DISCONNECT; |
4235 | } | |
4236 | return PCI_ERS_RESULT_NEED_RESET; | |
4237 | } | |
4238 | ||
4239 | static pci_ers_result_t | |
4240 | qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) | |
4241 | { | |
4242 | int risc_paused = 0; | |
4243 | uint32_t stat; | |
4244 | unsigned long flags; | |
e315cd28 AC |
4245 | scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); |
4246 | struct qla_hw_data *ha = base_vha->hw; | |
14e660e6 SJ |
4247 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
4248 | struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; | |
4249 | ||
bcc5b6d3 SK |
4250 | if (IS_QLA82XX(ha)) |
4251 | return PCI_ERS_RESULT_RECOVERED; | |
4252 | ||
14e660e6 SJ |
4253 | spin_lock_irqsave(&ha->hardware_lock, flags); |
4254 | if (IS_QLA2100(ha) || IS_QLA2200(ha)){ | |
4255 | stat = RD_REG_DWORD(®->hccr); | |
4256 | if (stat & HCCR_RISC_PAUSE) | |
4257 | risc_paused = 1; | |
4258 | } else if (IS_QLA23XX(ha)) { | |
4259 | stat = RD_REG_DWORD(®->u.isp2300.host_status); | |
4260 | if (stat & HSR_RISC_PAUSED) | |
4261 | risc_paused = 1; | |
4262 | } else if (IS_FWI2_CAPABLE(ha)) { | |
4263 | stat = RD_REG_DWORD(®24->host_status); | |
4264 | if (stat & HSRX_RISC_PAUSED) | |
4265 | risc_paused = 1; | |
4266 | } | |
4267 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
4268 | ||
4269 | if (risc_paused) { | |
7c3df132 SK |
4270 | ql_log(ql_log_info, base_vha, 0x9003, |
4271 | "RISC paused -- mmio_enabled, Dumping firmware.\n"); | |
e315cd28 | 4272 | ha->isp_ops->fw_dump(base_vha, 0); |
14e660e6 SJ |
4273 | |
4274 | return PCI_ERS_RESULT_NEED_RESET; | |
4275 | } else | |
4276 | return PCI_ERS_RESULT_RECOVERED; | |
4277 | } | |
4278 | ||
a5b36321 LC |
4279 | uint32_t qla82xx_error_recovery(scsi_qla_host_t *base_vha) |
4280 | { | |
4281 | uint32_t rval = QLA_FUNCTION_FAILED; | |
4282 | uint32_t drv_active = 0; | |
4283 | struct qla_hw_data *ha = base_vha->hw; | |
4284 | int fn; | |
4285 | struct pci_dev *other_pdev = NULL; | |
4286 | ||
7c3df132 SK |
4287 | ql_dbg(ql_dbg_aer, base_vha, 0x9006, |
4288 | "Entered %s.\n", __func__); | |
a5b36321 LC |
4289 | |
4290 | set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); | |
4291 | ||
4292 | if (base_vha->flags.online) { | |
4293 | /* Abort all outstanding commands, | |
4294 | * so as to be requeued later */ | |
4295 | qla2x00_abort_isp_cleanup(base_vha); | |
4296 | } | |
4297 | ||
4298 | ||
4299 | fn = PCI_FUNC(ha->pdev->devfn); | |
4300 | while (fn > 0) { | |
4301 | fn--; | |
7c3df132 SK |
4302 | ql_dbg(ql_dbg_aer, base_vha, 0x9007, |
4303 | "Finding pci device at function = 0x%x.\n", fn); | |
a5b36321 LC |
4304 | other_pdev = |
4305 | pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus), | |
4306 | ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn), | |
4307 | fn)); | |
4308 | ||
4309 | if (!other_pdev) | |
4310 | continue; | |
4311 | if (atomic_read(&other_pdev->enable_cnt)) { | |
7c3df132 SK |
4312 | ql_dbg(ql_dbg_aer, base_vha, 0x9008, |
4313 | "Found PCI func available and enable at 0x%x.\n", | |
4314 | fn); | |
a5b36321 LC |
4315 | pci_dev_put(other_pdev); |
4316 | break; | |
4317 | } | |
4318 | pci_dev_put(other_pdev); | |
4319 | } | |
4320 | ||
4321 | if (!fn) { | |
4322 | /* Reset owner */ | |
7c3df132 SK |
4323 | ql_dbg(ql_dbg_aer, base_vha, 0x9009, |
4324 | "This devfn is reset owner = 0x%x.\n", | |
4325 | ha->pdev->devfn); | |
a5b36321 LC |
4326 | qla82xx_idc_lock(ha); |
4327 | ||
4328 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | |
4329 | QLA82XX_DEV_INITIALIZING); | |
4330 | ||
4331 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, | |
4332 | QLA82XX_IDC_VERSION); | |
4333 | ||
4334 | drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); | |
7c3df132 SK |
4335 | ql_dbg(ql_dbg_aer, base_vha, 0x900a, |
4336 | "drv_active = 0x%x.\n", drv_active); | |
a5b36321 LC |
4337 | |
4338 | qla82xx_idc_unlock(ha); | |
4339 | /* Reset if device is not already reset | |
4340 | * drv_active would be 0 if a reset has already been done | |
4341 | */ | |
4342 | if (drv_active) | |
4343 | rval = qla82xx_start_firmware(base_vha); | |
4344 | else | |
4345 | rval = QLA_SUCCESS; | |
4346 | qla82xx_idc_lock(ha); | |
4347 | ||
4348 | if (rval != QLA_SUCCESS) { | |
7c3df132 SK |
4349 | ql_log(ql_log_info, base_vha, 0x900b, |
4350 | "HW State: FAILED.\n"); | |
a5b36321 LC |
4351 | qla82xx_clear_drv_active(ha); |
4352 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | |
4353 | QLA82XX_DEV_FAILED); | |
4354 | } else { | |
7c3df132 SK |
4355 | ql_log(ql_log_info, base_vha, 0x900c, |
4356 | "HW State: READY.\n"); | |
a5b36321 LC |
4357 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, |
4358 | QLA82XX_DEV_READY); | |
4359 | qla82xx_idc_unlock(ha); | |
7190575f | 4360 | ha->flags.isp82xx_fw_hung = 0; |
a5b36321 LC |
4361 | rval = qla82xx_restart_isp(base_vha); |
4362 | qla82xx_idc_lock(ha); | |
4363 | /* Clear driver state register */ | |
4364 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); | |
4365 | qla82xx_set_drv_active(base_vha); | |
4366 | } | |
4367 | qla82xx_idc_unlock(ha); | |
4368 | } else { | |
7c3df132 SK |
4369 | ql_dbg(ql_dbg_aer, base_vha, 0x900d, |
4370 | "This devfn is not reset owner = 0x%x.\n", | |
4371 | ha->pdev->devfn); | |
a5b36321 LC |
4372 | if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) == |
4373 | QLA82XX_DEV_READY)) { | |
7190575f | 4374 | ha->flags.isp82xx_fw_hung = 0; |
a5b36321 LC |
4375 | rval = qla82xx_restart_isp(base_vha); |
4376 | qla82xx_idc_lock(ha); | |
4377 | qla82xx_set_drv_active(base_vha); | |
4378 | qla82xx_idc_unlock(ha); | |
4379 | } | |
4380 | } | |
4381 | clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); | |
4382 | ||
4383 | return rval; | |
4384 | } | |
4385 | ||
14e660e6 SJ |
4386 | static pci_ers_result_t |
4387 | qla2xxx_pci_slot_reset(struct pci_dev *pdev) | |
4388 | { | |
4389 | pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; | |
e315cd28 AC |
4390 | scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); |
4391 | struct qla_hw_data *ha = base_vha->hw; | |
90a86fc0 JC |
4392 | struct rsp_que *rsp; |
4393 | int rc, retries = 10; | |
09483916 | 4394 | |
7c3df132 SK |
4395 | ql_dbg(ql_dbg_aer, base_vha, 0x9004, |
4396 | "Slot Reset.\n"); | |
85880801 | 4397 | |
90a86fc0 JC |
4398 | /* Workaround: qla2xxx driver which access hardware earlier |
4399 | * needs error state to be pci_channel_io_online. | |
4400 | * Otherwise mailbox command timesout. | |
4401 | */ | |
4402 | pdev->error_state = pci_channel_io_normal; | |
4403 | ||
4404 | pci_restore_state(pdev); | |
4405 | ||
8c1496bd RL |
4406 | /* pci_restore_state() clears the saved_state flag of the device |
4407 | * save restored state which resets saved_state flag | |
4408 | */ | |
4409 | pci_save_state(pdev); | |
4410 | ||
09483916 BH |
4411 | if (ha->mem_only) |
4412 | rc = pci_enable_device_mem(pdev); | |
4413 | else | |
4414 | rc = pci_enable_device(pdev); | |
14e660e6 | 4415 | |
09483916 | 4416 | if (rc) { |
7c3df132 | 4417 | ql_log(ql_log_warn, base_vha, 0x9005, |
14e660e6 | 4418 | "Can't re-enable PCI device after reset.\n"); |
a5b36321 | 4419 | goto exit_slot_reset; |
14e660e6 | 4420 | } |
14e660e6 | 4421 | |
90a86fc0 JC |
4422 | rsp = ha->rsp_q_map[0]; |
4423 | if (qla2x00_request_irqs(ha, rsp)) | |
a5b36321 | 4424 | goto exit_slot_reset; |
90a86fc0 | 4425 | |
e315cd28 | 4426 | if (ha->isp_ops->pci_config(base_vha)) |
a5b36321 LC |
4427 | goto exit_slot_reset; |
4428 | ||
4429 | if (IS_QLA82XX(ha)) { | |
4430 | if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) { | |
4431 | ret = PCI_ERS_RESULT_RECOVERED; | |
4432 | goto exit_slot_reset; | |
4433 | } else | |
4434 | goto exit_slot_reset; | |
4435 | } | |
14e660e6 | 4436 | |
90a86fc0 JC |
4437 | while (ha->flags.mbox_busy && retries--) |
4438 | msleep(1000); | |
85880801 | 4439 | |
e315cd28 | 4440 | set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); |
a9083016 | 4441 | if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) |
14e660e6 | 4442 | ret = PCI_ERS_RESULT_RECOVERED; |
e315cd28 | 4443 | clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); |
14e660e6 | 4444 | |
90a86fc0 | 4445 | |
a5b36321 | 4446 | exit_slot_reset: |
7c3df132 SK |
4447 | ql_dbg(ql_dbg_aer, base_vha, 0x900e, |
4448 | "slot_reset return %x.\n", ret); | |
85880801 | 4449 | |
14e660e6 SJ |
4450 | return ret; |
4451 | } | |
4452 | ||
4453 | static void | |
4454 | qla2xxx_pci_resume(struct pci_dev *pdev) | |
4455 | { | |
e315cd28 AC |
4456 | scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); |
4457 | struct qla_hw_data *ha = base_vha->hw; | |
14e660e6 SJ |
4458 | int ret; |
4459 | ||
7c3df132 SK |
4460 | ql_dbg(ql_dbg_aer, base_vha, 0x900f, |
4461 | "pci_resume.\n"); | |
85880801 | 4462 | |
e315cd28 | 4463 | ret = qla2x00_wait_for_hba_online(base_vha); |
14e660e6 | 4464 | if (ret != QLA_SUCCESS) { |
7c3df132 SK |
4465 | ql_log(ql_log_fatal, base_vha, 0x9002, |
4466 | "The device failed to resume I/O from slot/link_reset.\n"); | |
14e660e6 | 4467 | } |
85880801 | 4468 | |
3e46f031 LC |
4469 | pci_cleanup_aer_uncorrect_error_status(pdev); |
4470 | ||
85880801 | 4471 | ha->flags.eeh_busy = 0; |
14e660e6 SJ |
4472 | } |
4473 | ||
a55b2d21 | 4474 | static const struct pci_error_handlers qla2xxx_err_handler = { |
14e660e6 SJ |
4475 | .error_detected = qla2xxx_pci_error_detected, |
4476 | .mmio_enabled = qla2xxx_pci_mmio_enabled, | |
4477 | .slot_reset = qla2xxx_pci_slot_reset, | |
4478 | .resume = qla2xxx_pci_resume, | |
4479 | }; | |
4480 | ||
5433383e | 4481 | static struct pci_device_id qla2xxx_pci_tbl[] = { |
47f5e069 AV |
4482 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, |
4483 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, | |
4484 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, | |
4485 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, | |
4486 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, | |
4487 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, | |
4488 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, | |
4489 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, | |
4490 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, | |
4d4df193 | 4491 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, |
47f5e069 AV |
4492 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, |
4493 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, | |
c3a2f0df | 4494 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, |
6246b8a1 | 4495 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, |
3a03eb79 | 4496 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, |
a9083016 | 4497 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, |
5433383e AV |
4498 | { 0 }, |
4499 | }; | |
4500 | MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); | |
4501 | ||
fca29703 | 4502 | static struct pci_driver qla2xxx_pci_driver = { |
cb63067a | 4503 | .name = QLA2XXX_DRIVER_NAME, |
0a21ef1e JB |
4504 | .driver = { |
4505 | .owner = THIS_MODULE, | |
4506 | }, | |
fca29703 | 4507 | .id_table = qla2xxx_pci_tbl, |
7ee61397 | 4508 | .probe = qla2x00_probe_one, |
4c993f76 | 4509 | .remove = qla2x00_remove_one, |
e30d1756 | 4510 | .shutdown = qla2x00_shutdown, |
14e660e6 | 4511 | .err_handler = &qla2xxx_err_handler, |
fca29703 AV |
4512 | }; |
4513 | ||
6a03b4cd HZ |
4514 | static struct file_operations apidev_fops = { |
4515 | .owner = THIS_MODULE, | |
6038f373 | 4516 | .llseek = noop_llseek, |
6a03b4cd HZ |
4517 | }; |
4518 | ||
1da177e4 LT |
4519 | /** |
4520 | * qla2x00_module_init - Module initialization. | |
4521 | **/ | |
4522 | static int __init | |
4523 | qla2x00_module_init(void) | |
4524 | { | |
fca29703 AV |
4525 | int ret = 0; |
4526 | ||
1da177e4 | 4527 | /* Allocate cache for SRBs. */ |
354d6b21 | 4528 | srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, |
20c2df83 | 4529 | SLAB_HWCACHE_ALIGN, NULL); |
1da177e4 | 4530 | if (srb_cachep == NULL) { |
7c3df132 SK |
4531 | ql_log(ql_log_fatal, NULL, 0x0001, |
4532 | "Unable to allocate SRB cache...Failing load!.\n"); | |
1da177e4 LT |
4533 | return -ENOMEM; |
4534 | } | |
4535 | ||
2d70c103 NB |
4536 | /* Initialize target kmem_cache and mem_pools */ |
4537 | ret = qlt_init(); | |
4538 | if (ret < 0) { | |
4539 | kmem_cache_destroy(srb_cachep); | |
4540 | return ret; | |
4541 | } else if (ret > 0) { | |
4542 | /* | |
4543 | * If initiator mode is explictly disabled by qlt_init(), | |
4544 | * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from | |
4545 | * performing scsi_scan_target() during LOOP UP event. | |
4546 | */ | |
4547 | qla2xxx_transport_functions.disable_target_scan = 1; | |
4548 | qla2xxx_transport_vport_functions.disable_target_scan = 1; | |
4549 | } | |
4550 | ||
1da177e4 LT |
4551 | /* Derive version string. */ |
4552 | strcpy(qla2x00_version_str, QLA2XXX_VERSION); | |
11010fec | 4553 | if (ql2xextended_error_logging) |
0181944f AV |
4554 | strcat(qla2x00_version_str, "-debug"); |
4555 | ||
1c97a12a AV |
4556 | qla2xxx_transport_template = |
4557 | fc_attach_transport(&qla2xxx_transport_functions); | |
2c3dfe3f SJ |
4558 | if (!qla2xxx_transport_template) { |
4559 | kmem_cache_destroy(srb_cachep); | |
7c3df132 SK |
4560 | ql_log(ql_log_fatal, NULL, 0x0002, |
4561 | "fc_attach_transport failed...Failing load!.\n"); | |
2d70c103 | 4562 | qlt_exit(); |
1da177e4 | 4563 | return -ENODEV; |
2c3dfe3f | 4564 | } |
6a03b4cd HZ |
4565 | |
4566 | apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); | |
4567 | if (apidev_major < 0) { | |
7c3df132 SK |
4568 | ql_log(ql_log_fatal, NULL, 0x0003, |
4569 | "Unable to register char device %s.\n", QLA2XXX_APIDEV); | |
6a03b4cd HZ |
4570 | } |
4571 | ||
2c3dfe3f SJ |
4572 | qla2xxx_transport_vport_template = |
4573 | fc_attach_transport(&qla2xxx_transport_vport_functions); | |
4574 | if (!qla2xxx_transport_vport_template) { | |
4575 | kmem_cache_destroy(srb_cachep); | |
2d70c103 | 4576 | qlt_exit(); |
2c3dfe3f | 4577 | fc_release_transport(qla2xxx_transport_template); |
7c3df132 SK |
4578 | ql_log(ql_log_fatal, NULL, 0x0004, |
4579 | "fc_attach_transport vport failed...Failing load!.\n"); | |
1da177e4 | 4580 | return -ENODEV; |
2c3dfe3f | 4581 | } |
7c3df132 SK |
4582 | ql_log(ql_log_info, NULL, 0x0005, |
4583 | "QLogic Fibre Channel HBA Driver: %s.\n", | |
fd9a29f0 | 4584 | qla2x00_version_str); |
7ee61397 | 4585 | ret = pci_register_driver(&qla2xxx_pci_driver); |
fca29703 AV |
4586 | if (ret) { |
4587 | kmem_cache_destroy(srb_cachep); | |
2d70c103 | 4588 | qlt_exit(); |
fca29703 | 4589 | fc_release_transport(qla2xxx_transport_template); |
2c3dfe3f | 4590 | fc_release_transport(qla2xxx_transport_vport_template); |
7c3df132 SK |
4591 | ql_log(ql_log_fatal, NULL, 0x0006, |
4592 | "pci_register_driver failed...ret=%d Failing load!.\n", | |
4593 | ret); | |
fca29703 AV |
4594 | } |
4595 | return ret; | |
1da177e4 LT |
4596 | } |
4597 | ||
4598 | /** | |
4599 | * qla2x00_module_exit - Module cleanup. | |
4600 | **/ | |
4601 | static void __exit | |
4602 | qla2x00_module_exit(void) | |
4603 | { | |
6a03b4cd | 4604 | unregister_chrdev(apidev_major, QLA2XXX_APIDEV); |
7ee61397 | 4605 | pci_unregister_driver(&qla2xxx_pci_driver); |
5433383e | 4606 | qla2x00_release_firmware(); |
354d6b21 | 4607 | kmem_cache_destroy(srb_cachep); |
2d70c103 | 4608 | qlt_exit(); |
a9083016 GM |
4609 | if (ctx_cachep) |
4610 | kmem_cache_destroy(ctx_cachep); | |
1da177e4 | 4611 | fc_release_transport(qla2xxx_transport_template); |
2c3dfe3f | 4612 | fc_release_transport(qla2xxx_transport_vport_template); |
1da177e4 LT |
4613 | } |
4614 | ||
4615 | module_init(qla2x00_module_init); | |
4616 | module_exit(qla2x00_module_exit); | |
4617 | ||
4618 | MODULE_AUTHOR("QLogic Corporation"); | |
4619 | MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); | |
4620 | MODULE_LICENSE("GPL"); | |
4621 | MODULE_VERSION(QLA2XXX_VERSION); | |
bb8ee499 AV |
4622 | MODULE_FIRMWARE(FW_FILE_ISP21XX); |
4623 | MODULE_FIRMWARE(FW_FILE_ISP22XX); | |
4624 | MODULE_FIRMWARE(FW_FILE_ISP2300); | |
4625 | MODULE_FIRMWARE(FW_FILE_ISP2322); | |
4626 | MODULE_FIRMWARE(FW_FILE_ISP24XX); | |
61623fc3 | 4627 | MODULE_FIRMWARE(FW_FILE_ISP25XX); |