Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
fa90c54f | 2 | * QLogic Fibre Channel HBA Driver |
bd21eaf9 | 3 | * Copyright (c) 2003-2014 QLogic Corporation |
1da177e4 | 4 | * |
fa90c54f | 5 | * See LICENSE.qla2xxx for copyright and licensing details. |
1da177e4 LT |
6 | */ |
7 | #include "qla_def.h" | |
8 | ||
9 | #include <linux/moduleparam.h> | |
10 | #include <linux/vmalloc.h> | |
1da177e4 | 11 | #include <linux/delay.h> |
39a11240 | 12 | #include <linux/kthread.h> |
e1e82b6f | 13 | #include <linux/mutex.h> |
3420d36c | 14 | #include <linux/kobject.h> |
5a0e3ad6 | 15 | #include <linux/slab.h> |
1da177e4 LT |
16 | #include <scsi/scsi_tcq.h> |
17 | #include <scsi/scsicam.h> | |
18 | #include <scsi/scsi_transport.h> | |
19 | #include <scsi/scsi_transport_fc.h> | |
20 | ||
2d70c103 NB |
21 | #include "qla_target.h" |
22 | ||
1da177e4 LT |
23 | /* |
24 | * Driver version | |
25 | */ | |
26 | char qla2x00_version_str[40]; | |
27 | ||
6a03b4cd HZ |
28 | static int apidev_major; |
29 | ||
1da177e4 LT |
30 | /* |
31 | * SRB allocation cache | |
32 | */ | |
e18b890b | 33 | static struct kmem_cache *srb_cachep; |
1da177e4 | 34 | |
a9083016 GM |
35 | /* |
36 | * CT6 CTX allocation cache | |
37 | */ | |
38 | static struct kmem_cache *ctx_cachep; | |
3ce8866c SK |
39 | /* |
40 | * error level for logging | |
41 | */ | |
42 | int ql_errlev = ql_log_all; | |
a9083016 | 43 | |
fa492630 | 44 | static int ql2xenableclass2; |
2d70c103 NB |
45 | module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); |
46 | MODULE_PARM_DESC(ql2xenableclass2, | |
47 | "Specify if Class 2 operations are supported from the very " | |
48 | "beginning. Default is 0 - class 2 not supported."); | |
49 | ||
8ae6d9c7 | 50 | |
1da177e4 | 51 | int ql2xlogintimeout = 20; |
f2019cb1 | 52 | module_param(ql2xlogintimeout, int, S_IRUGO); |
1da177e4 LT |
53 | MODULE_PARM_DESC(ql2xlogintimeout, |
54 | "Login timeout value in seconds."); | |
55 | ||
a7b61842 | 56 | int qlport_down_retry; |
f2019cb1 | 57 | module_param(qlport_down_retry, int, S_IRUGO); |
1da177e4 | 58 | MODULE_PARM_DESC(qlport_down_retry, |
900d9f98 | 59 | "Maximum number of command retries to a port that returns " |
1da177e4 LT |
60 | "a PORT-DOWN status."); |
61 | ||
1da177e4 LT |
62 | int ql2xplogiabsentdevice; |
63 | module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); | |
64 | MODULE_PARM_DESC(ql2xplogiabsentdevice, | |
65 | "Option to enable PLOGI to devices that are not present after " | |
900d9f98 | 66 | "a Fabric scan. This is needed for several broken switches. " |
1da177e4 LT |
67 | "Default is 0 - no PLOGI. 1 - perfom PLOGI."); |
68 | ||
1da177e4 | 69 | int ql2xloginretrycount = 0; |
f2019cb1 | 70 | module_param(ql2xloginretrycount, int, S_IRUGO); |
1da177e4 LT |
71 | MODULE_PARM_DESC(ql2xloginretrycount, |
72 | "Specify an alternate value for the NVRAM login retry count."); | |
73 | ||
a7a167bf | 74 | int ql2xallocfwdump = 1; |
f2019cb1 | 75 | module_param(ql2xallocfwdump, int, S_IRUGO); |
a7a167bf AV |
76 | MODULE_PARM_DESC(ql2xallocfwdump, |
77 | "Option to enable allocation of memory for a firmware dump " | |
78 | "during HBA initialization. Memory allocation requirements " | |
79 | "vary by ISP type. Default is 1 - allocate memory."); | |
80 | ||
11010fec | 81 | int ql2xextended_error_logging; |
27d94035 | 82 | module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); |
a2b3e01d | 83 | module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); |
11010fec | 84 | MODULE_PARM_DESC(ql2xextended_error_logging, |
3ce8866c SK |
85 | "Option to enable extended error logging,\n" |
86 | "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" | |
87 | "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" | |
88 | "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" | |
89 | "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" | |
90 | "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" | |
91 | "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" | |
92 | "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" | |
93 | "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" | |
29f9f90c CD |
94 | "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" |
95 | "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" | |
3ce8866c | 96 | "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" |
cfb0919c CD |
97 | "\t\t0x1e400000 - Preferred value for capturing essential " |
98 | "debug information (equivalent to old " | |
99 | "ql2xextended_error_logging=1).\n" | |
3ce8866c | 100 | "\t\tDo LOGICAL OR of the value to enable more than one level"); |
0181944f | 101 | |
a9083016 | 102 | int ql2xshiftctondsd = 6; |
f2019cb1 | 103 | module_param(ql2xshiftctondsd, int, S_IRUGO); |
a9083016 GM |
104 | MODULE_PARM_DESC(ql2xshiftctondsd, |
105 | "Set to control shifting of command type processing " | |
106 | "based on total number of SG elements."); | |
107 | ||
7e47e5ca | 108 | int ql2xfdmienable=1; |
de187df8 | 109 | module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); |
a2b3e01d | 110 | module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); |
cca5335c | 111 | MODULE_PARM_DESC(ql2xfdmienable, |
7794a5af FW |
112 | "Enables FDMI registrations. " |
113 | "0 - no FDMI. Default is 1 - perform FDMI."); | |
cca5335c | 114 | |
50280c01 CD |
115 | #define MAX_Q_DEPTH 32 |
116 | static int ql2xmaxqdepth = MAX_Q_DEPTH; | |
df7baa50 AV |
117 | module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); |
118 | MODULE_PARM_DESC(ql2xmaxqdepth, | |
e92e4a8f CD |
119 | "Maximum queue depth to set for each LUN. " |
120 | "Default is 32."); | |
df7baa50 | 121 | |
9e522cd8 AE |
122 | int ql2xenabledif = 2; |
123 | module_param(ql2xenabledif, int, S_IRUGO); | |
bad75002 | 124 | MODULE_PARM_DESC(ql2xenabledif, |
b97f5d0b SM |
125 | " Enable T10-CRC-DIF:\n" |
126 | " Default is 2.\n" | |
127 | " 0 -- No DIF Support\n" | |
128 | " 1 -- Enable DIF for all types\n" | |
129 | " 2 -- Enable DIF for all types, except Type 0.\n"); | |
bad75002 | 130 | |
8cb2049c | 131 | int ql2xenablehba_err_chk = 2; |
bad75002 AE |
132 | module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); |
133 | MODULE_PARM_DESC(ql2xenablehba_err_chk, | |
8cb2049c | 134 | " Enable T10-CRC-DIF Error isolation by HBA:\n" |
b97f5d0b | 135 | " Default is 2.\n" |
8cb2049c AE |
136 | " 0 -- Error isolation disabled\n" |
137 | " 1 -- Error isolation enabled only for DIX Type 0\n" | |
138 | " 2 -- Error isolation enabled for all Types\n"); | |
bad75002 | 139 | |
e5896bd5 | 140 | int ql2xiidmaenable=1; |
f2019cb1 | 141 | module_param(ql2xiidmaenable, int, S_IRUGO); |
e5896bd5 AV |
142 | MODULE_PARM_DESC(ql2xiidmaenable, |
143 | "Enables iIDMA settings " | |
144 | "Default is 1 - perform iIDMA. 0 - no iIDMA."); | |
145 | ||
73208dfd | 146 | int ql2xmaxqueues = 1; |
f2019cb1 | 147 | module_param(ql2xmaxqueues, int, S_IRUGO); |
73208dfd AC |
148 | MODULE_PARM_DESC(ql2xmaxqueues, |
149 | "Enables MQ settings " | |
ae68230c JP |
150 | "Default is 1 for single queue. Set it to number " |
151 | "of queues in MQ mode."); | |
68ca949c AC |
152 | |
153 | int ql2xmultique_tag; | |
f2019cb1 | 154 | module_param(ql2xmultique_tag, int, S_IRUGO); |
68ca949c AC |
155 | MODULE_PARM_DESC(ql2xmultique_tag, |
156 | "Enables CPU affinity settings for the driver " | |
157 | "Default is 0 for no affinity of request and response IO. " | |
158 | "Set it to 1 to turn on the cpu affinity."); | |
e337d907 AV |
159 | |
160 | int ql2xfwloadbin; | |
86e45bf6 | 161 | module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); |
a2b3e01d | 162 | module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); |
e337d907 | 163 | MODULE_PARM_DESC(ql2xfwloadbin, |
7c3df132 SK |
164 | "Option to specify location from which to load ISP firmware:.\n" |
165 | " 2 -- load firmware via the request_firmware() (hotplug).\n" | |
e337d907 AV |
166 | " interface.\n" |
167 | " 1 -- load firmware from flash.\n" | |
168 | " 0 -- use default semantics.\n"); | |
169 | ||
ae97c91e | 170 | int ql2xetsenable; |
f2019cb1 | 171 | module_param(ql2xetsenable, int, S_IRUGO); |
ae97c91e AV |
172 | MODULE_PARM_DESC(ql2xetsenable, |
173 | "Enables firmware ETS burst." | |
174 | "Default is 0 - skip ETS enablement."); | |
175 | ||
6907869d | 176 | int ql2xdbwr = 1; |
86e45bf6 | 177 | module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); |
a9083016 | 178 | MODULE_PARM_DESC(ql2xdbwr, |
08de2844 GM |
179 | "Option to specify scheme for request queue posting.\n" |
180 | " 0 -- Regular doorbell.\n" | |
181 | " 1 -- CAMRAM doorbell (faster).\n"); | |
a9083016 | 182 | |
f4c496c1 | 183 | int ql2xtargetreset = 1; |
f2019cb1 | 184 | module_param(ql2xtargetreset, int, S_IRUGO); |
f4c496c1 GM |
185 | MODULE_PARM_DESC(ql2xtargetreset, |
186 | "Enable target reset." | |
187 | "Default is 1 - use hw defaults."); | |
188 | ||
4da26e16 | 189 | int ql2xgffidenable; |
f2019cb1 | 190 | module_param(ql2xgffidenable, int, S_IRUGO); |
4da26e16 CD |
191 | MODULE_PARM_DESC(ql2xgffidenable, |
192 | "Enables GFF_ID checks of port type. " | |
193 | "Default is 0 - Do not use GFF_ID information."); | |
a9083016 | 194 | |
3822263e | 195 | int ql2xasynctmfenable; |
f2019cb1 | 196 | module_param(ql2xasynctmfenable, int, S_IRUGO); |
3822263e MI |
197 | MODULE_PARM_DESC(ql2xasynctmfenable, |
198 | "Enables issue of TM IOCBs asynchronously via IOCB mechanism" | |
199 | "Default is 0 - Issue TM IOCBs via mailbox mechanism."); | |
ed0de87c GM |
200 | |
201 | int ql2xdontresethba; | |
86e45bf6 | 202 | module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); |
ed0de87c | 203 | MODULE_PARM_DESC(ql2xdontresethba, |
08de2844 GM |
204 | "Option to specify reset behaviour.\n" |
205 | " 0 (Default) -- Reset on failure.\n" | |
206 | " 1 -- Do not reset on failure.\n"); | |
ed0de87c | 207 | |
1abf635d HR |
208 | uint64_t ql2xmaxlun = MAX_LUNS; |
209 | module_param(ql2xmaxlun, ullong, S_IRUGO); | |
82515920 AV |
210 | MODULE_PARM_DESC(ql2xmaxlun, |
211 | "Defines the maximum LU number to register with the SCSI " | |
212 | "midlayer. Default is 65535."); | |
213 | ||
08de2844 GM |
214 | int ql2xmdcapmask = 0x1F; |
215 | module_param(ql2xmdcapmask, int, S_IRUGO); | |
216 | MODULE_PARM_DESC(ql2xmdcapmask, | |
217 | "Set the Minidump driver capture mask level. " | |
6e96fa7b | 218 | "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); |
08de2844 | 219 | |
3aadff35 | 220 | int ql2xmdenable = 1; |
08de2844 GM |
221 | module_param(ql2xmdenable, int, S_IRUGO); |
222 | MODULE_PARM_DESC(ql2xmdenable, | |
223 | "Enable/disable MiniDump. " | |
3aadff35 GM |
224 | "0 - MiniDump disabled. " |
225 | "1 (Default) - MiniDump enabled."); | |
08de2844 | 226 | |
b0d6cabd HM |
227 | int ql2xexlogins = 0; |
228 | module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); | |
229 | MODULE_PARM_DESC(ql2xexlogins, | |
230 | "Number of extended Logins. " | |
231 | "0 (Default)- Disabled."); | |
232 | ||
2f56a7f1 HM |
233 | int ql2xexchoffld = 0; |
234 | module_param(ql2xexchoffld, uint, S_IRUGO|S_IWUSR); | |
235 | MODULE_PARM_DESC(ql2xexchoffld, | |
236 | "Number of exchanges to offload. " | |
237 | "0 (Default)- Disabled."); | |
238 | ||
f198cafa HM |
239 | int ql2xfwholdabts = 0; |
240 | module_param(ql2xfwholdabts, int, S_IRUGO); | |
241 | MODULE_PARM_DESC(ql2xfwholdabts, | |
242 | "Allow FW to hold status IOCB until ABTS rsp received. " | |
243 | "0 (Default) Do not set fw option. " | |
244 | "1 - Set fw option to hold ABTS."); | |
245 | ||
1da177e4 | 246 | /* |
fa2a1ce5 | 247 | * SCSI host template entry points |
1da177e4 LT |
248 | */ |
249 | static int qla2xxx_slave_configure(struct scsi_device * device); | |
f4f051eb | 250 | static int qla2xxx_slave_alloc(struct scsi_device *); |
1e99e33a AV |
251 | static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time); |
252 | static void qla2xxx_scan_start(struct Scsi_Host *); | |
f4f051eb | 253 | static void qla2xxx_slave_destroy(struct scsi_device *); |
f281233d | 254 | static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd); |
1da177e4 LT |
255 | static int qla2xxx_eh_abort(struct scsi_cmnd *); |
256 | static int qla2xxx_eh_device_reset(struct scsi_cmnd *); | |
523ec773 | 257 | static int qla2xxx_eh_target_reset(struct scsi_cmnd *); |
1da177e4 LT |
258 | static int qla2xxx_eh_bus_reset(struct scsi_cmnd *); |
259 | static int qla2xxx_eh_host_reset(struct scsi_cmnd *); | |
1da177e4 | 260 | |
1a2fbf18 | 261 | static void qla2x00_clear_drv_active(struct qla_hw_data *); |
3491255e | 262 | static void qla2x00_free_device(scsi_qla_host_t *); |
2d5a4c34 | 263 | static void qla83xx_disable_laser(scsi_qla_host_t *vha); |
ce7e4af7 | 264 | |
a5326f86 | 265 | struct scsi_host_template qla2xxx_driver_template = { |
1da177e4 | 266 | .module = THIS_MODULE, |
cb63067a | 267 | .name = QLA2XXX_DRIVER_NAME, |
a5326f86 | 268 | .queuecommand = qla2xxx_queuecommand, |
fca29703 AV |
269 | |
270 | .eh_abort_handler = qla2xxx_eh_abort, | |
271 | .eh_device_reset_handler = qla2xxx_eh_device_reset, | |
523ec773 | 272 | .eh_target_reset_handler = qla2xxx_eh_target_reset, |
fca29703 AV |
273 | .eh_bus_reset_handler = qla2xxx_eh_bus_reset, |
274 | .eh_host_reset_handler = qla2xxx_eh_host_reset, | |
275 | ||
276 | .slave_configure = qla2xxx_slave_configure, | |
277 | ||
278 | .slave_alloc = qla2xxx_slave_alloc, | |
279 | .slave_destroy = qla2xxx_slave_destroy, | |
ed677086 AV |
280 | .scan_finished = qla2xxx_scan_finished, |
281 | .scan_start = qla2xxx_scan_start, | |
db5ed4df | 282 | .change_queue_depth = scsi_change_queue_depth, |
fca29703 AV |
283 | .this_id = -1, |
284 | .cmd_per_lun = 3, | |
285 | .use_clustering = ENABLE_CLUSTERING, | |
286 | .sg_tablesize = SG_ALL, | |
287 | ||
288 | .max_sectors = 0xFFFF, | |
afb046e2 | 289 | .shost_attrs = qla2x00_host_attrs, |
2d70c103 NB |
290 | |
291 | .supported_mode = MODE_INITIATOR, | |
c40ecc12 | 292 | .track_queue_depth = 1, |
fca29703 AV |
293 | }; |
294 | ||
1da177e4 | 295 | static struct scsi_transport_template *qla2xxx_transport_template = NULL; |
2c3dfe3f | 296 | struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; |
1da177e4 | 297 | |
1da177e4 LT |
298 | /* TODO Convert to inlines |
299 | * | |
300 | * Timer routines | |
301 | */ | |
1da177e4 | 302 | |
2c3dfe3f | 303 | __inline__ void |
e315cd28 | 304 | qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval) |
1da177e4 | 305 | { |
e315cd28 AC |
306 | init_timer(&vha->timer); |
307 | vha->timer.expires = jiffies + interval * HZ; | |
308 | vha->timer.data = (unsigned long)vha; | |
309 | vha->timer.function = (void (*)(unsigned long))func; | |
310 | add_timer(&vha->timer); | |
311 | vha->timer_active = 1; | |
1da177e4 LT |
312 | } |
313 | ||
314 | static inline void | |
e315cd28 | 315 | qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) |
1da177e4 | 316 | { |
a9083016 | 317 | /* Currently used for 82XX only. */ |
7c3df132 SK |
318 | if (vha->device_flags & DFLG_DEV_FAILED) { |
319 | ql_dbg(ql_dbg_timer, vha, 0x600d, | |
320 | "Device in a failed state, returning.\n"); | |
a9083016 | 321 | return; |
7c3df132 | 322 | } |
a9083016 | 323 | |
e315cd28 | 324 | mod_timer(&vha->timer, jiffies + interval * HZ); |
1da177e4 LT |
325 | } |
326 | ||
a824ebb3 | 327 | static __inline__ void |
e315cd28 | 328 | qla2x00_stop_timer(scsi_qla_host_t *vha) |
1da177e4 | 329 | { |
e315cd28 AC |
330 | del_timer_sync(&vha->timer); |
331 | vha->timer_active = 0; | |
1da177e4 LT |
332 | } |
333 | ||
1da177e4 LT |
334 | static int qla2x00_do_dpc(void *data); |
335 | ||
336 | static void qla2x00_rst_aen(scsi_qla_host_t *); | |
337 | ||
73208dfd AC |
338 | static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, |
339 | struct req_que **, struct rsp_que **); | |
e30d1756 | 340 | static void qla2x00_free_fw_dump(struct qla_hw_data *); |
e315cd28 | 341 | static void qla2x00_mem_free(struct qla_hw_data *); |
1da177e4 | 342 | |
1da177e4 | 343 | /* -------------------------------------------------------------------------- */ |
9a347ff4 CD |
344 | static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, |
345 | struct rsp_que *rsp) | |
73208dfd | 346 | { |
7c3df132 | 347 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); |
2afa19a9 | 348 | ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues, |
73208dfd AC |
349 | GFP_KERNEL); |
350 | if (!ha->req_q_map) { | |
7c3df132 SK |
351 | ql_log(ql_log_fatal, vha, 0x003b, |
352 | "Unable to allocate memory for request queue ptrs.\n"); | |
73208dfd AC |
353 | goto fail_req_map; |
354 | } | |
355 | ||
2afa19a9 | 356 | ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues, |
73208dfd AC |
357 | GFP_KERNEL); |
358 | if (!ha->rsp_q_map) { | |
7c3df132 SK |
359 | ql_log(ql_log_fatal, vha, 0x003c, |
360 | "Unable to allocate memory for response queue ptrs.\n"); | |
73208dfd AC |
361 | goto fail_rsp_map; |
362 | } | |
9a347ff4 CD |
363 | /* |
364 | * Make sure we record at least the request and response queue zero in | |
365 | * case we need to free them if part of the probe fails. | |
366 | */ | |
367 | ha->rsp_q_map[0] = rsp; | |
368 | ha->req_q_map[0] = req; | |
73208dfd AC |
369 | set_bit(0, ha->rsp_qid_map); |
370 | set_bit(0, ha->req_qid_map); | |
371 | return 1; | |
372 | ||
373 | fail_rsp_map: | |
374 | kfree(ha->req_q_map); | |
375 | ha->req_q_map = NULL; | |
376 | fail_req_map: | |
377 | return -ENOMEM; | |
378 | } | |
379 | ||
2afa19a9 | 380 | static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) |
73208dfd | 381 | { |
8ae6d9c7 GM |
382 | if (IS_QLAFX00(ha)) { |
383 | if (req && req->ring_fx00) | |
384 | dma_free_coherent(&ha->pdev->dev, | |
385 | (req->length_fx00 + 1) * sizeof(request_t), | |
386 | req->ring_fx00, req->dma_fx00); | |
387 | } else if (req && req->ring) | |
73208dfd AC |
388 | dma_free_coherent(&ha->pdev->dev, |
389 | (req->length + 1) * sizeof(request_t), | |
390 | req->ring, req->dma); | |
391 | ||
8d93f550 CD |
392 | if (req) |
393 | kfree(req->outstanding_cmds); | |
394 | ||
73208dfd AC |
395 | kfree(req); |
396 | req = NULL; | |
397 | } | |
398 | ||
2afa19a9 AC |
399 | static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) |
400 | { | |
8ae6d9c7 GM |
401 | if (IS_QLAFX00(ha)) { |
402 | if (rsp && rsp->ring) | |
403 | dma_free_coherent(&ha->pdev->dev, | |
404 | (rsp->length_fx00 + 1) * sizeof(request_t), | |
405 | rsp->ring_fx00, rsp->dma_fx00); | |
406 | } else if (rsp && rsp->ring) { | |
2afa19a9 AC |
407 | dma_free_coherent(&ha->pdev->dev, |
408 | (rsp->length + 1) * sizeof(response_t), | |
409 | rsp->ring, rsp->dma); | |
8ae6d9c7 | 410 | } |
2afa19a9 AC |
411 | kfree(rsp); |
412 | rsp = NULL; | |
413 | } | |
414 | ||
73208dfd AC |
415 | static void qla2x00_free_queues(struct qla_hw_data *ha) |
416 | { | |
417 | struct req_que *req; | |
418 | struct rsp_que *rsp; | |
419 | int cnt; | |
420 | ||
2afa19a9 | 421 | for (cnt = 0; cnt < ha->max_req_queues; cnt++) { |
cb43285f QT |
422 | if (!test_bit(cnt, ha->req_qid_map)) |
423 | continue; | |
424 | ||
73208dfd | 425 | req = ha->req_q_map[cnt]; |
2afa19a9 | 426 | qla2x00_free_req_que(ha, req); |
73208dfd | 427 | } |
73208dfd AC |
428 | kfree(ha->req_q_map); |
429 | ha->req_q_map = NULL; | |
2afa19a9 AC |
430 | |
431 | for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { | |
cb43285f QT |
432 | if (!test_bit(cnt, ha->rsp_qid_map)) |
433 | continue; | |
434 | ||
2afa19a9 AC |
435 | rsp = ha->rsp_q_map[cnt]; |
436 | qla2x00_free_rsp_que(ha, rsp); | |
437 | } | |
438 | kfree(ha->rsp_q_map); | |
439 | ha->rsp_q_map = NULL; | |
73208dfd AC |
440 | } |
441 | ||
68ca949c AC |
442 | static int qla25xx_setup_mode(struct scsi_qla_host *vha) |
443 | { | |
444 | uint16_t options = 0; | |
445 | int ques, req, ret; | |
446 | struct qla_hw_data *ha = vha->hw; | |
447 | ||
7163ea81 | 448 | if (!(ha->fw_attributes & BIT_6)) { |
7c3df132 SK |
449 | ql_log(ql_log_warn, vha, 0x00d8, |
450 | "Firmware is not multi-queue capable.\n"); | |
7163ea81 AC |
451 | goto fail; |
452 | } | |
68ca949c | 453 | if (ql2xmultique_tag) { |
68ca949c AC |
454 | /* create a request queue for IO */ |
455 | options |= BIT_7; | |
456 | req = qla25xx_create_req_que(ha, options, 0, 0, -1, | |
457 | QLA_DEFAULT_QUE_QOS); | |
458 | if (!req) { | |
7c3df132 SK |
459 | ql_log(ql_log_warn, vha, 0x00e0, |
460 | "Failed to create request queue.\n"); | |
68ca949c AC |
461 | goto fail; |
462 | } | |
278274d5 | 463 | ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1); |
68ca949c AC |
464 | vha->req = ha->req_q_map[req]; |
465 | options |= BIT_1; | |
466 | for (ques = 1; ques < ha->max_rsp_queues; ques++) { | |
467 | ret = qla25xx_create_rsp_que(ha, options, 0, 0, req); | |
468 | if (!ret) { | |
7c3df132 SK |
469 | ql_log(ql_log_warn, vha, 0x00e8, |
470 | "Failed to create response queue.\n"); | |
68ca949c AC |
471 | goto fail2; |
472 | } | |
473 | } | |
7163ea81 | 474 | ha->flags.cpu_affinity_enabled = 1; |
7c3df132 | 475 | ql_dbg(ql_dbg_multiq, vha, 0xc007, |
6ef68da7 | 476 | "CPU affinity mode enabled, " |
7c3df132 SK |
477 | "no. of response queues:%d no. of request queues:%d.\n", |
478 | ha->max_rsp_queues, ha->max_req_queues); | |
479 | ql_dbg(ql_dbg_init, vha, 0x00e9, | |
6ef68da7 | 480 | "CPU affinity mode enabled, " |
7c3df132 SK |
481 | "no. of response queues:%d no. of request queues:%d.\n", |
482 | ha->max_rsp_queues, ha->max_req_queues); | |
68ca949c AC |
483 | } |
484 | return 0; | |
485 | fail2: | |
486 | qla25xx_delete_queues(vha); | |
7163ea81 AC |
487 | destroy_workqueue(ha->wq); |
488 | ha->wq = NULL; | |
0cd33fcf | 489 | vha->req = ha->req_q_map[0]; |
68ca949c AC |
490 | fail: |
491 | ha->mqenable = 0; | |
7163ea81 AC |
492 | kfree(ha->req_q_map); |
493 | kfree(ha->rsp_q_map); | |
494 | ha->max_req_queues = ha->max_rsp_queues = 1; | |
68ca949c AC |
495 | return 1; |
496 | } | |
497 | ||
1da177e4 | 498 | static char * |
e315cd28 | 499 | qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str) |
1da177e4 | 500 | { |
e315cd28 | 501 | struct qla_hw_data *ha = vha->hw; |
1da177e4 LT |
502 | static char *pci_bus_modes[] = { |
503 | "33", "66", "100", "133", | |
504 | }; | |
505 | uint16_t pci_bus; | |
506 | ||
507 | strcpy(str, "PCI"); | |
508 | pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; | |
509 | if (pci_bus) { | |
510 | strcat(str, "-X ("); | |
511 | strcat(str, pci_bus_modes[pci_bus]); | |
512 | } else { | |
513 | pci_bus = (ha->pci_attr & BIT_8) >> 8; | |
514 | strcat(str, " ("); | |
515 | strcat(str, pci_bus_modes[pci_bus]); | |
516 | } | |
517 | strcat(str, " MHz)"); | |
518 | ||
519 | return (str); | |
520 | } | |
521 | ||
fca29703 | 522 | static char * |
e315cd28 | 523 | qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str) |
fca29703 AV |
524 | { |
525 | static char *pci_bus_modes[] = { "33", "66", "100", "133", }; | |
e315cd28 | 526 | struct qla_hw_data *ha = vha->hw; |
fca29703 | 527 | uint32_t pci_bus; |
fca29703 | 528 | |
62a276f8 | 529 | if (pci_is_pcie(ha->pdev)) { |
fca29703 | 530 | char lwstr[6]; |
62a276f8 | 531 | uint32_t lstat, lspeed, lwidth; |
fca29703 | 532 | |
62a276f8 BH |
533 | pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); |
534 | lspeed = lstat & PCI_EXP_LNKCAP_SLS; | |
535 | lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; | |
fca29703 AV |
536 | |
537 | strcpy(str, "PCIe ("); | |
49300af7 SK |
538 | switch (lspeed) { |
539 | case 1: | |
c87a0d8c | 540 | strcat(str, "2.5GT/s "); |
49300af7 SK |
541 | break; |
542 | case 2: | |
c87a0d8c | 543 | strcat(str, "5.0GT/s "); |
49300af7 SK |
544 | break; |
545 | case 3: | |
546 | strcat(str, "8.0GT/s "); | |
547 | break; | |
548 | default: | |
fca29703 | 549 | strcat(str, "<unknown> "); |
49300af7 SK |
550 | break; |
551 | } | |
fca29703 AV |
552 | snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth); |
553 | strcat(str, lwstr); | |
554 | ||
555 | return str; | |
556 | } | |
557 | ||
558 | strcpy(str, "PCI"); | |
559 | pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; | |
560 | if (pci_bus == 0 || pci_bus == 8) { | |
561 | strcat(str, " ("); | |
562 | strcat(str, pci_bus_modes[pci_bus >> 3]); | |
563 | } else { | |
564 | strcat(str, "-X "); | |
565 | if (pci_bus & BIT_2) | |
566 | strcat(str, "Mode 2"); | |
567 | else | |
568 | strcat(str, "Mode 1"); | |
569 | strcat(str, " ("); | |
570 | strcat(str, pci_bus_modes[pci_bus & ~BIT_2]); | |
571 | } | |
572 | strcat(str, " MHz)"); | |
573 | ||
574 | return str; | |
575 | } | |
576 | ||
e5f82ab8 | 577 | static char * |
df57caba | 578 | qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) |
1da177e4 LT |
579 | { |
580 | char un_str[10]; | |
e315cd28 | 581 | struct qla_hw_data *ha = vha->hw; |
fa2a1ce5 | 582 | |
df57caba HM |
583 | snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, |
584 | ha->fw_minor_version, ha->fw_subminor_version); | |
1da177e4 LT |
585 | |
586 | if (ha->fw_attributes & BIT_9) { | |
587 | strcat(str, "FLX"); | |
588 | return (str); | |
589 | } | |
590 | ||
591 | switch (ha->fw_attributes & 0xFF) { | |
592 | case 0x7: | |
593 | strcat(str, "EF"); | |
594 | break; | |
595 | case 0x17: | |
596 | strcat(str, "TP"); | |
597 | break; | |
598 | case 0x37: | |
599 | strcat(str, "IP"); | |
600 | break; | |
601 | case 0x77: | |
602 | strcat(str, "VI"); | |
603 | break; | |
604 | default: | |
605 | sprintf(un_str, "(%x)", ha->fw_attributes); | |
606 | strcat(str, un_str); | |
607 | break; | |
608 | } | |
609 | if (ha->fw_attributes & 0x100) | |
610 | strcat(str, "X"); | |
611 | ||
612 | return (str); | |
613 | } | |
614 | ||
e5f82ab8 | 615 | static char * |
df57caba | 616 | qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) |
fca29703 | 617 | { |
e315cd28 | 618 | struct qla_hw_data *ha = vha->hw; |
f0883ac6 | 619 | |
df57caba | 620 | snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, |
3a03eb79 | 621 | ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); |
fca29703 | 622 | return str; |
fca29703 AV |
623 | } |
624 | ||
9ba56b95 GM |
625 | void |
626 | qla2x00_sp_free_dma(void *vha, void *ptr) | |
fca29703 | 627 | { |
9ba56b95 GM |
628 | srb_t *sp = (srb_t *)ptr; |
629 | struct scsi_cmnd *cmd = GET_CMD_SP(sp); | |
630 | struct qla_hw_data *ha = sp->fcport->vha->hw; | |
631 | void *ctx = GET_CMD_CTX_SP(sp); | |
fca29703 | 632 | |
9ba56b95 GM |
633 | if (sp->flags & SRB_DMA_VALID) { |
634 | scsi_dma_unmap(cmd); | |
635 | sp->flags &= ~SRB_DMA_VALID; | |
7c3df132 | 636 | } |
fca29703 | 637 | |
9ba56b95 GM |
638 | if (sp->flags & SRB_CRC_PROT_DMA_VALID) { |
639 | dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), | |
640 | scsi_prot_sg_count(cmd), cmd->sc_data_direction); | |
641 | sp->flags &= ~SRB_CRC_PROT_DMA_VALID; | |
642 | } | |
643 | ||
644 | if (sp->flags & SRB_CRC_CTX_DSD_VALID) { | |
645 | /* List assured to be having elements */ | |
f83adb61 | 646 | qla2x00_clean_dsd_pool(ha, sp, NULL); |
9ba56b95 GM |
647 | sp->flags &= ~SRB_CRC_CTX_DSD_VALID; |
648 | } | |
649 | ||
650 | if (sp->flags & SRB_CRC_CTX_DMA_VALID) { | |
651 | dma_pool_free(ha->dl_dma_pool, ctx, | |
652 | ((struct crc_context *)ctx)->crc_ctx_dma); | |
653 | sp->flags &= ~SRB_CRC_CTX_DMA_VALID; | |
654 | } | |
655 | ||
656 | if (sp->flags & SRB_FCP_CMND_DMA_VALID) { | |
657 | struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx; | |
fca29703 | 658 | |
9ba56b95 GM |
659 | dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, |
660 | ctx1->fcp_cmnd_dma); | |
661 | list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); | |
662 | ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; | |
663 | ha->gbl_dsd_avail += ctx1->dsd_use_cnt; | |
664 | mempool_free(ctx1, ha->ctx_mempool); | |
665 | ctx1 = NULL; | |
666 | } | |
667 | ||
668 | CMD_SP(cmd) = NULL; | |
b00ee7d7 | 669 | qla2x00_rel_sp(sp->fcport->vha, sp); |
9ba56b95 GM |
670 | } |
671 | ||
14b06808 | 672 | static void |
9ba56b95 GM |
673 | qla2x00_sp_compl(void *data, void *ptr, int res) |
674 | { | |
675 | struct qla_hw_data *ha = (struct qla_hw_data *)data; | |
676 | srb_t *sp = (srb_t *)ptr; | |
677 | struct scsi_cmnd *cmd = GET_CMD_SP(sp); | |
678 | ||
679 | cmd->result = res; | |
680 | ||
681 | if (atomic_read(&sp->ref_count) == 0) { | |
682 | ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015, | |
683 | "SP reference-count to ZERO -- sp=%p cmd=%p.\n", | |
684 | sp, GET_CMD_SP(sp)); | |
685 | if (ql2xextended_error_logging & ql_dbg_io) | |
8fbdac8c | 686 | WARN_ON(atomic_read(&sp->ref_count) == 0); |
9ba56b95 GM |
687 | return; |
688 | } | |
689 | if (!atomic_dec_and_test(&sp->ref_count)) | |
690 | return; | |
691 | ||
692 | qla2x00_sp_free_dma(ha, sp); | |
693 | cmd->scsi_done(cmd); | |
fca29703 AV |
694 | } |
695 | ||
8ae6d9c7 GM |
696 | /* If we are SP1 here, we need to still take and release the host_lock as SP1 |
697 | * does not have the changes necessary to avoid taking host->host_lock. | |
698 | */ | |
1da177e4 | 699 | static int |
f5e3e40b | 700 | qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) |
fca29703 | 701 | { |
134ae078 | 702 | scsi_qla_host_t *vha = shost_priv(host); |
fca29703 | 703 | fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; |
19a7b4ae | 704 | struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); |
e315cd28 AC |
705 | struct qla_hw_data *ha = vha->hw; |
706 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); | |
fca29703 AV |
707 | srb_t *sp; |
708 | int rval; | |
709 | ||
85880801 | 710 | if (ha->flags.eeh_busy) { |
7c3df132 | 711 | if (ha->flags.pci_channel_io_perm_failure) { |
5f28d2d7 | 712 | ql_dbg(ql_dbg_aer, vha, 0x9010, |
7c3df132 SK |
713 | "PCI Channel IO permanent failure, exiting " |
714 | "cmd=%p.\n", cmd); | |
b9b12f73 | 715 | cmd->result = DID_NO_CONNECT << 16; |
7c3df132 | 716 | } else { |
5f28d2d7 | 717 | ql_dbg(ql_dbg_aer, vha, 0x9011, |
7c3df132 | 718 | "EEH_Busy, Requeuing the cmd=%p.\n", cmd); |
85880801 | 719 | cmd->result = DID_REQUEUE << 16; |
7c3df132 | 720 | } |
14e660e6 SJ |
721 | goto qc24_fail_command; |
722 | } | |
723 | ||
19a7b4ae JSEC |
724 | rval = fc_remote_port_chkready(rport); |
725 | if (rval) { | |
726 | cmd->result = rval; | |
5f28d2d7 | 727 | ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, |
7c3df132 SK |
728 | "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", |
729 | cmd, rval); | |
fca29703 AV |
730 | goto qc24_fail_command; |
731 | } | |
732 | ||
bad75002 AE |
733 | if (!vha->flags.difdix_supported && |
734 | scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { | |
7c3df132 SK |
735 | ql_dbg(ql_dbg_io, vha, 0x3004, |
736 | "DIF Cap not reg, fail DIF capable cmd's:%p.\n", | |
737 | cmd); | |
bad75002 AE |
738 | cmd->result = DID_NO_CONNECT << 16; |
739 | goto qc24_fail_command; | |
740 | } | |
aa651be8 CD |
741 | |
742 | if (!fcport) { | |
743 | cmd->result = DID_NO_CONNECT << 16; | |
744 | goto qc24_fail_command; | |
745 | } | |
746 | ||
fca29703 AV |
747 | if (atomic_read(&fcport->state) != FCS_ONLINE) { |
748 | if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || | |
38170fa8 | 749 | atomic_read(&base_vha->loop_state) == LOOP_DEAD) { |
7c3df132 SK |
750 | ql_dbg(ql_dbg_io, vha, 0x3005, |
751 | "Returning DNC, fcport_state=%d loop_state=%d.\n", | |
752 | atomic_read(&fcport->state), | |
753 | atomic_read(&base_vha->loop_state)); | |
fca29703 AV |
754 | cmd->result = DID_NO_CONNECT << 16; |
755 | goto qc24_fail_command; | |
756 | } | |
7b594131 | 757 | goto qc24_target_busy; |
fca29703 AV |
758 | } |
759 | ||
e05fe292 CD |
760 | /* |
761 | * Return target busy if we've received a non-zero retry_delay_timer | |
762 | * in a FCP_RSP. | |
763 | */ | |
975f7d46 BP |
764 | if (fcport->retry_delay_timestamp == 0) { |
765 | /* retry delay not set */ | |
766 | } else if (time_after(jiffies, fcport->retry_delay_timestamp)) | |
e05fe292 CD |
767 | fcport->retry_delay_timestamp = 0; |
768 | else | |
769 | goto qc24_target_busy; | |
770 | ||
b00ee7d7 | 771 | sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC); |
50280c01 | 772 | if (!sp) |
f5e3e40b | 773 | goto qc24_host_busy; |
fca29703 | 774 | |
9ba56b95 GM |
775 | sp->u.scmd.cmd = cmd; |
776 | sp->type = SRB_SCSI_CMD; | |
777 | atomic_set(&sp->ref_count, 1); | |
778 | CMD_SP(cmd) = (void *)sp; | |
779 | sp->free = qla2x00_sp_free_dma; | |
780 | sp->done = qla2x00_sp_compl; | |
781 | ||
e315cd28 | 782 | rval = ha->isp_ops->start_scsi(sp); |
7c3df132 | 783 | if (rval != QLA_SUCCESS) { |
53016ed3 | 784 | ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, |
7c3df132 | 785 | "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); |
fca29703 | 786 | goto qc24_host_busy_free_sp; |
7c3df132 | 787 | } |
fca29703 | 788 | |
fca29703 AV |
789 | return 0; |
790 | ||
791 | qc24_host_busy_free_sp: | |
9ba56b95 | 792 | qla2x00_sp_free_dma(ha, sp); |
fca29703 | 793 | |
f5e3e40b | 794 | qc24_host_busy: |
fca29703 AV |
795 | return SCSI_MLQUEUE_HOST_BUSY; |
796 | ||
7b594131 MC |
797 | qc24_target_busy: |
798 | return SCSI_MLQUEUE_TARGET_BUSY; | |
799 | ||
fca29703 | 800 | qc24_fail_command: |
f5e3e40b | 801 | cmd->scsi_done(cmd); |
fca29703 AV |
802 | |
803 | return 0; | |
804 | } | |
805 | ||
1da177e4 LT |
806 | /* |
807 | * qla2x00_eh_wait_on_command | |
808 | * Waits for the command to be returned by the Firmware for some | |
809 | * max time. | |
810 | * | |
811 | * Input: | |
1da177e4 | 812 | * cmd = Scsi Command to wait on. |
1da177e4 LT |
813 | * |
814 | * Return: | |
815 | * Not Found : 0 | |
816 | * Found : 1 | |
817 | */ | |
818 | static int | |
e315cd28 | 819 | qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) |
1da177e4 | 820 | { |
fe74c71f | 821 | #define ABORT_POLLING_PERIOD 1000 |
478c3b03 | 822 | #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) |
f4f051eb | 823 | unsigned long wait_iter = ABORT_WAIT_ITER; |
85880801 AV |
824 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
825 | struct qla_hw_data *ha = vha->hw; | |
f4f051eb | 826 | int ret = QLA_SUCCESS; |
1da177e4 | 827 | |
85880801 | 828 | if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { |
7c3df132 SK |
829 | ql_dbg(ql_dbg_taskm, vha, 0x8005, |
830 | "Return:eh_wait.\n"); | |
85880801 AV |
831 | return ret; |
832 | } | |
833 | ||
d970432c | 834 | while (CMD_SP(cmd) && wait_iter--) { |
fe74c71f | 835 | msleep(ABORT_POLLING_PERIOD); |
f4f051eb | 836 | } |
837 | if (CMD_SP(cmd)) | |
838 | ret = QLA_FUNCTION_FAILED; | |
1da177e4 | 839 | |
f4f051eb | 840 | return ret; |
1da177e4 LT |
841 | } |
842 | ||
843 | /* | |
844 | * qla2x00_wait_for_hba_online | |
fa2a1ce5 | 845 | * Wait till the HBA is online after going through |
1da177e4 LT |
846 | * <= MAX_RETRIES_OF_ISP_ABORT or |
847 | * finally HBA is disabled ie marked offline | |
848 | * | |
849 | * Input: | |
850 | * ha - pointer to host adapter structure | |
fa2a1ce5 AV |
851 | * |
852 | * Note: | |
1da177e4 LT |
853 | * Does context switching-Release SPIN_LOCK |
854 | * (if any) before calling this routine. | |
855 | * | |
856 | * Return: | |
857 | * Success (Adapter is online) : 0 | |
858 | * Failed (Adapter is offline/disabled) : 1 | |
859 | */ | |
854165f4 | 860 | int |
e315cd28 | 861 | qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) |
1da177e4 | 862 | { |
fca29703 AV |
863 | int return_status; |
864 | unsigned long wait_online; | |
e315cd28 AC |
865 | struct qla_hw_data *ha = vha->hw; |
866 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); | |
1da177e4 | 867 | |
fa2a1ce5 | 868 | wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); |
e315cd28 AC |
869 | while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || |
870 | test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || | |
871 | test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || | |
872 | ha->dpc_active) && time_before(jiffies, wait_online)) { | |
1da177e4 LT |
873 | |
874 | msleep(1000); | |
875 | } | |
e315cd28 | 876 | if (base_vha->flags.online) |
fa2a1ce5 | 877 | return_status = QLA_SUCCESS; |
1da177e4 LT |
878 | else |
879 | return_status = QLA_FUNCTION_FAILED; | |
880 | ||
1da177e4 LT |
881 | return (return_status); |
882 | } | |
883 | ||
86fbee86 | 884 | /* |
638a1a01 SC |
885 | * qla2x00_wait_for_hba_ready |
886 | * Wait till the HBA is ready before doing driver unload | |
86fbee86 LC |
887 | * |
888 | * Input: | |
889 | * ha - pointer to host adapter structure | |
890 | * | |
891 | * Note: | |
892 | * Does context switching-Release SPIN_LOCK | |
893 | * (if any) before calling this routine. | |
894 | * | |
86fbee86 | 895 | */ |
638a1a01 SC |
896 | static void |
897 | qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) | |
86fbee86 | 898 | { |
86fbee86 | 899 | struct qla_hw_data *ha = vha->hw; |
783e0dc4 | 900 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); |
86fbee86 | 901 | |
9d35894d SC |
902 | while (((qla2x00_reset_active(vha)) || ha->dpc_active || |
903 | ha->flags.mbox_busy) || | |
904 | test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || | |
783e0dc4 SC |
905 | test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) { |
906 | if (test_bit(UNLOADING, &base_vha->dpc_flags)) | |
907 | break; | |
86fbee86 | 908 | msleep(1000); |
783e0dc4 | 909 | } |
86fbee86 LC |
910 | } |
911 | ||
2533cf67 LC |
912 | int |
913 | qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) | |
914 | { | |
915 | int return_status; | |
916 | unsigned long wait_reset; | |
917 | struct qla_hw_data *ha = vha->hw; | |
918 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); | |
919 | ||
920 | wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); | |
921 | while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || | |
922 | test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || | |
923 | test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || | |
924 | ha->dpc_active) && time_before(jiffies, wait_reset)) { | |
925 | ||
926 | msleep(1000); | |
927 | ||
928 | if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && | |
929 | ha->flags.chip_reset_done) | |
930 | break; | |
931 | } | |
932 | if (ha->flags.chip_reset_done) | |
933 | return_status = QLA_SUCCESS; | |
934 | else | |
935 | return_status = QLA_FUNCTION_FAILED; | |
936 | ||
937 | return return_status; | |
938 | } | |
939 | ||
083a469d GM |
940 | static void |
941 | sp_get(struct srb *sp) | |
942 | { | |
943 | atomic_inc(&sp->ref_count); | |
944 | } | |
945 | ||
a465537a SC |
946 | #define ISP_REG_DISCONNECT 0xffffffffU |
947 | /************************************************************************** | |
948 | * qla2x00_isp_reg_stat | |
949 | * | |
950 | * Description: | |
951 | * Read the host status register of ISP before aborting the command. | |
952 | * | |
953 | * Input: | |
954 | * ha = pointer to host adapter structure. | |
955 | * | |
956 | * | |
957 | * Returns: | |
958 | * Either true or false. | |
959 | * | |
960 | * Note: Return true if there is register disconnect. | |
961 | **************************************************************************/ | |
962 | static inline | |
963 | uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha) | |
964 | { | |
965 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
966 | ||
967 | return ((RD_REG_DWORD(®->host_status)) == ISP_REG_DISCONNECT); | |
968 | } | |
969 | ||
1da177e4 LT |
970 | /************************************************************************** |
971 | * qla2xxx_eh_abort | |
972 | * | |
973 | * Description: | |
974 | * The abort function will abort the specified command. | |
975 | * | |
976 | * Input: | |
977 | * cmd = Linux SCSI command packet to be aborted. | |
978 | * | |
979 | * Returns: | |
980 | * Either SUCCESS or FAILED. | |
981 | * | |
982 | * Note: | |
2ea00202 | 983 | * Only return FAILED if command not returned by firmware. |
1da177e4 | 984 | **************************************************************************/ |
e5f82ab8 | 985 | static int |
1da177e4 LT |
986 | qla2xxx_eh_abort(struct scsi_cmnd *cmd) |
987 | { | |
e315cd28 | 988 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
f4f051eb | 989 | srb_t *sp; |
4e98d3b8 | 990 | int ret; |
9cb78c16 HR |
991 | unsigned int id; |
992 | uint64_t lun; | |
18e144d3 | 993 | unsigned long flags; |
f934c9d0 | 994 | int rval, wait = 0; |
e315cd28 | 995 | struct qla_hw_data *ha = vha->hw; |
1da177e4 | 996 | |
a465537a SC |
997 | if (qla2x00_isp_reg_stat(ha)) { |
998 | ql_log(ql_log_info, vha, 0x8042, | |
999 | "PCI/Register disconnect, exiting.\n"); | |
1000 | return FAILED; | |
1001 | } | |
f4f051eb | 1002 | if (!CMD_SP(cmd)) |
2ea00202 | 1003 | return SUCCESS; |
1da177e4 | 1004 | |
4e98d3b8 AV |
1005 | ret = fc_block_scsi_eh(cmd); |
1006 | if (ret != 0) | |
1007 | return ret; | |
1008 | ret = SUCCESS; | |
1009 | ||
f4f051eb | 1010 | id = cmd->device->id; |
1011 | lun = cmd->device->lun; | |
1da177e4 | 1012 | |
e315cd28 | 1013 | spin_lock_irqsave(&ha->hardware_lock, flags); |
170babc3 MC |
1014 | sp = (srb_t *) CMD_SP(cmd); |
1015 | if (!sp) { | |
1016 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1017 | return SUCCESS; | |
1018 | } | |
1da177e4 | 1019 | |
7c3df132 | 1020 | ql_dbg(ql_dbg_taskm, vha, 0x8002, |
c7bc4cae CD |
1021 | "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", |
1022 | vha->host_no, id, lun, sp, cmd, sp->handle); | |
17d98630 | 1023 | |
170babc3 MC |
1024 | /* Get a reference to the sp and drop the lock.*/ |
1025 | sp_get(sp); | |
083a469d | 1026 | |
e315cd28 | 1027 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
f934c9d0 CD |
1028 | rval = ha->isp_ops->abort_command(sp); |
1029 | if (rval) { | |
96219424 | 1030 | if (rval == QLA_FUNCTION_PARAMETER_ERROR) |
f934c9d0 | 1031 | ret = SUCCESS; |
96219424 | 1032 | else |
f934c9d0 CD |
1033 | ret = FAILED; |
1034 | ||
7c3df132 | 1035 | ql_dbg(ql_dbg_taskm, vha, 0x8003, |
f934c9d0 | 1036 | "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval); |
170babc3 | 1037 | } else { |
7c3df132 | 1038 | ql_dbg(ql_dbg_taskm, vha, 0x8004, |
cfb0919c | 1039 | "Abort command mbx success cmd=%p.\n", cmd); |
170babc3 MC |
1040 | wait = 1; |
1041 | } | |
75942064 SK |
1042 | |
1043 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
9ba56b95 | 1044 | sp->done(ha, sp, 0); |
75942064 | 1045 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
1da177e4 | 1046 | |
bc91ade9 CD |
1047 | /* Did the command return during mailbox execution? */ |
1048 | if (ret == FAILED && !CMD_SP(cmd)) | |
1049 | ret = SUCCESS; | |
1050 | ||
f4f051eb | 1051 | /* Wait for the command to be returned. */ |
2ea00202 | 1052 | if (wait) { |
e315cd28 | 1053 | if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) { |
7c3df132 | 1054 | ql_log(ql_log_warn, vha, 0x8006, |
cfb0919c | 1055 | "Abort handler timed out cmd=%p.\n", cmd); |
2ea00202 | 1056 | ret = FAILED; |
f4f051eb | 1057 | } |
1da177e4 | 1058 | } |
1da177e4 | 1059 | |
7c3df132 | 1060 | ql_log(ql_log_info, vha, 0x801c, |
9cb78c16 | 1061 | "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n", |
cfb0919c | 1062 | vha->host_no, id, lun, wait, ret); |
1da177e4 | 1063 | |
f4f051eb | 1064 | return ret; |
1065 | } | |
1da177e4 | 1066 | |
4d78c973 | 1067 | int |
e315cd28 | 1068 | qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, |
9cb78c16 | 1069 | uint64_t l, enum nexus_wait_type type) |
f4f051eb | 1070 | { |
17d98630 | 1071 | int cnt, match, status; |
18e144d3 | 1072 | unsigned long flags; |
e315cd28 | 1073 | struct qla_hw_data *ha = vha->hw; |
73208dfd | 1074 | struct req_que *req; |
4d78c973 | 1075 | srb_t *sp; |
9ba56b95 | 1076 | struct scsi_cmnd *cmd; |
1da177e4 | 1077 | |
523ec773 | 1078 | status = QLA_SUCCESS; |
17d98630 | 1079 | |
e315cd28 | 1080 | spin_lock_irqsave(&ha->hardware_lock, flags); |
67c2e93a | 1081 | req = vha->req; |
17d98630 | 1082 | for (cnt = 1; status == QLA_SUCCESS && |
8d93f550 | 1083 | cnt < req->num_outstanding_cmds; cnt++) { |
17d98630 AC |
1084 | sp = req->outstanding_cmds[cnt]; |
1085 | if (!sp) | |
523ec773 | 1086 | continue; |
9ba56b95 | 1087 | if (sp->type != SRB_SCSI_CMD) |
cf53b069 | 1088 | continue; |
17d98630 AC |
1089 | if (vha->vp_idx != sp->fcport->vha->vp_idx) |
1090 | continue; | |
1091 | match = 0; | |
9ba56b95 | 1092 | cmd = GET_CMD_SP(sp); |
17d98630 AC |
1093 | switch (type) { |
1094 | case WAIT_HOST: | |
1095 | match = 1; | |
1096 | break; | |
1097 | case WAIT_TARGET: | |
9ba56b95 | 1098 | match = cmd->device->id == t; |
17d98630 AC |
1099 | break; |
1100 | case WAIT_LUN: | |
9ba56b95 GM |
1101 | match = (cmd->device->id == t && |
1102 | cmd->device->lun == l); | |
17d98630 | 1103 | break; |
73208dfd | 1104 | } |
17d98630 AC |
1105 | if (!match) |
1106 | continue; | |
1107 | ||
1108 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
9ba56b95 | 1109 | status = qla2x00_eh_wait_on_command(cmd); |
17d98630 | 1110 | spin_lock_irqsave(&ha->hardware_lock, flags); |
1da177e4 | 1111 | } |
e315cd28 | 1112 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
523ec773 AV |
1113 | |
1114 | return status; | |
1da177e4 LT |
1115 | } |
1116 | ||
523ec773 AV |
1117 | static char *reset_errors[] = { |
1118 | "HBA not online", | |
1119 | "HBA not ready", | |
1120 | "Task management failed", | |
1121 | "Waiting for command completions", | |
1122 | }; | |
1da177e4 | 1123 | |
e5f82ab8 | 1124 | static int |
523ec773 | 1125 | __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, |
9cb78c16 | 1126 | struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int)) |
1da177e4 | 1127 | { |
e315cd28 | 1128 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
bdf79621 | 1129 | fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; |
523ec773 | 1130 | int err; |
1da177e4 | 1131 | |
7c3df132 | 1132 | if (!fcport) { |
523ec773 | 1133 | return FAILED; |
7c3df132 | 1134 | } |
1da177e4 | 1135 | |
4e98d3b8 AV |
1136 | err = fc_block_scsi_eh(cmd); |
1137 | if (err != 0) | |
1138 | return err; | |
1139 | ||
7c3df132 | 1140 | ql_log(ql_log_info, vha, 0x8009, |
9cb78c16 | 1141 | "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no, |
7c3df132 | 1142 | cmd->device->id, cmd->device->lun, cmd); |
1da177e4 | 1143 | |
523ec773 | 1144 | err = 0; |
7c3df132 SK |
1145 | if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { |
1146 | ql_log(ql_log_warn, vha, 0x800a, | |
1147 | "Wait for hba online failed for cmd=%p.\n", cmd); | |
523ec773 | 1148 | goto eh_reset_failed; |
7c3df132 | 1149 | } |
523ec773 | 1150 | err = 2; |
2afa19a9 | 1151 | if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1) |
7c3df132 SK |
1152 | != QLA_SUCCESS) { |
1153 | ql_log(ql_log_warn, vha, 0x800c, | |
1154 | "do_reset failed for cmd=%p.\n", cmd); | |
523ec773 | 1155 | goto eh_reset_failed; |
7c3df132 | 1156 | } |
523ec773 | 1157 | err = 3; |
e315cd28 | 1158 | if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, |
7c3df132 SK |
1159 | cmd->device->lun, type) != QLA_SUCCESS) { |
1160 | ql_log(ql_log_warn, vha, 0x800d, | |
d6a03581 | 1161 | "wait for pending cmds failed for cmd=%p.\n", cmd); |
523ec773 | 1162 | goto eh_reset_failed; |
7c3df132 | 1163 | } |
523ec773 | 1164 | |
7c3df132 | 1165 | ql_log(ql_log_info, vha, 0x800e, |
9cb78c16 | 1166 | "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name, |
cfb0919c | 1167 | vha->host_no, cmd->device->id, cmd->device->lun, cmd); |
523ec773 AV |
1168 | |
1169 | return SUCCESS; | |
1170 | ||
4d78c973 | 1171 | eh_reset_failed: |
7c3df132 | 1172 | ql_log(ql_log_info, vha, 0x800f, |
9cb78c16 | 1173 | "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name, |
cfb0919c CD |
1174 | reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, |
1175 | cmd); | |
523ec773 AV |
1176 | return FAILED; |
1177 | } | |
1da177e4 | 1178 | |
523ec773 AV |
1179 | static int |
1180 | qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) | |
1181 | { | |
e315cd28 AC |
1182 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
1183 | struct qla_hw_data *ha = vha->hw; | |
1da177e4 | 1184 | |
a465537a SC |
1185 | if (qla2x00_isp_reg_stat(ha)) { |
1186 | ql_log(ql_log_info, vha, 0x803e, | |
1187 | "PCI/Register disconnect, exiting.\n"); | |
1188 | return FAILED; | |
1189 | } | |
1190 | ||
523ec773 AV |
1191 | return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, |
1192 | ha->isp_ops->lun_reset); | |
1da177e4 LT |
1193 | } |
1194 | ||
1da177e4 | 1195 | static int |
523ec773 | 1196 | qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) |
1da177e4 | 1197 | { |
e315cd28 AC |
1198 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
1199 | struct qla_hw_data *ha = vha->hw; | |
1da177e4 | 1200 | |
a465537a SC |
1201 | if (qla2x00_isp_reg_stat(ha)) { |
1202 | ql_log(ql_log_info, vha, 0x803f, | |
1203 | "PCI/Register disconnect, exiting.\n"); | |
1204 | return FAILED; | |
1205 | } | |
1206 | ||
523ec773 AV |
1207 | return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, |
1208 | ha->isp_ops->target_reset); | |
1da177e4 LT |
1209 | } |
1210 | ||
1da177e4 LT |
1211 | /************************************************************************** |
1212 | * qla2xxx_eh_bus_reset | |
1213 | * | |
1214 | * Description: | |
1215 | * The bus reset function will reset the bus and abort any executing | |
1216 | * commands. | |
1217 | * | |
1218 | * Input: | |
1219 | * cmd = Linux SCSI command packet of the command that cause the | |
1220 | * bus reset. | |
1221 | * | |
1222 | * Returns: | |
1223 | * SUCCESS/FAILURE (defined as macro in scsi.h). | |
1224 | * | |
1225 | **************************************************************************/ | |
e5f82ab8 | 1226 | static int |
1da177e4 LT |
1227 | qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) |
1228 | { | |
e315cd28 | 1229 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
bdf79621 | 1230 | fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; |
2c3dfe3f | 1231 | int ret = FAILED; |
9cb78c16 HR |
1232 | unsigned int id; |
1233 | uint64_t lun; | |
a465537a SC |
1234 | struct qla_hw_data *ha = vha->hw; |
1235 | ||
1236 | if (qla2x00_isp_reg_stat(ha)) { | |
1237 | ql_log(ql_log_info, vha, 0x8040, | |
1238 | "PCI/Register disconnect, exiting.\n"); | |
1239 | return FAILED; | |
1240 | } | |
f4f051eb | 1241 | |
f4f051eb | 1242 | id = cmd->device->id; |
1243 | lun = cmd->device->lun; | |
1da177e4 | 1244 | |
7c3df132 | 1245 | if (!fcport) { |
f4f051eb | 1246 | return ret; |
7c3df132 | 1247 | } |
1da177e4 | 1248 | |
4e98d3b8 AV |
1249 | ret = fc_block_scsi_eh(cmd); |
1250 | if (ret != 0) | |
1251 | return ret; | |
1252 | ret = FAILED; | |
1253 | ||
7c3df132 | 1254 | ql_log(ql_log_info, vha, 0x8012, |
9cb78c16 | 1255 | "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); |
1da177e4 | 1256 | |
e315cd28 | 1257 | if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { |
7c3df132 SK |
1258 | ql_log(ql_log_fatal, vha, 0x8013, |
1259 | "Wait for hba online failed board disabled.\n"); | |
f4f051eb | 1260 | goto eh_bus_reset_done; |
1da177e4 LT |
1261 | } |
1262 | ||
ad537689 SK |
1263 | if (qla2x00_loop_reset(vha) == QLA_SUCCESS) |
1264 | ret = SUCCESS; | |
1265 | ||
f4f051eb | 1266 | if (ret == FAILED) |
1267 | goto eh_bus_reset_done; | |
1da177e4 | 1268 | |
9a41a62b | 1269 | /* Flush outstanding commands. */ |
4d78c973 | 1270 | if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != |
7c3df132 SK |
1271 | QLA_SUCCESS) { |
1272 | ql_log(ql_log_warn, vha, 0x8014, | |
1273 | "Wait for pending commands failed.\n"); | |
9a41a62b | 1274 | ret = FAILED; |
7c3df132 | 1275 | } |
1da177e4 | 1276 | |
f4f051eb | 1277 | eh_bus_reset_done: |
7c3df132 | 1278 | ql_log(ql_log_warn, vha, 0x802b, |
9cb78c16 | 1279 | "BUS RESET %s nexus=%ld:%d:%llu.\n", |
d6a03581 | 1280 | (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); |
1da177e4 | 1281 | |
f4f051eb | 1282 | return ret; |
1da177e4 LT |
1283 | } |
1284 | ||
1285 | /************************************************************************** | |
1286 | * qla2xxx_eh_host_reset | |
1287 | * | |
1288 | * Description: | |
1289 | * The reset function will reset the Adapter. | |
1290 | * | |
1291 | * Input: | |
1292 | * cmd = Linux SCSI command packet of the command that cause the | |
1293 | * adapter reset. | |
1294 | * | |
1295 | * Returns: | |
1296 | * Either SUCCESS or FAILED. | |
1297 | * | |
1298 | * Note: | |
1299 | **************************************************************************/ | |
e5f82ab8 | 1300 | static int |
1da177e4 LT |
1301 | qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) |
1302 | { | |
e315cd28 | 1303 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
e315cd28 | 1304 | struct qla_hw_data *ha = vha->hw; |
2c3dfe3f | 1305 | int ret = FAILED; |
9cb78c16 HR |
1306 | unsigned int id; |
1307 | uint64_t lun; | |
e315cd28 | 1308 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); |
1da177e4 | 1309 | |
a465537a SC |
1310 | if (qla2x00_isp_reg_stat(ha)) { |
1311 | ql_log(ql_log_info, vha, 0x8041, | |
1312 | "PCI/Register disconnect, exiting.\n"); | |
1313 | schedule_work(&ha->board_disable); | |
1314 | return SUCCESS; | |
1315 | } | |
1316 | ||
f4f051eb | 1317 | id = cmd->device->id; |
1318 | lun = cmd->device->lun; | |
f4f051eb | 1319 | |
7c3df132 | 1320 | ql_log(ql_log_info, vha, 0x8018, |
9cb78c16 | 1321 | "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); |
1da177e4 | 1322 | |
63ee7072 CD |
1323 | /* |
1324 | * No point in issuing another reset if one is active. Also do not | |
1325 | * attempt a reset if we are updating flash. | |
1326 | */ | |
1327 | if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) | |
f4f051eb | 1328 | goto eh_host_reset_lock; |
1da177e4 | 1329 | |
e315cd28 AC |
1330 | if (vha != base_vha) { |
1331 | if (qla2x00_vp_abort_isp(vha)) | |
f4f051eb | 1332 | goto eh_host_reset_lock; |
e315cd28 | 1333 | } else { |
7ec0effd | 1334 | if (IS_P3P_TYPE(vha->hw)) { |
a9083016 GM |
1335 | if (!qla82xx_fcoe_ctx_reset(vha)) { |
1336 | /* Ctx reset success */ | |
1337 | ret = SUCCESS; | |
1338 | goto eh_host_reset_lock; | |
1339 | } | |
1340 | /* fall thru if ctx reset failed */ | |
1341 | } | |
68ca949c AC |
1342 | if (ha->wq) |
1343 | flush_workqueue(ha->wq); | |
1344 | ||
e315cd28 | 1345 | set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); |
a9083016 | 1346 | if (ha->isp_ops->abort_isp(base_vha)) { |
e315cd28 AC |
1347 | clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); |
1348 | /* failed. schedule dpc to try */ | |
1349 | set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); | |
1350 | ||
7c3df132 SK |
1351 | if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { |
1352 | ql_log(ql_log_warn, vha, 0x802a, | |
1353 | "wait for hba online failed.\n"); | |
e315cd28 | 1354 | goto eh_host_reset_lock; |
7c3df132 | 1355 | } |
e315cd28 AC |
1356 | } |
1357 | clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); | |
fa2a1ce5 | 1358 | } |
1da177e4 | 1359 | |
e315cd28 | 1360 | /* Waiting for command to be returned to OS.*/ |
4d78c973 | 1361 | if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == |
e315cd28 | 1362 | QLA_SUCCESS) |
f4f051eb | 1363 | ret = SUCCESS; |
1da177e4 | 1364 | |
f4f051eb | 1365 | eh_host_reset_lock: |
cfb0919c | 1366 | ql_log(ql_log_info, vha, 0x8017, |
9cb78c16 | 1367 | "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", |
cfb0919c | 1368 | (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); |
1da177e4 | 1369 | |
f4f051eb | 1370 | return ret; |
1371 | } | |
1da177e4 LT |
1372 | |
1373 | /* | |
1374 | * qla2x00_loop_reset | |
1375 | * Issue loop reset. | |
1376 | * | |
1377 | * Input: | |
1378 | * ha = adapter block pointer. | |
1379 | * | |
1380 | * Returns: | |
1381 | * 0 = success | |
1382 | */ | |
a4722cf2 | 1383 | int |
e315cd28 | 1384 | qla2x00_loop_reset(scsi_qla_host_t *vha) |
1da177e4 | 1385 | { |
0c8c39af | 1386 | int ret; |
bdf79621 | 1387 | struct fc_port *fcport; |
e315cd28 | 1388 | struct qla_hw_data *ha = vha->hw; |
1da177e4 | 1389 | |
5854771e AB |
1390 | if (IS_QLAFX00(ha)) { |
1391 | return qlafx00_loop_reset(vha); | |
1392 | } | |
1393 | ||
f4c496c1 | 1394 | if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { |
55e5ed27 AV |
1395 | list_for_each_entry(fcport, &vha->vp_fcports, list) { |
1396 | if (fcport->port_type != FCT_TARGET) | |
1397 | continue; | |
1398 | ||
1399 | ret = ha->isp_ops->target_reset(fcport, 0, 0); | |
1400 | if (ret != QLA_SUCCESS) { | |
7c3df132 | 1401 | ql_dbg(ql_dbg_taskm, vha, 0x802c, |
5854771e | 1402 | "Bus Reset failed: Reset=%d " |
7c3df132 | 1403 | "d_id=%x.\n", ret, fcport->d_id.b24); |
55e5ed27 AV |
1404 | } |
1405 | } | |
1406 | } | |
1407 | ||
8ae6d9c7 | 1408 | |
6246b8a1 | 1409 | if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { |
0b7e7c53 AV |
1410 | atomic_set(&vha->loop_state, LOOP_DOWN); |
1411 | atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); | |
1412 | qla2x00_mark_all_devices_lost(vha, 0); | |
e315cd28 | 1413 | ret = qla2x00_full_login_lip(vha); |
0c8c39af | 1414 | if (ret != QLA_SUCCESS) { |
7c3df132 SK |
1415 | ql_dbg(ql_dbg_taskm, vha, 0x802d, |
1416 | "full_login_lip=%d.\n", ret); | |
749af3d5 | 1417 | } |
0c8c39af AV |
1418 | } |
1419 | ||
0d6e61bc | 1420 | if (ha->flags.enable_lip_reset) { |
e315cd28 | 1421 | ret = qla2x00_lip_reset(vha); |
ad537689 | 1422 | if (ret != QLA_SUCCESS) |
7c3df132 SK |
1423 | ql_dbg(ql_dbg_taskm, vha, 0x802e, |
1424 | "lip_reset failed (%d).\n", ret); | |
1da177e4 LT |
1425 | } |
1426 | ||
1da177e4 | 1427 | /* Issue marker command only when we are going to start the I/O */ |
e315cd28 | 1428 | vha->marker_needed = 1; |
1da177e4 | 1429 | |
0c8c39af | 1430 | return QLA_SUCCESS; |
1da177e4 LT |
1431 | } |
1432 | ||
df4bf0bb | 1433 | void |
e315cd28 | 1434 | qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) |
df4bf0bb | 1435 | { |
73208dfd | 1436 | int que, cnt; |
df4bf0bb AV |
1437 | unsigned long flags; |
1438 | srb_t *sp; | |
e315cd28 | 1439 | struct qla_hw_data *ha = vha->hw; |
73208dfd | 1440 | struct req_que *req; |
df4bf0bb | 1441 | |
c0cb4496 AE |
1442 | qlt_host_reset_handler(ha); |
1443 | ||
df4bf0bb | 1444 | spin_lock_irqsave(&ha->hardware_lock, flags); |
2afa19a9 | 1445 | for (que = 0; que < ha->max_req_queues; que++) { |
29bdccbe | 1446 | req = ha->req_q_map[que]; |
73208dfd AC |
1447 | if (!req) |
1448 | continue; | |
8d93f550 CD |
1449 | if (!req->outstanding_cmds) |
1450 | continue; | |
1451 | for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { | |
73208dfd | 1452 | sp = req->outstanding_cmds[cnt]; |
e612d465 | 1453 | if (sp) { |
73208dfd | 1454 | req->outstanding_cmds[cnt] = NULL; |
9ba56b95 | 1455 | sp->done(vha, sp, res); |
73208dfd | 1456 | } |
df4bf0bb AV |
1457 | } |
1458 | } | |
1459 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1460 | } | |
1461 | ||
f4f051eb | 1462 | static int |
1463 | qla2xxx_slave_alloc(struct scsi_device *sdev) | |
1da177e4 | 1464 | { |
bdf79621 | 1465 | struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); |
1da177e4 | 1466 | |
19a7b4ae | 1467 | if (!rport || fc_remote_port_chkready(rport)) |
f4f051eb | 1468 | return -ENXIO; |
bdf79621 | 1469 | |
19a7b4ae | 1470 | sdev->hostdata = *(fc_port_t **)rport->dd_data; |
1da177e4 | 1471 | |
f4f051eb | 1472 | return 0; |
1473 | } | |
1da177e4 | 1474 | |
f4f051eb | 1475 | static int |
1476 | qla2xxx_slave_configure(struct scsi_device *sdev) | |
1477 | { | |
e315cd28 | 1478 | scsi_qla_host_t *vha = shost_priv(sdev->host); |
2afa19a9 | 1479 | struct req_que *req = vha->req; |
8482e118 | 1480 | |
9e522cd8 AE |
1481 | if (IS_T10_PI_CAPABLE(vha->hw)) |
1482 | blk_queue_update_dma_alignment(sdev->request_queue, 0x7); | |
1483 | ||
db5ed4df | 1484 | scsi_change_queue_depth(sdev, req->max_q_depth); |
f4f051eb | 1485 | return 0; |
1486 | } | |
1da177e4 | 1487 | |
f4f051eb | 1488 | static void |
1489 | qla2xxx_slave_destroy(struct scsi_device *sdev) | |
1490 | { | |
1491 | sdev->hostdata = NULL; | |
1da177e4 LT |
1492 | } |
1493 | ||
1494 | /** | |
1495 | * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. | |
1496 | * @ha: HA context | |
1497 | * | |
1498 | * At exit, the @ha's flags.enable_64bit_addressing set to indicated | |
1499 | * supported addressing method. | |
1500 | */ | |
1501 | static void | |
53303c42 | 1502 | qla2x00_config_dma_addressing(struct qla_hw_data *ha) |
1da177e4 | 1503 | { |
7524f9b9 | 1504 | /* Assume a 32bit DMA mask. */ |
1da177e4 | 1505 | ha->flags.enable_64bit_addressing = 0; |
1da177e4 | 1506 | |
6a35528a | 1507 | if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { |
7524f9b9 AV |
1508 | /* Any upper-dword bits set? */ |
1509 | if (MSD(dma_get_required_mask(&ha->pdev->dev)) && | |
6a35528a | 1510 | !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { |
7524f9b9 | 1511 | /* Ok, a 64bit DMA mask is applicable. */ |
1da177e4 | 1512 | ha->flags.enable_64bit_addressing = 1; |
fd34f556 AV |
1513 | ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; |
1514 | ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; | |
7524f9b9 | 1515 | return; |
1da177e4 | 1516 | } |
1da177e4 | 1517 | } |
7524f9b9 | 1518 | |
284901a9 YH |
1519 | dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); |
1520 | pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); | |
1da177e4 LT |
1521 | } |
1522 | ||
fd34f556 | 1523 | static void |
e315cd28 | 1524 | qla2x00_enable_intrs(struct qla_hw_data *ha) |
fd34f556 AV |
1525 | { |
1526 | unsigned long flags = 0; | |
1527 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
1528 | ||
1529 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1530 | ha->interrupts_on = 1; | |
1531 | /* enable risc and host interrupts */ | |
1532 | WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); | |
1533 | RD_REG_WORD(®->ictrl); | |
1534 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1535 | ||
1536 | } | |
1537 | ||
1538 | static void | |
e315cd28 | 1539 | qla2x00_disable_intrs(struct qla_hw_data *ha) |
fd34f556 AV |
1540 | { |
1541 | unsigned long flags = 0; | |
1542 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
1543 | ||
1544 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1545 | ha->interrupts_on = 0; | |
1546 | /* disable risc and host interrupts */ | |
1547 | WRT_REG_WORD(®->ictrl, 0); | |
1548 | RD_REG_WORD(®->ictrl); | |
1549 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1550 | } | |
1551 | ||
1552 | static void | |
e315cd28 | 1553 | qla24xx_enable_intrs(struct qla_hw_data *ha) |
fd34f556 AV |
1554 | { |
1555 | unsigned long flags = 0; | |
1556 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
1557 | ||
1558 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1559 | ha->interrupts_on = 1; | |
1560 | WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); | |
1561 | RD_REG_DWORD(®->ictrl); | |
1562 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1563 | } | |
1564 | ||
1565 | static void | |
e315cd28 | 1566 | qla24xx_disable_intrs(struct qla_hw_data *ha) |
fd34f556 AV |
1567 | { |
1568 | unsigned long flags = 0; | |
1569 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
1570 | ||
124f85e6 AV |
1571 | if (IS_NOPOLLING_TYPE(ha)) |
1572 | return; | |
fd34f556 AV |
1573 | spin_lock_irqsave(&ha->hardware_lock, flags); |
1574 | ha->interrupts_on = 0; | |
1575 | WRT_REG_DWORD(®->ictrl, 0); | |
1576 | RD_REG_DWORD(®->ictrl); | |
1577 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1578 | } | |
1579 | ||
706f457d GM |
1580 | static int |
1581 | qla2x00_iospace_config(struct qla_hw_data *ha) | |
1582 | { | |
1583 | resource_size_t pio; | |
1584 | uint16_t msix; | |
1585 | int cpus; | |
1586 | ||
706f457d GM |
1587 | if (pci_request_selected_regions(ha->pdev, ha->bars, |
1588 | QLA2XXX_DRIVER_NAME)) { | |
1589 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, | |
1590 | "Failed to reserve PIO/MMIO regions (%s), aborting.\n", | |
1591 | pci_name(ha->pdev)); | |
1592 | goto iospace_error_exit; | |
1593 | } | |
1594 | if (!(ha->bars & 1)) | |
1595 | goto skip_pio; | |
1596 | ||
1597 | /* We only need PIO for Flash operations on ISP2312 v2 chips. */ | |
1598 | pio = pci_resource_start(ha->pdev, 0); | |
1599 | if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { | |
1600 | if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { | |
1601 | ql_log_pci(ql_log_warn, ha->pdev, 0x0012, | |
1602 | "Invalid pci I/O region size (%s).\n", | |
1603 | pci_name(ha->pdev)); | |
1604 | pio = 0; | |
1605 | } | |
1606 | } else { | |
1607 | ql_log_pci(ql_log_warn, ha->pdev, 0x0013, | |
1608 | "Region #0 no a PIO resource (%s).\n", | |
1609 | pci_name(ha->pdev)); | |
1610 | pio = 0; | |
1611 | } | |
1612 | ha->pio_address = pio; | |
1613 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, | |
1614 | "PIO address=%llu.\n", | |
1615 | (unsigned long long)ha->pio_address); | |
1616 | ||
1617 | skip_pio: | |
1618 | /* Use MMIO operations for all accesses. */ | |
1619 | if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { | |
1620 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, | |
1621 | "Region #1 not an MMIO resource (%s), aborting.\n", | |
1622 | pci_name(ha->pdev)); | |
1623 | goto iospace_error_exit; | |
1624 | } | |
1625 | if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { | |
1626 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, | |
1627 | "Invalid PCI mem region size (%s), aborting.\n", | |
1628 | pci_name(ha->pdev)); | |
1629 | goto iospace_error_exit; | |
1630 | } | |
1631 | ||
1632 | ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); | |
1633 | if (!ha->iobase) { | |
1634 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, | |
1635 | "Cannot remap MMIO (%s), aborting.\n", | |
1636 | pci_name(ha->pdev)); | |
1637 | goto iospace_error_exit; | |
1638 | } | |
1639 | ||
1640 | /* Determine queue resources */ | |
1641 | ha->max_req_queues = ha->max_rsp_queues = 1; | |
1642 | if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) || | |
1643 | (ql2xmaxqueues > 1 && ql2xmultique_tag) || | |
1644 | (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) | |
1645 | goto mqiobase_exit; | |
1646 | ||
1647 | ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), | |
1648 | pci_resource_len(ha->pdev, 3)); | |
1649 | if (ha->mqiobase) { | |
1650 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, | |
1651 | "MQIO Base=%p.\n", ha->mqiobase); | |
1652 | /* Read MSIX vector size of the board */ | |
1653 | pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); | |
1654 | ha->msix_count = msix; | |
1655 | /* Max queues are bounded by available msix vectors */ | |
1656 | /* queue 0 uses two msix vectors */ | |
1657 | if (ql2xmultique_tag) { | |
1658 | cpus = num_online_cpus(); | |
1659 | ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ? | |
1660 | (cpus + 1) : (ha->msix_count - 1); | |
1661 | ha->max_req_queues = 2; | |
1662 | } else if (ql2xmaxqueues > 1) { | |
1663 | ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ? | |
1664 | QLA_MQ_SIZE : ql2xmaxqueues; | |
1665 | ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008, | |
1666 | "QoS mode set, max no of request queues:%d.\n", | |
1667 | ha->max_req_queues); | |
1668 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019, | |
1669 | "QoS mode set, max no of request queues:%d.\n", | |
1670 | ha->max_req_queues); | |
1671 | } | |
1672 | ql_log_pci(ql_log_info, ha->pdev, 0x001a, | |
1673 | "MSI-X vector count: %d.\n", msix); | |
1674 | } else | |
1675 | ql_log_pci(ql_log_info, ha->pdev, 0x001b, | |
1676 | "BAR 3 not enabled.\n"); | |
1677 | ||
1678 | mqiobase_exit: | |
1679 | ha->msix_count = ha->max_rsp_queues + 1; | |
1680 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, | |
1681 | "MSIX Count:%d.\n", ha->msix_count); | |
1682 | return (0); | |
1683 | ||
1684 | iospace_error_exit: | |
1685 | return (-ENOMEM); | |
1686 | } | |
1687 | ||
1688 | ||
6246b8a1 GM |
1689 | static int |
1690 | qla83xx_iospace_config(struct qla_hw_data *ha) | |
1691 | { | |
1692 | uint16_t msix; | |
1693 | int cpus; | |
1694 | ||
1695 | if (pci_request_selected_regions(ha->pdev, ha->bars, | |
1696 | QLA2XXX_DRIVER_NAME)) { | |
1697 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, | |
1698 | "Failed to reserve PIO/MMIO regions (%s), aborting.\n", | |
1699 | pci_name(ha->pdev)); | |
1700 | ||
1701 | goto iospace_error_exit; | |
1702 | } | |
1703 | ||
1704 | /* Use MMIO operations for all accesses. */ | |
1705 | if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { | |
1706 | ql_log_pci(ql_log_warn, ha->pdev, 0x0118, | |
1707 | "Invalid pci I/O region size (%s).\n", | |
1708 | pci_name(ha->pdev)); | |
1709 | goto iospace_error_exit; | |
1710 | } | |
1711 | if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { | |
1712 | ql_log_pci(ql_log_warn, ha->pdev, 0x0119, | |
1713 | "Invalid PCI mem region size (%s), aborting\n", | |
1714 | pci_name(ha->pdev)); | |
1715 | goto iospace_error_exit; | |
1716 | } | |
1717 | ||
1718 | ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); | |
1719 | if (!ha->iobase) { | |
1720 | ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, | |
1721 | "Cannot remap MMIO (%s), aborting.\n", | |
1722 | pci_name(ha->pdev)); | |
1723 | goto iospace_error_exit; | |
1724 | } | |
1725 | ||
1726 | /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ | |
1727 | /* 83XX 26XX always use MQ type access for queues | |
1728 | * - mbar 2, a.k.a region 4 */ | |
1729 | ha->max_req_queues = ha->max_rsp_queues = 1; | |
1730 | ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), | |
1731 | pci_resource_len(ha->pdev, 4)); | |
1732 | ||
1733 | if (!ha->mqiobase) { | |
1734 | ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, | |
1735 | "BAR2/region4 not enabled\n"); | |
1736 | goto mqiobase_exit; | |
1737 | } | |
1738 | ||
1739 | ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), | |
1740 | pci_resource_len(ha->pdev, 2)); | |
1741 | if (ha->msixbase) { | |
1742 | /* Read MSIX vector size of the board */ | |
1743 | pci_read_config_word(ha->pdev, | |
1744 | QLA_83XX_PCI_MSIX_CONTROL, &msix); | |
1745 | ha->msix_count = msix; | |
1746 | /* Max queues are bounded by available msix vectors */ | |
1747 | /* queue 0 uses two msix vectors */ | |
1748 | if (ql2xmultique_tag) { | |
1749 | cpus = num_online_cpus(); | |
1750 | ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ? | |
1751 | (cpus + 1) : (ha->msix_count - 1); | |
1752 | ha->max_req_queues = 2; | |
1753 | } else if (ql2xmaxqueues > 1) { | |
1754 | ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ? | |
1755 | QLA_MQ_SIZE : ql2xmaxqueues; | |
1756 | ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c, | |
1757 | "QoS mode set, max no of request queues:%d.\n", | |
1758 | ha->max_req_queues); | |
1759 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, | |
1760 | "QoS mode set, max no of request queues:%d.\n", | |
1761 | ha->max_req_queues); | |
1762 | } | |
1763 | ql_log_pci(ql_log_info, ha->pdev, 0x011c, | |
1764 | "MSI-X vector count: %d.\n", msix); | |
1765 | } else | |
1766 | ql_log_pci(ql_log_info, ha->pdev, 0x011e, | |
1767 | "BAR 1 not enabled.\n"); | |
1768 | ||
1769 | mqiobase_exit: | |
1770 | ha->msix_count = ha->max_rsp_queues + 1; | |
aa230bc5 AE |
1771 | |
1772 | qlt_83xx_iospace_config(ha); | |
1773 | ||
6246b8a1 GM |
1774 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, |
1775 | "MSIX Count:%d.\n", ha->msix_count); | |
1776 | return 0; | |
1777 | ||
1778 | iospace_error_exit: | |
1779 | return -ENOMEM; | |
1780 | } | |
1781 | ||
fd34f556 AV |
1782 | static struct isp_operations qla2100_isp_ops = { |
1783 | .pci_config = qla2100_pci_config, | |
1784 | .reset_chip = qla2x00_reset_chip, | |
1785 | .chip_diag = qla2x00_chip_diag, | |
1786 | .config_rings = qla2x00_config_rings, | |
1787 | .reset_adapter = qla2x00_reset_adapter, | |
1788 | .nvram_config = qla2x00_nvram_config, | |
1789 | .update_fw_options = qla2x00_update_fw_options, | |
1790 | .load_risc = qla2x00_load_risc, | |
1791 | .pci_info_str = qla2x00_pci_info_str, | |
1792 | .fw_version_str = qla2x00_fw_version_str, | |
1793 | .intr_handler = qla2100_intr_handler, | |
1794 | .enable_intrs = qla2x00_enable_intrs, | |
1795 | .disable_intrs = qla2x00_disable_intrs, | |
1796 | .abort_command = qla2x00_abort_command, | |
523ec773 AV |
1797 | .target_reset = qla2x00_abort_target, |
1798 | .lun_reset = qla2x00_lun_reset, | |
fd34f556 AV |
1799 | .fabric_login = qla2x00_login_fabric, |
1800 | .fabric_logout = qla2x00_fabric_logout, | |
1801 | .calc_req_entries = qla2x00_calc_iocbs_32, | |
1802 | .build_iocbs = qla2x00_build_scsi_iocbs_32, | |
1803 | .prep_ms_iocb = qla2x00_prep_ms_iocb, | |
1804 | .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, | |
1805 | .read_nvram = qla2x00_read_nvram_data, | |
1806 | .write_nvram = qla2x00_write_nvram_data, | |
1807 | .fw_dump = qla2100_fw_dump, | |
1808 | .beacon_on = NULL, | |
1809 | .beacon_off = NULL, | |
1810 | .beacon_blink = NULL, | |
1811 | .read_optrom = qla2x00_read_optrom_data, | |
1812 | .write_optrom = qla2x00_write_optrom_data, | |
1813 | .get_flash_version = qla2x00_get_flash_version, | |
e315cd28 | 1814 | .start_scsi = qla2x00_start_scsi, |
a9083016 | 1815 | .abort_isp = qla2x00_abort_isp, |
706f457d | 1816 | .iospace_config = qla2x00_iospace_config, |
8ae6d9c7 | 1817 | .initialize_adapter = qla2x00_initialize_adapter, |
fd34f556 AV |
1818 | }; |
1819 | ||
1820 | static struct isp_operations qla2300_isp_ops = { | |
1821 | .pci_config = qla2300_pci_config, | |
1822 | .reset_chip = qla2x00_reset_chip, | |
1823 | .chip_diag = qla2x00_chip_diag, | |
1824 | .config_rings = qla2x00_config_rings, | |
1825 | .reset_adapter = qla2x00_reset_adapter, | |
1826 | .nvram_config = qla2x00_nvram_config, | |
1827 | .update_fw_options = qla2x00_update_fw_options, | |
1828 | .load_risc = qla2x00_load_risc, | |
1829 | .pci_info_str = qla2x00_pci_info_str, | |
1830 | .fw_version_str = qla2x00_fw_version_str, | |
1831 | .intr_handler = qla2300_intr_handler, | |
1832 | .enable_intrs = qla2x00_enable_intrs, | |
1833 | .disable_intrs = qla2x00_disable_intrs, | |
1834 | .abort_command = qla2x00_abort_command, | |
523ec773 AV |
1835 | .target_reset = qla2x00_abort_target, |
1836 | .lun_reset = qla2x00_lun_reset, | |
fd34f556 AV |
1837 | .fabric_login = qla2x00_login_fabric, |
1838 | .fabric_logout = qla2x00_fabric_logout, | |
1839 | .calc_req_entries = qla2x00_calc_iocbs_32, | |
1840 | .build_iocbs = qla2x00_build_scsi_iocbs_32, | |
1841 | .prep_ms_iocb = qla2x00_prep_ms_iocb, | |
1842 | .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, | |
1843 | .read_nvram = qla2x00_read_nvram_data, | |
1844 | .write_nvram = qla2x00_write_nvram_data, | |
1845 | .fw_dump = qla2300_fw_dump, | |
1846 | .beacon_on = qla2x00_beacon_on, | |
1847 | .beacon_off = qla2x00_beacon_off, | |
1848 | .beacon_blink = qla2x00_beacon_blink, | |
1849 | .read_optrom = qla2x00_read_optrom_data, | |
1850 | .write_optrom = qla2x00_write_optrom_data, | |
1851 | .get_flash_version = qla2x00_get_flash_version, | |
e315cd28 | 1852 | .start_scsi = qla2x00_start_scsi, |
a9083016 | 1853 | .abort_isp = qla2x00_abort_isp, |
7ec0effd | 1854 | .iospace_config = qla2x00_iospace_config, |
8ae6d9c7 | 1855 | .initialize_adapter = qla2x00_initialize_adapter, |
fd34f556 AV |
1856 | }; |
1857 | ||
1858 | static struct isp_operations qla24xx_isp_ops = { | |
1859 | .pci_config = qla24xx_pci_config, | |
1860 | .reset_chip = qla24xx_reset_chip, | |
1861 | .chip_diag = qla24xx_chip_diag, | |
1862 | .config_rings = qla24xx_config_rings, | |
1863 | .reset_adapter = qla24xx_reset_adapter, | |
1864 | .nvram_config = qla24xx_nvram_config, | |
1865 | .update_fw_options = qla24xx_update_fw_options, | |
1866 | .load_risc = qla24xx_load_risc, | |
1867 | .pci_info_str = qla24xx_pci_info_str, | |
1868 | .fw_version_str = qla24xx_fw_version_str, | |
1869 | .intr_handler = qla24xx_intr_handler, | |
1870 | .enable_intrs = qla24xx_enable_intrs, | |
1871 | .disable_intrs = qla24xx_disable_intrs, | |
1872 | .abort_command = qla24xx_abort_command, | |
523ec773 AV |
1873 | .target_reset = qla24xx_abort_target, |
1874 | .lun_reset = qla24xx_lun_reset, | |
fd34f556 AV |
1875 | .fabric_login = qla24xx_login_fabric, |
1876 | .fabric_logout = qla24xx_fabric_logout, | |
1877 | .calc_req_entries = NULL, | |
1878 | .build_iocbs = NULL, | |
1879 | .prep_ms_iocb = qla24xx_prep_ms_iocb, | |
1880 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, | |
1881 | .read_nvram = qla24xx_read_nvram_data, | |
1882 | .write_nvram = qla24xx_write_nvram_data, | |
1883 | .fw_dump = qla24xx_fw_dump, | |
1884 | .beacon_on = qla24xx_beacon_on, | |
1885 | .beacon_off = qla24xx_beacon_off, | |
1886 | .beacon_blink = qla24xx_beacon_blink, | |
1887 | .read_optrom = qla24xx_read_optrom_data, | |
1888 | .write_optrom = qla24xx_write_optrom_data, | |
1889 | .get_flash_version = qla24xx_get_flash_version, | |
e315cd28 | 1890 | .start_scsi = qla24xx_start_scsi, |
a9083016 | 1891 | .abort_isp = qla2x00_abort_isp, |
7ec0effd | 1892 | .iospace_config = qla2x00_iospace_config, |
8ae6d9c7 | 1893 | .initialize_adapter = qla2x00_initialize_adapter, |
fd34f556 AV |
1894 | }; |
1895 | ||
c3a2f0df AV |
1896 | static struct isp_operations qla25xx_isp_ops = { |
1897 | .pci_config = qla25xx_pci_config, | |
1898 | .reset_chip = qla24xx_reset_chip, | |
1899 | .chip_diag = qla24xx_chip_diag, | |
1900 | .config_rings = qla24xx_config_rings, | |
1901 | .reset_adapter = qla24xx_reset_adapter, | |
1902 | .nvram_config = qla24xx_nvram_config, | |
1903 | .update_fw_options = qla24xx_update_fw_options, | |
1904 | .load_risc = qla24xx_load_risc, | |
1905 | .pci_info_str = qla24xx_pci_info_str, | |
1906 | .fw_version_str = qla24xx_fw_version_str, | |
1907 | .intr_handler = qla24xx_intr_handler, | |
1908 | .enable_intrs = qla24xx_enable_intrs, | |
1909 | .disable_intrs = qla24xx_disable_intrs, | |
1910 | .abort_command = qla24xx_abort_command, | |
523ec773 AV |
1911 | .target_reset = qla24xx_abort_target, |
1912 | .lun_reset = qla24xx_lun_reset, | |
c3a2f0df AV |
1913 | .fabric_login = qla24xx_login_fabric, |
1914 | .fabric_logout = qla24xx_fabric_logout, | |
1915 | .calc_req_entries = NULL, | |
1916 | .build_iocbs = NULL, | |
1917 | .prep_ms_iocb = qla24xx_prep_ms_iocb, | |
1918 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, | |
1919 | .read_nvram = qla25xx_read_nvram_data, | |
1920 | .write_nvram = qla25xx_write_nvram_data, | |
1921 | .fw_dump = qla25xx_fw_dump, | |
1922 | .beacon_on = qla24xx_beacon_on, | |
1923 | .beacon_off = qla24xx_beacon_off, | |
1924 | .beacon_blink = qla24xx_beacon_blink, | |
338c9161 | 1925 | .read_optrom = qla25xx_read_optrom_data, |
c3a2f0df AV |
1926 | .write_optrom = qla24xx_write_optrom_data, |
1927 | .get_flash_version = qla24xx_get_flash_version, | |
bad75002 | 1928 | .start_scsi = qla24xx_dif_start_scsi, |
a9083016 | 1929 | .abort_isp = qla2x00_abort_isp, |
7ec0effd | 1930 | .iospace_config = qla2x00_iospace_config, |
8ae6d9c7 | 1931 | .initialize_adapter = qla2x00_initialize_adapter, |
c3a2f0df AV |
1932 | }; |
1933 | ||
3a03eb79 AV |
1934 | static struct isp_operations qla81xx_isp_ops = { |
1935 | .pci_config = qla25xx_pci_config, | |
1936 | .reset_chip = qla24xx_reset_chip, | |
1937 | .chip_diag = qla24xx_chip_diag, | |
1938 | .config_rings = qla24xx_config_rings, | |
1939 | .reset_adapter = qla24xx_reset_adapter, | |
1940 | .nvram_config = qla81xx_nvram_config, | |
1941 | .update_fw_options = qla81xx_update_fw_options, | |
eaac30be | 1942 | .load_risc = qla81xx_load_risc, |
3a03eb79 AV |
1943 | .pci_info_str = qla24xx_pci_info_str, |
1944 | .fw_version_str = qla24xx_fw_version_str, | |
1945 | .intr_handler = qla24xx_intr_handler, | |
1946 | .enable_intrs = qla24xx_enable_intrs, | |
1947 | .disable_intrs = qla24xx_disable_intrs, | |
1948 | .abort_command = qla24xx_abort_command, | |
1949 | .target_reset = qla24xx_abort_target, | |
1950 | .lun_reset = qla24xx_lun_reset, | |
1951 | .fabric_login = qla24xx_login_fabric, | |
1952 | .fabric_logout = qla24xx_fabric_logout, | |
1953 | .calc_req_entries = NULL, | |
1954 | .build_iocbs = NULL, | |
1955 | .prep_ms_iocb = qla24xx_prep_ms_iocb, | |
1956 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, | |
3d79038f AV |
1957 | .read_nvram = NULL, |
1958 | .write_nvram = NULL, | |
3a03eb79 AV |
1959 | .fw_dump = qla81xx_fw_dump, |
1960 | .beacon_on = qla24xx_beacon_on, | |
1961 | .beacon_off = qla24xx_beacon_off, | |
6246b8a1 | 1962 | .beacon_blink = qla83xx_beacon_blink, |
3a03eb79 AV |
1963 | .read_optrom = qla25xx_read_optrom_data, |
1964 | .write_optrom = qla24xx_write_optrom_data, | |
1965 | .get_flash_version = qla24xx_get_flash_version, | |
ba77ef53 | 1966 | .start_scsi = qla24xx_dif_start_scsi, |
a9083016 | 1967 | .abort_isp = qla2x00_abort_isp, |
7ec0effd | 1968 | .iospace_config = qla2x00_iospace_config, |
8ae6d9c7 | 1969 | .initialize_adapter = qla2x00_initialize_adapter, |
a9083016 GM |
1970 | }; |
1971 | ||
1972 | static struct isp_operations qla82xx_isp_ops = { | |
1973 | .pci_config = qla82xx_pci_config, | |
1974 | .reset_chip = qla82xx_reset_chip, | |
1975 | .chip_diag = qla24xx_chip_diag, | |
1976 | .config_rings = qla82xx_config_rings, | |
1977 | .reset_adapter = qla24xx_reset_adapter, | |
1978 | .nvram_config = qla81xx_nvram_config, | |
1979 | .update_fw_options = qla24xx_update_fw_options, | |
1980 | .load_risc = qla82xx_load_risc, | |
9d55ca66 | 1981 | .pci_info_str = qla24xx_pci_info_str, |
a9083016 GM |
1982 | .fw_version_str = qla24xx_fw_version_str, |
1983 | .intr_handler = qla82xx_intr_handler, | |
1984 | .enable_intrs = qla82xx_enable_intrs, | |
1985 | .disable_intrs = qla82xx_disable_intrs, | |
1986 | .abort_command = qla24xx_abort_command, | |
1987 | .target_reset = qla24xx_abort_target, | |
1988 | .lun_reset = qla24xx_lun_reset, | |
1989 | .fabric_login = qla24xx_login_fabric, | |
1990 | .fabric_logout = qla24xx_fabric_logout, | |
1991 | .calc_req_entries = NULL, | |
1992 | .build_iocbs = NULL, | |
1993 | .prep_ms_iocb = qla24xx_prep_ms_iocb, | |
1994 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, | |
1995 | .read_nvram = qla24xx_read_nvram_data, | |
1996 | .write_nvram = qla24xx_write_nvram_data, | |
a1b23c5a | 1997 | .fw_dump = qla82xx_fw_dump, |
999916dc SK |
1998 | .beacon_on = qla82xx_beacon_on, |
1999 | .beacon_off = qla82xx_beacon_off, | |
2000 | .beacon_blink = NULL, | |
a9083016 GM |
2001 | .read_optrom = qla82xx_read_optrom_data, |
2002 | .write_optrom = qla82xx_write_optrom_data, | |
7ec0effd | 2003 | .get_flash_version = qla82xx_get_flash_version, |
a9083016 GM |
2004 | .start_scsi = qla82xx_start_scsi, |
2005 | .abort_isp = qla82xx_abort_isp, | |
706f457d | 2006 | .iospace_config = qla82xx_iospace_config, |
8ae6d9c7 | 2007 | .initialize_adapter = qla2x00_initialize_adapter, |
3a03eb79 AV |
2008 | }; |
2009 | ||
7ec0effd AD |
2010 | static struct isp_operations qla8044_isp_ops = { |
2011 | .pci_config = qla82xx_pci_config, | |
2012 | .reset_chip = qla82xx_reset_chip, | |
2013 | .chip_diag = qla24xx_chip_diag, | |
2014 | .config_rings = qla82xx_config_rings, | |
2015 | .reset_adapter = qla24xx_reset_adapter, | |
2016 | .nvram_config = qla81xx_nvram_config, | |
2017 | .update_fw_options = qla24xx_update_fw_options, | |
2018 | .load_risc = qla82xx_load_risc, | |
2019 | .pci_info_str = qla24xx_pci_info_str, | |
2020 | .fw_version_str = qla24xx_fw_version_str, | |
2021 | .intr_handler = qla8044_intr_handler, | |
2022 | .enable_intrs = qla82xx_enable_intrs, | |
2023 | .disable_intrs = qla82xx_disable_intrs, | |
2024 | .abort_command = qla24xx_abort_command, | |
2025 | .target_reset = qla24xx_abort_target, | |
2026 | .lun_reset = qla24xx_lun_reset, | |
2027 | .fabric_login = qla24xx_login_fabric, | |
2028 | .fabric_logout = qla24xx_fabric_logout, | |
2029 | .calc_req_entries = NULL, | |
2030 | .build_iocbs = NULL, | |
2031 | .prep_ms_iocb = qla24xx_prep_ms_iocb, | |
2032 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, | |
2033 | .read_nvram = NULL, | |
2034 | .write_nvram = NULL, | |
a1b23c5a | 2035 | .fw_dump = qla8044_fw_dump, |
7ec0effd AD |
2036 | .beacon_on = qla82xx_beacon_on, |
2037 | .beacon_off = qla82xx_beacon_off, | |
2038 | .beacon_blink = NULL, | |
888e639d | 2039 | .read_optrom = qla8044_read_optrom_data, |
7ec0effd AD |
2040 | .write_optrom = qla8044_write_optrom_data, |
2041 | .get_flash_version = qla82xx_get_flash_version, | |
2042 | .start_scsi = qla82xx_start_scsi, | |
2043 | .abort_isp = qla8044_abort_isp, | |
2044 | .iospace_config = qla82xx_iospace_config, | |
2045 | .initialize_adapter = qla2x00_initialize_adapter, | |
2046 | }; | |
2047 | ||
6246b8a1 GM |
2048 | static struct isp_operations qla83xx_isp_ops = { |
2049 | .pci_config = qla25xx_pci_config, | |
2050 | .reset_chip = qla24xx_reset_chip, | |
2051 | .chip_diag = qla24xx_chip_diag, | |
2052 | .config_rings = qla24xx_config_rings, | |
2053 | .reset_adapter = qla24xx_reset_adapter, | |
2054 | .nvram_config = qla81xx_nvram_config, | |
2055 | .update_fw_options = qla81xx_update_fw_options, | |
2056 | .load_risc = qla81xx_load_risc, | |
2057 | .pci_info_str = qla24xx_pci_info_str, | |
2058 | .fw_version_str = qla24xx_fw_version_str, | |
2059 | .intr_handler = qla24xx_intr_handler, | |
2060 | .enable_intrs = qla24xx_enable_intrs, | |
2061 | .disable_intrs = qla24xx_disable_intrs, | |
2062 | .abort_command = qla24xx_abort_command, | |
2063 | .target_reset = qla24xx_abort_target, | |
2064 | .lun_reset = qla24xx_lun_reset, | |
2065 | .fabric_login = qla24xx_login_fabric, | |
2066 | .fabric_logout = qla24xx_fabric_logout, | |
2067 | .calc_req_entries = NULL, | |
2068 | .build_iocbs = NULL, | |
2069 | .prep_ms_iocb = qla24xx_prep_ms_iocb, | |
2070 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, | |
2071 | .read_nvram = NULL, | |
2072 | .write_nvram = NULL, | |
2073 | .fw_dump = qla83xx_fw_dump, | |
2074 | .beacon_on = qla24xx_beacon_on, | |
2075 | .beacon_off = qla24xx_beacon_off, | |
2076 | .beacon_blink = qla83xx_beacon_blink, | |
2077 | .read_optrom = qla25xx_read_optrom_data, | |
2078 | .write_optrom = qla24xx_write_optrom_data, | |
2079 | .get_flash_version = qla24xx_get_flash_version, | |
2080 | .start_scsi = qla24xx_dif_start_scsi, | |
2081 | .abort_isp = qla2x00_abort_isp, | |
2082 | .iospace_config = qla83xx_iospace_config, | |
8ae6d9c7 GM |
2083 | .initialize_adapter = qla2x00_initialize_adapter, |
2084 | }; | |
2085 | ||
2086 | static struct isp_operations qlafx00_isp_ops = { | |
2087 | .pci_config = qlafx00_pci_config, | |
2088 | .reset_chip = qlafx00_soft_reset, | |
2089 | .chip_diag = qlafx00_chip_diag, | |
2090 | .config_rings = qlafx00_config_rings, | |
2091 | .reset_adapter = qlafx00_soft_reset, | |
2092 | .nvram_config = NULL, | |
2093 | .update_fw_options = NULL, | |
2094 | .load_risc = NULL, | |
2095 | .pci_info_str = qlafx00_pci_info_str, | |
2096 | .fw_version_str = qlafx00_fw_version_str, | |
2097 | .intr_handler = qlafx00_intr_handler, | |
2098 | .enable_intrs = qlafx00_enable_intrs, | |
2099 | .disable_intrs = qlafx00_disable_intrs, | |
4440e46d | 2100 | .abort_command = qla24xx_async_abort_command, |
8ae6d9c7 GM |
2101 | .target_reset = qlafx00_abort_target, |
2102 | .lun_reset = qlafx00_lun_reset, | |
2103 | .fabric_login = NULL, | |
2104 | .fabric_logout = NULL, | |
2105 | .calc_req_entries = NULL, | |
2106 | .build_iocbs = NULL, | |
2107 | .prep_ms_iocb = qla24xx_prep_ms_iocb, | |
2108 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, | |
2109 | .read_nvram = qla24xx_read_nvram_data, | |
2110 | .write_nvram = qla24xx_write_nvram_data, | |
2111 | .fw_dump = NULL, | |
2112 | .beacon_on = qla24xx_beacon_on, | |
2113 | .beacon_off = qla24xx_beacon_off, | |
2114 | .beacon_blink = NULL, | |
2115 | .read_optrom = qla24xx_read_optrom_data, | |
2116 | .write_optrom = qla24xx_write_optrom_data, | |
2117 | .get_flash_version = qla24xx_get_flash_version, | |
2118 | .start_scsi = qlafx00_start_scsi, | |
2119 | .abort_isp = qlafx00_abort_isp, | |
2120 | .iospace_config = qlafx00_iospace_config, | |
2121 | .initialize_adapter = qlafx00_initialize_adapter, | |
6246b8a1 GM |
2122 | }; |
2123 | ||
f73cb695 CD |
2124 | static struct isp_operations qla27xx_isp_ops = { |
2125 | .pci_config = qla25xx_pci_config, | |
2126 | .reset_chip = qla24xx_reset_chip, | |
2127 | .chip_diag = qla24xx_chip_diag, | |
2128 | .config_rings = qla24xx_config_rings, | |
2129 | .reset_adapter = qla24xx_reset_adapter, | |
2130 | .nvram_config = qla81xx_nvram_config, | |
2131 | .update_fw_options = qla81xx_update_fw_options, | |
2132 | .load_risc = qla81xx_load_risc, | |
2133 | .pci_info_str = qla24xx_pci_info_str, | |
2134 | .fw_version_str = qla24xx_fw_version_str, | |
2135 | .intr_handler = qla24xx_intr_handler, | |
2136 | .enable_intrs = qla24xx_enable_intrs, | |
2137 | .disable_intrs = qla24xx_disable_intrs, | |
2138 | .abort_command = qla24xx_abort_command, | |
2139 | .target_reset = qla24xx_abort_target, | |
2140 | .lun_reset = qla24xx_lun_reset, | |
2141 | .fabric_login = qla24xx_login_fabric, | |
2142 | .fabric_logout = qla24xx_fabric_logout, | |
2143 | .calc_req_entries = NULL, | |
2144 | .build_iocbs = NULL, | |
2145 | .prep_ms_iocb = qla24xx_prep_ms_iocb, | |
2146 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, | |
2147 | .read_nvram = NULL, | |
2148 | .write_nvram = NULL, | |
2149 | .fw_dump = qla27xx_fwdump, | |
2150 | .beacon_on = qla24xx_beacon_on, | |
2151 | .beacon_off = qla24xx_beacon_off, | |
2152 | .beacon_blink = qla83xx_beacon_blink, | |
2153 | .read_optrom = qla25xx_read_optrom_data, | |
2154 | .write_optrom = qla24xx_write_optrom_data, | |
2155 | .get_flash_version = qla24xx_get_flash_version, | |
2156 | .start_scsi = qla24xx_dif_start_scsi, | |
2157 | .abort_isp = qla2x00_abort_isp, | |
2158 | .iospace_config = qla83xx_iospace_config, | |
2159 | .initialize_adapter = qla2x00_initialize_adapter, | |
2160 | }; | |
2161 | ||
ea5b6382 | 2162 | static inline void |
e315cd28 | 2163 | qla2x00_set_isp_flags(struct qla_hw_data *ha) |
ea5b6382 | 2164 | { |
2165 | ha->device_type = DT_EXTENDED_IDS; | |
2166 | switch (ha->pdev->device) { | |
2167 | case PCI_DEVICE_ID_QLOGIC_ISP2100: | |
9e052e2d | 2168 | ha->isp_type |= DT_ISP2100; |
ea5b6382 | 2169 | ha->device_type &= ~DT_EXTENDED_IDS; |
441d1072 | 2170 | ha->fw_srisc_address = RISC_START_ADDRESS_2100; |
ea5b6382 | 2171 | break; |
2172 | case PCI_DEVICE_ID_QLOGIC_ISP2200: | |
9e052e2d | 2173 | ha->isp_type |= DT_ISP2200; |
ea5b6382 | 2174 | ha->device_type &= ~DT_EXTENDED_IDS; |
441d1072 | 2175 | ha->fw_srisc_address = RISC_START_ADDRESS_2100; |
ea5b6382 | 2176 | break; |
2177 | case PCI_DEVICE_ID_QLOGIC_ISP2300: | |
9e052e2d | 2178 | ha->isp_type |= DT_ISP2300; |
4a59f71d | 2179 | ha->device_type |= DT_ZIO_SUPPORTED; |
441d1072 | 2180 | ha->fw_srisc_address = RISC_START_ADDRESS_2300; |
ea5b6382 | 2181 | break; |
2182 | case PCI_DEVICE_ID_QLOGIC_ISP2312: | |
9e052e2d | 2183 | ha->isp_type |= DT_ISP2312; |
4a59f71d | 2184 | ha->device_type |= DT_ZIO_SUPPORTED; |
441d1072 | 2185 | ha->fw_srisc_address = RISC_START_ADDRESS_2300; |
ea5b6382 | 2186 | break; |
2187 | case PCI_DEVICE_ID_QLOGIC_ISP2322: | |
9e052e2d | 2188 | ha->isp_type |= DT_ISP2322; |
4a59f71d | 2189 | ha->device_type |= DT_ZIO_SUPPORTED; |
ea5b6382 | 2190 | if (ha->pdev->subsystem_vendor == 0x1028 && |
2191 | ha->pdev->subsystem_device == 0x0170) | |
2192 | ha->device_type |= DT_OEM_001; | |
441d1072 | 2193 | ha->fw_srisc_address = RISC_START_ADDRESS_2300; |
ea5b6382 | 2194 | break; |
2195 | case PCI_DEVICE_ID_QLOGIC_ISP6312: | |
9e052e2d | 2196 | ha->isp_type |= DT_ISP6312; |
441d1072 | 2197 | ha->fw_srisc_address = RISC_START_ADDRESS_2300; |
ea5b6382 | 2198 | break; |
2199 | case PCI_DEVICE_ID_QLOGIC_ISP6322: | |
9e052e2d | 2200 | ha->isp_type |= DT_ISP6322; |
441d1072 | 2201 | ha->fw_srisc_address = RISC_START_ADDRESS_2300; |
ea5b6382 | 2202 | break; |
2203 | case PCI_DEVICE_ID_QLOGIC_ISP2422: | |
9e052e2d | 2204 | ha->isp_type |= DT_ISP2422; |
4a59f71d | 2205 | ha->device_type |= DT_ZIO_SUPPORTED; |
e428924c | 2206 | ha->device_type |= DT_FWI2; |
c76f2c01 | 2207 | ha->device_type |= DT_IIDMA; |
441d1072 | 2208 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; |
ea5b6382 | 2209 | break; |
2210 | case PCI_DEVICE_ID_QLOGIC_ISP2432: | |
9e052e2d | 2211 | ha->isp_type |= DT_ISP2432; |
4a59f71d | 2212 | ha->device_type |= DT_ZIO_SUPPORTED; |
e428924c | 2213 | ha->device_type |= DT_FWI2; |
c76f2c01 | 2214 | ha->device_type |= DT_IIDMA; |
441d1072 | 2215 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; |
ea5b6382 | 2216 | break; |
4d4df193 | 2217 | case PCI_DEVICE_ID_QLOGIC_ISP8432: |
9e052e2d | 2218 | ha->isp_type |= DT_ISP8432; |
4d4df193 HK |
2219 | ha->device_type |= DT_ZIO_SUPPORTED; |
2220 | ha->device_type |= DT_FWI2; | |
2221 | ha->device_type |= DT_IIDMA; | |
2222 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
2223 | break; | |
044cc6c8 | 2224 | case PCI_DEVICE_ID_QLOGIC_ISP5422: |
9e052e2d | 2225 | ha->isp_type |= DT_ISP5422; |
e428924c | 2226 | ha->device_type |= DT_FWI2; |
441d1072 | 2227 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; |
ea5b6382 | 2228 | break; |
044cc6c8 | 2229 | case PCI_DEVICE_ID_QLOGIC_ISP5432: |
9e052e2d | 2230 | ha->isp_type |= DT_ISP5432; |
e428924c | 2231 | ha->device_type |= DT_FWI2; |
441d1072 | 2232 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; |
ea5b6382 | 2233 | break; |
c3a2f0df | 2234 | case PCI_DEVICE_ID_QLOGIC_ISP2532: |
9e052e2d | 2235 | ha->isp_type |= DT_ISP2532; |
c3a2f0df AV |
2236 | ha->device_type |= DT_ZIO_SUPPORTED; |
2237 | ha->device_type |= DT_FWI2; | |
2238 | ha->device_type |= DT_IIDMA; | |
441d1072 | 2239 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; |
ea5b6382 | 2240 | break; |
3a03eb79 | 2241 | case PCI_DEVICE_ID_QLOGIC_ISP8001: |
9e052e2d | 2242 | ha->isp_type |= DT_ISP8001; |
3a03eb79 AV |
2243 | ha->device_type |= DT_ZIO_SUPPORTED; |
2244 | ha->device_type |= DT_FWI2; | |
2245 | ha->device_type |= DT_IIDMA; | |
2246 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
2247 | break; | |
a9083016 | 2248 | case PCI_DEVICE_ID_QLOGIC_ISP8021: |
9e052e2d | 2249 | ha->isp_type |= DT_ISP8021; |
a9083016 GM |
2250 | ha->device_type |= DT_ZIO_SUPPORTED; |
2251 | ha->device_type |= DT_FWI2; | |
2252 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
2253 | /* Initialize 82XX ISP flags */ | |
2254 | qla82xx_init_flags(ha); | |
2255 | break; | |
7ec0effd | 2256 | case PCI_DEVICE_ID_QLOGIC_ISP8044: |
9e052e2d | 2257 | ha->isp_type |= DT_ISP8044; |
7ec0effd AD |
2258 | ha->device_type |= DT_ZIO_SUPPORTED; |
2259 | ha->device_type |= DT_FWI2; | |
2260 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
2261 | /* Initialize 82XX ISP flags */ | |
2262 | qla82xx_init_flags(ha); | |
2263 | break; | |
6246b8a1 | 2264 | case PCI_DEVICE_ID_QLOGIC_ISP2031: |
9e052e2d | 2265 | ha->isp_type |= DT_ISP2031; |
6246b8a1 GM |
2266 | ha->device_type |= DT_ZIO_SUPPORTED; |
2267 | ha->device_type |= DT_FWI2; | |
2268 | ha->device_type |= DT_IIDMA; | |
2269 | ha->device_type |= DT_T10_PI; | |
2270 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
2271 | break; | |
2272 | case PCI_DEVICE_ID_QLOGIC_ISP8031: | |
9e052e2d | 2273 | ha->isp_type |= DT_ISP8031; |
6246b8a1 GM |
2274 | ha->device_type |= DT_ZIO_SUPPORTED; |
2275 | ha->device_type |= DT_FWI2; | |
2276 | ha->device_type |= DT_IIDMA; | |
2277 | ha->device_type |= DT_T10_PI; | |
2278 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
2279 | break; | |
8ae6d9c7 | 2280 | case PCI_DEVICE_ID_QLOGIC_ISPF001: |
9e052e2d | 2281 | ha->isp_type |= DT_ISPFX00; |
8ae6d9c7 | 2282 | break; |
f73cb695 | 2283 | case PCI_DEVICE_ID_QLOGIC_ISP2071: |
9e052e2d | 2284 | ha->isp_type |= DT_ISP2071; |
f73cb695 CD |
2285 | ha->device_type |= DT_ZIO_SUPPORTED; |
2286 | ha->device_type |= DT_FWI2; | |
2287 | ha->device_type |= DT_IIDMA; | |
8ce3f570 | 2288 | ha->device_type |= DT_T10_PI; |
f73cb695 CD |
2289 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; |
2290 | break; | |
2c5bbbb2 | 2291 | case PCI_DEVICE_ID_QLOGIC_ISP2271: |
9e052e2d | 2292 | ha->isp_type |= DT_ISP2271; |
2c5bbbb2 JC |
2293 | ha->device_type |= DT_ZIO_SUPPORTED; |
2294 | ha->device_type |= DT_FWI2; | |
2295 | ha->device_type |= DT_IIDMA; | |
8ce3f570 | 2296 | ha->device_type |= DT_T10_PI; |
2c5bbbb2 JC |
2297 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; |
2298 | break; | |
2b48992f | 2299 | case PCI_DEVICE_ID_QLOGIC_ISP2261: |
9e052e2d | 2300 | ha->isp_type |= DT_ISP2261; |
2b48992f SC |
2301 | ha->device_type |= DT_ZIO_SUPPORTED; |
2302 | ha->device_type |= DT_FWI2; | |
2303 | ha->device_type |= DT_IIDMA; | |
8ce3f570 | 2304 | ha->device_type |= DT_T10_PI; |
2b48992f SC |
2305 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; |
2306 | break; | |
ea5b6382 | 2307 | } |
e5b68a61 | 2308 | |
a9083016 | 2309 | if (IS_QLA82XX(ha)) |
43a9c38b | 2310 | ha->port_no = ha->portnum & 1; |
f73cb695 | 2311 | else { |
a9083016 GM |
2312 | /* Get adapter physical port no from interrupt pin register. */ |
2313 | pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); | |
f73cb695 CD |
2314 | if (IS_QLA27XX(ha)) |
2315 | ha->port_no--; | |
2316 | else | |
2317 | ha->port_no = !(ha->port_no & 1); | |
2318 | } | |
a9083016 | 2319 | |
7c3df132 | 2320 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, |
d8424f68 | 2321 | "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", |
f73cb695 | 2322 | ha->device_type, ha->port_no, ha->fw_srisc_address); |
ea5b6382 | 2323 | } |
2324 | ||
1e99e33a AV |
2325 | static void |
2326 | qla2xxx_scan_start(struct Scsi_Host *shost) | |
2327 | { | |
e315cd28 | 2328 | scsi_qla_host_t *vha = shost_priv(shost); |
1e99e33a | 2329 | |
cbc8eb67 AV |
2330 | if (vha->hw->flags.running_gold_fw) |
2331 | return; | |
2332 | ||
e315cd28 AC |
2333 | set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); |
2334 | set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); | |
2335 | set_bit(RSCN_UPDATE, &vha->dpc_flags); | |
2336 | set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); | |
1e99e33a AV |
2337 | } |
2338 | ||
2339 | static int | |
2340 | qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) | |
2341 | { | |
e315cd28 | 2342 | scsi_qla_host_t *vha = shost_priv(shost); |
1e99e33a | 2343 | |
e315cd28 | 2344 | if (!vha->host) |
1e99e33a | 2345 | return 1; |
e315cd28 | 2346 | if (time > vha->hw->loop_reset_delay * HZ) |
1e99e33a AV |
2347 | return 1; |
2348 | ||
e315cd28 | 2349 | return atomic_read(&vha->loop_state) == LOOP_READY; |
1e99e33a AV |
2350 | } |
2351 | ||
1da177e4 LT |
2352 | /* |
2353 | * PCI driver interface | |
2354 | */ | |
6f039790 | 2355 | static int |
7ee61397 | 2356 | qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) |
1da177e4 | 2357 | { |
a1541d5a | 2358 | int ret = -ENODEV; |
1da177e4 | 2359 | struct Scsi_Host *host; |
e315cd28 AC |
2360 | scsi_qla_host_t *base_vha = NULL; |
2361 | struct qla_hw_data *ha; | |
29856e28 | 2362 | char pci_info[30]; |
7d613ac6 | 2363 | char fw_str[30], wq_name[30]; |
5433383e | 2364 | struct scsi_host_template *sht; |
642ef983 | 2365 | int bars, mem_only = 0; |
e315cd28 | 2366 | uint16_t req_length = 0, rsp_length = 0; |
73208dfd AC |
2367 | struct req_que *req = NULL; |
2368 | struct rsp_que *rsp = NULL; | |
285d0321 | 2369 | bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); |
a5326f86 | 2370 | sht = &qla2xxx_driver_template; |
5433383e | 2371 | if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || |
8bc69e7d | 2372 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || |
4d4df193 | 2373 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || |
8bc69e7d | 2374 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || |
c3a2f0df | 2375 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || |
3a03eb79 | 2376 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || |
a9083016 | 2377 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || |
6246b8a1 GM |
2378 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || |
2379 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || | |
8ae6d9c7 | 2380 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || |
7ec0effd | 2381 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || |
f73cb695 | 2382 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || |
2c5bbbb2 | 2383 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || |
2b48992f SC |
2384 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || |
2385 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) { | |
285d0321 | 2386 | bars = pci_select_bars(pdev, IORESOURCE_MEM); |
09483916 | 2387 | mem_only = 1; |
7c3df132 SK |
2388 | ql_dbg_pci(ql_dbg_init, pdev, 0x0007, |
2389 | "Mem only adapter.\n"); | |
285d0321 | 2390 | } |
7c3df132 SK |
2391 | ql_dbg_pci(ql_dbg_init, pdev, 0x0008, |
2392 | "Bars=%d.\n", bars); | |
285d0321 | 2393 | |
09483916 BH |
2394 | if (mem_only) { |
2395 | if (pci_enable_device_mem(pdev)) | |
2396 | goto probe_out; | |
2397 | } else { | |
2398 | if (pci_enable_device(pdev)) | |
2399 | goto probe_out; | |
2400 | } | |
285d0321 | 2401 | |
0927678f JB |
2402 | /* This may fail but that's ok */ |
2403 | pci_enable_pcie_error_reporting(pdev); | |
285d0321 | 2404 | |
e315cd28 AC |
2405 | ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); |
2406 | if (!ha) { | |
7c3df132 SK |
2407 | ql_log_pci(ql_log_fatal, pdev, 0x0009, |
2408 | "Unable to allocate memory for ha.\n"); | |
e315cd28 | 2409 | goto probe_out; |
1da177e4 | 2410 | } |
7c3df132 SK |
2411 | ql_dbg_pci(ql_dbg_init, pdev, 0x000a, |
2412 | "Memory allocated for ha=%p.\n", ha); | |
e315cd28 | 2413 | ha->pdev = pdev; |
2d70c103 | 2414 | ha->tgt.enable_class_2 = ql2xenableclass2; |
33e79977 QT |
2415 | INIT_LIST_HEAD(&ha->tgt.q_full_list); |
2416 | spin_lock_init(&ha->tgt.q_full_lock); | |
7560151b | 2417 | spin_lock_init(&ha->tgt.sess_lock); |
2f424b9b QT |
2418 | spin_lock_init(&ha->tgt.atio_lock); |
2419 | ||
1da177e4 LT |
2420 | |
2421 | /* Clear our data area */ | |
285d0321 | 2422 | ha->bars = bars; |
09483916 | 2423 | ha->mem_only = mem_only; |
df4bf0bb | 2424 | spin_lock_init(&ha->hardware_lock); |
339aa70e | 2425 | spin_lock_init(&ha->vport_slock); |
a9b6f722 | 2426 | mutex_init(&ha->selflogin_lock); |
7a8ab9c8 | 2427 | mutex_init(&ha->optrom_mutex); |
1da177e4 | 2428 | |
ea5b6382 | 2429 | /* Set ISP-type information. */ |
2430 | qla2x00_set_isp_flags(ha); | |
ca79cf66 DG |
2431 | |
2432 | /* Set EEH reset type to fundamental if required by hba */ | |
95676112 | 2433 | if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || |
f73cb695 | 2434 | IS_QLA83XX(ha) || IS_QLA27XX(ha)) |
ca79cf66 | 2435 | pdev->needs_freset = 1; |
ca79cf66 | 2436 | |
cba1e47f CD |
2437 | ha->prev_topology = 0; |
2438 | ha->init_cb_size = sizeof(init_cb_t); | |
2439 | ha->link_data_rate = PORT_SPEED_UNKNOWN; | |
2440 | ha->optrom_size = OPTROM_SIZE_2300; | |
2441 | ||
abbd8870 | 2442 | /* Assign ISP specific operations. */ |
1da177e4 | 2443 | if (IS_QLA2100(ha)) { |
642ef983 | 2444 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; |
1da177e4 | 2445 | ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; |
e315cd28 AC |
2446 | req_length = REQUEST_ENTRY_CNT_2100; |
2447 | rsp_length = RESPONSE_ENTRY_CNT_2100; | |
2448 | ha->max_loop_id = SNS_LAST_LOOP_ID_2100; | |
abbd8870 | 2449 | ha->gid_list_info_size = 4; |
3a03eb79 AV |
2450 | ha->flash_conf_off = ~0; |
2451 | ha->flash_data_off = ~0; | |
2452 | ha->nvram_conf_off = ~0; | |
2453 | ha->nvram_data_off = ~0; | |
fd34f556 | 2454 | ha->isp_ops = &qla2100_isp_ops; |
1da177e4 | 2455 | } else if (IS_QLA2200(ha)) { |
642ef983 | 2456 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; |
67ddda35 | 2457 | ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; |
e315cd28 AC |
2458 | req_length = REQUEST_ENTRY_CNT_2200; |
2459 | rsp_length = RESPONSE_ENTRY_CNT_2100; | |
2460 | ha->max_loop_id = SNS_LAST_LOOP_ID_2100; | |
abbd8870 | 2461 | ha->gid_list_info_size = 4; |
3a03eb79 AV |
2462 | ha->flash_conf_off = ~0; |
2463 | ha->flash_data_off = ~0; | |
2464 | ha->nvram_conf_off = ~0; | |
2465 | ha->nvram_data_off = ~0; | |
fd34f556 | 2466 | ha->isp_ops = &qla2100_isp_ops; |
fca29703 | 2467 | } else if (IS_QLA23XX(ha)) { |
642ef983 | 2468 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; |
1da177e4 | 2469 | ha->mbx_count = MAILBOX_REGISTER_COUNT; |
e315cd28 AC |
2470 | req_length = REQUEST_ENTRY_CNT_2200; |
2471 | rsp_length = RESPONSE_ENTRY_CNT_2300; | |
2472 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; | |
abbd8870 | 2473 | ha->gid_list_info_size = 6; |
854165f4 | 2474 | if (IS_QLA2322(ha) || IS_QLA6322(ha)) |
2475 | ha->optrom_size = OPTROM_SIZE_2322; | |
3a03eb79 AV |
2476 | ha->flash_conf_off = ~0; |
2477 | ha->flash_data_off = ~0; | |
2478 | ha->nvram_conf_off = ~0; | |
2479 | ha->nvram_data_off = ~0; | |
fd34f556 | 2480 | ha->isp_ops = &qla2300_isp_ops; |
4d4df193 | 2481 | } else if (IS_QLA24XX_TYPE(ha)) { |
642ef983 | 2482 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; |
fca29703 | 2483 | ha->mbx_count = MAILBOX_REGISTER_COUNT; |
e315cd28 AC |
2484 | req_length = REQUEST_ENTRY_CNT_24XX; |
2485 | rsp_length = RESPONSE_ENTRY_CNT_2300; | |
2d70c103 | 2486 | ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; |
e315cd28 | 2487 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; |
2c3dfe3f | 2488 | ha->init_cb_size = sizeof(struct mid_init_cb_24xx); |
fca29703 | 2489 | ha->gid_list_info_size = 8; |
854165f4 | 2490 | ha->optrom_size = OPTROM_SIZE_24XX; |
73208dfd | 2491 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; |
fd34f556 | 2492 | ha->isp_ops = &qla24xx_isp_ops; |
3a03eb79 AV |
2493 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; |
2494 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA; | |
2495 | ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; | |
2496 | ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; | |
c3a2f0df | 2497 | } else if (IS_QLA25XX(ha)) { |
642ef983 | 2498 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; |
c3a2f0df | 2499 | ha->mbx_count = MAILBOX_REGISTER_COUNT; |
e315cd28 AC |
2500 | req_length = REQUEST_ENTRY_CNT_24XX; |
2501 | rsp_length = RESPONSE_ENTRY_CNT_2300; | |
2d70c103 | 2502 | ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; |
e315cd28 | 2503 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; |
c3a2f0df | 2504 | ha->init_cb_size = sizeof(struct mid_init_cb_24xx); |
c3a2f0df AV |
2505 | ha->gid_list_info_size = 8; |
2506 | ha->optrom_size = OPTROM_SIZE_25XX; | |
73208dfd | 2507 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; |
c3a2f0df | 2508 | ha->isp_ops = &qla25xx_isp_ops; |
3a03eb79 AV |
2509 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; |
2510 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA; | |
2511 | ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; | |
2512 | ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; | |
2513 | } else if (IS_QLA81XX(ha)) { | |
642ef983 | 2514 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; |
3a03eb79 AV |
2515 | ha->mbx_count = MAILBOX_REGISTER_COUNT; |
2516 | req_length = REQUEST_ENTRY_CNT_24XX; | |
2517 | rsp_length = RESPONSE_ENTRY_CNT_2300; | |
aa230bc5 | 2518 | ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; |
3a03eb79 AV |
2519 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; |
2520 | ha->init_cb_size = sizeof(struct mid_init_cb_81xx); | |
2521 | ha->gid_list_info_size = 8; | |
2522 | ha->optrom_size = OPTROM_SIZE_81XX; | |
40859ae5 | 2523 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; |
3a03eb79 AV |
2524 | ha->isp_ops = &qla81xx_isp_ops; |
2525 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; | |
2526 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; | |
2527 | ha->nvram_conf_off = ~0; | |
2528 | ha->nvram_data_off = ~0; | |
a9083016 | 2529 | } else if (IS_QLA82XX(ha)) { |
642ef983 | 2530 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; |
a9083016 GM |
2531 | ha->mbx_count = MAILBOX_REGISTER_COUNT; |
2532 | req_length = REQUEST_ENTRY_CNT_82XX; | |
2533 | rsp_length = RESPONSE_ENTRY_CNT_82XX; | |
2534 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; | |
2535 | ha->init_cb_size = sizeof(struct mid_init_cb_81xx); | |
2536 | ha->gid_list_info_size = 8; | |
2537 | ha->optrom_size = OPTROM_SIZE_82XX; | |
087c621e | 2538 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; |
a9083016 GM |
2539 | ha->isp_ops = &qla82xx_isp_ops; |
2540 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; | |
2541 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA; | |
2542 | ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; | |
2543 | ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; | |
7ec0effd AD |
2544 | } else if (IS_QLA8044(ha)) { |
2545 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; | |
2546 | ha->mbx_count = MAILBOX_REGISTER_COUNT; | |
2547 | req_length = REQUEST_ENTRY_CNT_82XX; | |
2548 | rsp_length = RESPONSE_ENTRY_CNT_82XX; | |
2549 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; | |
2550 | ha->init_cb_size = sizeof(struct mid_init_cb_81xx); | |
2551 | ha->gid_list_info_size = 8; | |
2552 | ha->optrom_size = OPTROM_SIZE_83XX; | |
2553 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; | |
2554 | ha->isp_ops = &qla8044_isp_ops; | |
2555 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; | |
2556 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA; | |
2557 | ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; | |
2558 | ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; | |
6246b8a1 | 2559 | } else if (IS_QLA83XX(ha)) { |
7d613ac6 | 2560 | ha->portnum = PCI_FUNC(ha->pdev->devfn); |
642ef983 | 2561 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; |
6246b8a1 | 2562 | ha->mbx_count = MAILBOX_REGISTER_COUNT; |
f2ea653f | 2563 | req_length = REQUEST_ENTRY_CNT_83XX; |
e7b42e33 | 2564 | rsp_length = RESPONSE_ENTRY_CNT_83XX; |
b8aa4bdf | 2565 | ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; |
6246b8a1 GM |
2566 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; |
2567 | ha->init_cb_size = sizeof(struct mid_init_cb_81xx); | |
2568 | ha->gid_list_info_size = 8; | |
2569 | ha->optrom_size = OPTROM_SIZE_83XX; | |
2570 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; | |
2571 | ha->isp_ops = &qla83xx_isp_ops; | |
2572 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; | |
2573 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; | |
2574 | ha->nvram_conf_off = ~0; | |
2575 | ha->nvram_data_off = ~0; | |
8ae6d9c7 GM |
2576 | } else if (IS_QLAFX00(ha)) { |
2577 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; | |
2578 | ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; | |
2579 | ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; | |
2580 | req_length = REQUEST_ENTRY_CNT_FX00; | |
2581 | rsp_length = RESPONSE_ENTRY_CNT_FX00; | |
8ae6d9c7 GM |
2582 | ha->isp_ops = &qlafx00_isp_ops; |
2583 | ha->port_down_retry_count = 30; /* default value */ | |
2584 | ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; | |
2585 | ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; | |
71e56003 | 2586 | ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; |
8ae6d9c7 | 2587 | ha->mr.fw_hbt_en = 1; |
e8f5e95d AB |
2588 | ha->mr.host_info_resend = false; |
2589 | ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; | |
f73cb695 CD |
2590 | } else if (IS_QLA27XX(ha)) { |
2591 | ha->portnum = PCI_FUNC(ha->pdev->devfn); | |
2592 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; | |
2593 | ha->mbx_count = MAILBOX_REGISTER_COUNT; | |
e7b42e33 QT |
2594 | req_length = REQUEST_ENTRY_CNT_83XX; |
2595 | rsp_length = RESPONSE_ENTRY_CNT_83XX; | |
b20f02e1 | 2596 | ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; |
f73cb695 CD |
2597 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; |
2598 | ha->init_cb_size = sizeof(struct mid_init_cb_81xx); | |
2599 | ha->gid_list_info_size = 8; | |
2600 | ha->optrom_size = OPTROM_SIZE_83XX; | |
2601 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; | |
2602 | ha->isp_ops = &qla27xx_isp_ops; | |
2603 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; | |
2604 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; | |
2605 | ha->nvram_conf_off = ~0; | |
2606 | ha->nvram_data_off = ~0; | |
1da177e4 | 2607 | } |
6246b8a1 | 2608 | |
7c3df132 SK |
2609 | ql_dbg_pci(ql_dbg_init, pdev, 0x001e, |
2610 | "mbx_count=%d, req_length=%d, " | |
2611 | "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " | |
642ef983 CD |
2612 | "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " |
2613 | "max_fibre_devices=%d.\n", | |
7c3df132 SK |
2614 | ha->mbx_count, req_length, rsp_length, ha->max_loop_id, |
2615 | ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, | |
642ef983 | 2616 | ha->nvram_npiv_size, ha->max_fibre_devices); |
7c3df132 SK |
2617 | ql_dbg_pci(ql_dbg_init, pdev, 0x001f, |
2618 | "isp_ops=%p, flash_conf_off=%d, " | |
2619 | "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", | |
2620 | ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, | |
2621 | ha->nvram_conf_off, ha->nvram_data_off); | |
706f457d GM |
2622 | |
2623 | /* Configure PCI I/O space */ | |
2624 | ret = ha->isp_ops->iospace_config(ha); | |
2625 | if (ret) | |
0a63ad12 | 2626 | goto iospace_config_failed; |
706f457d GM |
2627 | |
2628 | ql_log_pci(ql_log_info, pdev, 0x001d, | |
2629 | "Found an ISP%04X irq %d iobase 0x%p.\n", | |
2630 | pdev->device, pdev->irq, ha->iobase); | |
6c2f527c | 2631 | mutex_init(&ha->vport_lock); |
0b05a1f0 MB |
2632 | init_completion(&ha->mbx_cmd_comp); |
2633 | complete(&ha->mbx_cmd_comp); | |
2634 | init_completion(&ha->mbx_intr_comp); | |
23f2ebd1 | 2635 | init_completion(&ha->dcbx_comp); |
f356bef1 | 2636 | init_completion(&ha->lb_portup_comp); |
1da177e4 | 2637 | |
2c3dfe3f | 2638 | set_bit(0, (unsigned long *) ha->vp_idx_map); |
1da177e4 | 2639 | |
53303c42 | 2640 | qla2x00_config_dma_addressing(ha); |
7c3df132 SK |
2641 | ql_dbg_pci(ql_dbg_init, pdev, 0x0020, |
2642 | "64 Bit addressing is %s.\n", | |
2643 | ha->flags.enable_64bit_addressing ? "enable" : | |
2644 | "disable"); | |
73208dfd | 2645 | ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); |
b2a72ec3 | 2646 | if (ret) { |
7c3df132 SK |
2647 | ql_log_pci(ql_log_fatal, pdev, 0x0031, |
2648 | "Failed to allocate memory for adapter, aborting.\n"); | |
1da177e4 | 2649 | |
e315cd28 AC |
2650 | goto probe_hw_failed; |
2651 | } | |
2652 | ||
73208dfd | 2653 | req->max_q_depth = MAX_Q_DEPTH; |
e315cd28 | 2654 | if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) |
73208dfd AC |
2655 | req->max_q_depth = ql2xmaxqdepth; |
2656 | ||
e315cd28 AC |
2657 | |
2658 | base_vha = qla2x00_create_host(sht, ha); | |
2659 | if (!base_vha) { | |
a1541d5a | 2660 | ret = -ENOMEM; |
6e9f21f3 | 2661 | qla2x00_mem_free(ha); |
2afa19a9 AC |
2662 | qla2x00_free_req_que(ha, req); |
2663 | qla2x00_free_rsp_que(ha, rsp); | |
e315cd28 | 2664 | goto probe_hw_failed; |
1da177e4 LT |
2665 | } |
2666 | ||
e315cd28 | 2667 | pci_set_drvdata(pdev, base_vha); |
6b383979 | 2668 | set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); |
e315cd28 | 2669 | |
e315cd28 | 2670 | host = base_vha->host; |
2afa19a9 | 2671 | base_vha->req = req; |
73208dfd | 2672 | if (IS_QLA2XXX_MIDTYPE(ha)) |
e315cd28 | 2673 | base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx; |
73208dfd | 2674 | else |
e315cd28 AC |
2675 | base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + |
2676 | base_vha->vp_idx; | |
58548cb5 | 2677 | |
8ae6d9c7 GM |
2678 | /* Setup fcport template structure. */ |
2679 | ha->mr.fcport.vha = base_vha; | |
2680 | ha->mr.fcport.port_type = FCT_UNKNOWN; | |
2681 | ha->mr.fcport.loop_id = FC_NO_LOOP_ID; | |
2682 | qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); | |
2683 | ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; | |
2684 | ha->mr.fcport.scan_state = 1; | |
2685 | ||
58548cb5 GM |
2686 | /* Set the SG table size based on ISP type */ |
2687 | if (!IS_FWI2_CAPABLE(ha)) { | |
2688 | if (IS_QLA2100(ha)) | |
2689 | host->sg_tablesize = 32; | |
2690 | } else { | |
2691 | if (!IS_QLA82XX(ha)) | |
2692 | host->sg_tablesize = QLA_SG_ALL; | |
2693 | } | |
642ef983 | 2694 | host->max_id = ha->max_fibre_devices; |
e315cd28 AC |
2695 | host->cmd_per_lun = 3; |
2696 | host->unique_id = host->host_no; | |
e02587d7 | 2697 | if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) |
0c470874 AE |
2698 | host->max_cmd_len = 32; |
2699 | else | |
2700 | host->max_cmd_len = MAX_CMDSZ; | |
e315cd28 | 2701 | host->max_channel = MAX_BUSES - 1; |
755f516b HR |
2702 | /* Older HBAs support only 16-bit LUNs */ |
2703 | if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && | |
2704 | ql2xmaxlun > 0xffff) | |
2705 | host->max_lun = 0xffff; | |
2706 | else | |
2707 | host->max_lun = ql2xmaxlun; | |
e315cd28 | 2708 | host->transportt = qla2xxx_transport_template; |
9a069e19 | 2709 | sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); |
e315cd28 | 2710 | |
7c3df132 SK |
2711 | ql_dbg(ql_dbg_init, base_vha, 0x0033, |
2712 | "max_id=%d this_id=%d " | |
2713 | "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " | |
1abf635d | 2714 | "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, |
7c3df132 SK |
2715 | host->this_id, host->cmd_per_lun, host->unique_id, |
2716 | host->max_cmd_len, host->max_channel, host->max_lun, | |
2717 | host->transportt, sht->vendor_id); | |
2718 | ||
9a347ff4 CD |
2719 | que_init: |
2720 | /* Alloc arrays of request and response ring ptrs */ | |
2721 | if (!qla2x00_alloc_queues(ha, req, rsp)) { | |
2722 | ql_log(ql_log_fatal, base_vha, 0x003d, | |
2723 | "Failed to allocate memory for queue pointers..." | |
2724 | "aborting.\n"); | |
2725 | goto probe_init_failed; | |
2726 | } | |
2727 | ||
2d70c103 | 2728 | qlt_probe_one_stage1(base_vha, ha); |
9a347ff4 | 2729 | |
73208dfd AC |
2730 | /* Set up the irqs */ |
2731 | ret = qla2x00_request_irqs(ha, rsp); | |
2732 | if (ret) | |
6e9f21f3 | 2733 | goto probe_init_failed; |
90a86fc0 JC |
2734 | |
2735 | pci_save_state(pdev); | |
2736 | ||
9a347ff4 | 2737 | /* Assign back pointers */ |
2afa19a9 AC |
2738 | rsp->req = req; |
2739 | req->rsp = rsp; | |
9a347ff4 | 2740 | |
8ae6d9c7 GM |
2741 | if (IS_QLAFX00(ha)) { |
2742 | ha->rsp_q_map[0] = rsp; | |
2743 | ha->req_q_map[0] = req; | |
2744 | set_bit(0, ha->req_qid_map); | |
2745 | set_bit(0, ha->rsp_qid_map); | |
2746 | } | |
2747 | ||
08029990 AV |
2748 | /* FWI2-capable only. */ |
2749 | req->req_q_in = &ha->iobase->isp24.req_q_in; | |
2750 | req->req_q_out = &ha->iobase->isp24.req_q_out; | |
2751 | rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; | |
2752 | rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; | |
f73cb695 | 2753 | if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) { |
08029990 AV |
2754 | req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; |
2755 | req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; | |
2756 | rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; | |
2757 | rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; | |
17d98630 AC |
2758 | } |
2759 | ||
8ae6d9c7 GM |
2760 | if (IS_QLAFX00(ha)) { |
2761 | req->req_q_in = &ha->iobase->ispfx00.req_q_in; | |
2762 | req->req_q_out = &ha->iobase->ispfx00.req_q_out; | |
2763 | rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; | |
2764 | rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; | |
2765 | } | |
2766 | ||
7ec0effd | 2767 | if (IS_P3P_TYPE(ha)) { |
a9083016 GM |
2768 | req->req_q_out = &ha->iobase->isp82.req_q_out[0]; |
2769 | rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; | |
2770 | rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; | |
2771 | } | |
2772 | ||
7c3df132 SK |
2773 | ql_dbg(ql_dbg_multiq, base_vha, 0xc009, |
2774 | "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", | |
2775 | ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); | |
2776 | ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, | |
2777 | "req->req_q_in=%p req->req_q_out=%p " | |
2778 | "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", | |
2779 | req->req_q_in, req->req_q_out, | |
2780 | rsp->rsp_q_in, rsp->rsp_q_out); | |
2781 | ql_dbg(ql_dbg_init, base_vha, 0x003e, | |
2782 | "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", | |
2783 | ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); | |
2784 | ql_dbg(ql_dbg_init, base_vha, 0x003f, | |
2785 | "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", | |
2786 | req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); | |
1da177e4 | 2787 | |
8ae6d9c7 | 2788 | if (ha->isp_ops->initialize_adapter(base_vha)) { |
7c3df132 SK |
2789 | ql_log(ql_log_fatal, base_vha, 0x00d6, |
2790 | "Failed to initialize adapter - Adapter flags %x.\n", | |
2791 | base_vha->device_flags); | |
1da177e4 | 2792 | |
a9083016 GM |
2793 | if (IS_QLA82XX(ha)) { |
2794 | qla82xx_idc_lock(ha); | |
2795 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | |
7d613ac6 | 2796 | QLA8XXX_DEV_FAILED); |
a9083016 | 2797 | qla82xx_idc_unlock(ha); |
7c3df132 SK |
2798 | ql_log(ql_log_fatal, base_vha, 0x00d7, |
2799 | "HW State: FAILED.\n"); | |
7ec0effd AD |
2800 | } else if (IS_QLA8044(ha)) { |
2801 | qla8044_idc_lock(ha); | |
2802 | qla8044_wr_direct(base_vha, | |
2803 | QLA8044_CRB_DEV_STATE_INDEX, | |
2804 | QLA8XXX_DEV_FAILED); | |
2805 | qla8044_idc_unlock(ha); | |
2806 | ql_log(ql_log_fatal, base_vha, 0x0150, | |
2807 | "HW State: FAILED.\n"); | |
a9083016 GM |
2808 | } |
2809 | ||
a1541d5a | 2810 | ret = -ENODEV; |
1da177e4 LT |
2811 | goto probe_failed; |
2812 | } | |
2813 | ||
3b1bef64 CD |
2814 | if (IS_QLAFX00(ha)) |
2815 | host->can_queue = QLAFX00_MAX_CANQUEUE; | |
2816 | else | |
2817 | host->can_queue = req->num_outstanding_cmds - 10; | |
2818 | ||
2819 | ql_dbg(ql_dbg_init, base_vha, 0x0032, | |
2820 | "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", | |
2821 | host->can_queue, base_vha->req, | |
2822 | base_vha->mgmt_svr_loop_id, host->sg_tablesize); | |
2823 | ||
7163ea81 AC |
2824 | if (ha->mqenable) { |
2825 | if (qla25xx_setup_mode(base_vha)) { | |
7c3df132 SK |
2826 | ql_log(ql_log_warn, base_vha, 0x00ec, |
2827 | "Failed to create queues, falling back to single queue mode.\n"); | |
7163ea81 AC |
2828 | goto que_init; |
2829 | } | |
2830 | } | |
68ca949c | 2831 | |
cbc8eb67 AV |
2832 | if (ha->flags.running_gold_fw) |
2833 | goto skip_dpc; | |
2834 | ||
1da177e4 LT |
2835 | /* |
2836 | * Startup the kernel thread for this host adapter | |
2837 | */ | |
39a11240 | 2838 | ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, |
7c3df132 | 2839 | "%s_dpc", base_vha->host_str); |
39a11240 | 2840 | if (IS_ERR(ha->dpc_thread)) { |
7c3df132 SK |
2841 | ql_log(ql_log_fatal, base_vha, 0x00ed, |
2842 | "Failed to start DPC thread.\n"); | |
39a11240 | 2843 | ret = PTR_ERR(ha->dpc_thread); |
1da177e4 LT |
2844 | goto probe_failed; |
2845 | } | |
7c3df132 SK |
2846 | ql_dbg(ql_dbg_init, base_vha, 0x00ee, |
2847 | "DPC thread started successfully.\n"); | |
1da177e4 | 2848 | |
2d70c103 NB |
2849 | /* |
2850 | * If we're not coming up in initiator mode, we might sit for | |
2851 | * a while without waking up the dpc thread, which leads to a | |
2852 | * stuck process warning. So just kick the dpc once here and | |
2853 | * let the kthread start (and go back to sleep in qla2x00_do_dpc). | |
2854 | */ | |
2855 | qla2xxx_wake_dpc(base_vha); | |
2856 | ||
f3ddac19 CD |
2857 | INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); |
2858 | ||
81178772 SK |
2859 | if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { |
2860 | sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); | |
2861 | ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); | |
2862 | INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); | |
2863 | ||
2864 | sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); | |
2865 | ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); | |
2866 | INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); | |
2867 | INIT_WORK(&ha->idc_state_handler, | |
2868 | qla83xx_idc_state_handler_work); | |
2869 | INIT_WORK(&ha->nic_core_unrecoverable, | |
2870 | qla83xx_nic_core_unrecoverable_work); | |
2871 | } | |
2872 | ||
cbc8eb67 | 2873 | skip_dpc: |
e315cd28 AC |
2874 | list_add_tail(&base_vha->list, &ha->vp_list); |
2875 | base_vha->host->irq = ha->pdev->irq; | |
1da177e4 LT |
2876 | |
2877 | /* Initialized the timer */ | |
e315cd28 | 2878 | qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL); |
7c3df132 SK |
2879 | ql_dbg(ql_dbg_init, base_vha, 0x00ef, |
2880 | "Started qla2x00_timer with " | |
2881 | "interval=%d.\n", WATCH_INTERVAL); | |
2882 | ql_dbg(ql_dbg_init, base_vha, 0x00f0, | |
2883 | "Detected hba at address=%p.\n", | |
2884 | ha); | |
d19044c3 | 2885 | |
e02587d7 | 2886 | if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { |
bad75002 | 2887 | if (ha->fw_attributes & BIT_4) { |
9e522cd8 | 2888 | int prot = 0, guard; |
bad75002 | 2889 | base_vha->flags.difdix_supported = 1; |
7c3df132 SK |
2890 | ql_dbg(ql_dbg_init, base_vha, 0x00f1, |
2891 | "Registering for DIF/DIX type 1 and 3 protection.\n"); | |
8cb2049c AE |
2892 | if (ql2xenabledif == 1) |
2893 | prot = SHOST_DIX_TYPE0_PROTECTION; | |
bad75002 | 2894 | scsi_host_set_prot(host, |
8cb2049c | 2895 | prot | SHOST_DIF_TYPE1_PROTECTION |
0c470874 | 2896 | | SHOST_DIF_TYPE2_PROTECTION |
bad75002 AE |
2897 | | SHOST_DIF_TYPE3_PROTECTION |
2898 | | SHOST_DIX_TYPE1_PROTECTION | |
0c470874 | 2899 | | SHOST_DIX_TYPE2_PROTECTION |
bad75002 | 2900 | | SHOST_DIX_TYPE3_PROTECTION); |
9e522cd8 AE |
2901 | |
2902 | guard = SHOST_DIX_GUARD_CRC; | |
2903 | ||
2904 | if (IS_PI_IPGUARD_CAPABLE(ha) && | |
2905 | (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) | |
2906 | guard |= SHOST_DIX_GUARD_IP; | |
2907 | ||
2908 | scsi_host_set_guard(host, guard); | |
bad75002 AE |
2909 | } else |
2910 | base_vha->flags.difdix_supported = 0; | |
2911 | } | |
2912 | ||
a9083016 GM |
2913 | ha->isp_ops->enable_intrs(ha); |
2914 | ||
1fe19ee4 AB |
2915 | if (IS_QLAFX00(ha)) { |
2916 | ret = qlafx00_fx_disc(base_vha, | |
2917 | &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); | |
2918 | host->sg_tablesize = (ha->mr.extended_io_enabled) ? | |
2919 | QLA_SG_ALL : 128; | |
2920 | } | |
2921 | ||
a1541d5a AV |
2922 | ret = scsi_add_host(host, &pdev->dev); |
2923 | if (ret) | |
2924 | goto probe_failed; | |
2925 | ||
1486400f MR |
2926 | base_vha->flags.init_done = 1; |
2927 | base_vha->flags.online = 1; | |
edaa5c74 | 2928 | ha->prev_minidump_failed = 0; |
1486400f | 2929 | |
7c3df132 SK |
2930 | ql_dbg(ql_dbg_init, base_vha, 0x00f2, |
2931 | "Init done and hba is online.\n"); | |
2932 | ||
2d70c103 NB |
2933 | if (qla_ini_mode_enabled(base_vha)) |
2934 | scsi_scan_host(host); | |
2935 | else | |
2936 | ql_dbg(ql_dbg_init, base_vha, 0x0122, | |
2937 | "skipping scsi_scan_host() for non-initiator port\n"); | |
1e99e33a | 2938 | |
e315cd28 | 2939 | qla2x00_alloc_sysfs_attr(base_vha); |
a1541d5a | 2940 | |
8ae6d9c7 | 2941 | if (IS_QLAFX00(ha)) { |
8ae6d9c7 GM |
2942 | ret = qlafx00_fx_disc(base_vha, |
2943 | &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); | |
2944 | ||
2945 | /* Register system information */ | |
2946 | ret = qlafx00_fx_disc(base_vha, | |
2947 | &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); | |
2948 | } | |
2949 | ||
e315cd28 | 2950 | qla2x00_init_host_attr(base_vha); |
a1541d5a | 2951 | |
e315cd28 | 2952 | qla2x00_dfs_setup(base_vha); |
df613b96 | 2953 | |
03eb912a AB |
2954 | ql_log(ql_log_info, base_vha, 0x00fb, |
2955 | "QLogic %s - %s.\n", ha->model_number, ha->model_desc); | |
7c3df132 SK |
2956 | ql_log(ql_log_info, base_vha, 0x00fc, |
2957 | "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", | |
2958 | pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info), | |
2959 | pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', | |
2960 | base_vha->host_no, | |
df57caba | 2961 | ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); |
1da177e4 | 2962 | |
2d70c103 NB |
2963 | qlt_add_target(ha, base_vha); |
2964 | ||
6b383979 | 2965 | clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); |
a29b3dd7 JC |
2966 | |
2967 | if (test_bit(UNLOADING, &base_vha->dpc_flags)) | |
2968 | return -ENODEV; | |
2969 | ||
1da177e4 LT |
2970 | return 0; |
2971 | ||
6e9f21f3 | 2972 | probe_init_failed: |
2afa19a9 | 2973 | qla2x00_free_req_que(ha, req); |
9a347ff4 CD |
2974 | ha->req_q_map[0] = NULL; |
2975 | clear_bit(0, ha->req_qid_map); | |
2afa19a9 | 2976 | qla2x00_free_rsp_que(ha, rsp); |
9a347ff4 CD |
2977 | ha->rsp_q_map[0] = NULL; |
2978 | clear_bit(0, ha->rsp_qid_map); | |
2afa19a9 | 2979 | ha->max_req_queues = ha->max_rsp_queues = 0; |
6e9f21f3 | 2980 | |
1da177e4 | 2981 | probe_failed: |
b9978769 AV |
2982 | if (base_vha->timer_active) |
2983 | qla2x00_stop_timer(base_vha); | |
2984 | base_vha->flags.online = 0; | |
2985 | if (ha->dpc_thread) { | |
2986 | struct task_struct *t = ha->dpc_thread; | |
2987 | ||
2988 | ha->dpc_thread = NULL; | |
2989 | kthread_stop(t); | |
2990 | } | |
2991 | ||
e315cd28 | 2992 | qla2x00_free_device(base_vha); |
1da177e4 | 2993 | |
e315cd28 | 2994 | scsi_host_put(base_vha->host); |
1da177e4 | 2995 | |
e315cd28 | 2996 | probe_hw_failed: |
1a2fbf18 JL |
2997 | qla2x00_clear_drv_active(ha); |
2998 | ||
0a63ad12 | 2999 | iospace_config_failed: |
7ec0effd | 3000 | if (IS_P3P_TYPE(ha)) { |
0a63ad12 | 3001 | if (!ha->nx_pcibase) |
f73cb695 | 3002 | iounmap((device_reg_t *)ha->nx_pcibase); |
a9083016 | 3003 | if (!ql2xdbwr) |
f73cb695 | 3004 | iounmap((device_reg_t *)ha->nxdb_wr_ptr); |
a9083016 GM |
3005 | } else { |
3006 | if (ha->iobase) | |
3007 | iounmap(ha->iobase); | |
8ae6d9c7 GM |
3008 | if (ha->cregbase) |
3009 | iounmap(ha->cregbase); | |
a9083016 | 3010 | } |
e315cd28 AC |
3011 | pci_release_selected_regions(ha->pdev, ha->bars); |
3012 | kfree(ha); | |
3013 | ha = NULL; | |
1da177e4 | 3014 | |
a1541d5a | 3015 | probe_out: |
e315cd28 | 3016 | pci_disable_device(pdev); |
a1541d5a | 3017 | return ret; |
1da177e4 | 3018 | } |
1da177e4 | 3019 | |
e30d1756 MI |
3020 | static void |
3021 | qla2x00_shutdown(struct pci_dev *pdev) | |
3022 | { | |
3023 | scsi_qla_host_t *vha; | |
3024 | struct qla_hw_data *ha; | |
3025 | ||
552f3f9a MI |
3026 | if (!atomic_read(&pdev->enable_cnt)) |
3027 | return; | |
3028 | ||
e30d1756 MI |
3029 | vha = pci_get_drvdata(pdev); |
3030 | ha = vha->hw; | |
3031 | ||
42479343 AB |
3032 | /* Notify ISPFX00 firmware */ |
3033 | if (IS_QLAFX00(ha)) | |
3034 | qlafx00_driver_shutdown(vha, 20); | |
3035 | ||
e30d1756 MI |
3036 | /* Turn-off FCE trace */ |
3037 | if (ha->flags.fce_enabled) { | |
3038 | qla2x00_disable_fce_trace(vha, NULL, NULL); | |
3039 | ha->flags.fce_enabled = 0; | |
3040 | } | |
3041 | ||
3042 | /* Turn-off EFT trace */ | |
3043 | if (ha->eft) | |
3044 | qla2x00_disable_eft_trace(vha); | |
3045 | ||
3046 | /* Stop currently executing firmware. */ | |
3047 | qla2x00_try_to_stop_firmware(vha); | |
3048 | ||
3049 | /* Turn adapter off line */ | |
3050 | vha->flags.online = 0; | |
3051 | ||
3052 | /* turn-off interrupts on the card */ | |
3053 | if (ha->interrupts_on) { | |
3054 | vha->flags.init_done = 0; | |
3055 | ha->isp_ops->disable_intrs(ha); | |
3056 | } | |
3057 | ||
3058 | qla2x00_free_irqs(vha); | |
3059 | ||
3060 | qla2x00_free_fw_dump(ha); | |
61d41f61 CD |
3061 | |
3062 | pci_disable_pcie_error_reporting(pdev); | |
3063 | pci_disable_device(pdev); | |
e30d1756 MI |
3064 | } |
3065 | ||
fe1b806f | 3066 | /* Deletes all the virtual ports for a given ha */ |
4c993f76 | 3067 | static void |
fe1b806f | 3068 | qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) |
1da177e4 | 3069 | { |
fe1b806f | 3070 | scsi_qla_host_t *vha; |
feafb7b1 | 3071 | unsigned long flags; |
e315cd28 | 3072 | |
43ebf16d AE |
3073 | mutex_lock(&ha->vport_lock); |
3074 | while (ha->cur_vport_count) { | |
43ebf16d | 3075 | spin_lock_irqsave(&ha->vport_slock, flags); |
feafb7b1 | 3076 | |
43ebf16d AE |
3077 | BUG_ON(base_vha->list.next == &ha->vp_list); |
3078 | /* This assumes first entry in ha->vp_list is always base vha */ | |
3079 | vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); | |
52c82823 | 3080 | scsi_host_get(vha->host); |
feafb7b1 | 3081 | |
43ebf16d AE |
3082 | spin_unlock_irqrestore(&ha->vport_slock, flags); |
3083 | mutex_unlock(&ha->vport_lock); | |
3084 | ||
3085 | fc_vport_terminate(vha->fc_vport); | |
3086 | scsi_host_put(vha->host); | |
feafb7b1 | 3087 | |
43ebf16d | 3088 | mutex_lock(&ha->vport_lock); |
e315cd28 | 3089 | } |
43ebf16d | 3090 | mutex_unlock(&ha->vport_lock); |
fe1b806f | 3091 | } |
1da177e4 | 3092 | |
fe1b806f CD |
3093 | /* Stops all deferred work threads */ |
3094 | static void | |
3095 | qla2x00_destroy_deferred_work(struct qla_hw_data *ha) | |
3096 | { | |
68ca949c AC |
3097 | /* Flush the work queue and remove it */ |
3098 | if (ha->wq) { | |
3099 | flush_workqueue(ha->wq); | |
3100 | destroy_workqueue(ha->wq); | |
3101 | ha->wq = NULL; | |
3102 | } | |
3103 | ||
7d613ac6 SV |
3104 | /* Cancel all work and destroy DPC workqueues */ |
3105 | if (ha->dpc_lp_wq) { | |
3106 | cancel_work_sync(&ha->idc_aen); | |
3107 | destroy_workqueue(ha->dpc_lp_wq); | |
3108 | ha->dpc_lp_wq = NULL; | |
3109 | } | |
3110 | ||
3111 | if (ha->dpc_hp_wq) { | |
3112 | cancel_work_sync(&ha->nic_core_reset); | |
3113 | cancel_work_sync(&ha->idc_state_handler); | |
3114 | cancel_work_sync(&ha->nic_core_unrecoverable); | |
3115 | destroy_workqueue(ha->dpc_hp_wq); | |
3116 | ha->dpc_hp_wq = NULL; | |
3117 | } | |
3118 | ||
b9978769 AV |
3119 | /* Kill the kernel thread for this host */ |
3120 | if (ha->dpc_thread) { | |
3121 | struct task_struct *t = ha->dpc_thread; | |
3122 | ||
3123 | /* | |
3124 | * qla2xxx_wake_dpc checks for ->dpc_thread | |
3125 | * so we need to zero it out. | |
3126 | */ | |
3127 | ha->dpc_thread = NULL; | |
3128 | kthread_stop(t); | |
3129 | } | |
fe1b806f | 3130 | } |
1da177e4 | 3131 | |
fe1b806f CD |
3132 | static void |
3133 | qla2x00_unmap_iobases(struct qla_hw_data *ha) | |
3134 | { | |
a9083016 | 3135 | if (IS_QLA82XX(ha)) { |
b963752f | 3136 | |
f73cb695 | 3137 | iounmap((device_reg_t *)ha->nx_pcibase); |
a9083016 | 3138 | if (!ql2xdbwr) |
f73cb695 | 3139 | iounmap((device_reg_t *)ha->nxdb_wr_ptr); |
a9083016 GM |
3140 | } else { |
3141 | if (ha->iobase) | |
3142 | iounmap(ha->iobase); | |
1da177e4 | 3143 | |
8ae6d9c7 GM |
3144 | if (ha->cregbase) |
3145 | iounmap(ha->cregbase); | |
3146 | ||
a9083016 GM |
3147 | if (ha->mqiobase) |
3148 | iounmap(ha->mqiobase); | |
6246b8a1 | 3149 | |
f73cb695 | 3150 | if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase) |
6246b8a1 | 3151 | iounmap(ha->msixbase); |
a9083016 | 3152 | } |
fe1b806f CD |
3153 | } |
3154 | ||
3155 | static void | |
db7157d4 | 3156 | qla2x00_clear_drv_active(struct qla_hw_data *ha) |
fe1b806f | 3157 | { |
fe1b806f CD |
3158 | if (IS_QLA8044(ha)) { |
3159 | qla8044_idc_lock(ha); | |
c41afc9a | 3160 | qla8044_clear_drv_active(ha); |
fe1b806f CD |
3161 | qla8044_idc_unlock(ha); |
3162 | } else if (IS_QLA82XX(ha)) { | |
3163 | qla82xx_idc_lock(ha); | |
3164 | qla82xx_clear_drv_active(ha); | |
3165 | qla82xx_idc_unlock(ha); | |
3166 | } | |
3167 | } | |
3168 | ||
3169 | static void | |
3170 | qla2x00_remove_one(struct pci_dev *pdev) | |
3171 | { | |
3172 | scsi_qla_host_t *base_vha; | |
3173 | struct qla_hw_data *ha; | |
3174 | ||
beb9e315 JL |
3175 | base_vha = pci_get_drvdata(pdev); |
3176 | ha = base_vha->hw; | |
3177 | ||
3178 | /* Indicate device removal to prevent future board_disable and wait | |
3179 | * until any pending board_disable has completed. */ | |
3180 | set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); | |
3181 | cancel_work_sync(&ha->board_disable); | |
3182 | ||
fe1b806f | 3183 | /* |
beb9e315 JL |
3184 | * If the PCI device is disabled then there was a PCI-disconnect and |
3185 | * qla2x00_disable_board_on_pci_error has taken care of most of the | |
3186 | * resources. | |
fe1b806f | 3187 | */ |
beb9e315 JL |
3188 | if (!atomic_read(&pdev->enable_cnt)) { |
3189 | scsi_host_put(base_vha->host); | |
3190 | kfree(ha); | |
3191 | pci_set_drvdata(pdev, NULL); | |
fe1b806f | 3192 | return; |
beb9e315 | 3193 | } |
fe1b806f | 3194 | |
638a1a01 SC |
3195 | qla2x00_wait_for_hba_ready(base_vha); |
3196 | ||
783e0dc4 SC |
3197 | /* if UNLOAD flag is already set, then continue unload, |
3198 | * where it was set first. | |
3199 | */ | |
3200 | if (test_bit(UNLOADING, &base_vha->dpc_flags)) | |
3201 | return; | |
3202 | ||
fe1b806f CD |
3203 | set_bit(UNLOADING, &base_vha->dpc_flags); |
3204 | ||
3205 | if (IS_QLAFX00(ha)) | |
3206 | qlafx00_driver_shutdown(base_vha, 20); | |
3207 | ||
3208 | qla2x00_delete_all_vps(ha, base_vha); | |
3209 | ||
3210 | if (IS_QLA8031(ha)) { | |
3211 | ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, | |
3212 | "Clearing fcoe driver presence.\n"); | |
3213 | if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) | |
3214 | ql_dbg(ql_dbg_p3p, base_vha, 0xb079, | |
3215 | "Error while clearing DRV-Presence.\n"); | |
3216 | } | |
3217 | ||
3218 | qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); | |
3219 | ||
3220 | qla2x00_dfs_remove(base_vha); | |
3221 | ||
3222 | qla84xx_put_chip(base_vha); | |
3223 | ||
2d5a4c34 HM |
3224 | /* Laser should be disabled only for ISP2031 */ |
3225 | if (IS_QLA2031(ha)) | |
3226 | qla83xx_disable_laser(base_vha); | |
3227 | ||
fe1b806f CD |
3228 | /* Disable timer */ |
3229 | if (base_vha->timer_active) | |
3230 | qla2x00_stop_timer(base_vha); | |
3231 | ||
3232 | base_vha->flags.online = 0; | |
3233 | ||
b0d6cabd HM |
3234 | /* free DMA memory */ |
3235 | if (ha->exlogin_buf) | |
3236 | qla2x00_free_exlogin_buffer(ha); | |
3237 | ||
2f56a7f1 HM |
3238 | /* free DMA memory */ |
3239 | if (ha->exchoffld_buf) | |
3240 | qla2x00_free_exchoffld_buffer(ha); | |
3241 | ||
fe1b806f CD |
3242 | qla2x00_destroy_deferred_work(ha); |
3243 | ||
3244 | qlt_remove_target(ha, base_vha); | |
3245 | ||
3246 | qla2x00_free_sysfs_attr(base_vha, true); | |
3247 | ||
3248 | fc_remove_host(base_vha->host); | |
3249 | ||
3250 | scsi_remove_host(base_vha->host); | |
3251 | ||
3252 | qla2x00_free_device(base_vha); | |
3253 | ||
db7157d4 | 3254 | qla2x00_clear_drv_active(ha); |
fe1b806f | 3255 | |
d2749ffa AE |
3256 | scsi_host_put(base_vha->host); |
3257 | ||
fe1b806f | 3258 | qla2x00_unmap_iobases(ha); |
73208dfd | 3259 | |
e315cd28 AC |
3260 | pci_release_selected_regions(ha->pdev, ha->bars); |
3261 | kfree(ha); | |
3262 | ha = NULL; | |
1da177e4 | 3263 | |
90a86fc0 JC |
3264 | pci_disable_pcie_error_reporting(pdev); |
3265 | ||
665db93b | 3266 | pci_disable_device(pdev); |
1da177e4 | 3267 | } |
1da177e4 LT |
3268 | |
3269 | static void | |
e315cd28 | 3270 | qla2x00_free_device(scsi_qla_host_t *vha) |
1da177e4 | 3271 | { |
e315cd28 | 3272 | struct qla_hw_data *ha = vha->hw; |
1da177e4 | 3273 | |
85880801 AV |
3274 | qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); |
3275 | ||
3276 | /* Disable timer */ | |
3277 | if (vha->timer_active) | |
3278 | qla2x00_stop_timer(vha); | |
3279 | ||
2afa19a9 | 3280 | qla25xx_delete_queues(vha); |
fe1b806f | 3281 | |
df613b96 | 3282 | if (ha->flags.fce_enabled) |
e315cd28 | 3283 | qla2x00_disable_fce_trace(vha, NULL, NULL); |
df613b96 | 3284 | |
a7a167bf | 3285 | if (ha->eft) |
e315cd28 | 3286 | qla2x00_disable_eft_trace(vha); |
a7a167bf | 3287 | |
f6ef3b18 | 3288 | /* Stop currently executing firmware. */ |
e315cd28 | 3289 | qla2x00_try_to_stop_firmware(vha); |
1da177e4 | 3290 | |
85880801 AV |
3291 | vha->flags.online = 0; |
3292 | ||
f6ef3b18 | 3293 | /* turn-off interrupts on the card */ |
a9083016 GM |
3294 | if (ha->interrupts_on) { |
3295 | vha->flags.init_done = 0; | |
fd34f556 | 3296 | ha->isp_ops->disable_intrs(ha); |
a9083016 | 3297 | } |
f6ef3b18 | 3298 | |
e315cd28 | 3299 | qla2x00_free_irqs(vha); |
1da177e4 | 3300 | |
8867048b CD |
3301 | qla2x00_free_fcports(vha); |
3302 | ||
e315cd28 | 3303 | qla2x00_mem_free(ha); |
73208dfd | 3304 | |
08de2844 GM |
3305 | qla82xx_md_free(vha); |
3306 | ||
73208dfd | 3307 | qla2x00_free_queues(ha); |
1da177e4 LT |
3308 | } |
3309 | ||
8867048b CD |
3310 | void qla2x00_free_fcports(struct scsi_qla_host *vha) |
3311 | { | |
3312 | fc_port_t *fcport, *tfcport; | |
3313 | ||
3314 | list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) { | |
3315 | list_del(&fcport->list); | |
5f16b331 | 3316 | qla2x00_clear_loop_id(fcport); |
8867048b CD |
3317 | kfree(fcport); |
3318 | fcport = NULL; | |
3319 | } | |
3320 | } | |
3321 | ||
d97994dc | 3322 | static inline void |
e315cd28 | 3323 | qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport, |
d97994dc | 3324 | int defer) |
3325 | { | |
d97994dc | 3326 | struct fc_rport *rport; |
67becc00 | 3327 | scsi_qla_host_t *base_vha; |
044d78e1 | 3328 | unsigned long flags; |
d97994dc | 3329 | |
3330 | if (!fcport->rport) | |
3331 | return; | |
3332 | ||
3333 | rport = fcport->rport; | |
3334 | if (defer) { | |
67becc00 | 3335 | base_vha = pci_get_drvdata(vha->hw->pdev); |
044d78e1 | 3336 | spin_lock_irqsave(vha->host->host_lock, flags); |
d97994dc | 3337 | fcport->drport = rport; |
044d78e1 | 3338 | spin_unlock_irqrestore(vha->host->host_lock, flags); |
df673274 | 3339 | qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen); |
67becc00 AV |
3340 | set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); |
3341 | qla2xxx_wake_dpc(base_vha); | |
2d70c103 | 3342 | } else { |
df673274 | 3343 | int now; |
d20ed91b AP |
3344 | if (rport) |
3345 | fc_remote_port_delete(rport); | |
df673274 AP |
3346 | qlt_do_generation_tick(vha, &now); |
3347 | qlt_fc_port_deleted(vha, fcport, now); | |
2d70c103 | 3348 | } |
d97994dc | 3349 | } |
3350 | ||
1da177e4 LT |
3351 | /* |
3352 | * qla2x00_mark_device_lost Updates fcport state when device goes offline. | |
3353 | * | |
3354 | * Input: ha = adapter block pointer. fcport = port structure pointer. | |
3355 | * | |
3356 | * Return: None. | |
3357 | * | |
3358 | * Context: | |
3359 | */ | |
e315cd28 | 3360 | void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, |
d97994dc | 3361 | int do_login, int defer) |
1da177e4 | 3362 | { |
8ae6d9c7 GM |
3363 | if (IS_QLAFX00(vha->hw)) { |
3364 | qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); | |
3365 | qla2x00_schedule_rport_del(vha, fcport, defer); | |
3366 | return; | |
3367 | } | |
3368 | ||
2c3dfe3f | 3369 | if (atomic_read(&fcport->state) == FCS_ONLINE && |
c6d39e23 | 3370 | vha->vp_idx == fcport->vha->vp_idx) { |
ec426e10 | 3371 | qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); |
e315cd28 AC |
3372 | qla2x00_schedule_rport_del(vha, fcport, defer); |
3373 | } | |
fa2a1ce5 | 3374 | /* |
1da177e4 LT |
3375 | * We may need to retry the login, so don't change the state of the |
3376 | * port but do the retries. | |
3377 | */ | |
3378 | if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) | |
ec426e10 | 3379 | qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); |
1da177e4 LT |
3380 | |
3381 | if (!do_login) | |
3382 | return; | |
3383 | ||
a1d0285e AE |
3384 | set_bit(RELOGIN_NEEDED, &vha->dpc_flags); |
3385 | ||
1da177e4 | 3386 | if (fcport->login_retry == 0) { |
e315cd28 | 3387 | fcport->login_retry = vha->hw->login_retry_count; |
1da177e4 | 3388 | |
7c3df132 | 3389 | ql_dbg(ql_dbg_disc, vha, 0x2067, |
7b833558 OK |
3390 | "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n", |
3391 | fcport->port_name, fcport->loop_id, fcport->login_retry); | |
1da177e4 LT |
3392 | } |
3393 | } | |
3394 | ||
3395 | /* | |
3396 | * qla2x00_mark_all_devices_lost | |
3397 | * Updates fcport state when device goes offline. | |
3398 | * | |
3399 | * Input: | |
3400 | * ha = adapter block pointer. | |
3401 | * fcport = port structure pointer. | |
3402 | * | |
3403 | * Return: | |
3404 | * None. | |
3405 | * | |
3406 | * Context: | |
3407 | */ | |
3408 | void | |
e315cd28 | 3409 | qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer) |
1da177e4 LT |
3410 | { |
3411 | fc_port_t *fcport; | |
3412 | ||
e315cd28 | 3413 | list_for_each_entry(fcport, &vha->vp_fcports, list) { |
c6d39e23 | 3414 | if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx) |
1da177e4 | 3415 | continue; |
0d6e61bc | 3416 | |
1da177e4 LT |
3417 | /* |
3418 | * No point in marking the device as lost, if the device is | |
3419 | * already DEAD. | |
3420 | */ | |
3421 | if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD) | |
3422 | continue; | |
e315cd28 | 3423 | if (atomic_read(&fcport->state) == FCS_ONLINE) { |
ec426e10 | 3424 | qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); |
0d6e61bc AV |
3425 | if (defer) |
3426 | qla2x00_schedule_rport_del(vha, fcport, defer); | |
c6d39e23 | 3427 | else if (vha->vp_idx == fcport->vha->vp_idx) |
0d6e61bc AV |
3428 | qla2x00_schedule_rport_del(vha, fcport, defer); |
3429 | } | |
1da177e4 LT |
3430 | } |
3431 | } | |
3432 | ||
3433 | /* | |
3434 | * qla2x00_mem_alloc | |
3435 | * Allocates adapter memory. | |
3436 | * | |
3437 | * Returns: | |
3438 | * 0 = success. | |
e8711085 | 3439 | * !0 = failure. |
1da177e4 | 3440 | */ |
e8711085 | 3441 | static int |
73208dfd AC |
3442 | qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, |
3443 | struct req_que **req, struct rsp_que **rsp) | |
1da177e4 LT |
3444 | { |
3445 | char name[16]; | |
1da177e4 | 3446 | |
e8711085 | 3447 | ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, |
e315cd28 | 3448 | &ha->init_cb_dma, GFP_KERNEL); |
e8711085 | 3449 | if (!ha->init_cb) |
e315cd28 | 3450 | goto fail; |
e8711085 | 3451 | |
2d70c103 NB |
3452 | if (qlt_mem_alloc(ha) < 0) |
3453 | goto fail_free_init_cb; | |
3454 | ||
642ef983 CD |
3455 | ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, |
3456 | qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); | |
e315cd28 | 3457 | if (!ha->gid_list) |
2d70c103 | 3458 | goto fail_free_tgt_mem; |
1da177e4 | 3459 | |
e8711085 AV |
3460 | ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); |
3461 | if (!ha->srb_mempool) | |
e315cd28 | 3462 | goto fail_free_gid_list; |
e8711085 | 3463 | |
7ec0effd | 3464 | if (IS_P3P_TYPE(ha)) { |
a9083016 GM |
3465 | /* Allocate cache for CT6 Ctx. */ |
3466 | if (!ctx_cachep) { | |
3467 | ctx_cachep = kmem_cache_create("qla2xxx_ctx", | |
3468 | sizeof(struct ct6_dsd), 0, | |
3469 | SLAB_HWCACHE_ALIGN, NULL); | |
3470 | if (!ctx_cachep) | |
3471 | goto fail_free_gid_list; | |
3472 | } | |
3473 | ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, | |
3474 | ctx_cachep); | |
3475 | if (!ha->ctx_mempool) | |
3476 | goto fail_free_srb_mempool; | |
7c3df132 SK |
3477 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, |
3478 | "ctx_cachep=%p ctx_mempool=%p.\n", | |
3479 | ctx_cachep, ha->ctx_mempool); | |
a9083016 GM |
3480 | } |
3481 | ||
e8711085 AV |
3482 | /* Get memory for cached NVRAM */ |
3483 | ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); | |
3484 | if (!ha->nvram) | |
a9083016 | 3485 | goto fail_free_ctx_mempool; |
e8711085 | 3486 | |
e315cd28 AC |
3487 | snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, |
3488 | ha->pdev->device); | |
3489 | ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, | |
3490 | DMA_POOL_SIZE, 8, 0); | |
3491 | if (!ha->s_dma_pool) | |
3492 | goto fail_free_nvram; | |
3493 | ||
7c3df132 SK |
3494 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, |
3495 | "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", | |
3496 | ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); | |
3497 | ||
7ec0effd | 3498 | if (IS_P3P_TYPE(ha) || ql2xenabledif) { |
a9083016 GM |
3499 | ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, |
3500 | DSD_LIST_DMA_POOL_SIZE, 8, 0); | |
3501 | if (!ha->dl_dma_pool) { | |
7c3df132 SK |
3502 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, |
3503 | "Failed to allocate memory for dl_dma_pool.\n"); | |
a9083016 GM |
3504 | goto fail_s_dma_pool; |
3505 | } | |
3506 | ||
3507 | ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, | |
3508 | FCP_CMND_DMA_POOL_SIZE, 8, 0); | |
3509 | if (!ha->fcp_cmnd_dma_pool) { | |
7c3df132 SK |
3510 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, |
3511 | "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); | |
a9083016 GM |
3512 | goto fail_dl_dma_pool; |
3513 | } | |
7c3df132 SK |
3514 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, |
3515 | "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n", | |
3516 | ha->dl_dma_pool, ha->fcp_cmnd_dma_pool); | |
a9083016 GM |
3517 | } |
3518 | ||
e8711085 AV |
3519 | /* Allocate memory for SNS commands */ |
3520 | if (IS_QLA2100(ha) || IS_QLA2200(ha)) { | |
e315cd28 | 3521 | /* Get consistent memory allocated for SNS commands */ |
e8711085 | 3522 | ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, |
e315cd28 | 3523 | sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); |
e8711085 | 3524 | if (!ha->sns_cmd) |
e315cd28 | 3525 | goto fail_dma_pool; |
7c3df132 | 3526 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, |
d8424f68 | 3527 | "sns_cmd: %p.\n", ha->sns_cmd); |
e8711085 | 3528 | } else { |
e315cd28 | 3529 | /* Get consistent memory allocated for MS IOCB */ |
e8711085 | 3530 | ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, |
e315cd28 | 3531 | &ha->ms_iocb_dma); |
e8711085 | 3532 | if (!ha->ms_iocb) |
e315cd28 AC |
3533 | goto fail_dma_pool; |
3534 | /* Get consistent memory allocated for CT SNS commands */ | |
e8711085 | 3535 | ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, |
e315cd28 | 3536 | sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); |
e8711085 AV |
3537 | if (!ha->ct_sns) |
3538 | goto fail_free_ms_iocb; | |
7c3df132 SK |
3539 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, |
3540 | "ms_iocb=%p ct_sns=%p.\n", | |
3541 | ha->ms_iocb, ha->ct_sns); | |
1da177e4 LT |
3542 | } |
3543 | ||
e315cd28 | 3544 | /* Allocate memory for request ring */ |
73208dfd AC |
3545 | *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); |
3546 | if (!*req) { | |
7c3df132 SK |
3547 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, |
3548 | "Failed to allocate memory for req.\n"); | |
e315cd28 AC |
3549 | goto fail_req; |
3550 | } | |
73208dfd AC |
3551 | (*req)->length = req_len; |
3552 | (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, | |
3553 | ((*req)->length + 1) * sizeof(request_t), | |
3554 | &(*req)->dma, GFP_KERNEL); | |
3555 | if (!(*req)->ring) { | |
7c3df132 SK |
3556 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, |
3557 | "Failed to allocate memory for req_ring.\n"); | |
e315cd28 AC |
3558 | goto fail_req_ring; |
3559 | } | |
3560 | /* Allocate memory for response ring */ | |
73208dfd AC |
3561 | *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); |
3562 | if (!*rsp) { | |
7c3df132 SK |
3563 | ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, |
3564 | "Failed to allocate memory for rsp.\n"); | |
e315cd28 AC |
3565 | goto fail_rsp; |
3566 | } | |
73208dfd AC |
3567 | (*rsp)->hw = ha; |
3568 | (*rsp)->length = rsp_len; | |
3569 | (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, | |
3570 | ((*rsp)->length + 1) * sizeof(response_t), | |
3571 | &(*rsp)->dma, GFP_KERNEL); | |
3572 | if (!(*rsp)->ring) { | |
7c3df132 SK |
3573 | ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, |
3574 | "Failed to allocate memory for rsp_ring.\n"); | |
e315cd28 AC |
3575 | goto fail_rsp_ring; |
3576 | } | |
73208dfd AC |
3577 | (*req)->rsp = *rsp; |
3578 | (*rsp)->req = *req; | |
7c3df132 SK |
3579 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, |
3580 | "req=%p req->length=%d req->ring=%p rsp=%p " | |
3581 | "rsp->length=%d rsp->ring=%p.\n", | |
3582 | *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, | |
3583 | (*rsp)->ring); | |
73208dfd AC |
3584 | /* Allocate memory for NVRAM data for vports */ |
3585 | if (ha->nvram_npiv_size) { | |
3586 | ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) * | |
7c3df132 | 3587 | ha->nvram_npiv_size, GFP_KERNEL); |
73208dfd | 3588 | if (!ha->npiv_info) { |
7c3df132 SK |
3589 | ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, |
3590 | "Failed to allocate memory for npiv_info.\n"); | |
73208dfd AC |
3591 | goto fail_npiv_info; |
3592 | } | |
3593 | } else | |
3594 | ha->npiv_info = NULL; | |
e8711085 | 3595 | |
b64b0e8f | 3596 | /* Get consistent memory allocated for EX-INIT-CB. */ |
f73cb695 | 3597 | if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { |
b64b0e8f AV |
3598 | ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, |
3599 | &ha->ex_init_cb_dma); | |
3600 | if (!ha->ex_init_cb) | |
3601 | goto fail_ex_init_cb; | |
7c3df132 SK |
3602 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, |
3603 | "ex_init_cb=%p.\n", ha->ex_init_cb); | |
b64b0e8f AV |
3604 | } |
3605 | ||
a9083016 GM |
3606 | INIT_LIST_HEAD(&ha->gbl_dsd_list); |
3607 | ||
5ff1d584 AV |
3608 | /* Get consistent memory allocated for Async Port-Database. */ |
3609 | if (!IS_FWI2_CAPABLE(ha)) { | |
3610 | ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, | |
3611 | &ha->async_pd_dma); | |
3612 | if (!ha->async_pd) | |
3613 | goto fail_async_pd; | |
7c3df132 SK |
3614 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, |
3615 | "async_pd=%p.\n", ha->async_pd); | |
5ff1d584 AV |
3616 | } |
3617 | ||
e315cd28 | 3618 | INIT_LIST_HEAD(&ha->vp_list); |
5f16b331 CD |
3619 | |
3620 | /* Allocate memory for our loop_id bitmap */ | |
3621 | ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long), | |
3622 | GFP_KERNEL); | |
3623 | if (!ha->loop_id_map) | |
3624 | goto fail_async_pd; | |
3625 | else { | |
3626 | qla2x00_set_reserved_loop_ids(ha); | |
3627 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, | |
b2a72ec3 | 3628 | "loop_id_map=%p.\n", ha->loop_id_map); |
5f16b331 CD |
3629 | } |
3630 | ||
b2a72ec3 | 3631 | return 0; |
e315cd28 | 3632 | |
5ff1d584 AV |
3633 | fail_async_pd: |
3634 | dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); | |
b64b0e8f AV |
3635 | fail_ex_init_cb: |
3636 | kfree(ha->npiv_info); | |
73208dfd AC |
3637 | fail_npiv_info: |
3638 | dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * | |
3639 | sizeof(response_t), (*rsp)->ring, (*rsp)->dma); | |
3640 | (*rsp)->ring = NULL; | |
3641 | (*rsp)->dma = 0; | |
e315cd28 | 3642 | fail_rsp_ring: |
73208dfd | 3643 | kfree(*rsp); |
e315cd28 | 3644 | fail_rsp: |
73208dfd AC |
3645 | dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * |
3646 | sizeof(request_t), (*req)->ring, (*req)->dma); | |
3647 | (*req)->ring = NULL; | |
3648 | (*req)->dma = 0; | |
e315cd28 | 3649 | fail_req_ring: |
73208dfd | 3650 | kfree(*req); |
e315cd28 AC |
3651 | fail_req: |
3652 | dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), | |
3653 | ha->ct_sns, ha->ct_sns_dma); | |
3654 | ha->ct_sns = NULL; | |
3655 | ha->ct_sns_dma = 0; | |
e8711085 AV |
3656 | fail_free_ms_iocb: |
3657 | dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); | |
3658 | ha->ms_iocb = NULL; | |
3659 | ha->ms_iocb_dma = 0; | |
e315cd28 | 3660 | fail_dma_pool: |
bad75002 | 3661 | if (IS_QLA82XX(ha) || ql2xenabledif) { |
a9083016 GM |
3662 | dma_pool_destroy(ha->fcp_cmnd_dma_pool); |
3663 | ha->fcp_cmnd_dma_pool = NULL; | |
3664 | } | |
3665 | fail_dl_dma_pool: | |
bad75002 | 3666 | if (IS_QLA82XX(ha) || ql2xenabledif) { |
a9083016 GM |
3667 | dma_pool_destroy(ha->dl_dma_pool); |
3668 | ha->dl_dma_pool = NULL; | |
3669 | } | |
3670 | fail_s_dma_pool: | |
e315cd28 AC |
3671 | dma_pool_destroy(ha->s_dma_pool); |
3672 | ha->s_dma_pool = NULL; | |
e8711085 AV |
3673 | fail_free_nvram: |
3674 | kfree(ha->nvram); | |
3675 | ha->nvram = NULL; | |
a9083016 GM |
3676 | fail_free_ctx_mempool: |
3677 | mempool_destroy(ha->ctx_mempool); | |
3678 | ha->ctx_mempool = NULL; | |
e8711085 AV |
3679 | fail_free_srb_mempool: |
3680 | mempool_destroy(ha->srb_mempool); | |
3681 | ha->srb_mempool = NULL; | |
e8711085 | 3682 | fail_free_gid_list: |
642ef983 CD |
3683 | dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), |
3684 | ha->gid_list, | |
e315cd28 | 3685 | ha->gid_list_dma); |
e8711085 AV |
3686 | ha->gid_list = NULL; |
3687 | ha->gid_list_dma = 0; | |
2d70c103 NB |
3688 | fail_free_tgt_mem: |
3689 | qlt_mem_free(ha); | |
e315cd28 AC |
3690 | fail_free_init_cb: |
3691 | dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, | |
3692 | ha->init_cb_dma); | |
3693 | ha->init_cb = NULL; | |
3694 | ha->init_cb_dma = 0; | |
e8711085 | 3695 | fail: |
7c3df132 SK |
3696 | ql_log(ql_log_fatal, NULL, 0x0030, |
3697 | "Memory allocation failure.\n"); | |
e8711085 | 3698 | return -ENOMEM; |
1da177e4 LT |
3699 | } |
3700 | ||
b0d6cabd HM |
3701 | int |
3702 | qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) | |
3703 | { | |
3704 | int rval; | |
3705 | uint16_t size, max_cnt, temp; | |
3706 | struct qla_hw_data *ha = vha->hw; | |
3707 | ||
3708 | /* Return if we don't need to alloacate any extended logins */ | |
3709 | if (!ql2xexlogins) | |
3710 | return QLA_SUCCESS; | |
3711 | ||
3712 | ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); | |
3713 | max_cnt = 0; | |
3714 | rval = qla_get_exlogin_status(vha, &size, &max_cnt); | |
3715 | if (rval != QLA_SUCCESS) { | |
3716 | ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, | |
3717 | "Failed to get exlogin status.\n"); | |
3718 | return rval; | |
3719 | } | |
3720 | ||
3721 | temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; | |
3722 | ha->exlogin_size = (size * temp); | |
3723 | ql_log(ql_log_info, vha, 0xd024, | |
3724 | "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", | |
3725 | max_cnt, size, temp); | |
3726 | ||
3727 | ql_log(ql_log_info, vha, 0xd025, "EXLOGIN: requested size=0x%x\n", | |
3728 | ha->exlogin_size); | |
3729 | ||
3730 | /* Get consistent memory for extended logins */ | |
3731 | ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, | |
3732 | ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); | |
3733 | if (!ha->exlogin_buf) { | |
3734 | ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, | |
3735 | "Failed to allocate memory for exlogin_buf_dma.\n"); | |
3736 | return -ENOMEM; | |
3737 | } | |
3738 | ||
3739 | /* Now configure the dma buffer */ | |
3740 | rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); | |
3741 | if (rval) { | |
3742 | ql_log(ql_log_fatal, vha, 0x00cf, | |
3743 | "Setup extended login buffer ****FAILED****.\n"); | |
3744 | qla2x00_free_exlogin_buffer(ha); | |
3745 | } | |
3746 | ||
3747 | return rval; | |
3748 | } | |
3749 | ||
3750 | /* | |
3751 | * qla2x00_free_exlogin_buffer | |
3752 | * | |
3753 | * Input: | |
3754 | * ha = adapter block pointer | |
3755 | */ | |
3756 | void | |
3757 | qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) | |
3758 | { | |
3759 | if (ha->exlogin_buf) { | |
3760 | dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, | |
3761 | ha->exlogin_buf, ha->exlogin_buf_dma); | |
3762 | ha->exlogin_buf = NULL; | |
3763 | ha->exlogin_size = 0; | |
3764 | } | |
3765 | } | |
3766 | ||
2f56a7f1 HM |
3767 | int |
3768 | qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) | |
3769 | { | |
3770 | int rval; | |
3771 | uint16_t size, max_cnt, temp; | |
3772 | struct qla_hw_data *ha = vha->hw; | |
3773 | ||
3774 | /* Return if we don't need to alloacate any extended logins */ | |
3775 | if (!ql2xexchoffld) | |
3776 | return QLA_SUCCESS; | |
3777 | ||
3778 | ql_log(ql_log_info, vha, 0xd014, | |
3779 | "Exchange offload count: %d.\n", ql2xexlogins); | |
3780 | ||
3781 | max_cnt = 0; | |
3782 | rval = qla_get_exchoffld_status(vha, &size, &max_cnt); | |
3783 | if (rval != QLA_SUCCESS) { | |
3784 | ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, | |
3785 | "Failed to get exlogin status.\n"); | |
3786 | return rval; | |
3787 | } | |
3788 | ||
3789 | temp = (ql2xexchoffld > max_cnt) ? max_cnt : ql2xexchoffld; | |
3790 | ha->exchoffld_size = (size * temp); | |
3791 | ql_log(ql_log_info, vha, 0xd016, | |
3792 | "Exchange offload: max_count=%d, buffers=0x%x, total=%d.\n", | |
3793 | max_cnt, size, temp); | |
3794 | ||
3795 | ql_log(ql_log_info, vha, 0xd017, | |
3796 | "Exchange Buffers requested size = 0x%x\n", ha->exchoffld_size); | |
3797 | ||
3798 | /* Get consistent memory for extended logins */ | |
3799 | ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, | |
3800 | ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); | |
3801 | if (!ha->exchoffld_buf) { | |
3802 | ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, | |
3803 | "Failed to allocate memory for exchoffld_buf_dma.\n"); | |
3804 | return -ENOMEM; | |
3805 | } | |
3806 | ||
3807 | /* Now configure the dma buffer */ | |
3808 | rval = qla_set_exchoffld_mem_cfg(vha, ha->exchoffld_buf_dma); | |
3809 | if (rval) { | |
3810 | ql_log(ql_log_fatal, vha, 0xd02e, | |
3811 | "Setup exchange offload buffer ****FAILED****.\n"); | |
3812 | qla2x00_free_exchoffld_buffer(ha); | |
3813 | } | |
3814 | ||
3815 | return rval; | |
3816 | } | |
3817 | ||
3818 | /* | |
3819 | * qla2x00_free_exchoffld_buffer | |
3820 | * | |
3821 | * Input: | |
3822 | * ha = adapter block pointer | |
3823 | */ | |
3824 | void | |
3825 | qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) | |
3826 | { | |
3827 | if (ha->exchoffld_buf) { | |
3828 | dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, | |
3829 | ha->exchoffld_buf, ha->exchoffld_buf_dma); | |
3830 | ha->exchoffld_buf = NULL; | |
3831 | ha->exchoffld_size = 0; | |
3832 | } | |
3833 | } | |
3834 | ||
1da177e4 | 3835 | /* |
e30d1756 MI |
3836 | * qla2x00_free_fw_dump |
3837 | * Frees fw dump stuff. | |
1da177e4 LT |
3838 | * |
3839 | * Input: | |
7ec0effd | 3840 | * ha = adapter block pointer |
1da177e4 | 3841 | */ |
a824ebb3 | 3842 | static void |
e30d1756 | 3843 | qla2x00_free_fw_dump(struct qla_hw_data *ha) |
1da177e4 | 3844 | { |
df613b96 | 3845 | if (ha->fce) |
f73cb695 CD |
3846 | dma_free_coherent(&ha->pdev->dev, |
3847 | FCE_SIZE, ha->fce, ha->fce_dma); | |
df613b96 | 3848 | |
f73cb695 CD |
3849 | if (ha->eft) |
3850 | dma_free_coherent(&ha->pdev->dev, | |
3851 | EFT_SIZE, ha->eft, ha->eft_dma); | |
3852 | ||
3853 | if (ha->fw_dump) | |
a7a167bf | 3854 | vfree(ha->fw_dump); |
f73cb695 CD |
3855 | if (ha->fw_dump_template) |
3856 | vfree(ha->fw_dump_template); | |
3857 | ||
e30d1756 MI |
3858 | ha->fce = NULL; |
3859 | ha->fce_dma = 0; | |
3860 | ha->eft = NULL; | |
3861 | ha->eft_dma = 0; | |
e30d1756 | 3862 | ha->fw_dumped = 0; |
61f098dd | 3863 | ha->fw_dump_cap_flags = 0; |
e30d1756 | 3864 | ha->fw_dump_reading = 0; |
f73cb695 CD |
3865 | ha->fw_dump = NULL; |
3866 | ha->fw_dump_len = 0; | |
3867 | ha->fw_dump_template = NULL; | |
3868 | ha->fw_dump_template_len = 0; | |
e30d1756 MI |
3869 | } |
3870 | ||
3871 | /* | |
3872 | * qla2x00_mem_free | |
3873 | * Frees all adapter allocated memory. | |
3874 | * | |
3875 | * Input: | |
3876 | * ha = adapter block pointer. | |
3877 | */ | |
3878 | static void | |
3879 | qla2x00_mem_free(struct qla_hw_data *ha) | |
3880 | { | |
3881 | qla2x00_free_fw_dump(ha); | |
3882 | ||
81178772 SK |
3883 | if (ha->mctp_dump) |
3884 | dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, | |
3885 | ha->mctp_dump_dma); | |
3886 | ||
e30d1756 MI |
3887 | if (ha->srb_mempool) |
3888 | mempool_destroy(ha->srb_mempool); | |
a7a167bf | 3889 | |
11bbc1d8 AV |
3890 | if (ha->dcbx_tlv) |
3891 | dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, | |
3892 | ha->dcbx_tlv, ha->dcbx_tlv_dma); | |
3893 | ||
ce0423f4 AV |
3894 | if (ha->xgmac_data) |
3895 | dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, | |
3896 | ha->xgmac_data, ha->xgmac_data_dma); | |
3897 | ||
1da177e4 LT |
3898 | if (ha->sns_cmd) |
3899 | dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), | |
e315cd28 | 3900 | ha->sns_cmd, ha->sns_cmd_dma); |
1da177e4 LT |
3901 | |
3902 | if (ha->ct_sns) | |
3903 | dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), | |
e315cd28 | 3904 | ha->ct_sns, ha->ct_sns_dma); |
1da177e4 | 3905 | |
88729e53 AV |
3906 | if (ha->sfp_data) |
3907 | dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma); | |
3908 | ||
1da177e4 LT |
3909 | if (ha->ms_iocb) |
3910 | dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); | |
3911 | ||
b64b0e8f | 3912 | if (ha->ex_init_cb) |
a9083016 GM |
3913 | dma_pool_free(ha->s_dma_pool, |
3914 | ha->ex_init_cb, ha->ex_init_cb_dma); | |
b64b0e8f | 3915 | |
5ff1d584 AV |
3916 | if (ha->async_pd) |
3917 | dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); | |
3918 | ||
1da177e4 LT |
3919 | if (ha->s_dma_pool) |
3920 | dma_pool_destroy(ha->s_dma_pool); | |
3921 | ||
1da177e4 | 3922 | if (ha->gid_list) |
642ef983 CD |
3923 | dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), |
3924 | ha->gid_list, ha->gid_list_dma); | |
1da177e4 | 3925 | |
a9083016 GM |
3926 | if (IS_QLA82XX(ha)) { |
3927 | if (!list_empty(&ha->gbl_dsd_list)) { | |
3928 | struct dsd_dma *dsd_ptr, *tdsd_ptr; | |
3929 | ||
3930 | /* clean up allocated prev pool */ | |
3931 | list_for_each_entry_safe(dsd_ptr, | |
3932 | tdsd_ptr, &ha->gbl_dsd_list, list) { | |
3933 | dma_pool_free(ha->dl_dma_pool, | |
3934 | dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); | |
3935 | list_del(&dsd_ptr->list); | |
3936 | kfree(dsd_ptr); | |
3937 | } | |
3938 | } | |
3939 | } | |
3940 | ||
3941 | if (ha->dl_dma_pool) | |
3942 | dma_pool_destroy(ha->dl_dma_pool); | |
3943 | ||
3944 | if (ha->fcp_cmnd_dma_pool) | |
3945 | dma_pool_destroy(ha->fcp_cmnd_dma_pool); | |
3946 | ||
3947 | if (ha->ctx_mempool) | |
3948 | mempool_destroy(ha->ctx_mempool); | |
3949 | ||
2d70c103 NB |
3950 | qlt_mem_free(ha); |
3951 | ||
e315cd28 AC |
3952 | if (ha->init_cb) |
3953 | dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, | |
a9083016 | 3954 | ha->init_cb, ha->init_cb_dma); |
e315cd28 AC |
3955 | vfree(ha->optrom_buffer); |
3956 | kfree(ha->nvram); | |
73208dfd | 3957 | kfree(ha->npiv_info); |
7a67735b | 3958 | kfree(ha->swl); |
5f16b331 | 3959 | kfree(ha->loop_id_map); |
1da177e4 | 3960 | |
e8711085 | 3961 | ha->srb_mempool = NULL; |
a9083016 | 3962 | ha->ctx_mempool = NULL; |
1da177e4 LT |
3963 | ha->sns_cmd = NULL; |
3964 | ha->sns_cmd_dma = 0; | |
3965 | ha->ct_sns = NULL; | |
3966 | ha->ct_sns_dma = 0; | |
3967 | ha->ms_iocb = NULL; | |
3968 | ha->ms_iocb_dma = 0; | |
1da177e4 LT |
3969 | ha->init_cb = NULL; |
3970 | ha->init_cb_dma = 0; | |
b64b0e8f AV |
3971 | ha->ex_init_cb = NULL; |
3972 | ha->ex_init_cb_dma = 0; | |
5ff1d584 AV |
3973 | ha->async_pd = NULL; |
3974 | ha->async_pd_dma = 0; | |
1da177e4 LT |
3975 | |
3976 | ha->s_dma_pool = NULL; | |
a9083016 GM |
3977 | ha->dl_dma_pool = NULL; |
3978 | ha->fcp_cmnd_dma_pool = NULL; | |
1da177e4 | 3979 | |
1da177e4 LT |
3980 | ha->gid_list = NULL; |
3981 | ha->gid_list_dma = 0; | |
2d70c103 NB |
3982 | |
3983 | ha->tgt.atio_ring = NULL; | |
3984 | ha->tgt.atio_dma = 0; | |
3985 | ha->tgt.tgt_vp_map = NULL; | |
e315cd28 | 3986 | } |
1da177e4 | 3987 | |
e315cd28 AC |
3988 | struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, |
3989 | struct qla_hw_data *ha) | |
3990 | { | |
3991 | struct Scsi_Host *host; | |
3992 | struct scsi_qla_host *vha = NULL; | |
854165f4 | 3993 | |
e315cd28 AC |
3994 | host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); |
3995 | if (host == NULL) { | |
7c3df132 SK |
3996 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, |
3997 | "Failed to allocate host from the scsi layer, aborting.\n"); | |
e315cd28 AC |
3998 | goto fail; |
3999 | } | |
4000 | ||
4001 | /* Clear our data area */ | |
4002 | vha = shost_priv(host); | |
4003 | memset(vha, 0, sizeof(scsi_qla_host_t)); | |
4004 | ||
4005 | vha->host = host; | |
4006 | vha->host_no = host->host_no; | |
4007 | vha->hw = ha; | |
4008 | ||
4009 | INIT_LIST_HEAD(&vha->vp_fcports); | |
4010 | INIT_LIST_HEAD(&vha->work_list); | |
4011 | INIT_LIST_HEAD(&vha->list); | |
8b2f5ff3 SN |
4012 | INIT_LIST_HEAD(&vha->qla_cmd_list); |
4013 | INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list); | |
71cdc079 | 4014 | INIT_LIST_HEAD(&vha->logo_list); |
b7bd104e | 4015 | INIT_LIST_HEAD(&vha->plogi_ack_list); |
e315cd28 | 4016 | |
f999f4c1 | 4017 | spin_lock_init(&vha->work_lock); |
8b2f5ff3 | 4018 | spin_lock_init(&vha->cmd_list_lock); |
f999f4c1 | 4019 | |
e315cd28 | 4020 | sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); |
7c3df132 SK |
4021 | ql_dbg(ql_dbg_init, vha, 0x0041, |
4022 | "Allocated the host=%p hw=%p vha=%p dev_name=%s", | |
4023 | vha->host, vha->hw, vha, | |
4024 | dev_name(&(ha->pdev->dev))); | |
4025 | ||
e315cd28 AC |
4026 | return vha; |
4027 | ||
4028 | fail: | |
4029 | return vha; | |
1da177e4 LT |
4030 | } |
4031 | ||
01ef66bb | 4032 | static struct qla_work_evt * |
f999f4c1 | 4033 | qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) |
0971de7f AV |
4034 | { |
4035 | struct qla_work_evt *e; | |
feafb7b1 AE |
4036 | uint8_t bail; |
4037 | ||
4038 | QLA_VHA_MARK_BUSY(vha, bail); | |
4039 | if (bail) | |
4040 | return NULL; | |
0971de7f | 4041 | |
f999f4c1 | 4042 | e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); |
feafb7b1 AE |
4043 | if (!e) { |
4044 | QLA_VHA_MARK_NOT_BUSY(vha); | |
0971de7f | 4045 | return NULL; |
feafb7b1 | 4046 | } |
0971de7f AV |
4047 | |
4048 | INIT_LIST_HEAD(&e->list); | |
4049 | e->type = type; | |
4050 | e->flags = QLA_EVT_FLAG_FREE; | |
4051 | return e; | |
4052 | } | |
4053 | ||
01ef66bb | 4054 | static int |
f999f4c1 | 4055 | qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) |
0971de7f | 4056 | { |
f999f4c1 | 4057 | unsigned long flags; |
0971de7f | 4058 | |
f999f4c1 | 4059 | spin_lock_irqsave(&vha->work_lock, flags); |
e315cd28 | 4060 | list_add_tail(&e->list, &vha->work_list); |
f999f4c1 | 4061 | spin_unlock_irqrestore(&vha->work_lock, flags); |
e315cd28 | 4062 | qla2xxx_wake_dpc(vha); |
f999f4c1 | 4063 | |
0971de7f AV |
4064 | return QLA_SUCCESS; |
4065 | } | |
4066 | ||
4067 | int | |
e315cd28 | 4068 | qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, |
0971de7f AV |
4069 | u32 data) |
4070 | { | |
4071 | struct qla_work_evt *e; | |
4072 | ||
f999f4c1 | 4073 | e = qla2x00_alloc_work(vha, QLA_EVT_AEN); |
0971de7f AV |
4074 | if (!e) |
4075 | return QLA_FUNCTION_FAILED; | |
4076 | ||
4077 | e->u.aen.code = code; | |
4078 | e->u.aen.data = data; | |
f999f4c1 | 4079 | return qla2x00_post_work(vha, e); |
0971de7f AV |
4080 | } |
4081 | ||
8a659571 AV |
4082 | int |
4083 | qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) | |
4084 | { | |
4085 | struct qla_work_evt *e; | |
4086 | ||
f999f4c1 | 4087 | e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); |
8a659571 AV |
4088 | if (!e) |
4089 | return QLA_FUNCTION_FAILED; | |
4090 | ||
4091 | memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); | |
f999f4c1 | 4092 | return qla2x00_post_work(vha, e); |
8a659571 AV |
4093 | } |
4094 | ||
ac280b67 AV |
4095 | #define qla2x00_post_async_work(name, type) \ |
4096 | int qla2x00_post_async_##name##_work( \ | |
4097 | struct scsi_qla_host *vha, \ | |
4098 | fc_port_t *fcport, uint16_t *data) \ | |
4099 | { \ | |
4100 | struct qla_work_evt *e; \ | |
4101 | \ | |
4102 | e = qla2x00_alloc_work(vha, type); \ | |
4103 | if (!e) \ | |
4104 | return QLA_FUNCTION_FAILED; \ | |
4105 | \ | |
4106 | e->u.logio.fcport = fcport; \ | |
4107 | if (data) { \ | |
4108 | e->u.logio.data[0] = data[0]; \ | |
4109 | e->u.logio.data[1] = data[1]; \ | |
4110 | } \ | |
4111 | return qla2x00_post_work(vha, e); \ | |
4112 | } | |
4113 | ||
4114 | qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); | |
4115 | qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE); | |
4116 | qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); | |
4117 | qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE); | |
5ff1d584 AV |
4118 | qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); |
4119 | qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE); | |
ac280b67 | 4120 | |
3420d36c AV |
4121 | int |
4122 | qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) | |
4123 | { | |
4124 | struct qla_work_evt *e; | |
4125 | ||
4126 | e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); | |
4127 | if (!e) | |
4128 | return QLA_FUNCTION_FAILED; | |
4129 | ||
4130 | e->u.uevent.code = code; | |
4131 | return qla2x00_post_work(vha, e); | |
4132 | } | |
4133 | ||
4134 | static void | |
4135 | qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) | |
4136 | { | |
4137 | char event_string[40]; | |
4138 | char *envp[] = { event_string, NULL }; | |
4139 | ||
4140 | switch (code) { | |
4141 | case QLA_UEVENT_CODE_FW_DUMP: | |
4142 | snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", | |
4143 | vha->host_no); | |
4144 | break; | |
4145 | default: | |
4146 | /* do nothing */ | |
4147 | break; | |
4148 | } | |
4149 | kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); | |
4150 | } | |
4151 | ||
8ae6d9c7 GM |
4152 | int |
4153 | qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, | |
4154 | uint32_t *data, int cnt) | |
4155 | { | |
4156 | struct qla_work_evt *e; | |
4157 | ||
4158 | e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); | |
4159 | if (!e) | |
4160 | return QLA_FUNCTION_FAILED; | |
4161 | ||
4162 | e->u.aenfx.evtcode = evtcode; | |
4163 | e->u.aenfx.count = cnt; | |
4164 | memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); | |
4165 | return qla2x00_post_work(vha, e); | |
4166 | } | |
4167 | ||
ac280b67 | 4168 | void |
e315cd28 | 4169 | qla2x00_do_work(struct scsi_qla_host *vha) |
0971de7f | 4170 | { |
f999f4c1 AV |
4171 | struct qla_work_evt *e, *tmp; |
4172 | unsigned long flags; | |
4173 | LIST_HEAD(work); | |
0971de7f | 4174 | |
f999f4c1 AV |
4175 | spin_lock_irqsave(&vha->work_lock, flags); |
4176 | list_splice_init(&vha->work_list, &work); | |
4177 | spin_unlock_irqrestore(&vha->work_lock, flags); | |
4178 | ||
4179 | list_for_each_entry_safe(e, tmp, &work, list) { | |
0971de7f | 4180 | list_del_init(&e->list); |
0971de7f AV |
4181 | |
4182 | switch (e->type) { | |
4183 | case QLA_EVT_AEN: | |
e315cd28 | 4184 | fc_host_post_event(vha->host, fc_get_event_number(), |
0971de7f AV |
4185 | e->u.aen.code, e->u.aen.data); |
4186 | break; | |
8a659571 AV |
4187 | case QLA_EVT_IDC_ACK: |
4188 | qla81xx_idc_ack(vha, e->u.idc_ack.mb); | |
4189 | break; | |
ac280b67 AV |
4190 | case QLA_EVT_ASYNC_LOGIN: |
4191 | qla2x00_async_login(vha, e->u.logio.fcport, | |
4192 | e->u.logio.data); | |
4193 | break; | |
4194 | case QLA_EVT_ASYNC_LOGIN_DONE: | |
4195 | qla2x00_async_login_done(vha, e->u.logio.fcport, | |
4196 | e->u.logio.data); | |
4197 | break; | |
4198 | case QLA_EVT_ASYNC_LOGOUT: | |
4199 | qla2x00_async_logout(vha, e->u.logio.fcport); | |
4200 | break; | |
4201 | case QLA_EVT_ASYNC_LOGOUT_DONE: | |
4202 | qla2x00_async_logout_done(vha, e->u.logio.fcport, | |
4203 | e->u.logio.data); | |
4204 | break; | |
5ff1d584 AV |
4205 | case QLA_EVT_ASYNC_ADISC: |
4206 | qla2x00_async_adisc(vha, e->u.logio.fcport, | |
4207 | e->u.logio.data); | |
4208 | break; | |
4209 | case QLA_EVT_ASYNC_ADISC_DONE: | |
4210 | qla2x00_async_adisc_done(vha, e->u.logio.fcport, | |
4211 | e->u.logio.data); | |
4212 | break; | |
3420d36c AV |
4213 | case QLA_EVT_UEVENT: |
4214 | qla2x00_uevent_emit(vha, e->u.uevent.code); | |
4215 | break; | |
8ae6d9c7 GM |
4216 | case QLA_EVT_AENFX: |
4217 | qlafx00_process_aen(vha, e); | |
4218 | break; | |
0971de7f AV |
4219 | } |
4220 | if (e->flags & QLA_EVT_FLAG_FREE) | |
4221 | kfree(e); | |
feafb7b1 AE |
4222 | |
4223 | /* For each work completed decrement vha ref count */ | |
4224 | QLA_VHA_MARK_NOT_BUSY(vha); | |
e315cd28 | 4225 | } |
e315cd28 | 4226 | } |
f999f4c1 | 4227 | |
e315cd28 AC |
4228 | /* Relogins all the fcports of a vport |
4229 | * Context: dpc thread | |
4230 | */ | |
4231 | void qla2x00_relogin(struct scsi_qla_host *vha) | |
4232 | { | |
4233 | fc_port_t *fcport; | |
c6b2fca8 | 4234 | int status; |
e315cd28 AC |
4235 | uint16_t next_loopid = 0; |
4236 | struct qla_hw_data *ha = vha->hw; | |
ac280b67 | 4237 | uint16_t data[2]; |
e315cd28 AC |
4238 | |
4239 | list_for_each_entry(fcport, &vha->vp_fcports, list) { | |
4240 | /* | |
4241 | * If the port is not ONLINE then try to login | |
4242 | * to it if we haven't run out of retries. | |
4243 | */ | |
5ff1d584 AV |
4244 | if (atomic_read(&fcport->state) != FCS_ONLINE && |
4245 | fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) { | |
ac280b67 | 4246 | fcport->login_retry--; |
e315cd28 | 4247 | if (fcport->flags & FCF_FABRIC_DEVICE) { |
f08b7251 | 4248 | if (fcport->flags & FCF_FCP2_DEVICE) |
e315cd28 AC |
4249 | ha->isp_ops->fabric_logout(vha, |
4250 | fcport->loop_id, | |
4251 | fcport->d_id.b.domain, | |
4252 | fcport->d_id.b.area, | |
4253 | fcport->d_id.b.al_pa); | |
4254 | ||
03bcfb57 JC |
4255 | if (fcport->loop_id == FC_NO_LOOP_ID) { |
4256 | fcport->loop_id = next_loopid = | |
4257 | ha->min_external_loopid; | |
4258 | status = qla2x00_find_new_loop_id( | |
4259 | vha, fcport); | |
4260 | if (status != QLA_SUCCESS) { | |
4261 | /* Ran out of IDs to use */ | |
4262 | break; | |
4263 | } | |
4264 | } | |
4265 | ||
ac280b67 | 4266 | if (IS_ALOGIO_CAPABLE(ha)) { |
5ff1d584 | 4267 | fcport->flags |= FCF_ASYNC_SENT; |
ac280b67 AV |
4268 | data[0] = 0; |
4269 | data[1] = QLA_LOGIO_LOGIN_RETRIED; | |
4270 | status = qla2x00_post_async_login_work( | |
4271 | vha, fcport, data); | |
4272 | if (status == QLA_SUCCESS) | |
4273 | continue; | |
4274 | /* Attempt a retry. */ | |
4275 | status = 1; | |
aaf4d3e2 | 4276 | } else { |
ac280b67 AV |
4277 | status = qla2x00_fabric_login(vha, |
4278 | fcport, &next_loopid); | |
aaf4d3e2 SK |
4279 | if (status == QLA_SUCCESS) { |
4280 | int status2; | |
4281 | uint8_t opts; | |
4282 | ||
4283 | opts = 0; | |
4284 | if (fcport->flags & | |
4285 | FCF_FCP2_DEVICE) | |
4286 | opts |= BIT_1; | |
03003960 SK |
4287 | status2 = |
4288 | qla2x00_get_port_database( | |
4289 | vha, fcport, opts); | |
aaf4d3e2 SK |
4290 | if (status2 != QLA_SUCCESS) |
4291 | status = 1; | |
4292 | } | |
4293 | } | |
e315cd28 AC |
4294 | } else |
4295 | status = qla2x00_local_device_login(vha, | |
4296 | fcport); | |
4297 | ||
e315cd28 AC |
4298 | if (status == QLA_SUCCESS) { |
4299 | fcport->old_loop_id = fcport->loop_id; | |
4300 | ||
7c3df132 SK |
4301 | ql_dbg(ql_dbg_disc, vha, 0x2003, |
4302 | "Port login OK: logged in ID 0x%x.\n", | |
4303 | fcport->loop_id); | |
e315cd28 AC |
4304 | |
4305 | qla2x00_update_fcport(vha, fcport); | |
4306 | ||
4307 | } else if (status == 1) { | |
4308 | set_bit(RELOGIN_NEEDED, &vha->dpc_flags); | |
4309 | /* retry the login again */ | |
7c3df132 SK |
4310 | ql_dbg(ql_dbg_disc, vha, 0x2007, |
4311 | "Retrying %d login again loop_id 0x%x.\n", | |
4312 | fcport->login_retry, fcport->loop_id); | |
e315cd28 AC |
4313 | } else { |
4314 | fcport->login_retry = 0; | |
4315 | } | |
4316 | ||
4317 | if (fcport->login_retry == 0 && status != QLA_SUCCESS) | |
5f16b331 | 4318 | qla2x00_clear_loop_id(fcport); |
e315cd28 AC |
4319 | } |
4320 | if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) | |
4321 | break; | |
0971de7f | 4322 | } |
0971de7f AV |
4323 | } |
4324 | ||
7d613ac6 SV |
4325 | /* Schedule work on any of the dpc-workqueues */ |
4326 | void | |
4327 | qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) | |
4328 | { | |
4329 | struct qla_hw_data *ha = base_vha->hw; | |
4330 | ||
4331 | switch (work_code) { | |
4332 | case MBA_IDC_AEN: /* 0x8200 */ | |
4333 | if (ha->dpc_lp_wq) | |
4334 | queue_work(ha->dpc_lp_wq, &ha->idc_aen); | |
4335 | break; | |
4336 | ||
4337 | case QLA83XX_NIC_CORE_RESET: /* 0x1 */ | |
4338 | if (!ha->flags.nic_core_reset_hdlr_active) { | |
4339 | if (ha->dpc_hp_wq) | |
4340 | queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); | |
4341 | } else | |
4342 | ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, | |
4343 | "NIC Core reset is already active. Skip " | |
4344 | "scheduling it again.\n"); | |
4345 | break; | |
4346 | case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ | |
4347 | if (ha->dpc_hp_wq) | |
4348 | queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); | |
4349 | break; | |
4350 | case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ | |
4351 | if (ha->dpc_hp_wq) | |
4352 | queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); | |
4353 | break; | |
4354 | default: | |
4355 | ql_log(ql_log_warn, base_vha, 0xb05f, | |
d939be3a | 4356 | "Unknown work-code=0x%x.\n", work_code); |
7d613ac6 SV |
4357 | } |
4358 | ||
4359 | return; | |
4360 | } | |
4361 | ||
4362 | /* Work: Perform NIC Core Unrecoverable state handling */ | |
4363 | void | |
4364 | qla83xx_nic_core_unrecoverable_work(struct work_struct *work) | |
4365 | { | |
4366 | struct qla_hw_data *ha = | |
2ad1b67c | 4367 | container_of(work, struct qla_hw_data, nic_core_unrecoverable); |
7d613ac6 SV |
4368 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); |
4369 | uint32_t dev_state = 0; | |
4370 | ||
4371 | qla83xx_idc_lock(base_vha, 0); | |
4372 | qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); | |
4373 | qla83xx_reset_ownership(base_vha); | |
4374 | if (ha->flags.nic_core_reset_owner) { | |
4375 | ha->flags.nic_core_reset_owner = 0; | |
4376 | qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, | |
4377 | QLA8XXX_DEV_FAILED); | |
4378 | ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); | |
4379 | qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); | |
4380 | } | |
4381 | qla83xx_idc_unlock(base_vha, 0); | |
4382 | } | |
4383 | ||
4384 | /* Work: Execute IDC state handler */ | |
4385 | void | |
4386 | qla83xx_idc_state_handler_work(struct work_struct *work) | |
4387 | { | |
4388 | struct qla_hw_data *ha = | |
2ad1b67c | 4389 | container_of(work, struct qla_hw_data, idc_state_handler); |
7d613ac6 SV |
4390 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); |
4391 | uint32_t dev_state = 0; | |
4392 | ||
4393 | qla83xx_idc_lock(base_vha, 0); | |
4394 | qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); | |
4395 | if (dev_state == QLA8XXX_DEV_FAILED || | |
4396 | dev_state == QLA8XXX_DEV_NEED_QUIESCENT) | |
4397 | qla83xx_idc_state_handler(base_vha); | |
4398 | qla83xx_idc_unlock(base_vha, 0); | |
4399 | } | |
4400 | ||
fa492630 | 4401 | static int |
7d613ac6 SV |
4402 | qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) |
4403 | { | |
4404 | int rval = QLA_SUCCESS; | |
4405 | unsigned long heart_beat_wait = jiffies + (1 * HZ); | |
4406 | uint32_t heart_beat_counter1, heart_beat_counter2; | |
4407 | ||
4408 | do { | |
4409 | if (time_after(jiffies, heart_beat_wait)) { | |
4410 | ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, | |
4411 | "Nic Core f/w is not alive.\n"); | |
4412 | rval = QLA_FUNCTION_FAILED; | |
4413 | break; | |
4414 | } | |
4415 | ||
4416 | qla83xx_idc_lock(base_vha, 0); | |
4417 | qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, | |
4418 | &heart_beat_counter1); | |
4419 | qla83xx_idc_unlock(base_vha, 0); | |
4420 | msleep(100); | |
4421 | qla83xx_idc_lock(base_vha, 0); | |
4422 | qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, | |
4423 | &heart_beat_counter2); | |
4424 | qla83xx_idc_unlock(base_vha, 0); | |
4425 | } while (heart_beat_counter1 == heart_beat_counter2); | |
4426 | ||
4427 | return rval; | |
4428 | } | |
4429 | ||
4430 | /* Work: Perform NIC Core Reset handling */ | |
4431 | void | |
4432 | qla83xx_nic_core_reset_work(struct work_struct *work) | |
4433 | { | |
4434 | struct qla_hw_data *ha = | |
4435 | container_of(work, struct qla_hw_data, nic_core_reset); | |
4436 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); | |
4437 | uint32_t dev_state = 0; | |
4438 | ||
81178772 SK |
4439 | if (IS_QLA2031(ha)) { |
4440 | if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) | |
4441 | ql_log(ql_log_warn, base_vha, 0xb081, | |
4442 | "Failed to dump mctp\n"); | |
4443 | return; | |
4444 | } | |
4445 | ||
7d613ac6 SV |
4446 | if (!ha->flags.nic_core_reset_hdlr_active) { |
4447 | if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { | |
4448 | qla83xx_idc_lock(base_vha, 0); | |
4449 | qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, | |
4450 | &dev_state); | |
4451 | qla83xx_idc_unlock(base_vha, 0); | |
4452 | if (dev_state != QLA8XXX_DEV_NEED_RESET) { | |
4453 | ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, | |
4454 | "Nic Core f/w is alive.\n"); | |
4455 | return; | |
4456 | } | |
4457 | } | |
4458 | ||
4459 | ha->flags.nic_core_reset_hdlr_active = 1; | |
4460 | if (qla83xx_nic_core_reset(base_vha)) { | |
4461 | /* NIC Core reset failed. */ | |
4462 | ql_dbg(ql_dbg_p3p, base_vha, 0xb061, | |
4463 | "NIC Core reset failed.\n"); | |
4464 | } | |
4465 | ha->flags.nic_core_reset_hdlr_active = 0; | |
4466 | } | |
4467 | } | |
4468 | ||
4469 | /* Work: Handle 8200 IDC aens */ | |
4470 | void | |
4471 | qla83xx_service_idc_aen(struct work_struct *work) | |
4472 | { | |
4473 | struct qla_hw_data *ha = | |
4474 | container_of(work, struct qla_hw_data, idc_aen); | |
4475 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); | |
4476 | uint32_t dev_state, idc_control; | |
4477 | ||
4478 | qla83xx_idc_lock(base_vha, 0); | |
4479 | qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); | |
4480 | qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); | |
4481 | qla83xx_idc_unlock(base_vha, 0); | |
4482 | if (dev_state == QLA8XXX_DEV_NEED_RESET) { | |
4483 | if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { | |
4484 | ql_dbg(ql_dbg_p3p, base_vha, 0xb062, | |
4485 | "Application requested NIC Core Reset.\n"); | |
4486 | qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); | |
4487 | } else if (qla83xx_check_nic_core_fw_alive(base_vha) == | |
4488 | QLA_SUCCESS) { | |
4489 | ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, | |
4490 | "Other protocol driver requested NIC Core Reset.\n"); | |
4491 | qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); | |
4492 | } | |
4493 | } else if (dev_state == QLA8XXX_DEV_FAILED || | |
4494 | dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { | |
4495 | qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); | |
4496 | } | |
4497 | } | |
4498 | ||
4499 | static void | |
4500 | qla83xx_wait_logic(void) | |
4501 | { | |
4502 | int i; | |
4503 | ||
4504 | /* Yield CPU */ | |
4505 | if (!in_interrupt()) { | |
4506 | /* | |
4507 | * Wait about 200ms before retrying again. | |
4508 | * This controls the number of retries for single | |
4509 | * lock operation. | |
4510 | */ | |
4511 | msleep(100); | |
4512 | schedule(); | |
4513 | } else { | |
4514 | for (i = 0; i < 20; i++) | |
4515 | cpu_relax(); /* This a nop instr on i386 */ | |
4516 | } | |
4517 | } | |
4518 | ||
fa492630 | 4519 | static int |
7d613ac6 SV |
4520 | qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) |
4521 | { | |
4522 | int rval; | |
4523 | uint32_t data; | |
4524 | uint32_t idc_lck_rcvry_stage_mask = 0x3; | |
4525 | uint32_t idc_lck_rcvry_owner_mask = 0x3c; | |
4526 | struct qla_hw_data *ha = base_vha->hw; | |
6c315553 SK |
4527 | ql_dbg(ql_dbg_p3p, base_vha, 0xb086, |
4528 | "Trying force recovery of the IDC lock.\n"); | |
7d613ac6 SV |
4529 | |
4530 | rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); | |
4531 | if (rval) | |
4532 | return rval; | |
4533 | ||
4534 | if ((data & idc_lck_rcvry_stage_mask) > 0) { | |
4535 | return QLA_SUCCESS; | |
4536 | } else { | |
4537 | data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); | |
4538 | rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, | |
4539 | data); | |
4540 | if (rval) | |
4541 | return rval; | |
4542 | ||
4543 | msleep(200); | |
4544 | ||
4545 | rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, | |
4546 | &data); | |
4547 | if (rval) | |
4548 | return rval; | |
4549 | ||
4550 | if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { | |
4551 | data &= (IDC_LOCK_RECOVERY_STAGE2 | | |
4552 | ~(idc_lck_rcvry_stage_mask)); | |
4553 | rval = qla83xx_wr_reg(base_vha, | |
4554 | QLA83XX_IDC_LOCK_RECOVERY, data); | |
4555 | if (rval) | |
4556 | return rval; | |
4557 | ||
4558 | /* Forcefully perform IDC UnLock */ | |
4559 | rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, | |
4560 | &data); | |
4561 | if (rval) | |
4562 | return rval; | |
4563 | /* Clear lock-id by setting 0xff */ | |
4564 | rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, | |
4565 | 0xff); | |
4566 | if (rval) | |
4567 | return rval; | |
4568 | /* Clear lock-recovery by setting 0x0 */ | |
4569 | rval = qla83xx_wr_reg(base_vha, | |
4570 | QLA83XX_IDC_LOCK_RECOVERY, 0x0); | |
4571 | if (rval) | |
4572 | return rval; | |
4573 | } else | |
4574 | return QLA_SUCCESS; | |
4575 | } | |
4576 | ||
4577 | return rval; | |
4578 | } | |
4579 | ||
fa492630 | 4580 | static int |
7d613ac6 SV |
4581 | qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) |
4582 | { | |
4583 | int rval = QLA_SUCCESS; | |
4584 | uint32_t o_drv_lockid, n_drv_lockid; | |
4585 | unsigned long lock_recovery_timeout; | |
4586 | ||
4587 | lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; | |
4588 | retry_lockid: | |
4589 | rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); | |
4590 | if (rval) | |
4591 | goto exit; | |
4592 | ||
4593 | /* MAX wait time before forcing IDC Lock recovery = 2 secs */ | |
4594 | if (time_after_eq(jiffies, lock_recovery_timeout)) { | |
4595 | if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) | |
4596 | return QLA_SUCCESS; | |
4597 | else | |
4598 | return QLA_FUNCTION_FAILED; | |
4599 | } | |
4600 | ||
4601 | rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); | |
4602 | if (rval) | |
4603 | goto exit; | |
4604 | ||
4605 | if (o_drv_lockid == n_drv_lockid) { | |
4606 | qla83xx_wait_logic(); | |
4607 | goto retry_lockid; | |
4608 | } else | |
4609 | return QLA_SUCCESS; | |
4610 | ||
4611 | exit: | |
4612 | return rval; | |
4613 | } | |
4614 | ||
4615 | void | |
4616 | qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) | |
4617 | { | |
4618 | uint16_t options = (requester_id << 15) | BIT_6; | |
4619 | uint32_t data; | |
6c315553 | 4620 | uint32_t lock_owner; |
7d613ac6 SV |
4621 | struct qla_hw_data *ha = base_vha->hw; |
4622 | ||
4623 | /* IDC-lock implementation using driver-lock/lock-id remote registers */ | |
4624 | retry_lock: | |
4625 | if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) | |
4626 | == QLA_SUCCESS) { | |
4627 | if (data) { | |
4628 | /* Setting lock-id to our function-number */ | |
4629 | qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, | |
4630 | ha->portnum); | |
4631 | } else { | |
6c315553 SK |
4632 | qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, |
4633 | &lock_owner); | |
7d613ac6 | 4634 | ql_dbg(ql_dbg_p3p, base_vha, 0xb063, |
6c315553 SK |
4635 | "Failed to acquire IDC lock, acquired by %d, " |
4636 | "retrying...\n", lock_owner); | |
7d613ac6 SV |
4637 | |
4638 | /* Retry/Perform IDC-Lock recovery */ | |
4639 | if (qla83xx_idc_lock_recovery(base_vha) | |
4640 | == QLA_SUCCESS) { | |
4641 | qla83xx_wait_logic(); | |
4642 | goto retry_lock; | |
4643 | } else | |
4644 | ql_log(ql_log_warn, base_vha, 0xb075, | |
4645 | "IDC Lock recovery FAILED.\n"); | |
4646 | } | |
4647 | ||
4648 | } | |
4649 | ||
4650 | return; | |
4651 | ||
4652 | /* XXX: IDC-lock implementation using access-control mbx */ | |
4653 | retry_lock2: | |
4654 | if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { | |
4655 | ql_dbg(ql_dbg_p3p, base_vha, 0xb072, | |
4656 | "Failed to acquire IDC lock. retrying...\n"); | |
4657 | /* Retry/Perform IDC-Lock recovery */ | |
4658 | if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) { | |
4659 | qla83xx_wait_logic(); | |
4660 | goto retry_lock2; | |
4661 | } else | |
4662 | ql_log(ql_log_warn, base_vha, 0xb076, | |
4663 | "IDC Lock recovery FAILED.\n"); | |
4664 | } | |
4665 | ||
4666 | return; | |
4667 | } | |
4668 | ||
4669 | void | |
4670 | qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) | |
4671 | { | |
5897cb2f BVA |
4672 | #if 0 |
4673 | uint16_t options = (requester_id << 15) | BIT_7; | |
4674 | #endif | |
4675 | uint16_t retry; | |
7d613ac6 SV |
4676 | uint32_t data; |
4677 | struct qla_hw_data *ha = base_vha->hw; | |
4678 | ||
4679 | /* IDC-unlock implementation using driver-unlock/lock-id | |
4680 | * remote registers | |
4681 | */ | |
4682 | retry = 0; | |
4683 | retry_unlock: | |
4684 | if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) | |
4685 | == QLA_SUCCESS) { | |
4686 | if (data == ha->portnum) { | |
4687 | qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); | |
4688 | /* Clearing lock-id by setting 0xff */ | |
4689 | qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); | |
4690 | } else if (retry < 10) { | |
4691 | /* SV: XXX: IDC unlock retrying needed here? */ | |
4692 | ||
4693 | /* Retry for IDC-unlock */ | |
4694 | qla83xx_wait_logic(); | |
4695 | retry++; | |
4696 | ql_dbg(ql_dbg_p3p, base_vha, 0xb064, | |
4697 | "Failed to release IDC lock, retyring=%d\n", retry); | |
4698 | goto retry_unlock; | |
4699 | } | |
4700 | } else if (retry < 10) { | |
4701 | /* Retry for IDC-unlock */ | |
4702 | qla83xx_wait_logic(); | |
4703 | retry++; | |
4704 | ql_dbg(ql_dbg_p3p, base_vha, 0xb065, | |
4705 | "Failed to read drv-lockid, retyring=%d\n", retry); | |
4706 | goto retry_unlock; | |
4707 | } | |
4708 | ||
4709 | return; | |
4710 | ||
5897cb2f | 4711 | #if 0 |
7d613ac6 SV |
4712 | /* XXX: IDC-unlock implementation using access-control mbx */ |
4713 | retry = 0; | |
4714 | retry_unlock2: | |
4715 | if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { | |
4716 | if (retry < 10) { | |
4717 | /* Retry for IDC-unlock */ | |
4718 | qla83xx_wait_logic(); | |
4719 | retry++; | |
4720 | ql_dbg(ql_dbg_p3p, base_vha, 0xb066, | |
4721 | "Failed to release IDC lock, retyring=%d\n", retry); | |
4722 | goto retry_unlock2; | |
4723 | } | |
4724 | } | |
4725 | ||
4726 | return; | |
5897cb2f | 4727 | #endif |
7d613ac6 SV |
4728 | } |
4729 | ||
4730 | int | |
4731 | __qla83xx_set_drv_presence(scsi_qla_host_t *vha) | |
4732 | { | |
4733 | int rval = QLA_SUCCESS; | |
4734 | struct qla_hw_data *ha = vha->hw; | |
4735 | uint32_t drv_presence; | |
4736 | ||
4737 | rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); | |
4738 | if (rval == QLA_SUCCESS) { | |
4739 | drv_presence |= (1 << ha->portnum); | |
4740 | rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, | |
4741 | drv_presence); | |
4742 | } | |
4743 | ||
4744 | return rval; | |
4745 | } | |
4746 | ||
4747 | int | |
4748 | qla83xx_set_drv_presence(scsi_qla_host_t *vha) | |
4749 | { | |
4750 | int rval = QLA_SUCCESS; | |
4751 | ||
4752 | qla83xx_idc_lock(vha, 0); | |
4753 | rval = __qla83xx_set_drv_presence(vha); | |
4754 | qla83xx_idc_unlock(vha, 0); | |
4755 | ||
4756 | return rval; | |
4757 | } | |
4758 | ||
4759 | int | |
4760 | __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) | |
4761 | { | |
4762 | int rval = QLA_SUCCESS; | |
4763 | struct qla_hw_data *ha = vha->hw; | |
4764 | uint32_t drv_presence; | |
4765 | ||
4766 | rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); | |
4767 | if (rval == QLA_SUCCESS) { | |
4768 | drv_presence &= ~(1 << ha->portnum); | |
4769 | rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, | |
4770 | drv_presence); | |
4771 | } | |
4772 | ||
4773 | return rval; | |
4774 | } | |
4775 | ||
4776 | int | |
4777 | qla83xx_clear_drv_presence(scsi_qla_host_t *vha) | |
4778 | { | |
4779 | int rval = QLA_SUCCESS; | |
4780 | ||
4781 | qla83xx_idc_lock(vha, 0); | |
4782 | rval = __qla83xx_clear_drv_presence(vha); | |
4783 | qla83xx_idc_unlock(vha, 0); | |
4784 | ||
4785 | return rval; | |
4786 | } | |
4787 | ||
fa492630 | 4788 | static void |
7d613ac6 SV |
4789 | qla83xx_need_reset_handler(scsi_qla_host_t *vha) |
4790 | { | |
4791 | struct qla_hw_data *ha = vha->hw; | |
4792 | uint32_t drv_ack, drv_presence; | |
4793 | unsigned long ack_timeout; | |
4794 | ||
4795 | /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ | |
4796 | ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); | |
4797 | while (1) { | |
4798 | qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); | |
4799 | qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); | |
807fb6d8 | 4800 | if ((drv_ack & drv_presence) == drv_presence) |
7d613ac6 SV |
4801 | break; |
4802 | ||
4803 | if (time_after_eq(jiffies, ack_timeout)) { | |
4804 | ql_log(ql_log_warn, vha, 0xb067, | |
4805 | "RESET ACK TIMEOUT! drv_presence=0x%x " | |
4806 | "drv_ack=0x%x\n", drv_presence, drv_ack); | |
4807 | /* | |
4808 | * The function(s) which did not ack in time are forced | |
4809 | * to withdraw any further participation in the IDC | |
4810 | * reset. | |
4811 | */ | |
4812 | if (drv_ack != drv_presence) | |
4813 | qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, | |
4814 | drv_ack); | |
4815 | break; | |
4816 | } | |
4817 | ||
4818 | qla83xx_idc_unlock(vha, 0); | |
4819 | msleep(1000); | |
4820 | qla83xx_idc_lock(vha, 0); | |
4821 | } | |
4822 | ||
4823 | qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); | |
4824 | ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); | |
4825 | } | |
4826 | ||
fa492630 | 4827 | static int |
7d613ac6 SV |
4828 | qla83xx_device_bootstrap(scsi_qla_host_t *vha) |
4829 | { | |
4830 | int rval = QLA_SUCCESS; | |
4831 | uint32_t idc_control; | |
4832 | ||
4833 | qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); | |
4834 | ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); | |
4835 | ||
4836 | /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ | |
4837 | __qla83xx_get_idc_control(vha, &idc_control); | |
4838 | idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; | |
4839 | __qla83xx_set_idc_control(vha, 0); | |
4840 | ||
4841 | qla83xx_idc_unlock(vha, 0); | |
4842 | rval = qla83xx_restart_nic_firmware(vha); | |
4843 | qla83xx_idc_lock(vha, 0); | |
4844 | ||
4845 | if (rval != QLA_SUCCESS) { | |
4846 | ql_log(ql_log_fatal, vha, 0xb06a, | |
4847 | "Failed to restart NIC f/w.\n"); | |
4848 | qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); | |
4849 | ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); | |
4850 | } else { | |
4851 | ql_dbg(ql_dbg_p3p, vha, 0xb06c, | |
4852 | "Success in restarting nic f/w.\n"); | |
4853 | qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); | |
4854 | ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); | |
4855 | } | |
4856 | ||
4857 | return rval; | |
4858 | } | |
4859 | ||
4860 | /* Assumes idc_lock always held on entry */ | |
4861 | int | |
4862 | qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) | |
4863 | { | |
4864 | struct qla_hw_data *ha = base_vha->hw; | |
4865 | int rval = QLA_SUCCESS; | |
4866 | unsigned long dev_init_timeout; | |
4867 | uint32_t dev_state; | |
4868 | ||
4869 | /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ | |
4870 | dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); | |
4871 | ||
4872 | while (1) { | |
4873 | ||
4874 | if (time_after_eq(jiffies, dev_init_timeout)) { | |
4875 | ql_log(ql_log_warn, base_vha, 0xb06e, | |
4876 | "Initialization TIMEOUT!\n"); | |
4877 | /* Init timeout. Disable further NIC Core | |
4878 | * communication. | |
4879 | */ | |
4880 | qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, | |
4881 | QLA8XXX_DEV_FAILED); | |
4882 | ql_log(ql_log_info, base_vha, 0xb06f, | |
4883 | "HW State: FAILED.\n"); | |
4884 | } | |
4885 | ||
4886 | qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); | |
4887 | switch (dev_state) { | |
4888 | case QLA8XXX_DEV_READY: | |
4889 | if (ha->flags.nic_core_reset_owner) | |
4890 | qla83xx_idc_audit(base_vha, | |
4891 | IDC_AUDIT_COMPLETION); | |
4892 | ha->flags.nic_core_reset_owner = 0; | |
4893 | ql_dbg(ql_dbg_p3p, base_vha, 0xb070, | |
4894 | "Reset_owner reset by 0x%x.\n", | |
4895 | ha->portnum); | |
4896 | goto exit; | |
4897 | case QLA8XXX_DEV_COLD: | |
4898 | if (ha->flags.nic_core_reset_owner) | |
4899 | rval = qla83xx_device_bootstrap(base_vha); | |
4900 | else { | |
4901 | /* Wait for AEN to change device-state */ | |
4902 | qla83xx_idc_unlock(base_vha, 0); | |
4903 | msleep(1000); | |
4904 | qla83xx_idc_lock(base_vha, 0); | |
4905 | } | |
4906 | break; | |
4907 | case QLA8XXX_DEV_INITIALIZING: | |
4908 | /* Wait for AEN to change device-state */ | |
4909 | qla83xx_idc_unlock(base_vha, 0); | |
4910 | msleep(1000); | |
4911 | qla83xx_idc_lock(base_vha, 0); | |
4912 | break; | |
4913 | case QLA8XXX_DEV_NEED_RESET: | |
4914 | if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) | |
4915 | qla83xx_need_reset_handler(base_vha); | |
4916 | else { | |
4917 | /* Wait for AEN to change device-state */ | |
4918 | qla83xx_idc_unlock(base_vha, 0); | |
4919 | msleep(1000); | |
4920 | qla83xx_idc_lock(base_vha, 0); | |
4921 | } | |
4922 | /* reset timeout value after need reset handler */ | |
4923 | dev_init_timeout = jiffies + | |
4924 | (ha->fcoe_dev_init_timeout * HZ); | |
4925 | break; | |
4926 | case QLA8XXX_DEV_NEED_QUIESCENT: | |
4927 | /* XXX: DEBUG for now */ | |
4928 | qla83xx_idc_unlock(base_vha, 0); | |
4929 | msleep(1000); | |
4930 | qla83xx_idc_lock(base_vha, 0); | |
4931 | break; | |
4932 | case QLA8XXX_DEV_QUIESCENT: | |
4933 | /* XXX: DEBUG for now */ | |
4934 | if (ha->flags.quiesce_owner) | |
4935 | goto exit; | |
4936 | ||
4937 | qla83xx_idc_unlock(base_vha, 0); | |
4938 | msleep(1000); | |
4939 | qla83xx_idc_lock(base_vha, 0); | |
4940 | dev_init_timeout = jiffies + | |
4941 | (ha->fcoe_dev_init_timeout * HZ); | |
4942 | break; | |
4943 | case QLA8XXX_DEV_FAILED: | |
4944 | if (ha->flags.nic_core_reset_owner) | |
4945 | qla83xx_idc_audit(base_vha, | |
4946 | IDC_AUDIT_COMPLETION); | |
4947 | ha->flags.nic_core_reset_owner = 0; | |
4948 | __qla83xx_clear_drv_presence(base_vha); | |
4949 | qla83xx_idc_unlock(base_vha, 0); | |
4950 | qla8xxx_dev_failed_handler(base_vha); | |
4951 | rval = QLA_FUNCTION_FAILED; | |
4952 | qla83xx_idc_lock(base_vha, 0); | |
4953 | goto exit; | |
4954 | case QLA8XXX_BAD_VALUE: | |
4955 | qla83xx_idc_unlock(base_vha, 0); | |
4956 | msleep(1000); | |
4957 | qla83xx_idc_lock(base_vha, 0); | |
4958 | break; | |
4959 | default: | |
4960 | ql_log(ql_log_warn, base_vha, 0xb071, | |
d939be3a | 4961 | "Unknown Device State: %x.\n", dev_state); |
7d613ac6 SV |
4962 | qla83xx_idc_unlock(base_vha, 0); |
4963 | qla8xxx_dev_failed_handler(base_vha); | |
4964 | rval = QLA_FUNCTION_FAILED; | |
4965 | qla83xx_idc_lock(base_vha, 0); | |
4966 | goto exit; | |
4967 | } | |
4968 | } | |
4969 | ||
4970 | exit: | |
4971 | return rval; | |
4972 | } | |
4973 | ||
f3ddac19 CD |
4974 | void |
4975 | qla2x00_disable_board_on_pci_error(struct work_struct *work) | |
4976 | { | |
4977 | struct qla_hw_data *ha = container_of(work, struct qla_hw_data, | |
4978 | board_disable); | |
4979 | struct pci_dev *pdev = ha->pdev; | |
4980 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); | |
4981 | ||
783e0dc4 SC |
4982 | /* if UNLOAD flag is already set, then continue unload, |
4983 | * where it was set first. | |
4984 | */ | |
4985 | if (test_bit(UNLOADING, &base_vha->dpc_flags)) | |
4986 | return; | |
4987 | ||
f3ddac19 CD |
4988 | ql_log(ql_log_warn, base_vha, 0x015b, |
4989 | "Disabling adapter.\n"); | |
4990 | ||
4991 | set_bit(UNLOADING, &base_vha->dpc_flags); | |
4992 | ||
4993 | qla2x00_delete_all_vps(ha, base_vha); | |
4994 | ||
4995 | qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); | |
4996 | ||
4997 | qla2x00_dfs_remove(base_vha); | |
4998 | ||
4999 | qla84xx_put_chip(base_vha); | |
5000 | ||
5001 | if (base_vha->timer_active) | |
5002 | qla2x00_stop_timer(base_vha); | |
5003 | ||
5004 | base_vha->flags.online = 0; | |
5005 | ||
5006 | qla2x00_destroy_deferred_work(ha); | |
5007 | ||
5008 | /* | |
5009 | * Do not try to stop beacon blink as it will issue a mailbox | |
5010 | * command. | |
5011 | */ | |
5012 | qla2x00_free_sysfs_attr(base_vha, false); | |
5013 | ||
5014 | fc_remove_host(base_vha->host); | |
5015 | ||
5016 | scsi_remove_host(base_vha->host); | |
5017 | ||
5018 | base_vha->flags.init_done = 0; | |
5019 | qla25xx_delete_queues(base_vha); | |
5020 | qla2x00_free_irqs(base_vha); | |
5021 | qla2x00_free_fcports(base_vha); | |
5022 | qla2x00_mem_free(ha); | |
5023 | qla82xx_md_free(base_vha); | |
5024 | qla2x00_free_queues(ha); | |
5025 | ||
f3ddac19 CD |
5026 | qla2x00_unmap_iobases(ha); |
5027 | ||
5028 | pci_release_selected_regions(ha->pdev, ha->bars); | |
f3ddac19 CD |
5029 | pci_disable_pcie_error_reporting(pdev); |
5030 | pci_disable_device(pdev); | |
f3ddac19 | 5031 | |
beb9e315 JL |
5032 | /* |
5033 | * Let qla2x00_remove_one cleanup qla_hw_data on device removal. | |
5034 | */ | |
f3ddac19 CD |
5035 | } |
5036 | ||
1da177e4 LT |
5037 | /************************************************************************** |
5038 | * qla2x00_do_dpc | |
5039 | * This kernel thread is a task that is schedule by the interrupt handler | |
5040 | * to perform the background processing for interrupts. | |
5041 | * | |
5042 | * Notes: | |
5043 | * This task always run in the context of a kernel thread. It | |
5044 | * is kick-off by the driver's detect code and starts up | |
5045 | * up one per adapter. It immediately goes to sleep and waits for | |
5046 | * some fibre event. When either the interrupt handler or | |
5047 | * the timer routine detects a event it will one of the task | |
5048 | * bits then wake us up. | |
5049 | **************************************************************************/ | |
5050 | static int | |
5051 | qla2x00_do_dpc(void *data) | |
5052 | { | |
e315cd28 AC |
5053 | scsi_qla_host_t *base_vha; |
5054 | struct qla_hw_data *ha; | |
1da177e4 | 5055 | |
e315cd28 AC |
5056 | ha = (struct qla_hw_data *)data; |
5057 | base_vha = pci_get_drvdata(ha->pdev); | |
1da177e4 | 5058 | |
8698a745 | 5059 | set_user_nice(current, MIN_NICE); |
1da177e4 | 5060 | |
563585ec | 5061 | set_current_state(TASK_INTERRUPTIBLE); |
39a11240 | 5062 | while (!kthread_should_stop()) { |
7c3df132 SK |
5063 | ql_dbg(ql_dbg_dpc, base_vha, 0x4000, |
5064 | "DPC handler sleeping.\n"); | |
1da177e4 | 5065 | |
39a11240 | 5066 | schedule(); |
1da177e4 | 5067 | |
c142caf0 AV |
5068 | if (!base_vha->flags.init_done || ha->flags.mbox_busy) |
5069 | goto end_loop; | |
1da177e4 | 5070 | |
85880801 | 5071 | if (ha->flags.eeh_busy) { |
7c3df132 SK |
5072 | ql_dbg(ql_dbg_dpc, base_vha, 0x4003, |
5073 | "eeh_busy=%d.\n", ha->flags.eeh_busy); | |
c142caf0 | 5074 | goto end_loop; |
85880801 AV |
5075 | } |
5076 | ||
1da177e4 LT |
5077 | ha->dpc_active = 1; |
5078 | ||
5f28d2d7 SK |
5079 | ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, |
5080 | "DPC handler waking up, dpc_flags=0x%lx.\n", | |
5081 | base_vha->dpc_flags); | |
1da177e4 | 5082 | |
a29b3dd7 JC |
5083 | if (test_bit(UNLOADING, &base_vha->dpc_flags)) |
5084 | break; | |
5085 | ||
e315cd28 | 5086 | qla2x00_do_work(base_vha); |
0971de7f | 5087 | |
7ec0effd AD |
5088 | if (IS_P3P_TYPE(ha)) { |
5089 | if (IS_QLA8044(ha)) { | |
5090 | if (test_and_clear_bit(ISP_UNRECOVERABLE, | |
5091 | &base_vha->dpc_flags)) { | |
5092 | qla8044_idc_lock(ha); | |
5093 | qla8044_wr_direct(base_vha, | |
5094 | QLA8044_CRB_DEV_STATE_INDEX, | |
5095 | QLA8XXX_DEV_FAILED); | |
5096 | qla8044_idc_unlock(ha); | |
5097 | ql_log(ql_log_info, base_vha, 0x4004, | |
5098 | "HW State: FAILED.\n"); | |
5099 | qla8044_device_state_handler(base_vha); | |
5100 | continue; | |
5101 | } | |
5102 | ||
5103 | } else { | |
5104 | if (test_and_clear_bit(ISP_UNRECOVERABLE, | |
5105 | &base_vha->dpc_flags)) { | |
5106 | qla82xx_idc_lock(ha); | |
5107 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | |
5108 | QLA8XXX_DEV_FAILED); | |
5109 | qla82xx_idc_unlock(ha); | |
5110 | ql_log(ql_log_info, base_vha, 0x0151, | |
5111 | "HW State: FAILED.\n"); | |
5112 | qla82xx_device_state_handler(base_vha); | |
5113 | continue; | |
5114 | } | |
a9083016 GM |
5115 | } |
5116 | ||
5117 | if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, | |
5118 | &base_vha->dpc_flags)) { | |
5119 | ||
7c3df132 SK |
5120 | ql_dbg(ql_dbg_dpc, base_vha, 0x4005, |
5121 | "FCoE context reset scheduled.\n"); | |
a9083016 GM |
5122 | if (!(test_and_set_bit(ABORT_ISP_ACTIVE, |
5123 | &base_vha->dpc_flags))) { | |
5124 | if (qla82xx_fcoe_ctx_reset(base_vha)) { | |
5125 | /* FCoE-ctx reset failed. | |
5126 | * Escalate to chip-reset | |
5127 | */ | |
5128 | set_bit(ISP_ABORT_NEEDED, | |
5129 | &base_vha->dpc_flags); | |
5130 | } | |
5131 | clear_bit(ABORT_ISP_ACTIVE, | |
5132 | &base_vha->dpc_flags); | |
5133 | } | |
5134 | ||
7c3df132 SK |
5135 | ql_dbg(ql_dbg_dpc, base_vha, 0x4006, |
5136 | "FCoE context reset end.\n"); | |
a9083016 | 5137 | } |
8ae6d9c7 GM |
5138 | } else if (IS_QLAFX00(ha)) { |
5139 | if (test_and_clear_bit(ISP_UNRECOVERABLE, | |
5140 | &base_vha->dpc_flags)) { | |
5141 | ql_dbg(ql_dbg_dpc, base_vha, 0x4020, | |
5142 | "Firmware Reset Recovery\n"); | |
5143 | if (qlafx00_reset_initialize(base_vha)) { | |
5144 | /* Failed. Abort isp later. */ | |
5145 | if (!test_bit(UNLOADING, | |
f92f82d6 | 5146 | &base_vha->dpc_flags)) { |
8ae6d9c7 GM |
5147 | set_bit(ISP_UNRECOVERABLE, |
5148 | &base_vha->dpc_flags); | |
5149 | ql_dbg(ql_dbg_dpc, base_vha, | |
5150 | 0x4021, | |
5151 | "Reset Recovery Failed\n"); | |
f92f82d6 | 5152 | } |
8ae6d9c7 GM |
5153 | } |
5154 | } | |
5155 | ||
5156 | if (test_and_clear_bit(FX00_TARGET_SCAN, | |
5157 | &base_vha->dpc_flags)) { | |
5158 | ql_dbg(ql_dbg_dpc, base_vha, 0x4022, | |
5159 | "ISPFx00 Target Scan scheduled\n"); | |
5160 | if (qlafx00_rescan_isp(base_vha)) { | |
5161 | if (!test_bit(UNLOADING, | |
5162 | &base_vha->dpc_flags)) | |
5163 | set_bit(ISP_UNRECOVERABLE, | |
5164 | &base_vha->dpc_flags); | |
5165 | ql_dbg(ql_dbg_dpc, base_vha, 0x401e, | |
5166 | "ISPFx00 Target Scan Failed\n"); | |
5167 | } | |
5168 | ql_dbg(ql_dbg_dpc, base_vha, 0x401f, | |
5169 | "ISPFx00 Target Scan End\n"); | |
5170 | } | |
e8f5e95d AB |
5171 | if (test_and_clear_bit(FX00_HOST_INFO_RESEND, |
5172 | &base_vha->dpc_flags)) { | |
5173 | ql_dbg(ql_dbg_dpc, base_vha, 0x4023, | |
5174 | "ISPFx00 Host Info resend scheduled\n"); | |
5175 | qlafx00_fx_disc(base_vha, | |
5176 | &base_vha->hw->mr.fcport, | |
5177 | FXDISC_REG_HOST_INFO); | |
5178 | } | |
a9083016 GM |
5179 | } |
5180 | ||
e315cd28 AC |
5181 | if (test_and_clear_bit(ISP_ABORT_NEEDED, |
5182 | &base_vha->dpc_flags)) { | |
1da177e4 | 5183 | |
7c3df132 SK |
5184 | ql_dbg(ql_dbg_dpc, base_vha, 0x4007, |
5185 | "ISP abort scheduled.\n"); | |
1da177e4 | 5186 | if (!(test_and_set_bit(ABORT_ISP_ACTIVE, |
e315cd28 | 5187 | &base_vha->dpc_flags))) { |
1da177e4 | 5188 | |
a9083016 | 5189 | if (ha->isp_ops->abort_isp(base_vha)) { |
1da177e4 LT |
5190 | /* failed. retry later */ |
5191 | set_bit(ISP_ABORT_NEEDED, | |
e315cd28 | 5192 | &base_vha->dpc_flags); |
99363ef8 | 5193 | } |
e315cd28 AC |
5194 | clear_bit(ABORT_ISP_ACTIVE, |
5195 | &base_vha->dpc_flags); | |
99363ef8 SJ |
5196 | } |
5197 | ||
7c3df132 SK |
5198 | ql_dbg(ql_dbg_dpc, base_vha, 0x4008, |
5199 | "ISP abort end.\n"); | |
1da177e4 LT |
5200 | } |
5201 | ||
a394aac8 DJ |
5202 | if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, |
5203 | &base_vha->dpc_flags)) { | |
e315cd28 | 5204 | qla2x00_update_fcports(base_vha); |
c9c5ced9 | 5205 | } |
d97994dc | 5206 | |
2d70c103 NB |
5207 | if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) { |
5208 | int ret; | |
5209 | ret = qla2x00_send_change_request(base_vha, 0x3, 0); | |
5210 | if (ret != QLA_SUCCESS) | |
5211 | ql_log(ql_log_warn, base_vha, 0x121, | |
5212 | "Failed to enable receiving of RSCN " | |
5213 | "requests: 0x%x.\n", ret); | |
5214 | clear_bit(SCR_PENDING, &base_vha->dpc_flags); | |
5215 | } | |
5216 | ||
8ae6d9c7 GM |
5217 | if (IS_QLAFX00(ha)) |
5218 | goto loop_resync_check; | |
5219 | ||
579d12b5 | 5220 | if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { |
7c3df132 SK |
5221 | ql_dbg(ql_dbg_dpc, base_vha, 0x4009, |
5222 | "Quiescence mode scheduled.\n"); | |
7ec0effd AD |
5223 | if (IS_P3P_TYPE(ha)) { |
5224 | if (IS_QLA82XX(ha)) | |
5225 | qla82xx_device_state_handler(base_vha); | |
5226 | if (IS_QLA8044(ha)) | |
5227 | qla8044_device_state_handler(base_vha); | |
8fcd6b8b CD |
5228 | clear_bit(ISP_QUIESCE_NEEDED, |
5229 | &base_vha->dpc_flags); | |
5230 | if (!ha->flags.quiesce_owner) { | |
5231 | qla2x00_perform_loop_resync(base_vha); | |
7ec0effd AD |
5232 | if (IS_QLA82XX(ha)) { |
5233 | qla82xx_idc_lock(ha); | |
5234 | qla82xx_clear_qsnt_ready( | |
5235 | base_vha); | |
5236 | qla82xx_idc_unlock(ha); | |
5237 | } else if (IS_QLA8044(ha)) { | |
5238 | qla8044_idc_lock(ha); | |
5239 | qla8044_clear_qsnt_ready( | |
5240 | base_vha); | |
5241 | qla8044_idc_unlock(ha); | |
5242 | } | |
8fcd6b8b CD |
5243 | } |
5244 | } else { | |
5245 | clear_bit(ISP_QUIESCE_NEEDED, | |
5246 | &base_vha->dpc_flags); | |
5247 | qla2x00_quiesce_io(base_vha); | |
579d12b5 | 5248 | } |
7c3df132 SK |
5249 | ql_dbg(ql_dbg_dpc, base_vha, 0x400a, |
5250 | "Quiescence mode end.\n"); | |
579d12b5 SK |
5251 | } |
5252 | ||
e315cd28 | 5253 | if (test_and_clear_bit(RESET_MARKER_NEEDED, |
8ae6d9c7 | 5254 | &base_vha->dpc_flags) && |
e315cd28 | 5255 | (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { |
1da177e4 | 5256 | |
7c3df132 SK |
5257 | ql_dbg(ql_dbg_dpc, base_vha, 0x400b, |
5258 | "Reset marker scheduled.\n"); | |
e315cd28 AC |
5259 | qla2x00_rst_aen(base_vha); |
5260 | clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); | |
7c3df132 SK |
5261 | ql_dbg(ql_dbg_dpc, base_vha, 0x400c, |
5262 | "Reset marker end.\n"); | |
1da177e4 LT |
5263 | } |
5264 | ||
5265 | /* Retry each device up to login retry count */ | |
e315cd28 AC |
5266 | if ((test_and_clear_bit(RELOGIN_NEEDED, |
5267 | &base_vha->dpc_flags)) && | |
5268 | !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && | |
5269 | atomic_read(&base_vha->loop_state) != LOOP_DOWN) { | |
1da177e4 | 5270 | |
7c3df132 SK |
5271 | ql_dbg(ql_dbg_dpc, base_vha, 0x400d, |
5272 | "Relogin scheduled.\n"); | |
e315cd28 | 5273 | qla2x00_relogin(base_vha); |
7c3df132 SK |
5274 | ql_dbg(ql_dbg_dpc, base_vha, 0x400e, |
5275 | "Relogin end.\n"); | |
1da177e4 | 5276 | } |
8ae6d9c7 | 5277 | loop_resync_check: |
e315cd28 | 5278 | if (test_and_clear_bit(LOOP_RESYNC_NEEDED, |
8ae6d9c7 | 5279 | &base_vha->dpc_flags)) { |
1da177e4 | 5280 | |
7c3df132 SK |
5281 | ql_dbg(ql_dbg_dpc, base_vha, 0x400f, |
5282 | "Loop resync scheduled.\n"); | |
1da177e4 LT |
5283 | |
5284 | if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, | |
e315cd28 | 5285 | &base_vha->dpc_flags))) { |
1da177e4 | 5286 | |
52c82823 | 5287 | qla2x00_loop_resync(base_vha); |
1da177e4 | 5288 | |
e315cd28 AC |
5289 | clear_bit(LOOP_RESYNC_ACTIVE, |
5290 | &base_vha->dpc_flags); | |
1da177e4 LT |
5291 | } |
5292 | ||
7c3df132 SK |
5293 | ql_dbg(ql_dbg_dpc, base_vha, 0x4010, |
5294 | "Loop resync end.\n"); | |
1da177e4 LT |
5295 | } |
5296 | ||
8ae6d9c7 GM |
5297 | if (IS_QLAFX00(ha)) |
5298 | goto intr_on_check; | |
5299 | ||
e315cd28 AC |
5300 | if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && |
5301 | atomic_read(&base_vha->loop_state) == LOOP_READY) { | |
5302 | clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); | |
5303 | qla2xxx_flash_npiv_conf(base_vha); | |
272976ca AV |
5304 | } |
5305 | ||
8ae6d9c7 | 5306 | intr_on_check: |
1da177e4 | 5307 | if (!ha->interrupts_on) |
fd34f556 | 5308 | ha->isp_ops->enable_intrs(ha); |
1da177e4 | 5309 | |
e315cd28 | 5310 | if (test_and_clear_bit(BEACON_BLINK_NEEDED, |
90b604f2 HM |
5311 | &base_vha->dpc_flags)) { |
5312 | if (ha->beacon_blink_led == 1) | |
5313 | ha->isp_ops->beacon_blink(base_vha); | |
5314 | } | |
f6df144c | 5315 | |
8ae6d9c7 GM |
5316 | if (!IS_QLAFX00(ha)) |
5317 | qla2x00_do_dpc_all_vps(base_vha); | |
2c3dfe3f | 5318 | |
1da177e4 | 5319 | ha->dpc_active = 0; |
c142caf0 | 5320 | end_loop: |
563585ec | 5321 | set_current_state(TASK_INTERRUPTIBLE); |
1da177e4 | 5322 | } /* End of while(1) */ |
563585ec | 5323 | __set_current_state(TASK_RUNNING); |
1da177e4 | 5324 | |
7c3df132 SK |
5325 | ql_dbg(ql_dbg_dpc, base_vha, 0x4011, |
5326 | "DPC handler exiting.\n"); | |
1da177e4 LT |
5327 | |
5328 | /* | |
5329 | * Make sure that nobody tries to wake us up again. | |
5330 | */ | |
1da177e4 LT |
5331 | ha->dpc_active = 0; |
5332 | ||
ac280b67 AV |
5333 | /* Cleanup any residual CTX SRBs. */ |
5334 | qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); | |
5335 | ||
39a11240 CH |
5336 | return 0; |
5337 | } | |
5338 | ||
5339 | void | |
e315cd28 | 5340 | qla2xxx_wake_dpc(struct scsi_qla_host *vha) |
39a11240 | 5341 | { |
e315cd28 | 5342 | struct qla_hw_data *ha = vha->hw; |
c795c1e4 AV |
5343 | struct task_struct *t = ha->dpc_thread; |
5344 | ||
e315cd28 | 5345 | if (!test_bit(UNLOADING, &vha->dpc_flags) && t) |
c795c1e4 | 5346 | wake_up_process(t); |
1da177e4 LT |
5347 | } |
5348 | ||
1da177e4 LT |
5349 | /* |
5350 | * qla2x00_rst_aen | |
5351 | * Processes asynchronous reset. | |
5352 | * | |
5353 | * Input: | |
5354 | * ha = adapter block pointer. | |
5355 | */ | |
5356 | static void | |
e315cd28 | 5357 | qla2x00_rst_aen(scsi_qla_host_t *vha) |
1da177e4 | 5358 | { |
e315cd28 AC |
5359 | if (vha->flags.online && !vha->flags.reset_active && |
5360 | !atomic_read(&vha->loop_down_timer) && | |
5361 | !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { | |
1da177e4 | 5362 | do { |
e315cd28 | 5363 | clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); |
1da177e4 LT |
5364 | |
5365 | /* | |
5366 | * Issue marker command only when we are going to start | |
5367 | * the I/O. | |
5368 | */ | |
e315cd28 AC |
5369 | vha->marker_needed = 1; |
5370 | } while (!atomic_read(&vha->loop_down_timer) && | |
5371 | (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); | |
1da177e4 LT |
5372 | } |
5373 | } | |
5374 | ||
1da177e4 LT |
5375 | /************************************************************************** |
5376 | * qla2x00_timer | |
5377 | * | |
5378 | * Description: | |
5379 | * One second timer | |
5380 | * | |
5381 | * Context: Interrupt | |
5382 | ***************************************************************************/ | |
2c3dfe3f | 5383 | void |
e315cd28 | 5384 | qla2x00_timer(scsi_qla_host_t *vha) |
1da177e4 | 5385 | { |
1da177e4 | 5386 | unsigned long cpu_flags = 0; |
1da177e4 LT |
5387 | int start_dpc = 0; |
5388 | int index; | |
5389 | srb_t *sp; | |
85880801 | 5390 | uint16_t w; |
e315cd28 | 5391 | struct qla_hw_data *ha = vha->hw; |
73208dfd | 5392 | struct req_que *req; |
85880801 | 5393 | |
a5b36321 | 5394 | if (ha->flags.eeh_busy) { |
7c3df132 SK |
5395 | ql_dbg(ql_dbg_timer, vha, 0x6000, |
5396 | "EEH = %d, restarting timer.\n", | |
5397 | ha->flags.eeh_busy); | |
a5b36321 LC |
5398 | qla2x00_restart_timer(vha, WATCH_INTERVAL); |
5399 | return; | |
5400 | } | |
5401 | ||
f3ddac19 CD |
5402 | /* |
5403 | * Hardware read to raise pending EEH errors during mailbox waits. If | |
5404 | * the read returns -1 then disable the board. | |
5405 | */ | |
5406 | if (!pci_channel_offline(ha->pdev)) { | |
85880801 | 5407 | pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); |
c821e0d5 | 5408 | qla2x00_check_reg16_for_disconnect(vha, w); |
f3ddac19 | 5409 | } |
1da177e4 | 5410 | |
cefcaba6 | 5411 | /* Make sure qla82xx_watchdog is run only for physical port */ |
7ec0effd | 5412 | if (!vha->vp_idx && IS_P3P_TYPE(ha)) { |
579d12b5 SK |
5413 | if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) |
5414 | start_dpc++; | |
7ec0effd AD |
5415 | if (IS_QLA82XX(ha)) |
5416 | qla82xx_watchdog(vha); | |
5417 | else if (IS_QLA8044(ha)) | |
5418 | qla8044_watchdog(vha); | |
579d12b5 SK |
5419 | } |
5420 | ||
8ae6d9c7 GM |
5421 | if (!vha->vp_idx && IS_QLAFX00(ha)) |
5422 | qlafx00_timer_routine(vha); | |
5423 | ||
1da177e4 | 5424 | /* Loop down handler. */ |
e315cd28 | 5425 | if (atomic_read(&vha->loop_down_timer) > 0 && |
8f7daead GM |
5426 | !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && |
5427 | !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) | |
e315cd28 | 5428 | && vha->flags.online) { |
1da177e4 | 5429 | |
e315cd28 AC |
5430 | if (atomic_read(&vha->loop_down_timer) == |
5431 | vha->loop_down_abort_time) { | |
1da177e4 | 5432 | |
7c3df132 SK |
5433 | ql_log(ql_log_info, vha, 0x6008, |
5434 | "Loop down - aborting the queues before time expires.\n"); | |
1da177e4 | 5435 | |
e315cd28 AC |
5436 | if (!IS_QLA2100(ha) && vha->link_down_timeout) |
5437 | atomic_set(&vha->loop_state, LOOP_DEAD); | |
1da177e4 | 5438 | |
f08b7251 AV |
5439 | /* |
5440 | * Schedule an ISP abort to return any FCP2-device | |
5441 | * commands. | |
5442 | */ | |
2c3dfe3f | 5443 | /* NPIV - scan physical port only */ |
e315cd28 | 5444 | if (!vha->vp_idx) { |
2c3dfe3f SJ |
5445 | spin_lock_irqsave(&ha->hardware_lock, |
5446 | cpu_flags); | |
73208dfd | 5447 | req = ha->req_q_map[0]; |
2c3dfe3f | 5448 | for (index = 1; |
8d93f550 | 5449 | index < req->num_outstanding_cmds; |
2c3dfe3f SJ |
5450 | index++) { |
5451 | fc_port_t *sfcp; | |
5452 | ||
e315cd28 | 5453 | sp = req->outstanding_cmds[index]; |
2c3dfe3f SJ |
5454 | if (!sp) |
5455 | continue; | |
9ba56b95 | 5456 | if (sp->type != SRB_SCSI_CMD) |
cf53b069 | 5457 | continue; |
2c3dfe3f | 5458 | sfcp = sp->fcport; |
f08b7251 | 5459 | if (!(sfcp->flags & FCF_FCP2_DEVICE)) |
2c3dfe3f | 5460 | continue; |
bdf79621 | 5461 | |
8f7daead GM |
5462 | if (IS_QLA82XX(ha)) |
5463 | set_bit(FCOE_CTX_RESET_NEEDED, | |
5464 | &vha->dpc_flags); | |
5465 | else | |
5466 | set_bit(ISP_ABORT_NEEDED, | |
e315cd28 | 5467 | &vha->dpc_flags); |
2c3dfe3f SJ |
5468 | break; |
5469 | } | |
5470 | spin_unlock_irqrestore(&ha->hardware_lock, | |
e315cd28 | 5471 | cpu_flags); |
1da177e4 | 5472 | } |
1da177e4 LT |
5473 | start_dpc++; |
5474 | } | |
5475 | ||
5476 | /* if the loop has been down for 4 minutes, reinit adapter */ | |
e315cd28 | 5477 | if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { |
0d6e61bc | 5478 | if (!(vha->device_flags & DFLG_NO_CABLE)) { |
7c3df132 | 5479 | ql_log(ql_log_warn, vha, 0x6009, |
1da177e4 LT |
5480 | "Loop down - aborting ISP.\n"); |
5481 | ||
8f7daead GM |
5482 | if (IS_QLA82XX(ha)) |
5483 | set_bit(FCOE_CTX_RESET_NEEDED, | |
5484 | &vha->dpc_flags); | |
5485 | else | |
5486 | set_bit(ISP_ABORT_NEEDED, | |
5487 | &vha->dpc_flags); | |
1da177e4 LT |
5488 | } |
5489 | } | |
7c3df132 SK |
5490 | ql_dbg(ql_dbg_timer, vha, 0x600a, |
5491 | "Loop down - seconds remaining %d.\n", | |
5492 | atomic_read(&vha->loop_down_timer)); | |
1da177e4 | 5493 | } |
cefcaba6 SK |
5494 | /* Check if beacon LED needs to be blinked for physical host only */ |
5495 | if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { | |
999916dc | 5496 | /* There is no beacon_blink function for ISP82xx */ |
7ec0effd | 5497 | if (!IS_P3P_TYPE(ha)) { |
999916dc SK |
5498 | set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); |
5499 | start_dpc++; | |
5500 | } | |
f6df144c | 5501 | } |
5502 | ||
550bf57d | 5503 | /* Process any deferred work. */ |
e315cd28 | 5504 | if (!list_empty(&vha->work_list)) |
550bf57d AV |
5505 | start_dpc++; |
5506 | ||
1da177e4 | 5507 | /* Schedule the DPC routine if needed */ |
e315cd28 AC |
5508 | if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || |
5509 | test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || | |
5510 | test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || | |
1da177e4 | 5511 | start_dpc || |
e315cd28 AC |
5512 | test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || |
5513 | test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || | |
a9083016 GM |
5514 | test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || |
5515 | test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || | |
e315cd28 | 5516 | test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || |
50280c01 | 5517 | test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) { |
7c3df132 SK |
5518 | ql_dbg(ql_dbg_timer, vha, 0x600b, |
5519 | "isp_abort_needed=%d loop_resync_needed=%d " | |
5520 | "fcport_update_needed=%d start_dpc=%d " | |
5521 | "reset_marker_needed=%d", | |
5522 | test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), | |
5523 | test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), | |
5524 | test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), | |
5525 | start_dpc, | |
5526 | test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); | |
5527 | ql_dbg(ql_dbg_timer, vha, 0x600c, | |
5528 | "beacon_blink_needed=%d isp_unrecoverable=%d " | |
5529 | "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " | |
50280c01 | 5530 | "relogin_needed=%d.\n", |
7c3df132 SK |
5531 | test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), |
5532 | test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), | |
5533 | test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), | |
5534 | test_bit(VP_DPC_NEEDED, &vha->dpc_flags), | |
50280c01 | 5535 | test_bit(RELOGIN_NEEDED, &vha->dpc_flags)); |
e315cd28 | 5536 | qla2xxx_wake_dpc(vha); |
7c3df132 | 5537 | } |
1da177e4 | 5538 | |
e315cd28 | 5539 | qla2x00_restart_timer(vha, WATCH_INTERVAL); |
1da177e4 LT |
5540 | } |
5541 | ||
5433383e AV |
5542 | /* Firmware interface routines. */ |
5543 | ||
f73cb695 | 5544 | #define FW_BLOBS 11 |
5433383e AV |
5545 | #define FW_ISP21XX 0 |
5546 | #define FW_ISP22XX 1 | |
5547 | #define FW_ISP2300 2 | |
5548 | #define FW_ISP2322 3 | |
48c02fde | 5549 | #define FW_ISP24XX 4 |
c3a2f0df | 5550 | #define FW_ISP25XX 5 |
3a03eb79 | 5551 | #define FW_ISP81XX 6 |
a9083016 | 5552 | #define FW_ISP82XX 7 |
6246b8a1 GM |
5553 | #define FW_ISP2031 8 |
5554 | #define FW_ISP8031 9 | |
2c5bbbb2 | 5555 | #define FW_ISP27XX 10 |
5433383e | 5556 | |
bb8ee499 AV |
5557 | #define FW_FILE_ISP21XX "ql2100_fw.bin" |
5558 | #define FW_FILE_ISP22XX "ql2200_fw.bin" | |
5559 | #define FW_FILE_ISP2300 "ql2300_fw.bin" | |
5560 | #define FW_FILE_ISP2322 "ql2322_fw.bin" | |
5561 | #define FW_FILE_ISP24XX "ql2400_fw.bin" | |
c3a2f0df | 5562 | #define FW_FILE_ISP25XX "ql2500_fw.bin" |
3a03eb79 | 5563 | #define FW_FILE_ISP81XX "ql8100_fw.bin" |
a9083016 | 5564 | #define FW_FILE_ISP82XX "ql8200_fw.bin" |
6246b8a1 GM |
5565 | #define FW_FILE_ISP2031 "ql2600_fw.bin" |
5566 | #define FW_FILE_ISP8031 "ql8300_fw.bin" | |
2c5bbbb2 | 5567 | #define FW_FILE_ISP27XX "ql2700_fw.bin" |
f73cb695 | 5568 | |
bb8ee499 | 5569 | |
e1e82b6f | 5570 | static DEFINE_MUTEX(qla_fw_lock); |
5433383e AV |
5571 | |
5572 | static struct fw_blob qla_fw_blobs[FW_BLOBS] = { | |
bb8ee499 AV |
5573 | { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, |
5574 | { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, | |
5575 | { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, | |
5576 | { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, | |
5577 | { .name = FW_FILE_ISP24XX, }, | |
c3a2f0df | 5578 | { .name = FW_FILE_ISP25XX, }, |
3a03eb79 | 5579 | { .name = FW_FILE_ISP81XX, }, |
a9083016 | 5580 | { .name = FW_FILE_ISP82XX, }, |
6246b8a1 GM |
5581 | { .name = FW_FILE_ISP2031, }, |
5582 | { .name = FW_FILE_ISP8031, }, | |
2c5bbbb2 | 5583 | { .name = FW_FILE_ISP27XX, }, |
5433383e AV |
5584 | }; |
5585 | ||
5586 | struct fw_blob * | |
e315cd28 | 5587 | qla2x00_request_firmware(scsi_qla_host_t *vha) |
5433383e | 5588 | { |
e315cd28 | 5589 | struct qla_hw_data *ha = vha->hw; |
5433383e AV |
5590 | struct fw_blob *blob; |
5591 | ||
5433383e AV |
5592 | if (IS_QLA2100(ha)) { |
5593 | blob = &qla_fw_blobs[FW_ISP21XX]; | |
5594 | } else if (IS_QLA2200(ha)) { | |
5595 | blob = &qla_fw_blobs[FW_ISP22XX]; | |
48c02fde | 5596 | } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { |
5433383e | 5597 | blob = &qla_fw_blobs[FW_ISP2300]; |
48c02fde | 5598 | } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { |
5433383e | 5599 | blob = &qla_fw_blobs[FW_ISP2322]; |
4d4df193 | 5600 | } else if (IS_QLA24XX_TYPE(ha)) { |
5433383e | 5601 | blob = &qla_fw_blobs[FW_ISP24XX]; |
c3a2f0df AV |
5602 | } else if (IS_QLA25XX(ha)) { |
5603 | blob = &qla_fw_blobs[FW_ISP25XX]; | |
3a03eb79 AV |
5604 | } else if (IS_QLA81XX(ha)) { |
5605 | blob = &qla_fw_blobs[FW_ISP81XX]; | |
a9083016 GM |
5606 | } else if (IS_QLA82XX(ha)) { |
5607 | blob = &qla_fw_blobs[FW_ISP82XX]; | |
6246b8a1 GM |
5608 | } else if (IS_QLA2031(ha)) { |
5609 | blob = &qla_fw_blobs[FW_ISP2031]; | |
5610 | } else if (IS_QLA8031(ha)) { | |
5611 | blob = &qla_fw_blobs[FW_ISP8031]; | |
2c5bbbb2 JC |
5612 | } else if (IS_QLA27XX(ha)) { |
5613 | blob = &qla_fw_blobs[FW_ISP27XX]; | |
8a655229 DC |
5614 | } else { |
5615 | return NULL; | |
5433383e AV |
5616 | } |
5617 | ||
e1e82b6f | 5618 | mutex_lock(&qla_fw_lock); |
5433383e AV |
5619 | if (blob->fw) |
5620 | goto out; | |
5621 | ||
5622 | if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { | |
7c3df132 SK |
5623 | ql_log(ql_log_warn, vha, 0x0063, |
5624 | "Failed to load firmware image (%s).\n", blob->name); | |
5433383e AV |
5625 | blob->fw = NULL; |
5626 | blob = NULL; | |
5627 | goto out; | |
5628 | } | |
5629 | ||
5630 | out: | |
e1e82b6f | 5631 | mutex_unlock(&qla_fw_lock); |
5433383e AV |
5632 | return blob; |
5633 | } | |
5634 | ||
5635 | static void | |
5636 | qla2x00_release_firmware(void) | |
5637 | { | |
5638 | int idx; | |
5639 | ||
e1e82b6f | 5640 | mutex_lock(&qla_fw_lock); |
5433383e | 5641 | for (idx = 0; idx < FW_BLOBS; idx++) |
cf92549f | 5642 | release_firmware(qla_fw_blobs[idx].fw); |
e1e82b6f | 5643 | mutex_unlock(&qla_fw_lock); |
5433383e AV |
5644 | } |
5645 | ||
14e660e6 SJ |
5646 | static pci_ers_result_t |
5647 | qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) | |
5648 | { | |
85880801 AV |
5649 | scsi_qla_host_t *vha = pci_get_drvdata(pdev); |
5650 | struct qla_hw_data *ha = vha->hw; | |
5651 | ||
7c3df132 SK |
5652 | ql_dbg(ql_dbg_aer, vha, 0x9000, |
5653 | "PCI error detected, state %x.\n", state); | |
b9b12f73 | 5654 | |
14e660e6 SJ |
5655 | switch (state) { |
5656 | case pci_channel_io_normal: | |
85880801 | 5657 | ha->flags.eeh_busy = 0; |
14e660e6 SJ |
5658 | return PCI_ERS_RESULT_CAN_RECOVER; |
5659 | case pci_channel_io_frozen: | |
85880801 | 5660 | ha->flags.eeh_busy = 1; |
a5b36321 LC |
5661 | /* For ISP82XX complete any pending mailbox cmd */ |
5662 | if (IS_QLA82XX(ha)) { | |
7190575f | 5663 | ha->flags.isp82xx_fw_hung = 1; |
c8f6544e CD |
5664 | ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n"); |
5665 | qla82xx_clear_pending_mbx(vha); | |
a5b36321 | 5666 | } |
90a86fc0 | 5667 | qla2x00_free_irqs(vha); |
14e660e6 | 5668 | pci_disable_device(pdev); |
bddd2d65 LC |
5669 | /* Return back all IOs */ |
5670 | qla2x00_abort_all_cmds(vha, DID_RESET << 16); | |
14e660e6 SJ |
5671 | return PCI_ERS_RESULT_NEED_RESET; |
5672 | case pci_channel_io_perm_failure: | |
85880801 AV |
5673 | ha->flags.pci_channel_io_perm_failure = 1; |
5674 | qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); | |
14e660e6 SJ |
5675 | return PCI_ERS_RESULT_DISCONNECT; |
5676 | } | |
5677 | return PCI_ERS_RESULT_NEED_RESET; | |
5678 | } | |
5679 | ||
5680 | static pci_ers_result_t | |
5681 | qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) | |
5682 | { | |
5683 | int risc_paused = 0; | |
5684 | uint32_t stat; | |
5685 | unsigned long flags; | |
e315cd28 AC |
5686 | scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); |
5687 | struct qla_hw_data *ha = base_vha->hw; | |
14e660e6 SJ |
5688 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
5689 | struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; | |
5690 | ||
bcc5b6d3 SK |
5691 | if (IS_QLA82XX(ha)) |
5692 | return PCI_ERS_RESULT_RECOVERED; | |
5693 | ||
14e660e6 SJ |
5694 | spin_lock_irqsave(&ha->hardware_lock, flags); |
5695 | if (IS_QLA2100(ha) || IS_QLA2200(ha)){ | |
5696 | stat = RD_REG_DWORD(®->hccr); | |
5697 | if (stat & HCCR_RISC_PAUSE) | |
5698 | risc_paused = 1; | |
5699 | } else if (IS_QLA23XX(ha)) { | |
5700 | stat = RD_REG_DWORD(®->u.isp2300.host_status); | |
5701 | if (stat & HSR_RISC_PAUSED) | |
5702 | risc_paused = 1; | |
5703 | } else if (IS_FWI2_CAPABLE(ha)) { | |
5704 | stat = RD_REG_DWORD(®24->host_status); | |
5705 | if (stat & HSRX_RISC_PAUSED) | |
5706 | risc_paused = 1; | |
5707 | } | |
5708 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
5709 | ||
5710 | if (risc_paused) { | |
7c3df132 SK |
5711 | ql_log(ql_log_info, base_vha, 0x9003, |
5712 | "RISC paused -- mmio_enabled, Dumping firmware.\n"); | |
e315cd28 | 5713 | ha->isp_ops->fw_dump(base_vha, 0); |
14e660e6 SJ |
5714 | |
5715 | return PCI_ERS_RESULT_NEED_RESET; | |
5716 | } else | |
5717 | return PCI_ERS_RESULT_RECOVERED; | |
5718 | } | |
5719 | ||
fa492630 SK |
5720 | static uint32_t |
5721 | qla82xx_error_recovery(scsi_qla_host_t *base_vha) | |
a5b36321 LC |
5722 | { |
5723 | uint32_t rval = QLA_FUNCTION_FAILED; | |
5724 | uint32_t drv_active = 0; | |
5725 | struct qla_hw_data *ha = base_vha->hw; | |
5726 | int fn; | |
5727 | struct pci_dev *other_pdev = NULL; | |
5728 | ||
7c3df132 SK |
5729 | ql_dbg(ql_dbg_aer, base_vha, 0x9006, |
5730 | "Entered %s.\n", __func__); | |
a5b36321 LC |
5731 | |
5732 | set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); | |
5733 | ||
5734 | if (base_vha->flags.online) { | |
5735 | /* Abort all outstanding commands, | |
5736 | * so as to be requeued later */ | |
5737 | qla2x00_abort_isp_cleanup(base_vha); | |
5738 | } | |
5739 | ||
5740 | ||
5741 | fn = PCI_FUNC(ha->pdev->devfn); | |
5742 | while (fn > 0) { | |
5743 | fn--; | |
7c3df132 SK |
5744 | ql_dbg(ql_dbg_aer, base_vha, 0x9007, |
5745 | "Finding pci device at function = 0x%x.\n", fn); | |
a5b36321 LC |
5746 | other_pdev = |
5747 | pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus), | |
5748 | ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn), | |
5749 | fn)); | |
5750 | ||
5751 | if (!other_pdev) | |
5752 | continue; | |
5753 | if (atomic_read(&other_pdev->enable_cnt)) { | |
7c3df132 SK |
5754 | ql_dbg(ql_dbg_aer, base_vha, 0x9008, |
5755 | "Found PCI func available and enable at 0x%x.\n", | |
5756 | fn); | |
a5b36321 LC |
5757 | pci_dev_put(other_pdev); |
5758 | break; | |
5759 | } | |
5760 | pci_dev_put(other_pdev); | |
5761 | } | |
5762 | ||
5763 | if (!fn) { | |
5764 | /* Reset owner */ | |
7c3df132 SK |
5765 | ql_dbg(ql_dbg_aer, base_vha, 0x9009, |
5766 | "This devfn is reset owner = 0x%x.\n", | |
5767 | ha->pdev->devfn); | |
a5b36321 LC |
5768 | qla82xx_idc_lock(ha); |
5769 | ||
5770 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | |
7d613ac6 | 5771 | QLA8XXX_DEV_INITIALIZING); |
a5b36321 LC |
5772 | |
5773 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, | |
5774 | QLA82XX_IDC_VERSION); | |
5775 | ||
5776 | drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); | |
7c3df132 SK |
5777 | ql_dbg(ql_dbg_aer, base_vha, 0x900a, |
5778 | "drv_active = 0x%x.\n", drv_active); | |
a5b36321 LC |
5779 | |
5780 | qla82xx_idc_unlock(ha); | |
5781 | /* Reset if device is not already reset | |
5782 | * drv_active would be 0 if a reset has already been done | |
5783 | */ | |
5784 | if (drv_active) | |
5785 | rval = qla82xx_start_firmware(base_vha); | |
5786 | else | |
5787 | rval = QLA_SUCCESS; | |
5788 | qla82xx_idc_lock(ha); | |
5789 | ||
5790 | if (rval != QLA_SUCCESS) { | |
7c3df132 SK |
5791 | ql_log(ql_log_info, base_vha, 0x900b, |
5792 | "HW State: FAILED.\n"); | |
a5b36321 LC |
5793 | qla82xx_clear_drv_active(ha); |
5794 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | |
7d613ac6 | 5795 | QLA8XXX_DEV_FAILED); |
a5b36321 | 5796 | } else { |
7c3df132 SK |
5797 | ql_log(ql_log_info, base_vha, 0x900c, |
5798 | "HW State: READY.\n"); | |
a5b36321 | 5799 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, |
7d613ac6 | 5800 | QLA8XXX_DEV_READY); |
a5b36321 | 5801 | qla82xx_idc_unlock(ha); |
7190575f | 5802 | ha->flags.isp82xx_fw_hung = 0; |
a5b36321 LC |
5803 | rval = qla82xx_restart_isp(base_vha); |
5804 | qla82xx_idc_lock(ha); | |
5805 | /* Clear driver state register */ | |
5806 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); | |
5807 | qla82xx_set_drv_active(base_vha); | |
5808 | } | |
5809 | qla82xx_idc_unlock(ha); | |
5810 | } else { | |
7c3df132 SK |
5811 | ql_dbg(ql_dbg_aer, base_vha, 0x900d, |
5812 | "This devfn is not reset owner = 0x%x.\n", | |
5813 | ha->pdev->devfn); | |
a5b36321 | 5814 | if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) == |
7d613ac6 | 5815 | QLA8XXX_DEV_READY)) { |
7190575f | 5816 | ha->flags.isp82xx_fw_hung = 0; |
a5b36321 LC |
5817 | rval = qla82xx_restart_isp(base_vha); |
5818 | qla82xx_idc_lock(ha); | |
5819 | qla82xx_set_drv_active(base_vha); | |
5820 | qla82xx_idc_unlock(ha); | |
5821 | } | |
5822 | } | |
5823 | clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); | |
5824 | ||
5825 | return rval; | |
5826 | } | |
5827 | ||
14e660e6 SJ |
5828 | static pci_ers_result_t |
5829 | qla2xxx_pci_slot_reset(struct pci_dev *pdev) | |
5830 | { | |
5831 | pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; | |
e315cd28 AC |
5832 | scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); |
5833 | struct qla_hw_data *ha = base_vha->hw; | |
90a86fc0 JC |
5834 | struct rsp_que *rsp; |
5835 | int rc, retries = 10; | |
09483916 | 5836 | |
7c3df132 SK |
5837 | ql_dbg(ql_dbg_aer, base_vha, 0x9004, |
5838 | "Slot Reset.\n"); | |
85880801 | 5839 | |
90a86fc0 JC |
5840 | /* Workaround: qla2xxx driver which access hardware earlier |
5841 | * needs error state to be pci_channel_io_online. | |
5842 | * Otherwise mailbox command timesout. | |
5843 | */ | |
5844 | pdev->error_state = pci_channel_io_normal; | |
5845 | ||
5846 | pci_restore_state(pdev); | |
5847 | ||
8c1496bd RL |
5848 | /* pci_restore_state() clears the saved_state flag of the device |
5849 | * save restored state which resets saved_state flag | |
5850 | */ | |
5851 | pci_save_state(pdev); | |
5852 | ||
09483916 BH |
5853 | if (ha->mem_only) |
5854 | rc = pci_enable_device_mem(pdev); | |
5855 | else | |
5856 | rc = pci_enable_device(pdev); | |
14e660e6 | 5857 | |
09483916 | 5858 | if (rc) { |
7c3df132 | 5859 | ql_log(ql_log_warn, base_vha, 0x9005, |
14e660e6 | 5860 | "Can't re-enable PCI device after reset.\n"); |
a5b36321 | 5861 | goto exit_slot_reset; |
14e660e6 | 5862 | } |
14e660e6 | 5863 | |
90a86fc0 JC |
5864 | rsp = ha->rsp_q_map[0]; |
5865 | if (qla2x00_request_irqs(ha, rsp)) | |
a5b36321 | 5866 | goto exit_slot_reset; |
90a86fc0 | 5867 | |
e315cd28 | 5868 | if (ha->isp_ops->pci_config(base_vha)) |
a5b36321 LC |
5869 | goto exit_slot_reset; |
5870 | ||
5871 | if (IS_QLA82XX(ha)) { | |
5872 | if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) { | |
5873 | ret = PCI_ERS_RESULT_RECOVERED; | |
5874 | goto exit_slot_reset; | |
5875 | } else | |
5876 | goto exit_slot_reset; | |
5877 | } | |
14e660e6 | 5878 | |
90a86fc0 JC |
5879 | while (ha->flags.mbox_busy && retries--) |
5880 | msleep(1000); | |
85880801 | 5881 | |
e315cd28 | 5882 | set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); |
a9083016 | 5883 | if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) |
14e660e6 | 5884 | ret = PCI_ERS_RESULT_RECOVERED; |
e315cd28 | 5885 | clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); |
14e660e6 | 5886 | |
90a86fc0 | 5887 | |
a5b36321 | 5888 | exit_slot_reset: |
7c3df132 SK |
5889 | ql_dbg(ql_dbg_aer, base_vha, 0x900e, |
5890 | "slot_reset return %x.\n", ret); | |
85880801 | 5891 | |
14e660e6 SJ |
5892 | return ret; |
5893 | } | |
5894 | ||
5895 | static void | |
5896 | qla2xxx_pci_resume(struct pci_dev *pdev) | |
5897 | { | |
e315cd28 AC |
5898 | scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); |
5899 | struct qla_hw_data *ha = base_vha->hw; | |
14e660e6 SJ |
5900 | int ret; |
5901 | ||
7c3df132 SK |
5902 | ql_dbg(ql_dbg_aer, base_vha, 0x900f, |
5903 | "pci_resume.\n"); | |
85880801 | 5904 | |
e315cd28 | 5905 | ret = qla2x00_wait_for_hba_online(base_vha); |
14e660e6 | 5906 | if (ret != QLA_SUCCESS) { |
7c3df132 SK |
5907 | ql_log(ql_log_fatal, base_vha, 0x9002, |
5908 | "The device failed to resume I/O from slot/link_reset.\n"); | |
14e660e6 | 5909 | } |
85880801 | 5910 | |
3e46f031 LC |
5911 | pci_cleanup_aer_uncorrect_error_status(pdev); |
5912 | ||
85880801 | 5913 | ha->flags.eeh_busy = 0; |
14e660e6 SJ |
5914 | } |
5915 | ||
2d5a4c34 HM |
5916 | static void |
5917 | qla83xx_disable_laser(scsi_qla_host_t *vha) | |
5918 | { | |
5919 | uint32_t reg, data, fn; | |
5920 | struct qla_hw_data *ha = vha->hw; | |
5921 | struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24; | |
5922 | ||
5923 | /* pci func #/port # */ | |
5924 | ql_dbg(ql_dbg_init, vha, 0x004b, | |
5925 | "Disabling Laser for hba: %p\n", vha); | |
5926 | ||
5927 | fn = (RD_REG_DWORD(&isp_reg->ctrl_status) & | |
5928 | (BIT_15|BIT_14|BIT_13|BIT_12)); | |
5929 | ||
5930 | fn = (fn >> 12); | |
5931 | ||
5932 | if (fn & 1) | |
5933 | reg = PORT_1_2031; | |
5934 | else | |
5935 | reg = PORT_0_2031; | |
5936 | ||
5937 | data = LASER_OFF_2031; | |
5938 | ||
5939 | qla83xx_wr_reg(vha, reg, data); | |
5940 | } | |
5941 | ||
a55b2d21 | 5942 | static const struct pci_error_handlers qla2xxx_err_handler = { |
14e660e6 SJ |
5943 | .error_detected = qla2xxx_pci_error_detected, |
5944 | .mmio_enabled = qla2xxx_pci_mmio_enabled, | |
5945 | .slot_reset = qla2xxx_pci_slot_reset, | |
5946 | .resume = qla2xxx_pci_resume, | |
5947 | }; | |
5948 | ||
5433383e | 5949 | static struct pci_device_id qla2xxx_pci_tbl[] = { |
47f5e069 AV |
5950 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, |
5951 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, | |
5952 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, | |
5953 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, | |
5954 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, | |
5955 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, | |
5956 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, | |
5957 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, | |
5958 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, | |
4d4df193 | 5959 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, |
47f5e069 AV |
5960 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, |
5961 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, | |
c3a2f0df | 5962 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, |
6246b8a1 | 5963 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, |
3a03eb79 | 5964 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, |
a9083016 | 5965 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, |
650f528f | 5966 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, |
8ae6d9c7 | 5967 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, |
7ec0effd | 5968 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, |
f73cb695 | 5969 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, |
2c5bbbb2 | 5970 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, |
2b48992f | 5971 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, |
5433383e AV |
5972 | { 0 }, |
5973 | }; | |
5974 | MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); | |
5975 | ||
fca29703 | 5976 | static struct pci_driver qla2xxx_pci_driver = { |
cb63067a | 5977 | .name = QLA2XXX_DRIVER_NAME, |
0a21ef1e JB |
5978 | .driver = { |
5979 | .owner = THIS_MODULE, | |
5980 | }, | |
fca29703 | 5981 | .id_table = qla2xxx_pci_tbl, |
7ee61397 | 5982 | .probe = qla2x00_probe_one, |
4c993f76 | 5983 | .remove = qla2x00_remove_one, |
e30d1756 | 5984 | .shutdown = qla2x00_shutdown, |
14e660e6 | 5985 | .err_handler = &qla2xxx_err_handler, |
fca29703 AV |
5986 | }; |
5987 | ||
75ef9de1 | 5988 | static const struct file_operations apidev_fops = { |
6a03b4cd | 5989 | .owner = THIS_MODULE, |
6038f373 | 5990 | .llseek = noop_llseek, |
6a03b4cd HZ |
5991 | }; |
5992 | ||
1da177e4 LT |
5993 | /** |
5994 | * qla2x00_module_init - Module initialization. | |
5995 | **/ | |
5996 | static int __init | |
5997 | qla2x00_module_init(void) | |
5998 | { | |
fca29703 AV |
5999 | int ret = 0; |
6000 | ||
1da177e4 | 6001 | /* Allocate cache for SRBs. */ |
354d6b21 | 6002 | srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, |
20c2df83 | 6003 | SLAB_HWCACHE_ALIGN, NULL); |
1da177e4 | 6004 | if (srb_cachep == NULL) { |
7c3df132 SK |
6005 | ql_log(ql_log_fatal, NULL, 0x0001, |
6006 | "Unable to allocate SRB cache...Failing load!.\n"); | |
1da177e4 LT |
6007 | return -ENOMEM; |
6008 | } | |
6009 | ||
2d70c103 NB |
6010 | /* Initialize target kmem_cache and mem_pools */ |
6011 | ret = qlt_init(); | |
6012 | if (ret < 0) { | |
6013 | kmem_cache_destroy(srb_cachep); | |
6014 | return ret; | |
6015 | } else if (ret > 0) { | |
6016 | /* | |
6017 | * If initiator mode is explictly disabled by qlt_init(), | |
6018 | * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from | |
6019 | * performing scsi_scan_target() during LOOP UP event. | |
6020 | */ | |
6021 | qla2xxx_transport_functions.disable_target_scan = 1; | |
6022 | qla2xxx_transport_vport_functions.disable_target_scan = 1; | |
6023 | } | |
6024 | ||
1da177e4 LT |
6025 | /* Derive version string. */ |
6026 | strcpy(qla2x00_version_str, QLA2XXX_VERSION); | |
11010fec | 6027 | if (ql2xextended_error_logging) |
0181944f AV |
6028 | strcat(qla2x00_version_str, "-debug"); |
6029 | ||
1c97a12a AV |
6030 | qla2xxx_transport_template = |
6031 | fc_attach_transport(&qla2xxx_transport_functions); | |
2c3dfe3f SJ |
6032 | if (!qla2xxx_transport_template) { |
6033 | kmem_cache_destroy(srb_cachep); | |
7c3df132 SK |
6034 | ql_log(ql_log_fatal, NULL, 0x0002, |
6035 | "fc_attach_transport failed...Failing load!.\n"); | |
2d70c103 | 6036 | qlt_exit(); |
1da177e4 | 6037 | return -ENODEV; |
2c3dfe3f | 6038 | } |
6a03b4cd HZ |
6039 | |
6040 | apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); | |
6041 | if (apidev_major < 0) { | |
7c3df132 SK |
6042 | ql_log(ql_log_fatal, NULL, 0x0003, |
6043 | "Unable to register char device %s.\n", QLA2XXX_APIDEV); | |
6a03b4cd HZ |
6044 | } |
6045 | ||
2c3dfe3f SJ |
6046 | qla2xxx_transport_vport_template = |
6047 | fc_attach_transport(&qla2xxx_transport_vport_functions); | |
6048 | if (!qla2xxx_transport_vport_template) { | |
6049 | kmem_cache_destroy(srb_cachep); | |
2d70c103 | 6050 | qlt_exit(); |
2c3dfe3f | 6051 | fc_release_transport(qla2xxx_transport_template); |
7c3df132 SK |
6052 | ql_log(ql_log_fatal, NULL, 0x0004, |
6053 | "fc_attach_transport vport failed...Failing load!.\n"); | |
1da177e4 | 6054 | return -ENODEV; |
2c3dfe3f | 6055 | } |
7c3df132 SK |
6056 | ql_log(ql_log_info, NULL, 0x0005, |
6057 | "QLogic Fibre Channel HBA Driver: %s.\n", | |
fd9a29f0 | 6058 | qla2x00_version_str); |
7ee61397 | 6059 | ret = pci_register_driver(&qla2xxx_pci_driver); |
fca29703 AV |
6060 | if (ret) { |
6061 | kmem_cache_destroy(srb_cachep); | |
2d70c103 | 6062 | qlt_exit(); |
fca29703 | 6063 | fc_release_transport(qla2xxx_transport_template); |
2c3dfe3f | 6064 | fc_release_transport(qla2xxx_transport_vport_template); |
7c3df132 SK |
6065 | ql_log(ql_log_fatal, NULL, 0x0006, |
6066 | "pci_register_driver failed...ret=%d Failing load!.\n", | |
6067 | ret); | |
fca29703 AV |
6068 | } |
6069 | return ret; | |
1da177e4 LT |
6070 | } |
6071 | ||
6072 | /** | |
6073 | * qla2x00_module_exit - Module cleanup. | |
6074 | **/ | |
6075 | static void __exit | |
6076 | qla2x00_module_exit(void) | |
6077 | { | |
6a03b4cd | 6078 | unregister_chrdev(apidev_major, QLA2XXX_APIDEV); |
7ee61397 | 6079 | pci_unregister_driver(&qla2xxx_pci_driver); |
5433383e | 6080 | qla2x00_release_firmware(); |
354d6b21 | 6081 | kmem_cache_destroy(srb_cachep); |
2d70c103 | 6082 | qlt_exit(); |
a9083016 GM |
6083 | if (ctx_cachep) |
6084 | kmem_cache_destroy(ctx_cachep); | |
1da177e4 | 6085 | fc_release_transport(qla2xxx_transport_template); |
2c3dfe3f | 6086 | fc_release_transport(qla2xxx_transport_vport_template); |
1da177e4 LT |
6087 | } |
6088 | ||
6089 | module_init(qla2x00_module_init); | |
6090 | module_exit(qla2x00_module_exit); | |
6091 | ||
6092 | MODULE_AUTHOR("QLogic Corporation"); | |
6093 | MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); | |
6094 | MODULE_LICENSE("GPL"); | |
6095 | MODULE_VERSION(QLA2XXX_VERSION); | |
bb8ee499 AV |
6096 | MODULE_FIRMWARE(FW_FILE_ISP21XX); |
6097 | MODULE_FIRMWARE(FW_FILE_ISP22XX); | |
6098 | MODULE_FIRMWARE(FW_FILE_ISP2300); | |
6099 | MODULE_FIRMWARE(FW_FILE_ISP2322); | |
6100 | MODULE_FIRMWARE(FW_FILE_ISP24XX); | |
61623fc3 | 6101 | MODULE_FIRMWARE(FW_FILE_ISP25XX); |