Commit | Line | Data |
---|---|---|
fa90c54f AV |
1 | /* |
2 | * QLogic Fibre Channel HBA Driver | |
01e58d8e | 3 | * Copyright (c) 2003-2008 QLogic Corporation |
1da177e4 | 4 | * |
fa90c54f AV |
5 | * See LICENSE.qla2xxx for copyright and licensing details. |
6 | */ | |
1da177e4 LT |
7 | #include "qla_def.h" |
8 | ||
9 | #include <linux/delay.h> | |
2c96d8d0 | 10 | #include <linux/vmalloc.h> |
1da177e4 LT |
11 | #include <asm/uaccess.h> |
12 | ||
13 | static uint16_t qla2x00_nvram_request(scsi_qla_host_t *, uint32_t); | |
14 | static void qla2x00_nv_deselect(scsi_qla_host_t *); | |
15 | static void qla2x00_nv_write(scsi_qla_host_t *, uint16_t); | |
16 | ||
17 | /* | |
18 | * NVRAM support routines | |
19 | */ | |
20 | ||
21 | /** | |
fa2a1ce5 | 22 | * qla2x00_lock_nvram_access() - |
1da177e4 LT |
23 | * @ha: HA context |
24 | */ | |
a824ebb3 | 25 | static void |
1da177e4 LT |
26 | qla2x00_lock_nvram_access(scsi_qla_host_t *ha) |
27 | { | |
28 | uint16_t data; | |
3d71644c | 29 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 LT |
30 | |
31 | if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) { | |
32 | data = RD_REG_WORD(®->nvram); | |
33 | while (data & NVR_BUSY) { | |
34 | udelay(100); | |
35 | data = RD_REG_WORD(®->nvram); | |
36 | } | |
37 | ||
38 | /* Lock resource */ | |
39 | WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1); | |
40 | RD_REG_WORD(®->u.isp2300.host_semaphore); | |
41 | udelay(5); | |
42 | data = RD_REG_WORD(®->u.isp2300.host_semaphore); | |
43 | while ((data & BIT_0) == 0) { | |
44 | /* Lock failed */ | |
45 | udelay(100); | |
46 | WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1); | |
47 | RD_REG_WORD(®->u.isp2300.host_semaphore); | |
48 | udelay(5); | |
49 | data = RD_REG_WORD(®->u.isp2300.host_semaphore); | |
50 | } | |
51 | } | |
52 | } | |
53 | ||
54 | /** | |
fa2a1ce5 | 55 | * qla2x00_unlock_nvram_access() - |
1da177e4 LT |
56 | * @ha: HA context |
57 | */ | |
a824ebb3 | 58 | static void |
1da177e4 LT |
59 | qla2x00_unlock_nvram_access(scsi_qla_host_t *ha) |
60 | { | |
3d71644c | 61 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 LT |
62 | |
63 | if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) { | |
64 | WRT_REG_WORD(®->u.isp2300.host_semaphore, 0); | |
65 | RD_REG_WORD(®->u.isp2300.host_semaphore); | |
66 | } | |
67 | } | |
68 | ||
1da177e4 LT |
69 | /** |
70 | * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the | |
71 | * request routine to get the word from NVRAM. | |
72 | * @ha: HA context | |
73 | * @addr: Address in NVRAM to read | |
74 | * | |
75 | * Returns the word read from nvram @addr. | |
76 | */ | |
a824ebb3 | 77 | static uint16_t |
1da177e4 LT |
78 | qla2x00_get_nvram_word(scsi_qla_host_t *ha, uint32_t addr) |
79 | { | |
80 | uint16_t data; | |
81 | uint32_t nv_cmd; | |
82 | ||
83 | nv_cmd = addr << 16; | |
84 | nv_cmd |= NV_READ_OP; | |
85 | data = qla2x00_nvram_request(ha, nv_cmd); | |
86 | ||
87 | return (data); | |
88 | } | |
89 | ||
90 | /** | |
91 | * qla2x00_write_nvram_word() - Write NVRAM data. | |
92 | * @ha: HA context | |
93 | * @addr: Address in NVRAM to write | |
94 | * @data: word to program | |
95 | */ | |
a824ebb3 | 96 | static void |
1da177e4 LT |
97 | qla2x00_write_nvram_word(scsi_qla_host_t *ha, uint32_t addr, uint16_t data) |
98 | { | |
99 | int count; | |
100 | uint16_t word; | |
45aeaf1e | 101 | uint32_t nv_cmd, wait_cnt; |
3d71644c | 102 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 LT |
103 | |
104 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
105 | qla2x00_nv_write(ha, 0); | |
106 | qla2x00_nv_write(ha, 0); | |
107 | ||
108 | for (word = 0; word < 8; word++) | |
109 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
110 | ||
111 | qla2x00_nv_deselect(ha); | |
112 | ||
113 | /* Write data */ | |
114 | nv_cmd = (addr << 16) | NV_WRITE_OP; | |
115 | nv_cmd |= data; | |
116 | nv_cmd <<= 5; | |
117 | for (count = 0; count < 27; count++) { | |
118 | if (nv_cmd & BIT_31) | |
119 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
120 | else | |
121 | qla2x00_nv_write(ha, 0); | |
122 | ||
123 | nv_cmd <<= 1; | |
124 | } | |
125 | ||
126 | qla2x00_nv_deselect(ha); | |
127 | ||
128 | /* Wait for NVRAM to become ready */ | |
129 | WRT_REG_WORD(®->nvram, NVR_SELECT); | |
dcb36ce9 | 130 | RD_REG_WORD(®->nvram); /* PCI Posting. */ |
45aeaf1e | 131 | wait_cnt = NVR_WAIT_CNT; |
1da177e4 | 132 | do { |
45aeaf1e RA |
133 | if (!--wait_cnt) { |
134 | DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n", | |
135 | __func__, ha->host_no)); | |
136 | break; | |
137 | } | |
1da177e4 LT |
138 | NVRAM_DELAY(); |
139 | word = RD_REG_WORD(®->nvram); | |
140 | } while ((word & NVR_DATA_IN) == 0); | |
141 | ||
142 | qla2x00_nv_deselect(ha); | |
143 | ||
144 | /* Disable writes */ | |
145 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
146 | for (count = 0; count < 10; count++) | |
147 | qla2x00_nv_write(ha, 0); | |
148 | ||
149 | qla2x00_nv_deselect(ha); | |
150 | } | |
151 | ||
459c5378 AV |
152 | static int |
153 | qla2x00_write_nvram_word_tmo(scsi_qla_host_t *ha, uint32_t addr, uint16_t data, | |
154 | uint32_t tmo) | |
155 | { | |
156 | int ret, count; | |
157 | uint16_t word; | |
158 | uint32_t nv_cmd; | |
159 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
160 | ||
161 | ret = QLA_SUCCESS; | |
162 | ||
163 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
164 | qla2x00_nv_write(ha, 0); | |
165 | qla2x00_nv_write(ha, 0); | |
166 | ||
167 | for (word = 0; word < 8; word++) | |
168 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
169 | ||
170 | qla2x00_nv_deselect(ha); | |
171 | ||
172 | /* Write data */ | |
173 | nv_cmd = (addr << 16) | NV_WRITE_OP; | |
174 | nv_cmd |= data; | |
175 | nv_cmd <<= 5; | |
176 | for (count = 0; count < 27; count++) { | |
177 | if (nv_cmd & BIT_31) | |
178 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
179 | else | |
180 | qla2x00_nv_write(ha, 0); | |
181 | ||
182 | nv_cmd <<= 1; | |
183 | } | |
184 | ||
185 | qla2x00_nv_deselect(ha); | |
186 | ||
187 | /* Wait for NVRAM to become ready */ | |
188 | WRT_REG_WORD(®->nvram, NVR_SELECT); | |
dcb36ce9 | 189 | RD_REG_WORD(®->nvram); /* PCI Posting. */ |
459c5378 AV |
190 | do { |
191 | NVRAM_DELAY(); | |
192 | word = RD_REG_WORD(®->nvram); | |
193 | if (!--tmo) { | |
194 | ret = QLA_FUNCTION_FAILED; | |
195 | break; | |
196 | } | |
197 | } while ((word & NVR_DATA_IN) == 0); | |
198 | ||
199 | qla2x00_nv_deselect(ha); | |
200 | ||
201 | /* Disable writes */ | |
202 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
203 | for (count = 0; count < 10; count++) | |
204 | qla2x00_nv_write(ha, 0); | |
205 | ||
206 | qla2x00_nv_deselect(ha); | |
207 | ||
208 | return ret; | |
209 | } | |
210 | ||
1da177e4 LT |
211 | /** |
212 | * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from | |
213 | * NVRAM. | |
214 | * @ha: HA context | |
215 | * @nv_cmd: NVRAM command | |
216 | * | |
217 | * Bit definitions for NVRAM command: | |
218 | * | |
219 | * Bit 26 = start bit | |
220 | * Bit 25, 24 = opcode | |
221 | * Bit 23-16 = address | |
222 | * Bit 15-0 = write data | |
223 | * | |
224 | * Returns the word read from nvram @addr. | |
225 | */ | |
226 | static uint16_t | |
227 | qla2x00_nvram_request(scsi_qla_host_t *ha, uint32_t nv_cmd) | |
228 | { | |
229 | uint8_t cnt; | |
3d71644c | 230 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 LT |
231 | uint16_t data = 0; |
232 | uint16_t reg_data; | |
233 | ||
234 | /* Send command to NVRAM. */ | |
235 | nv_cmd <<= 5; | |
236 | for (cnt = 0; cnt < 11; cnt++) { | |
237 | if (nv_cmd & BIT_31) | |
238 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
239 | else | |
240 | qla2x00_nv_write(ha, 0); | |
241 | nv_cmd <<= 1; | |
242 | } | |
243 | ||
244 | /* Read data from NVRAM. */ | |
245 | for (cnt = 0; cnt < 16; cnt++) { | |
246 | WRT_REG_WORD(®->nvram, NVR_SELECT | NVR_CLOCK); | |
dcb36ce9 | 247 | RD_REG_WORD(®->nvram); /* PCI Posting. */ |
1da177e4 LT |
248 | NVRAM_DELAY(); |
249 | data <<= 1; | |
250 | reg_data = RD_REG_WORD(®->nvram); | |
251 | if (reg_data & NVR_DATA_IN) | |
252 | data |= BIT_0; | |
253 | WRT_REG_WORD(®->nvram, NVR_SELECT); | |
254 | RD_REG_WORD(®->nvram); /* PCI Posting. */ | |
255 | NVRAM_DELAY(); | |
256 | } | |
257 | ||
258 | /* Deselect chip. */ | |
259 | WRT_REG_WORD(®->nvram, NVR_DESELECT); | |
260 | RD_REG_WORD(®->nvram); /* PCI Posting. */ | |
261 | NVRAM_DELAY(); | |
262 | ||
263 | return (data); | |
264 | } | |
265 | ||
266 | /** | |
267 | * qla2x00_nv_write() - Clean NVRAM operations. | |
268 | * @ha: HA context | |
269 | */ | |
270 | static void | |
271 | qla2x00_nv_deselect(scsi_qla_host_t *ha) | |
272 | { | |
3d71644c | 273 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 LT |
274 | |
275 | WRT_REG_WORD(®->nvram, NVR_DESELECT); | |
276 | RD_REG_WORD(®->nvram); /* PCI Posting. */ | |
277 | NVRAM_DELAY(); | |
278 | } | |
279 | ||
280 | /** | |
281 | * qla2x00_nv_write() - Prepare for NVRAM read/write operation. | |
282 | * @ha: HA context | |
283 | * @data: Serial interface selector | |
284 | */ | |
285 | static void | |
286 | qla2x00_nv_write(scsi_qla_host_t *ha, uint16_t data) | |
287 | { | |
3d71644c | 288 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 LT |
289 | |
290 | WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); | |
291 | RD_REG_WORD(®->nvram); /* PCI Posting. */ | |
292 | NVRAM_DELAY(); | |
293 | WRT_REG_WORD(®->nvram, data | NVR_SELECT| NVR_CLOCK | | |
294 | NVR_WRT_ENABLE); | |
295 | RD_REG_WORD(®->nvram); /* PCI Posting. */ | |
296 | NVRAM_DELAY(); | |
297 | WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); | |
298 | RD_REG_WORD(®->nvram); /* PCI Posting. */ | |
299 | NVRAM_DELAY(); | |
300 | } | |
301 | ||
459c5378 AV |
302 | /** |
303 | * qla2x00_clear_nvram_protection() - | |
304 | * @ha: HA context | |
305 | */ | |
306 | static int | |
307 | qla2x00_clear_nvram_protection(scsi_qla_host_t *ha) | |
308 | { | |
309 | int ret, stat; | |
310 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
45aeaf1e | 311 | uint32_t word, wait_cnt; |
459c5378 AV |
312 | uint16_t wprot, wprot_old; |
313 | ||
314 | /* Clear NVRAM write protection. */ | |
315 | ret = QLA_FUNCTION_FAILED; | |
45aeaf1e RA |
316 | |
317 | wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base)); | |
318 | stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base, | |
459c5378 | 319 | __constant_cpu_to_le16(0x1234), 100000); |
45aeaf1e RA |
320 | wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base)); |
321 | if (stat != QLA_SUCCESS || wprot != 0x1234) { | |
459c5378 AV |
322 | /* Write enable. */ |
323 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
324 | qla2x00_nv_write(ha, 0); | |
325 | qla2x00_nv_write(ha, 0); | |
326 | for (word = 0; word < 8; word++) | |
327 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
328 | ||
329 | qla2x00_nv_deselect(ha); | |
330 | ||
331 | /* Enable protection register. */ | |
332 | qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); | |
333 | qla2x00_nv_write(ha, NVR_PR_ENABLE); | |
334 | qla2x00_nv_write(ha, NVR_PR_ENABLE); | |
335 | for (word = 0; word < 8; word++) | |
336 | qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); | |
337 | ||
338 | qla2x00_nv_deselect(ha); | |
339 | ||
340 | /* Clear protection register (ffff is cleared). */ | |
341 | qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); | |
342 | qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); | |
343 | qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); | |
344 | for (word = 0; word < 8; word++) | |
345 | qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); | |
346 | ||
347 | qla2x00_nv_deselect(ha); | |
348 | ||
349 | /* Wait for NVRAM to become ready. */ | |
350 | WRT_REG_WORD(®->nvram, NVR_SELECT); | |
dcb36ce9 | 351 | RD_REG_WORD(®->nvram); /* PCI Posting. */ |
45aeaf1e | 352 | wait_cnt = NVR_WAIT_CNT; |
459c5378 | 353 | do { |
45aeaf1e RA |
354 | if (!--wait_cnt) { |
355 | DEBUG9_10(printk("%s(%ld): NVRAM didn't go " | |
356 | "ready...\n", __func__, | |
357 | ha->host_no)); | |
358 | break; | |
359 | } | |
459c5378 AV |
360 | NVRAM_DELAY(); |
361 | word = RD_REG_WORD(®->nvram); | |
362 | } while ((word & NVR_DATA_IN) == 0); | |
363 | ||
45aeaf1e RA |
364 | if (wait_cnt) |
365 | ret = QLA_SUCCESS; | |
459c5378 | 366 | } else |
45aeaf1e | 367 | qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old); |
459c5378 AV |
368 | |
369 | return ret; | |
370 | } | |
371 | ||
372 | static void | |
373 | qla2x00_set_nvram_protection(scsi_qla_host_t *ha, int stat) | |
374 | { | |
375 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
45aeaf1e | 376 | uint32_t word, wait_cnt; |
459c5378 AV |
377 | |
378 | if (stat != QLA_SUCCESS) | |
379 | return; | |
380 | ||
381 | /* Set NVRAM write protection. */ | |
382 | /* Write enable. */ | |
383 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
384 | qla2x00_nv_write(ha, 0); | |
385 | qla2x00_nv_write(ha, 0); | |
386 | for (word = 0; word < 8; word++) | |
387 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
388 | ||
389 | qla2x00_nv_deselect(ha); | |
390 | ||
391 | /* Enable protection register. */ | |
392 | qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); | |
393 | qla2x00_nv_write(ha, NVR_PR_ENABLE); | |
394 | qla2x00_nv_write(ha, NVR_PR_ENABLE); | |
395 | for (word = 0; word < 8; word++) | |
396 | qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); | |
397 | ||
398 | qla2x00_nv_deselect(ha); | |
399 | ||
400 | /* Enable protection register. */ | |
401 | qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); | |
402 | qla2x00_nv_write(ha, NVR_PR_ENABLE); | |
403 | qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); | |
404 | for (word = 0; word < 8; word++) | |
405 | qla2x00_nv_write(ha, NVR_PR_ENABLE); | |
406 | ||
407 | qla2x00_nv_deselect(ha); | |
408 | ||
409 | /* Wait for NVRAM to become ready. */ | |
410 | WRT_REG_WORD(®->nvram, NVR_SELECT); | |
dcb36ce9 | 411 | RD_REG_WORD(®->nvram); /* PCI Posting. */ |
45aeaf1e | 412 | wait_cnt = NVR_WAIT_CNT; |
459c5378 | 413 | do { |
45aeaf1e RA |
414 | if (!--wait_cnt) { |
415 | DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n", | |
416 | __func__, ha->host_no)); | |
417 | break; | |
418 | } | |
459c5378 AV |
419 | NVRAM_DELAY(); |
420 | word = RD_REG_WORD(®->nvram); | |
421 | } while ((word & NVR_DATA_IN) == 0); | |
422 | } | |
423 | ||
424 | ||
425 | /*****************************************************************************/ | |
426 | /* Flash Manipulation Routines */ | |
427 | /*****************************************************************************/ | |
428 | ||
338c9161 AV |
429 | #define OPTROM_BURST_SIZE 0x1000 |
430 | #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) | |
431 | ||
459c5378 AV |
432 | static inline uint32_t |
433 | flash_conf_to_access_addr(uint32_t faddr) | |
434 | { | |
435 | return FARX_ACCESS_FLASH_CONF | faddr; | |
436 | } | |
437 | ||
438 | static inline uint32_t | |
439 | flash_data_to_access_addr(uint32_t faddr) | |
440 | { | |
441 | return FARX_ACCESS_FLASH_DATA | faddr; | |
442 | } | |
443 | ||
444 | static inline uint32_t | |
445 | nvram_conf_to_access_addr(uint32_t naddr) | |
446 | { | |
447 | return FARX_ACCESS_NVRAM_CONF | naddr; | |
448 | } | |
449 | ||
450 | static inline uint32_t | |
451 | nvram_data_to_access_addr(uint32_t naddr) | |
452 | { | |
453 | return FARX_ACCESS_NVRAM_DATA | naddr; | |
454 | } | |
455 | ||
e5f82ab8 | 456 | static uint32_t |
459c5378 AV |
457 | qla24xx_read_flash_dword(scsi_qla_host_t *ha, uint32_t addr) |
458 | { | |
459 | int rval; | |
460 | uint32_t cnt, data; | |
461 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
462 | ||
463 | WRT_REG_DWORD(®->flash_addr, addr & ~FARX_DATA_FLAG); | |
464 | /* Wait for READ cycle to complete. */ | |
465 | rval = QLA_SUCCESS; | |
466 | for (cnt = 3000; | |
467 | (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) == 0 && | |
468 | rval == QLA_SUCCESS; cnt--) { | |
469 | if (cnt) | |
470 | udelay(10); | |
471 | else | |
472 | rval = QLA_FUNCTION_TIMEOUT; | |
40a2e34a | 473 | cond_resched(); |
459c5378 AV |
474 | } |
475 | ||
476 | /* TODO: What happens if we time out? */ | |
477 | data = 0xDEADDEAD; | |
478 | if (rval == QLA_SUCCESS) | |
479 | data = RD_REG_DWORD(®->flash_data); | |
480 | ||
481 | return data; | |
482 | } | |
483 | ||
484 | uint32_t * | |
485 | qla24xx_read_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr, | |
486 | uint32_t dwords) | |
487 | { | |
488 | uint32_t i; | |
459c5378 AV |
489 | |
490 | /* Dword reads to flash. */ | |
491 | for (i = 0; i < dwords; i++, faddr++) | |
492 | dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha, | |
493 | flash_data_to_access_addr(faddr))); | |
494 | ||
459c5378 AV |
495 | return dwptr; |
496 | } | |
497 | ||
e5f82ab8 | 498 | static int |
459c5378 AV |
499 | qla24xx_write_flash_dword(scsi_qla_host_t *ha, uint32_t addr, uint32_t data) |
500 | { | |
501 | int rval; | |
502 | uint32_t cnt; | |
503 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
504 | ||
505 | WRT_REG_DWORD(®->flash_data, data); | |
506 | RD_REG_DWORD(®->flash_data); /* PCI Posting. */ | |
507 | WRT_REG_DWORD(®->flash_addr, addr | FARX_DATA_FLAG); | |
508 | /* Wait for Write cycle to complete. */ | |
509 | rval = QLA_SUCCESS; | |
510 | for (cnt = 500000; (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) && | |
511 | rval == QLA_SUCCESS; cnt--) { | |
512 | if (cnt) | |
513 | udelay(10); | |
514 | else | |
515 | rval = QLA_FUNCTION_TIMEOUT; | |
40a2e34a | 516 | cond_resched(); |
459c5378 AV |
517 | } |
518 | return rval; | |
519 | } | |
520 | ||
e5f82ab8 | 521 | static void |
459c5378 AV |
522 | qla24xx_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id, |
523 | uint8_t *flash_id) | |
524 | { | |
525 | uint32_t ids; | |
526 | ||
527 | ids = qla24xx_read_flash_dword(ha, flash_data_to_access_addr(0xd03ab)); | |
528 | *man_id = LSB(ids); | |
529 | *flash_id = MSB(ids); | |
45aeaf1e RA |
530 | |
531 | /* Check if man_id and flash_id are valid. */ | |
532 | if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) { | |
533 | /* Read information using 0x9f opcode | |
534 | * Device ID, Mfg ID would be read in the format: | |
535 | * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID> | |
536 | * Example: ATMEL 0x00 01 45 1F | |
537 | * Extract MFG and Dev ID from last two bytes. | |
538 | */ | |
539 | ids = qla24xx_read_flash_dword(ha, | |
540 | flash_data_to_access_addr(0xd009f)); | |
541 | *man_id = LSB(ids); | |
542 | *flash_id = MSB(ids); | |
543 | } | |
459c5378 AV |
544 | } |
545 | ||
e5f82ab8 | 546 | static int |
459c5378 AV |
547 | qla24xx_write_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr, |
548 | uint32_t dwords) | |
549 | { | |
550 | int ret; | |
338c9161 AV |
551 | uint32_t liter, miter; |
552 | uint32_t sec_mask, rest_addr, conf_addr; | |
6f13fd57 | 553 | uint32_t fdata, findex, cnt; |
459c5378 AV |
554 | uint8_t man_id, flash_id; |
555 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
338c9161 AV |
556 | dma_addr_t optrom_dma; |
557 | void *optrom = NULL; | |
558 | uint32_t *s, *d; | |
459c5378 AV |
559 | |
560 | ret = QLA_SUCCESS; | |
561 | ||
338c9161 | 562 | /* Prepare burst-capable write on supported ISPs. */ |
b7cc176c | 563 | if (IS_QLA25XX(ha) && !(faddr & 0xfff) && |
338c9161 AV |
564 | dwords > OPTROM_BURST_DWORDS) { |
565 | optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, | |
566 | &optrom_dma, GFP_KERNEL); | |
567 | if (!optrom) { | |
568 | qla_printk(KERN_DEBUG, ha, | |
569 | "Unable to allocate memory for optrom burst write " | |
570 | "(%x KB).\n", OPTROM_BURST_SIZE / 1024); | |
571 | } | |
572 | } | |
573 | ||
459c5378 AV |
574 | qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id); |
575 | DEBUG9(printk("%s(%ld): Flash man_id=%d flash_id=%d\n", __func__, | |
576 | ha->host_no, man_id, flash_id)); | |
577 | ||
578 | conf_addr = flash_conf_to_access_addr(0x03d8); | |
579 | switch (man_id) { | |
fa2a1ce5 | 580 | case 0xbf: /* STT flash. */ |
338c9161 AV |
581 | if (flash_id == 0x8e) { |
582 | rest_addr = 0x3fff; | |
583 | sec_mask = 0x7c000; | |
584 | } else { | |
585 | rest_addr = 0x1fff; | |
586 | sec_mask = 0x7e000; | |
587 | } | |
459c5378 AV |
588 | if (flash_id == 0x80) |
589 | conf_addr = flash_conf_to_access_addr(0x0352); | |
590 | break; | |
fa2a1ce5 | 591 | case 0x13: /* ST M25P80. */ |
459c5378 | 592 | rest_addr = 0x3fff; |
338c9161 | 593 | sec_mask = 0x7c000; |
459c5378 | 594 | break; |
45aeaf1e | 595 | case 0x1f: // Atmel 26DF081A |
338c9161 AV |
596 | rest_addr = 0x3fff; |
597 | sec_mask = 0x7c000; | |
45aeaf1e RA |
598 | conf_addr = flash_conf_to_access_addr(0x0320); |
599 | break; | |
459c5378 | 600 | default: |
fa2a1ce5 | 601 | /* Default to 64 kb sector size. */ |
459c5378 | 602 | rest_addr = 0x3fff; |
338c9161 | 603 | sec_mask = 0x7c000; |
459c5378 AV |
604 | break; |
605 | } | |
606 | ||
607 | /* Enable flash write. */ | |
608 | WRT_REG_DWORD(®->ctrl_status, | |
609 | RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE); | |
610 | RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ | |
611 | ||
612 | /* Disable flash write-protection. */ | |
613 | qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0); | |
45aeaf1e RA |
614 | /* Some flash parts need an additional zero-write to clear bits.*/ |
615 | qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0); | |
459c5378 | 616 | |
338c9161 AV |
617 | for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) { |
618 | if (man_id == 0x1f) { | |
619 | findex = faddr << 2; | |
620 | fdata = findex & sec_mask; | |
621 | } else { | |
622 | findex = faddr; | |
623 | fdata = (findex & sec_mask) << 2; | |
624 | } | |
45aeaf1e | 625 | |
338c9161 AV |
626 | /* Are we at the beginning of a sector? */ |
627 | if ((findex & rest_addr) == 0) { | |
628 | /* Do sector unprotect at 4K boundry for Atmel part. */ | |
629 | if (man_id == 0x1f) | |
630 | qla24xx_write_flash_dword(ha, | |
631 | flash_conf_to_access_addr(0x0339), | |
632 | (fdata & 0xff00) | ((fdata << 16) & | |
459c5378 | 633 | 0xff0000) | ((fdata >> 16) & 0xff)); |
338c9161 AV |
634 | ret = qla24xx_write_flash_dword(ha, conf_addr, |
635 | (fdata & 0xff00) |((fdata << 16) & | |
636 | 0xff0000) | ((fdata >> 16) & 0xff)); | |
637 | if (ret != QLA_SUCCESS) { | |
638 | DEBUG9(printk("%s(%ld) Unable to flash " | |
639 | "sector: address=%x.\n", __func__, | |
640 | ha->host_no, faddr)); | |
641 | break; | |
459c5378 | 642 | } |
338c9161 AV |
643 | } |
644 | ||
645 | /* Go with burst-write. */ | |
94d6a2b3 | 646 | if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) { |
338c9161 AV |
647 | /* Copy data to DMA'ble buffer. */ |
648 | for (miter = 0, s = optrom, d = dwptr; | |
649 | miter < OPTROM_BURST_DWORDS; miter++, s++, d++) | |
650 | *s = cpu_to_le32(*d); | |
651 | ||
652 | ret = qla2x00_load_ram(ha, optrom_dma, | |
459c5378 | 653 | flash_data_to_access_addr(faddr), |
338c9161 | 654 | OPTROM_BURST_DWORDS); |
459c5378 | 655 | if (ret != QLA_SUCCESS) { |
338c9161 AV |
656 | qla_printk(KERN_WARNING, ha, |
657 | "Unable to burst-write optrom segment " | |
658 | "(%x/%x/%llx).\n", ret, | |
659 | flash_data_to_access_addr(faddr), | |
875baf3c | 660 | (unsigned long long)optrom_dma); |
338c9161 AV |
661 | qla_printk(KERN_WARNING, ha, |
662 | "Reverting to slow-write.\n"); | |
663 | ||
664 | dma_free_coherent(&ha->pdev->dev, | |
665 | OPTROM_BURST_SIZE, optrom, optrom_dma); | |
666 | optrom = NULL; | |
667 | } else { | |
668 | liter += OPTROM_BURST_DWORDS - 1; | |
669 | faddr += OPTROM_BURST_DWORDS - 1; | |
670 | dwptr += OPTROM_BURST_DWORDS - 1; | |
671 | continue; | |
459c5378 | 672 | } |
338c9161 | 673 | } |
45aeaf1e | 674 | |
338c9161 AV |
675 | ret = qla24xx_write_flash_dword(ha, |
676 | flash_data_to_access_addr(faddr), cpu_to_le32(*dwptr)); | |
677 | if (ret != QLA_SUCCESS) { | |
678 | DEBUG9(printk("%s(%ld) Unable to program flash " | |
679 | "address=%x data=%x.\n", __func__, | |
680 | ha->host_no, faddr, *dwptr)); | |
681 | break; | |
459c5378 | 682 | } |
338c9161 AV |
683 | |
684 | /* Do sector protect at 4K boundry for Atmel part. */ | |
685 | if (man_id == 0x1f && | |
686 | ((faddr & rest_addr) == rest_addr)) | |
687 | qla24xx_write_flash_dword(ha, | |
688 | flash_conf_to_access_addr(0x0336), | |
689 | (fdata & 0xff00) | ((fdata << 16) & | |
690 | 0xff0000) | ((fdata >> 16) & 0xff)); | |
691 | } | |
459c5378 | 692 | |
6f13fd57 | 693 | /* Enable flash write-protection and wait for completion. */ |
e978010c | 694 | qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0x9c); |
6f13fd57 AV |
695 | for (cnt = 300; cnt && |
696 | qla24xx_read_flash_dword(ha, | |
697 | flash_conf_to_access_addr(0x005)) & BIT_0; | |
698 | cnt--) { | |
699 | udelay(10); | |
700 | } | |
e978010c | 701 | |
459c5378 AV |
702 | /* Disable flash write. */ |
703 | WRT_REG_DWORD(®->ctrl_status, | |
704 | RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE); | |
705 | RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ | |
706 | ||
338c9161 AV |
707 | if (optrom) |
708 | dma_free_coherent(&ha->pdev->dev, | |
709 | OPTROM_BURST_SIZE, optrom, optrom_dma); | |
710 | ||
459c5378 AV |
711 | return ret; |
712 | } | |
713 | ||
714 | uint8_t * | |
715 | qla2x00_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, | |
716 | uint32_t bytes) | |
717 | { | |
718 | uint32_t i; | |
719 | uint16_t *wptr; | |
720 | ||
721 | /* Word reads to NVRAM via registers. */ | |
722 | wptr = (uint16_t *)buf; | |
723 | qla2x00_lock_nvram_access(ha); | |
724 | for (i = 0; i < bytes >> 1; i++, naddr++) | |
725 | wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha, | |
726 | naddr)); | |
727 | qla2x00_unlock_nvram_access(ha); | |
728 | ||
729 | return buf; | |
730 | } | |
731 | ||
732 | uint8_t * | |
733 | qla24xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, | |
734 | uint32_t bytes) | |
735 | { | |
736 | uint32_t i; | |
737 | uint32_t *dwptr; | |
459c5378 AV |
738 | |
739 | /* Dword reads to flash. */ | |
740 | dwptr = (uint32_t *)buf; | |
741 | for (i = 0; i < bytes >> 2; i++, naddr++) | |
742 | dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha, | |
743 | nvram_data_to_access_addr(naddr))); | |
744 | ||
459c5378 AV |
745 | return buf; |
746 | } | |
747 | ||
748 | int | |
749 | qla2x00_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, | |
750 | uint32_t bytes) | |
751 | { | |
752 | int ret, stat; | |
753 | uint32_t i; | |
754 | uint16_t *wptr; | |
2c96d8d0 | 755 | unsigned long flags; |
459c5378 AV |
756 | |
757 | ret = QLA_SUCCESS; | |
758 | ||
2c96d8d0 | 759 | spin_lock_irqsave(&ha->hardware_lock, flags); |
459c5378 AV |
760 | qla2x00_lock_nvram_access(ha); |
761 | ||
762 | /* Disable NVRAM write-protection. */ | |
763 | stat = qla2x00_clear_nvram_protection(ha); | |
764 | ||
765 | wptr = (uint16_t *)buf; | |
766 | for (i = 0; i < bytes >> 1; i++, naddr++) { | |
767 | qla2x00_write_nvram_word(ha, naddr, | |
768 | cpu_to_le16(*wptr)); | |
769 | wptr++; | |
770 | } | |
771 | ||
772 | /* Enable NVRAM write-protection. */ | |
773 | qla2x00_set_nvram_protection(ha, stat); | |
774 | ||
775 | qla2x00_unlock_nvram_access(ha); | |
2c96d8d0 | 776 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
459c5378 AV |
777 | |
778 | return ret; | |
779 | } | |
780 | ||
781 | int | |
782 | qla24xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, | |
783 | uint32_t bytes) | |
784 | { | |
785 | int ret; | |
786 | uint32_t i; | |
787 | uint32_t *dwptr; | |
788 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
2c96d8d0 | 789 | unsigned long flags; |
459c5378 AV |
790 | |
791 | ret = QLA_SUCCESS; | |
792 | ||
2c96d8d0 | 793 | spin_lock_irqsave(&ha->hardware_lock, flags); |
459c5378 AV |
794 | /* Enable flash write. */ |
795 | WRT_REG_DWORD(®->ctrl_status, | |
796 | RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE); | |
797 | RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ | |
798 | ||
799 | /* Disable NVRAM write-protection. */ | |
800 | qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101), | |
801 | 0); | |
802 | qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101), | |
803 | 0); | |
804 | ||
805 | /* Dword writes to flash. */ | |
806 | dwptr = (uint32_t *)buf; | |
807 | for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) { | |
808 | ret = qla24xx_write_flash_dword(ha, | |
809 | nvram_data_to_access_addr(naddr), | |
810 | cpu_to_le32(*dwptr)); | |
811 | if (ret != QLA_SUCCESS) { | |
812 | DEBUG9(printk("%s(%ld) Unable to program " | |
813 | "nvram address=%x data=%x.\n", __func__, | |
814 | ha->host_no, naddr, *dwptr)); | |
815 | break; | |
816 | } | |
817 | } | |
818 | ||
819 | /* Enable NVRAM write-protection. */ | |
820 | qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101), | |
821 | 0x8c); | |
822 | ||
823 | /* Disable flash write. */ | |
824 | WRT_REG_DWORD(®->ctrl_status, | |
825 | RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE); | |
826 | RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ | |
2c96d8d0 | 827 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
459c5378 | 828 | |
459c5378 AV |
829 | return ret; |
830 | } | |
f6df144c | 831 | |
c3a2f0df AV |
832 | uint8_t * |
833 | qla25xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, | |
834 | uint32_t bytes) | |
835 | { | |
836 | uint32_t i; | |
837 | uint32_t *dwptr; | |
838 | ||
839 | /* Dword reads to flash. */ | |
840 | dwptr = (uint32_t *)buf; | |
841 | for (i = 0; i < bytes >> 2; i++, naddr++) | |
842 | dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha, | |
843 | flash_data_to_access_addr(FA_VPD_NVRAM_ADDR | naddr))); | |
844 | ||
845 | return buf; | |
846 | } | |
847 | ||
848 | int | |
849 | qla25xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, | |
850 | uint32_t bytes) | |
851 | { | |
2c96d8d0 AV |
852 | #define RMW_BUFFER_SIZE (64 * 1024) |
853 | uint8_t *dbuf; | |
854 | ||
855 | dbuf = vmalloc(RMW_BUFFER_SIZE); | |
856 | if (!dbuf) | |
857 | return QLA_MEMORY_ALLOC_FAILED; | |
858 | ha->isp_ops->read_optrom(ha, dbuf, FA_VPD_NVRAM_ADDR << 2, | |
859 | RMW_BUFFER_SIZE); | |
860 | memcpy(dbuf + (naddr << 2), buf, bytes); | |
861 | ha->isp_ops->write_optrom(ha, dbuf, FA_VPD_NVRAM_ADDR << 2, | |
862 | RMW_BUFFER_SIZE); | |
863 | vfree(dbuf); | |
864 | ||
865 | return QLA_SUCCESS; | |
c3a2f0df | 866 | } |
f6df144c | 867 | |
868 | static inline void | |
869 | qla2x00_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags) | |
870 | { | |
871 | if (IS_QLA2322(ha)) { | |
872 | /* Flip all colors. */ | |
873 | if (ha->beacon_color_state == QLA_LED_ALL_ON) { | |
874 | /* Turn off. */ | |
875 | ha->beacon_color_state = 0; | |
876 | *pflags = GPIO_LED_ALL_OFF; | |
877 | } else { | |
878 | /* Turn on. */ | |
879 | ha->beacon_color_state = QLA_LED_ALL_ON; | |
880 | *pflags = GPIO_LED_RGA_ON; | |
881 | } | |
882 | } else { | |
883 | /* Flip green led only. */ | |
884 | if (ha->beacon_color_state == QLA_LED_GRN_ON) { | |
885 | /* Turn off. */ | |
886 | ha->beacon_color_state = 0; | |
887 | *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF; | |
888 | } else { | |
889 | /* Turn on. */ | |
890 | ha->beacon_color_state = QLA_LED_GRN_ON; | |
891 | *pflags = GPIO_LED_GREEN_ON_AMBER_OFF; | |
892 | } | |
893 | } | |
894 | } | |
895 | ||
948882f6 AV |
896 | #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r)) |
897 | ||
f6df144c | 898 | void |
899 | qla2x00_beacon_blink(struct scsi_qla_host *ha) | |
900 | { | |
901 | uint16_t gpio_enable; | |
902 | uint16_t gpio_data; | |
903 | uint16_t led_color = 0; | |
904 | unsigned long flags; | |
905 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
906 | ||
f6df144c | 907 | spin_lock_irqsave(&ha->hardware_lock, flags); |
908 | ||
909 | /* Save the Original GPIOE. */ | |
910 | if (ha->pio_address) { | |
948882f6 AV |
911 | gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe)); |
912 | gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod)); | |
f6df144c | 913 | } else { |
914 | gpio_enable = RD_REG_WORD(®->gpioe); | |
915 | gpio_data = RD_REG_WORD(®->gpiod); | |
916 | } | |
917 | ||
918 | /* Set the modified gpio_enable values */ | |
919 | gpio_enable |= GPIO_LED_MASK; | |
920 | ||
921 | if (ha->pio_address) { | |
948882f6 | 922 | WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable); |
f6df144c | 923 | } else { |
924 | WRT_REG_WORD(®->gpioe, gpio_enable); | |
925 | RD_REG_WORD(®->gpioe); | |
926 | } | |
927 | ||
928 | qla2x00_flip_colors(ha, &led_color); | |
929 | ||
930 | /* Clear out any previously set LED color. */ | |
931 | gpio_data &= ~GPIO_LED_MASK; | |
932 | ||
933 | /* Set the new input LED color to GPIOD. */ | |
934 | gpio_data |= led_color; | |
935 | ||
936 | /* Set the modified gpio_data values */ | |
937 | if (ha->pio_address) { | |
948882f6 | 938 | WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data); |
f6df144c | 939 | } else { |
940 | WRT_REG_WORD(®->gpiod, gpio_data); | |
941 | RD_REG_WORD(®->gpiod); | |
942 | } | |
943 | ||
944 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
945 | } | |
946 | ||
947 | int | |
948 | qla2x00_beacon_on(struct scsi_qla_host *ha) | |
949 | { | |
950 | uint16_t gpio_enable; | |
951 | uint16_t gpio_data; | |
952 | unsigned long flags; | |
953 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
954 | ||
955 | ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; | |
956 | ha->fw_options[1] |= FO1_DISABLE_GPIO6_7; | |
957 | ||
958 | if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) { | |
959 | qla_printk(KERN_WARNING, ha, | |
960 | "Unable to update fw options (beacon on).\n"); | |
961 | return QLA_FUNCTION_FAILED; | |
962 | } | |
963 | ||
f6df144c | 964 | /* Turn off LEDs. */ |
965 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
966 | if (ha->pio_address) { | |
948882f6 AV |
967 | gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe)); |
968 | gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod)); | |
f6df144c | 969 | } else { |
970 | gpio_enable = RD_REG_WORD(®->gpioe); | |
971 | gpio_data = RD_REG_WORD(®->gpiod); | |
972 | } | |
973 | gpio_enable |= GPIO_LED_MASK; | |
974 | ||
975 | /* Set the modified gpio_enable values. */ | |
976 | if (ha->pio_address) { | |
948882f6 | 977 | WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable); |
f6df144c | 978 | } else { |
979 | WRT_REG_WORD(®->gpioe, gpio_enable); | |
980 | RD_REG_WORD(®->gpioe); | |
981 | } | |
982 | ||
983 | /* Clear out previously set LED colour. */ | |
984 | gpio_data &= ~GPIO_LED_MASK; | |
985 | if (ha->pio_address) { | |
948882f6 | 986 | WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data); |
f6df144c | 987 | } else { |
988 | WRT_REG_WORD(®->gpiod, gpio_data); | |
989 | RD_REG_WORD(®->gpiod); | |
990 | } | |
991 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
992 | ||
993 | /* | |
994 | * Let the per HBA timer kick off the blinking process based on | |
995 | * the following flags. No need to do anything else now. | |
996 | */ | |
997 | ha->beacon_blink_led = 1; | |
998 | ha->beacon_color_state = 0; | |
999 | ||
1000 | return QLA_SUCCESS; | |
1001 | } | |
1002 | ||
1003 | int | |
1004 | qla2x00_beacon_off(struct scsi_qla_host *ha) | |
1005 | { | |
1006 | int rval = QLA_SUCCESS; | |
1007 | ||
1008 | ha->beacon_blink_led = 0; | |
1009 | ||
1010 | /* Set the on flag so when it gets flipped it will be off. */ | |
1011 | if (IS_QLA2322(ha)) | |
1012 | ha->beacon_color_state = QLA_LED_ALL_ON; | |
1013 | else | |
1014 | ha->beacon_color_state = QLA_LED_GRN_ON; | |
1015 | ||
fd34f556 | 1016 | ha->isp_ops->beacon_blink(ha); /* This turns green LED off */ |
f6df144c | 1017 | |
1018 | ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; | |
1019 | ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7; | |
1020 | ||
1021 | rval = qla2x00_set_fw_options(ha, ha->fw_options); | |
1022 | if (rval != QLA_SUCCESS) | |
1023 | qla_printk(KERN_WARNING, ha, | |
1024 | "Unable to update fw options (beacon off).\n"); | |
1025 | return rval; | |
1026 | } | |
1027 | ||
1028 | ||
1029 | static inline void | |
1030 | qla24xx_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags) | |
1031 | { | |
1032 | /* Flip all colors. */ | |
1033 | if (ha->beacon_color_state == QLA_LED_ALL_ON) { | |
1034 | /* Turn off. */ | |
1035 | ha->beacon_color_state = 0; | |
1036 | *pflags = 0; | |
1037 | } else { | |
1038 | /* Turn on. */ | |
1039 | ha->beacon_color_state = QLA_LED_ALL_ON; | |
1040 | *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON; | |
1041 | } | |
1042 | } | |
1043 | ||
1044 | void | |
1045 | qla24xx_beacon_blink(struct scsi_qla_host *ha) | |
1046 | { | |
1047 | uint16_t led_color = 0; | |
1048 | uint32_t gpio_data; | |
1049 | unsigned long flags; | |
1050 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
1051 | ||
1052 | /* Save the Original GPIOD. */ | |
1053 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1054 | gpio_data = RD_REG_DWORD(®->gpiod); | |
1055 | ||
1056 | /* Enable the gpio_data reg for update. */ | |
1057 | gpio_data |= GPDX_LED_UPDATE_MASK; | |
1058 | ||
1059 | WRT_REG_DWORD(®->gpiod, gpio_data); | |
1060 | gpio_data = RD_REG_DWORD(®->gpiod); | |
1061 | ||
1062 | /* Set the color bits. */ | |
1063 | qla24xx_flip_colors(ha, &led_color); | |
1064 | ||
1065 | /* Clear out any previously set LED color. */ | |
1066 | gpio_data &= ~GPDX_LED_COLOR_MASK; | |
1067 | ||
1068 | /* Set the new input LED color to GPIOD. */ | |
1069 | gpio_data |= led_color; | |
1070 | ||
1071 | /* Set the modified gpio_data values. */ | |
1072 | WRT_REG_DWORD(®->gpiod, gpio_data); | |
1073 | gpio_data = RD_REG_DWORD(®->gpiod); | |
1074 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1075 | } | |
1076 | ||
1077 | int | |
1078 | qla24xx_beacon_on(struct scsi_qla_host *ha) | |
1079 | { | |
1080 | uint32_t gpio_data; | |
1081 | unsigned long flags; | |
1082 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
1083 | ||
1084 | if (ha->beacon_blink_led == 0) { | |
1085 | /* Enable firmware for update */ | |
1086 | ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL; | |
1087 | ||
1088 | if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) | |
1089 | return QLA_FUNCTION_FAILED; | |
1090 | ||
1091 | if (qla2x00_get_fw_options(ha, ha->fw_options) != | |
1092 | QLA_SUCCESS) { | |
1093 | qla_printk(KERN_WARNING, ha, | |
1094 | "Unable to update fw options (beacon on).\n"); | |
1095 | return QLA_FUNCTION_FAILED; | |
1096 | } | |
1097 | ||
1098 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1099 | gpio_data = RD_REG_DWORD(®->gpiod); | |
1100 | ||
1101 | /* Enable the gpio_data reg for update. */ | |
1102 | gpio_data |= GPDX_LED_UPDATE_MASK; | |
1103 | WRT_REG_DWORD(®->gpiod, gpio_data); | |
1104 | RD_REG_DWORD(®->gpiod); | |
1105 | ||
1106 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1107 | } | |
1108 | ||
1109 | /* So all colors blink together. */ | |
1110 | ha->beacon_color_state = 0; | |
1111 | ||
1112 | /* Let the per HBA timer kick off the blinking process. */ | |
1113 | ha->beacon_blink_led = 1; | |
1114 | ||
1115 | return QLA_SUCCESS; | |
1116 | } | |
1117 | ||
1118 | int | |
1119 | qla24xx_beacon_off(struct scsi_qla_host *ha) | |
1120 | { | |
1121 | uint32_t gpio_data; | |
1122 | unsigned long flags; | |
1123 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
1124 | ||
1125 | ha->beacon_blink_led = 0; | |
1126 | ha->beacon_color_state = QLA_LED_ALL_ON; | |
1127 | ||
fd34f556 | 1128 | ha->isp_ops->beacon_blink(ha); /* Will flip to all off. */ |
f6df144c | 1129 | |
1130 | /* Give control back to firmware. */ | |
1131 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1132 | gpio_data = RD_REG_DWORD(®->gpiod); | |
1133 | ||
1134 | /* Disable the gpio_data reg for update. */ | |
1135 | gpio_data &= ~GPDX_LED_UPDATE_MASK; | |
1136 | WRT_REG_DWORD(®->gpiod, gpio_data); | |
1137 | RD_REG_DWORD(®->gpiod); | |
1138 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1139 | ||
1140 | ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL; | |
1141 | ||
1142 | if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) { | |
1143 | qla_printk(KERN_WARNING, ha, | |
1144 | "Unable to update fw options (beacon off).\n"); | |
1145 | return QLA_FUNCTION_FAILED; | |
1146 | } | |
1147 | ||
1148 | if (qla2x00_get_fw_options(ha, ha->fw_options) != QLA_SUCCESS) { | |
1149 | qla_printk(KERN_WARNING, ha, | |
1150 | "Unable to get fw options (beacon off).\n"); | |
1151 | return QLA_FUNCTION_FAILED; | |
1152 | } | |
1153 | ||
1154 | return QLA_SUCCESS; | |
1155 | } | |
854165f4 | 1156 | |
1157 | ||
1158 | /* | |
1159 | * Flash support routines | |
1160 | */ | |
1161 | ||
1162 | /** | |
1163 | * qla2x00_flash_enable() - Setup flash for reading and writing. | |
1164 | * @ha: HA context | |
1165 | */ | |
1166 | static void | |
1167 | qla2x00_flash_enable(scsi_qla_host_t *ha) | |
1168 | { | |
1169 | uint16_t data; | |
1170 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
1171 | ||
1172 | data = RD_REG_WORD(®->ctrl_status); | |
1173 | data |= CSR_FLASH_ENABLE; | |
1174 | WRT_REG_WORD(®->ctrl_status, data); | |
1175 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1176 | } | |
1177 | ||
1178 | /** | |
1179 | * qla2x00_flash_disable() - Disable flash and allow RISC to run. | |
1180 | * @ha: HA context | |
1181 | */ | |
1182 | static void | |
1183 | qla2x00_flash_disable(scsi_qla_host_t *ha) | |
1184 | { | |
1185 | uint16_t data; | |
1186 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
1187 | ||
1188 | data = RD_REG_WORD(®->ctrl_status); | |
1189 | data &= ~(CSR_FLASH_ENABLE); | |
1190 | WRT_REG_WORD(®->ctrl_status, data); | |
1191 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1192 | } | |
1193 | ||
1194 | /** | |
1195 | * qla2x00_read_flash_byte() - Reads a byte from flash | |
1196 | * @ha: HA context | |
1197 | * @addr: Address in flash to read | |
1198 | * | |
1199 | * A word is read from the chip, but, only the lower byte is valid. | |
1200 | * | |
1201 | * Returns the byte read from flash @addr. | |
1202 | */ | |
1203 | static uint8_t | |
1204 | qla2x00_read_flash_byte(scsi_qla_host_t *ha, uint32_t addr) | |
1205 | { | |
1206 | uint16_t data; | |
1207 | uint16_t bank_select; | |
1208 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
1209 | ||
1210 | bank_select = RD_REG_WORD(®->ctrl_status); | |
1211 | ||
1212 | if (IS_QLA2322(ha) || IS_QLA6322(ha)) { | |
1213 | /* Specify 64K address range: */ | |
1214 | /* clear out Module Select and Flash Address bits [19:16]. */ | |
1215 | bank_select &= ~0xf8; | |
1216 | bank_select |= addr >> 12 & 0xf0; | |
1217 | bank_select |= CSR_FLASH_64K_BANK; | |
1218 | WRT_REG_WORD(®->ctrl_status, bank_select); | |
1219 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1220 | ||
1221 | WRT_REG_WORD(®->flash_address, (uint16_t)addr); | |
1222 | data = RD_REG_WORD(®->flash_data); | |
1223 | ||
1224 | return (uint8_t)data; | |
1225 | } | |
1226 | ||
1227 | /* Setup bit 16 of flash address. */ | |
1228 | if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) { | |
1229 | bank_select |= CSR_FLASH_64K_BANK; | |
1230 | WRT_REG_WORD(®->ctrl_status, bank_select); | |
1231 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1232 | } else if (((addr & BIT_16) == 0) && | |
1233 | (bank_select & CSR_FLASH_64K_BANK)) { | |
1234 | bank_select &= ~(CSR_FLASH_64K_BANK); | |
1235 | WRT_REG_WORD(®->ctrl_status, bank_select); | |
1236 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1237 | } | |
1238 | ||
1239 | /* Always perform IO mapped accesses to the FLASH registers. */ | |
1240 | if (ha->pio_address) { | |
1241 | uint16_t data2; | |
1242 | ||
948882f6 | 1243 | WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr); |
854165f4 | 1244 | do { |
948882f6 | 1245 | data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data)); |
854165f4 | 1246 | barrier(); |
1247 | cpu_relax(); | |
948882f6 | 1248 | data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data)); |
854165f4 | 1249 | } while (data != data2); |
1250 | } else { | |
1251 | WRT_REG_WORD(®->flash_address, (uint16_t)addr); | |
1252 | data = qla2x00_debounce_register(®->flash_data); | |
1253 | } | |
1254 | ||
1255 | return (uint8_t)data; | |
1256 | } | |
1257 | ||
1258 | /** | |
1259 | * qla2x00_write_flash_byte() - Write a byte to flash | |
1260 | * @ha: HA context | |
1261 | * @addr: Address in flash to write | |
1262 | * @data: Data to write | |
1263 | */ | |
1264 | static void | |
1265 | qla2x00_write_flash_byte(scsi_qla_host_t *ha, uint32_t addr, uint8_t data) | |
1266 | { | |
1267 | uint16_t bank_select; | |
1268 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
1269 | ||
1270 | bank_select = RD_REG_WORD(®->ctrl_status); | |
1271 | if (IS_QLA2322(ha) || IS_QLA6322(ha)) { | |
1272 | /* Specify 64K address range: */ | |
1273 | /* clear out Module Select and Flash Address bits [19:16]. */ | |
1274 | bank_select &= ~0xf8; | |
1275 | bank_select |= addr >> 12 & 0xf0; | |
1276 | bank_select |= CSR_FLASH_64K_BANK; | |
1277 | WRT_REG_WORD(®->ctrl_status, bank_select); | |
1278 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1279 | ||
1280 | WRT_REG_WORD(®->flash_address, (uint16_t)addr); | |
1281 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1282 | WRT_REG_WORD(®->flash_data, (uint16_t)data); | |
1283 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1284 | ||
1285 | return; | |
1286 | } | |
1287 | ||
1288 | /* Setup bit 16 of flash address. */ | |
1289 | if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) { | |
1290 | bank_select |= CSR_FLASH_64K_BANK; | |
1291 | WRT_REG_WORD(®->ctrl_status, bank_select); | |
1292 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1293 | } else if (((addr & BIT_16) == 0) && | |
1294 | (bank_select & CSR_FLASH_64K_BANK)) { | |
1295 | bank_select &= ~(CSR_FLASH_64K_BANK); | |
1296 | WRT_REG_WORD(®->ctrl_status, bank_select); | |
1297 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1298 | } | |
1299 | ||
1300 | /* Always perform IO mapped accesses to the FLASH registers. */ | |
1301 | if (ha->pio_address) { | |
948882f6 AV |
1302 | WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr); |
1303 | WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data); | |
854165f4 | 1304 | } else { |
1305 | WRT_REG_WORD(®->flash_address, (uint16_t)addr); | |
1306 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1307 | WRT_REG_WORD(®->flash_data, (uint16_t)data); | |
1308 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1309 | } | |
1310 | } | |
1311 | ||
1312 | /** | |
1313 | * qla2x00_poll_flash() - Polls flash for completion. | |
1314 | * @ha: HA context | |
1315 | * @addr: Address in flash to poll | |
1316 | * @poll_data: Data to be polled | |
1317 | * @man_id: Flash manufacturer ID | |
1318 | * @flash_id: Flash ID | |
1319 | * | |
1320 | * This function polls the device until bit 7 of what is read matches data | |
1321 | * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed | |
1322 | * out (a fatal error). The flash book recommeds reading bit 7 again after | |
1323 | * reading bit 5 as a 1. | |
1324 | * | |
1325 | * Returns 0 on success, else non-zero. | |
1326 | */ | |
1327 | static int | |
1328 | qla2x00_poll_flash(scsi_qla_host_t *ha, uint32_t addr, uint8_t poll_data, | |
1329 | uint8_t man_id, uint8_t flash_id) | |
1330 | { | |
1331 | int status; | |
1332 | uint8_t flash_data; | |
1333 | uint32_t cnt; | |
1334 | ||
1335 | status = 1; | |
1336 | ||
1337 | /* Wait for 30 seconds for command to finish. */ | |
1338 | poll_data &= BIT_7; | |
1339 | for (cnt = 3000000; cnt; cnt--) { | |
1340 | flash_data = qla2x00_read_flash_byte(ha, addr); | |
1341 | if ((flash_data & BIT_7) == poll_data) { | |
1342 | status = 0; | |
1343 | break; | |
1344 | } | |
1345 | ||
1346 | if (man_id != 0x40 && man_id != 0xda) { | |
1347 | if ((flash_data & BIT_5) && cnt > 2) | |
1348 | cnt = 2; | |
1349 | } | |
1350 | udelay(10); | |
1351 | barrier(); | |
40a2e34a | 1352 | cond_resched(); |
854165f4 | 1353 | } |
1354 | return status; | |
1355 | } | |
1356 | ||
854165f4 | 1357 | /** |
1358 | * qla2x00_program_flash_address() - Programs a flash address | |
1359 | * @ha: HA context | |
1360 | * @addr: Address in flash to program | |
1361 | * @data: Data to be written in flash | |
1362 | * @man_id: Flash manufacturer ID | |
1363 | * @flash_id: Flash ID | |
1364 | * | |
1365 | * Returns 0 on success, else non-zero. | |
1366 | */ | |
1367 | static int | |
1368 | qla2x00_program_flash_address(scsi_qla_host_t *ha, uint32_t addr, uint8_t data, | |
1369 | uint8_t man_id, uint8_t flash_id) | |
1370 | { | |
1371 | /* Write Program Command Sequence. */ | |
1372 | if (IS_OEM_001(ha)) { | |
1373 | qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); | |
1374 | qla2x00_write_flash_byte(ha, 0x555, 0x55); | |
1375 | qla2x00_write_flash_byte(ha, 0xaaa, 0xa0); | |
1376 | qla2x00_write_flash_byte(ha, addr, data); | |
1377 | } else { | |
1378 | if (man_id == 0xda && flash_id == 0xc1) { | |
1379 | qla2x00_write_flash_byte(ha, addr, data); | |
1380 | if (addr & 0x7e) | |
1381 | return 0; | |
1382 | } else { | |
1383 | qla2x00_write_flash_byte(ha, 0x5555, 0xaa); | |
1384 | qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); | |
1385 | qla2x00_write_flash_byte(ha, 0x5555, 0xa0); | |
1386 | qla2x00_write_flash_byte(ha, addr, data); | |
1387 | } | |
1388 | } | |
1389 | ||
1390 | udelay(150); | |
1391 | ||
1392 | /* Wait for write to complete. */ | |
1393 | return qla2x00_poll_flash(ha, addr, data, man_id, flash_id); | |
1394 | } | |
1395 | ||
1396 | /** | |
1397 | * qla2x00_erase_flash() - Erase the flash. | |
1398 | * @ha: HA context | |
1399 | * @man_id: Flash manufacturer ID | |
1400 | * @flash_id: Flash ID | |
1401 | * | |
1402 | * Returns 0 on success, else non-zero. | |
1403 | */ | |
1404 | static int | |
1405 | qla2x00_erase_flash(scsi_qla_host_t *ha, uint8_t man_id, uint8_t flash_id) | |
1406 | { | |
1407 | /* Individual Sector Erase Command Sequence */ | |
1408 | if (IS_OEM_001(ha)) { | |
1409 | qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); | |
1410 | qla2x00_write_flash_byte(ha, 0x555, 0x55); | |
1411 | qla2x00_write_flash_byte(ha, 0xaaa, 0x80); | |
1412 | qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); | |
1413 | qla2x00_write_flash_byte(ha, 0x555, 0x55); | |
1414 | qla2x00_write_flash_byte(ha, 0xaaa, 0x10); | |
1415 | } else { | |
1416 | qla2x00_write_flash_byte(ha, 0x5555, 0xaa); | |
1417 | qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); | |
1418 | qla2x00_write_flash_byte(ha, 0x5555, 0x80); | |
1419 | qla2x00_write_flash_byte(ha, 0x5555, 0xaa); | |
1420 | qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); | |
1421 | qla2x00_write_flash_byte(ha, 0x5555, 0x10); | |
1422 | } | |
1423 | ||
1424 | udelay(150); | |
1425 | ||
1426 | /* Wait for erase to complete. */ | |
1427 | return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id); | |
1428 | } | |
1429 | ||
1430 | /** | |
1431 | * qla2x00_erase_flash_sector() - Erase a flash sector. | |
1432 | * @ha: HA context | |
1433 | * @addr: Flash sector to erase | |
1434 | * @sec_mask: Sector address mask | |
1435 | * @man_id: Flash manufacturer ID | |
1436 | * @flash_id: Flash ID | |
1437 | * | |
1438 | * Returns 0 on success, else non-zero. | |
1439 | */ | |
1440 | static int | |
1441 | qla2x00_erase_flash_sector(scsi_qla_host_t *ha, uint32_t addr, | |
1442 | uint32_t sec_mask, uint8_t man_id, uint8_t flash_id) | |
1443 | { | |
1444 | /* Individual Sector Erase Command Sequence */ | |
1445 | qla2x00_write_flash_byte(ha, 0x5555, 0xaa); | |
1446 | qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); | |
1447 | qla2x00_write_flash_byte(ha, 0x5555, 0x80); | |
1448 | qla2x00_write_flash_byte(ha, 0x5555, 0xaa); | |
1449 | qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); | |
1450 | if (man_id == 0x1f && flash_id == 0x13) | |
1451 | qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10); | |
1452 | else | |
1453 | qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30); | |
1454 | ||
1455 | udelay(150); | |
1456 | ||
1457 | /* Wait for erase to complete. */ | |
1458 | return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id); | |
1459 | } | |
1460 | ||
1461 | /** | |
1462 | * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip. | |
1463 | * @man_id: Flash manufacturer ID | |
1464 | * @flash_id: Flash ID | |
1465 | */ | |
1466 | static void | |
1467 | qla2x00_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id, | |
1468 | uint8_t *flash_id) | |
1469 | { | |
1470 | qla2x00_write_flash_byte(ha, 0x5555, 0xaa); | |
1471 | qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); | |
1472 | qla2x00_write_flash_byte(ha, 0x5555, 0x90); | |
1473 | *man_id = qla2x00_read_flash_byte(ha, 0x0000); | |
1474 | *flash_id = qla2x00_read_flash_byte(ha, 0x0001); | |
1475 | qla2x00_write_flash_byte(ha, 0x5555, 0xaa); | |
1476 | qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); | |
1477 | qla2x00_write_flash_byte(ha, 0x5555, 0xf0); | |
1478 | } | |
1479 | ||
30c47662 AV |
1480 | static void |
1481 | qla2x00_read_flash_data(scsi_qla_host_t *ha, uint8_t *tmp_buf, uint32_t saddr, | |
1482 | uint32_t length) | |
1483 | { | |
1484 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
1485 | uint32_t midpoint, ilength; | |
1486 | uint8_t data; | |
1487 | ||
1488 | midpoint = length / 2; | |
1489 | ||
1490 | WRT_REG_WORD(®->nvram, 0); | |
1491 | RD_REG_WORD(®->nvram); | |
1492 | for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) { | |
1493 | if (ilength == midpoint) { | |
1494 | WRT_REG_WORD(®->nvram, NVR_SELECT); | |
1495 | RD_REG_WORD(®->nvram); | |
1496 | } | |
1497 | data = qla2x00_read_flash_byte(ha, saddr); | |
1498 | if (saddr % 100) | |
1499 | udelay(10); | |
1500 | *tmp_buf = data; | |
40a2e34a | 1501 | cond_resched(); |
30c47662 AV |
1502 | } |
1503 | } | |
854165f4 | 1504 | |
1505 | static inline void | |
1506 | qla2x00_suspend_hba(struct scsi_qla_host *ha) | |
1507 | { | |
1508 | int cnt; | |
1509 | unsigned long flags; | |
1510 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
1511 | ||
1512 | /* Suspend HBA. */ | |
1513 | scsi_block_requests(ha->host); | |
fd34f556 | 1514 | ha->isp_ops->disable_intrs(ha); |
854165f4 | 1515 | set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); |
1516 | ||
1517 | /* Pause RISC. */ | |
1518 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1519 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); | |
1520 | RD_REG_WORD(®->hccr); | |
1521 | if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { | |
1522 | for (cnt = 0; cnt < 30000; cnt++) { | |
1523 | if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) != 0) | |
1524 | break; | |
1525 | udelay(100); | |
1526 | } | |
1527 | } else { | |
1528 | udelay(10); | |
1529 | } | |
1530 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1531 | } | |
1532 | ||
1533 | static inline void | |
1534 | qla2x00_resume_hba(struct scsi_qla_host *ha) | |
1535 | { | |
1536 | /* Resume HBA. */ | |
1537 | clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); | |
1538 | set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags); | |
39a11240 | 1539 | qla2xxx_wake_dpc(ha); |
854165f4 | 1540 | qla2x00_wait_for_hba_online(ha); |
1541 | scsi_unblock_requests(ha->host); | |
1542 | } | |
1543 | ||
1544 | uint8_t * | |
1545 | qla2x00_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, | |
1546 | uint32_t offset, uint32_t length) | |
1547 | { | |
854165f4 | 1548 | uint32_t addr, midpoint; |
1549 | uint8_t *data; | |
1550 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
1551 | ||
1552 | /* Suspend HBA. */ | |
1553 | qla2x00_suspend_hba(ha); | |
1554 | ||
1555 | /* Go with read. */ | |
854165f4 | 1556 | midpoint = ha->optrom_size / 2; |
1557 | ||
1558 | qla2x00_flash_enable(ha); | |
1559 | WRT_REG_WORD(®->nvram, 0); | |
1560 | RD_REG_WORD(®->nvram); /* PCI Posting. */ | |
1561 | for (addr = offset, data = buf; addr < length; addr++, data++) { | |
1562 | if (addr == midpoint) { | |
1563 | WRT_REG_WORD(®->nvram, NVR_SELECT); | |
1564 | RD_REG_WORD(®->nvram); /* PCI Posting. */ | |
1565 | } | |
1566 | ||
1567 | *data = qla2x00_read_flash_byte(ha, addr); | |
1568 | } | |
1569 | qla2x00_flash_disable(ha); | |
854165f4 | 1570 | |
1571 | /* Resume HBA. */ | |
1572 | qla2x00_resume_hba(ha); | |
1573 | ||
1574 | return buf; | |
1575 | } | |
1576 | ||
1577 | int | |
1578 | qla2x00_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, | |
1579 | uint32_t offset, uint32_t length) | |
1580 | { | |
1581 | ||
1582 | int rval; | |
854165f4 | 1583 | uint8_t man_id, flash_id, sec_number, data; |
1584 | uint16_t wd; | |
1585 | uint32_t addr, liter, sec_mask, rest_addr; | |
1586 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
1587 | ||
1588 | /* Suspend HBA. */ | |
1589 | qla2x00_suspend_hba(ha); | |
1590 | ||
1591 | rval = QLA_SUCCESS; | |
1592 | sec_number = 0; | |
1593 | ||
1594 | /* Reset ISP chip. */ | |
854165f4 | 1595 | WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); |
1596 | pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); | |
1597 | ||
1598 | /* Go with write. */ | |
1599 | qla2x00_flash_enable(ha); | |
1600 | do { /* Loop once to provide quick error exit */ | |
1601 | /* Structure of flash memory based on manufacturer */ | |
1602 | if (IS_OEM_001(ha)) { | |
1603 | /* OEM variant with special flash part. */ | |
1604 | man_id = flash_id = 0; | |
1605 | rest_addr = 0xffff; | |
1606 | sec_mask = 0x10000; | |
1607 | goto update_flash; | |
1608 | } | |
1609 | qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id); | |
1610 | switch (man_id) { | |
1611 | case 0x20: /* ST flash. */ | |
1612 | if (flash_id == 0xd2 || flash_id == 0xe3) { | |
1613 | /* | |
1614 | * ST m29w008at part - 64kb sector size with | |
1615 | * 32kb,8kb,8kb,16kb sectors at memory address | |
1616 | * 0xf0000. | |
1617 | */ | |
1618 | rest_addr = 0xffff; | |
1619 | sec_mask = 0x10000; | |
1620 | break; | |
1621 | } | |
1622 | /* | |
1623 | * ST m29w010b part - 16kb sector size | |
1624 | * Default to 16kb sectors | |
1625 | */ | |
1626 | rest_addr = 0x3fff; | |
1627 | sec_mask = 0x1c000; | |
1628 | break; | |
1629 | case 0x40: /* Mostel flash. */ | |
1630 | /* Mostel v29c51001 part - 512 byte sector size. */ | |
1631 | rest_addr = 0x1ff; | |
1632 | sec_mask = 0x1fe00; | |
1633 | break; | |
1634 | case 0xbf: /* SST flash. */ | |
1635 | /* SST39sf10 part - 4kb sector size. */ | |
1636 | rest_addr = 0xfff; | |
1637 | sec_mask = 0x1f000; | |
1638 | break; | |
1639 | case 0xda: /* Winbond flash. */ | |
1640 | /* Winbond W29EE011 part - 256 byte sector size. */ | |
1641 | rest_addr = 0x7f; | |
1642 | sec_mask = 0x1ff80; | |
1643 | break; | |
1644 | case 0xc2: /* Macronix flash. */ | |
1645 | /* 64k sector size. */ | |
1646 | if (flash_id == 0x38 || flash_id == 0x4f) { | |
1647 | rest_addr = 0xffff; | |
1648 | sec_mask = 0x10000; | |
1649 | break; | |
1650 | } | |
1651 | /* Fall through... */ | |
1652 | ||
1653 | case 0x1f: /* Atmel flash. */ | |
1654 | /* 512k sector size. */ | |
1655 | if (flash_id == 0x13) { | |
1656 | rest_addr = 0x7fffffff; | |
1657 | sec_mask = 0x80000000; | |
1658 | break; | |
1659 | } | |
1660 | /* Fall through... */ | |
1661 | ||
1662 | case 0x01: /* AMD flash. */ | |
1663 | if (flash_id == 0x38 || flash_id == 0x40 || | |
1664 | flash_id == 0x4f) { | |
1665 | /* Am29LV081 part - 64kb sector size. */ | |
1666 | /* Am29LV002BT part - 64kb sector size. */ | |
1667 | rest_addr = 0xffff; | |
1668 | sec_mask = 0x10000; | |
1669 | break; | |
1670 | } else if (flash_id == 0x3e) { | |
1671 | /* | |
1672 | * Am29LV008b part - 64kb sector size with | |
1673 | * 32kb,8kb,8kb,16kb sector at memory address | |
1674 | * h0xf0000. | |
1675 | */ | |
1676 | rest_addr = 0xffff; | |
1677 | sec_mask = 0x10000; | |
1678 | break; | |
1679 | } else if (flash_id == 0x20 || flash_id == 0x6e) { | |
1680 | /* | |
1681 | * Am29LV010 part or AM29f010 - 16kb sector | |
1682 | * size. | |
1683 | */ | |
1684 | rest_addr = 0x3fff; | |
1685 | sec_mask = 0x1c000; | |
1686 | break; | |
1687 | } else if (flash_id == 0x6d) { | |
1688 | /* Am29LV001 part - 8kb sector size. */ | |
1689 | rest_addr = 0x1fff; | |
1690 | sec_mask = 0x1e000; | |
1691 | break; | |
1692 | } | |
1693 | default: | |
1694 | /* Default to 16 kb sector size. */ | |
1695 | rest_addr = 0x3fff; | |
1696 | sec_mask = 0x1c000; | |
1697 | break; | |
1698 | } | |
1699 | ||
1700 | update_flash: | |
1701 | if (IS_QLA2322(ha) || IS_QLA6322(ha)) { | |
1702 | if (qla2x00_erase_flash(ha, man_id, flash_id)) { | |
1703 | rval = QLA_FUNCTION_FAILED; | |
1704 | break; | |
1705 | } | |
1706 | } | |
1707 | ||
1708 | for (addr = offset, liter = 0; liter < length; liter++, | |
1709 | addr++) { | |
1710 | data = buf[liter]; | |
1711 | /* Are we at the beginning of a sector? */ | |
1712 | if ((addr & rest_addr) == 0) { | |
1713 | if (IS_QLA2322(ha) || IS_QLA6322(ha)) { | |
1714 | if (addr >= 0x10000UL) { | |
1715 | if (((addr >> 12) & 0xf0) && | |
1716 | ((man_id == 0x01 && | |
1717 | flash_id == 0x3e) || | |
1718 | (man_id == 0x20 && | |
1719 | flash_id == 0xd2))) { | |
1720 | sec_number++; | |
1721 | if (sec_number == 1) { | |
1722 | rest_addr = | |
1723 | 0x7fff; | |
1724 | sec_mask = | |
1725 | 0x18000; | |
1726 | } else if ( | |
1727 | sec_number == 2 || | |
1728 | sec_number == 3) { | |
1729 | rest_addr = | |
1730 | 0x1fff; | |
1731 | sec_mask = | |
1732 | 0x1e000; | |
1733 | } else if ( | |
1734 | sec_number == 4) { | |
1735 | rest_addr = | |
1736 | 0x3fff; | |
1737 | sec_mask = | |
1738 | 0x1c000; | |
1739 | } | |
1740 | } | |
1741 | } | |
1742 | } else if (addr == ha->optrom_size / 2) { | |
1743 | WRT_REG_WORD(®->nvram, NVR_SELECT); | |
1744 | RD_REG_WORD(®->nvram); | |
1745 | } | |
1746 | ||
1747 | if (flash_id == 0xda && man_id == 0xc1) { | |
1748 | qla2x00_write_flash_byte(ha, 0x5555, | |
1749 | 0xaa); | |
1750 | qla2x00_write_flash_byte(ha, 0x2aaa, | |
1751 | 0x55); | |
1752 | qla2x00_write_flash_byte(ha, 0x5555, | |
1753 | 0xa0); | |
1754 | } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) { | |
1755 | /* Then erase it */ | |
1756 | if (qla2x00_erase_flash_sector(ha, | |
1757 | addr, sec_mask, man_id, | |
1758 | flash_id)) { | |
1759 | rval = QLA_FUNCTION_FAILED; | |
1760 | break; | |
1761 | } | |
1762 | if (man_id == 0x01 && flash_id == 0x6d) | |
1763 | sec_number++; | |
1764 | } | |
1765 | } | |
1766 | ||
1767 | if (man_id == 0x01 && flash_id == 0x6d) { | |
1768 | if (sec_number == 1 && | |
1769 | addr == (rest_addr - 1)) { | |
1770 | rest_addr = 0x0fff; | |
1771 | sec_mask = 0x1f000; | |
1772 | } else if (sec_number == 3 && (addr & 0x7ffe)) { | |
1773 | rest_addr = 0x3fff; | |
1774 | sec_mask = 0x1c000; | |
1775 | } | |
1776 | } | |
1777 | ||
1778 | if (qla2x00_program_flash_address(ha, addr, data, | |
1779 | man_id, flash_id)) { | |
1780 | rval = QLA_FUNCTION_FAILED; | |
1781 | break; | |
1782 | } | |
40a2e34a | 1783 | cond_resched(); |
854165f4 | 1784 | } |
1785 | } while (0); | |
1786 | qla2x00_flash_disable(ha); | |
854165f4 | 1787 | |
1788 | /* Resume HBA. */ | |
1789 | qla2x00_resume_hba(ha); | |
1790 | ||
1791 | return rval; | |
1792 | } | |
1793 | ||
1794 | uint8_t * | |
1795 | qla24xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, | |
1796 | uint32_t offset, uint32_t length) | |
1797 | { | |
1798 | /* Suspend HBA. */ | |
1799 | scsi_block_requests(ha->host); | |
854165f4 | 1800 | set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); |
1801 | ||
1802 | /* Go with read. */ | |
1803 | qla24xx_read_flash_data(ha, (uint32_t *)buf, offset >> 2, length >> 2); | |
1804 | ||
1805 | /* Resume HBA. */ | |
1806 | clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); | |
854165f4 | 1807 | scsi_unblock_requests(ha->host); |
1808 | ||
1809 | return buf; | |
1810 | } | |
1811 | ||
1812 | int | |
1813 | qla24xx_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, | |
1814 | uint32_t offset, uint32_t length) | |
1815 | { | |
1816 | int rval; | |
1817 | ||
1818 | /* Suspend HBA. */ | |
1819 | scsi_block_requests(ha->host); | |
854165f4 | 1820 | set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); |
1821 | ||
1822 | /* Go with write. */ | |
1823 | rval = qla24xx_write_flash_data(ha, (uint32_t *)buf, offset >> 2, | |
1824 | length >> 2); | |
1825 | ||
1826 | /* Resume HBA -- RISC reset needed. */ | |
1827 | clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); | |
1828 | set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags); | |
39a11240 | 1829 | qla2xxx_wake_dpc(ha); |
854165f4 | 1830 | qla2x00_wait_for_hba_online(ha); |
1831 | scsi_unblock_requests(ha->host); | |
1832 | ||
1833 | return rval; | |
1834 | } | |
30c47662 | 1835 | |
338c9161 AV |
1836 | uint8_t * |
1837 | qla25xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, | |
1838 | uint32_t offset, uint32_t length) | |
1839 | { | |
1840 | int rval; | |
1841 | dma_addr_t optrom_dma; | |
1842 | void *optrom; | |
1843 | uint8_t *pbuf; | |
1844 | uint32_t faddr, left, burst; | |
1845 | ||
b7cc176c | 1846 | if (offset & 0xfff) |
338c9161 AV |
1847 | goto slow_read; |
1848 | if (length < OPTROM_BURST_SIZE) | |
1849 | goto slow_read; | |
1850 | ||
1851 | optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, | |
1852 | &optrom_dma, GFP_KERNEL); | |
1853 | if (!optrom) { | |
1854 | qla_printk(KERN_DEBUG, ha, | |
1855 | "Unable to allocate memory for optrom burst read " | |
1856 | "(%x KB).\n", OPTROM_BURST_SIZE / 1024); | |
1857 | ||
1858 | goto slow_read; | |
1859 | } | |
1860 | ||
1861 | pbuf = buf; | |
1862 | faddr = offset >> 2; | |
1863 | left = length >> 2; | |
1864 | burst = OPTROM_BURST_DWORDS; | |
1865 | while (left != 0) { | |
1866 | if (burst > left) | |
1867 | burst = left; | |
1868 | ||
1869 | rval = qla2x00_dump_ram(ha, optrom_dma, | |
1870 | flash_data_to_access_addr(faddr), burst); | |
1871 | if (rval) { | |
1872 | qla_printk(KERN_WARNING, ha, | |
1873 | "Unable to burst-read optrom segment " | |
1874 | "(%x/%x/%llx).\n", rval, | |
875baf3c AM |
1875 | flash_data_to_access_addr(faddr), |
1876 | (unsigned long long)optrom_dma); | |
338c9161 AV |
1877 | qla_printk(KERN_WARNING, ha, |
1878 | "Reverting to slow-read.\n"); | |
1879 | ||
1880 | dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, | |
1881 | optrom, optrom_dma); | |
1882 | goto slow_read; | |
1883 | } | |
1884 | ||
1885 | memcpy(pbuf, optrom, burst * 4); | |
1886 | ||
1887 | left -= burst; | |
1888 | faddr += burst; | |
1889 | pbuf += burst * 4; | |
1890 | } | |
1891 | ||
1892 | dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom, | |
1893 | optrom_dma); | |
1894 | ||
1895 | return buf; | |
1896 | ||
1897 | slow_read: | |
1898 | return qla24xx_read_optrom_data(ha, buf, offset, length); | |
1899 | } | |
1900 | ||
30c47662 AV |
1901 | /** |
1902 | * qla2x00_get_fcode_version() - Determine an FCODE image's version. | |
1903 | * @ha: HA context | |
1904 | * @pcids: Pointer to the FCODE PCI data structure | |
1905 | * | |
1906 | * The process of retrieving the FCODE version information is at best | |
1907 | * described as interesting. | |
1908 | * | |
1909 | * Within the first 100h bytes of the image an ASCII string is present | |
1910 | * which contains several pieces of information including the FCODE | |
1911 | * version. Unfortunately it seems the only reliable way to retrieve | |
1912 | * the version is by scanning for another sentinel within the string, | |
1913 | * the FCODE build date: | |
1914 | * | |
1915 | * ... 2.00.02 10/17/02 ... | |
1916 | * | |
1917 | * Returns QLA_SUCCESS on successful retrieval of version. | |
1918 | */ | |
1919 | static void | |
1920 | qla2x00_get_fcode_version(scsi_qla_host_t *ha, uint32_t pcids) | |
1921 | { | |
1922 | int ret = QLA_FUNCTION_FAILED; | |
1923 | uint32_t istart, iend, iter, vend; | |
1924 | uint8_t do_next, rbyte, *vbyte; | |
1925 | ||
1926 | memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); | |
1927 | ||
1928 | /* Skip the PCI data structure. */ | |
1929 | istart = pcids + | |
1930 | ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) | | |
1931 | qla2x00_read_flash_byte(ha, pcids + 0x0A)); | |
1932 | iend = istart + 0x100; | |
1933 | do { | |
1934 | /* Scan for the sentinel date string...eeewww. */ | |
1935 | do_next = 0; | |
1936 | iter = istart; | |
1937 | while ((iter < iend) && !do_next) { | |
1938 | iter++; | |
1939 | if (qla2x00_read_flash_byte(ha, iter) == '/') { | |
1940 | if (qla2x00_read_flash_byte(ha, iter + 2) == | |
1941 | '/') | |
1942 | do_next++; | |
1943 | else if (qla2x00_read_flash_byte(ha, | |
1944 | iter + 3) == '/') | |
1945 | do_next++; | |
1946 | } | |
1947 | } | |
1948 | if (!do_next) | |
1949 | break; | |
1950 | ||
1951 | /* Backtrack to previous ' ' (space). */ | |
1952 | do_next = 0; | |
1953 | while ((iter > istart) && !do_next) { | |
1954 | iter--; | |
1955 | if (qla2x00_read_flash_byte(ha, iter) == ' ') | |
1956 | do_next++; | |
1957 | } | |
1958 | if (!do_next) | |
1959 | break; | |
1960 | ||
1961 | /* | |
1962 | * Mark end of version tag, and find previous ' ' (space) or | |
1963 | * string length (recent FCODE images -- major hack ahead!!!). | |
1964 | */ | |
1965 | vend = iter - 1; | |
1966 | do_next = 0; | |
1967 | while ((iter > istart) && !do_next) { | |
1968 | iter--; | |
1969 | rbyte = qla2x00_read_flash_byte(ha, iter); | |
1970 | if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10) | |
1971 | do_next++; | |
1972 | } | |
1973 | if (!do_next) | |
1974 | break; | |
1975 | ||
1976 | /* Mark beginning of version tag, and copy data. */ | |
1977 | iter++; | |
1978 | if ((vend - iter) && | |
1979 | ((vend - iter) < sizeof(ha->fcode_revision))) { | |
1980 | vbyte = ha->fcode_revision; | |
1981 | while (iter <= vend) { | |
1982 | *vbyte++ = qla2x00_read_flash_byte(ha, iter); | |
1983 | iter++; | |
1984 | } | |
1985 | ret = QLA_SUCCESS; | |
1986 | } | |
1987 | } while (0); | |
1988 | ||
1989 | if (ret != QLA_SUCCESS) | |
1990 | memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); | |
1991 | } | |
1992 | ||
1993 | int | |
1994 | qla2x00_get_flash_version(scsi_qla_host_t *ha, void *mbuf) | |
1995 | { | |
1996 | int ret = QLA_SUCCESS; | |
1997 | uint8_t code_type, last_image; | |
1998 | uint32_t pcihdr, pcids; | |
1999 | uint8_t *dbyte; | |
2000 | uint16_t *dcode; | |
2001 | ||
2002 | if (!ha->pio_address || !mbuf) | |
2003 | return QLA_FUNCTION_FAILED; | |
2004 | ||
2005 | memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); | |
2006 | memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); | |
2007 | memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); | |
2008 | memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); | |
2009 | ||
2010 | qla2x00_flash_enable(ha); | |
2011 | ||
2012 | /* Begin with first PCI expansion ROM header. */ | |
2013 | pcihdr = 0; | |
2014 | last_image = 1; | |
2015 | do { | |
2016 | /* Verify PCI expansion ROM header. */ | |
2017 | if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 || | |
2018 | qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) { | |
2019 | /* No signature */ | |
2020 | DEBUG2(printk("scsi(%ld): No matching ROM " | |
2021 | "signature.\n", ha->host_no)); | |
2022 | ret = QLA_FUNCTION_FAILED; | |
2023 | break; | |
2024 | } | |
2025 | ||
2026 | /* Locate PCI data structure. */ | |
2027 | pcids = pcihdr + | |
2028 | ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) | | |
2029 | qla2x00_read_flash_byte(ha, pcihdr + 0x18)); | |
2030 | ||
2031 | /* Validate signature of PCI data structure. */ | |
2032 | if (qla2x00_read_flash_byte(ha, pcids) != 'P' || | |
2033 | qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' || | |
2034 | qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' || | |
2035 | qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') { | |
2036 | /* Incorrect header. */ | |
2037 | DEBUG2(printk("%s(): PCI data struct not found " | |
2038 | "pcir_adr=%x.\n", __func__, pcids)); | |
2039 | ret = QLA_FUNCTION_FAILED; | |
2040 | break; | |
2041 | } | |
2042 | ||
2043 | /* Read version */ | |
2044 | code_type = qla2x00_read_flash_byte(ha, pcids + 0x14); | |
2045 | switch (code_type) { | |
2046 | case ROM_CODE_TYPE_BIOS: | |
2047 | /* Intel x86, PC-AT compatible. */ | |
2048 | ha->bios_revision[0] = | |
2049 | qla2x00_read_flash_byte(ha, pcids + 0x12); | |
2050 | ha->bios_revision[1] = | |
2051 | qla2x00_read_flash_byte(ha, pcids + 0x13); | |
2052 | DEBUG3(printk("%s(): read BIOS %d.%d.\n", __func__, | |
2053 | ha->bios_revision[1], ha->bios_revision[0])); | |
2054 | break; | |
2055 | case ROM_CODE_TYPE_FCODE: | |
2056 | /* Open Firmware standard for PCI (FCode). */ | |
2057 | /* Eeeewww... */ | |
2058 | qla2x00_get_fcode_version(ha, pcids); | |
2059 | break; | |
2060 | case ROM_CODE_TYPE_EFI: | |
2061 | /* Extensible Firmware Interface (EFI). */ | |
2062 | ha->efi_revision[0] = | |
2063 | qla2x00_read_flash_byte(ha, pcids + 0x12); | |
2064 | ha->efi_revision[1] = | |
2065 | qla2x00_read_flash_byte(ha, pcids + 0x13); | |
2066 | DEBUG3(printk("%s(): read EFI %d.%d.\n", __func__, | |
2067 | ha->efi_revision[1], ha->efi_revision[0])); | |
2068 | break; | |
2069 | default: | |
2070 | DEBUG2(printk("%s(): Unrecognized code type %x at " | |
2071 | "pcids %x.\n", __func__, code_type, pcids)); | |
2072 | break; | |
2073 | } | |
2074 | ||
2075 | last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7; | |
2076 | ||
2077 | /* Locate next PCI expansion ROM. */ | |
2078 | pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) | | |
2079 | qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512; | |
2080 | } while (!last_image); | |
2081 | ||
2082 | if (IS_QLA2322(ha)) { | |
2083 | /* Read firmware image information. */ | |
2084 | memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); | |
2085 | dbyte = mbuf; | |
2086 | memset(dbyte, 0, 8); | |
2087 | dcode = (uint16_t *)dbyte; | |
2088 | ||
2089 | qla2x00_read_flash_data(ha, dbyte, FA_RISC_CODE_ADDR * 4 + 10, | |
2090 | 8); | |
2091 | DEBUG3(printk("%s(%ld): dumping fw ver from flash:\n", | |
2092 | __func__, ha->host_no)); | |
2093 | DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte, 8)); | |
2094 | ||
2095 | if ((dcode[0] == 0xffff && dcode[1] == 0xffff && | |
2096 | dcode[2] == 0xffff && dcode[3] == 0xffff) || | |
2097 | (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && | |
2098 | dcode[3] == 0)) { | |
2099 | DEBUG2(printk("%s(): Unrecognized fw revision at " | |
2100 | "%x.\n", __func__, FA_RISC_CODE_ADDR * 4)); | |
2101 | } else { | |
2102 | /* values are in big endian */ | |
2103 | ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1]; | |
2104 | ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3]; | |
2105 | ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5]; | |
2106 | } | |
2107 | } | |
2108 | ||
2109 | qla2x00_flash_disable(ha); | |
2110 | ||
2111 | return ret; | |
2112 | } | |
2113 | ||
2114 | int | |
2115 | qla24xx_get_flash_version(scsi_qla_host_t *ha, void *mbuf) | |
2116 | { | |
2117 | int ret = QLA_SUCCESS; | |
2118 | uint32_t pcihdr, pcids; | |
2119 | uint32_t *dcode; | |
2120 | uint8_t *bcode; | |
2121 | uint8_t code_type, last_image; | |
2122 | int i; | |
2123 | ||
2124 | if (!mbuf) | |
2125 | return QLA_FUNCTION_FAILED; | |
2126 | ||
2127 | memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); | |
2128 | memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); | |
2129 | memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); | |
2130 | memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); | |
2131 | ||
2132 | dcode = mbuf; | |
2133 | ||
2134 | /* Begin with first PCI expansion ROM header. */ | |
2135 | pcihdr = 0; | |
2136 | last_image = 1; | |
2137 | do { | |
2138 | /* Verify PCI expansion ROM header. */ | |
2139 | qla24xx_read_flash_data(ha, dcode, pcihdr >> 2, 0x20); | |
2140 | bcode = mbuf + (pcihdr % 4); | |
2141 | if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) { | |
2142 | /* No signature */ | |
2143 | DEBUG2(printk("scsi(%ld): No matching ROM " | |
2144 | "signature.\n", ha->host_no)); | |
2145 | ret = QLA_FUNCTION_FAILED; | |
2146 | break; | |
2147 | } | |
2148 | ||
2149 | /* Locate PCI data structure. */ | |
2150 | pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]); | |
2151 | ||
2152 | qla24xx_read_flash_data(ha, dcode, pcids >> 2, 0x20); | |
2153 | bcode = mbuf + (pcihdr % 4); | |
2154 | ||
2155 | /* Validate signature of PCI data structure. */ | |
2156 | if (bcode[0x0] != 'P' || bcode[0x1] != 'C' || | |
2157 | bcode[0x2] != 'I' || bcode[0x3] != 'R') { | |
2158 | /* Incorrect header. */ | |
2159 | DEBUG2(printk("%s(): PCI data struct not found " | |
2160 | "pcir_adr=%x.\n", __func__, pcids)); | |
2161 | ret = QLA_FUNCTION_FAILED; | |
2162 | break; | |
2163 | } | |
2164 | ||
2165 | /* Read version */ | |
2166 | code_type = bcode[0x14]; | |
2167 | switch (code_type) { | |
2168 | case ROM_CODE_TYPE_BIOS: | |
2169 | /* Intel x86, PC-AT compatible. */ | |
2170 | ha->bios_revision[0] = bcode[0x12]; | |
2171 | ha->bios_revision[1] = bcode[0x13]; | |
2172 | DEBUG3(printk("%s(): read BIOS %d.%d.\n", __func__, | |
2173 | ha->bios_revision[1], ha->bios_revision[0])); | |
2174 | break; | |
2175 | case ROM_CODE_TYPE_FCODE: | |
2176 | /* Open Firmware standard for PCI (FCode). */ | |
2177 | ha->fcode_revision[0] = bcode[0x12]; | |
2178 | ha->fcode_revision[1] = bcode[0x13]; | |
2179 | DEBUG3(printk("%s(): read FCODE %d.%d.\n", __func__, | |
2180 | ha->fcode_revision[1], ha->fcode_revision[0])); | |
2181 | break; | |
2182 | case ROM_CODE_TYPE_EFI: | |
2183 | /* Extensible Firmware Interface (EFI). */ | |
2184 | ha->efi_revision[0] = bcode[0x12]; | |
2185 | ha->efi_revision[1] = bcode[0x13]; | |
2186 | DEBUG3(printk("%s(): read EFI %d.%d.\n", __func__, | |
2187 | ha->efi_revision[1], ha->efi_revision[0])); | |
2188 | break; | |
2189 | default: | |
2190 | DEBUG2(printk("%s(): Unrecognized code type %x at " | |
2191 | "pcids %x.\n", __func__, code_type, pcids)); | |
2192 | break; | |
2193 | } | |
2194 | ||
2195 | last_image = bcode[0x15] & BIT_7; | |
2196 | ||
2197 | /* Locate next PCI expansion ROM. */ | |
2198 | pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512; | |
2199 | } while (!last_image); | |
2200 | ||
2201 | /* Read firmware image information. */ | |
2202 | memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); | |
2203 | dcode = mbuf; | |
2204 | ||
2205 | qla24xx_read_flash_data(ha, dcode, FA_RISC_CODE_ADDR + 4, 4); | |
2206 | for (i = 0; i < 4; i++) | |
2207 | dcode[i] = be32_to_cpu(dcode[i]); | |
2208 | ||
2209 | if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff && | |
2210 | dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) || | |
2211 | (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && | |
2212 | dcode[3] == 0)) { | |
2213 | DEBUG2(printk("%s(): Unrecognized fw version at %x.\n", | |
2214 | __func__, FA_RISC_CODE_ADDR)); | |
2215 | } else { | |
2216 | ha->fw_revision[0] = dcode[0]; | |
2217 | ha->fw_revision[1] = dcode[1]; | |
2218 | ha->fw_revision[2] = dcode[2]; | |
2219 | ha->fw_revision[3] = dcode[3]; | |
2220 | } | |
2221 | ||
2222 | return ret; | |
2223 | } |