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[SCSI] qla2xxx: Correct queue-creation bug when driver loaded in QoS mode.
[deliverable/linux.git] / drivers / scsi / qla2xxx / qla_sup.c
CommitLineData
fa90c54f
AV		 1/*
2 * QLogic Fibre Channel HBA Driver
01e58d8e 3 * Copyright (c) 2003-2008 QLogic Corporation
1da177e4 4 *
fa90c54f
AV		 5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
1da177e4
LT		 7#include "qla_def.h"
8
9#include <linux/delay.h>
2c96d8d0 10#include <linux/vmalloc.h>
1da177e4
LT		 11#include <asm/uaccess.h>
12
1da177e4
LT		 13/*
14 * NVRAM support routines
15 */
16
17/**
fa2a1ce5 18 * qla2x00_lock_nvram_access() -
1da177e4
LT		 19 * @ha: HA context
20 */
a824ebb3 21static void
7b867cf7 22qla2x00_lock_nvram_access(struct qla_hw_data *ha)
1da177e4
LT		 23{
24 uint16_t data;
3d71644c 25 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 26
27 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
28 data = RD_REG_WORD(&reg->nvram);
29 while (data & NVR_BUSY) {
30 udelay(100);
31 data = RD_REG_WORD(&reg->nvram);
32 }
33
34 /* Lock resource */
35 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
36 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
37 udelay(5);
38 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
39 while ((data & BIT_0) == 0) {
40 /* Lock failed */
41 udelay(100);
42 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
43 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
44 udelay(5);
45 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
46 }
47 }
48}
49
50/**
fa2a1ce5 51 * qla2x00_unlock_nvram_access() -
1da177e4
LT		 52 * @ha: HA context
53 */
a824ebb3 54static void
7b867cf7 55qla2x00_unlock_nvram_access(struct qla_hw_data *ha)
1da177e4 56{
3d71644c 57 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 58
59 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
60 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
61 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
62 }
63}
64
7b867cf7
AC		 65/**
66 * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
67 * @ha: HA context
68 * @data: Serial interface selector
69 */
70static void
71qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data)
72{
73 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
74
75 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
76 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
77 NVRAM_DELAY();
78 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_CLOCK |
79 NVR_WRT_ENABLE);
80 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
81 NVRAM_DELAY();
82 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
83 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
84 NVRAM_DELAY();
85}
86
87/**
88 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
89 * NVRAM.
90 * @ha: HA context
91 * @nv_cmd: NVRAM command
92 *
93 * Bit definitions for NVRAM command:
94 *
95 * Bit 26 = start bit
96 * Bit 25, 24 = opcode
97 * Bit 23-16 = address
98 * Bit 15-0 = write data
99 *
100 * Returns the word read from nvram @addr.
101 */
102static uint16_t
103qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd)
104{
105 uint8_t cnt;
106 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
107 uint16_t data = 0;
108 uint16_t reg_data;
109
110 /* Send command to NVRAM. */
111 nv_cmd <<= 5;
112 for (cnt = 0; cnt < 11; cnt++) {
113 if (nv_cmd & BIT_31)
114 qla2x00_nv_write(ha, NVR_DATA_OUT);
115 else
116 qla2x00_nv_write(ha, 0);
117 nv_cmd <<= 1;
118 }
119
120 /* Read data from NVRAM. */
121 for (cnt = 0; cnt < 16; cnt++) {
122 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
123 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
124 NVRAM_DELAY();
125 data <<= 1;
126 reg_data = RD_REG_WORD(&reg->nvram);
127 if (reg_data & NVR_DATA_IN)
128 data |= BIT_0;
129 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
130 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
131 NVRAM_DELAY();
132 }
133
134 /* Deselect chip. */
135 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
136 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
137 NVRAM_DELAY();
138
139 return data;
140}
141
142
1da177e4
LT		 143/**
144 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
145 * request routine to get the word from NVRAM.
146 * @ha: HA context
147 * @addr: Address in NVRAM to read
148 *
149 * Returns the word read from nvram @addr.
150 */
a824ebb3 151static uint16_t
7b867cf7 152qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr)
1da177e4
LT		 153{
154 uint16_t data;
155 uint32_t nv_cmd;
156
157 nv_cmd = addr << 16;
158 nv_cmd |= NV_READ_OP;
159 data = qla2x00_nvram_request(ha, nv_cmd);
160
161 return (data);
162}
163
7b867cf7
AC		 164/**
165 * qla2x00_nv_deselect() - Deselect NVRAM operations.
166 * @ha: HA context
167 */
168static void
169qla2x00_nv_deselect(struct qla_hw_data *ha)
170{
171 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
172
173 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
174 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
175 NVRAM_DELAY();
176}
177
1da177e4
LT		 178/**
179 * qla2x00_write_nvram_word() - Write NVRAM data.
180 * @ha: HA context
181 * @addr: Address in NVRAM to write
182 * @data: word to program
183 */
a824ebb3 184static void
7b867cf7 185qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data)
1da177e4
LT		 186{
187 int count;
188 uint16_t word;
45aeaf1e 189 uint32_t nv_cmd, wait_cnt;
3d71644c 190 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 191
192 qla2x00_nv_write(ha, NVR_DATA_OUT);
193 qla2x00_nv_write(ha, 0);
194 qla2x00_nv_write(ha, 0);
195
196 for (word = 0; word < 8; word++)
197 qla2x00_nv_write(ha, NVR_DATA_OUT);
198
199 qla2x00_nv_deselect(ha);
200
201 /* Write data */
202 nv_cmd = (addr << 16) | NV_WRITE_OP;
203 nv_cmd |= data;
204 nv_cmd <<= 5;
205 for (count = 0; count < 27; count++) {
206 if (nv_cmd & BIT_31)
207 qla2x00_nv_write(ha, NVR_DATA_OUT);
208 else
209 qla2x00_nv_write(ha, 0);
210
211 nv_cmd <<= 1;
212 }
213
214 qla2x00_nv_deselect(ha);
215
216 /* Wait for NVRAM to become ready */
217 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 218 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
45aeaf1e 219 wait_cnt = NVR_WAIT_CNT;
1da177e4 220 do {
45aeaf1e 221 if (!--wait_cnt) {
7640335e
AV		 222 DEBUG9_10(qla_printk(KERN_WARNING, ha,
223 "NVRAM didn't go ready...\n"));
45aeaf1e
RA		 224 break;
225 }
1da177e4
LT		 226 NVRAM_DELAY();
227 word = RD_REG_WORD(&reg->nvram);
228 } while ((word & NVR_DATA_IN) == 0);
229
230 qla2x00_nv_deselect(ha);
231
232 /* Disable writes */
233 qla2x00_nv_write(ha, NVR_DATA_OUT);
234 for (count = 0; count < 10; count++)
235 qla2x00_nv_write(ha, 0);
236
237 qla2x00_nv_deselect(ha);
238}
239
459c5378 240static int
7b867cf7
AC		 241qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr,
242 uint16_t data, uint32_t tmo)
459c5378
AV		 243{
244 int ret, count;
245 uint16_t word;
246 uint32_t nv_cmd;
247 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
248
249 ret = QLA_SUCCESS;
250
251 qla2x00_nv_write(ha, NVR_DATA_OUT);
252 qla2x00_nv_write(ha, 0);
253 qla2x00_nv_write(ha, 0);
254
255 for (word = 0; word < 8; word++)
256 qla2x00_nv_write(ha, NVR_DATA_OUT);
257
258 qla2x00_nv_deselect(ha);
259
260 /* Write data */
261 nv_cmd = (addr << 16) | NV_WRITE_OP;
262 nv_cmd |= data;
263 nv_cmd <<= 5;
264 for (count = 0; count < 27; count++) {
265 if (nv_cmd & BIT_31)
266 qla2x00_nv_write(ha, NVR_DATA_OUT);
267 else
268 qla2x00_nv_write(ha, 0);
269
270 nv_cmd <<= 1;
271 }
272
273 qla2x00_nv_deselect(ha);
274
275 /* Wait for NVRAM to become ready */
276 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 277 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
459c5378
AV		 278 do {
279 NVRAM_DELAY();
280 word = RD_REG_WORD(&reg->nvram);
281 if (!--tmo) {
282 ret = QLA_FUNCTION_FAILED;
283 break;
284 }
285 } while ((word & NVR_DATA_IN) == 0);
286
287 qla2x00_nv_deselect(ha);
288
289 /* Disable writes */
290 qla2x00_nv_write(ha, NVR_DATA_OUT);
291 for (count = 0; count < 10; count++)
292 qla2x00_nv_write(ha, 0);
293
294 qla2x00_nv_deselect(ha);
295
296 return ret;
297}
298
459c5378
AV		 299/**
300 * qla2x00_clear_nvram_protection() -
301 * @ha: HA context
302 */
303static int
7b867cf7 304qla2x00_clear_nvram_protection(struct qla_hw_data *ha)
459c5378
AV		 305{
306 int ret, stat;
307 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
45aeaf1e 308 uint32_t word, wait_cnt;
459c5378
AV		 309 uint16_t wprot, wprot_old;
310
311 /* Clear NVRAM write protection. */
312 ret = QLA_FUNCTION_FAILED;
45aeaf1e
RA		 313
314 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
315 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
459c5378 316 __constant_cpu_to_le16(0x1234), 100000);
45aeaf1e
RA		 317 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
318 if (stat != QLA_SUCCESS || wprot != 0x1234) {
459c5378
AV		 319 /* Write enable. */
320 qla2x00_nv_write(ha, NVR_DATA_OUT);
321 qla2x00_nv_write(ha, 0);
322 qla2x00_nv_write(ha, 0);
323 for (word = 0; word < 8; word++)
324 qla2x00_nv_write(ha, NVR_DATA_OUT);
325
326 qla2x00_nv_deselect(ha);
327
328 /* Enable protection register. */
329 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
330 qla2x00_nv_write(ha, NVR_PR_ENABLE);
331 qla2x00_nv_write(ha, NVR_PR_ENABLE);
332 for (word = 0; word < 8; word++)
333 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
334
335 qla2x00_nv_deselect(ha);
336
337 /* Clear protection register (ffff is cleared). */
338 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
339 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
340 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
341 for (word = 0; word < 8; word++)
342 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
343
344 qla2x00_nv_deselect(ha);
345
346 /* Wait for NVRAM to become ready. */
347 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 348 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
45aeaf1e 349 wait_cnt = NVR_WAIT_CNT;
459c5378 350 do {
45aeaf1e 351 if (!--wait_cnt) {
7640335e 352 DEBUG9_10(qla_printk(KERN_WARNING, ha,
7b867cf7 353 "NVRAM didn't go ready...\n"));
45aeaf1e
RA		 354 break;
355 }
459c5378
AV		 356 NVRAM_DELAY();
357 word = RD_REG_WORD(&reg->nvram);
358 } while ((word & NVR_DATA_IN) == 0);
359
45aeaf1e
RA		 360 if (wait_cnt)
361 ret = QLA_SUCCESS;
459c5378 362 } else
45aeaf1e 363 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
459c5378
AV		 364
365 return ret;
366}
367
368static void
7b867cf7 369qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat)
459c5378
AV		 370{
371 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
45aeaf1e 372 uint32_t word, wait_cnt;
459c5378
AV		 373
374 if (stat != QLA_SUCCESS)
375 return;
376
377 /* Set NVRAM write protection. */
378 /* Write enable. */
379 qla2x00_nv_write(ha, NVR_DATA_OUT);
380 qla2x00_nv_write(ha, 0);
381 qla2x00_nv_write(ha, 0);
382 for (word = 0; word < 8; word++)
383 qla2x00_nv_write(ha, NVR_DATA_OUT);
384
385 qla2x00_nv_deselect(ha);
386
387 /* Enable protection register. */
388 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
389 qla2x00_nv_write(ha, NVR_PR_ENABLE);
390 qla2x00_nv_write(ha, NVR_PR_ENABLE);
391 for (word = 0; word < 8; word++)
392 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
393
394 qla2x00_nv_deselect(ha);
395
396 /* Enable protection register. */
397 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
398 qla2x00_nv_write(ha, NVR_PR_ENABLE);
399 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
400 for (word = 0; word < 8; word++)
401 qla2x00_nv_write(ha, NVR_PR_ENABLE);
402
403 qla2x00_nv_deselect(ha);
404
405 /* Wait for NVRAM to become ready. */
406 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 407 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
45aeaf1e 408 wait_cnt = NVR_WAIT_CNT;
459c5378 409 do {
45aeaf1e 410 if (!--wait_cnt) {
7640335e
AV		 411 DEBUG9_10(qla_printk(KERN_WARNING, ha,
412 "NVRAM didn't go ready...\n"));
45aeaf1e
RA		 413 break;
414 }
459c5378
AV		 415 NVRAM_DELAY();
416 word = RD_REG_WORD(&reg->nvram);
417 } while ((word & NVR_DATA_IN) == 0);
418}
419
420
421/*****************************************************************************/
422/* Flash Manipulation Routines */
423/*****************************************************************************/
424
338c9161
AV		 425#define OPTROM_BURST_SIZE 0x1000
426#define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
427
459c5378 428static inline uint32_t
3a03eb79 429flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr)
459c5378 430{
3a03eb79 431 return ha->flash_conf_off | faddr;
459c5378
AV		 432}
433
434static inline uint32_t
3a03eb79 435flash_data_addr(struct qla_hw_data *ha, uint32_t faddr)
459c5378 436{
3a03eb79 437 return ha->flash_data_off | faddr;
459c5378
AV		 438}
439
440static inline uint32_t
3a03eb79 441nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr)
459c5378 442{
3a03eb79 443 return ha->nvram_conf_off | naddr;
459c5378
AV		 444}
445
446static inline uint32_t
3a03eb79 447nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr)
459c5378 448{
3a03eb79 449 return ha->nvram_data_off | naddr;
459c5378
AV		 450}
451
e5f82ab8 452static uint32_t
7b867cf7 453qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr)
459c5378
AV		 454{
455 int rval;
456 uint32_t cnt, data;
457 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
458
459 WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
460 /* Wait for READ cycle to complete. */
461 rval = QLA_SUCCESS;
462 for (cnt = 3000;
463 (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
464 rval == QLA_SUCCESS; cnt--) {
465 if (cnt)
466 udelay(10);
467 else
468 rval = QLA_FUNCTION_TIMEOUT;
40a2e34a 469 cond_resched();
459c5378
AV		 470 }
471
472 /* TODO: What happens if we time out? */
473 data = 0xDEADDEAD;
474 if (rval == QLA_SUCCESS)
475 data = RD_REG_DWORD(&reg->flash_data);
476
477 return data;
478}
479
480uint32_t *
7b867cf7 481qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
459c5378
AV		 482 uint32_t dwords)
483{
484 uint32_t i;
3a03eb79
AV		 485 struct qla_hw_data *ha = vha->hw;
486
459c5378
AV		 487 /* Dword reads to flash. */
488 for (i = 0; i < dwords; i++, faddr++)
3a03eb79
AV		 489 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
490 flash_data_addr(ha, faddr)));
459c5378 491
459c5378
AV		 492 return dwptr;
493}
494
e5f82ab8 495static int
7b867cf7 496qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data)
459c5378
AV		 497{
498 int rval;
499 uint32_t cnt;
500 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
501
502 WRT_REG_DWORD(&reg->flash_data, data);
503 RD_REG_DWORD(&reg->flash_data); /* PCI Posting. */
504 WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
505 /* Wait for Write cycle to complete. */
506 rval = QLA_SUCCESS;
507 for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
508 rval == QLA_SUCCESS; cnt--) {
509 if (cnt)
510 udelay(10);
511 else
512 rval = QLA_FUNCTION_TIMEOUT;
40a2e34a 513 cond_resched();
459c5378
AV		 514 }
515 return rval;
516}
517
e5f82ab8 518static void
7b867cf7 519qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
459c5378
AV		 520 uint8_t *flash_id)
521{
522 uint32_t ids;
523
3a03eb79 524 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x03ab));
459c5378
AV		 525 *man_id = LSB(ids);
526 *flash_id = MSB(ids);
45aeaf1e
RA		 527
528 /* Check if man_id and flash_id are valid. */
529 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
530 /* Read information using 0x9f opcode
531 * Device ID, Mfg ID would be read in the format:
532 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
533 * Example: ATMEL 0x00 01 45 1F
534 * Extract MFG and Dev ID from last two bytes.
535 */
3a03eb79 536 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x009f));
45aeaf1e
RA		 537 *man_id = LSB(ids);
538 *flash_id = MSB(ids);
539 }
459c5378
AV		 540}
541
c00d8994 542static int
7b867cf7 543qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
c00d8994
AV		 544{
545 const char *loc, *locations[] = { "DEF", "PCI" };
546 uint32_t pcihdr, pcids;
547 uint32_t *dcode;
548 uint8_t *buf, *bcode, last_image;
549 uint16_t cnt, chksum, *wptr;
550 struct qla_flt_location *fltl;
7b867cf7 551 struct qla_hw_data *ha = vha->hw;
73208dfd 552 struct req_que *req = ha->req_q_map[0];
c00d8994
AV		 553
554 /*
555 * FLT-location structure resides after the last PCI region.
556 */
557
558 /* Begin with sane defaults. */
559 loc = locations[0];
3a03eb79
AV		 560 *start = 0;
561 if (IS_QLA24XX_TYPE(ha))
562 *start = FA_FLASH_LAYOUT_ADDR_24;
563 else if (IS_QLA25XX(ha))
564 *start = FA_FLASH_LAYOUT_ADDR;
565 else if (IS_QLA81XX(ha))
566 *start = FA_FLASH_LAYOUT_ADDR_81;
c00d8994 567 /* Begin with first PCI expansion ROM header. */
7b867cf7
AC		 568 buf = (uint8_t *)req->ring;
569 dcode = (uint32_t *)req->ring;
c00d8994
AV		 570 pcihdr = 0;
571 last_image = 1;
572 do {
573 /* Verify PCI expansion ROM header. */
7b867cf7 574 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
c00d8994
AV		 575 bcode = buf + (pcihdr % 4);
576 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa)
577 goto end;
578
579 /* Locate PCI data structure. */
580 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
7b867cf7 581 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
c00d8994
AV		 582 bcode = buf + (pcihdr % 4);
583
584 /* Validate signature of PCI data structure. */
585 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
586 bcode[0x2] != 'I' || bcode[0x3] != 'R')
587 goto end;
588
589 last_image = bcode[0x15] & BIT_7;
590
591 /* Locate next PCI expansion ROM. */
592 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
593 } while (!last_image);
594
595 /* Now verify FLT-location structure. */
7b867cf7
AC		 596 fltl = (struct qla_flt_location *)req->ring;
597 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2,
c00d8994
AV		 598 sizeof(struct qla_flt_location) >> 2);
599 if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' ||
600 fltl->sig[2] != 'L' || fltl->sig[3] != 'T')
601 goto end;
602
7b867cf7 603 wptr = (uint16_t *)req->ring;
c00d8994
AV		 604 cnt = sizeof(struct qla_flt_location) >> 1;
605 for (chksum = 0; cnt; cnt--)
606 chksum += le16_to_cpu(*wptr++);
607 if (chksum) {
608 qla_printk(KERN_ERR, ha,
609 "Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
610 qla2x00_dump_buffer(buf, sizeof(struct qla_flt_location));
611 return QLA_FUNCTION_FAILED;
612 }
613
614 /* Good data. Use specified location. */
615 loc = locations[1];
79c13a74
HZ		 616 *start = (le16_to_cpu(fltl->start_hi) << 16 |
617 le16_to_cpu(fltl->start_lo)) >> 2;
c00d8994
AV		 618end:
619 DEBUG2(qla_printk(KERN_DEBUG, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
620 return QLA_SUCCESS;
621}
622
623static void
7b867cf7 624qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
c00d8994
AV		 625{
626 const char *loc, *locations[] = { "DEF", "FLT" };
3a03eb79
AV		 627 const uint32_t def_fw[] =
628 { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 };
629 const uint32_t def_boot[] =
630 { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 };
631 const uint32_t def_vpd_nvram[] =
632 { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 };
3d79038f
AV		 633 const uint32_t def_vpd0[] =
634 { 0, 0, FA_VPD0_ADDR_81 };
635 const uint32_t def_vpd1[] =
636 { 0, 0, FA_VPD1_ADDR_81 };
637 const uint32_t def_nvram0[] =
638 { 0, 0, FA_NVRAM0_ADDR_81 };
639 const uint32_t def_nvram1[] =
640 { 0, 0, FA_NVRAM1_ADDR_81 };
3a03eb79
AV		 641 const uint32_t def_fdt[] =
642 { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR,
643 FA_FLASH_DESCR_ADDR_81 };
644 const uint32_t def_npiv_conf0[] =
645 { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR,
646 FA_NPIV_CONF0_ADDR_81 };
647 const uint32_t def_npiv_conf1[] =
648 { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR,
649 FA_NPIV_CONF1_ADDR_81 };
650 uint32_t def;
c00d8994
AV		 651 uint16_t *wptr;
652 uint16_t cnt, chksum;
653 uint32_t start;
654 struct qla_flt_header *flt;
655 struct qla_flt_region *region;
7b867cf7 656 struct qla_hw_data *ha = vha->hw;
73208dfd 657 struct req_que *req = ha->req_q_map[0];
c00d8994
AV		 658
659 ha->flt_region_flt = flt_addr;
7b867cf7
AC		 660 wptr = (uint16_t *)req->ring;
661 flt = (struct qla_flt_header *)req->ring;
c00d8994 662 region = (struct qla_flt_region *)&flt[1];
7b867cf7 663 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
c00d8994
AV		 664 flt_addr << 2, OPTROM_BURST_SIZE);
665 if (*wptr == __constant_cpu_to_le16(0xffff))
666 goto no_flash_data;
667 if (flt->version != __constant_cpu_to_le16(1)) {
668 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported FLT detected: "
669 "version=0x%x length=0x%x checksum=0x%x.\n",
670 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
671 le16_to_cpu(flt->checksum)));
672 goto no_flash_data;
673 }
674
675 cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
676 for (chksum = 0; cnt; cnt--)
677 chksum += le16_to_cpu(*wptr++);
678 if (chksum) {
679 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
680 "version=0x%x length=0x%x checksum=0x%x.\n",
681 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
682 chksum));
683 goto no_flash_data;
684 }
685
686 loc = locations[1];
687 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
688 for ( ; cnt; cnt--, region++) {
689 /* Store addresses as DWORD offsets. */
690 start = le32_to_cpu(region->start) >> 2;
691
692 DEBUG3(qla_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
693 "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
694 le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
695
9088608e 696 switch (le32_to_cpu(region->code) & 0xff) {
c00d8994
AV		 697 case FLT_REG_FW:
698 ha->flt_region_fw = start;
699 break;
700 case FLT_REG_BOOT_CODE:
701 ha->flt_region_boot = start;
702 break;
703 case FLT_REG_VPD_0:
704 ha->flt_region_vpd_nvram = start;
e5b68a61 705 if (ha->flags.port0)
3d79038f
AV		 706 ha->flt_region_vpd = start;
707 break;
708 case FLT_REG_VPD_1:
e5b68a61 709 if (!ha->flags.port0)
3d79038f
AV		 710 ha->flt_region_vpd = start;
711 break;
712 case FLT_REG_NVRAM_0:
e5b68a61 713 if (ha->flags.port0)
3d79038f
AV		 714 ha->flt_region_nvram = start;
715 break;
716 case FLT_REG_NVRAM_1:
e5b68a61 717 if (!ha->flags.port0)
3d79038f 718 ha->flt_region_nvram = start;
c00d8994
AV		 719 break;
720 case FLT_REG_FDT:
721 ha->flt_region_fdt = start;
722 break;
272976ca 723 case FLT_REG_NPIV_CONF_0:
e5b68a61 724 if (ha->flags.port0)
272976ca
AV		 725 ha->flt_region_npiv_conf = start;
726 break;
727 case FLT_REG_NPIV_CONF_1:
e5b68a61 728 if (!ha->flags.port0)
272976ca
AV		 729 ha->flt_region_npiv_conf = start;
730 break;
c00d8994
AV		 731 }
732 }
733 goto done;
734
735no_flash_data:
736 /* Use hardcoded defaults. */
737 loc = locations[0];
3a03eb79
AV		 738 def = 0;
739 if (IS_QLA24XX_TYPE(ha))
740 def = 0;
741 else if (IS_QLA25XX(ha))
742 def = 1;
743 else if (IS_QLA81XX(ha))
744 def = 2;
745 ha->flt_region_fw = def_fw[def];
746 ha->flt_region_boot = def_boot[def];
747 ha->flt_region_vpd_nvram = def_vpd_nvram[def];
e5b68a61 748 ha->flt_region_vpd = ha->flags.port0 ?
3d79038f 749 def_vpd0[def]: def_vpd1[def];
e5b68a61 750 ha->flt_region_nvram = ha->flags.port0 ?
3d79038f 751 def_nvram0[def]: def_nvram1[def];
3a03eb79 752 ha->flt_region_fdt = def_fdt[def];
e5b68a61 753 ha->flt_region_npiv_conf = ha->flags.port0 ?
3a03eb79 754 def_npiv_conf0[def]: def_npiv_conf1[def];
c00d8994
AV		 755done:
756 DEBUG2(qla_printk(KERN_DEBUG, ha, "FLT[%s]: boot=0x%x fw=0x%x "
3d79038f
AV		 757 "vpd_nvram=0x%x vpd=0x%x nvram=0x%x fdt=0x%x flt=0x%x "
758 "npiv=0x%x.\n", loc, ha->flt_region_boot, ha->flt_region_fw,
759 ha->flt_region_vpd_nvram, ha->flt_region_vpd, ha->flt_region_nvram,
1ded85e2 760 ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf));
c00d8994
AV		 761}
762
763static void
7b867cf7 764qla2xxx_get_fdt_info(scsi_qla_host_t *vha)
7d232c74 765{
821b3996 766#define FLASH_BLK_SIZE_4K 0x1000
7d232c74
AV		 767#define FLASH_BLK_SIZE_32K 0x8000
768#define FLASH_BLK_SIZE_64K 0x10000
c00d8994 769 const char *loc, *locations[] = { "MID", "FDT" };
7d232c74
AV		 770 uint16_t cnt, chksum;
771 uint16_t *wptr;
772 struct qla_fdt_layout *fdt;
773 uint8_t man_id, flash_id;
c00d8994 774 uint16_t mid, fid;
7b867cf7 775 struct qla_hw_data *ha = vha->hw;
73208dfd 776 struct req_que *req = ha->req_q_map[0];
7d232c74 777
7b867cf7
AC		 778 wptr = (uint16_t *)req->ring;
779 fdt = (struct qla_fdt_layout *)req->ring;
780 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
c00d8994 781 ha->flt_region_fdt << 2, OPTROM_BURST_SIZE);
7d232c74
AV		 782 if (*wptr == __constant_cpu_to_le16(0xffff))
783 goto no_flash_data;
784 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
785 fdt->sig[3] != 'D')
786 goto no_flash_data;
787
788 for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
789 cnt++)
790 chksum += le16_to_cpu(*wptr++);
791 if (chksum) {
792 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
793 "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
794 le16_to_cpu(fdt->version)));
795 DEBUG9(qla2x00_dump_buffer((uint8_t *)fdt, sizeof(*fdt)));
796 goto no_flash_data;
797 }
798
c00d8994
AV		 799 loc = locations[1];
800 mid = le16_to_cpu(fdt->man_id);
801 fid = le16_to_cpu(fdt->id);
7d232c74 802 ha->fdt_wrt_disable = fdt->wrt_disable_bits;
3a03eb79 803 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0300 | fdt->erase_cmd);
7d232c74
AV		 804 ha->fdt_block_size = le32_to_cpu(fdt->block_size);
805 if (fdt->unprotect_sec_cmd) {
3a03eb79 806 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 |
7d232c74
AV		 807 fdt->unprotect_sec_cmd);
808 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
3a03eb79
AV		 809 flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd):
810 flash_conf_addr(ha, 0x0336);
7d232c74 811 }
c00d8994 812 goto done;
7d232c74 813no_flash_data:
c00d8994 814 loc = locations[0];
7d232c74 815 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
c00d8994
AV		 816 mid = man_id;
817 fid = flash_id;
7d232c74 818 ha->fdt_wrt_disable = 0x9c;
3a03eb79 819 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8);
7d232c74
AV		 820 switch (man_id) {
821 case 0xbf: /* STT flash. */
822 if (flash_id == 0x8e)
823 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
824 else
825 ha->fdt_block_size = FLASH_BLK_SIZE_32K;
826
827 if (flash_id == 0x80)
3a03eb79 828 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352);
7d232c74
AV		 829 break;
830 case 0x13: /* ST M25P80. */
831 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
832 break;
833 case 0x1f: /* Atmel 26DF081A. */
821b3996 834 ha->fdt_block_size = FLASH_BLK_SIZE_4K;
3a03eb79
AV		 835 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320);
836 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339);
837 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336);
7d232c74
AV		 838 break;
839 default:
840 /* Default to 64 kb sector size. */
841 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
842 break;
843 }
c00d8994
AV		 844done:
845 DEBUG2(qla_printk(KERN_DEBUG, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
821b3996 846 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
7d232c74 847 ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
821b3996 848 ha->fdt_unprotect_sec_cmd, ha->fdt_wrt_disable,
7d232c74
AV		 849 ha->fdt_block_size));
850}
851
c00d8994 852int
7b867cf7 853qla2xxx_get_flash_info(scsi_qla_host_t *vha)
c00d8994
AV		 854{
855 int ret;
856 uint32_t flt_addr;
7b867cf7 857 struct qla_hw_data *ha = vha->hw;
c00d8994 858
3a03eb79 859 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA81XX(ha))
c00d8994
AV		 860 return QLA_SUCCESS;
861
7b867cf7 862 ret = qla2xxx_find_flt_start(vha, &flt_addr);
c00d8994
AV		 863 if (ret != QLA_SUCCESS)
864 return ret;
865
7b867cf7
AC		 866 qla2xxx_get_flt_info(vha, flt_addr);
867 qla2xxx_get_fdt_info(vha);
c00d8994
AV		 868
869 return QLA_SUCCESS;
870}
871
272976ca 872void
7b867cf7 873qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
272976ca
AV		 874{
875#define NPIV_CONFIG_SIZE (16*1024)
876 void *data;
877 uint16_t *wptr;
878 uint16_t cnt, chksum;
73208dfd 879 int i;
272976ca
AV		 880 struct qla_npiv_header hdr;
881 struct qla_npiv_entry *entry;
7b867cf7 882 struct qla_hw_data *ha = vha->hw;
272976ca 883
3a03eb79 884 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA81XX(ha))
272976ca
AV		 885 return;
886
7b867cf7 887 ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr,
272976ca
AV		 888 ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header));
889 if (hdr.version == __constant_cpu_to_le16(0xffff))
890 return;
891 if (hdr.version != __constant_cpu_to_le16(1)) {
892 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported NPIV-Config "
893 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
894 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
895 le16_to_cpu(hdr.checksum)));
896 return;
897 }
898
899 data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL);
900 if (!data) {
901 DEBUG2(qla_printk(KERN_INFO, ha, "NPIV-Config: Unable to "
902 "allocate memory.\n"));
903 return;
904 }
905
7b867cf7 906 ha->isp_ops->read_optrom(vha, (uint8_t *)data,
272976ca
AV		 907 ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE);
908
909 cnt = (sizeof(struct qla_npiv_header) + le16_to_cpu(hdr.entries) *
910 sizeof(struct qla_npiv_entry)) >> 1;
911 for (wptr = data, chksum = 0; cnt; cnt--)
912 chksum += le16_to_cpu(*wptr++);
913 if (chksum) {
914 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent NPIV-Config "
915 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
916 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
917 chksum));
918 goto done;
919 }
920
921 entry = data + sizeof(struct qla_npiv_header);
922 cnt = le16_to_cpu(hdr.entries);
73208dfd 923 for (i = 0; cnt; cnt--, entry++, i++) {
272976ca
AV		 924 uint16_t flags;
925 struct fc_vport_identifiers vid;
926 struct fc_vport *vport;
927
40859ae5
AC		 928 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry));
929
272976ca
AV		 930 flags = le16_to_cpu(entry->flags);
931 if (flags == 0xffff)
932 continue;
933 if ((flags & BIT_0) == 0)
934 continue;
935
936 memset(&vid, 0, sizeof(vid));
937 vid.roles = FC_PORT_ROLE_FCP_INITIATOR;
938 vid.vport_type = FC_PORTTYPE_NPIV;
939 vid.disable = false;
940 vid.port_name = wwn_to_u64(entry->port_name);
941 vid.node_name = wwn_to_u64(entry->node_name);
942
40859ae5 943 DEBUG2(qla_printk(KERN_INFO, ha, "NPIV[%02x]: wwpn=%llx "
73208dfd
AC		 944 "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt,
945 vid.port_name, vid.node_name, le16_to_cpu(entry->vf_id),
946 entry->q_qos, entry->f_qos));
947
948 if (i < QLA_PRECONFIG_VPORTS) {
949 vport = fc_vport_create(vha->host, 0, &vid);
950 if (!vport)
951 qla_printk(KERN_INFO, ha,
952 "NPIV-Config: Failed to create vport [%02x]: "
953 "wwpn=%llx wwnn=%llx.\n", cnt,
954 vid.port_name, vid.node_name);
955 }
272976ca
AV		 956 }
957done:
958 kfree(data);
959}
960
1d2874de
JC		 961static int
962qla24xx_unprotect_flash(scsi_qla_host_t *vha)
cb8dacbf 963{
1d2874de 964 struct qla_hw_data *ha = vha->hw;
cb8dacbf
AV		 965 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
966
1d2874de
JC		 967 if (ha->flags.fac_supported)
968 return qla81xx_fac_do_write_enable(vha, 1);
969
cb8dacbf
AV		 970 /* Enable flash write. */
971 WRT_REG_DWORD(&reg->ctrl_status,
972 RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
973 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
974
7d232c74 975 if (!ha->fdt_wrt_disable)
1d2874de 976 goto done;
7d232c74 977
b872ca40 978 /* Disable flash write-protection, first clear SR protection bit */
3a03eb79 979 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
b872ca40 980 /* Then write zero again to clear remaining SR bits.*/
3a03eb79 981 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
1d2874de
JC		 982done:
983 return QLA_SUCCESS;
cb8dacbf
AV		 984}
985
1d2874de
JC		 986static int
987qla24xx_protect_flash(scsi_qla_host_t *vha)
cb8dacbf
AV		 988{
989 uint32_t cnt;
1d2874de 990 struct qla_hw_data *ha = vha->hw;
cb8dacbf
AV		 991 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
992
1d2874de
JC		 993 if (ha->flags.fac_supported)
994 return qla81xx_fac_do_write_enable(vha, 0);
995
7d232c74
AV		 996 if (!ha->fdt_wrt_disable)
997 goto skip_wrt_protect;
998
cb8dacbf 999 /* Enable flash write-protection and wait for completion. */
3a03eb79 1000 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101),
7d232c74 1001 ha->fdt_wrt_disable);
cb8dacbf 1002 for (cnt = 300; cnt &&
3a03eb79 1003 qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x005)) & BIT_0;
cb8dacbf
AV		 1004 cnt--) {
1005 udelay(10);
1006 }
1007
7d232c74 1008skip_wrt_protect:
cb8dacbf
AV		 1009 /* Disable flash write. */
1010 WRT_REG_DWORD(&reg->ctrl_status,
1011 RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1012 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1d2874de
JC		 1013
1014 return QLA_SUCCESS;
1015}
1016
1017static int
1018qla24xx_erase_sector(scsi_qla_host_t *vha, uint32_t fdata)
1019{
1020 struct qla_hw_data *ha = vha->hw;
1021 uint32_t start, finish;
1022
1023 if (ha->flags.fac_supported) {
1024 start = fdata >> 2;
1025 finish = start + (ha->fdt_block_size >> 2) - 1;
1026 return qla81xx_fac_erase_sector(vha, flash_data_addr(ha,
1027 start), flash_data_addr(ha, finish));
1028 }
1029
1030 return qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd,
1031 (fdata & 0xff00) | ((fdata << 16) & 0xff0000) |
1032 ((fdata >> 16) & 0xff));
cb8dacbf
AV		 1033}
1034
e5f82ab8 1035static int
7b867cf7 1036qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
459c5378
AV		 1037 uint32_t dwords)
1038{
1039 int ret;
7c283177 1040 uint32_t liter;
7d232c74 1041 uint32_t sec_mask, rest_addr;
85d0acbb 1042 uint32_t fdata;
338c9161
AV		 1043 dma_addr_t optrom_dma;
1044 void *optrom = NULL;
7b867cf7 1045 struct qla_hw_data *ha = vha->hw;
459c5378 1046
338c9161 1047 /* Prepare burst-capable write on supported ISPs. */
3a03eb79 1048 if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && !(faddr & 0xfff) &&
338c9161
AV		 1049 dwords > OPTROM_BURST_DWORDS) {
1050 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1051 &optrom_dma, GFP_KERNEL);
1052 if (!optrom) {
1053 qla_printk(KERN_DEBUG, ha,
1054 "Unable to allocate memory for optrom burst write "
1055 "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
1056 }
1057 }
1058
7d232c74 1059 rest_addr = (ha->fdt_block_size >> 2) - 1;
85d0acbb 1060 sec_mask = ~rest_addr;
459c5378 1061
1d2874de
JC		 1062 ret = qla24xx_unprotect_flash(vha);
1063 if (ret != QLA_SUCCESS) {
1064 qla_printk(KERN_WARNING, ha,
1065 "Unable to unprotect flash for update.\n");
1066 goto done;
1067 }
459c5378 1068
338c9161 1069 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
85d0acbb 1070 fdata = (faddr & sec_mask) << 2;
45aeaf1e 1071
338c9161 1072 /* Are we at the beginning of a sector? */
85d0acbb 1073 if ((faddr & rest_addr) == 0) {
7d232c74
AV		 1074 /* Do sector unprotect. */
1075 if (ha->fdt_unprotect_sec_cmd)
338c9161 1076 qla24xx_write_flash_dword(ha,
7d232c74 1077 ha->fdt_unprotect_sec_cmd,
338c9161 1078 (fdata & 0xff00) | ((fdata << 16) &
459c5378 1079 0xff0000) | ((fdata >> 16) & 0xff));
1d2874de 1080 ret = qla24xx_erase_sector(vha, fdata);
338c9161 1081 if (ret != QLA_SUCCESS) {
7640335e
AV		 1082 DEBUG9(qla_printk(KERN_WARNING, ha,
1083 "Unable to erase sector: address=%x.\n",
1084 faddr));
338c9161 1085 break;
459c5378 1086 }
338c9161
AV		 1087 }
1088
1089 /* Go with burst-write. */
94d6a2b3 1090 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
338c9161 1091 /* Copy data to DMA'ble buffer. */
7c283177 1092 memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
338c9161 1093
7b867cf7 1094 ret = qla2x00_load_ram(vha, optrom_dma,
3a03eb79 1095 flash_data_addr(ha, faddr),
338c9161 1096 OPTROM_BURST_DWORDS);
459c5378 1097 if (ret != QLA_SUCCESS) {
338c9161
AV		 1098 qla_printk(KERN_WARNING, ha,
1099 "Unable to burst-write optrom segment "
1100 "(%x/%x/%llx).\n", ret,
3a03eb79 1101 flash_data_addr(ha, faddr),
875baf3c 1102 (unsigned long long)optrom_dma);
338c9161
AV		 1103 qla_printk(KERN_WARNING, ha,
1104 "Reverting to slow-write.\n");
1105
1106 dma_free_coherent(&ha->pdev->dev,
1107 OPTROM_BURST_SIZE, optrom, optrom_dma);
1108 optrom = NULL;
1109 } else {
1110 liter += OPTROM_BURST_DWORDS - 1;
1111 faddr += OPTROM_BURST_DWORDS - 1;
1112 dwptr += OPTROM_BURST_DWORDS - 1;
1113 continue;
459c5378 1114 }
338c9161 1115 }
45aeaf1e 1116
338c9161 1117 ret = qla24xx_write_flash_dword(ha,
3a03eb79 1118 flash_data_addr(ha, faddr), cpu_to_le32(*dwptr));
338c9161
AV		 1119 if (ret != QLA_SUCCESS) {
1120 DEBUG9(printk("%s(%ld) Unable to program flash "
1121 "address=%x data=%x.\n", __func__,
7b867cf7 1122 vha->host_no, faddr, *dwptr));
338c9161 1123 break;
459c5378 1124 }
338c9161 1125
7d232c74
AV		 1126 /* Do sector protect. */
1127 if (ha->fdt_unprotect_sec_cmd &&
338c9161
AV		 1128 ((faddr & rest_addr) == rest_addr))
1129 qla24xx_write_flash_dword(ha,
7d232c74 1130 ha->fdt_protect_sec_cmd,
338c9161
AV		 1131 (fdata & 0xff00) | ((fdata << 16) &
1132 0xff0000) | ((fdata >> 16) & 0xff));
1133 }
459c5378 1134
1d2874de
JC		 1135 ret = qla24xx_protect_flash(vha);
1136 if (ret != QLA_SUCCESS)
1137 qla_printk(KERN_WARNING, ha,
1138 "Unable to protect flash after update.\n");
1139done:
338c9161
AV		 1140 if (optrom)
1141 dma_free_coherent(&ha->pdev->dev,
1142 OPTROM_BURST_SIZE, optrom, optrom_dma);
1143
459c5378
AV		 1144 return ret;
1145}
1146
1147uint8_t *
7b867cf7 1148qla2x00_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
459c5378
AV		 1149 uint32_t bytes)
1150{
1151 uint32_t i;
1152 uint16_t *wptr;
7b867cf7 1153 struct qla_hw_data *ha = vha->hw;
459c5378
AV		 1154
1155 /* Word reads to NVRAM via registers. */
1156 wptr = (uint16_t *)buf;
1157 qla2x00_lock_nvram_access(ha);
1158 for (i = 0; i < bytes >> 1; i++, naddr++)
1159 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
1160 naddr));
1161 qla2x00_unlock_nvram_access(ha);
1162
1163 return buf;
1164}
1165
1166uint8_t *
7b867cf7 1167qla24xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
459c5378
AV		 1168 uint32_t bytes)
1169{
1170 uint32_t i;
1171 uint32_t *dwptr;
3a03eb79 1172 struct qla_hw_data *ha = vha->hw;
459c5378
AV		 1173
1174 /* Dword reads to flash. */
1175 dwptr = (uint32_t *)buf;
1176 for (i = 0; i < bytes >> 2; i++, naddr++)
3a03eb79
AV		 1177 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1178 nvram_data_addr(ha, naddr)));
459c5378 1179
459c5378
AV		 1180 return buf;
1181}
1182
1183int
7b867cf7 1184qla2x00_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
459c5378
AV		 1185 uint32_t bytes)
1186{
1187 int ret, stat;
1188 uint32_t i;
1189 uint16_t *wptr;
2c96d8d0 1190 unsigned long flags;
7b867cf7 1191 struct qla_hw_data *ha = vha->hw;
459c5378
AV		 1192
1193 ret = QLA_SUCCESS;
1194
2c96d8d0 1195 spin_lock_irqsave(&ha->hardware_lock, flags);
459c5378
AV		 1196 qla2x00_lock_nvram_access(ha);
1197
1198 /* Disable NVRAM write-protection. */
1199 stat = qla2x00_clear_nvram_protection(ha);
1200
1201 wptr = (uint16_t *)buf;
1202 for (i = 0; i < bytes >> 1; i++, naddr++) {
1203 qla2x00_write_nvram_word(ha, naddr,
1204 cpu_to_le16(*wptr));
1205 wptr++;
1206 }
1207
1208 /* Enable NVRAM write-protection. */
1209 qla2x00_set_nvram_protection(ha, stat);
1210
1211 qla2x00_unlock_nvram_access(ha);
2c96d8d0 1212 spin_unlock_irqrestore(&ha->hardware_lock, flags);
459c5378
AV		 1213
1214 return ret;
1215}
1216
1217int
7b867cf7 1218qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
459c5378
AV		 1219 uint32_t bytes)
1220{
1221 int ret;
1222 uint32_t i;
1223 uint32_t *dwptr;
7b867cf7 1224 struct qla_hw_data *ha = vha->hw;
459c5378
AV		 1225 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1226
1227 ret = QLA_SUCCESS;
1228
459c5378
AV		 1229 /* Enable flash write. */
1230 WRT_REG_DWORD(&reg->ctrl_status,
1231 RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1232 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1233
1234 /* Disable NVRAM write-protection. */
3a03eb79
AV		 1235 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1236 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
459c5378
AV		 1237
1238 /* Dword writes to flash. */
1239 dwptr = (uint32_t *)buf;
1240 for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
1241 ret = qla24xx_write_flash_dword(ha,
3a03eb79 1242 nvram_data_addr(ha, naddr), cpu_to_le32(*dwptr));
459c5378 1243 if (ret != QLA_SUCCESS) {
7640335e
AV		 1244 DEBUG9(qla_printk(KERN_WARNING, ha,
1245 "Unable to program nvram address=%x data=%x.\n",
1246 naddr, *dwptr));
459c5378
AV		 1247 break;
1248 }
1249 }
1250
1251 /* Enable NVRAM write-protection. */
3a03eb79 1252 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c);
459c5378
AV		 1253
1254 /* Disable flash write. */
1255 WRT_REG_DWORD(&reg->ctrl_status,
1256 RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1257 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1258
459c5378
AV		 1259 return ret;
1260}
f6df144c 1261
c3a2f0df 1262uint8_t *
7b867cf7 1263qla25xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
c3a2f0df
AV		 1264 uint32_t bytes)
1265{
1266 uint32_t i;
1267 uint32_t *dwptr;
7b867cf7 1268 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 1269
1270 /* Dword reads to flash. */
1271 dwptr = (uint32_t *)buf;
1272 for (i = 0; i < bytes >> 2; i++, naddr++)
1273 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
3a03eb79 1274 flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr)));
c3a2f0df
AV		 1275
1276 return buf;
1277}
1278
1279int
7b867cf7 1280qla25xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
c3a2f0df
AV		 1281 uint32_t bytes)
1282{
7b867cf7 1283 struct qla_hw_data *ha = vha->hw;
2c96d8d0
AV		 1284#define RMW_BUFFER_SIZE (64 * 1024)
1285 uint8_t *dbuf;
1286
1287 dbuf = vmalloc(RMW_BUFFER_SIZE);
1288 if (!dbuf)
1289 return QLA_MEMORY_ALLOC_FAILED;
7b867cf7 1290 ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
2c96d8d0
AV		 1291 RMW_BUFFER_SIZE);
1292 memcpy(dbuf + (naddr << 2), buf, bytes);
7b867cf7 1293 ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
2c96d8d0
AV		 1294 RMW_BUFFER_SIZE);
1295 vfree(dbuf);
1296
1297 return QLA_SUCCESS;
c3a2f0df 1298}
f6df144c 1299
1300static inline void
7b867cf7 1301qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
f6df144c 1302{
1303 if (IS_QLA2322(ha)) {
1304 /* Flip all colors. */
1305 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1306 /* Turn off. */
1307 ha->beacon_color_state = 0;
1308 *pflags = GPIO_LED_ALL_OFF;
1309 } else {
1310 /* Turn on. */
1311 ha->beacon_color_state = QLA_LED_ALL_ON;
1312 *pflags = GPIO_LED_RGA_ON;
1313 }
1314 } else {
1315 /* Flip green led only. */
1316 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
1317 /* Turn off. */
1318 ha->beacon_color_state = 0;
1319 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
1320 } else {
1321 /* Turn on. */
1322 ha->beacon_color_state = QLA_LED_GRN_ON;
1323 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
1324 }
1325 }
1326}
1327
948882f6
AV		 1328#define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1329
f6df144c 1330void
7b867cf7 1331qla2x00_beacon_blink(struct scsi_qla_host *vha)
f6df144c 1332{
1333 uint16_t gpio_enable;
1334 uint16_t gpio_data;
1335 uint16_t led_color = 0;
1336 unsigned long flags;
7b867cf7 1337 struct qla_hw_data *ha = vha->hw;
f6df144c 1338 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1339
f6df144c 1340 spin_lock_irqsave(&ha->hardware_lock, flags);
1341
1342 /* Save the Original GPIOE. */
1343 if (ha->pio_address) {
948882f6
AV		 1344 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1345 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
f6df144c 1346 } else {
1347 gpio_enable = RD_REG_WORD(&reg->gpioe);
1348 gpio_data = RD_REG_WORD(&reg->gpiod);
1349 }
1350
1351 /* Set the modified gpio_enable values */
1352 gpio_enable |= GPIO_LED_MASK;
1353
1354 if (ha->pio_address) {
948882f6 1355 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
f6df144c 1356 } else {
1357 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1358 RD_REG_WORD(&reg->gpioe);
1359 }
1360
1361 qla2x00_flip_colors(ha, &led_color);
1362
1363 /* Clear out any previously set LED color. */
1364 gpio_data &= ~GPIO_LED_MASK;
1365
1366 /* Set the new input LED color to GPIOD. */
1367 gpio_data |= led_color;
1368
1369 /* Set the modified gpio_data values */
1370 if (ha->pio_address) {
948882f6 1371 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
f6df144c 1372 } else {
1373 WRT_REG_WORD(&reg->gpiod, gpio_data);
1374 RD_REG_WORD(&reg->gpiod);
1375 }
1376
1377 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1378}
1379
1380int
7b867cf7 1381qla2x00_beacon_on(struct scsi_qla_host *vha)
f6df144c 1382{
1383 uint16_t gpio_enable;
1384 uint16_t gpio_data;
1385 unsigned long flags;
7b867cf7 1386 struct qla_hw_data *ha = vha->hw;
f6df144c 1387 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1388
1389 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1390 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
1391
7b867cf7 1392 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
f6df144c 1393 qla_printk(KERN_WARNING, ha,
1394 "Unable to update fw options (beacon on).\n");
1395 return QLA_FUNCTION_FAILED;
1396 }
1397
f6df144c 1398 /* Turn off LEDs. */
1399 spin_lock_irqsave(&ha->hardware_lock, flags);
1400 if (ha->pio_address) {
948882f6
AV		 1401 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1402 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
f6df144c 1403 } else {
1404 gpio_enable = RD_REG_WORD(&reg->gpioe);
1405 gpio_data = RD_REG_WORD(&reg->gpiod);
1406 }
1407 gpio_enable |= GPIO_LED_MASK;
1408
1409 /* Set the modified gpio_enable values. */
1410 if (ha->pio_address) {
948882f6 1411 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
f6df144c 1412 } else {
1413 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1414 RD_REG_WORD(&reg->gpioe);
1415 }
1416
1417 /* Clear out previously set LED colour. */
1418 gpio_data &= ~GPIO_LED_MASK;
1419 if (ha->pio_address) {
948882f6 1420 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
f6df144c 1421 } else {
1422 WRT_REG_WORD(&reg->gpiod, gpio_data);
1423 RD_REG_WORD(&reg->gpiod);
1424 }
1425 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1426
1427 /*
1428 * Let the per HBA timer kick off the blinking process based on
1429 * the following flags. No need to do anything else now.
1430 */
1431 ha->beacon_blink_led = 1;
1432 ha->beacon_color_state = 0;
1433
1434 return QLA_SUCCESS;
1435}
1436
1437int
7b867cf7 1438qla2x00_beacon_off(struct scsi_qla_host *vha)
f6df144c 1439{
1440 int rval = QLA_SUCCESS;
7b867cf7 1441 struct qla_hw_data *ha = vha->hw;
f6df144c 1442
1443 ha->beacon_blink_led = 0;
1444
1445 /* Set the on flag so when it gets flipped it will be off. */
1446 if (IS_QLA2322(ha))
1447 ha->beacon_color_state = QLA_LED_ALL_ON;
1448 else
1449 ha->beacon_color_state = QLA_LED_GRN_ON;
1450
7b867cf7 1451 ha->isp_ops->beacon_blink(vha); /* This turns green LED off */
f6df144c 1452
1453 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1454 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1455
7b867cf7 1456 rval = qla2x00_set_fw_options(vha, ha->fw_options);
f6df144c 1457 if (rval != QLA_SUCCESS)
1458 qla_printk(KERN_WARNING, ha,
1459 "Unable to update fw options (beacon off).\n");
1460 return rval;
1461}
1462
1463
1464static inline void
7b867cf7 1465qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
f6df144c 1466{
1467 /* Flip all colors. */
1468 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1469 /* Turn off. */
1470 ha->beacon_color_state = 0;
1471 *pflags = 0;
1472 } else {
1473 /* Turn on. */
1474 ha->beacon_color_state = QLA_LED_ALL_ON;
1475 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1476 }
1477}
1478
1479void
7b867cf7 1480qla24xx_beacon_blink(struct scsi_qla_host *vha)
f6df144c 1481{
1482 uint16_t led_color = 0;
1483 uint32_t gpio_data;
1484 unsigned long flags;
7b867cf7 1485 struct qla_hw_data *ha = vha->hw;
f6df144c 1486 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1487
1488 /* Save the Original GPIOD. */
1489 spin_lock_irqsave(&ha->hardware_lock, flags);
1490 gpio_data = RD_REG_DWORD(&reg->gpiod);
1491
1492 /* Enable the gpio_data reg for update. */
1493 gpio_data |= GPDX_LED_UPDATE_MASK;
1494
1495 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1496 gpio_data = RD_REG_DWORD(&reg->gpiod);
1497
1498 /* Set the color bits. */
1499 qla24xx_flip_colors(ha, &led_color);
1500
1501 /* Clear out any previously set LED color. */
1502 gpio_data &= ~GPDX_LED_COLOR_MASK;
1503
1504 /* Set the new input LED color to GPIOD. */
1505 gpio_data |= led_color;
1506
1507 /* Set the modified gpio_data values. */
1508 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1509 gpio_data = RD_REG_DWORD(&reg->gpiod);
1510 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1511}
1512
1513int
7b867cf7 1514qla24xx_beacon_on(struct scsi_qla_host *vha)
f6df144c 1515{
1516 uint32_t gpio_data;
1517 unsigned long flags;
7b867cf7 1518 struct qla_hw_data *ha = vha->hw;
f6df144c 1519 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1520
1521 if (ha->beacon_blink_led == 0) {
1522 /* Enable firmware for update */
1523 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1524
7b867cf7 1525 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS)
f6df144c 1526 return QLA_FUNCTION_FAILED;
1527
7b867cf7 1528 if (qla2x00_get_fw_options(vha, ha->fw_options) !=
f6df144c 1529 QLA_SUCCESS) {
1530 qla_printk(KERN_WARNING, ha,
1531 "Unable to update fw options (beacon on).\n");
1532 return QLA_FUNCTION_FAILED;
1533 }
1534
1535 spin_lock_irqsave(&ha->hardware_lock, flags);
1536 gpio_data = RD_REG_DWORD(&reg->gpiod);
1537
1538 /* Enable the gpio_data reg for update. */
1539 gpio_data |= GPDX_LED_UPDATE_MASK;
1540 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1541 RD_REG_DWORD(&reg->gpiod);
1542
1543 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1544 }
1545
1546 /* So all colors blink together. */
1547 ha->beacon_color_state = 0;
1548
1549 /* Let the per HBA timer kick off the blinking process. */
1550 ha->beacon_blink_led = 1;
1551
1552 return QLA_SUCCESS;
1553}
1554
1555int
7b867cf7 1556qla24xx_beacon_off(struct scsi_qla_host *vha)
f6df144c 1557{
1558 uint32_t gpio_data;
1559 unsigned long flags;
7b867cf7 1560 struct qla_hw_data *ha = vha->hw;
f6df144c 1561 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1562
1563 ha->beacon_blink_led = 0;
1564 ha->beacon_color_state = QLA_LED_ALL_ON;
1565
7b867cf7 1566 ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */
f6df144c 1567
1568 /* Give control back to firmware. */
1569 spin_lock_irqsave(&ha->hardware_lock, flags);
1570 gpio_data = RD_REG_DWORD(&reg->gpiod);
1571
1572 /* Disable the gpio_data reg for update. */
1573 gpio_data &= ~GPDX_LED_UPDATE_MASK;
1574 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1575 RD_REG_DWORD(&reg->gpiod);
1576 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1577
1578 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1579
7b867cf7 1580 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
f6df144c 1581 qla_printk(KERN_WARNING, ha,
1582 "Unable to update fw options (beacon off).\n");
1583 return QLA_FUNCTION_FAILED;
1584 }
1585
7b867cf7 1586 if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
f6df144c 1587 qla_printk(KERN_WARNING, ha,
1588 "Unable to get fw options (beacon off).\n");
1589 return QLA_FUNCTION_FAILED;
1590 }
1591
1592 return QLA_SUCCESS;
1593}
854165f4 1594
1595
1596/*
1597 * Flash support routines
1598 */
1599
1600/**
1601 * qla2x00_flash_enable() - Setup flash for reading and writing.
1602 * @ha: HA context
1603 */
1604static void
7b867cf7 1605qla2x00_flash_enable(struct qla_hw_data *ha)
854165f4 1606{
1607 uint16_t data;
1608 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1609
1610 data = RD_REG_WORD(&reg->ctrl_status);
1611 data |= CSR_FLASH_ENABLE;
1612 WRT_REG_WORD(&reg->ctrl_status, data);
1613 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1614}
1615
1616/**
1617 * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1618 * @ha: HA context
1619 */
1620static void
7b867cf7 1621qla2x00_flash_disable(struct qla_hw_data *ha)
854165f4 1622{
1623 uint16_t data;
1624 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1625
1626 data = RD_REG_WORD(&reg->ctrl_status);
1627 data &= ~(CSR_FLASH_ENABLE);
1628 WRT_REG_WORD(&reg->ctrl_status, data);
1629 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1630}
1631
1632/**
1633 * qla2x00_read_flash_byte() - Reads a byte from flash
1634 * @ha: HA context
1635 * @addr: Address in flash to read
1636 *
1637 * A word is read from the chip, but, only the lower byte is valid.
1638 *
1639 * Returns the byte read from flash @addr.
1640 */
1641static uint8_t
7b867cf7 1642qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr)
854165f4 1643{
1644 uint16_t data;
1645 uint16_t bank_select;
1646 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1647
1648 bank_select = RD_REG_WORD(&reg->ctrl_status);
1649
1650 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1651 /* Specify 64K address range: */
1652 /* clear out Module Select and Flash Address bits [19:16]. */
1653 bank_select &= ~0xf8;
1654 bank_select |= addr >> 12 & 0xf0;
1655 bank_select |= CSR_FLASH_64K_BANK;
1656 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1657 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1658
1659 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1660 data = RD_REG_WORD(&reg->flash_data);
1661
1662 return (uint8_t)data;
1663 }
1664
1665 /* Setup bit 16 of flash address. */
1666 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1667 bank_select |= CSR_FLASH_64K_BANK;
1668 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1669 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1670 } else if (((addr & BIT_16) == 0) &&
1671 (bank_select & CSR_FLASH_64K_BANK)) {
1672 bank_select &= ~(CSR_FLASH_64K_BANK);
1673 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1674 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1675 }
1676
1677 /* Always perform IO mapped accesses to the FLASH registers. */
1678 if (ha->pio_address) {
1679 uint16_t data2;
1680
948882f6 1681 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
854165f4 1682 do {
948882f6 1683 data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
854165f4 1684 barrier();
1685 cpu_relax();
948882f6 1686 data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
854165f4 1687 } while (data != data2);
1688 } else {
1689 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1690 data = qla2x00_debounce_register(&reg->flash_data);
1691 }
1692
1693 return (uint8_t)data;
1694}
1695
1696/**
1697 * qla2x00_write_flash_byte() - Write a byte to flash
1698 * @ha: HA context
1699 * @addr: Address in flash to write
1700 * @data: Data to write
1701 */
1702static void
7b867cf7 1703qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data)
854165f4 1704{
1705 uint16_t bank_select;
1706 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1707
1708 bank_select = RD_REG_WORD(&reg->ctrl_status);
1709 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1710 /* Specify 64K address range: */
1711 /* clear out Module Select and Flash Address bits [19:16]. */
1712 bank_select &= ~0xf8;
1713 bank_select |= addr >> 12 & 0xf0;
1714 bank_select |= CSR_FLASH_64K_BANK;
1715 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1716 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1717
1718 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1719 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1720 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1721 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1722
1723 return;
1724 }
1725
1726 /* Setup bit 16 of flash address. */
1727 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1728 bank_select |= CSR_FLASH_64K_BANK;
1729 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1730 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1731 } else if (((addr & BIT_16) == 0) &&
1732 (bank_select & CSR_FLASH_64K_BANK)) {
1733 bank_select &= ~(CSR_FLASH_64K_BANK);
1734 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1735 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1736 }
1737
1738 /* Always perform IO mapped accesses to the FLASH registers. */
1739 if (ha->pio_address) {
948882f6
AV		 1740 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1741 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
854165f4 1742 } else {
1743 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1744 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1745 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1746 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1747 }
1748}
1749
1750/**
1751 * qla2x00_poll_flash() - Polls flash for completion.
1752 * @ha: HA context
1753 * @addr: Address in flash to poll
1754 * @poll_data: Data to be polled
1755 * @man_id: Flash manufacturer ID
1756 * @flash_id: Flash ID
1757 *
1758 * This function polls the device until bit 7 of what is read matches data
1759 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed
1760 * out (a fatal error). The flash book recommeds reading bit 7 again after
1761 * reading bit 5 as a 1.
1762 *
1763 * Returns 0 on success, else non-zero.
1764 */
1765static int
7b867cf7 1766qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data,
854165f4 1767 uint8_t man_id, uint8_t flash_id)
1768{
1769 int status;
1770 uint8_t flash_data;
1771 uint32_t cnt;
1772
1773 status = 1;
1774
1775 /* Wait for 30 seconds for command to finish. */
1776 poll_data &= BIT_7;
1777 for (cnt = 3000000; cnt; cnt--) {
1778 flash_data = qla2x00_read_flash_byte(ha, addr);
1779 if ((flash_data & BIT_7) == poll_data) {
1780 status = 0;
1781 break;
1782 }
1783
1784 if (man_id != 0x40 && man_id != 0xda) {
1785 if ((flash_data & BIT_5) && cnt > 2)
1786 cnt = 2;
1787 }
1788 udelay(10);
1789 barrier();
40a2e34a 1790 cond_resched();
854165f4 1791 }
1792 return status;
1793}
1794
854165f4 1795/**
1796 * qla2x00_program_flash_address() - Programs a flash address
1797 * @ha: HA context
1798 * @addr: Address in flash to program
1799 * @data: Data to be written in flash
1800 * @man_id: Flash manufacturer ID
1801 * @flash_id: Flash ID
1802 *
1803 * Returns 0 on success, else non-zero.
1804 */
1805static int
7b867cf7
AC		 1806qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr,
1807 uint8_t data, uint8_t man_id, uint8_t flash_id)
854165f4 1808{
1809 /* Write Program Command Sequence. */
1810 if (IS_OEM_001(ha)) {
1811 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1812 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1813 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
1814 qla2x00_write_flash_byte(ha, addr, data);
1815 } else {
1816 if (man_id == 0xda && flash_id == 0xc1) {
1817 qla2x00_write_flash_byte(ha, addr, data);
1818 if (addr & 0x7e)
1819 return 0;
1820 } else {
1821 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1822 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1823 qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
1824 qla2x00_write_flash_byte(ha, addr, data);
1825 }
1826 }
1827
1828 udelay(150);
1829
1830 /* Wait for write to complete. */
1831 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
1832}
1833
1834/**
1835 * qla2x00_erase_flash() - Erase the flash.
1836 * @ha: HA context
1837 * @man_id: Flash manufacturer ID
1838 * @flash_id: Flash ID
1839 *
1840 * Returns 0 on success, else non-zero.
1841 */
1842static int
7b867cf7 1843qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id)
854165f4 1844{
1845 /* Individual Sector Erase Command Sequence */
1846 if (IS_OEM_001(ha)) {
1847 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1848 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1849 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
1850 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1851 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1852 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
1853 } else {
1854 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1855 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1856 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1857 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1858 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1859 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
1860 }
1861
1862 udelay(150);
1863
1864 /* Wait for erase to complete. */
1865 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
1866}
1867
1868/**
1869 * qla2x00_erase_flash_sector() - Erase a flash sector.
1870 * @ha: HA context
1871 * @addr: Flash sector to erase
1872 * @sec_mask: Sector address mask
1873 * @man_id: Flash manufacturer ID
1874 * @flash_id: Flash ID
1875 *
1876 * Returns 0 on success, else non-zero.
1877 */
1878static int
7b867cf7 1879qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr,
854165f4 1880 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
1881{
1882 /* Individual Sector Erase Command Sequence */
1883 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1884 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1885 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1886 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1887 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1888 if (man_id == 0x1f && flash_id == 0x13)
1889 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
1890 else
1891 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
1892
1893 udelay(150);
1894
1895 /* Wait for erase to complete. */
1896 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
1897}
1898
1899/**
1900 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
1901 * @man_id: Flash manufacturer ID
1902 * @flash_id: Flash ID
1903 */
1904static void
7b867cf7 1905qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
854165f4 1906 uint8_t *flash_id)
1907{
1908 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1909 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1910 qla2x00_write_flash_byte(ha, 0x5555, 0x90);
1911 *man_id = qla2x00_read_flash_byte(ha, 0x0000);
1912 *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
1913 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1914 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1915 qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
1916}
1917
30c47662 1918static void
7b867cf7
AC		 1919qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf,
1920 uint32_t saddr, uint32_t length)
30c47662
AV		 1921{
1922 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1923 uint32_t midpoint, ilength;
1924 uint8_t data;
1925
1926 midpoint = length / 2;
1927
1928 WRT_REG_WORD(&reg->nvram, 0);
1929 RD_REG_WORD(&reg->nvram);
1930 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
1931 if (ilength == midpoint) {
1932 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1933 RD_REG_WORD(&reg->nvram);
1934 }
1935 data = qla2x00_read_flash_byte(ha, saddr);
1936 if (saddr % 100)
1937 udelay(10);
1938 *tmp_buf = data;
40a2e34a 1939 cond_resched();
30c47662
AV		 1940 }
1941}
854165f4 1942
1943static inline void
7b867cf7 1944qla2x00_suspend_hba(struct scsi_qla_host *vha)
854165f4 1945{
1946 int cnt;
1947 unsigned long flags;
7b867cf7 1948 struct qla_hw_data *ha = vha->hw;
854165f4 1949 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1950
1951 /* Suspend HBA. */
7b867cf7 1952 scsi_block_requests(vha->host);
fd34f556 1953 ha->isp_ops->disable_intrs(ha);
854165f4 1954 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1955
1956 /* Pause RISC. */
1957 spin_lock_irqsave(&ha->hardware_lock, flags);
1958 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1959 RD_REG_WORD(&reg->hccr);
1960 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1961 for (cnt = 0; cnt < 30000; cnt++) {
1962 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
1963 break;
1964 udelay(100);
1965 }
1966 } else {
1967 udelay(10);
1968 }
1969 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1970}
1971
1972static inline void
7b867cf7 1973qla2x00_resume_hba(struct scsi_qla_host *vha)
854165f4 1974{
7b867cf7
AC		 1975 struct qla_hw_data *ha = vha->hw;
1976
854165f4 1977 /* Resume HBA. */
1978 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
7b867cf7
AC		 1979 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1980 qla2xxx_wake_dpc(vha);
2533cf67 1981 qla2x00_wait_for_chip_reset(vha);
7b867cf7 1982 scsi_unblock_requests(vha->host);
854165f4 1983}
1984
1985uint8_t *
7b867cf7 1986qla2x00_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
854165f4 1987 uint32_t offset, uint32_t length)
1988{
854165f4 1989 uint32_t addr, midpoint;
1990 uint8_t *data;
7b867cf7 1991 struct qla_hw_data *ha = vha->hw;
854165f4 1992 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1993
1994 /* Suspend HBA. */
7b867cf7 1995 qla2x00_suspend_hba(vha);
854165f4 1996
1997 /* Go with read. */
854165f4 1998 midpoint = ha->optrom_size / 2;
1999
2000 qla2x00_flash_enable(ha);
2001 WRT_REG_WORD(&reg->nvram, 0);
2002 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
2003 for (addr = offset, data = buf; addr < length; addr++, data++) {
2004 if (addr == midpoint) {
2005 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2006 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
2007 }
2008
2009 *data = qla2x00_read_flash_byte(ha, addr);
2010 }
2011 qla2x00_flash_disable(ha);
854165f4 2012
2013 /* Resume HBA. */
7b867cf7 2014 qla2x00_resume_hba(vha);
854165f4 2015
2016 return buf;
2017}
2018
2019int
7b867cf7 2020qla2x00_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
854165f4 2021 uint32_t offset, uint32_t length)
2022{
2023
2024 int rval;
854165f4 2025 uint8_t man_id, flash_id, sec_number, data;
2026 uint16_t wd;
2027 uint32_t addr, liter, sec_mask, rest_addr;
7b867cf7 2028 struct qla_hw_data *ha = vha->hw;
854165f4 2029 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2030
2031 /* Suspend HBA. */
7b867cf7 2032 qla2x00_suspend_hba(vha);
854165f4 2033
2034 rval = QLA_SUCCESS;
2035 sec_number = 0;
2036
2037 /* Reset ISP chip. */
854165f4 2038 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2039 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
2040
2041 /* Go with write. */
2042 qla2x00_flash_enable(ha);
2043 do { /* Loop once to provide quick error exit */
2044 /* Structure of flash memory based on manufacturer */
2045 if (IS_OEM_001(ha)) {
2046 /* OEM variant with special flash part. */
2047 man_id = flash_id = 0;
2048 rest_addr = 0xffff;
2049 sec_mask = 0x10000;
2050 goto update_flash;
2051 }
2052 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
2053 switch (man_id) {
2054 case 0x20: /* ST flash. */
2055 if (flash_id == 0xd2 || flash_id == 0xe3) {
2056 /*
2057 * ST m29w008at part - 64kb sector size with
2058 * 32kb,8kb,8kb,16kb sectors at memory address
2059 * 0xf0000.
2060 */
2061 rest_addr = 0xffff;
2062 sec_mask = 0x10000;
2063 break;
2064 }
2065 /*
2066 * ST m29w010b part - 16kb sector size
2067 * Default to 16kb sectors
2068 */
2069 rest_addr = 0x3fff;
2070 sec_mask = 0x1c000;
2071 break;
2072 case 0x40: /* Mostel flash. */
2073 /* Mostel v29c51001 part - 512 byte sector size. */
2074 rest_addr = 0x1ff;
2075 sec_mask = 0x1fe00;
2076 break;
2077 case 0xbf: /* SST flash. */
2078 /* SST39sf10 part - 4kb sector size. */
2079 rest_addr = 0xfff;
2080 sec_mask = 0x1f000;
2081 break;
2082 case 0xda: /* Winbond flash. */
2083 /* Winbond W29EE011 part - 256 byte sector size. */
2084 rest_addr = 0x7f;
2085 sec_mask = 0x1ff80;
2086 break;
2087 case 0xc2: /* Macronix flash. */
2088 /* 64k sector size. */
2089 if (flash_id == 0x38 || flash_id == 0x4f) {
2090 rest_addr = 0xffff;
2091 sec_mask = 0x10000;
2092 break;
2093 }
2094 /* Fall through... */
2095
2096 case 0x1f: /* Atmel flash. */
2097 /* 512k sector size. */
2098 if (flash_id == 0x13) {
2099 rest_addr = 0x7fffffff;
2100 sec_mask = 0x80000000;
2101 break;
2102 }
2103 /* Fall through... */
2104
2105 case 0x01: /* AMD flash. */
2106 if (flash_id == 0x38 || flash_id == 0x40 ||
2107 flash_id == 0x4f) {
2108 /* Am29LV081 part - 64kb sector size. */
2109 /* Am29LV002BT part - 64kb sector size. */
2110 rest_addr = 0xffff;
2111 sec_mask = 0x10000;
2112 break;
2113 } else if (flash_id == 0x3e) {
2114 /*
2115 * Am29LV008b part - 64kb sector size with
2116 * 32kb,8kb,8kb,16kb sector at memory address
2117 * h0xf0000.
2118 */
2119 rest_addr = 0xffff;
2120 sec_mask = 0x10000;
2121 break;
2122 } else if (flash_id == 0x20 || flash_id == 0x6e) {
2123 /*
2124 * Am29LV010 part or AM29f010 - 16kb sector
2125 * size.
2126 */
2127 rest_addr = 0x3fff;
2128 sec_mask = 0x1c000;
2129 break;
2130 } else if (flash_id == 0x6d) {
2131 /* Am29LV001 part - 8kb sector size. */
2132 rest_addr = 0x1fff;
2133 sec_mask = 0x1e000;
2134 break;
2135 }
2136 default:
2137 /* Default to 16 kb sector size. */
2138 rest_addr = 0x3fff;
2139 sec_mask = 0x1c000;
2140 break;
2141 }
2142
2143update_flash:
2144 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2145 if (qla2x00_erase_flash(ha, man_id, flash_id)) {
2146 rval = QLA_FUNCTION_FAILED;
2147 break;
2148 }
2149 }
2150
2151 for (addr = offset, liter = 0; liter < length; liter++,
2152 addr++) {
2153 data = buf[liter];
2154 /* Are we at the beginning of a sector? */
2155 if ((addr & rest_addr) == 0) {
2156 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2157 if (addr >= 0x10000UL) {
2158 if (((addr >> 12) & 0xf0) &&
2159 ((man_id == 0x01 &&
2160 flash_id == 0x3e) ||
2161 (man_id == 0x20 &&
2162 flash_id == 0xd2))) {
2163 sec_number++;
2164 if (sec_number == 1) {
2165 rest_addr =
2166 0x7fff;
2167 sec_mask =
2168 0x18000;
2169 } else if (
2170 sec_number == 2 ||
2171 sec_number == 3) {
2172 rest_addr =
2173 0x1fff;
2174 sec_mask =
2175 0x1e000;
2176 } else if (
2177 sec_number == 4) {
2178 rest_addr =
2179 0x3fff;
2180 sec_mask =
2181 0x1c000;
2182 }
2183 }
2184 }
2185 } else if (addr == ha->optrom_size / 2) {
2186 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2187 RD_REG_WORD(&reg->nvram);
2188 }
2189
2190 if (flash_id == 0xda && man_id == 0xc1) {
2191 qla2x00_write_flash_byte(ha, 0x5555,
2192 0xaa);
2193 qla2x00_write_flash_byte(ha, 0x2aaa,
2194 0x55);
2195 qla2x00_write_flash_byte(ha, 0x5555,
2196 0xa0);
2197 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
2198 /* Then erase it */
2199 if (qla2x00_erase_flash_sector(ha,
2200 addr, sec_mask, man_id,
2201 flash_id)) {
2202 rval = QLA_FUNCTION_FAILED;
2203 break;
2204 }
2205 if (man_id == 0x01 && flash_id == 0x6d)
2206 sec_number++;
2207 }
2208 }
2209
2210 if (man_id == 0x01 && flash_id == 0x6d) {
2211 if (sec_number == 1 &&
2212 addr == (rest_addr - 1)) {
2213 rest_addr = 0x0fff;
2214 sec_mask = 0x1f000;
2215 } else if (sec_number == 3 && (addr & 0x7ffe)) {
2216 rest_addr = 0x3fff;
2217 sec_mask = 0x1c000;
2218 }
2219 }
2220
2221 if (qla2x00_program_flash_address(ha, addr, data,
2222 man_id, flash_id)) {
2223 rval = QLA_FUNCTION_FAILED;
2224 break;
2225 }
40a2e34a 2226 cond_resched();
854165f4 2227 }
2228 } while (0);
2229 qla2x00_flash_disable(ha);
854165f4 2230
2231 /* Resume HBA. */
7b867cf7 2232 qla2x00_resume_hba(vha);
854165f4 2233
2234 return rval;
2235}
2236
2237uint8_t *
7b867cf7 2238qla24xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
854165f4 2239 uint32_t offset, uint32_t length)
2240{
7b867cf7
AC		 2241 struct qla_hw_data *ha = vha->hw;
2242
854165f4 2243 /* Suspend HBA. */
7b867cf7 2244 scsi_block_requests(vha->host);
854165f4 2245 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2246
2247 /* Go with read. */
7b867cf7 2248 qla24xx_read_flash_data(vha, (uint32_t *)buf, offset >> 2, length >> 2);
854165f4 2249
2250 /* Resume HBA. */
2251 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
7b867cf7 2252 scsi_unblock_requests(vha->host);
854165f4 2253
2254 return buf;
2255}
2256
2257int
7b867cf7 2258qla24xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
854165f4 2259 uint32_t offset, uint32_t length)
2260{
2261 int rval;
7b867cf7 2262 struct qla_hw_data *ha = vha->hw;
854165f4 2263
2264 /* Suspend HBA. */
7b867cf7 2265 scsi_block_requests(vha->host);
854165f4 2266 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2267
2268 /* Go with write. */
7b867cf7 2269 rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, offset >> 2,
854165f4 2270 length >> 2);
2271
854165f4 2272 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
7b867cf7 2273 scsi_unblock_requests(vha->host);
854165f4 2274
2275 return rval;
2276}
30c47662 2277
338c9161 2278uint8_t *
7b867cf7 2279qla25xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
338c9161
AV		 2280 uint32_t offset, uint32_t length)
2281{
2282 int rval;
2283 dma_addr_t optrom_dma;
2284 void *optrom;
2285 uint8_t *pbuf;
2286 uint32_t faddr, left, burst;
7b867cf7 2287 struct qla_hw_data *ha = vha->hw;
338c9161 2288
b7cc176c 2289 if (offset & 0xfff)
338c9161
AV		 2290 goto slow_read;
2291 if (length < OPTROM_BURST_SIZE)
2292 goto slow_read;
2293
2294 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2295 &optrom_dma, GFP_KERNEL);
2296 if (!optrom) {
2297 qla_printk(KERN_DEBUG, ha,
2298 "Unable to allocate memory for optrom burst read "
2299 "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
2300
2301 goto slow_read;
2302 }
2303
2304 pbuf = buf;
2305 faddr = offset >> 2;
2306 left = length >> 2;
2307 burst = OPTROM_BURST_DWORDS;
2308 while (left != 0) {
2309 if (burst > left)
2310 burst = left;
2311
7b867cf7 2312 rval = qla2x00_dump_ram(vha, optrom_dma,
3a03eb79 2313 flash_data_addr(ha, faddr), burst);
338c9161
AV		 2314 if (rval) {
2315 qla_printk(KERN_WARNING, ha,
2316 "Unable to burst-read optrom segment "
2317 "(%x/%x/%llx).\n", rval,
3a03eb79 2318 flash_data_addr(ha, faddr),
875baf3c 2319 (unsigned long long)optrom_dma);
338c9161
AV		 2320 qla_printk(KERN_WARNING, ha,
2321 "Reverting to slow-read.\n");
2322
2323 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2324 optrom, optrom_dma);
2325 goto slow_read;
2326 }
2327
2328 memcpy(pbuf, optrom, burst * 4);
2329
2330 left -= burst;
2331 faddr += burst;
2332 pbuf += burst * 4;
2333 }
2334
2335 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
2336 optrom_dma);
2337
2338 return buf;
2339
2340slow_read:
7b867cf7 2341 return qla24xx_read_optrom_data(vha, buf, offset, length);
338c9161
AV		 2342}
2343
30c47662
AV		 2344/**
2345 * qla2x00_get_fcode_version() - Determine an FCODE image's version.
2346 * @ha: HA context
2347 * @pcids: Pointer to the FCODE PCI data structure
2348 *
2349 * The process of retrieving the FCODE version information is at best
2350 * described as interesting.
2351 *
2352 * Within the first 100h bytes of the image an ASCII string is present
2353 * which contains several pieces of information including the FCODE
2354 * version. Unfortunately it seems the only reliable way to retrieve
2355 * the version is by scanning for another sentinel within the string,
2356 * the FCODE build date:
2357 *
2358 * ... 2.00.02 10/17/02 ...
2359 *
2360 * Returns QLA_SUCCESS on successful retrieval of version.
2361 */
2362static void
7b867cf7 2363qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids)
30c47662
AV		 2364{
2365 int ret = QLA_FUNCTION_FAILED;
2366 uint32_t istart, iend, iter, vend;
2367 uint8_t do_next, rbyte, *vbyte;
2368
2369 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2370
2371 /* Skip the PCI data structure. */
2372 istart = pcids +
2373 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
2374 qla2x00_read_flash_byte(ha, pcids + 0x0A));
2375 iend = istart + 0x100;
2376 do {
2377 /* Scan for the sentinel date string...eeewww. */
2378 do_next = 0;
2379 iter = istart;
2380 while ((iter < iend) && !do_next) {
2381 iter++;
2382 if (qla2x00_read_flash_byte(ha, iter) == '/') {
2383 if (qla2x00_read_flash_byte(ha, iter + 2) ==
2384 '/')
2385 do_next++;
2386 else if (qla2x00_read_flash_byte(ha,
2387 iter + 3) == '/')
2388 do_next++;
2389 }
2390 }
2391 if (!do_next)
2392 break;
2393
2394 /* Backtrack to previous ' ' (space). */
2395 do_next = 0;
2396 while ((iter > istart) && !do_next) {
2397 iter--;
2398 if (qla2x00_read_flash_byte(ha, iter) == ' ')
2399 do_next++;
2400 }
2401 if (!do_next)
2402 break;
2403
2404 /*
2405 * Mark end of version tag, and find previous ' ' (space) or
2406 * string length (recent FCODE images -- major hack ahead!!!).
2407 */
2408 vend = iter - 1;
2409 do_next = 0;
2410 while ((iter > istart) && !do_next) {
2411 iter--;
2412 rbyte = qla2x00_read_flash_byte(ha, iter);
2413 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
2414 do_next++;
2415 }
2416 if (!do_next)
2417 break;
2418
2419 /* Mark beginning of version tag, and copy data. */
2420 iter++;
2421 if ((vend - iter) &&
2422 ((vend - iter) < sizeof(ha->fcode_revision))) {
2423 vbyte = ha->fcode_revision;
2424 while (iter <= vend) {
2425 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
2426 iter++;
2427 }
2428 ret = QLA_SUCCESS;
2429 }
2430 } while (0);
2431
2432 if (ret != QLA_SUCCESS)
2433 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2434}
2435
2436int
7b867cf7 2437qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
30c47662
AV		 2438{
2439 int ret = QLA_SUCCESS;
2440 uint8_t code_type, last_image;
2441 uint32_t pcihdr, pcids;
2442 uint8_t *dbyte;
2443 uint16_t *dcode;
7b867cf7 2444 struct qla_hw_data *ha = vha->hw;
30c47662
AV		 2445
2446 if (!ha->pio_address || !mbuf)
2447 return QLA_FUNCTION_FAILED;
2448
2449 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2450 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2451 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2452 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2453
2454 qla2x00_flash_enable(ha);
2455
2456 /* Begin with first PCI expansion ROM header. */
2457 pcihdr = 0;
2458 last_image = 1;
2459 do {
2460 /* Verify PCI expansion ROM header. */
2461 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
2462 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2463 /* No signature */
7b867cf7
AC		 2464 DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM "
2465 "signature.\n"));
30c47662
AV		 2466 ret = QLA_FUNCTION_FAILED;
2467 break;
2468 }
2469
2470 /* Locate PCI data structure. */
2471 pcids = pcihdr +
2472 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2473 qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2474
2475 /* Validate signature of PCI data structure. */
2476 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2477 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2478 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2479 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2480 /* Incorrect header. */
7b867cf7
AC		 2481 DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not "
2482 "found pcir_adr=%x.\n", pcids));
30c47662
AV		 2483 ret = QLA_FUNCTION_FAILED;
2484 break;
2485 }
2486
2487 /* Read version */
2488 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2489 switch (code_type) {
2490 case ROM_CODE_TYPE_BIOS:
2491 /* Intel x86, PC-AT compatible. */
2492 ha->bios_revision[0] =
2493 qla2x00_read_flash_byte(ha, pcids + 0x12);
2494 ha->bios_revision[1] =
2495 qla2x00_read_flash_byte(ha, pcids + 0x13);
7b867cf7 2496 DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n",
30c47662
AV		 2497 ha->bios_revision[1], ha->bios_revision[0]));
2498 break;
2499 case ROM_CODE_TYPE_FCODE:
2500 /* Open Firmware standard for PCI (FCode). */
2501 /* Eeeewww... */
2502 qla2x00_get_fcode_version(ha, pcids);
2503 break;
2504 case ROM_CODE_TYPE_EFI:
2505 /* Extensible Firmware Interface (EFI). */
2506 ha->efi_revision[0] =
2507 qla2x00_read_flash_byte(ha, pcids + 0x12);
2508 ha->efi_revision[1] =
2509 qla2x00_read_flash_byte(ha, pcids + 0x13);
7b867cf7 2510 DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n",
30c47662
AV		 2511 ha->efi_revision[1], ha->efi_revision[0]));
2512 break;
2513 default:
7b867cf7
AC		 2514 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code "
2515 "type %x at pcids %x.\n", code_type, pcids));
30c47662
AV		 2516 break;
2517 }
2518
2519 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2520
2521 /* Locate next PCI expansion ROM. */
2522 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2523 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2524 } while (!last_image);
2525
2526 if (IS_QLA2322(ha)) {
2527 /* Read firmware image information. */
2528 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2529 dbyte = mbuf;
2530 memset(dbyte, 0, 8);
2531 dcode = (uint16_t *)dbyte;
2532
c00d8994 2533 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10,
30c47662 2534 8);
7b867cf7
AC		 2535 DEBUG3(qla_printk(KERN_DEBUG, ha, "dumping fw ver from "
2536 "flash:\n"));
30c47662
AV		 2537 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte, 8));
2538
2539 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2540 dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2541 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2542 dcode[3] == 0)) {
7b867cf7
AC		 2543 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw "
2544 "revision at %x.\n", ha->flt_region_fw * 4));
30c47662
AV		 2545 } else {
2546 /* values are in big endian */
2547 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2548 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2549 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
2550 }
2551 }
2552
2553 qla2x00_flash_disable(ha);
2554
2555 return ret;
2556}
2557
2558int
7b867cf7 2559qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
30c47662
AV		 2560{
2561 int ret = QLA_SUCCESS;
2562 uint32_t pcihdr, pcids;
2563 uint32_t *dcode;
2564 uint8_t *bcode;
2565 uint8_t code_type, last_image;
2566 int i;
7b867cf7 2567 struct qla_hw_data *ha = vha->hw;
30c47662
AV		 2568
2569 if (!mbuf)
2570 return QLA_FUNCTION_FAILED;
2571
2572 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2573 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2574 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2575 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2576
2577 dcode = mbuf;
2578
2579 /* Begin with first PCI expansion ROM header. */
6315a5f8 2580 pcihdr = ha->flt_region_boot << 2;
30c47662
AV		 2581 last_image = 1;
2582 do {
2583 /* Verify PCI expansion ROM header. */
7b867cf7 2584 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
30c47662
AV		 2585 bcode = mbuf + (pcihdr % 4);
2586 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2587 /* No signature */
7b867cf7
AC		 2588 DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM "
2589 "signature.\n"));
30c47662
AV		 2590 ret = QLA_FUNCTION_FAILED;
2591 break;
2592 }
2593
2594 /* Locate PCI data structure. */
2595 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2596
7b867cf7 2597 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
30c47662
AV		 2598 bcode = mbuf + (pcihdr % 4);
2599
2600 /* Validate signature of PCI data structure. */
2601 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2602 bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2603 /* Incorrect header. */
7b867cf7
AC		 2604 DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not "
2605 "found pcir_adr=%x.\n", pcids));
30c47662
AV		 2606 ret = QLA_FUNCTION_FAILED;
2607 break;
2608 }
2609
2610 /* Read version */
2611 code_type = bcode[0x14];
2612 switch (code_type) {
2613 case ROM_CODE_TYPE_BIOS:
2614 /* Intel x86, PC-AT compatible. */
2615 ha->bios_revision[0] = bcode[0x12];
2616 ha->bios_revision[1] = bcode[0x13];
7b867cf7 2617 DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n",
30c47662
AV		 2618 ha->bios_revision[1], ha->bios_revision[0]));
2619 break;
2620 case ROM_CODE_TYPE_FCODE:
2621 /* Open Firmware standard for PCI (FCode). */
2622 ha->fcode_revision[0] = bcode[0x12];
2623 ha->fcode_revision[1] = bcode[0x13];
7b867cf7 2624 DEBUG3(qla_printk(KERN_DEBUG, ha, "read FCODE %d.%d.\n",
30c47662
AV		 2625 ha->fcode_revision[1], ha->fcode_revision[0]));
2626 break;
2627 case ROM_CODE_TYPE_EFI:
2628 /* Extensible Firmware Interface (EFI). */
2629 ha->efi_revision[0] = bcode[0x12];
2630 ha->efi_revision[1] = bcode[0x13];
7b867cf7 2631 DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n",
30c47662
AV		 2632 ha->efi_revision[1], ha->efi_revision[0]));
2633 break;
2634 default:
7b867cf7
AC		 2635 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code "
2636 "type %x at pcids %x.\n", code_type, pcids));
30c47662
AV		 2637 break;
2638 }
2639
2640 last_image = bcode[0x15] & BIT_7;
2641
2642 /* Locate next PCI expansion ROM. */
2643 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2644 } while (!last_image);
2645
2646 /* Read firmware image information. */
2647 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2648 dcode = mbuf;
2649
7b867cf7 2650 qla24xx_read_flash_data(vha, dcode, ha->flt_region_fw + 4, 4);
30c47662
AV		 2651 for (i = 0; i < 4; i++)
2652 dcode[i] = be32_to_cpu(dcode[i]);
2653
2654 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
2655 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
2656 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2657 dcode[3] == 0)) {
7b867cf7
AC		 2658 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw "
2659 "revision at %x.\n", ha->flt_region_fw * 4));
30c47662
AV		 2660 } else {
2661 ha->fw_revision[0] = dcode[0];
2662 ha->fw_revision[1] = dcode[1];
2663 ha->fw_revision[2] = dcode[2];
2664 ha->fw_revision[3] = dcode[3];
2665 }
2666
2667 return ret;
2668}
cb8dacbf 2669
1ee27146
JC		 2670static int
2671qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end)
2672{
2673 if (pos >= end || *pos != 0x82)
2674 return 0;
2675
2676 pos += 3 + pos[1];
2677 if (pos >= end || *pos != 0x90)
2678 return 0;
2679
2680 pos += 3 + pos[1];
2681 if (pos >= end || *pos != 0x78)
2682 return 0;
2683
2684 return 1;
2685}
2686
2687int
7b867cf7 2688qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size)
1ee27146 2689{
7b867cf7 2690 struct qla_hw_data *ha = vha->hw;
1ee27146
JC		 2691 uint8_t *pos = ha->vpd;
2692 uint8_t *end = pos + ha->vpd_size;
2693 int len = 0;
2694
2695 if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end))
2696 return 0;
2697
2698 while (pos < end && *pos != 0x78) {
2699 len = (*pos == 0x82) ? pos[1] : pos[2];
2700
2701 if (!strncmp(pos, key, strlen(key)))
2702 break;
2703
2704 if (*pos != 0x90 && *pos != 0x91)
2705 pos += len;
2706
2707 pos += 3;
2708 }
2709
2710 if (pos < end - len && *pos != 0x78)
2711 return snprintf(str, size, "%.*s", len, pos + 3);
2712
2713 return 0;
2714}
Linux kernel - Deliverables
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