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[SCSI] qla2xxx: Use proper request/response queues with MQ instantiations.
[deliverable/linux.git] / drivers / scsi / qla2xxx / qla_sup.c
CommitLineData
fa90c54f
AV		 1/*
2 * QLogic Fibre Channel HBA Driver
01e58d8e 3 * Copyright (c) 2003-2008 QLogic Corporation
1da177e4 4 *
fa90c54f
AV		 5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
1da177e4
LT		 7#include "qla_def.h"
8
9#include <linux/delay.h>
2c96d8d0 10#include <linux/vmalloc.h>
1da177e4
LT		 11#include <asm/uaccess.h>
12
1da177e4
LT		 13/*
14 * NVRAM support routines
15 */
16
17/**
fa2a1ce5 18 * qla2x00_lock_nvram_access() -
1da177e4
LT		 19 * @ha: HA context
20 */
a824ebb3 21static void
7b867cf7 22qla2x00_lock_nvram_access(struct qla_hw_data *ha)
1da177e4
LT		 23{
24 uint16_t data;
3d71644c 25 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 26
27 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
28 data = RD_REG_WORD(&reg->nvram);
29 while (data & NVR_BUSY) {
30 udelay(100);
31 data = RD_REG_WORD(&reg->nvram);
32 }
33
34 /* Lock resource */
35 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
36 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
37 udelay(5);
38 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
39 while ((data & BIT_0) == 0) {
40 /* Lock failed */
41 udelay(100);
42 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
43 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
44 udelay(5);
45 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
46 }
47 }
48}
49
50/**
fa2a1ce5 51 * qla2x00_unlock_nvram_access() -
1da177e4
LT		 52 * @ha: HA context
53 */
a824ebb3 54static void
7b867cf7 55qla2x00_unlock_nvram_access(struct qla_hw_data *ha)
1da177e4 56{
3d71644c 57 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 58
59 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
60 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
61 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
62 }
63}
64
7b867cf7
AC		 65/**
66 * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
67 * @ha: HA context
68 * @data: Serial interface selector
69 */
70static void
71qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data)
72{
73 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
74
75 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
76 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
77 NVRAM_DELAY();
78 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_CLOCK |
79 NVR_WRT_ENABLE);
80 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
81 NVRAM_DELAY();
82 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
83 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
84 NVRAM_DELAY();
85}
86
87/**
88 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
89 * NVRAM.
90 * @ha: HA context
91 * @nv_cmd: NVRAM command
92 *
93 * Bit definitions for NVRAM command:
94 *
95 * Bit 26 = start bit
96 * Bit 25, 24 = opcode
97 * Bit 23-16 = address
98 * Bit 15-0 = write data
99 *
100 * Returns the word read from nvram @addr.
101 */
102static uint16_t
103qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd)
104{
105 uint8_t cnt;
106 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
107 uint16_t data = 0;
108 uint16_t reg_data;
109
110 /* Send command to NVRAM. */
111 nv_cmd <<= 5;
112 for (cnt = 0; cnt < 11; cnt++) {
113 if (nv_cmd & BIT_31)
114 qla2x00_nv_write(ha, NVR_DATA_OUT);
115 else
116 qla2x00_nv_write(ha, 0);
117 nv_cmd <<= 1;
118 }
119
120 /* Read data from NVRAM. */
121 for (cnt = 0; cnt < 16; cnt++) {
122 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
123 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
124 NVRAM_DELAY();
125 data <<= 1;
126 reg_data = RD_REG_WORD(&reg->nvram);
127 if (reg_data & NVR_DATA_IN)
128 data |= BIT_0;
129 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
130 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
131 NVRAM_DELAY();
132 }
133
134 /* Deselect chip. */
135 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
136 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
137 NVRAM_DELAY();
138
139 return data;
140}
141
142
1da177e4
LT		 143/**
144 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
145 * request routine to get the word from NVRAM.
146 * @ha: HA context
147 * @addr: Address in NVRAM to read
148 *
149 * Returns the word read from nvram @addr.
150 */
a824ebb3 151static uint16_t
7b867cf7 152qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr)
1da177e4
LT		 153{
154 uint16_t data;
155 uint32_t nv_cmd;
156
157 nv_cmd = addr << 16;
158 nv_cmd |= NV_READ_OP;
159 data = qla2x00_nvram_request(ha, nv_cmd);
160
161 return (data);
162}
163
7b867cf7
AC		 164/**
165 * qla2x00_nv_deselect() - Deselect NVRAM operations.
166 * @ha: HA context
167 */
168static void
169qla2x00_nv_deselect(struct qla_hw_data *ha)
170{
171 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
172
173 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
174 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
175 NVRAM_DELAY();
176}
177
1da177e4
LT		 178/**
179 * qla2x00_write_nvram_word() - Write NVRAM data.
180 * @ha: HA context
181 * @addr: Address in NVRAM to write
182 * @data: word to program
183 */
a824ebb3 184static void
7b867cf7 185qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data)
1da177e4
LT		 186{
187 int count;
188 uint16_t word;
45aeaf1e 189 uint32_t nv_cmd, wait_cnt;
3d71644c 190 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 191
192 qla2x00_nv_write(ha, NVR_DATA_OUT);
193 qla2x00_nv_write(ha, 0);
194 qla2x00_nv_write(ha, 0);
195
196 for (word = 0; word < 8; word++)
197 qla2x00_nv_write(ha, NVR_DATA_OUT);
198
199 qla2x00_nv_deselect(ha);
200
201 /* Write data */
202 nv_cmd = (addr << 16) | NV_WRITE_OP;
203 nv_cmd |= data;
204 nv_cmd <<= 5;
205 for (count = 0; count < 27; count++) {
206 if (nv_cmd & BIT_31)
207 qla2x00_nv_write(ha, NVR_DATA_OUT);
208 else
209 qla2x00_nv_write(ha, 0);
210
211 nv_cmd <<= 1;
212 }
213
214 qla2x00_nv_deselect(ha);
215
216 /* Wait for NVRAM to become ready */
217 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 218 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
45aeaf1e 219 wait_cnt = NVR_WAIT_CNT;
1da177e4 220 do {
45aeaf1e
RA		 221 if (!--wait_cnt) {
222 DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
7b867cf7 223 __func__, vha->host_no));
45aeaf1e
RA		 224 break;
225 }
1da177e4
LT		 226 NVRAM_DELAY();
227 word = RD_REG_WORD(&reg->nvram);
228 } while ((word & NVR_DATA_IN) == 0);
229
230 qla2x00_nv_deselect(ha);
231
232 /* Disable writes */
233 qla2x00_nv_write(ha, NVR_DATA_OUT);
234 for (count = 0; count < 10; count++)
235 qla2x00_nv_write(ha, 0);
236
237 qla2x00_nv_deselect(ha);
238}
239
459c5378 240static int
7b867cf7
AC		 241qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr,
242 uint16_t data, uint32_t tmo)
459c5378
AV		 243{
244 int ret, count;
245 uint16_t word;
246 uint32_t nv_cmd;
247 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
248
249 ret = QLA_SUCCESS;
250
251 qla2x00_nv_write(ha, NVR_DATA_OUT);
252 qla2x00_nv_write(ha, 0);
253 qla2x00_nv_write(ha, 0);
254
255 for (word = 0; word < 8; word++)
256 qla2x00_nv_write(ha, NVR_DATA_OUT);
257
258 qla2x00_nv_deselect(ha);
259
260 /* Write data */
261 nv_cmd = (addr << 16) | NV_WRITE_OP;
262 nv_cmd |= data;
263 nv_cmd <<= 5;
264 for (count = 0; count < 27; count++) {
265 if (nv_cmd & BIT_31)
266 qla2x00_nv_write(ha, NVR_DATA_OUT);
267 else
268 qla2x00_nv_write(ha, 0);
269
270 nv_cmd <<= 1;
271 }
272
273 qla2x00_nv_deselect(ha);
274
275 /* Wait for NVRAM to become ready */
276 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 277 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
459c5378
AV		 278 do {
279 NVRAM_DELAY();
280 word = RD_REG_WORD(&reg->nvram);
281 if (!--tmo) {
282 ret = QLA_FUNCTION_FAILED;
283 break;
284 }
285 } while ((word & NVR_DATA_IN) == 0);
286
287 qla2x00_nv_deselect(ha);
288
289 /* Disable writes */
290 qla2x00_nv_write(ha, NVR_DATA_OUT);
291 for (count = 0; count < 10; count++)
292 qla2x00_nv_write(ha, 0);
293
294 qla2x00_nv_deselect(ha);
295
296 return ret;
297}
298
459c5378
AV		 299/**
300 * qla2x00_clear_nvram_protection() -
301 * @ha: HA context
302 */
303static int
7b867cf7 304qla2x00_clear_nvram_protection(struct qla_hw_data *ha)
459c5378
AV		 305{
306 int ret, stat;
307 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
45aeaf1e 308 uint32_t word, wait_cnt;
459c5378
AV		 309 uint16_t wprot, wprot_old;
310
311 /* Clear NVRAM write protection. */
312 ret = QLA_FUNCTION_FAILED;
45aeaf1e
RA		 313
314 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
315 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
459c5378 316 __constant_cpu_to_le16(0x1234), 100000);
45aeaf1e
RA		 317 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
318 if (stat != QLA_SUCCESS || wprot != 0x1234) {
459c5378
AV		 319 /* Write enable. */
320 qla2x00_nv_write(ha, NVR_DATA_OUT);
321 qla2x00_nv_write(ha, 0);
322 qla2x00_nv_write(ha, 0);
323 for (word = 0; word < 8; word++)
324 qla2x00_nv_write(ha, NVR_DATA_OUT);
325
326 qla2x00_nv_deselect(ha);
327
328 /* Enable protection register. */
329 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
330 qla2x00_nv_write(ha, NVR_PR_ENABLE);
331 qla2x00_nv_write(ha, NVR_PR_ENABLE);
332 for (word = 0; word < 8; word++)
333 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
334
335 qla2x00_nv_deselect(ha);
336
337 /* Clear protection register (ffff is cleared). */
338 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
339 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
340 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
341 for (word = 0; word < 8; word++)
342 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
343
344 qla2x00_nv_deselect(ha);
345
346 /* Wait for NVRAM to become ready. */
347 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 348 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
45aeaf1e 349 wait_cnt = NVR_WAIT_CNT;
459c5378 350 do {
45aeaf1e 351 if (!--wait_cnt) {
7b867cf7
AC		 352 DEBUG9_10(qla_printk(
353 "NVRAM didn't go ready...\n"));
45aeaf1e
RA		 354 break;
355 }
459c5378
AV		 356 NVRAM_DELAY();
357 word = RD_REG_WORD(&reg->nvram);
358 } while ((word & NVR_DATA_IN) == 0);
359
45aeaf1e
RA		 360 if (wait_cnt)
361 ret = QLA_SUCCESS;
459c5378 362 } else
45aeaf1e 363 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
459c5378
AV		 364
365 return ret;
366}
367
368static void
7b867cf7 369qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat)
459c5378
AV		 370{
371 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
45aeaf1e 372 uint32_t word, wait_cnt;
459c5378
AV		 373
374 if (stat != QLA_SUCCESS)
375 return;
376
377 /* Set NVRAM write protection. */
378 /* Write enable. */
379 qla2x00_nv_write(ha, NVR_DATA_OUT);
380 qla2x00_nv_write(ha, 0);
381 qla2x00_nv_write(ha, 0);
382 for (word = 0; word < 8; word++)
383 qla2x00_nv_write(ha, NVR_DATA_OUT);
384
385 qla2x00_nv_deselect(ha);
386
387 /* Enable protection register. */
388 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
389 qla2x00_nv_write(ha, NVR_PR_ENABLE);
390 qla2x00_nv_write(ha, NVR_PR_ENABLE);
391 for (word = 0; word < 8; word++)
392 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
393
394 qla2x00_nv_deselect(ha);
395
396 /* Enable protection register. */
397 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
398 qla2x00_nv_write(ha, NVR_PR_ENABLE);
399 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
400 for (word = 0; word < 8; word++)
401 qla2x00_nv_write(ha, NVR_PR_ENABLE);
402
403 qla2x00_nv_deselect(ha);
404
405 /* Wait for NVRAM to become ready. */
406 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 407 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
45aeaf1e 408 wait_cnt = NVR_WAIT_CNT;
459c5378 409 do {
45aeaf1e 410 if (!--wait_cnt) {
7b867cf7 411 DEBUG9_10(qla_printk("NVRAM didn't go ready...\n"));
45aeaf1e
RA		 412 break;
413 }
459c5378
AV		 414 NVRAM_DELAY();
415 word = RD_REG_WORD(&reg->nvram);
416 } while ((word & NVR_DATA_IN) == 0);
417}
418
419
420/*****************************************************************************/
421/* Flash Manipulation Routines */
422/*****************************************************************************/
423
338c9161
AV		 424#define OPTROM_BURST_SIZE 0x1000
425#define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
426
459c5378
AV		 427static inline uint32_t
428flash_conf_to_access_addr(uint32_t faddr)
429{
430 return FARX_ACCESS_FLASH_CONF | faddr;
431}
432
433static inline uint32_t
434flash_data_to_access_addr(uint32_t faddr)
435{
436 return FARX_ACCESS_FLASH_DATA | faddr;
437}
438
439static inline uint32_t
440nvram_conf_to_access_addr(uint32_t naddr)
441{
442 return FARX_ACCESS_NVRAM_CONF | naddr;
443}
444
445static inline uint32_t
446nvram_data_to_access_addr(uint32_t naddr)
447{
448 return FARX_ACCESS_NVRAM_DATA | naddr;
449}
450
e5f82ab8 451static uint32_t
7b867cf7 452qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr)
459c5378
AV		 453{
454 int rval;
455 uint32_t cnt, data;
456 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
457
458 WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
459 /* Wait for READ cycle to complete. */
460 rval = QLA_SUCCESS;
461 for (cnt = 3000;
462 (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
463 rval == QLA_SUCCESS; cnt--) {
464 if (cnt)
465 udelay(10);
466 else
467 rval = QLA_FUNCTION_TIMEOUT;
40a2e34a 468 cond_resched();
459c5378
AV		 469 }
470
471 /* TODO: What happens if we time out? */
472 data = 0xDEADDEAD;
473 if (rval == QLA_SUCCESS)
474 data = RD_REG_DWORD(&reg->flash_data);
475
476 return data;
477}
478
479uint32_t *
7b867cf7 480qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
459c5378
AV		 481 uint32_t dwords)
482{
483 uint32_t i;
459c5378
AV		 484 /* Dword reads to flash. */
485 for (i = 0; i < dwords; i++, faddr++)
7b867cf7 486 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(vha->hw,
459c5378
AV		 487 flash_data_to_access_addr(faddr)));
488
459c5378
AV		 489 return dwptr;
490}
491
e5f82ab8 492static int
7b867cf7 493qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data)
459c5378
AV		 494{
495 int rval;
496 uint32_t cnt;
497 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
498
499 WRT_REG_DWORD(&reg->flash_data, data);
500 RD_REG_DWORD(&reg->flash_data); /* PCI Posting. */
501 WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
502 /* Wait for Write cycle to complete. */
503 rval = QLA_SUCCESS;
504 for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
505 rval == QLA_SUCCESS; cnt--) {
506 if (cnt)
507 udelay(10);
508 else
509 rval = QLA_FUNCTION_TIMEOUT;
40a2e34a 510 cond_resched();
459c5378
AV		 511 }
512 return rval;
513}
514
e5f82ab8 515static void
7b867cf7 516qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
459c5378
AV		 517 uint8_t *flash_id)
518{
519 uint32_t ids;
520
521 ids = qla24xx_read_flash_dword(ha, flash_data_to_access_addr(0xd03ab));
522 *man_id = LSB(ids);
523 *flash_id = MSB(ids);
45aeaf1e
RA		 524
525 /* Check if man_id and flash_id are valid. */
526 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
527 /* Read information using 0x9f opcode
528 * Device ID, Mfg ID would be read in the format:
529 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
530 * Example: ATMEL 0x00 01 45 1F
531 * Extract MFG and Dev ID from last two bytes.
532 */
533 ids = qla24xx_read_flash_dword(ha,
534 flash_data_to_access_addr(0xd009f));
535 *man_id = LSB(ids);
536 *flash_id = MSB(ids);
537 }
459c5378
AV		 538}
539
c00d8994 540static int
7b867cf7 541qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
c00d8994
AV		 542{
543 const char *loc, *locations[] = { "DEF", "PCI" };
544 uint32_t pcihdr, pcids;
545 uint32_t *dcode;
546 uint8_t *buf, *bcode, last_image;
547 uint16_t cnt, chksum, *wptr;
548 struct qla_flt_location *fltl;
7b867cf7 549 struct qla_hw_data *ha = vha->hw;
73208dfd 550 struct req_que *req = ha->req_q_map[0];
c00d8994
AV		 551
552 /*
553 * FLT-location structure resides after the last PCI region.
554 */
555
556 /* Begin with sane defaults. */
557 loc = locations[0];
558 *start = IS_QLA24XX_TYPE(ha) ? FA_FLASH_LAYOUT_ADDR_24:
559 FA_FLASH_LAYOUT_ADDR;
560
561 /* Begin with first PCI expansion ROM header. */
7b867cf7
AC		 562 buf = (uint8_t *)req->ring;
563 dcode = (uint32_t *)req->ring;
c00d8994
AV		 564 pcihdr = 0;
565 last_image = 1;
566 do {
567 /* Verify PCI expansion ROM header. */
7b867cf7 568 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
c00d8994
AV		 569 bcode = buf + (pcihdr % 4);
570 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa)
571 goto end;
572
573 /* Locate PCI data structure. */
574 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
7b867cf7 575 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
c00d8994
AV		 576 bcode = buf + (pcihdr % 4);
577
578 /* Validate signature of PCI data structure. */
579 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
580 bcode[0x2] != 'I' || bcode[0x3] != 'R')
581 goto end;
582
583 last_image = bcode[0x15] & BIT_7;
584
585 /* Locate next PCI expansion ROM. */
586 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
587 } while (!last_image);
588
589 /* Now verify FLT-location structure. */
7b867cf7
AC		 590 fltl = (struct qla_flt_location *)req->ring;
591 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2,
c00d8994
AV		 592 sizeof(struct qla_flt_location) >> 2);
593 if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' ||
594 fltl->sig[2] != 'L' || fltl->sig[3] != 'T')
595 goto end;
596
7b867cf7 597 wptr = (uint16_t *)req->ring;
c00d8994
AV		 598 cnt = sizeof(struct qla_flt_location) >> 1;
599 for (chksum = 0; cnt; cnt--)
600 chksum += le16_to_cpu(*wptr++);
601 if (chksum) {
602 qla_printk(KERN_ERR, ha,
603 "Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
604 qla2x00_dump_buffer(buf, sizeof(struct qla_flt_location));
605 return QLA_FUNCTION_FAILED;
606 }
607
608 /* Good data. Use specified location. */
609 loc = locations[1];
610 *start = le16_to_cpu(fltl->start_hi) << 16 |
611 le16_to_cpu(fltl->start_lo);
612end:
613 DEBUG2(qla_printk(KERN_DEBUG, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
614 return QLA_SUCCESS;
615}
616
617static void
7b867cf7 618qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
c00d8994
AV		 619{
620 const char *loc, *locations[] = { "DEF", "FLT" };
621 uint16_t *wptr;
622 uint16_t cnt, chksum;
623 uint32_t start;
624 struct qla_flt_header *flt;
625 struct qla_flt_region *region;
7b867cf7 626 struct qla_hw_data *ha = vha->hw;
73208dfd 627 struct req_que *req = ha->req_q_map[0];
c00d8994
AV		 628
629 ha->flt_region_flt = flt_addr;
7b867cf7
AC		 630 wptr = (uint16_t *)req->ring;
631 flt = (struct qla_flt_header *)req->ring;
c00d8994 632 region = (struct qla_flt_region *)&flt[1];
7b867cf7 633 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
c00d8994
AV		 634 flt_addr << 2, OPTROM_BURST_SIZE);
635 if (*wptr == __constant_cpu_to_le16(0xffff))
636 goto no_flash_data;
637 if (flt->version != __constant_cpu_to_le16(1)) {
638 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported FLT detected: "
639 "version=0x%x length=0x%x checksum=0x%x.\n",
640 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
641 le16_to_cpu(flt->checksum)));
642 goto no_flash_data;
643 }
644
645 cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
646 for (chksum = 0; cnt; cnt--)
647 chksum += le16_to_cpu(*wptr++);
648 if (chksum) {
649 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
650 "version=0x%x length=0x%x checksum=0x%x.\n",
651 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
652 chksum));
653 goto no_flash_data;
654 }
655
656 loc = locations[1];
657 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
658 for ( ; cnt; cnt--, region++) {
659 /* Store addresses as DWORD offsets. */
660 start = le32_to_cpu(region->start) >> 2;
661
662 DEBUG3(qla_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
663 "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
664 le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
665
666 switch (le32_to_cpu(region->code)) {
667 case FLT_REG_FW:
668 ha->flt_region_fw = start;
669 break;
670 case FLT_REG_BOOT_CODE:
671 ha->flt_region_boot = start;
672 break;
673 case FLT_REG_VPD_0:
674 ha->flt_region_vpd_nvram = start;
675 break;
676 case FLT_REG_FDT:
677 ha->flt_region_fdt = start;
678 break;
272976ca
AV		 679 case FLT_REG_NPIV_CONF_0:
680 if (!PCI_FUNC(ha->pdev->devfn))
681 ha->flt_region_npiv_conf = start;
682 break;
683 case FLT_REG_NPIV_CONF_1:
684 if (PCI_FUNC(ha->pdev->devfn))
685 ha->flt_region_npiv_conf = start;
686 break;
c00d8994
AV		 687 }
688 }
689 goto done;
690
691no_flash_data:
692 /* Use hardcoded defaults. */
693 loc = locations[0];
694 ha->flt_region_fw = FA_RISC_CODE_ADDR;
695 ha->flt_region_boot = FA_BOOT_CODE_ADDR;
696 ha->flt_region_vpd_nvram = FA_VPD_NVRAM_ADDR;
697 ha->flt_region_fdt = IS_QLA24XX_TYPE(ha) ? FA_FLASH_DESCR_ADDR_24:
698 FA_FLASH_DESCR_ADDR;
272976ca
AV		 699 ha->flt_region_npiv_conf = !PCI_FUNC(ha->pdev->devfn) ?
700 (IS_QLA24XX_TYPE(ha) ? FA_NPIV_CONF0_ADDR_24: FA_NPIV_CONF0_ADDR):
701 (IS_QLA24XX_TYPE(ha) ? FA_NPIV_CONF1_ADDR_24: FA_NPIV_CONF1_ADDR);
c00d8994
AV		 702done:
703 DEBUG2(qla_printk(KERN_DEBUG, ha, "FLT[%s]: boot=0x%x fw=0x%x "
1ded85e2 704 "vpd_nvram=0x%x fdt=0x%x flt=0x%x npiv=0x%x.\n", loc,
c00d8994 705 ha->flt_region_boot, ha->flt_region_fw, ha->flt_region_vpd_nvram,
1ded85e2 706 ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf));
c00d8994
AV		 707}
708
709static void
7b867cf7 710qla2xxx_get_fdt_info(scsi_qla_host_t *vha)
7d232c74 711{
821b3996 712#define FLASH_BLK_SIZE_4K 0x1000
7d232c74
AV		 713#define FLASH_BLK_SIZE_32K 0x8000
714#define FLASH_BLK_SIZE_64K 0x10000
c00d8994 715 const char *loc, *locations[] = { "MID", "FDT" };
7d232c74
AV		 716 uint16_t cnt, chksum;
717 uint16_t *wptr;
718 struct qla_fdt_layout *fdt;
719 uint8_t man_id, flash_id;
c00d8994 720 uint16_t mid, fid;
7b867cf7 721 struct qla_hw_data *ha = vha->hw;
73208dfd 722 struct req_que *req = ha->req_q_map[0];
7d232c74 723
7b867cf7
AC		 724 wptr = (uint16_t *)req->ring;
725 fdt = (struct qla_fdt_layout *)req->ring;
726 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
c00d8994 727 ha->flt_region_fdt << 2, OPTROM_BURST_SIZE);
7d232c74
AV		 728 if (*wptr == __constant_cpu_to_le16(0xffff))
729 goto no_flash_data;
730 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
731 fdt->sig[3] != 'D')
732 goto no_flash_data;
733
734 for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
735 cnt++)
736 chksum += le16_to_cpu(*wptr++);
737 if (chksum) {
738 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
739 "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
740 le16_to_cpu(fdt->version)));
741 DEBUG9(qla2x00_dump_buffer((uint8_t *)fdt, sizeof(*fdt)));
742 goto no_flash_data;
743 }
744
c00d8994
AV		 745 loc = locations[1];
746 mid = le16_to_cpu(fdt->man_id);
747 fid = le16_to_cpu(fdt->id);
7d232c74
AV		 748 ha->fdt_wrt_disable = fdt->wrt_disable_bits;
749 ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0300 | fdt->erase_cmd);
750 ha->fdt_block_size = le32_to_cpu(fdt->block_size);
751 if (fdt->unprotect_sec_cmd) {
752 ha->fdt_unprotect_sec_cmd = flash_conf_to_access_addr(0x0300 |
753 fdt->unprotect_sec_cmd);
754 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
755 flash_conf_to_access_addr(0x0300 | fdt->protect_sec_cmd):
756 flash_conf_to_access_addr(0x0336);
757 }
c00d8994 758 goto done;
7d232c74 759no_flash_data:
c00d8994 760 loc = locations[0];
7d232c74 761 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
c00d8994
AV		 762 mid = man_id;
763 fid = flash_id;
7d232c74
AV		 764 ha->fdt_wrt_disable = 0x9c;
765 ha->fdt_erase_cmd = flash_conf_to_access_addr(0x03d8);
766 switch (man_id) {
767 case 0xbf: /* STT flash. */
768 if (flash_id == 0x8e)
769 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
770 else
771 ha->fdt_block_size = FLASH_BLK_SIZE_32K;
772
773 if (flash_id == 0x80)
774 ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0352);
775 break;
776 case 0x13: /* ST M25P80. */
777 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
778 break;
779 case 0x1f: /* Atmel 26DF081A. */
821b3996 780 ha->fdt_block_size = FLASH_BLK_SIZE_4K;
7d232c74
AV		 781 ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0320);
782 ha->fdt_unprotect_sec_cmd = flash_conf_to_access_addr(0x0339);
783 ha->fdt_protect_sec_cmd = flash_conf_to_access_addr(0x0336);
784 break;
785 default:
786 /* Default to 64 kb sector size. */
787 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
788 break;
789 }
c00d8994
AV		 790done:
791 DEBUG2(qla_printk(KERN_DEBUG, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
821b3996 792 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
7d232c74 793 ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
821b3996 794 ha->fdt_unprotect_sec_cmd, ha->fdt_wrt_disable,
7d232c74
AV		 795 ha->fdt_block_size));
796}
797
c00d8994 798int
7b867cf7 799qla2xxx_get_flash_info(scsi_qla_host_t *vha)
c00d8994
AV		 800{
801 int ret;
802 uint32_t flt_addr;
7b867cf7 803 struct qla_hw_data *ha = vha->hw;
c00d8994
AV		 804
805 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
806 return QLA_SUCCESS;
807
7b867cf7 808 ret = qla2xxx_find_flt_start(vha, &flt_addr);
c00d8994
AV		 809 if (ret != QLA_SUCCESS)
810 return ret;
811
7b867cf7
AC		 812 qla2xxx_get_flt_info(vha, flt_addr);
813 qla2xxx_get_fdt_info(vha);
c00d8994
AV		 814
815 return QLA_SUCCESS;
816}
817
272976ca 818void
7b867cf7 819qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
272976ca
AV		 820{
821#define NPIV_CONFIG_SIZE (16*1024)
822 void *data;
823 uint16_t *wptr;
824 uint16_t cnt, chksum;
73208dfd 825 int i;
272976ca
AV		 826 struct qla_npiv_header hdr;
827 struct qla_npiv_entry *entry;
7b867cf7 828 struct qla_hw_data *ha = vha->hw;
272976ca
AV		 829
830 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
831 return;
832
7b867cf7 833 ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr,
272976ca
AV		 834 ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header));
835 if (hdr.version == __constant_cpu_to_le16(0xffff))
836 return;
837 if (hdr.version != __constant_cpu_to_le16(1)) {
838 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported NPIV-Config "
839 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
840 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
841 le16_to_cpu(hdr.checksum)));
842 return;
843 }
844
845 data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL);
846 if (!data) {
847 DEBUG2(qla_printk(KERN_INFO, ha, "NPIV-Config: Unable to "
848 "allocate memory.\n"));
849 return;
850 }
851
7b867cf7 852 ha->isp_ops->read_optrom(vha, (uint8_t *)data,
272976ca
AV		 853 ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE);
854
855 cnt = (sizeof(struct qla_npiv_header) + le16_to_cpu(hdr.entries) *
856 sizeof(struct qla_npiv_entry)) >> 1;
857 for (wptr = data, chksum = 0; cnt; cnt--)
858 chksum += le16_to_cpu(*wptr++);
859 if (chksum) {
860 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent NPIV-Config "
861 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
862 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
863 chksum));
864 goto done;
865 }
866
867 entry = data + sizeof(struct qla_npiv_header);
868 cnt = le16_to_cpu(hdr.entries);
73208dfd 869 for (i = 0; cnt; cnt--, entry++, i++) {
272976ca
AV		 870 uint16_t flags;
871 struct fc_vport_identifiers vid;
872 struct fc_vport *vport;
873
874 flags = le16_to_cpu(entry->flags);
875 if (flags == 0xffff)
876 continue;
877 if ((flags & BIT_0) == 0)
878 continue;
879
880 memset(&vid, 0, sizeof(vid));
881 vid.roles = FC_PORT_ROLE_FCP_INITIATOR;
882 vid.vport_type = FC_PORTTYPE_NPIV;
883 vid.disable = false;
884 vid.port_name = wwn_to_u64(entry->port_name);
885 vid.node_name = wwn_to_u64(entry->node_name);
886
73208dfd
AC		 887 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry));
888
272976ca 889 DEBUG2(qla_printk(KERN_DEBUG, ha, "NPIV[%02x]: wwpn=%llx "
73208dfd
AC		 890 "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt,
891 vid.port_name, vid.node_name, le16_to_cpu(entry->vf_id),
892 entry->q_qos, entry->f_qos));
893
894 if (i < QLA_PRECONFIG_VPORTS) {
895 vport = fc_vport_create(vha->host, 0, &vid);
896 if (!vport)
897 qla_printk(KERN_INFO, ha,
898 "NPIV-Config: Failed to create vport [%02x]: "
899 "wwpn=%llx wwnn=%llx.\n", cnt,
900 vid.port_name, vid.node_name);
901 }
272976ca
AV		 902 }
903done:
904 kfree(data);
73208dfd 905 ha->npiv_info = NULL;
272976ca
AV		 906}
907
cb8dacbf 908static void
7b867cf7 909qla24xx_unprotect_flash(struct qla_hw_data *ha)
cb8dacbf
AV		 910{
911 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
912
913 /* Enable flash write. */
914 WRT_REG_DWORD(&reg->ctrl_status,
915 RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
916 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
917
7d232c74
AV		 918 if (!ha->fdt_wrt_disable)
919 return;
920
cb8dacbf
AV		 921 /* Disable flash write-protection. */
922 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
923 /* Some flash parts need an additional zero-write to clear bits.*/
924 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
925}
926
927static void
7b867cf7 928qla24xx_protect_flash(struct qla_hw_data *ha)
cb8dacbf
AV		 929{
930 uint32_t cnt;
931 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
932
7d232c74
AV		 933 if (!ha->fdt_wrt_disable)
934 goto skip_wrt_protect;
935
cb8dacbf 936 /* Enable flash write-protection and wait for completion. */
7d232c74
AV		 937 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101),
938 ha->fdt_wrt_disable);
cb8dacbf
AV		 939 for (cnt = 300; cnt &&
940 qla24xx_read_flash_dword(ha,
941 flash_conf_to_access_addr(0x005)) & BIT_0;
942 cnt--) {
943 udelay(10);
944 }
945
7d232c74 946skip_wrt_protect:
cb8dacbf
AV		 947 /* Disable flash write. */
948 WRT_REG_DWORD(&reg->ctrl_status,
949 RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
950 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
951}
952
e5f82ab8 953static int
7b867cf7 954qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
459c5378
AV		 955 uint32_t dwords)
956{
957 int ret;
338c9161 958 uint32_t liter, miter;
7d232c74 959 uint32_t sec_mask, rest_addr;
cb8dacbf 960 uint32_t fdata, findex;
338c9161
AV		 961 dma_addr_t optrom_dma;
962 void *optrom = NULL;
963 uint32_t *s, *d;
7b867cf7 964 struct qla_hw_data *ha = vha->hw;
459c5378
AV		 965
966 ret = QLA_SUCCESS;
967
338c9161 968 /* Prepare burst-capable write on supported ISPs. */
b7cc176c 969 if (IS_QLA25XX(ha) && !(faddr & 0xfff) &&
338c9161
AV		 970 dwords > OPTROM_BURST_DWORDS) {
971 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
972 &optrom_dma, GFP_KERNEL);
973 if (!optrom) {
974 qla_printk(KERN_DEBUG, ha,
975 "Unable to allocate memory for optrom burst write "
976 "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
977 }
978 }
979
7d232c74
AV		 980 rest_addr = (ha->fdt_block_size >> 2) - 1;
981 sec_mask = 0x80000 - (ha->fdt_block_size >> 2);
459c5378 982
cb8dacbf 983 qla24xx_unprotect_flash(ha);
459c5378 984
338c9161 985 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
821b3996
LC		 986
987 findex = faddr;
988 fdata = (findex & sec_mask) << 2;
45aeaf1e 989
338c9161
AV		 990 /* Are we at the beginning of a sector? */
991 if ((findex & rest_addr) == 0) {
7d232c74
AV		 992 /* Do sector unprotect. */
993 if (ha->fdt_unprotect_sec_cmd)
338c9161 994 qla24xx_write_flash_dword(ha,
7d232c74 995 ha->fdt_unprotect_sec_cmd,
338c9161 996 (fdata & 0xff00) | ((fdata << 16) &
459c5378 997 0xff0000) | ((fdata >> 16) & 0xff));
7d232c74 998 ret = qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd,
338c9161
AV		 999 (fdata & 0xff00) |((fdata << 16) &
1000 0xff0000) | ((fdata >> 16) & 0xff));
1001 if (ret != QLA_SUCCESS) {
7b867cf7
AC		 1002 DEBUG9(qla_printk("Unable to flash sector: "
1003 "address=%x.\n", faddr));
338c9161 1004 break;
459c5378 1005 }
338c9161
AV		 1006 }
1007
1008 /* Go with burst-write. */
94d6a2b3 1009 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
338c9161
AV		 1010 /* Copy data to DMA'ble buffer. */
1011 for (miter = 0, s = optrom, d = dwptr;
1012 miter < OPTROM_BURST_DWORDS; miter++, s++, d++)
1013 *s = cpu_to_le32(*d);
1014
7b867cf7 1015 ret = qla2x00_load_ram(vha, optrom_dma,
459c5378 1016 flash_data_to_access_addr(faddr),
338c9161 1017 OPTROM_BURST_DWORDS);
459c5378 1018 if (ret != QLA_SUCCESS) {
338c9161
AV		 1019 qla_printk(KERN_WARNING, ha,
1020 "Unable to burst-write optrom segment "
1021 "(%x/%x/%llx).\n", ret,
1022 flash_data_to_access_addr(faddr),
875baf3c 1023 (unsigned long long)optrom_dma);
338c9161
AV		 1024 qla_printk(KERN_WARNING, ha,
1025 "Reverting to slow-write.\n");
1026
1027 dma_free_coherent(&ha->pdev->dev,
1028 OPTROM_BURST_SIZE, optrom, optrom_dma);
1029 optrom = NULL;
1030 } else {
1031 liter += OPTROM_BURST_DWORDS - 1;
1032 faddr += OPTROM_BURST_DWORDS - 1;
1033 dwptr += OPTROM_BURST_DWORDS - 1;
1034 continue;
459c5378 1035 }
338c9161 1036 }
45aeaf1e 1037
338c9161
AV		 1038 ret = qla24xx_write_flash_dword(ha,
1039 flash_data_to_access_addr(faddr), cpu_to_le32(*dwptr));
1040 if (ret != QLA_SUCCESS) {
1041 DEBUG9(printk("%s(%ld) Unable to program flash "
1042 "address=%x data=%x.\n", __func__,
7b867cf7 1043 vha->host_no, faddr, *dwptr));
338c9161 1044 break;
459c5378 1045 }
338c9161 1046
7d232c74
AV		 1047 /* Do sector protect. */
1048 if (ha->fdt_unprotect_sec_cmd &&
338c9161
AV		 1049 ((faddr & rest_addr) == rest_addr))
1050 qla24xx_write_flash_dword(ha,
7d232c74 1051 ha->fdt_protect_sec_cmd,
338c9161
AV		 1052 (fdata & 0xff00) | ((fdata << 16) &
1053 0xff0000) | ((fdata >> 16) & 0xff));
1054 }
459c5378 1055
cb8dacbf 1056 qla24xx_protect_flash(ha);
459c5378 1057
338c9161
AV		 1058 if (optrom)
1059 dma_free_coherent(&ha->pdev->dev,
1060 OPTROM_BURST_SIZE, optrom, optrom_dma);
1061
459c5378
AV		 1062 return ret;
1063}
1064
1065uint8_t *
7b867cf7 1066qla2x00_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
459c5378
AV		 1067 uint32_t bytes)
1068{
1069 uint32_t i;
1070 uint16_t *wptr;
7b867cf7 1071 struct qla_hw_data *ha = vha->hw;
459c5378
AV		 1072
1073 /* Word reads to NVRAM via registers. */
1074 wptr = (uint16_t *)buf;
1075 qla2x00_lock_nvram_access(ha);
1076 for (i = 0; i < bytes >> 1; i++, naddr++)
1077 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
1078 naddr));
1079 qla2x00_unlock_nvram_access(ha);
1080
1081 return buf;
1082}
1083
1084uint8_t *
7b867cf7 1085qla24xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
459c5378
AV		 1086 uint32_t bytes)
1087{
1088 uint32_t i;
1089 uint32_t *dwptr;
459c5378
AV		 1090
1091 /* Dword reads to flash. */
1092 dwptr = (uint32_t *)buf;
1093 for (i = 0; i < bytes >> 2; i++, naddr++)
7b867cf7 1094 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(vha->hw,
459c5378
AV		 1095 nvram_data_to_access_addr(naddr)));
1096
459c5378
AV		 1097 return buf;
1098}
1099
1100int
7b867cf7 1101qla2x00_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
459c5378
AV		 1102 uint32_t bytes)
1103{
1104 int ret, stat;
1105 uint32_t i;
1106 uint16_t *wptr;
2c96d8d0 1107 unsigned long flags;
7b867cf7 1108 struct qla_hw_data *ha = vha->hw;
459c5378
AV		 1109
1110 ret = QLA_SUCCESS;
1111
2c96d8d0 1112 spin_lock_irqsave(&ha->hardware_lock, flags);
459c5378
AV		 1113 qla2x00_lock_nvram_access(ha);
1114
1115 /* Disable NVRAM write-protection. */
1116 stat = qla2x00_clear_nvram_protection(ha);
1117
1118 wptr = (uint16_t *)buf;
1119 for (i = 0; i < bytes >> 1; i++, naddr++) {
1120 qla2x00_write_nvram_word(ha, naddr,
1121 cpu_to_le16(*wptr));
1122 wptr++;
1123 }
1124
1125 /* Enable NVRAM write-protection. */
1126 qla2x00_set_nvram_protection(ha, stat);
1127
1128 qla2x00_unlock_nvram_access(ha);
2c96d8d0 1129 spin_unlock_irqrestore(&ha->hardware_lock, flags);
459c5378
AV		 1130
1131 return ret;
1132}
1133
1134int
7b867cf7 1135qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
459c5378
AV		 1136 uint32_t bytes)
1137{
1138 int ret;
1139 uint32_t i;
1140 uint32_t *dwptr;
7b867cf7 1141 struct qla_hw_data *ha = vha->hw;
459c5378
AV		 1142 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1143
1144 ret = QLA_SUCCESS;
1145
459c5378
AV		 1146 /* Enable flash write. */
1147 WRT_REG_DWORD(&reg->ctrl_status,
1148 RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1149 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1150
1151 /* Disable NVRAM write-protection. */
1152 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
1153 0);
1154 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
1155 0);
1156
1157 /* Dword writes to flash. */
1158 dwptr = (uint32_t *)buf;
1159 for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
1160 ret = qla24xx_write_flash_dword(ha,
1161 nvram_data_to_access_addr(naddr),
1162 cpu_to_le32(*dwptr));
1163 if (ret != QLA_SUCCESS) {
7b867cf7
AC		 1164 DEBUG9(qla_printk("Unable to program nvram address=%x "
1165 "data=%x.\n", naddr, *dwptr));
459c5378
AV		 1166 break;
1167 }
1168 }
1169
1170 /* Enable NVRAM write-protection. */
1171 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
1172 0x8c);
1173
1174 /* Disable flash write. */
1175 WRT_REG_DWORD(&reg->ctrl_status,
1176 RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1177 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1178
459c5378
AV		 1179 return ret;
1180}
f6df144c 1181
c3a2f0df 1182uint8_t *
7b867cf7 1183qla25xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
c3a2f0df
AV		 1184 uint32_t bytes)
1185{
1186 uint32_t i;
1187 uint32_t *dwptr;
7b867cf7 1188 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 1189
1190 /* Dword reads to flash. */
1191 dwptr = (uint32_t *)buf;
1192 for (i = 0; i < bytes >> 2; i++, naddr++)
1193 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
c00d8994
AV		 1194 flash_data_to_access_addr(ha->flt_region_vpd_nvram |
1195 naddr)));
c3a2f0df
AV		 1196
1197 return buf;
1198}
1199
1200int
7b867cf7 1201qla25xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
c3a2f0df
AV		 1202 uint32_t bytes)
1203{
7b867cf7 1204 struct qla_hw_data *ha = vha->hw;
2c96d8d0
AV		 1205#define RMW_BUFFER_SIZE (64 * 1024)
1206 uint8_t *dbuf;
1207
1208 dbuf = vmalloc(RMW_BUFFER_SIZE);
1209 if (!dbuf)
1210 return QLA_MEMORY_ALLOC_FAILED;
7b867cf7 1211 ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
2c96d8d0
AV		 1212 RMW_BUFFER_SIZE);
1213 memcpy(dbuf + (naddr << 2), buf, bytes);
7b867cf7 1214 ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
2c96d8d0
AV		 1215 RMW_BUFFER_SIZE);
1216 vfree(dbuf);
1217
1218 return QLA_SUCCESS;
c3a2f0df 1219}
f6df144c 1220
1221static inline void
7b867cf7 1222qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
f6df144c 1223{
1224 if (IS_QLA2322(ha)) {
1225 /* Flip all colors. */
1226 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1227 /* Turn off. */
1228 ha->beacon_color_state = 0;
1229 *pflags = GPIO_LED_ALL_OFF;
1230 } else {
1231 /* Turn on. */
1232 ha->beacon_color_state = QLA_LED_ALL_ON;
1233 *pflags = GPIO_LED_RGA_ON;
1234 }
1235 } else {
1236 /* Flip green led only. */
1237 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
1238 /* Turn off. */
1239 ha->beacon_color_state = 0;
1240 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
1241 } else {
1242 /* Turn on. */
1243 ha->beacon_color_state = QLA_LED_GRN_ON;
1244 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
1245 }
1246 }
1247}
1248
948882f6
AV		 1249#define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1250
f6df144c 1251void
7b867cf7 1252qla2x00_beacon_blink(struct scsi_qla_host *vha)
f6df144c 1253{
1254 uint16_t gpio_enable;
1255 uint16_t gpio_data;
1256 uint16_t led_color = 0;
1257 unsigned long flags;
7b867cf7 1258 struct qla_hw_data *ha = vha->hw;
f6df144c 1259 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1260
f6df144c 1261 spin_lock_irqsave(&ha->hardware_lock, flags);
1262
1263 /* Save the Original GPIOE. */
1264 if (ha->pio_address) {
948882f6
AV		 1265 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1266 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
f6df144c 1267 } else {
1268 gpio_enable = RD_REG_WORD(&reg->gpioe);
1269 gpio_data = RD_REG_WORD(&reg->gpiod);
1270 }
1271
1272 /* Set the modified gpio_enable values */
1273 gpio_enable |= GPIO_LED_MASK;
1274
1275 if (ha->pio_address) {
948882f6 1276 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
f6df144c 1277 } else {
1278 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1279 RD_REG_WORD(&reg->gpioe);
1280 }
1281
1282 qla2x00_flip_colors(ha, &led_color);
1283
1284 /* Clear out any previously set LED color. */
1285 gpio_data &= ~GPIO_LED_MASK;
1286
1287 /* Set the new input LED color to GPIOD. */
1288 gpio_data |= led_color;
1289
1290 /* Set the modified gpio_data values */
1291 if (ha->pio_address) {
948882f6 1292 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
f6df144c 1293 } else {
1294 WRT_REG_WORD(&reg->gpiod, gpio_data);
1295 RD_REG_WORD(&reg->gpiod);
1296 }
1297
1298 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1299}
1300
1301int
7b867cf7 1302qla2x00_beacon_on(struct scsi_qla_host *vha)
f6df144c 1303{
1304 uint16_t gpio_enable;
1305 uint16_t gpio_data;
1306 unsigned long flags;
7b867cf7 1307 struct qla_hw_data *ha = vha->hw;
f6df144c 1308 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1309
1310 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1311 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
1312
7b867cf7 1313 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
f6df144c 1314 qla_printk(KERN_WARNING, ha,
1315 "Unable to update fw options (beacon on).\n");
1316 return QLA_FUNCTION_FAILED;
1317 }
1318
f6df144c 1319 /* Turn off LEDs. */
1320 spin_lock_irqsave(&ha->hardware_lock, flags);
1321 if (ha->pio_address) {
948882f6
AV		 1322 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1323 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
f6df144c 1324 } else {
1325 gpio_enable = RD_REG_WORD(&reg->gpioe);
1326 gpio_data = RD_REG_WORD(&reg->gpiod);
1327 }
1328 gpio_enable |= GPIO_LED_MASK;
1329
1330 /* Set the modified gpio_enable values. */
1331 if (ha->pio_address) {
948882f6 1332 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
f6df144c 1333 } else {
1334 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1335 RD_REG_WORD(&reg->gpioe);
1336 }
1337
1338 /* Clear out previously set LED colour. */
1339 gpio_data &= ~GPIO_LED_MASK;
1340 if (ha->pio_address) {
948882f6 1341 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
f6df144c 1342 } else {
1343 WRT_REG_WORD(&reg->gpiod, gpio_data);
1344 RD_REG_WORD(&reg->gpiod);
1345 }
1346 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1347
1348 /*
1349 * Let the per HBA timer kick off the blinking process based on
1350 * the following flags. No need to do anything else now.
1351 */
1352 ha->beacon_blink_led = 1;
1353 ha->beacon_color_state = 0;
1354
1355 return QLA_SUCCESS;
1356}
1357
1358int
7b867cf7 1359qla2x00_beacon_off(struct scsi_qla_host *vha)
f6df144c 1360{
1361 int rval = QLA_SUCCESS;
7b867cf7 1362 struct qla_hw_data *ha = vha->hw;
f6df144c 1363
1364 ha->beacon_blink_led = 0;
1365
1366 /* Set the on flag so when it gets flipped it will be off. */
1367 if (IS_QLA2322(ha))
1368 ha->beacon_color_state = QLA_LED_ALL_ON;
1369 else
1370 ha->beacon_color_state = QLA_LED_GRN_ON;
1371
7b867cf7 1372 ha->isp_ops->beacon_blink(vha); /* This turns green LED off */
f6df144c 1373
1374 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1375 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1376
7b867cf7 1377 rval = qla2x00_set_fw_options(vha, ha->fw_options);
f6df144c 1378 if (rval != QLA_SUCCESS)
1379 qla_printk(KERN_WARNING, ha,
1380 "Unable to update fw options (beacon off).\n");
1381 return rval;
1382}
1383
1384
1385static inline void
7b867cf7 1386qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
f6df144c 1387{
1388 /* Flip all colors. */
1389 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1390 /* Turn off. */
1391 ha->beacon_color_state = 0;
1392 *pflags = 0;
1393 } else {
1394 /* Turn on. */
1395 ha->beacon_color_state = QLA_LED_ALL_ON;
1396 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1397 }
1398}
1399
1400void
7b867cf7 1401qla24xx_beacon_blink(struct scsi_qla_host *vha)
f6df144c 1402{
1403 uint16_t led_color = 0;
1404 uint32_t gpio_data;
1405 unsigned long flags;
7b867cf7 1406 struct qla_hw_data *ha = vha->hw;
f6df144c 1407 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1408
1409 /* Save the Original GPIOD. */
1410 spin_lock_irqsave(&ha->hardware_lock, flags);
1411 gpio_data = RD_REG_DWORD(&reg->gpiod);
1412
1413 /* Enable the gpio_data reg for update. */
1414 gpio_data |= GPDX_LED_UPDATE_MASK;
1415
1416 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1417 gpio_data = RD_REG_DWORD(&reg->gpiod);
1418
1419 /* Set the color bits. */
1420 qla24xx_flip_colors(ha, &led_color);
1421
1422 /* Clear out any previously set LED color. */
1423 gpio_data &= ~GPDX_LED_COLOR_MASK;
1424
1425 /* Set the new input LED color to GPIOD. */
1426 gpio_data |= led_color;
1427
1428 /* Set the modified gpio_data values. */
1429 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1430 gpio_data = RD_REG_DWORD(&reg->gpiod);
1431 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1432}
1433
1434int
7b867cf7 1435qla24xx_beacon_on(struct scsi_qla_host *vha)
f6df144c 1436{
1437 uint32_t gpio_data;
1438 unsigned long flags;
7b867cf7 1439 struct qla_hw_data *ha = vha->hw;
f6df144c 1440 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1441
1442 if (ha->beacon_blink_led == 0) {
1443 /* Enable firmware for update */
1444 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1445
7b867cf7 1446 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS)
f6df144c 1447 return QLA_FUNCTION_FAILED;
1448
7b867cf7 1449 if (qla2x00_get_fw_options(vha, ha->fw_options) !=
f6df144c 1450 QLA_SUCCESS) {
1451 qla_printk(KERN_WARNING, ha,
1452 "Unable to update fw options (beacon on).\n");
1453 return QLA_FUNCTION_FAILED;
1454 }
1455
1456 spin_lock_irqsave(&ha->hardware_lock, flags);
1457 gpio_data = RD_REG_DWORD(&reg->gpiod);
1458
1459 /* Enable the gpio_data reg for update. */
1460 gpio_data |= GPDX_LED_UPDATE_MASK;
1461 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1462 RD_REG_DWORD(&reg->gpiod);
1463
1464 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1465 }
1466
1467 /* So all colors blink together. */
1468 ha->beacon_color_state = 0;
1469
1470 /* Let the per HBA timer kick off the blinking process. */
1471 ha->beacon_blink_led = 1;
1472
1473 return QLA_SUCCESS;
1474}
1475
1476int
7b867cf7 1477qla24xx_beacon_off(struct scsi_qla_host *vha)
f6df144c 1478{
1479 uint32_t gpio_data;
1480 unsigned long flags;
7b867cf7 1481 struct qla_hw_data *ha = vha->hw;
f6df144c 1482 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1483
1484 ha->beacon_blink_led = 0;
1485 ha->beacon_color_state = QLA_LED_ALL_ON;
1486
7b867cf7 1487 ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */
f6df144c 1488
1489 /* Give control back to firmware. */
1490 spin_lock_irqsave(&ha->hardware_lock, flags);
1491 gpio_data = RD_REG_DWORD(&reg->gpiod);
1492
1493 /* Disable the gpio_data reg for update. */
1494 gpio_data &= ~GPDX_LED_UPDATE_MASK;
1495 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1496 RD_REG_DWORD(&reg->gpiod);
1497 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1498
1499 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1500
7b867cf7 1501 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
f6df144c 1502 qla_printk(KERN_WARNING, ha,
1503 "Unable to update fw options (beacon off).\n");
1504 return QLA_FUNCTION_FAILED;
1505 }
1506
7b867cf7 1507 if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
f6df144c 1508 qla_printk(KERN_WARNING, ha,
1509 "Unable to get fw options (beacon off).\n");
1510 return QLA_FUNCTION_FAILED;
1511 }
1512
1513 return QLA_SUCCESS;
1514}
854165f4 1515
1516
1517/*
1518 * Flash support routines
1519 */
1520
1521/**
1522 * qla2x00_flash_enable() - Setup flash for reading and writing.
1523 * @ha: HA context
1524 */
1525static void
7b867cf7 1526qla2x00_flash_enable(struct qla_hw_data *ha)
854165f4 1527{
1528 uint16_t data;
1529 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1530
1531 data = RD_REG_WORD(&reg->ctrl_status);
1532 data |= CSR_FLASH_ENABLE;
1533 WRT_REG_WORD(&reg->ctrl_status, data);
1534 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1535}
1536
1537/**
1538 * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1539 * @ha: HA context
1540 */
1541static void
7b867cf7 1542qla2x00_flash_disable(struct qla_hw_data *ha)
854165f4 1543{
1544 uint16_t data;
1545 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1546
1547 data = RD_REG_WORD(&reg->ctrl_status);
1548 data &= ~(CSR_FLASH_ENABLE);
1549 WRT_REG_WORD(&reg->ctrl_status, data);
1550 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1551}
1552
1553/**
1554 * qla2x00_read_flash_byte() - Reads a byte from flash
1555 * @ha: HA context
1556 * @addr: Address in flash to read
1557 *
1558 * A word is read from the chip, but, only the lower byte is valid.
1559 *
1560 * Returns the byte read from flash @addr.
1561 */
1562static uint8_t
7b867cf7 1563qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr)
854165f4 1564{
1565 uint16_t data;
1566 uint16_t bank_select;
1567 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1568
1569 bank_select = RD_REG_WORD(&reg->ctrl_status);
1570
1571 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1572 /* Specify 64K address range: */
1573 /* clear out Module Select and Flash Address bits [19:16]. */
1574 bank_select &= ~0xf8;
1575 bank_select |= addr >> 12 & 0xf0;
1576 bank_select |= CSR_FLASH_64K_BANK;
1577 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1578 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1579
1580 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1581 data = RD_REG_WORD(&reg->flash_data);
1582
1583 return (uint8_t)data;
1584 }
1585
1586 /* Setup bit 16 of flash address. */
1587 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1588 bank_select |= CSR_FLASH_64K_BANK;
1589 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1590 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1591 } else if (((addr & BIT_16) == 0) &&
1592 (bank_select & CSR_FLASH_64K_BANK)) {
1593 bank_select &= ~(CSR_FLASH_64K_BANK);
1594 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1595 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1596 }
1597
1598 /* Always perform IO mapped accesses to the FLASH registers. */
1599 if (ha->pio_address) {
1600 uint16_t data2;
1601
948882f6 1602 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
854165f4 1603 do {
948882f6 1604 data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
854165f4 1605 barrier();
1606 cpu_relax();
948882f6 1607 data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
854165f4 1608 } while (data != data2);
1609 } else {
1610 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1611 data = qla2x00_debounce_register(&reg->flash_data);
1612 }
1613
1614 return (uint8_t)data;
1615}
1616
1617/**
1618 * qla2x00_write_flash_byte() - Write a byte to flash
1619 * @ha: HA context
1620 * @addr: Address in flash to write
1621 * @data: Data to write
1622 */
1623static void
7b867cf7 1624qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data)
854165f4 1625{
1626 uint16_t bank_select;
1627 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1628
1629 bank_select = RD_REG_WORD(&reg->ctrl_status);
1630 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1631 /* Specify 64K address range: */
1632 /* clear out Module Select and Flash Address bits [19:16]. */
1633 bank_select &= ~0xf8;
1634 bank_select |= addr >> 12 & 0xf0;
1635 bank_select |= CSR_FLASH_64K_BANK;
1636 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1637 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1638
1639 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1640 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1641 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1642 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1643
1644 return;
1645 }
1646
1647 /* Setup bit 16 of flash address. */
1648 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1649 bank_select |= CSR_FLASH_64K_BANK;
1650 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1651 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1652 } else if (((addr & BIT_16) == 0) &&
1653 (bank_select & CSR_FLASH_64K_BANK)) {
1654 bank_select &= ~(CSR_FLASH_64K_BANK);
1655 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1656 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1657 }
1658
1659 /* Always perform IO mapped accesses to the FLASH registers. */
1660 if (ha->pio_address) {
948882f6
AV		 1661 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1662 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
854165f4 1663 } else {
1664 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1665 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1666 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1667 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1668 }
1669}
1670
1671/**
1672 * qla2x00_poll_flash() - Polls flash for completion.
1673 * @ha: HA context
1674 * @addr: Address in flash to poll
1675 * @poll_data: Data to be polled
1676 * @man_id: Flash manufacturer ID
1677 * @flash_id: Flash ID
1678 *
1679 * This function polls the device until bit 7 of what is read matches data
1680 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed
1681 * out (a fatal error). The flash book recommeds reading bit 7 again after
1682 * reading bit 5 as a 1.
1683 *
1684 * Returns 0 on success, else non-zero.
1685 */
1686static int
7b867cf7 1687qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data,
854165f4 1688 uint8_t man_id, uint8_t flash_id)
1689{
1690 int status;
1691 uint8_t flash_data;
1692 uint32_t cnt;
1693
1694 status = 1;
1695
1696 /* Wait for 30 seconds for command to finish. */
1697 poll_data &= BIT_7;
1698 for (cnt = 3000000; cnt; cnt--) {
1699 flash_data = qla2x00_read_flash_byte(ha, addr);
1700 if ((flash_data & BIT_7) == poll_data) {
1701 status = 0;
1702 break;
1703 }
1704
1705 if (man_id != 0x40 && man_id != 0xda) {
1706 if ((flash_data & BIT_5) && cnt > 2)
1707 cnt = 2;
1708 }
1709 udelay(10);
1710 barrier();
40a2e34a 1711 cond_resched();
854165f4 1712 }
1713 return status;
1714}
1715
854165f4 1716/**
1717 * qla2x00_program_flash_address() - Programs a flash address
1718 * @ha: HA context
1719 * @addr: Address in flash to program
1720 * @data: Data to be written in flash
1721 * @man_id: Flash manufacturer ID
1722 * @flash_id: Flash ID
1723 *
1724 * Returns 0 on success, else non-zero.
1725 */
1726static int
7b867cf7
AC		 1727qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr,
1728 uint8_t data, uint8_t man_id, uint8_t flash_id)
854165f4 1729{
1730 /* Write Program Command Sequence. */
1731 if (IS_OEM_001(ha)) {
1732 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1733 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1734 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
1735 qla2x00_write_flash_byte(ha, addr, data);
1736 } else {
1737 if (man_id == 0xda && flash_id == 0xc1) {
1738 qla2x00_write_flash_byte(ha, addr, data);
1739 if (addr & 0x7e)
1740 return 0;
1741 } else {
1742 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1743 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1744 qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
1745 qla2x00_write_flash_byte(ha, addr, data);
1746 }
1747 }
1748
1749 udelay(150);
1750
1751 /* Wait for write to complete. */
1752 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
1753}
1754
1755/**
1756 * qla2x00_erase_flash() - Erase the flash.
1757 * @ha: HA context
1758 * @man_id: Flash manufacturer ID
1759 * @flash_id: Flash ID
1760 *
1761 * Returns 0 on success, else non-zero.
1762 */
1763static int
7b867cf7 1764qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id)
854165f4 1765{
1766 /* Individual Sector Erase Command Sequence */
1767 if (IS_OEM_001(ha)) {
1768 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1769 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1770 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
1771 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1772 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1773 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
1774 } else {
1775 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1776 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1777 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1778 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1779 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1780 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
1781 }
1782
1783 udelay(150);
1784
1785 /* Wait for erase to complete. */
1786 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
1787}
1788
1789/**
1790 * qla2x00_erase_flash_sector() - Erase a flash sector.
1791 * @ha: HA context
1792 * @addr: Flash sector to erase
1793 * @sec_mask: Sector address mask
1794 * @man_id: Flash manufacturer ID
1795 * @flash_id: Flash ID
1796 *
1797 * Returns 0 on success, else non-zero.
1798 */
1799static int
7b867cf7 1800qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr,
854165f4 1801 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
1802{
1803 /* Individual Sector Erase Command Sequence */
1804 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1805 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1806 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1807 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1808 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1809 if (man_id == 0x1f && flash_id == 0x13)
1810 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
1811 else
1812 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
1813
1814 udelay(150);
1815
1816 /* Wait for erase to complete. */
1817 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
1818}
1819
1820/**
1821 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
1822 * @man_id: Flash manufacturer ID
1823 * @flash_id: Flash ID
1824 */
1825static void
7b867cf7 1826qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
854165f4 1827 uint8_t *flash_id)
1828{
1829 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1830 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1831 qla2x00_write_flash_byte(ha, 0x5555, 0x90);
1832 *man_id = qla2x00_read_flash_byte(ha, 0x0000);
1833 *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
1834 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1835 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1836 qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
1837}
1838
30c47662 1839static void
7b867cf7
AC		 1840qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf,
1841 uint32_t saddr, uint32_t length)
30c47662
AV		 1842{
1843 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1844 uint32_t midpoint, ilength;
1845 uint8_t data;
1846
1847 midpoint = length / 2;
1848
1849 WRT_REG_WORD(&reg->nvram, 0);
1850 RD_REG_WORD(&reg->nvram);
1851 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
1852 if (ilength == midpoint) {
1853 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1854 RD_REG_WORD(&reg->nvram);
1855 }
1856 data = qla2x00_read_flash_byte(ha, saddr);
1857 if (saddr % 100)
1858 udelay(10);
1859 *tmp_buf = data;
40a2e34a 1860 cond_resched();
30c47662
AV		 1861 }
1862}
854165f4 1863
1864static inline void
7b867cf7 1865qla2x00_suspend_hba(struct scsi_qla_host *vha)
854165f4 1866{
1867 int cnt;
1868 unsigned long flags;
7b867cf7 1869 struct qla_hw_data *ha = vha->hw;
854165f4 1870 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1871
1872 /* Suspend HBA. */
7b867cf7 1873 scsi_block_requests(vha->host);
fd34f556 1874 ha->isp_ops->disable_intrs(ha);
854165f4 1875 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1876
1877 /* Pause RISC. */
1878 spin_lock_irqsave(&ha->hardware_lock, flags);
1879 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1880 RD_REG_WORD(&reg->hccr);
1881 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1882 for (cnt = 0; cnt < 30000; cnt++) {
1883 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
1884 break;
1885 udelay(100);
1886 }
1887 } else {
1888 udelay(10);
1889 }
1890 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1891}
1892
1893static inline void
7b867cf7 1894qla2x00_resume_hba(struct scsi_qla_host *vha)
854165f4 1895{
7b867cf7
AC		 1896 struct qla_hw_data *ha = vha->hw;
1897
854165f4 1898 /* Resume HBA. */
1899 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
7b867cf7
AC		 1900 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1901 qla2xxx_wake_dpc(vha);
1902 qla2x00_wait_for_hba_online(vha);
1903 scsi_unblock_requests(vha->host);
854165f4 1904}
1905
1906uint8_t *
7b867cf7 1907qla2x00_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
854165f4 1908 uint32_t offset, uint32_t length)
1909{
854165f4 1910 uint32_t addr, midpoint;
1911 uint8_t *data;
7b867cf7 1912 struct qla_hw_data *ha = vha->hw;
854165f4 1913 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1914
1915 /* Suspend HBA. */
7b867cf7 1916 qla2x00_suspend_hba(vha);
854165f4 1917
1918 /* Go with read. */
854165f4 1919 midpoint = ha->optrom_size / 2;
1920
1921 qla2x00_flash_enable(ha);
1922 WRT_REG_WORD(&reg->nvram, 0);
1923 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
1924 for (addr = offset, data = buf; addr < length; addr++, data++) {
1925 if (addr == midpoint) {
1926 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1927 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
1928 }
1929
1930 *data = qla2x00_read_flash_byte(ha, addr);
1931 }
1932 qla2x00_flash_disable(ha);
854165f4 1933
1934 /* Resume HBA. */
7b867cf7 1935 qla2x00_resume_hba(vha);
854165f4 1936
1937 return buf;
1938}
1939
1940int
7b867cf7 1941qla2x00_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
854165f4 1942 uint32_t offset, uint32_t length)
1943{
1944
1945 int rval;
854165f4 1946 uint8_t man_id, flash_id, sec_number, data;
1947 uint16_t wd;
1948 uint32_t addr, liter, sec_mask, rest_addr;
7b867cf7 1949 struct qla_hw_data *ha = vha->hw;
854165f4 1950 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1951
1952 /* Suspend HBA. */
7b867cf7 1953 qla2x00_suspend_hba(vha);
854165f4 1954
1955 rval = QLA_SUCCESS;
1956 sec_number = 0;
1957
1958 /* Reset ISP chip. */
854165f4 1959 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1960 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
1961
1962 /* Go with write. */
1963 qla2x00_flash_enable(ha);
1964 do { /* Loop once to provide quick error exit */
1965 /* Structure of flash memory based on manufacturer */
1966 if (IS_OEM_001(ha)) {
1967 /* OEM variant with special flash part. */
1968 man_id = flash_id = 0;
1969 rest_addr = 0xffff;
1970 sec_mask = 0x10000;
1971 goto update_flash;
1972 }
1973 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
1974 switch (man_id) {
1975 case 0x20: /* ST flash. */
1976 if (flash_id == 0xd2 || flash_id == 0xe3) {
1977 /*
1978 * ST m29w008at part - 64kb sector size with
1979 * 32kb,8kb,8kb,16kb sectors at memory address
1980 * 0xf0000.
1981 */
1982 rest_addr = 0xffff;
1983 sec_mask = 0x10000;
1984 break;
1985 }
1986 /*
1987 * ST m29w010b part - 16kb sector size
1988 * Default to 16kb sectors
1989 */
1990 rest_addr = 0x3fff;
1991 sec_mask = 0x1c000;
1992 break;
1993 case 0x40: /* Mostel flash. */
1994 /* Mostel v29c51001 part - 512 byte sector size. */
1995 rest_addr = 0x1ff;
1996 sec_mask = 0x1fe00;
1997 break;
1998 case 0xbf: /* SST flash. */
1999 /* SST39sf10 part - 4kb sector size. */
2000 rest_addr = 0xfff;
2001 sec_mask = 0x1f000;
2002 break;
2003 case 0xda: /* Winbond flash. */
2004 /* Winbond W29EE011 part - 256 byte sector size. */
2005 rest_addr = 0x7f;
2006 sec_mask = 0x1ff80;
2007 break;
2008 case 0xc2: /* Macronix flash. */
2009 /* 64k sector size. */
2010 if (flash_id == 0x38 || flash_id == 0x4f) {
2011 rest_addr = 0xffff;
2012 sec_mask = 0x10000;
2013 break;
2014 }
2015 /* Fall through... */
2016
2017 case 0x1f: /* Atmel flash. */
2018 /* 512k sector size. */
2019 if (flash_id == 0x13) {
2020 rest_addr = 0x7fffffff;
2021 sec_mask = 0x80000000;
2022 break;
2023 }
2024 /* Fall through... */
2025
2026 case 0x01: /* AMD flash. */
2027 if (flash_id == 0x38 || flash_id == 0x40 ||
2028 flash_id == 0x4f) {
2029 /* Am29LV081 part - 64kb sector size. */
2030 /* Am29LV002BT part - 64kb sector size. */
2031 rest_addr = 0xffff;
2032 sec_mask = 0x10000;
2033 break;
2034 } else if (flash_id == 0x3e) {
2035 /*
2036 * Am29LV008b part - 64kb sector size with
2037 * 32kb,8kb,8kb,16kb sector at memory address
2038 * h0xf0000.
2039 */
2040 rest_addr = 0xffff;
2041 sec_mask = 0x10000;
2042 break;
2043 } else if (flash_id == 0x20 || flash_id == 0x6e) {
2044 /*
2045 * Am29LV010 part or AM29f010 - 16kb sector
2046 * size.
2047 */
2048 rest_addr = 0x3fff;
2049 sec_mask = 0x1c000;
2050 break;
2051 } else if (flash_id == 0x6d) {
2052 /* Am29LV001 part - 8kb sector size. */
2053 rest_addr = 0x1fff;
2054 sec_mask = 0x1e000;
2055 break;
2056 }
2057 default:
2058 /* Default to 16 kb sector size. */
2059 rest_addr = 0x3fff;
2060 sec_mask = 0x1c000;
2061 break;
2062 }
2063
2064update_flash:
2065 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2066 if (qla2x00_erase_flash(ha, man_id, flash_id)) {
2067 rval = QLA_FUNCTION_FAILED;
2068 break;
2069 }
2070 }
2071
2072 for (addr = offset, liter = 0; liter < length; liter++,
2073 addr++) {
2074 data = buf[liter];
2075 /* Are we at the beginning of a sector? */
2076 if ((addr & rest_addr) == 0) {
2077 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2078 if (addr >= 0x10000UL) {
2079 if (((addr >> 12) & 0xf0) &&
2080 ((man_id == 0x01 &&
2081 flash_id == 0x3e) ||
2082 (man_id == 0x20 &&
2083 flash_id == 0xd2))) {
2084 sec_number++;
2085 if (sec_number == 1) {
2086 rest_addr =
2087 0x7fff;
2088 sec_mask =
2089 0x18000;
2090 } else if (
2091 sec_number == 2 ||
2092 sec_number == 3) {
2093 rest_addr =
2094 0x1fff;
2095 sec_mask =
2096 0x1e000;
2097 } else if (
2098 sec_number == 4) {
2099 rest_addr =
2100 0x3fff;
2101 sec_mask =
2102 0x1c000;
2103 }
2104 }
2105 }
2106 } else if (addr == ha->optrom_size / 2) {
2107 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2108 RD_REG_WORD(&reg->nvram);
2109 }
2110
2111 if (flash_id == 0xda && man_id == 0xc1) {
2112 qla2x00_write_flash_byte(ha, 0x5555,
2113 0xaa);
2114 qla2x00_write_flash_byte(ha, 0x2aaa,
2115 0x55);
2116 qla2x00_write_flash_byte(ha, 0x5555,
2117 0xa0);
2118 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
2119 /* Then erase it */
2120 if (qla2x00_erase_flash_sector(ha,
2121 addr, sec_mask, man_id,
2122 flash_id)) {
2123 rval = QLA_FUNCTION_FAILED;
2124 break;
2125 }
2126 if (man_id == 0x01 && flash_id == 0x6d)
2127 sec_number++;
2128 }
2129 }
2130
2131 if (man_id == 0x01 && flash_id == 0x6d) {
2132 if (sec_number == 1 &&
2133 addr == (rest_addr - 1)) {
2134 rest_addr = 0x0fff;
2135 sec_mask = 0x1f000;
2136 } else if (sec_number == 3 && (addr & 0x7ffe)) {
2137 rest_addr = 0x3fff;
2138 sec_mask = 0x1c000;
2139 }
2140 }
2141
2142 if (qla2x00_program_flash_address(ha, addr, data,
2143 man_id, flash_id)) {
2144 rval = QLA_FUNCTION_FAILED;
2145 break;
2146 }
40a2e34a 2147 cond_resched();
854165f4 2148 }
2149 } while (0);
2150 qla2x00_flash_disable(ha);
854165f4 2151
2152 /* Resume HBA. */
7b867cf7 2153 qla2x00_resume_hba(vha);
854165f4 2154
2155 return rval;
2156}
2157
2158uint8_t *
7b867cf7 2159qla24xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
854165f4 2160 uint32_t offset, uint32_t length)
2161{
7b867cf7
AC		 2162 struct qla_hw_data *ha = vha->hw;
2163
854165f4 2164 /* Suspend HBA. */
7b867cf7 2165 scsi_block_requests(vha->host);
854165f4 2166 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2167
2168 /* Go with read. */
7b867cf7 2169 qla24xx_read_flash_data(vha, (uint32_t *)buf, offset >> 2, length >> 2);
854165f4 2170
2171 /* Resume HBA. */
2172 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
7b867cf7 2173 scsi_unblock_requests(vha->host);
854165f4 2174
2175 return buf;
2176}
2177
2178int
7b867cf7 2179qla24xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
854165f4 2180 uint32_t offset, uint32_t length)
2181{
2182 int rval;
7b867cf7 2183 struct qla_hw_data *ha = vha->hw;
854165f4 2184
2185 /* Suspend HBA. */
7b867cf7 2186 scsi_block_requests(vha->host);
854165f4 2187 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2188
2189 /* Go with write. */
7b867cf7 2190 rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, offset >> 2,
854165f4 2191 length >> 2);
2192
2193 /* Resume HBA -- RISC reset needed. */
2194 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
7b867cf7
AC		 2195 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2196 qla2xxx_wake_dpc(vha);
2197 qla2x00_wait_for_hba_online(vha);
2198 scsi_unblock_requests(vha->host);
854165f4 2199
2200 return rval;
2201}
30c47662 2202
338c9161 2203uint8_t *
7b867cf7 2204qla25xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
338c9161
AV		 2205 uint32_t offset, uint32_t length)
2206{
2207 int rval;
2208 dma_addr_t optrom_dma;
2209 void *optrom;
2210 uint8_t *pbuf;
2211 uint32_t faddr, left, burst;
7b867cf7 2212 struct qla_hw_data *ha = vha->hw;
338c9161 2213
b7cc176c 2214 if (offset & 0xfff)
338c9161
AV		 2215 goto slow_read;
2216 if (length < OPTROM_BURST_SIZE)
2217 goto slow_read;
2218
2219 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2220 &optrom_dma, GFP_KERNEL);
2221 if (!optrom) {
2222 qla_printk(KERN_DEBUG, ha,
2223 "Unable to allocate memory for optrom burst read "
2224 "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
2225
2226 goto slow_read;
2227 }
2228
2229 pbuf = buf;
2230 faddr = offset >> 2;
2231 left = length >> 2;
2232 burst = OPTROM_BURST_DWORDS;
2233 while (left != 0) {
2234 if (burst > left)
2235 burst = left;
2236
7b867cf7 2237 rval = qla2x00_dump_ram(vha, optrom_dma,
338c9161
AV		 2238 flash_data_to_access_addr(faddr), burst);
2239 if (rval) {
2240 qla_printk(KERN_WARNING, ha,
2241 "Unable to burst-read optrom segment "
2242 "(%x/%x/%llx).\n", rval,
875baf3c
AM		 2243 flash_data_to_access_addr(faddr),
2244 (unsigned long long)optrom_dma);
338c9161
AV		 2245 qla_printk(KERN_WARNING, ha,
2246 "Reverting to slow-read.\n");
2247
2248 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2249 optrom, optrom_dma);
2250 goto slow_read;
2251 }
2252
2253 memcpy(pbuf, optrom, burst * 4);
2254
2255 left -= burst;
2256 faddr += burst;
2257 pbuf += burst * 4;
2258 }
2259
2260 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
2261 optrom_dma);
2262
2263 return buf;
2264
2265slow_read:
7b867cf7 2266 return qla24xx_read_optrom_data(vha, buf, offset, length);
338c9161
AV		 2267}
2268
30c47662
AV		 2269/**
2270 * qla2x00_get_fcode_version() - Determine an FCODE image's version.
2271 * @ha: HA context
2272 * @pcids: Pointer to the FCODE PCI data structure
2273 *
2274 * The process of retrieving the FCODE version information is at best
2275 * described as interesting.
2276 *
2277 * Within the first 100h bytes of the image an ASCII string is present
2278 * which contains several pieces of information including the FCODE
2279 * version. Unfortunately it seems the only reliable way to retrieve
2280 * the version is by scanning for another sentinel within the string,
2281 * the FCODE build date:
2282 *
2283 * ... 2.00.02 10/17/02 ...
2284 *
2285 * Returns QLA_SUCCESS on successful retrieval of version.
2286 */
2287static void
7b867cf7 2288qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids)
30c47662
AV		 2289{
2290 int ret = QLA_FUNCTION_FAILED;
2291 uint32_t istart, iend, iter, vend;
2292 uint8_t do_next, rbyte, *vbyte;
2293
2294 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2295
2296 /* Skip the PCI data structure. */
2297 istart = pcids +
2298 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
2299 qla2x00_read_flash_byte(ha, pcids + 0x0A));
2300 iend = istart + 0x100;
2301 do {
2302 /* Scan for the sentinel date string...eeewww. */
2303 do_next = 0;
2304 iter = istart;
2305 while ((iter < iend) && !do_next) {
2306 iter++;
2307 if (qla2x00_read_flash_byte(ha, iter) == '/') {
2308 if (qla2x00_read_flash_byte(ha, iter + 2) ==
2309 '/')
2310 do_next++;
2311 else if (qla2x00_read_flash_byte(ha,
2312 iter + 3) == '/')
2313 do_next++;
2314 }
2315 }
2316 if (!do_next)
2317 break;
2318
2319 /* Backtrack to previous ' ' (space). */
2320 do_next = 0;
2321 while ((iter > istart) && !do_next) {
2322 iter--;
2323 if (qla2x00_read_flash_byte(ha, iter) == ' ')
2324 do_next++;
2325 }
2326 if (!do_next)
2327 break;
2328
2329 /*
2330 * Mark end of version tag, and find previous ' ' (space) or
2331 * string length (recent FCODE images -- major hack ahead!!!).
2332 */
2333 vend = iter - 1;
2334 do_next = 0;
2335 while ((iter > istart) && !do_next) {
2336 iter--;
2337 rbyte = qla2x00_read_flash_byte(ha, iter);
2338 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
2339 do_next++;
2340 }
2341 if (!do_next)
2342 break;
2343
2344 /* Mark beginning of version tag, and copy data. */
2345 iter++;
2346 if ((vend - iter) &&
2347 ((vend - iter) < sizeof(ha->fcode_revision))) {
2348 vbyte = ha->fcode_revision;
2349 while (iter <= vend) {
2350 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
2351 iter++;
2352 }
2353 ret = QLA_SUCCESS;
2354 }
2355 } while (0);
2356
2357 if (ret != QLA_SUCCESS)
2358 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2359}
2360
2361int
7b867cf7 2362qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
30c47662
AV		 2363{
2364 int ret = QLA_SUCCESS;
2365 uint8_t code_type, last_image;
2366 uint32_t pcihdr, pcids;
2367 uint8_t *dbyte;
2368 uint16_t *dcode;
7b867cf7 2369 struct qla_hw_data *ha = vha->hw;
30c47662
AV		 2370
2371 if (!ha->pio_address || !mbuf)
2372 return QLA_FUNCTION_FAILED;
2373
2374 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2375 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2376 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2377 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2378
2379 qla2x00_flash_enable(ha);
2380
2381 /* Begin with first PCI expansion ROM header. */
2382 pcihdr = 0;
2383 last_image = 1;
2384 do {
2385 /* Verify PCI expansion ROM header. */
2386 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
2387 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2388 /* No signature */
7b867cf7
AC		 2389 DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM "
2390 "signature.\n"));
30c47662
AV		 2391 ret = QLA_FUNCTION_FAILED;
2392 break;
2393 }
2394
2395 /* Locate PCI data structure. */
2396 pcids = pcihdr +
2397 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2398 qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2399
2400 /* Validate signature of PCI data structure. */
2401 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2402 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2403 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2404 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2405 /* Incorrect header. */
7b867cf7
AC		 2406 DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not "
2407 "found pcir_adr=%x.\n", pcids));
30c47662
AV		 2408 ret = QLA_FUNCTION_FAILED;
2409 break;
2410 }
2411
2412 /* Read version */
2413 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2414 switch (code_type) {
2415 case ROM_CODE_TYPE_BIOS:
2416 /* Intel x86, PC-AT compatible. */
2417 ha->bios_revision[0] =
2418 qla2x00_read_flash_byte(ha, pcids + 0x12);
2419 ha->bios_revision[1] =
2420 qla2x00_read_flash_byte(ha, pcids + 0x13);
7b867cf7 2421 DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n",
30c47662
AV		 2422 ha->bios_revision[1], ha->bios_revision[0]));
2423 break;
2424 case ROM_CODE_TYPE_FCODE:
2425 /* Open Firmware standard for PCI (FCode). */
2426 /* Eeeewww... */
2427 qla2x00_get_fcode_version(ha, pcids);
2428 break;
2429 case ROM_CODE_TYPE_EFI:
2430 /* Extensible Firmware Interface (EFI). */
2431 ha->efi_revision[0] =
2432 qla2x00_read_flash_byte(ha, pcids + 0x12);
2433 ha->efi_revision[1] =
2434 qla2x00_read_flash_byte(ha, pcids + 0x13);
7b867cf7 2435 DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n",
30c47662
AV		 2436 ha->efi_revision[1], ha->efi_revision[0]));
2437 break;
2438 default:
7b867cf7
AC		 2439 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code "
2440 "type %x at pcids %x.\n", code_type, pcids));
30c47662
AV		 2441 break;
2442 }
2443
2444 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2445
2446 /* Locate next PCI expansion ROM. */
2447 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2448 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2449 } while (!last_image);
2450
2451 if (IS_QLA2322(ha)) {
2452 /* Read firmware image information. */
2453 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2454 dbyte = mbuf;
2455 memset(dbyte, 0, 8);
2456 dcode = (uint16_t *)dbyte;
2457
c00d8994 2458 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10,
30c47662 2459 8);
7b867cf7
AC		 2460 DEBUG3(qla_printk(KERN_DEBUG, ha, "dumping fw ver from "
2461 "flash:\n"));
30c47662
AV		 2462 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte, 8));
2463
2464 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2465 dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2466 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2467 dcode[3] == 0)) {
7b867cf7
AC		 2468 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw "
2469 "revision at %x.\n", ha->flt_region_fw * 4));
30c47662
AV		 2470 } else {
2471 /* values are in big endian */
2472 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2473 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2474 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
2475 }
2476 }
2477
2478 qla2x00_flash_disable(ha);
2479
2480 return ret;
2481}
2482
2483int
7b867cf7 2484qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
30c47662
AV		 2485{
2486 int ret = QLA_SUCCESS;
2487 uint32_t pcihdr, pcids;
2488 uint32_t *dcode;
2489 uint8_t *bcode;
2490 uint8_t code_type, last_image;
2491 int i;
7b867cf7 2492 struct qla_hw_data *ha = vha->hw;
30c47662
AV		 2493
2494 if (!mbuf)
2495 return QLA_FUNCTION_FAILED;
2496
2497 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2498 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2499 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2500 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2501
2502 dcode = mbuf;
2503
2504 /* Begin with first PCI expansion ROM header. */
c00d8994 2505 pcihdr = ha->flt_region_boot;
30c47662
AV		 2506 last_image = 1;
2507 do {
2508 /* Verify PCI expansion ROM header. */
7b867cf7 2509 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
30c47662
AV		 2510 bcode = mbuf + (pcihdr % 4);
2511 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2512 /* No signature */
7b867cf7
AC		 2513 DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM "
2514 "signature.\n"));
30c47662
AV		 2515 ret = QLA_FUNCTION_FAILED;
2516 break;
2517 }
2518
2519 /* Locate PCI data structure. */
2520 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2521
7b867cf7 2522 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
30c47662
AV		 2523 bcode = mbuf + (pcihdr % 4);
2524
2525 /* Validate signature of PCI data structure. */
2526 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2527 bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2528 /* Incorrect header. */
7b867cf7
AC		 2529 DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not "
2530 "found pcir_adr=%x.\n", pcids));
30c47662
AV		 2531 ret = QLA_FUNCTION_FAILED;
2532 break;
2533 }
2534
2535 /* Read version */
2536 code_type = bcode[0x14];
2537 switch (code_type) {
2538 case ROM_CODE_TYPE_BIOS:
2539 /* Intel x86, PC-AT compatible. */
2540 ha->bios_revision[0] = bcode[0x12];
2541 ha->bios_revision[1] = bcode[0x13];
7b867cf7 2542 DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n",
30c47662
AV		 2543 ha->bios_revision[1], ha->bios_revision[0]));
2544 break;
2545 case ROM_CODE_TYPE_FCODE:
2546 /* Open Firmware standard for PCI (FCode). */
2547 ha->fcode_revision[0] = bcode[0x12];
2548 ha->fcode_revision[1] = bcode[0x13];
7b867cf7 2549 DEBUG3(qla_printk(KERN_DEBUG, ha, "read FCODE %d.%d.\n",
30c47662
AV		 2550 ha->fcode_revision[1], ha->fcode_revision[0]));
2551 break;
2552 case ROM_CODE_TYPE_EFI:
2553 /* Extensible Firmware Interface (EFI). */
2554 ha->efi_revision[0] = bcode[0x12];
2555 ha->efi_revision[1] = bcode[0x13];
7b867cf7 2556 DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n",
30c47662
AV		 2557 ha->efi_revision[1], ha->efi_revision[0]));
2558 break;
2559 default:
7b867cf7
AC		 2560 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code "
2561 "type %x at pcids %x.\n", code_type, pcids));
30c47662
AV		 2562 break;
2563 }
2564
2565 last_image = bcode[0x15] & BIT_7;
2566
2567 /* Locate next PCI expansion ROM. */
2568 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2569 } while (!last_image);
2570
2571 /* Read firmware image information. */
2572 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2573 dcode = mbuf;
2574
7b867cf7 2575 qla24xx_read_flash_data(vha, dcode, ha->flt_region_fw + 4, 4);
30c47662
AV		 2576 for (i = 0; i < 4; i++)
2577 dcode[i] = be32_to_cpu(dcode[i]);
2578
2579 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
2580 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
2581 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2582 dcode[3] == 0)) {
7b867cf7
AC		 2583 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw "
2584 "revision at %x.\n", ha->flt_region_fw * 4));
30c47662
AV		 2585 } else {
2586 ha->fw_revision[0] = dcode[0];
2587 ha->fw_revision[1] = dcode[1];
2588 ha->fw_revision[2] = dcode[2];
2589 ha->fw_revision[3] = dcode[3];
2590 }
2591
2592 return ret;
2593}
cb8dacbf 2594
1ee27146
JC		 2595static int
2596qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end)
2597{
2598 if (pos >= end || *pos != 0x82)
2599 return 0;
2600
2601 pos += 3 + pos[1];
2602 if (pos >= end || *pos != 0x90)
2603 return 0;
2604
2605 pos += 3 + pos[1];
2606 if (pos >= end || *pos != 0x78)
2607 return 0;
2608
2609 return 1;
2610}
2611
2612int
7b867cf7 2613qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size)
1ee27146 2614{
7b867cf7 2615 struct qla_hw_data *ha = vha->hw;
1ee27146
JC		 2616 uint8_t *pos = ha->vpd;
2617 uint8_t *end = pos + ha->vpd_size;
2618 int len = 0;
2619
2620 if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end))
2621 return 0;
2622
2623 while (pos < end && *pos != 0x78) {
2624 len = (*pos == 0x82) ? pos[1] : pos[2];
2625
2626 if (!strncmp(pos, key, strlen(key)))
2627 break;
2628
2629 if (*pos != 0x90 && *pos != 0x91)
2630 pos += len;
2631
2632 pos += 3;
2633 }
2634
2635 if (pos < end - len && *pos != 0x78)
2636 return snprintf(str, size, "%.*s", len, pos + 3);
2637
2638 return 0;
2639}
Linux kernel - Deliverables
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