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[SCSI] cxgb3i: add missing include
[deliverable/linux.git] / drivers / scsi / qla2xxx / qla_sup.c
CommitLineData
fa90c54f
AV		 1/*
2 * QLogic Fibre Channel HBA Driver
01e58d8e 3 * Copyright (c) 2003-2008 QLogic Corporation
1da177e4 4 *
fa90c54f
AV		 5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
1da177e4
LT		 7#include "qla_def.h"
8
9#include <linux/delay.h>
2c96d8d0 10#include <linux/vmalloc.h>
1da177e4
LT		 11#include <asm/uaccess.h>
12
1da177e4
LT		 13/*
14 * NVRAM support routines
15 */
16
17/**
fa2a1ce5 18 * qla2x00_lock_nvram_access() -
1da177e4
LT		 19 * @ha: HA context
20 */
a824ebb3 21static void
7b867cf7 22qla2x00_lock_nvram_access(struct qla_hw_data *ha)
1da177e4
LT		 23{
24 uint16_t data;
3d71644c 25 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 26
27 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
28 data = RD_REG_WORD(&reg->nvram);
29 while (data & NVR_BUSY) {
30 udelay(100);
31 data = RD_REG_WORD(&reg->nvram);
32 }
33
34 /* Lock resource */
35 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
36 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
37 udelay(5);
38 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
39 while ((data & BIT_0) == 0) {
40 /* Lock failed */
41 udelay(100);
42 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
43 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
44 udelay(5);
45 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
46 }
47 }
48}
49
50/**
fa2a1ce5 51 * qla2x00_unlock_nvram_access() -
1da177e4
LT		 52 * @ha: HA context
53 */
a824ebb3 54static void
7b867cf7 55qla2x00_unlock_nvram_access(struct qla_hw_data *ha)
1da177e4 56{
3d71644c 57 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 58
59 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
60 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
61 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
62 }
63}
64
7b867cf7
AC		 65/**
66 * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
67 * @ha: HA context
68 * @data: Serial interface selector
69 */
70static void
71qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data)
72{
73 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
74
75 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
76 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
77 NVRAM_DELAY();
78 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_CLOCK |
79 NVR_WRT_ENABLE);
80 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
81 NVRAM_DELAY();
82 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
83 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
84 NVRAM_DELAY();
85}
86
87/**
88 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
89 * NVRAM.
90 * @ha: HA context
91 * @nv_cmd: NVRAM command
92 *
93 * Bit definitions for NVRAM command:
94 *
95 * Bit 26 = start bit
96 * Bit 25, 24 = opcode
97 * Bit 23-16 = address
98 * Bit 15-0 = write data
99 *
100 * Returns the word read from nvram @addr.
101 */
102static uint16_t
103qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd)
104{
105 uint8_t cnt;
106 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
107 uint16_t data = 0;
108 uint16_t reg_data;
109
110 /* Send command to NVRAM. */
111 nv_cmd <<= 5;
112 for (cnt = 0; cnt < 11; cnt++) {
113 if (nv_cmd & BIT_31)
114 qla2x00_nv_write(ha, NVR_DATA_OUT);
115 else
116 qla2x00_nv_write(ha, 0);
117 nv_cmd <<= 1;
118 }
119
120 /* Read data from NVRAM. */
121 for (cnt = 0; cnt < 16; cnt++) {
122 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
123 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
124 NVRAM_DELAY();
125 data <<= 1;
126 reg_data = RD_REG_WORD(&reg->nvram);
127 if (reg_data & NVR_DATA_IN)
128 data |= BIT_0;
129 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
130 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
131 NVRAM_DELAY();
132 }
133
134 /* Deselect chip. */
135 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
136 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
137 NVRAM_DELAY();
138
139 return data;
140}
141
142
1da177e4
LT		 143/**
144 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
145 * request routine to get the word from NVRAM.
146 * @ha: HA context
147 * @addr: Address in NVRAM to read
148 *
149 * Returns the word read from nvram @addr.
150 */
a824ebb3 151static uint16_t
7b867cf7 152qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr)
1da177e4
LT		 153{
154 uint16_t data;
155 uint32_t nv_cmd;
156
157 nv_cmd = addr << 16;
158 nv_cmd |= NV_READ_OP;
159 data = qla2x00_nvram_request(ha, nv_cmd);
160
161 return (data);
162}
163
7b867cf7
AC		 164/**
165 * qla2x00_nv_deselect() - Deselect NVRAM operations.
166 * @ha: HA context
167 */
168static void
169qla2x00_nv_deselect(struct qla_hw_data *ha)
170{
171 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
172
173 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
174 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
175 NVRAM_DELAY();
176}
177
1da177e4
LT		 178/**
179 * qla2x00_write_nvram_word() - Write NVRAM data.
180 * @ha: HA context
181 * @addr: Address in NVRAM to write
182 * @data: word to program
183 */
a824ebb3 184static void
7b867cf7 185qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data)
1da177e4
LT		 186{
187 int count;
188 uint16_t word;
45aeaf1e 189 uint32_t nv_cmd, wait_cnt;
3d71644c 190 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 191
192 qla2x00_nv_write(ha, NVR_DATA_OUT);
193 qla2x00_nv_write(ha, 0);
194 qla2x00_nv_write(ha, 0);
195
196 for (word = 0; word < 8; word++)
197 qla2x00_nv_write(ha, NVR_DATA_OUT);
198
199 qla2x00_nv_deselect(ha);
200
201 /* Write data */
202 nv_cmd = (addr << 16) | NV_WRITE_OP;
203 nv_cmd |= data;
204 nv_cmd <<= 5;
205 for (count = 0; count < 27; count++) {
206 if (nv_cmd & BIT_31)
207 qla2x00_nv_write(ha, NVR_DATA_OUT);
208 else
209 qla2x00_nv_write(ha, 0);
210
211 nv_cmd <<= 1;
212 }
213
214 qla2x00_nv_deselect(ha);
215
216 /* Wait for NVRAM to become ready */
217 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 218 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
45aeaf1e 219 wait_cnt = NVR_WAIT_CNT;
1da177e4 220 do {
45aeaf1e
RA		 221 if (!--wait_cnt) {
222 DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
7b867cf7 223 __func__, vha->host_no));
45aeaf1e
RA		 224 break;
225 }
1da177e4
LT		 226 NVRAM_DELAY();
227 word = RD_REG_WORD(&reg->nvram);
228 } while ((word & NVR_DATA_IN) == 0);
229
230 qla2x00_nv_deselect(ha);
231
232 /* Disable writes */
233 qla2x00_nv_write(ha, NVR_DATA_OUT);
234 for (count = 0; count < 10; count++)
235 qla2x00_nv_write(ha, 0);
236
237 qla2x00_nv_deselect(ha);
238}
239
459c5378 240static int
7b867cf7
AC		 241qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr,
242 uint16_t data, uint32_t tmo)
459c5378
AV		 243{
244 int ret, count;
245 uint16_t word;
246 uint32_t nv_cmd;
247 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
248
249 ret = QLA_SUCCESS;
250
251 qla2x00_nv_write(ha, NVR_DATA_OUT);
252 qla2x00_nv_write(ha, 0);
253 qla2x00_nv_write(ha, 0);
254
255 for (word = 0; word < 8; word++)
256 qla2x00_nv_write(ha, NVR_DATA_OUT);
257
258 qla2x00_nv_deselect(ha);
259
260 /* Write data */
261 nv_cmd = (addr << 16) | NV_WRITE_OP;
262 nv_cmd |= data;
263 nv_cmd <<= 5;
264 for (count = 0; count < 27; count++) {
265 if (nv_cmd & BIT_31)
266 qla2x00_nv_write(ha, NVR_DATA_OUT);
267 else
268 qla2x00_nv_write(ha, 0);
269
270 nv_cmd <<= 1;
271 }
272
273 qla2x00_nv_deselect(ha);
274
275 /* Wait for NVRAM to become ready */
276 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 277 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
459c5378
AV		 278 do {
279 NVRAM_DELAY();
280 word = RD_REG_WORD(&reg->nvram);
281 if (!--tmo) {
282 ret = QLA_FUNCTION_FAILED;
283 break;
284 }
285 } while ((word & NVR_DATA_IN) == 0);
286
287 qla2x00_nv_deselect(ha);
288
289 /* Disable writes */
290 qla2x00_nv_write(ha, NVR_DATA_OUT);
291 for (count = 0; count < 10; count++)
292 qla2x00_nv_write(ha, 0);
293
294 qla2x00_nv_deselect(ha);
295
296 return ret;
297}
298
459c5378
AV		 299/**
300 * qla2x00_clear_nvram_protection() -
301 * @ha: HA context
302 */
303static int
7b867cf7 304qla2x00_clear_nvram_protection(struct qla_hw_data *ha)
459c5378
AV		 305{
306 int ret, stat;
307 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
45aeaf1e 308 uint32_t word, wait_cnt;
459c5378
AV		 309 uint16_t wprot, wprot_old;
310
311 /* Clear NVRAM write protection. */
312 ret = QLA_FUNCTION_FAILED;
45aeaf1e
RA		 313
314 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
315 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
459c5378 316 __constant_cpu_to_le16(0x1234), 100000);
45aeaf1e
RA		 317 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
318 if (stat != QLA_SUCCESS || wprot != 0x1234) {
459c5378
AV		 319 /* Write enable. */
320 qla2x00_nv_write(ha, NVR_DATA_OUT);
321 qla2x00_nv_write(ha, 0);
322 qla2x00_nv_write(ha, 0);
323 for (word = 0; word < 8; word++)
324 qla2x00_nv_write(ha, NVR_DATA_OUT);
325
326 qla2x00_nv_deselect(ha);
327
328 /* Enable protection register. */
329 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
330 qla2x00_nv_write(ha, NVR_PR_ENABLE);
331 qla2x00_nv_write(ha, NVR_PR_ENABLE);
332 for (word = 0; word < 8; word++)
333 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
334
335 qla2x00_nv_deselect(ha);
336
337 /* Clear protection register (ffff is cleared). */
338 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
339 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
340 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
341 for (word = 0; word < 8; word++)
342 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
343
344 qla2x00_nv_deselect(ha);
345
346 /* Wait for NVRAM to become ready. */
347 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 348 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
45aeaf1e 349 wait_cnt = NVR_WAIT_CNT;
459c5378 350 do {
45aeaf1e 351 if (!--wait_cnt) {
7b867cf7
AC		 352 DEBUG9_10(qla_printk(
353 "NVRAM didn't go ready...\n"));
45aeaf1e
RA		 354 break;
355 }
459c5378
AV		 356 NVRAM_DELAY();
357 word = RD_REG_WORD(&reg->nvram);
358 } while ((word & NVR_DATA_IN) == 0);
359
45aeaf1e
RA		 360 if (wait_cnt)
361 ret = QLA_SUCCESS;
459c5378 362 } else
45aeaf1e 363 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
459c5378
AV		 364
365 return ret;
366}
367
368static void
7b867cf7 369qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat)
459c5378
AV		 370{
371 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
45aeaf1e 372 uint32_t word, wait_cnt;
459c5378
AV		 373
374 if (stat != QLA_SUCCESS)
375 return;
376
377 /* Set NVRAM write protection. */
378 /* Write enable. */
379 qla2x00_nv_write(ha, NVR_DATA_OUT);
380 qla2x00_nv_write(ha, 0);
381 qla2x00_nv_write(ha, 0);
382 for (word = 0; word < 8; word++)
383 qla2x00_nv_write(ha, NVR_DATA_OUT);
384
385 qla2x00_nv_deselect(ha);
386
387 /* Enable protection register. */
388 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
389 qla2x00_nv_write(ha, NVR_PR_ENABLE);
390 qla2x00_nv_write(ha, NVR_PR_ENABLE);
391 for (word = 0; word < 8; word++)
392 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
393
394 qla2x00_nv_deselect(ha);
395
396 /* Enable protection register. */
397 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
398 qla2x00_nv_write(ha, NVR_PR_ENABLE);
399 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
400 for (word = 0; word < 8; word++)
401 qla2x00_nv_write(ha, NVR_PR_ENABLE);
402
403 qla2x00_nv_deselect(ha);
404
405 /* Wait for NVRAM to become ready. */
406 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 407 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
45aeaf1e 408 wait_cnt = NVR_WAIT_CNT;
459c5378 409 do {
45aeaf1e 410 if (!--wait_cnt) {
7b867cf7 411 DEBUG9_10(qla_printk("NVRAM didn't go ready...\n"));
45aeaf1e
RA		 412 break;
413 }
459c5378
AV		 414 NVRAM_DELAY();
415 word = RD_REG_WORD(&reg->nvram);
416 } while ((word & NVR_DATA_IN) == 0);
417}
418
419
420/*****************************************************************************/
421/* Flash Manipulation Routines */
422/*****************************************************************************/
423
338c9161
AV		 424#define OPTROM_BURST_SIZE 0x1000
425#define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
426
459c5378
AV		 427static inline uint32_t
428flash_conf_to_access_addr(uint32_t faddr)
429{
430 return FARX_ACCESS_FLASH_CONF | faddr;
431}
432
433static inline uint32_t
434flash_data_to_access_addr(uint32_t faddr)
435{
436 return FARX_ACCESS_FLASH_DATA | faddr;
437}
438
439static inline uint32_t
440nvram_conf_to_access_addr(uint32_t naddr)
441{
442 return FARX_ACCESS_NVRAM_CONF | naddr;
443}
444
445static inline uint32_t
446nvram_data_to_access_addr(uint32_t naddr)
447{
448 return FARX_ACCESS_NVRAM_DATA | naddr;
449}
450
e5f82ab8 451static uint32_t
7b867cf7 452qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr)
459c5378
AV		 453{
454 int rval;
455 uint32_t cnt, data;
456 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
457
458 WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
459 /* Wait for READ cycle to complete. */
460 rval = QLA_SUCCESS;
461 for (cnt = 3000;
462 (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
463 rval == QLA_SUCCESS; cnt--) {
464 if (cnt)
465 udelay(10);
466 else
467 rval = QLA_FUNCTION_TIMEOUT;
40a2e34a 468 cond_resched();
459c5378
AV		 469 }
470
471 /* TODO: What happens if we time out? */
472 data = 0xDEADDEAD;
473 if (rval == QLA_SUCCESS)
474 data = RD_REG_DWORD(&reg->flash_data);
475
476 return data;
477}
478
479uint32_t *
7b867cf7 480qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
459c5378
AV		 481 uint32_t dwords)
482{
483 uint32_t i;
459c5378
AV		 484 /* Dword reads to flash. */
485 for (i = 0; i < dwords; i++, faddr++)
7b867cf7 486 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(vha->hw,
459c5378
AV		 487 flash_data_to_access_addr(faddr)));
488
459c5378
AV		 489 return dwptr;
490}
491
e5f82ab8 492static int
7b867cf7 493qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data)
459c5378
AV		 494{
495 int rval;
496 uint32_t cnt;
497 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
498
499 WRT_REG_DWORD(&reg->flash_data, data);
500 RD_REG_DWORD(&reg->flash_data); /* PCI Posting. */
501 WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
502 /* Wait for Write cycle to complete. */
503 rval = QLA_SUCCESS;
504 for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
505 rval == QLA_SUCCESS; cnt--) {
506 if (cnt)
507 udelay(10);
508 else
509 rval = QLA_FUNCTION_TIMEOUT;
40a2e34a 510 cond_resched();
459c5378
AV		 511 }
512 return rval;
513}
514
e5f82ab8 515static void
7b867cf7 516qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
459c5378
AV		 517 uint8_t *flash_id)
518{
519 uint32_t ids;
520
521 ids = qla24xx_read_flash_dword(ha, flash_data_to_access_addr(0xd03ab));
522 *man_id = LSB(ids);
523 *flash_id = MSB(ids);
45aeaf1e
RA		 524
525 /* Check if man_id and flash_id are valid. */
526 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
527 /* Read information using 0x9f opcode
528 * Device ID, Mfg ID would be read in the format:
529 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
530 * Example: ATMEL 0x00 01 45 1F
531 * Extract MFG and Dev ID from last two bytes.
532 */
533 ids = qla24xx_read_flash_dword(ha,
534 flash_data_to_access_addr(0xd009f));
535 *man_id = LSB(ids);
536 *flash_id = MSB(ids);
537 }
459c5378
AV		 538}
539
c00d8994 540static int
7b867cf7 541qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
c00d8994
AV		 542{
543 const char *loc, *locations[] = { "DEF", "PCI" };
544 uint32_t pcihdr, pcids;
545 uint32_t *dcode;
546 uint8_t *buf, *bcode, last_image;
547 uint16_t cnt, chksum, *wptr;
548 struct qla_flt_location *fltl;
7b867cf7 549 struct qla_hw_data *ha = vha->hw;
73208dfd 550 struct req_que *req = ha->req_q_map[0];
c00d8994
AV		 551
552 /*
553 * FLT-location structure resides after the last PCI region.
554 */
555
556 /* Begin with sane defaults. */
557 loc = locations[0];
558 *start = IS_QLA24XX_TYPE(ha) ? FA_FLASH_LAYOUT_ADDR_24:
559 FA_FLASH_LAYOUT_ADDR;
560
561 /* Begin with first PCI expansion ROM header. */
7b867cf7
AC		 562 buf = (uint8_t *)req->ring;
563 dcode = (uint32_t *)req->ring;
c00d8994
AV		 564 pcihdr = 0;
565 last_image = 1;
566 do {
567 /* Verify PCI expansion ROM header. */
7b867cf7 568 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
c00d8994
AV		 569 bcode = buf + (pcihdr % 4);
570 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa)
571 goto end;
572
573 /* Locate PCI data structure. */
574 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
7b867cf7 575 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
c00d8994
AV		 576 bcode = buf + (pcihdr % 4);
577
578 /* Validate signature of PCI data structure. */
579 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
580 bcode[0x2] != 'I' || bcode[0x3] != 'R')
581 goto end;
582
583 last_image = bcode[0x15] & BIT_7;
584
585 /* Locate next PCI expansion ROM. */
586 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
587 } while (!last_image);
588
589 /* Now verify FLT-location structure. */
7b867cf7
AC		 590 fltl = (struct qla_flt_location *)req->ring;
591 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2,
c00d8994
AV		 592 sizeof(struct qla_flt_location) >> 2);
593 if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' ||
594 fltl->sig[2] != 'L' || fltl->sig[3] != 'T')
595 goto end;
596
7b867cf7 597 wptr = (uint16_t *)req->ring;
c00d8994
AV		 598 cnt = sizeof(struct qla_flt_location) >> 1;
599 for (chksum = 0; cnt; cnt--)
600 chksum += le16_to_cpu(*wptr++);
601 if (chksum) {
602 qla_printk(KERN_ERR, ha,
603 "Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
604 qla2x00_dump_buffer(buf, sizeof(struct qla_flt_location));
605 return QLA_FUNCTION_FAILED;
606 }
607
608 /* Good data. Use specified location. */
609 loc = locations[1];
610 *start = le16_to_cpu(fltl->start_hi) << 16 |
611 le16_to_cpu(fltl->start_lo);
612end:
613 DEBUG2(qla_printk(KERN_DEBUG, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
614 return QLA_SUCCESS;
615}
616
617static void
7b867cf7 618qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
c00d8994
AV		 619{
620 const char *loc, *locations[] = { "DEF", "FLT" };
621 uint16_t *wptr;
622 uint16_t cnt, chksum;
623 uint32_t start;
624 struct qla_flt_header *flt;
625 struct qla_flt_region *region;
7b867cf7 626 struct qla_hw_data *ha = vha->hw;
73208dfd 627 struct req_que *req = ha->req_q_map[0];
c00d8994
AV		 628
629 ha->flt_region_flt = flt_addr;
7b867cf7
AC		 630 wptr = (uint16_t *)req->ring;
631 flt = (struct qla_flt_header *)req->ring;
c00d8994 632 region = (struct qla_flt_region *)&flt[1];
7b867cf7 633 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
c00d8994
AV		 634 flt_addr << 2, OPTROM_BURST_SIZE);
635 if (*wptr == __constant_cpu_to_le16(0xffff))
636 goto no_flash_data;
637 if (flt->version != __constant_cpu_to_le16(1)) {
638 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported FLT detected: "
639 "version=0x%x length=0x%x checksum=0x%x.\n",
640 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
641 le16_to_cpu(flt->checksum)));
642 goto no_flash_data;
643 }
644
645 cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
646 for (chksum = 0; cnt; cnt--)
647 chksum += le16_to_cpu(*wptr++);
648 if (chksum) {
649 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
650 "version=0x%x length=0x%x checksum=0x%x.\n",
651 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
652 chksum));
653 goto no_flash_data;
654 }
655
656 loc = locations[1];
657 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
658 for ( ; cnt; cnt--, region++) {
659 /* Store addresses as DWORD offsets. */
660 start = le32_to_cpu(region->start) >> 2;
661
662 DEBUG3(qla_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
663 "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
664 le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
665
666 switch (le32_to_cpu(region->code)) {
667 case FLT_REG_FW:
668 ha->flt_region_fw = start;
669 break;
670 case FLT_REG_BOOT_CODE:
671 ha->flt_region_boot = start;
672 break;
673 case FLT_REG_VPD_0:
674 ha->flt_region_vpd_nvram = start;
675 break;
676 case FLT_REG_FDT:
677 ha->flt_region_fdt = start;
678 break;
679 case FLT_REG_HW_EVENT_0:
680 if (!PCI_FUNC(ha->pdev->devfn))
681 ha->flt_region_hw_event = start;
682 break;
683 case FLT_REG_HW_EVENT_1:
684 if (PCI_FUNC(ha->pdev->devfn))
685 ha->flt_region_hw_event = start;
686 break;
272976ca
AV		 687 case FLT_REG_NPIV_CONF_0:
688 if (!PCI_FUNC(ha->pdev->devfn))
689 ha->flt_region_npiv_conf = start;
690 break;
691 case FLT_REG_NPIV_CONF_1:
692 if (PCI_FUNC(ha->pdev->devfn))
693 ha->flt_region_npiv_conf = start;
694 break;
c00d8994
AV		 695 }
696 }
697 goto done;
698
699no_flash_data:
700 /* Use hardcoded defaults. */
701 loc = locations[0];
702 ha->flt_region_fw = FA_RISC_CODE_ADDR;
703 ha->flt_region_boot = FA_BOOT_CODE_ADDR;
704 ha->flt_region_vpd_nvram = FA_VPD_NVRAM_ADDR;
705 ha->flt_region_fdt = IS_QLA24XX_TYPE(ha) ? FA_FLASH_DESCR_ADDR_24:
706 FA_FLASH_DESCR_ADDR;
707 ha->flt_region_hw_event = !PCI_FUNC(ha->pdev->devfn) ?
708 FA_HW_EVENT0_ADDR: FA_HW_EVENT1_ADDR;
272976ca
AV		 709 ha->flt_region_npiv_conf = !PCI_FUNC(ha->pdev->devfn) ?
710 (IS_QLA24XX_TYPE(ha) ? FA_NPIV_CONF0_ADDR_24: FA_NPIV_CONF0_ADDR):
711 (IS_QLA24XX_TYPE(ha) ? FA_NPIV_CONF1_ADDR_24: FA_NPIV_CONF1_ADDR);
c00d8994
AV		 712done:
713 DEBUG2(qla_printk(KERN_DEBUG, ha, "FLT[%s]: boot=0x%x fw=0x%x "
272976ca 714 "vpd_nvram=0x%x fdt=0x%x flt=0x%x hwe=0x%x npiv=0x%x.\n", loc,
c00d8994 715 ha->flt_region_boot, ha->flt_region_fw, ha->flt_region_vpd_nvram,
272976ca
AV		 716 ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_hw_event,
717 ha->flt_region_npiv_conf));
c00d8994
AV		 718}
719
720static void
7b867cf7 721qla2xxx_get_fdt_info(scsi_qla_host_t *vha)
7d232c74 722{
821b3996 723#define FLASH_BLK_SIZE_4K 0x1000
7d232c74
AV		 724#define FLASH_BLK_SIZE_32K 0x8000
725#define FLASH_BLK_SIZE_64K 0x10000
c00d8994 726 const char *loc, *locations[] = { "MID", "FDT" };
7d232c74
AV		 727 uint16_t cnt, chksum;
728 uint16_t *wptr;
729 struct qla_fdt_layout *fdt;
730 uint8_t man_id, flash_id;
c00d8994 731 uint16_t mid, fid;
7b867cf7 732 struct qla_hw_data *ha = vha->hw;
73208dfd 733 struct req_que *req = ha->req_q_map[0];
7d232c74 734
7b867cf7
AC		 735 wptr = (uint16_t *)req->ring;
736 fdt = (struct qla_fdt_layout *)req->ring;
737 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
c00d8994 738 ha->flt_region_fdt << 2, OPTROM_BURST_SIZE);
7d232c74
AV		 739 if (*wptr == __constant_cpu_to_le16(0xffff))
740 goto no_flash_data;
741 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
742 fdt->sig[3] != 'D')
743 goto no_flash_data;
744
745 for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
746 cnt++)
747 chksum += le16_to_cpu(*wptr++);
748 if (chksum) {
749 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
750 "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
751 le16_to_cpu(fdt->version)));
752 DEBUG9(qla2x00_dump_buffer((uint8_t *)fdt, sizeof(*fdt)));
753 goto no_flash_data;
754 }
755
c00d8994
AV		 756 loc = locations[1];
757 mid = le16_to_cpu(fdt->man_id);
758 fid = le16_to_cpu(fdt->id);
7d232c74
AV		 759 ha->fdt_wrt_disable = fdt->wrt_disable_bits;
760 ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0300 | fdt->erase_cmd);
761 ha->fdt_block_size = le32_to_cpu(fdt->block_size);
762 if (fdt->unprotect_sec_cmd) {
763 ha->fdt_unprotect_sec_cmd = flash_conf_to_access_addr(0x0300 |
764 fdt->unprotect_sec_cmd);
765 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
766 flash_conf_to_access_addr(0x0300 | fdt->protect_sec_cmd):
767 flash_conf_to_access_addr(0x0336);
768 }
c00d8994 769 goto done;
7d232c74 770no_flash_data:
c00d8994 771 loc = locations[0];
7d232c74 772 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
c00d8994
AV		 773 mid = man_id;
774 fid = flash_id;
7d232c74
AV		 775 ha->fdt_wrt_disable = 0x9c;
776 ha->fdt_erase_cmd = flash_conf_to_access_addr(0x03d8);
777 switch (man_id) {
778 case 0xbf: /* STT flash. */
779 if (flash_id == 0x8e)
780 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
781 else
782 ha->fdt_block_size = FLASH_BLK_SIZE_32K;
783
784 if (flash_id == 0x80)
785 ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0352);
786 break;
787 case 0x13: /* ST M25P80. */
788 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
789 break;
790 case 0x1f: /* Atmel 26DF081A. */
821b3996 791 ha->fdt_block_size = FLASH_BLK_SIZE_4K;
7d232c74
AV		 792 ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0320);
793 ha->fdt_unprotect_sec_cmd = flash_conf_to_access_addr(0x0339);
794 ha->fdt_protect_sec_cmd = flash_conf_to_access_addr(0x0336);
795 break;
796 default:
797 /* Default to 64 kb sector size. */
798 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
799 break;
800 }
c00d8994
AV		 801done:
802 DEBUG2(qla_printk(KERN_DEBUG, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
821b3996 803 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
7d232c74 804 ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
821b3996 805 ha->fdt_unprotect_sec_cmd, ha->fdt_wrt_disable,
7d232c74
AV		 806 ha->fdt_block_size));
807}
808
c00d8994 809int
7b867cf7 810qla2xxx_get_flash_info(scsi_qla_host_t *vha)
c00d8994
AV		 811{
812 int ret;
813 uint32_t flt_addr;
7b867cf7 814 struct qla_hw_data *ha = vha->hw;
c00d8994
AV		 815
816 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
817 return QLA_SUCCESS;
818
7b867cf7 819 ret = qla2xxx_find_flt_start(vha, &flt_addr);
c00d8994
AV		 820 if (ret != QLA_SUCCESS)
821 return ret;
822
7b867cf7
AC		 823 qla2xxx_get_flt_info(vha, flt_addr);
824 qla2xxx_get_fdt_info(vha);
c00d8994
AV		 825
826 return QLA_SUCCESS;
827}
828
272976ca 829void
7b867cf7 830qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
272976ca
AV		 831{
832#define NPIV_CONFIG_SIZE (16*1024)
833 void *data;
834 uint16_t *wptr;
835 uint16_t cnt, chksum;
73208dfd 836 int i;
272976ca
AV		 837 struct qla_npiv_header hdr;
838 struct qla_npiv_entry *entry;
7b867cf7 839 struct qla_hw_data *ha = vha->hw;
272976ca
AV		 840
841 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
842 return;
843
7b867cf7 844 ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr,
272976ca
AV		 845 ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header));
846 if (hdr.version == __constant_cpu_to_le16(0xffff))
847 return;
848 if (hdr.version != __constant_cpu_to_le16(1)) {
849 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported NPIV-Config "
850 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
851 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
852 le16_to_cpu(hdr.checksum)));
853 return;
854 }
855
856 data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL);
857 if (!data) {
858 DEBUG2(qla_printk(KERN_INFO, ha, "NPIV-Config: Unable to "
859 "allocate memory.\n"));
860 return;
861 }
862
7b867cf7 863 ha->isp_ops->read_optrom(vha, (uint8_t *)data,
272976ca
AV		 864 ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE);
865
866 cnt = (sizeof(struct qla_npiv_header) + le16_to_cpu(hdr.entries) *
867 sizeof(struct qla_npiv_entry)) >> 1;
868 for (wptr = data, chksum = 0; cnt; cnt--)
869 chksum += le16_to_cpu(*wptr++);
870 if (chksum) {
871 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent NPIV-Config "
872 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
873 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
874 chksum));
875 goto done;
876 }
877
878 entry = data + sizeof(struct qla_npiv_header);
879 cnt = le16_to_cpu(hdr.entries);
73208dfd 880 for (i = 0; cnt; cnt--, entry++, i++) {
272976ca
AV		 881 uint16_t flags;
882 struct fc_vport_identifiers vid;
883 struct fc_vport *vport;
884
885 flags = le16_to_cpu(entry->flags);
886 if (flags == 0xffff)
887 continue;
888 if ((flags & BIT_0) == 0)
889 continue;
890
891 memset(&vid, 0, sizeof(vid));
892 vid.roles = FC_PORT_ROLE_FCP_INITIATOR;
893 vid.vport_type = FC_PORTTYPE_NPIV;
894 vid.disable = false;
895 vid.port_name = wwn_to_u64(entry->port_name);
896 vid.node_name = wwn_to_u64(entry->node_name);
897
73208dfd
AC		 898 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry));
899
272976ca 900 DEBUG2(qla_printk(KERN_DEBUG, ha, "NPIV[%02x]: wwpn=%llx "
73208dfd
AC		 901 "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt,
902 vid.port_name, vid.node_name, le16_to_cpu(entry->vf_id),
903 entry->q_qos, entry->f_qos));
904
905 if (i < QLA_PRECONFIG_VPORTS) {
906 vport = fc_vport_create(vha->host, 0, &vid);
907 if (!vport)
908 qla_printk(KERN_INFO, ha,
909 "NPIV-Config: Failed to create vport [%02x]: "
910 "wwpn=%llx wwnn=%llx.\n", cnt,
911 vid.port_name, vid.node_name);
912 }
272976ca
AV		 913 }
914done:
915 kfree(data);
73208dfd 916 ha->npiv_info = NULL;
272976ca
AV		 917}
918
cb8dacbf 919static void
7b867cf7 920qla24xx_unprotect_flash(struct qla_hw_data *ha)
cb8dacbf
AV		 921{
922 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
923
924 /* Enable flash write. */
925 WRT_REG_DWORD(&reg->ctrl_status,
926 RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
927 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
928
7d232c74
AV		 929 if (!ha->fdt_wrt_disable)
930 return;
931
cb8dacbf
AV		 932 /* Disable flash write-protection. */
933 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
934 /* Some flash parts need an additional zero-write to clear bits.*/
935 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
936}
937
938static void
7b867cf7 939qla24xx_protect_flash(struct qla_hw_data *ha)
cb8dacbf
AV		 940{
941 uint32_t cnt;
942 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
943
7d232c74
AV		 944 if (!ha->fdt_wrt_disable)
945 goto skip_wrt_protect;
946
cb8dacbf 947 /* Enable flash write-protection and wait for completion. */
7d232c74
AV		 948 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101),
949 ha->fdt_wrt_disable);
cb8dacbf
AV		 950 for (cnt = 300; cnt &&
951 qla24xx_read_flash_dword(ha,
952 flash_conf_to_access_addr(0x005)) & BIT_0;
953 cnt--) {
954 udelay(10);
955 }
956
7d232c74 957skip_wrt_protect:
cb8dacbf
AV		 958 /* Disable flash write. */
959 WRT_REG_DWORD(&reg->ctrl_status,
960 RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
961 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
962}
963
e5f82ab8 964static int
7b867cf7 965qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
459c5378
AV		 966 uint32_t dwords)
967{
968 int ret;
338c9161 969 uint32_t liter, miter;
7d232c74 970 uint32_t sec_mask, rest_addr;
cb8dacbf 971 uint32_t fdata, findex;
338c9161
AV		 972 dma_addr_t optrom_dma;
973 void *optrom = NULL;
974 uint32_t *s, *d;
7b867cf7 975 struct qla_hw_data *ha = vha->hw;
459c5378
AV		 976
977 ret = QLA_SUCCESS;
978
338c9161 979 /* Prepare burst-capable write on supported ISPs. */
b7cc176c 980 if (IS_QLA25XX(ha) && !(faddr & 0xfff) &&
338c9161
AV		 981 dwords > OPTROM_BURST_DWORDS) {
982 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
983 &optrom_dma, GFP_KERNEL);
984 if (!optrom) {
985 qla_printk(KERN_DEBUG, ha,
986 "Unable to allocate memory for optrom burst write "
987 "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
988 }
989 }
990
7d232c74
AV		 991 rest_addr = (ha->fdt_block_size >> 2) - 1;
992 sec_mask = 0x80000 - (ha->fdt_block_size >> 2);
459c5378 993
cb8dacbf 994 qla24xx_unprotect_flash(ha);
459c5378 995
338c9161 996 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
821b3996
LC		 997
998 findex = faddr;
999 fdata = (findex & sec_mask) << 2;
45aeaf1e 1000
338c9161
AV		 1001 /* Are we at the beginning of a sector? */
1002 if ((findex & rest_addr) == 0) {
7d232c74
AV		 1003 /* Do sector unprotect. */
1004 if (ha->fdt_unprotect_sec_cmd)
338c9161 1005 qla24xx_write_flash_dword(ha,
7d232c74 1006 ha->fdt_unprotect_sec_cmd,
338c9161 1007 (fdata & 0xff00) | ((fdata << 16) &
459c5378 1008 0xff0000) | ((fdata >> 16) & 0xff));
7d232c74 1009 ret = qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd,
338c9161
AV		 1010 (fdata & 0xff00) |((fdata << 16) &
1011 0xff0000) | ((fdata >> 16) & 0xff));
1012 if (ret != QLA_SUCCESS) {
7b867cf7
AC		 1013 DEBUG9(qla_printk("Unable to flash sector: "
1014 "address=%x.\n", faddr));
338c9161 1015 break;
459c5378 1016 }
338c9161
AV		 1017 }
1018
1019 /* Go with burst-write. */
94d6a2b3 1020 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
338c9161
AV		 1021 /* Copy data to DMA'ble buffer. */
1022 for (miter = 0, s = optrom, d = dwptr;
1023 miter < OPTROM_BURST_DWORDS; miter++, s++, d++)
1024 *s = cpu_to_le32(*d);
1025
7b867cf7 1026 ret = qla2x00_load_ram(vha, optrom_dma,
459c5378 1027 flash_data_to_access_addr(faddr),
338c9161 1028 OPTROM_BURST_DWORDS);
459c5378 1029 if (ret != QLA_SUCCESS) {
338c9161
AV		 1030 qla_printk(KERN_WARNING, ha,
1031 "Unable to burst-write optrom segment "
1032 "(%x/%x/%llx).\n", ret,
1033 flash_data_to_access_addr(faddr),
875baf3c 1034 (unsigned long long)optrom_dma);
338c9161
AV		 1035 qla_printk(KERN_WARNING, ha,
1036 "Reverting to slow-write.\n");
1037
1038 dma_free_coherent(&ha->pdev->dev,
1039 OPTROM_BURST_SIZE, optrom, optrom_dma);
1040 optrom = NULL;
1041 } else {
1042 liter += OPTROM_BURST_DWORDS - 1;
1043 faddr += OPTROM_BURST_DWORDS - 1;
1044 dwptr += OPTROM_BURST_DWORDS - 1;
1045 continue;
459c5378 1046 }
338c9161 1047 }
45aeaf1e 1048
338c9161
AV		 1049 ret = qla24xx_write_flash_dword(ha,
1050 flash_data_to_access_addr(faddr), cpu_to_le32(*dwptr));
1051 if (ret != QLA_SUCCESS) {
1052 DEBUG9(printk("%s(%ld) Unable to program flash "
1053 "address=%x data=%x.\n", __func__,
7b867cf7 1054 vha->host_no, faddr, *dwptr));
338c9161 1055 break;
459c5378 1056 }
338c9161 1057
7d232c74
AV		 1058 /* Do sector protect. */
1059 if (ha->fdt_unprotect_sec_cmd &&
338c9161
AV		 1060 ((faddr & rest_addr) == rest_addr))
1061 qla24xx_write_flash_dword(ha,
7d232c74 1062 ha->fdt_protect_sec_cmd,
338c9161
AV		 1063 (fdata & 0xff00) | ((fdata << 16) &
1064 0xff0000) | ((fdata >> 16) & 0xff));
1065 }
459c5378 1066
cb8dacbf 1067 qla24xx_protect_flash(ha);
459c5378 1068
338c9161
AV		 1069 if (optrom)
1070 dma_free_coherent(&ha->pdev->dev,
1071 OPTROM_BURST_SIZE, optrom, optrom_dma);
1072
459c5378
AV		 1073 return ret;
1074}
1075
1076uint8_t *
7b867cf7 1077qla2x00_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
459c5378
AV		 1078 uint32_t bytes)
1079{
1080 uint32_t i;
1081 uint16_t *wptr;
7b867cf7 1082 struct qla_hw_data *ha = vha->hw;
459c5378
AV		 1083
1084 /* Word reads to NVRAM via registers. */
1085 wptr = (uint16_t *)buf;
1086 qla2x00_lock_nvram_access(ha);
1087 for (i = 0; i < bytes >> 1; i++, naddr++)
1088 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
1089 naddr));
1090 qla2x00_unlock_nvram_access(ha);
1091
1092 return buf;
1093}
1094
1095uint8_t *
7b867cf7 1096qla24xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
459c5378
AV		 1097 uint32_t bytes)
1098{
1099 uint32_t i;
1100 uint32_t *dwptr;
459c5378
AV		 1101
1102 /* Dword reads to flash. */
1103 dwptr = (uint32_t *)buf;
1104 for (i = 0; i < bytes >> 2; i++, naddr++)
7b867cf7 1105 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(vha->hw,
459c5378
AV		 1106 nvram_data_to_access_addr(naddr)));
1107
459c5378
AV		 1108 return buf;
1109}
1110
1111int
7b867cf7 1112qla2x00_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
459c5378
AV		 1113 uint32_t bytes)
1114{
1115 int ret, stat;
1116 uint32_t i;
1117 uint16_t *wptr;
2c96d8d0 1118 unsigned long flags;
7b867cf7 1119 struct qla_hw_data *ha = vha->hw;
459c5378
AV		 1120
1121 ret = QLA_SUCCESS;
1122
2c96d8d0 1123 spin_lock_irqsave(&ha->hardware_lock, flags);
459c5378
AV		 1124 qla2x00_lock_nvram_access(ha);
1125
1126 /* Disable NVRAM write-protection. */
1127 stat = qla2x00_clear_nvram_protection(ha);
1128
1129 wptr = (uint16_t *)buf;
1130 for (i = 0; i < bytes >> 1; i++, naddr++) {
1131 qla2x00_write_nvram_word(ha, naddr,
1132 cpu_to_le16(*wptr));
1133 wptr++;
1134 }
1135
1136 /* Enable NVRAM write-protection. */
1137 qla2x00_set_nvram_protection(ha, stat);
1138
1139 qla2x00_unlock_nvram_access(ha);
2c96d8d0 1140 spin_unlock_irqrestore(&ha->hardware_lock, flags);
459c5378
AV		 1141
1142 return ret;
1143}
1144
1145int
7b867cf7 1146qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
459c5378
AV		 1147 uint32_t bytes)
1148{
1149 int ret;
1150 uint32_t i;
1151 uint32_t *dwptr;
7b867cf7 1152 struct qla_hw_data *ha = vha->hw;
459c5378
AV		 1153 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1154
1155 ret = QLA_SUCCESS;
1156
459c5378
AV		 1157 /* Enable flash write. */
1158 WRT_REG_DWORD(&reg->ctrl_status,
1159 RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1160 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1161
1162 /* Disable NVRAM write-protection. */
1163 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
1164 0);
1165 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
1166 0);
1167
1168 /* Dword writes to flash. */
1169 dwptr = (uint32_t *)buf;
1170 for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
1171 ret = qla24xx_write_flash_dword(ha,
1172 nvram_data_to_access_addr(naddr),
1173 cpu_to_le32(*dwptr));
1174 if (ret != QLA_SUCCESS) {
7b867cf7
AC		 1175 DEBUG9(qla_printk("Unable to program nvram address=%x "
1176 "data=%x.\n", naddr, *dwptr));
459c5378
AV		 1177 break;
1178 }
1179 }
1180
1181 /* Enable NVRAM write-protection. */
1182 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
1183 0x8c);
1184
1185 /* Disable flash write. */
1186 WRT_REG_DWORD(&reg->ctrl_status,
1187 RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1188 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1189
459c5378
AV		 1190 return ret;
1191}
f6df144c 1192
c3a2f0df 1193uint8_t *
7b867cf7 1194qla25xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
c3a2f0df
AV		 1195 uint32_t bytes)
1196{
1197 uint32_t i;
1198 uint32_t *dwptr;
7b867cf7 1199 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 1200
1201 /* Dword reads to flash. */
1202 dwptr = (uint32_t *)buf;
1203 for (i = 0; i < bytes >> 2; i++, naddr++)
1204 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
c00d8994
AV		 1205 flash_data_to_access_addr(ha->flt_region_vpd_nvram |
1206 naddr)));
c3a2f0df
AV		 1207
1208 return buf;
1209}
1210
1211int
7b867cf7 1212qla25xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
c3a2f0df
AV		 1213 uint32_t bytes)
1214{
7b867cf7 1215 struct qla_hw_data *ha = vha->hw;
2c96d8d0
AV		 1216#define RMW_BUFFER_SIZE (64 * 1024)
1217 uint8_t *dbuf;
1218
1219 dbuf = vmalloc(RMW_BUFFER_SIZE);
1220 if (!dbuf)
1221 return QLA_MEMORY_ALLOC_FAILED;
7b867cf7 1222 ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
2c96d8d0
AV		 1223 RMW_BUFFER_SIZE);
1224 memcpy(dbuf + (naddr << 2), buf, bytes);
7b867cf7 1225 ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
2c96d8d0
AV		 1226 RMW_BUFFER_SIZE);
1227 vfree(dbuf);
1228
1229 return QLA_SUCCESS;
c3a2f0df 1230}
f6df144c 1231
1232static inline void
7b867cf7 1233qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
f6df144c 1234{
1235 if (IS_QLA2322(ha)) {
1236 /* Flip all colors. */
1237 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1238 /* Turn off. */
1239 ha->beacon_color_state = 0;
1240 *pflags = GPIO_LED_ALL_OFF;
1241 } else {
1242 /* Turn on. */
1243 ha->beacon_color_state = QLA_LED_ALL_ON;
1244 *pflags = GPIO_LED_RGA_ON;
1245 }
1246 } else {
1247 /* Flip green led only. */
1248 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
1249 /* Turn off. */
1250 ha->beacon_color_state = 0;
1251 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
1252 } else {
1253 /* Turn on. */
1254 ha->beacon_color_state = QLA_LED_GRN_ON;
1255 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
1256 }
1257 }
1258}
1259
948882f6
AV		 1260#define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1261
f6df144c 1262void
7b867cf7 1263qla2x00_beacon_blink(struct scsi_qla_host *vha)
f6df144c 1264{
1265 uint16_t gpio_enable;
1266 uint16_t gpio_data;
1267 uint16_t led_color = 0;
1268 unsigned long flags;
7b867cf7 1269 struct qla_hw_data *ha = vha->hw;
f6df144c 1270 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1271
f6df144c 1272 spin_lock_irqsave(&ha->hardware_lock, flags);
1273
1274 /* Save the Original GPIOE. */
1275 if (ha->pio_address) {
948882f6
AV		 1276 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1277 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
f6df144c 1278 } else {
1279 gpio_enable = RD_REG_WORD(&reg->gpioe);
1280 gpio_data = RD_REG_WORD(&reg->gpiod);
1281 }
1282
1283 /* Set the modified gpio_enable values */
1284 gpio_enable |= GPIO_LED_MASK;
1285
1286 if (ha->pio_address) {
948882f6 1287 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
f6df144c 1288 } else {
1289 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1290 RD_REG_WORD(&reg->gpioe);
1291 }
1292
1293 qla2x00_flip_colors(ha, &led_color);
1294
1295 /* Clear out any previously set LED color. */
1296 gpio_data &= ~GPIO_LED_MASK;
1297
1298 /* Set the new input LED color to GPIOD. */
1299 gpio_data |= led_color;
1300
1301 /* Set the modified gpio_data values */
1302 if (ha->pio_address) {
948882f6 1303 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
f6df144c 1304 } else {
1305 WRT_REG_WORD(&reg->gpiod, gpio_data);
1306 RD_REG_WORD(&reg->gpiod);
1307 }
1308
1309 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1310}
1311
1312int
7b867cf7 1313qla2x00_beacon_on(struct scsi_qla_host *vha)
f6df144c 1314{
1315 uint16_t gpio_enable;
1316 uint16_t gpio_data;
1317 unsigned long flags;
7b867cf7 1318 struct qla_hw_data *ha = vha->hw;
f6df144c 1319 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1320
1321 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1322 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
1323
7b867cf7 1324 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
f6df144c 1325 qla_printk(KERN_WARNING, ha,
1326 "Unable to update fw options (beacon on).\n");
1327 return QLA_FUNCTION_FAILED;
1328 }
1329
f6df144c 1330 /* Turn off LEDs. */
1331 spin_lock_irqsave(&ha->hardware_lock, flags);
1332 if (ha->pio_address) {
948882f6
AV		 1333 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1334 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
f6df144c 1335 } else {
1336 gpio_enable = RD_REG_WORD(&reg->gpioe);
1337 gpio_data = RD_REG_WORD(&reg->gpiod);
1338 }
1339 gpio_enable |= GPIO_LED_MASK;
1340
1341 /* Set the modified gpio_enable values. */
1342 if (ha->pio_address) {
948882f6 1343 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
f6df144c 1344 } else {
1345 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1346 RD_REG_WORD(&reg->gpioe);
1347 }
1348
1349 /* Clear out previously set LED colour. */
1350 gpio_data &= ~GPIO_LED_MASK;
1351 if (ha->pio_address) {
948882f6 1352 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
f6df144c 1353 } else {
1354 WRT_REG_WORD(&reg->gpiod, gpio_data);
1355 RD_REG_WORD(&reg->gpiod);
1356 }
1357 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1358
1359 /*
1360 * Let the per HBA timer kick off the blinking process based on
1361 * the following flags. No need to do anything else now.
1362 */
1363 ha->beacon_blink_led = 1;
1364 ha->beacon_color_state = 0;
1365
1366 return QLA_SUCCESS;
1367}
1368
1369int
7b867cf7 1370qla2x00_beacon_off(struct scsi_qla_host *vha)
f6df144c 1371{
1372 int rval = QLA_SUCCESS;
7b867cf7 1373 struct qla_hw_data *ha = vha->hw;
f6df144c 1374
1375 ha->beacon_blink_led = 0;
1376
1377 /* Set the on flag so when it gets flipped it will be off. */
1378 if (IS_QLA2322(ha))
1379 ha->beacon_color_state = QLA_LED_ALL_ON;
1380 else
1381 ha->beacon_color_state = QLA_LED_GRN_ON;
1382
7b867cf7 1383 ha->isp_ops->beacon_blink(vha); /* This turns green LED off */
f6df144c 1384
1385 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1386 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1387
7b867cf7 1388 rval = qla2x00_set_fw_options(vha, ha->fw_options);
f6df144c 1389 if (rval != QLA_SUCCESS)
1390 qla_printk(KERN_WARNING, ha,
1391 "Unable to update fw options (beacon off).\n");
1392 return rval;
1393}
1394
1395
1396static inline void
7b867cf7 1397qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
f6df144c 1398{
1399 /* Flip all colors. */
1400 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1401 /* Turn off. */
1402 ha->beacon_color_state = 0;
1403 *pflags = 0;
1404 } else {
1405 /* Turn on. */
1406 ha->beacon_color_state = QLA_LED_ALL_ON;
1407 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1408 }
1409}
1410
1411void
7b867cf7 1412qla24xx_beacon_blink(struct scsi_qla_host *vha)
f6df144c 1413{
1414 uint16_t led_color = 0;
1415 uint32_t gpio_data;
1416 unsigned long flags;
7b867cf7 1417 struct qla_hw_data *ha = vha->hw;
f6df144c 1418 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1419
1420 /* Save the Original GPIOD. */
1421 spin_lock_irqsave(&ha->hardware_lock, flags);
1422 gpio_data = RD_REG_DWORD(&reg->gpiod);
1423
1424 /* Enable the gpio_data reg for update. */
1425 gpio_data |= GPDX_LED_UPDATE_MASK;
1426
1427 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1428 gpio_data = RD_REG_DWORD(&reg->gpiod);
1429
1430 /* Set the color bits. */
1431 qla24xx_flip_colors(ha, &led_color);
1432
1433 /* Clear out any previously set LED color. */
1434 gpio_data &= ~GPDX_LED_COLOR_MASK;
1435
1436 /* Set the new input LED color to GPIOD. */
1437 gpio_data |= led_color;
1438
1439 /* Set the modified gpio_data values. */
1440 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1441 gpio_data = RD_REG_DWORD(&reg->gpiod);
1442 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1443}
1444
1445int
7b867cf7 1446qla24xx_beacon_on(struct scsi_qla_host *vha)
f6df144c 1447{
1448 uint32_t gpio_data;
1449 unsigned long flags;
7b867cf7 1450 struct qla_hw_data *ha = vha->hw;
f6df144c 1451 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1452
1453 if (ha->beacon_blink_led == 0) {
1454 /* Enable firmware for update */
1455 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1456
7b867cf7 1457 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS)
f6df144c 1458 return QLA_FUNCTION_FAILED;
1459
7b867cf7 1460 if (qla2x00_get_fw_options(vha, ha->fw_options) !=
f6df144c 1461 QLA_SUCCESS) {
1462 qla_printk(KERN_WARNING, ha,
1463 "Unable to update fw options (beacon on).\n");
1464 return QLA_FUNCTION_FAILED;
1465 }
1466
1467 spin_lock_irqsave(&ha->hardware_lock, flags);
1468 gpio_data = RD_REG_DWORD(&reg->gpiod);
1469
1470 /* Enable the gpio_data reg for update. */
1471 gpio_data |= GPDX_LED_UPDATE_MASK;
1472 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1473 RD_REG_DWORD(&reg->gpiod);
1474
1475 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1476 }
1477
1478 /* So all colors blink together. */
1479 ha->beacon_color_state = 0;
1480
1481 /* Let the per HBA timer kick off the blinking process. */
1482 ha->beacon_blink_led = 1;
1483
1484 return QLA_SUCCESS;
1485}
1486
1487int
7b867cf7 1488qla24xx_beacon_off(struct scsi_qla_host *vha)
f6df144c 1489{
1490 uint32_t gpio_data;
1491 unsigned long flags;
7b867cf7 1492 struct qla_hw_data *ha = vha->hw;
f6df144c 1493 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1494
1495 ha->beacon_blink_led = 0;
1496 ha->beacon_color_state = QLA_LED_ALL_ON;
1497
7b867cf7 1498 ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */
f6df144c 1499
1500 /* Give control back to firmware. */
1501 spin_lock_irqsave(&ha->hardware_lock, flags);
1502 gpio_data = RD_REG_DWORD(&reg->gpiod);
1503
1504 /* Disable the gpio_data reg for update. */
1505 gpio_data &= ~GPDX_LED_UPDATE_MASK;
1506 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1507 RD_REG_DWORD(&reg->gpiod);
1508 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1509
1510 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1511
7b867cf7 1512 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
f6df144c 1513 qla_printk(KERN_WARNING, ha,
1514 "Unable to update fw options (beacon off).\n");
1515 return QLA_FUNCTION_FAILED;
1516 }
1517
7b867cf7 1518 if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
f6df144c 1519 qla_printk(KERN_WARNING, ha,
1520 "Unable to get fw options (beacon off).\n");
1521 return QLA_FUNCTION_FAILED;
1522 }
1523
1524 return QLA_SUCCESS;
1525}
854165f4 1526
1527
1528/*
1529 * Flash support routines
1530 */
1531
1532/**
1533 * qla2x00_flash_enable() - Setup flash for reading and writing.
1534 * @ha: HA context
1535 */
1536static void
7b867cf7 1537qla2x00_flash_enable(struct qla_hw_data *ha)
854165f4 1538{
1539 uint16_t data;
1540 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1541
1542 data = RD_REG_WORD(&reg->ctrl_status);
1543 data |= CSR_FLASH_ENABLE;
1544 WRT_REG_WORD(&reg->ctrl_status, data);
1545 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1546}
1547
1548/**
1549 * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1550 * @ha: HA context
1551 */
1552static void
7b867cf7 1553qla2x00_flash_disable(struct qla_hw_data *ha)
854165f4 1554{
1555 uint16_t data;
1556 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1557
1558 data = RD_REG_WORD(&reg->ctrl_status);
1559 data &= ~(CSR_FLASH_ENABLE);
1560 WRT_REG_WORD(&reg->ctrl_status, data);
1561 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1562}
1563
1564/**
1565 * qla2x00_read_flash_byte() - Reads a byte from flash
1566 * @ha: HA context
1567 * @addr: Address in flash to read
1568 *
1569 * A word is read from the chip, but, only the lower byte is valid.
1570 *
1571 * Returns the byte read from flash @addr.
1572 */
1573static uint8_t
7b867cf7 1574qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr)
854165f4 1575{
1576 uint16_t data;
1577 uint16_t bank_select;
1578 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1579
1580 bank_select = RD_REG_WORD(&reg->ctrl_status);
1581
1582 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1583 /* Specify 64K address range: */
1584 /* clear out Module Select and Flash Address bits [19:16]. */
1585 bank_select &= ~0xf8;
1586 bank_select |= addr >> 12 & 0xf0;
1587 bank_select |= CSR_FLASH_64K_BANK;
1588 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1589 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1590
1591 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1592 data = RD_REG_WORD(&reg->flash_data);
1593
1594 return (uint8_t)data;
1595 }
1596
1597 /* Setup bit 16 of flash address. */
1598 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1599 bank_select |= CSR_FLASH_64K_BANK;
1600 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1601 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1602 } else if (((addr & BIT_16) == 0) &&
1603 (bank_select & CSR_FLASH_64K_BANK)) {
1604 bank_select &= ~(CSR_FLASH_64K_BANK);
1605 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1606 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1607 }
1608
1609 /* Always perform IO mapped accesses to the FLASH registers. */
1610 if (ha->pio_address) {
1611 uint16_t data2;
1612
948882f6 1613 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
854165f4 1614 do {
948882f6 1615 data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
854165f4 1616 barrier();
1617 cpu_relax();
948882f6 1618 data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
854165f4 1619 } while (data != data2);
1620 } else {
1621 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1622 data = qla2x00_debounce_register(&reg->flash_data);
1623 }
1624
1625 return (uint8_t)data;
1626}
1627
1628/**
1629 * qla2x00_write_flash_byte() - Write a byte to flash
1630 * @ha: HA context
1631 * @addr: Address in flash to write
1632 * @data: Data to write
1633 */
1634static void
7b867cf7 1635qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data)
854165f4 1636{
1637 uint16_t bank_select;
1638 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1639
1640 bank_select = RD_REG_WORD(&reg->ctrl_status);
1641 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1642 /* Specify 64K address range: */
1643 /* clear out Module Select and Flash Address bits [19:16]. */
1644 bank_select &= ~0xf8;
1645 bank_select |= addr >> 12 & 0xf0;
1646 bank_select |= CSR_FLASH_64K_BANK;
1647 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1648 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1649
1650 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1651 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1652 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1653 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1654
1655 return;
1656 }
1657
1658 /* Setup bit 16 of flash address. */
1659 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1660 bank_select |= CSR_FLASH_64K_BANK;
1661 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1662 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1663 } else if (((addr & BIT_16) == 0) &&
1664 (bank_select & CSR_FLASH_64K_BANK)) {
1665 bank_select &= ~(CSR_FLASH_64K_BANK);
1666 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1667 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1668 }
1669
1670 /* Always perform IO mapped accesses to the FLASH registers. */
1671 if (ha->pio_address) {
948882f6
AV		 1672 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1673 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
854165f4 1674 } else {
1675 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1676 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1677 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1678 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1679 }
1680}
1681
1682/**
1683 * qla2x00_poll_flash() - Polls flash for completion.
1684 * @ha: HA context
1685 * @addr: Address in flash to poll
1686 * @poll_data: Data to be polled
1687 * @man_id: Flash manufacturer ID
1688 * @flash_id: Flash ID
1689 *
1690 * This function polls the device until bit 7 of what is read matches data
1691 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed
1692 * out (a fatal error). The flash book recommeds reading bit 7 again after
1693 * reading bit 5 as a 1.
1694 *
1695 * Returns 0 on success, else non-zero.
1696 */
1697static int
7b867cf7 1698qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data,
854165f4 1699 uint8_t man_id, uint8_t flash_id)
1700{
1701 int status;
1702 uint8_t flash_data;
1703 uint32_t cnt;
1704
1705 status = 1;
1706
1707 /* Wait for 30 seconds for command to finish. */
1708 poll_data &= BIT_7;
1709 for (cnt = 3000000; cnt; cnt--) {
1710 flash_data = qla2x00_read_flash_byte(ha, addr);
1711 if ((flash_data & BIT_7) == poll_data) {
1712 status = 0;
1713 break;
1714 }
1715
1716 if (man_id != 0x40 && man_id != 0xda) {
1717 if ((flash_data & BIT_5) && cnt > 2)
1718 cnt = 2;
1719 }
1720 udelay(10);
1721 barrier();
40a2e34a 1722 cond_resched();
854165f4 1723 }
1724 return status;
1725}
1726
854165f4 1727/**
1728 * qla2x00_program_flash_address() - Programs a flash address
1729 * @ha: HA context
1730 * @addr: Address in flash to program
1731 * @data: Data to be written in flash
1732 * @man_id: Flash manufacturer ID
1733 * @flash_id: Flash ID
1734 *
1735 * Returns 0 on success, else non-zero.
1736 */
1737static int
7b867cf7
AC		 1738qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr,
1739 uint8_t data, uint8_t man_id, uint8_t flash_id)
854165f4 1740{
1741 /* Write Program Command Sequence. */
1742 if (IS_OEM_001(ha)) {
1743 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1744 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1745 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
1746 qla2x00_write_flash_byte(ha, addr, data);
1747 } else {
1748 if (man_id == 0xda && flash_id == 0xc1) {
1749 qla2x00_write_flash_byte(ha, addr, data);
1750 if (addr & 0x7e)
1751 return 0;
1752 } else {
1753 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1754 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1755 qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
1756 qla2x00_write_flash_byte(ha, addr, data);
1757 }
1758 }
1759
1760 udelay(150);
1761
1762 /* Wait for write to complete. */
1763 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
1764}
1765
1766/**
1767 * qla2x00_erase_flash() - Erase the flash.
1768 * @ha: HA context
1769 * @man_id: Flash manufacturer ID
1770 * @flash_id: Flash ID
1771 *
1772 * Returns 0 on success, else non-zero.
1773 */
1774static int
7b867cf7 1775qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id)
854165f4 1776{
1777 /* Individual Sector Erase Command Sequence */
1778 if (IS_OEM_001(ha)) {
1779 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1780 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1781 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
1782 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1783 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1784 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
1785 } else {
1786 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1787 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1788 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1789 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1790 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1791 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
1792 }
1793
1794 udelay(150);
1795
1796 /* Wait for erase to complete. */
1797 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
1798}
1799
1800/**
1801 * qla2x00_erase_flash_sector() - Erase a flash sector.
1802 * @ha: HA context
1803 * @addr: Flash sector to erase
1804 * @sec_mask: Sector address mask
1805 * @man_id: Flash manufacturer ID
1806 * @flash_id: Flash ID
1807 *
1808 * Returns 0 on success, else non-zero.
1809 */
1810static int
7b867cf7 1811qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr,
854165f4 1812 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
1813{
1814 /* Individual Sector Erase Command Sequence */
1815 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1816 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1817 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1818 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1819 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1820 if (man_id == 0x1f && flash_id == 0x13)
1821 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
1822 else
1823 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
1824
1825 udelay(150);
1826
1827 /* Wait for erase to complete. */
1828 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
1829}
1830
1831/**
1832 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
1833 * @man_id: Flash manufacturer ID
1834 * @flash_id: Flash ID
1835 */
1836static void
7b867cf7 1837qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
854165f4 1838 uint8_t *flash_id)
1839{
1840 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1841 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1842 qla2x00_write_flash_byte(ha, 0x5555, 0x90);
1843 *man_id = qla2x00_read_flash_byte(ha, 0x0000);
1844 *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
1845 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1846 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1847 qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
1848}
1849
30c47662 1850static void
7b867cf7
AC		 1851qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf,
1852 uint32_t saddr, uint32_t length)
30c47662
AV		 1853{
1854 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1855 uint32_t midpoint, ilength;
1856 uint8_t data;
1857
1858 midpoint = length / 2;
1859
1860 WRT_REG_WORD(&reg->nvram, 0);
1861 RD_REG_WORD(&reg->nvram);
1862 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
1863 if (ilength == midpoint) {
1864 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1865 RD_REG_WORD(&reg->nvram);
1866 }
1867 data = qla2x00_read_flash_byte(ha, saddr);
1868 if (saddr % 100)
1869 udelay(10);
1870 *tmp_buf = data;
40a2e34a 1871 cond_resched();
30c47662
AV		 1872 }
1873}
854165f4 1874
1875static inline void
7b867cf7 1876qla2x00_suspend_hba(struct scsi_qla_host *vha)
854165f4 1877{
1878 int cnt;
1879 unsigned long flags;
7b867cf7 1880 struct qla_hw_data *ha = vha->hw;
854165f4 1881 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1882
1883 /* Suspend HBA. */
7b867cf7 1884 scsi_block_requests(vha->host);
fd34f556 1885 ha->isp_ops->disable_intrs(ha);
854165f4 1886 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1887
1888 /* Pause RISC. */
1889 spin_lock_irqsave(&ha->hardware_lock, flags);
1890 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1891 RD_REG_WORD(&reg->hccr);
1892 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1893 for (cnt = 0; cnt < 30000; cnt++) {
1894 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
1895 break;
1896 udelay(100);
1897 }
1898 } else {
1899 udelay(10);
1900 }
1901 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1902}
1903
1904static inline void
7b867cf7 1905qla2x00_resume_hba(struct scsi_qla_host *vha)
854165f4 1906{
7b867cf7
AC		 1907 struct qla_hw_data *ha = vha->hw;
1908
854165f4 1909 /* Resume HBA. */
1910 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
7b867cf7
AC		 1911 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1912 qla2xxx_wake_dpc(vha);
1913 qla2x00_wait_for_hba_online(vha);
1914 scsi_unblock_requests(vha->host);
854165f4 1915}
1916
1917uint8_t *
7b867cf7 1918qla2x00_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
854165f4 1919 uint32_t offset, uint32_t length)
1920{
854165f4 1921 uint32_t addr, midpoint;
1922 uint8_t *data;
7b867cf7 1923 struct qla_hw_data *ha = vha->hw;
854165f4 1924 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1925
1926 /* Suspend HBA. */
7b867cf7 1927 qla2x00_suspend_hba(vha);
854165f4 1928
1929 /* Go with read. */
854165f4 1930 midpoint = ha->optrom_size / 2;
1931
1932 qla2x00_flash_enable(ha);
1933 WRT_REG_WORD(&reg->nvram, 0);
1934 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
1935 for (addr = offset, data = buf; addr < length; addr++, data++) {
1936 if (addr == midpoint) {
1937 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1938 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
1939 }
1940
1941 *data = qla2x00_read_flash_byte(ha, addr);
1942 }
1943 qla2x00_flash_disable(ha);
854165f4 1944
1945 /* Resume HBA. */
7b867cf7 1946 qla2x00_resume_hba(vha);
854165f4 1947
1948 return buf;
1949}
1950
1951int
7b867cf7 1952qla2x00_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
854165f4 1953 uint32_t offset, uint32_t length)
1954{
1955
1956 int rval;
854165f4 1957 uint8_t man_id, flash_id, sec_number, data;
1958 uint16_t wd;
1959 uint32_t addr, liter, sec_mask, rest_addr;
7b867cf7 1960 struct qla_hw_data *ha = vha->hw;
854165f4 1961 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1962
1963 /* Suspend HBA. */
7b867cf7 1964 qla2x00_suspend_hba(vha);
854165f4 1965
1966 rval = QLA_SUCCESS;
1967 sec_number = 0;
1968
1969 /* Reset ISP chip. */
854165f4 1970 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1971 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
1972
1973 /* Go with write. */
1974 qla2x00_flash_enable(ha);
1975 do { /* Loop once to provide quick error exit */
1976 /* Structure of flash memory based on manufacturer */
1977 if (IS_OEM_001(ha)) {
1978 /* OEM variant with special flash part. */
1979 man_id = flash_id = 0;
1980 rest_addr = 0xffff;
1981 sec_mask = 0x10000;
1982 goto update_flash;
1983 }
1984 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
1985 switch (man_id) {
1986 case 0x20: /* ST flash. */
1987 if (flash_id == 0xd2 || flash_id == 0xe3) {
1988 /*
1989 * ST m29w008at part - 64kb sector size with
1990 * 32kb,8kb,8kb,16kb sectors at memory address
1991 * 0xf0000.
1992 */
1993 rest_addr = 0xffff;
1994 sec_mask = 0x10000;
1995 break;
1996 }
1997 /*
1998 * ST m29w010b part - 16kb sector size
1999 * Default to 16kb sectors
2000 */
2001 rest_addr = 0x3fff;
2002 sec_mask = 0x1c000;
2003 break;
2004 case 0x40: /* Mostel flash. */
2005 /* Mostel v29c51001 part - 512 byte sector size. */
2006 rest_addr = 0x1ff;
2007 sec_mask = 0x1fe00;
2008 break;
2009 case 0xbf: /* SST flash. */
2010 /* SST39sf10 part - 4kb sector size. */
2011 rest_addr = 0xfff;
2012 sec_mask = 0x1f000;
2013 break;
2014 case 0xda: /* Winbond flash. */
2015 /* Winbond W29EE011 part - 256 byte sector size. */
2016 rest_addr = 0x7f;
2017 sec_mask = 0x1ff80;
2018 break;
2019 case 0xc2: /* Macronix flash. */
2020 /* 64k sector size. */
2021 if (flash_id == 0x38 || flash_id == 0x4f) {
2022 rest_addr = 0xffff;
2023 sec_mask = 0x10000;
2024 break;
2025 }
2026 /* Fall through... */
2027
2028 case 0x1f: /* Atmel flash. */
2029 /* 512k sector size. */
2030 if (flash_id == 0x13) {
2031 rest_addr = 0x7fffffff;
2032 sec_mask = 0x80000000;
2033 break;
2034 }
2035 /* Fall through... */
2036
2037 case 0x01: /* AMD flash. */
2038 if (flash_id == 0x38 || flash_id == 0x40 ||
2039 flash_id == 0x4f) {
2040 /* Am29LV081 part - 64kb sector size. */
2041 /* Am29LV002BT part - 64kb sector size. */
2042 rest_addr = 0xffff;
2043 sec_mask = 0x10000;
2044 break;
2045 } else if (flash_id == 0x3e) {
2046 /*
2047 * Am29LV008b part - 64kb sector size with
2048 * 32kb,8kb,8kb,16kb sector at memory address
2049 * h0xf0000.
2050 */
2051 rest_addr = 0xffff;
2052 sec_mask = 0x10000;
2053 break;
2054 } else if (flash_id == 0x20 || flash_id == 0x6e) {
2055 /*
2056 * Am29LV010 part or AM29f010 - 16kb sector
2057 * size.
2058 */
2059 rest_addr = 0x3fff;
2060 sec_mask = 0x1c000;
2061 break;
2062 } else if (flash_id == 0x6d) {
2063 /* Am29LV001 part - 8kb sector size. */
2064 rest_addr = 0x1fff;
2065 sec_mask = 0x1e000;
2066 break;
2067 }
2068 default:
2069 /* Default to 16 kb sector size. */
2070 rest_addr = 0x3fff;
2071 sec_mask = 0x1c000;
2072 break;
2073 }
2074
2075update_flash:
2076 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2077 if (qla2x00_erase_flash(ha, man_id, flash_id)) {
2078 rval = QLA_FUNCTION_FAILED;
2079 break;
2080 }
2081 }
2082
2083 for (addr = offset, liter = 0; liter < length; liter++,
2084 addr++) {
2085 data = buf[liter];
2086 /* Are we at the beginning of a sector? */
2087 if ((addr & rest_addr) == 0) {
2088 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2089 if (addr >= 0x10000UL) {
2090 if (((addr >> 12) & 0xf0) &&
2091 ((man_id == 0x01 &&
2092 flash_id == 0x3e) ||
2093 (man_id == 0x20 &&
2094 flash_id == 0xd2))) {
2095 sec_number++;
2096 if (sec_number == 1) {
2097 rest_addr =
2098 0x7fff;
2099 sec_mask =
2100 0x18000;
2101 } else if (
2102 sec_number == 2 ||
2103 sec_number == 3) {
2104 rest_addr =
2105 0x1fff;
2106 sec_mask =
2107 0x1e000;
2108 } else if (
2109 sec_number == 4) {
2110 rest_addr =
2111 0x3fff;
2112 sec_mask =
2113 0x1c000;
2114 }
2115 }
2116 }
2117 } else if (addr == ha->optrom_size / 2) {
2118 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2119 RD_REG_WORD(&reg->nvram);
2120 }
2121
2122 if (flash_id == 0xda && man_id == 0xc1) {
2123 qla2x00_write_flash_byte(ha, 0x5555,
2124 0xaa);
2125 qla2x00_write_flash_byte(ha, 0x2aaa,
2126 0x55);
2127 qla2x00_write_flash_byte(ha, 0x5555,
2128 0xa0);
2129 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
2130 /* Then erase it */
2131 if (qla2x00_erase_flash_sector(ha,
2132 addr, sec_mask, man_id,
2133 flash_id)) {
2134 rval = QLA_FUNCTION_FAILED;
2135 break;
2136 }
2137 if (man_id == 0x01 && flash_id == 0x6d)
2138 sec_number++;
2139 }
2140 }
2141
2142 if (man_id == 0x01 && flash_id == 0x6d) {
2143 if (sec_number == 1 &&
2144 addr == (rest_addr - 1)) {
2145 rest_addr = 0x0fff;
2146 sec_mask = 0x1f000;
2147 } else if (sec_number == 3 && (addr & 0x7ffe)) {
2148 rest_addr = 0x3fff;
2149 sec_mask = 0x1c000;
2150 }
2151 }
2152
2153 if (qla2x00_program_flash_address(ha, addr, data,
2154 man_id, flash_id)) {
2155 rval = QLA_FUNCTION_FAILED;
2156 break;
2157 }
40a2e34a 2158 cond_resched();
854165f4 2159 }
2160 } while (0);
2161 qla2x00_flash_disable(ha);
854165f4 2162
2163 /* Resume HBA. */
7b867cf7 2164 qla2x00_resume_hba(vha);
854165f4 2165
2166 return rval;
2167}
2168
2169uint8_t *
7b867cf7 2170qla24xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
854165f4 2171 uint32_t offset, uint32_t length)
2172{
7b867cf7
AC		 2173 struct qla_hw_data *ha = vha->hw;
2174
854165f4 2175 /* Suspend HBA. */
7b867cf7 2176 scsi_block_requests(vha->host);
854165f4 2177 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2178
2179 /* Go with read. */
7b867cf7 2180 qla24xx_read_flash_data(vha, (uint32_t *)buf, offset >> 2, length >> 2);
854165f4 2181
2182 /* Resume HBA. */
2183 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
7b867cf7 2184 scsi_unblock_requests(vha->host);
854165f4 2185
2186 return buf;
2187}
2188
2189int
7b867cf7 2190qla24xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
854165f4 2191 uint32_t offset, uint32_t length)
2192{
2193 int rval;
7b867cf7 2194 struct qla_hw_data *ha = vha->hw;
854165f4 2195
2196 /* Suspend HBA. */
7b867cf7 2197 scsi_block_requests(vha->host);
854165f4 2198 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2199
2200 /* Go with write. */
7b867cf7 2201 rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, offset >> 2,
854165f4 2202 length >> 2);
2203
2204 /* Resume HBA -- RISC reset needed. */
2205 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
7b867cf7
AC		 2206 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2207 qla2xxx_wake_dpc(vha);
2208 qla2x00_wait_for_hba_online(vha);
2209 scsi_unblock_requests(vha->host);
854165f4 2210
2211 return rval;
2212}
30c47662 2213
338c9161 2214uint8_t *
7b867cf7 2215qla25xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
338c9161
AV		 2216 uint32_t offset, uint32_t length)
2217{
2218 int rval;
2219 dma_addr_t optrom_dma;
2220 void *optrom;
2221 uint8_t *pbuf;
2222 uint32_t faddr, left, burst;
7b867cf7 2223 struct qla_hw_data *ha = vha->hw;
338c9161 2224
b7cc176c 2225 if (offset & 0xfff)
338c9161
AV		 2226 goto slow_read;
2227 if (length < OPTROM_BURST_SIZE)
2228 goto slow_read;
2229
2230 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2231 &optrom_dma, GFP_KERNEL);
2232 if (!optrom) {
2233 qla_printk(KERN_DEBUG, ha,
2234 "Unable to allocate memory for optrom burst read "
2235 "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
2236
2237 goto slow_read;
2238 }
2239
2240 pbuf = buf;
2241 faddr = offset >> 2;
2242 left = length >> 2;
2243 burst = OPTROM_BURST_DWORDS;
2244 while (left != 0) {
2245 if (burst > left)
2246 burst = left;
2247
7b867cf7 2248 rval = qla2x00_dump_ram(vha, optrom_dma,
338c9161
AV		 2249 flash_data_to_access_addr(faddr), burst);
2250 if (rval) {
2251 qla_printk(KERN_WARNING, ha,
2252 "Unable to burst-read optrom segment "
2253 "(%x/%x/%llx).\n", rval,
875baf3c
AM		 2254 flash_data_to_access_addr(faddr),
2255 (unsigned long long)optrom_dma);
338c9161
AV		 2256 qla_printk(KERN_WARNING, ha,
2257 "Reverting to slow-read.\n");
2258
2259 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2260 optrom, optrom_dma);
2261 goto slow_read;
2262 }
2263
2264 memcpy(pbuf, optrom, burst * 4);
2265
2266 left -= burst;
2267 faddr += burst;
2268 pbuf += burst * 4;
2269 }
2270
2271 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
2272 optrom_dma);
2273
2274 return buf;
2275
2276slow_read:
7b867cf7 2277 return qla24xx_read_optrom_data(vha, buf, offset, length);
338c9161
AV		 2278}
2279
30c47662
AV		 2280/**
2281 * qla2x00_get_fcode_version() - Determine an FCODE image's version.
2282 * @ha: HA context
2283 * @pcids: Pointer to the FCODE PCI data structure
2284 *
2285 * The process of retrieving the FCODE version information is at best
2286 * described as interesting.
2287 *
2288 * Within the first 100h bytes of the image an ASCII string is present
2289 * which contains several pieces of information including the FCODE
2290 * version. Unfortunately it seems the only reliable way to retrieve
2291 * the version is by scanning for another sentinel within the string,
2292 * the FCODE build date:
2293 *
2294 * ... 2.00.02 10/17/02 ...
2295 *
2296 * Returns QLA_SUCCESS on successful retrieval of version.
2297 */
2298static void
7b867cf7 2299qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids)
30c47662
AV		 2300{
2301 int ret = QLA_FUNCTION_FAILED;
2302 uint32_t istart, iend, iter, vend;
2303 uint8_t do_next, rbyte, *vbyte;
2304
2305 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2306
2307 /* Skip the PCI data structure. */
2308 istart = pcids +
2309 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
2310 qla2x00_read_flash_byte(ha, pcids + 0x0A));
2311 iend = istart + 0x100;
2312 do {
2313 /* Scan for the sentinel date string...eeewww. */
2314 do_next = 0;
2315 iter = istart;
2316 while ((iter < iend) && !do_next) {
2317 iter++;
2318 if (qla2x00_read_flash_byte(ha, iter) == '/') {
2319 if (qla2x00_read_flash_byte(ha, iter + 2) ==
2320 '/')
2321 do_next++;
2322 else if (qla2x00_read_flash_byte(ha,
2323 iter + 3) == '/')
2324 do_next++;
2325 }
2326 }
2327 if (!do_next)
2328 break;
2329
2330 /* Backtrack to previous ' ' (space). */
2331 do_next = 0;
2332 while ((iter > istart) && !do_next) {
2333 iter--;
2334 if (qla2x00_read_flash_byte(ha, iter) == ' ')
2335 do_next++;
2336 }
2337 if (!do_next)
2338 break;
2339
2340 /*
2341 * Mark end of version tag, and find previous ' ' (space) or
2342 * string length (recent FCODE images -- major hack ahead!!!).
2343 */
2344 vend = iter - 1;
2345 do_next = 0;
2346 while ((iter > istart) && !do_next) {
2347 iter--;
2348 rbyte = qla2x00_read_flash_byte(ha, iter);
2349 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
2350 do_next++;
2351 }
2352 if (!do_next)
2353 break;
2354
2355 /* Mark beginning of version tag, and copy data. */
2356 iter++;
2357 if ((vend - iter) &&
2358 ((vend - iter) < sizeof(ha->fcode_revision))) {
2359 vbyte = ha->fcode_revision;
2360 while (iter <= vend) {
2361 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
2362 iter++;
2363 }
2364 ret = QLA_SUCCESS;
2365 }
2366 } while (0);
2367
2368 if (ret != QLA_SUCCESS)
2369 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2370}
2371
2372int
7b867cf7 2373qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
30c47662
AV		 2374{
2375 int ret = QLA_SUCCESS;
2376 uint8_t code_type, last_image;
2377 uint32_t pcihdr, pcids;
2378 uint8_t *dbyte;
2379 uint16_t *dcode;
7b867cf7 2380 struct qla_hw_data *ha = vha->hw;
30c47662
AV		 2381
2382 if (!ha->pio_address || !mbuf)
2383 return QLA_FUNCTION_FAILED;
2384
2385 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2386 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2387 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2388 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2389
2390 qla2x00_flash_enable(ha);
2391
2392 /* Begin with first PCI expansion ROM header. */
2393 pcihdr = 0;
2394 last_image = 1;
2395 do {
2396 /* Verify PCI expansion ROM header. */
2397 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
2398 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2399 /* No signature */
7b867cf7
AC		 2400 DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM "
2401 "signature.\n"));
30c47662
AV		 2402 ret = QLA_FUNCTION_FAILED;
2403 break;
2404 }
2405
2406 /* Locate PCI data structure. */
2407 pcids = pcihdr +
2408 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2409 qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2410
2411 /* Validate signature of PCI data structure. */
2412 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2413 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2414 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2415 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2416 /* Incorrect header. */
7b867cf7
AC		 2417 DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not "
2418 "found pcir_adr=%x.\n", pcids));
30c47662
AV		 2419 ret = QLA_FUNCTION_FAILED;
2420 break;
2421 }
2422
2423 /* Read version */
2424 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2425 switch (code_type) {
2426 case ROM_CODE_TYPE_BIOS:
2427 /* Intel x86, PC-AT compatible. */
2428 ha->bios_revision[0] =
2429 qla2x00_read_flash_byte(ha, pcids + 0x12);
2430 ha->bios_revision[1] =
2431 qla2x00_read_flash_byte(ha, pcids + 0x13);
7b867cf7 2432 DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n",
30c47662
AV		 2433 ha->bios_revision[1], ha->bios_revision[0]));
2434 break;
2435 case ROM_CODE_TYPE_FCODE:
2436 /* Open Firmware standard for PCI (FCode). */
2437 /* Eeeewww... */
2438 qla2x00_get_fcode_version(ha, pcids);
2439 break;
2440 case ROM_CODE_TYPE_EFI:
2441 /* Extensible Firmware Interface (EFI). */
2442 ha->efi_revision[0] =
2443 qla2x00_read_flash_byte(ha, pcids + 0x12);
2444 ha->efi_revision[1] =
2445 qla2x00_read_flash_byte(ha, pcids + 0x13);
7b867cf7 2446 DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n",
30c47662
AV		 2447 ha->efi_revision[1], ha->efi_revision[0]));
2448 break;
2449 default:
7b867cf7
AC		 2450 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code "
2451 "type %x at pcids %x.\n", code_type, pcids));
30c47662
AV		 2452 break;
2453 }
2454
2455 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2456
2457 /* Locate next PCI expansion ROM. */
2458 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2459 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2460 } while (!last_image);
2461
2462 if (IS_QLA2322(ha)) {
2463 /* Read firmware image information. */
2464 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2465 dbyte = mbuf;
2466 memset(dbyte, 0, 8);
2467 dcode = (uint16_t *)dbyte;
2468
c00d8994 2469 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10,
30c47662 2470 8);
7b867cf7
AC		 2471 DEBUG3(qla_printk(KERN_DEBUG, ha, "dumping fw ver from "
2472 "flash:\n"));
30c47662
AV		 2473 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte, 8));
2474
2475 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2476 dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2477 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2478 dcode[3] == 0)) {
7b867cf7
AC		 2479 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw "
2480 "revision at %x.\n", ha->flt_region_fw * 4));
30c47662
AV		 2481 } else {
2482 /* values are in big endian */
2483 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2484 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2485 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
2486 }
2487 }
2488
2489 qla2x00_flash_disable(ha);
2490
2491 return ret;
2492}
2493
2494int
7b867cf7 2495qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
30c47662
AV		 2496{
2497 int ret = QLA_SUCCESS;
2498 uint32_t pcihdr, pcids;
2499 uint32_t *dcode;
2500 uint8_t *bcode;
2501 uint8_t code_type, last_image;
2502 int i;
7b867cf7 2503 struct qla_hw_data *ha = vha->hw;
30c47662
AV		 2504
2505 if (!mbuf)
2506 return QLA_FUNCTION_FAILED;
2507
2508 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2509 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2510 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2511 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2512
2513 dcode = mbuf;
2514
2515 /* Begin with first PCI expansion ROM header. */
c00d8994 2516 pcihdr = ha->flt_region_boot;
30c47662
AV		 2517 last_image = 1;
2518 do {
2519 /* Verify PCI expansion ROM header. */
7b867cf7 2520 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
30c47662
AV		 2521 bcode = mbuf + (pcihdr % 4);
2522 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2523 /* No signature */
7b867cf7
AC		 2524 DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM "
2525 "signature.\n"));
30c47662
AV		 2526 ret = QLA_FUNCTION_FAILED;
2527 break;
2528 }
2529
2530 /* Locate PCI data structure. */
2531 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2532
7b867cf7 2533 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
30c47662
AV		 2534 bcode = mbuf + (pcihdr % 4);
2535
2536 /* Validate signature of PCI data structure. */
2537 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2538 bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2539 /* Incorrect header. */
7b867cf7
AC		 2540 DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not "
2541 "found pcir_adr=%x.\n", pcids));
30c47662
AV		 2542 ret = QLA_FUNCTION_FAILED;
2543 break;
2544 }
2545
2546 /* Read version */
2547 code_type = bcode[0x14];
2548 switch (code_type) {
2549 case ROM_CODE_TYPE_BIOS:
2550 /* Intel x86, PC-AT compatible. */
2551 ha->bios_revision[0] = bcode[0x12];
2552 ha->bios_revision[1] = bcode[0x13];
7b867cf7 2553 DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n",
30c47662
AV		 2554 ha->bios_revision[1], ha->bios_revision[0]));
2555 break;
2556 case ROM_CODE_TYPE_FCODE:
2557 /* Open Firmware standard for PCI (FCode). */
2558 ha->fcode_revision[0] = bcode[0x12];
2559 ha->fcode_revision[1] = bcode[0x13];
7b867cf7 2560 DEBUG3(qla_printk(KERN_DEBUG, ha, "read FCODE %d.%d.\n",
30c47662
AV		 2561 ha->fcode_revision[1], ha->fcode_revision[0]));
2562 break;
2563 case ROM_CODE_TYPE_EFI:
2564 /* Extensible Firmware Interface (EFI). */
2565 ha->efi_revision[0] = bcode[0x12];
2566 ha->efi_revision[1] = bcode[0x13];
7b867cf7 2567 DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n",
30c47662
AV		 2568 ha->efi_revision[1], ha->efi_revision[0]));
2569 break;
2570 default:
7b867cf7
AC		 2571 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code "
2572 "type %x at pcids %x.\n", code_type, pcids));
30c47662
AV		 2573 break;
2574 }
2575
2576 last_image = bcode[0x15] & BIT_7;
2577
2578 /* Locate next PCI expansion ROM. */
2579 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2580 } while (!last_image);
2581
2582 /* Read firmware image information. */
2583 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2584 dcode = mbuf;
2585
7b867cf7 2586 qla24xx_read_flash_data(vha, dcode, ha->flt_region_fw + 4, 4);
30c47662
AV		 2587 for (i = 0; i < 4; i++)
2588 dcode[i] = be32_to_cpu(dcode[i]);
2589
2590 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
2591 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
2592 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2593 dcode[3] == 0)) {
7b867cf7
AC		 2594 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw "
2595 "revision at %x.\n", ha->flt_region_fw * 4));
30c47662
AV		 2596 } else {
2597 ha->fw_revision[0] = dcode[0];
2598 ha->fw_revision[1] = dcode[1];
2599 ha->fw_revision[2] = dcode[2];
2600 ha->fw_revision[3] = dcode[3];
2601 }
2602
2603 return ret;
2604}
cb8dacbf 2605
1ee27146
JC		 2606static int
2607qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end)
2608{
2609 if (pos >= end || *pos != 0x82)
2610 return 0;
2611
2612 pos += 3 + pos[1];
2613 if (pos >= end || *pos != 0x90)
2614 return 0;
2615
2616 pos += 3 + pos[1];
2617 if (pos >= end || *pos != 0x78)
2618 return 0;
2619
2620 return 1;
2621}
2622
2623int
7b867cf7 2624qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size)
1ee27146 2625{
7b867cf7 2626 struct qla_hw_data *ha = vha->hw;
1ee27146
JC		 2627 uint8_t *pos = ha->vpd;
2628 uint8_t *end = pos + ha->vpd_size;
2629 int len = 0;
2630
2631 if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end))
2632 return 0;
2633
2634 while (pos < end && *pos != 0x78) {
2635 len = (*pos == 0x82) ? pos[1] : pos[2];
2636
2637 if (!strncmp(pos, key, strlen(key)))
2638 break;
2639
2640 if (*pos != 0x90 && *pos != 0x91)
2641 pos += len;
2642
2643 pos += 3;
2644 }
2645
2646 if (pos < end - len && *pos != 0x78)
2647 return snprintf(str, size, "%.*s", len, pos + 3);
2648
2649 return 0;
2650}
2651
cb8dacbf 2652static int
7b867cf7 2653qla2xxx_hw_event_store(scsi_qla_host_t *vha, uint32_t *fdata)
cb8dacbf
AV		 2654{
2655 uint32_t d[2], faddr;
7b867cf7 2656 struct qla_hw_data *ha = vha->hw;
cb8dacbf
AV		 2657
2658 /* Locate first empty entry. */
2659 for (;;) {
2660 if (ha->hw_event_ptr >=
c00d8994 2661 ha->flt_region_hw_event + FA_HW_EVENT_SIZE) {
cb8dacbf
AV		 2662 DEBUG2(qla_printk(KERN_WARNING, ha,
2663 "HW event -- Log Full!\n"));
2664 return QLA_MEMORY_ALLOC_FAILED;
2665 }
2666
7b867cf7 2667 qla24xx_read_flash_data(vha, d, ha->hw_event_ptr, 2);
cb8dacbf
AV		 2668 faddr = flash_data_to_access_addr(ha->hw_event_ptr);
2669 ha->hw_event_ptr += FA_HW_EVENT_ENTRY_SIZE;
2670 if (d[0] == __constant_cpu_to_le32(0xffffffff) &&
2671 d[1] == __constant_cpu_to_le32(0xffffffff)) {
2672 qla24xx_unprotect_flash(ha);
2673
2674 qla24xx_write_flash_dword(ha, faddr++,
2675 cpu_to_le32(jiffies));
2676 qla24xx_write_flash_dword(ha, faddr++, 0);
2677 qla24xx_write_flash_dword(ha, faddr++, *fdata++);
2678 qla24xx_write_flash_dword(ha, faddr++, *fdata);
2679
2680 qla24xx_protect_flash(ha);
2681 break;
2682 }
2683 }
2684 return QLA_SUCCESS;
2685}
2686
2687int
7b867cf7 2688qla2xxx_hw_event_log(scsi_qla_host_t *vha, uint16_t code, uint16_t d1,
cb8dacbf
AV		 2689 uint16_t d2, uint16_t d3)
2690{
2691#define QMARK(a, b, c, d) \
2692 cpu_to_le32(LSB(a) << 24 | LSB(b) << 16 | LSB(c) << 8 | LSB(d))
7b867cf7 2693 struct qla_hw_data *ha = vha->hw;
cb8dacbf
AV		 2694 int rval;
2695 uint32_t marker[2], fdata[4];
2696
c00d8994 2697 if (ha->flt_region_hw_event == 0)
cb8dacbf
AV		 2698 return QLA_FUNCTION_FAILED;
2699
2700 DEBUG2(qla_printk(KERN_WARNING, ha,
2701 "HW event -- code=%x, d1=%x, d2=%x, d3=%x.\n", code, d1, d2, d3));
2702
2703 /* If marker not already found, locate or write. */
2704 if (!ha->flags.hw_event_marker_found) {
2705 /* Create marker. */
2706 marker[0] = QMARK('L', ha->fw_major_version,
2707 ha->fw_minor_version, ha->fw_subminor_version);
2708 marker[1] = QMARK(QLA_DRIVER_MAJOR_VER, QLA_DRIVER_MINOR_VER,
2709 QLA_DRIVER_PATCH_VER, QLA_DRIVER_BETA_VER);
2710
2711 /* Locate marker. */
c00d8994 2712 ha->hw_event_ptr = ha->flt_region_hw_event;
cb8dacbf 2713 for (;;) {
7b867cf7 2714 qla24xx_read_flash_data(vha, fdata, ha->hw_event_ptr,
cb8dacbf
AV		 2715 4);
2716 if (fdata[0] == __constant_cpu_to_le32(0xffffffff) &&
2717 fdata[1] == __constant_cpu_to_le32(0xffffffff))
2718 break;
2719 ha->hw_event_ptr += FA_HW_EVENT_ENTRY_SIZE;
2720 if (ha->hw_event_ptr >=
c00d8994 2721 ha->flt_region_hw_event + FA_HW_EVENT_SIZE) {
cb8dacbf
AV		 2722 DEBUG2(qla_printk(KERN_WARNING, ha,
2723 "HW event -- Log Full!\n"));
2724 return QLA_MEMORY_ALLOC_FAILED;
2725 }
2726 if (fdata[2] == marker[0] && fdata[3] == marker[1]) {
2727 ha->flags.hw_event_marker_found = 1;
2728 break;
2729 }
2730 }
2731 /* No marker, write it. */
2732 if (!ha->flags.hw_event_marker_found) {
7b867cf7 2733 rval = qla2xxx_hw_event_store(vha, marker);
cb8dacbf
AV		 2734 if (rval != QLA_SUCCESS) {
2735 DEBUG2(qla_printk(KERN_WARNING, ha,
2736 "HW event -- Failed marker write=%x.!\n",
2737 rval));
2738 return rval;
2739 }
2740 ha->flags.hw_event_marker_found = 1;
2741 }
2742 }
2743
2744 /* Store error. */
2745 fdata[0] = cpu_to_le32(code << 16 | d1);
2746 fdata[1] = cpu_to_le32(d2 << 16 | d3);
7b867cf7 2747 rval = qla2xxx_hw_event_store(vha, fdata);
cb8dacbf
AV		 2748 if (rval != QLA_SUCCESS) {
2749 DEBUG2(qla_printk(KERN_WARNING, ha,
2750 "HW event -- Failed error write=%x.!\n",
2751 rval));
2752 }
2753
2754 return rval;
2755}
Linux kernel - Deliverables
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