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[SCSI] qla2xxx: Correct MSI-X vector allocation for single queue mode.
[deliverable/linux.git] / drivers / scsi / qla2xxx / qla_sup.c
CommitLineData
fa90c54f
AV		 1/*
2 * QLogic Fibre Channel HBA Driver
01e58d8e 3 * Copyright (c) 2003-2008 QLogic Corporation
1da177e4 4 *
fa90c54f
AV		 5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
1da177e4
LT		 7#include "qla_def.h"
8
9#include <linux/delay.h>
2c96d8d0 10#include <linux/vmalloc.h>
1da177e4
LT		 11#include <asm/uaccess.h>
12
1da177e4
LT		 13/*
14 * NVRAM support routines
15 */
16
17/**
fa2a1ce5 18 * qla2x00_lock_nvram_access() -
1da177e4
LT		 19 * @ha: HA context
20 */
a824ebb3 21static void
7b867cf7 22qla2x00_lock_nvram_access(struct qla_hw_data *ha)
1da177e4
LT		 23{
24 uint16_t data;
3d71644c 25 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 26
27 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
28 data = RD_REG_WORD(&reg->nvram);
29 while (data & NVR_BUSY) {
30 udelay(100);
31 data = RD_REG_WORD(&reg->nvram);
32 }
33
34 /* Lock resource */
35 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
36 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
37 udelay(5);
38 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
39 while ((data & BIT_0) == 0) {
40 /* Lock failed */
41 udelay(100);
42 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
43 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
44 udelay(5);
45 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
46 }
47 }
48}
49
50/**
fa2a1ce5 51 * qla2x00_unlock_nvram_access() -
1da177e4
LT		 52 * @ha: HA context
53 */
a824ebb3 54static void
7b867cf7 55qla2x00_unlock_nvram_access(struct qla_hw_data *ha)
1da177e4 56{
3d71644c 57 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 58
59 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
60 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
61 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
62 }
63}
64
7b867cf7
AC		 65/**
66 * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
67 * @ha: HA context
68 * @data: Serial interface selector
69 */
70static void
71qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data)
72{
73 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
74
75 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
76 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
77 NVRAM_DELAY();
78 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_CLOCK |
79 NVR_WRT_ENABLE);
80 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
81 NVRAM_DELAY();
82 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
83 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
84 NVRAM_DELAY();
85}
86
87/**
88 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
89 * NVRAM.
90 * @ha: HA context
91 * @nv_cmd: NVRAM command
92 *
93 * Bit definitions for NVRAM command:
94 *
95 * Bit 26 = start bit
96 * Bit 25, 24 = opcode
97 * Bit 23-16 = address
98 * Bit 15-0 = write data
99 *
100 * Returns the word read from nvram @addr.
101 */
102static uint16_t
103qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd)
104{
105 uint8_t cnt;
106 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
107 uint16_t data = 0;
108 uint16_t reg_data;
109
110 /* Send command to NVRAM. */
111 nv_cmd <<= 5;
112 for (cnt = 0; cnt < 11; cnt++) {
113 if (nv_cmd & BIT_31)
114 qla2x00_nv_write(ha, NVR_DATA_OUT);
115 else
116 qla2x00_nv_write(ha, 0);
117 nv_cmd <<= 1;
118 }
119
120 /* Read data from NVRAM. */
121 for (cnt = 0; cnt < 16; cnt++) {
122 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
123 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
124 NVRAM_DELAY();
125 data <<= 1;
126 reg_data = RD_REG_WORD(&reg->nvram);
127 if (reg_data & NVR_DATA_IN)
128 data |= BIT_0;
129 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
130 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
131 NVRAM_DELAY();
132 }
133
134 /* Deselect chip. */
135 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
136 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
137 NVRAM_DELAY();
138
139 return data;
140}
141
142
1da177e4
LT		 143/**
144 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
145 * request routine to get the word from NVRAM.
146 * @ha: HA context
147 * @addr: Address in NVRAM to read
148 *
149 * Returns the word read from nvram @addr.
150 */
a824ebb3 151static uint16_t
7b867cf7 152qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr)
1da177e4
LT		 153{
154 uint16_t data;
155 uint32_t nv_cmd;
156
157 nv_cmd = addr << 16;
158 nv_cmd |= NV_READ_OP;
159 data = qla2x00_nvram_request(ha, nv_cmd);
160
161 return (data);
162}
163
7b867cf7
AC		 164/**
165 * qla2x00_nv_deselect() - Deselect NVRAM operations.
166 * @ha: HA context
167 */
168static void
169qla2x00_nv_deselect(struct qla_hw_data *ha)
170{
171 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
172
173 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
174 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
175 NVRAM_DELAY();
176}
177
1da177e4
LT		 178/**
179 * qla2x00_write_nvram_word() - Write NVRAM data.
180 * @ha: HA context
181 * @addr: Address in NVRAM to write
182 * @data: word to program
183 */
a824ebb3 184static void
7b867cf7 185qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data)
1da177e4
LT		 186{
187 int count;
188 uint16_t word;
45aeaf1e 189 uint32_t nv_cmd, wait_cnt;
3d71644c 190 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 191
192 qla2x00_nv_write(ha, NVR_DATA_OUT);
193 qla2x00_nv_write(ha, 0);
194 qla2x00_nv_write(ha, 0);
195
196 for (word = 0; word < 8; word++)
197 qla2x00_nv_write(ha, NVR_DATA_OUT);
198
199 qla2x00_nv_deselect(ha);
200
201 /* Write data */
202 nv_cmd = (addr << 16) | NV_WRITE_OP;
203 nv_cmd |= data;
204 nv_cmd <<= 5;
205 for (count = 0; count < 27; count++) {
206 if (nv_cmd & BIT_31)
207 qla2x00_nv_write(ha, NVR_DATA_OUT);
208 else
209 qla2x00_nv_write(ha, 0);
210
211 nv_cmd <<= 1;
212 }
213
214 qla2x00_nv_deselect(ha);
215
216 /* Wait for NVRAM to become ready */
217 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 218 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
45aeaf1e 219 wait_cnt = NVR_WAIT_CNT;
1da177e4 220 do {
45aeaf1e
RA		 221 if (!--wait_cnt) {
222 DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
7b867cf7 223 __func__, vha->host_no));
45aeaf1e
RA		 224 break;
225 }
1da177e4
LT		 226 NVRAM_DELAY();
227 word = RD_REG_WORD(&reg->nvram);
228 } while ((word & NVR_DATA_IN) == 0);
229
230 qla2x00_nv_deselect(ha);
231
232 /* Disable writes */
233 qla2x00_nv_write(ha, NVR_DATA_OUT);
234 for (count = 0; count < 10; count++)
235 qla2x00_nv_write(ha, 0);
236
237 qla2x00_nv_deselect(ha);
238}
239
459c5378 240static int
7b867cf7
AC		 241qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr,
242 uint16_t data, uint32_t tmo)
459c5378
AV		 243{
244 int ret, count;
245 uint16_t word;
246 uint32_t nv_cmd;
247 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
248
249 ret = QLA_SUCCESS;
250
251 qla2x00_nv_write(ha, NVR_DATA_OUT);
252 qla2x00_nv_write(ha, 0);
253 qla2x00_nv_write(ha, 0);
254
255 for (word = 0; word < 8; word++)
256 qla2x00_nv_write(ha, NVR_DATA_OUT);
257
258 qla2x00_nv_deselect(ha);
259
260 /* Write data */
261 nv_cmd = (addr << 16) | NV_WRITE_OP;
262 nv_cmd |= data;
263 nv_cmd <<= 5;
264 for (count = 0; count < 27; count++) {
265 if (nv_cmd & BIT_31)
266 qla2x00_nv_write(ha, NVR_DATA_OUT);
267 else
268 qla2x00_nv_write(ha, 0);
269
270 nv_cmd <<= 1;
271 }
272
273 qla2x00_nv_deselect(ha);
274
275 /* Wait for NVRAM to become ready */
276 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 277 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
459c5378
AV		 278 do {
279 NVRAM_DELAY();
280 word = RD_REG_WORD(&reg->nvram);
281 if (!--tmo) {
282 ret = QLA_FUNCTION_FAILED;
283 break;
284 }
285 } while ((word & NVR_DATA_IN) == 0);
286
287 qla2x00_nv_deselect(ha);
288
289 /* Disable writes */
290 qla2x00_nv_write(ha, NVR_DATA_OUT);
291 for (count = 0; count < 10; count++)
292 qla2x00_nv_write(ha, 0);
293
294 qla2x00_nv_deselect(ha);
295
296 return ret;
297}
298
459c5378
AV		 299/**
300 * qla2x00_clear_nvram_protection() -
301 * @ha: HA context
302 */
303static int
7b867cf7 304qla2x00_clear_nvram_protection(struct qla_hw_data *ha)
459c5378
AV		 305{
306 int ret, stat;
307 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
45aeaf1e 308 uint32_t word, wait_cnt;
459c5378
AV		 309 uint16_t wprot, wprot_old;
310
311 /* Clear NVRAM write protection. */
312 ret = QLA_FUNCTION_FAILED;
45aeaf1e
RA		 313
314 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
315 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
459c5378 316 __constant_cpu_to_le16(0x1234), 100000);
45aeaf1e
RA		 317 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
318 if (stat != QLA_SUCCESS || wprot != 0x1234) {
459c5378
AV		 319 /* Write enable. */
320 qla2x00_nv_write(ha, NVR_DATA_OUT);
321 qla2x00_nv_write(ha, 0);
322 qla2x00_nv_write(ha, 0);
323 for (word = 0; word < 8; word++)
324 qla2x00_nv_write(ha, NVR_DATA_OUT);
325
326 qla2x00_nv_deselect(ha);
327
328 /* Enable protection register. */
329 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
330 qla2x00_nv_write(ha, NVR_PR_ENABLE);
331 qla2x00_nv_write(ha, NVR_PR_ENABLE);
332 for (word = 0; word < 8; word++)
333 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
334
335 qla2x00_nv_deselect(ha);
336
337 /* Clear protection register (ffff is cleared). */
338 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
339 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
340 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
341 for (word = 0; word < 8; word++)
342 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
343
344 qla2x00_nv_deselect(ha);
345
346 /* Wait for NVRAM to become ready. */
347 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 348 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
45aeaf1e 349 wait_cnt = NVR_WAIT_CNT;
459c5378 350 do {
45aeaf1e 351 if (!--wait_cnt) {
7b867cf7
AC		 352 DEBUG9_10(qla_printk(
353 "NVRAM didn't go ready...\n"));
45aeaf1e
RA		 354 break;
355 }
459c5378
AV		 356 NVRAM_DELAY();
357 word = RD_REG_WORD(&reg->nvram);
358 } while ((word & NVR_DATA_IN) == 0);
359
45aeaf1e
RA		 360 if (wait_cnt)
361 ret = QLA_SUCCESS;
459c5378 362 } else
45aeaf1e 363 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
459c5378
AV		 364
365 return ret;
366}
367
368static void
7b867cf7 369qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat)
459c5378
AV		 370{
371 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
45aeaf1e 372 uint32_t word, wait_cnt;
459c5378
AV		 373
374 if (stat != QLA_SUCCESS)
375 return;
376
377 /* Set NVRAM write protection. */
378 /* Write enable. */
379 qla2x00_nv_write(ha, NVR_DATA_OUT);
380 qla2x00_nv_write(ha, 0);
381 qla2x00_nv_write(ha, 0);
382 for (word = 0; word < 8; word++)
383 qla2x00_nv_write(ha, NVR_DATA_OUT);
384
385 qla2x00_nv_deselect(ha);
386
387 /* Enable protection register. */
388 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
389 qla2x00_nv_write(ha, NVR_PR_ENABLE);
390 qla2x00_nv_write(ha, NVR_PR_ENABLE);
391 for (word = 0; word < 8; word++)
392 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
393
394 qla2x00_nv_deselect(ha);
395
396 /* Enable protection register. */
397 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
398 qla2x00_nv_write(ha, NVR_PR_ENABLE);
399 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
400 for (word = 0; word < 8; word++)
401 qla2x00_nv_write(ha, NVR_PR_ENABLE);
402
403 qla2x00_nv_deselect(ha);
404
405 /* Wait for NVRAM to become ready. */
406 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 407 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
45aeaf1e 408 wait_cnt = NVR_WAIT_CNT;
459c5378 409 do {
45aeaf1e 410 if (!--wait_cnt) {
7b867cf7 411 DEBUG9_10(qla_printk("NVRAM didn't go ready...\n"));
45aeaf1e
RA		 412 break;
413 }
459c5378
AV		 414 NVRAM_DELAY();
415 word = RD_REG_WORD(&reg->nvram);
416 } while ((word & NVR_DATA_IN) == 0);
417}
418
419
420/*****************************************************************************/
421/* Flash Manipulation Routines */
422/*****************************************************************************/
423
338c9161
AV		 424#define OPTROM_BURST_SIZE 0x1000
425#define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
426
459c5378 427static inline uint32_t
3a03eb79 428flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr)
459c5378 429{
3a03eb79 430 return ha->flash_conf_off | faddr;
459c5378
AV		 431}
432
433static inline uint32_t
3a03eb79 434flash_data_addr(struct qla_hw_data *ha, uint32_t faddr)
459c5378 435{
3a03eb79 436 return ha->flash_data_off | faddr;
459c5378
AV		 437}
438
439static inline uint32_t
3a03eb79 440nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr)
459c5378 441{
3a03eb79 442 return ha->nvram_conf_off | naddr;
459c5378
AV		 443}
444
445static inline uint32_t
3a03eb79 446nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr)
459c5378 447{
3a03eb79 448 return ha->nvram_data_off | naddr;
459c5378
AV		 449}
450
e5f82ab8 451static uint32_t
7b867cf7 452qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr)
459c5378
AV		 453{
454 int rval;
455 uint32_t cnt, data;
456 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
457
458 WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
459 /* Wait for READ cycle to complete. */
460 rval = QLA_SUCCESS;
461 for (cnt = 3000;
462 (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
463 rval == QLA_SUCCESS; cnt--) {
464 if (cnt)
465 udelay(10);
466 else
467 rval = QLA_FUNCTION_TIMEOUT;
40a2e34a 468 cond_resched();
459c5378
AV		 469 }
470
471 /* TODO: What happens if we time out? */
472 data = 0xDEADDEAD;
473 if (rval == QLA_SUCCESS)
474 data = RD_REG_DWORD(&reg->flash_data);
475
476 return data;
477}
478
479uint32_t *
7b867cf7 480qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
459c5378
AV		 481 uint32_t dwords)
482{
483 uint32_t i;
3a03eb79
AV		 484 struct qla_hw_data *ha = vha->hw;
485
459c5378
AV		 486 /* Dword reads to flash. */
487 for (i = 0; i < dwords; i++, faddr++)
3a03eb79
AV		 488 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
489 flash_data_addr(ha, faddr)));
459c5378 490
459c5378
AV		 491 return dwptr;
492}
493
e5f82ab8 494static int
7b867cf7 495qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data)
459c5378
AV		 496{
497 int rval;
498 uint32_t cnt;
499 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
500
501 WRT_REG_DWORD(&reg->flash_data, data);
502 RD_REG_DWORD(&reg->flash_data); /* PCI Posting. */
503 WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
504 /* Wait for Write cycle to complete. */
505 rval = QLA_SUCCESS;
506 for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
507 rval == QLA_SUCCESS; cnt--) {
508 if (cnt)
509 udelay(10);
510 else
511 rval = QLA_FUNCTION_TIMEOUT;
40a2e34a 512 cond_resched();
459c5378
AV		 513 }
514 return rval;
515}
516
e5f82ab8 517static void
7b867cf7 518qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
459c5378
AV		 519 uint8_t *flash_id)
520{
521 uint32_t ids;
522
3a03eb79 523 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x03ab));
459c5378
AV		 524 *man_id = LSB(ids);
525 *flash_id = MSB(ids);
45aeaf1e
RA		 526
527 /* Check if man_id and flash_id are valid. */
528 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
529 /* Read information using 0x9f opcode
530 * Device ID, Mfg ID would be read in the format:
531 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
532 * Example: ATMEL 0x00 01 45 1F
533 * Extract MFG and Dev ID from last two bytes.
534 */
3a03eb79 535 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x009f));
45aeaf1e
RA		 536 *man_id = LSB(ids);
537 *flash_id = MSB(ids);
538 }
459c5378
AV		 539}
540
c00d8994 541static int
7b867cf7 542qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
c00d8994
AV		 543{
544 const char *loc, *locations[] = { "DEF", "PCI" };
545 uint32_t pcihdr, pcids;
546 uint32_t *dcode;
547 uint8_t *buf, *bcode, last_image;
548 uint16_t cnt, chksum, *wptr;
549 struct qla_flt_location *fltl;
7b867cf7 550 struct qla_hw_data *ha = vha->hw;
73208dfd 551 struct req_que *req = ha->req_q_map[0];
c00d8994
AV		 552
553 /*
554 * FLT-location structure resides after the last PCI region.
555 */
556
557 /* Begin with sane defaults. */
558 loc = locations[0];
3a03eb79
AV		 559 *start = 0;
560 if (IS_QLA24XX_TYPE(ha))
561 *start = FA_FLASH_LAYOUT_ADDR_24;
562 else if (IS_QLA25XX(ha))
563 *start = FA_FLASH_LAYOUT_ADDR;
564 else if (IS_QLA81XX(ha))
565 *start = FA_FLASH_LAYOUT_ADDR_81;
c00d8994 566 /* Begin with first PCI expansion ROM header. */
7b867cf7
AC		 567 buf = (uint8_t *)req->ring;
568 dcode = (uint32_t *)req->ring;
c00d8994
AV		 569 pcihdr = 0;
570 last_image = 1;
571 do {
572 /* Verify PCI expansion ROM header. */
7b867cf7 573 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
c00d8994
AV		 574 bcode = buf + (pcihdr % 4);
575 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa)
576 goto end;
577
578 /* Locate PCI data structure. */
579 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
7b867cf7 580 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
c00d8994
AV		 581 bcode = buf + (pcihdr % 4);
582
583 /* Validate signature of PCI data structure. */
584 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
585 bcode[0x2] != 'I' || bcode[0x3] != 'R')
586 goto end;
587
588 last_image = bcode[0x15] & BIT_7;
589
590 /* Locate next PCI expansion ROM. */
591 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
592 } while (!last_image);
593
594 /* Now verify FLT-location structure. */
7b867cf7
AC		 595 fltl = (struct qla_flt_location *)req->ring;
596 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2,
c00d8994
AV		 597 sizeof(struct qla_flt_location) >> 2);
598 if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' ||
599 fltl->sig[2] != 'L' || fltl->sig[3] != 'T')
600 goto end;
601
7b867cf7 602 wptr = (uint16_t *)req->ring;
c00d8994
AV		 603 cnt = sizeof(struct qla_flt_location) >> 1;
604 for (chksum = 0; cnt; cnt--)
605 chksum += le16_to_cpu(*wptr++);
606 if (chksum) {
607 qla_printk(KERN_ERR, ha,
608 "Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
609 qla2x00_dump_buffer(buf, sizeof(struct qla_flt_location));
610 return QLA_FUNCTION_FAILED;
611 }
612
613 /* Good data. Use specified location. */
614 loc = locations[1];
615 *start = le16_to_cpu(fltl->start_hi) << 16 |
616 le16_to_cpu(fltl->start_lo);
617end:
618 DEBUG2(qla_printk(KERN_DEBUG, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
619 return QLA_SUCCESS;
620}
621
622static void
7b867cf7 623qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
c00d8994
AV		 624{
625 const char *loc, *locations[] = { "DEF", "FLT" };
3a03eb79
AV		 626 const uint32_t def_fw[] =
627 { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 };
628 const uint32_t def_boot[] =
629 { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 };
630 const uint32_t def_vpd_nvram[] =
631 { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 };
632 const uint32_t def_fdt[] =
633 { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR,
634 FA_FLASH_DESCR_ADDR_81 };
635 const uint32_t def_npiv_conf0[] =
636 { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR,
637 FA_NPIV_CONF0_ADDR_81 };
638 const uint32_t def_npiv_conf1[] =
639 { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR,
640 FA_NPIV_CONF1_ADDR_81 };
641 uint32_t def;
c00d8994
AV		 642 uint16_t *wptr;
643 uint16_t cnt, chksum;
644 uint32_t start;
645 struct qla_flt_header *flt;
646 struct qla_flt_region *region;
7b867cf7 647 struct qla_hw_data *ha = vha->hw;
73208dfd 648 struct req_que *req = ha->req_q_map[0];
c00d8994
AV		 649
650 ha->flt_region_flt = flt_addr;
7b867cf7
AC		 651 wptr = (uint16_t *)req->ring;
652 flt = (struct qla_flt_header *)req->ring;
c00d8994 653 region = (struct qla_flt_region *)&flt[1];
7b867cf7 654 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
c00d8994
AV		 655 flt_addr << 2, OPTROM_BURST_SIZE);
656 if (*wptr == __constant_cpu_to_le16(0xffff))
657 goto no_flash_data;
658 if (flt->version != __constant_cpu_to_le16(1)) {
659 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported FLT detected: "
660 "version=0x%x length=0x%x checksum=0x%x.\n",
661 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
662 le16_to_cpu(flt->checksum)));
663 goto no_flash_data;
664 }
665
666 cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
667 for (chksum = 0; cnt; cnt--)
668 chksum += le16_to_cpu(*wptr++);
669 if (chksum) {
670 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
671 "version=0x%x length=0x%x checksum=0x%x.\n",
672 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
673 chksum));
674 goto no_flash_data;
675 }
676
677 loc = locations[1];
678 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
679 for ( ; cnt; cnt--, region++) {
680 /* Store addresses as DWORD offsets. */
681 start = le32_to_cpu(region->start) >> 2;
682
683 DEBUG3(qla_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
684 "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
685 le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
686
687 switch (le32_to_cpu(region->code)) {
688 case FLT_REG_FW:
689 ha->flt_region_fw = start;
690 break;
691 case FLT_REG_BOOT_CODE:
692 ha->flt_region_boot = start;
693 break;
694 case FLT_REG_VPD_0:
695 ha->flt_region_vpd_nvram = start;
696 break;
697 case FLT_REG_FDT:
698 ha->flt_region_fdt = start;
699 break;
272976ca 700 case FLT_REG_NPIV_CONF_0:
3a03eb79 701 if (!(PCI_FUNC(ha->pdev->devfn) & 1))
272976ca
AV		 702 ha->flt_region_npiv_conf = start;
703 break;
704 case FLT_REG_NPIV_CONF_1:
3a03eb79 705 if (PCI_FUNC(ha->pdev->devfn) & 1)
272976ca
AV		 706 ha->flt_region_npiv_conf = start;
707 break;
c00d8994
AV		 708 }
709 }
710 goto done;
711
712no_flash_data:
713 /* Use hardcoded defaults. */
714 loc = locations[0];
3a03eb79
AV		 715 def = 0;
716 if (IS_QLA24XX_TYPE(ha))
717 def = 0;
718 else if (IS_QLA25XX(ha))
719 def = 1;
720 else if (IS_QLA81XX(ha))
721 def = 2;
722 ha->flt_region_fw = def_fw[def];
723 ha->flt_region_boot = def_boot[def];
724 ha->flt_region_vpd_nvram = def_vpd_nvram[def];
725 ha->flt_region_fdt = def_fdt[def];
726 ha->flt_region_npiv_conf = !(PCI_FUNC(ha->pdev->devfn) & 1) ?
727 def_npiv_conf0[def]: def_npiv_conf1[def];
c00d8994
AV		 728done:
729 DEBUG2(qla_printk(KERN_DEBUG, ha, "FLT[%s]: boot=0x%x fw=0x%x "
1ded85e2 730 "vpd_nvram=0x%x fdt=0x%x flt=0x%x npiv=0x%x.\n", loc,
c00d8994 731 ha->flt_region_boot, ha->flt_region_fw, ha->flt_region_vpd_nvram,
1ded85e2 732 ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf));
c00d8994
AV		 733}
734
735static void
7b867cf7 736qla2xxx_get_fdt_info(scsi_qla_host_t *vha)
7d232c74 737{
821b3996 738#define FLASH_BLK_SIZE_4K 0x1000
7d232c74
AV		 739#define FLASH_BLK_SIZE_32K 0x8000
740#define FLASH_BLK_SIZE_64K 0x10000
c00d8994 741 const char *loc, *locations[] = { "MID", "FDT" };
7d232c74
AV		 742 uint16_t cnt, chksum;
743 uint16_t *wptr;
744 struct qla_fdt_layout *fdt;
745 uint8_t man_id, flash_id;
c00d8994 746 uint16_t mid, fid;
7b867cf7 747 struct qla_hw_data *ha = vha->hw;
73208dfd 748 struct req_que *req = ha->req_q_map[0];
7d232c74 749
7b867cf7
AC		 750 wptr = (uint16_t *)req->ring;
751 fdt = (struct qla_fdt_layout *)req->ring;
752 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
c00d8994 753 ha->flt_region_fdt << 2, OPTROM_BURST_SIZE);
7d232c74
AV		 754 if (*wptr == __constant_cpu_to_le16(0xffff))
755 goto no_flash_data;
756 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
757 fdt->sig[3] != 'D')
758 goto no_flash_data;
759
760 for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
761 cnt++)
762 chksum += le16_to_cpu(*wptr++);
763 if (chksum) {
764 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
765 "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
766 le16_to_cpu(fdt->version)));
767 DEBUG9(qla2x00_dump_buffer((uint8_t *)fdt, sizeof(*fdt)));
768 goto no_flash_data;
769 }
770
c00d8994
AV		 771 loc = locations[1];
772 mid = le16_to_cpu(fdt->man_id);
773 fid = le16_to_cpu(fdt->id);
7d232c74 774 ha->fdt_wrt_disable = fdt->wrt_disable_bits;
3a03eb79 775 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0300 | fdt->erase_cmd);
7d232c74
AV		 776 ha->fdt_block_size = le32_to_cpu(fdt->block_size);
777 if (fdt->unprotect_sec_cmd) {
3a03eb79 778 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 |
7d232c74
AV		 779 fdt->unprotect_sec_cmd);
780 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
3a03eb79
AV		 781 flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd):
782 flash_conf_addr(ha, 0x0336);
7d232c74 783 }
c00d8994 784 goto done;
7d232c74 785no_flash_data:
c00d8994 786 loc = locations[0];
7d232c74 787 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
c00d8994
AV		 788 mid = man_id;
789 fid = flash_id;
7d232c74 790 ha->fdt_wrt_disable = 0x9c;
3a03eb79 791 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8);
7d232c74
AV		 792 switch (man_id) {
793 case 0xbf: /* STT flash. */
794 if (flash_id == 0x8e)
795 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
796 else
797 ha->fdt_block_size = FLASH_BLK_SIZE_32K;
798
799 if (flash_id == 0x80)
3a03eb79 800 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352);
7d232c74
AV		 801 break;
802 case 0x13: /* ST M25P80. */
803 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
804 break;
805 case 0x1f: /* Atmel 26DF081A. */
821b3996 806 ha->fdt_block_size = FLASH_BLK_SIZE_4K;
3a03eb79
AV		 807 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320);
808 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339);
809 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336);
7d232c74
AV		 810 break;
811 default:
812 /* Default to 64 kb sector size. */
813 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
814 break;
815 }
c00d8994
AV		 816done:
817 DEBUG2(qla_printk(KERN_DEBUG, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
821b3996 818 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
7d232c74 819 ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
821b3996 820 ha->fdt_unprotect_sec_cmd, ha->fdt_wrt_disable,
7d232c74
AV		 821 ha->fdt_block_size));
822}
823
c00d8994 824int
7b867cf7 825qla2xxx_get_flash_info(scsi_qla_host_t *vha)
c00d8994
AV		 826{
827 int ret;
828 uint32_t flt_addr;
7b867cf7 829 struct qla_hw_data *ha = vha->hw;
c00d8994 830
3a03eb79 831 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA81XX(ha))
c00d8994
AV		 832 return QLA_SUCCESS;
833
7b867cf7 834 ret = qla2xxx_find_flt_start(vha, &flt_addr);
c00d8994
AV		 835 if (ret != QLA_SUCCESS)
836 return ret;
837
7b867cf7
AC		 838 qla2xxx_get_flt_info(vha, flt_addr);
839 qla2xxx_get_fdt_info(vha);
c00d8994
AV		 840
841 return QLA_SUCCESS;
842}
843
272976ca 844void
7b867cf7 845qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
272976ca
AV		 846{
847#define NPIV_CONFIG_SIZE (16*1024)
848 void *data;
849 uint16_t *wptr;
850 uint16_t cnt, chksum;
73208dfd 851 int i;
272976ca
AV		 852 struct qla_npiv_header hdr;
853 struct qla_npiv_entry *entry;
7b867cf7 854 struct qla_hw_data *ha = vha->hw;
272976ca 855
3a03eb79 856 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA81XX(ha))
272976ca
AV		 857 return;
858
7b867cf7 859 ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr,
272976ca
AV		 860 ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header));
861 if (hdr.version == __constant_cpu_to_le16(0xffff))
862 return;
863 if (hdr.version != __constant_cpu_to_le16(1)) {
864 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported NPIV-Config "
865 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
866 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
867 le16_to_cpu(hdr.checksum)));
868 return;
869 }
870
871 data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL);
872 if (!data) {
873 DEBUG2(qla_printk(KERN_INFO, ha, "NPIV-Config: Unable to "
874 "allocate memory.\n"));
875 return;
876 }
877
7b867cf7 878 ha->isp_ops->read_optrom(vha, (uint8_t *)data,
272976ca
AV		 879 ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE);
880
881 cnt = (sizeof(struct qla_npiv_header) + le16_to_cpu(hdr.entries) *
882 sizeof(struct qla_npiv_entry)) >> 1;
883 for (wptr = data, chksum = 0; cnt; cnt--)
884 chksum += le16_to_cpu(*wptr++);
885 if (chksum) {
886 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent NPIV-Config "
887 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
888 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
889 chksum));
890 goto done;
891 }
892
893 entry = data + sizeof(struct qla_npiv_header);
894 cnt = le16_to_cpu(hdr.entries);
73208dfd 895 for (i = 0; cnt; cnt--, entry++, i++) {
272976ca
AV		 896 uint16_t flags;
897 struct fc_vport_identifiers vid;
898 struct fc_vport *vport;
899
900 flags = le16_to_cpu(entry->flags);
901 if (flags == 0xffff)
902 continue;
903 if ((flags & BIT_0) == 0)
904 continue;
905
906 memset(&vid, 0, sizeof(vid));
907 vid.roles = FC_PORT_ROLE_FCP_INITIATOR;
908 vid.vport_type = FC_PORTTYPE_NPIV;
909 vid.disable = false;
910 vid.port_name = wwn_to_u64(entry->port_name);
911 vid.node_name = wwn_to_u64(entry->node_name);
912
73208dfd
AC		 913 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry));
914
272976ca 915 DEBUG2(qla_printk(KERN_DEBUG, ha, "NPIV[%02x]: wwpn=%llx "
73208dfd
AC		 916 "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt,
917 vid.port_name, vid.node_name, le16_to_cpu(entry->vf_id),
918 entry->q_qos, entry->f_qos));
919
920 if (i < QLA_PRECONFIG_VPORTS) {
921 vport = fc_vport_create(vha->host, 0, &vid);
922 if (!vport)
923 qla_printk(KERN_INFO, ha,
924 "NPIV-Config: Failed to create vport [%02x]: "
925 "wwpn=%llx wwnn=%llx.\n", cnt,
926 vid.port_name, vid.node_name);
927 }
272976ca
AV		 928 }
929done:
930 kfree(data);
73208dfd 931 ha->npiv_info = NULL;
272976ca
AV		 932}
933
cb8dacbf 934static void
7b867cf7 935qla24xx_unprotect_flash(struct qla_hw_data *ha)
cb8dacbf
AV		 936{
937 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
938
939 /* Enable flash write. */
940 WRT_REG_DWORD(&reg->ctrl_status,
941 RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
942 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
943
7d232c74
AV		 944 if (!ha->fdt_wrt_disable)
945 return;
946
cb8dacbf 947 /* Disable flash write-protection. */
3a03eb79 948 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
cb8dacbf 949 /* Some flash parts need an additional zero-write to clear bits.*/
3a03eb79 950 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
cb8dacbf
AV		 951}
952
953static void
7b867cf7 954qla24xx_protect_flash(struct qla_hw_data *ha)
cb8dacbf
AV		 955{
956 uint32_t cnt;
957 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
958
7d232c74
AV		 959 if (!ha->fdt_wrt_disable)
960 goto skip_wrt_protect;
961
cb8dacbf 962 /* Enable flash write-protection and wait for completion. */
3a03eb79 963 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101),
7d232c74 964 ha->fdt_wrt_disable);
cb8dacbf 965 for (cnt = 300; cnt &&
3a03eb79 966 qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x005)) & BIT_0;
cb8dacbf
AV		 967 cnt--) {
968 udelay(10);
969 }
970
7d232c74 971skip_wrt_protect:
cb8dacbf
AV		 972 /* Disable flash write. */
973 WRT_REG_DWORD(&reg->ctrl_status,
974 RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
975 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
976}
977
e5f82ab8 978static int
7b867cf7 979qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
459c5378
AV		 980 uint32_t dwords)
981{
982 int ret;
338c9161 983 uint32_t liter, miter;
7d232c74 984 uint32_t sec_mask, rest_addr;
85d0acbb 985 uint32_t fdata;
338c9161
AV		 986 dma_addr_t optrom_dma;
987 void *optrom = NULL;
988 uint32_t *s, *d;
7b867cf7 989 struct qla_hw_data *ha = vha->hw;
459c5378
AV		 990
991 ret = QLA_SUCCESS;
992
338c9161 993 /* Prepare burst-capable write on supported ISPs. */
3a03eb79 994 if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && !(faddr & 0xfff) &&
338c9161
AV		 995 dwords > OPTROM_BURST_DWORDS) {
996 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
997 &optrom_dma, GFP_KERNEL);
998 if (!optrom) {
999 qla_printk(KERN_DEBUG, ha,
1000 "Unable to allocate memory for optrom burst write "
1001 "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
1002 }
1003 }
1004
7d232c74 1005 rest_addr = (ha->fdt_block_size >> 2) - 1;
85d0acbb 1006 sec_mask = ~rest_addr;
459c5378 1007
cb8dacbf 1008 qla24xx_unprotect_flash(ha);
459c5378 1009
338c9161 1010 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
85d0acbb 1011 fdata = (faddr & sec_mask) << 2;
45aeaf1e 1012
338c9161 1013 /* Are we at the beginning of a sector? */
85d0acbb 1014 if ((faddr & rest_addr) == 0) {
7d232c74
AV		 1015 /* Do sector unprotect. */
1016 if (ha->fdt_unprotect_sec_cmd)
338c9161 1017 qla24xx_write_flash_dword(ha,
7d232c74 1018 ha->fdt_unprotect_sec_cmd,
338c9161 1019 (fdata & 0xff00) | ((fdata << 16) &
459c5378 1020 0xff0000) | ((fdata >> 16) & 0xff));
7d232c74 1021 ret = qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd,
338c9161
AV		 1022 (fdata & 0xff00) |((fdata << 16) &
1023 0xff0000) | ((fdata >> 16) & 0xff));
1024 if (ret != QLA_SUCCESS) {
7b867cf7
AC		 1025 DEBUG9(qla_printk("Unable to flash sector: "
1026 "address=%x.\n", faddr));
338c9161 1027 break;
459c5378 1028 }
338c9161
AV		 1029 }
1030
1031 /* Go with burst-write. */
94d6a2b3 1032 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
338c9161
AV		 1033 /* Copy data to DMA'ble buffer. */
1034 for (miter = 0, s = optrom, d = dwptr;
1035 miter < OPTROM_BURST_DWORDS; miter++, s++, d++)
1036 *s = cpu_to_le32(*d);
1037
7b867cf7 1038 ret = qla2x00_load_ram(vha, optrom_dma,
3a03eb79 1039 flash_data_addr(ha, faddr),
338c9161 1040 OPTROM_BURST_DWORDS);
459c5378 1041 if (ret != QLA_SUCCESS) {
338c9161
AV		 1042 qla_printk(KERN_WARNING, ha,
1043 "Unable to burst-write optrom segment "
1044 "(%x/%x/%llx).\n", ret,
3a03eb79 1045 flash_data_addr(ha, faddr),
875baf3c 1046 (unsigned long long)optrom_dma);
338c9161
AV		 1047 qla_printk(KERN_WARNING, ha,
1048 "Reverting to slow-write.\n");
1049
1050 dma_free_coherent(&ha->pdev->dev,
1051 OPTROM_BURST_SIZE, optrom, optrom_dma);
1052 optrom = NULL;
1053 } else {
1054 liter += OPTROM_BURST_DWORDS - 1;
1055 faddr += OPTROM_BURST_DWORDS - 1;
1056 dwptr += OPTROM_BURST_DWORDS - 1;
1057 continue;
459c5378 1058 }
338c9161 1059 }
45aeaf1e 1060
338c9161 1061 ret = qla24xx_write_flash_dword(ha,
3a03eb79 1062 flash_data_addr(ha, faddr), cpu_to_le32(*dwptr));
338c9161
AV		 1063 if (ret != QLA_SUCCESS) {
1064 DEBUG9(printk("%s(%ld) Unable to program flash "
1065 "address=%x data=%x.\n", __func__,
7b867cf7 1066 vha->host_no, faddr, *dwptr));
338c9161 1067 break;
459c5378 1068 }
338c9161 1069
7d232c74
AV		 1070 /* Do sector protect. */
1071 if (ha->fdt_unprotect_sec_cmd &&
338c9161
AV		 1072 ((faddr & rest_addr) == rest_addr))
1073 qla24xx_write_flash_dword(ha,
7d232c74 1074 ha->fdt_protect_sec_cmd,
338c9161
AV		 1075 (fdata & 0xff00) | ((fdata << 16) &
1076 0xff0000) | ((fdata >> 16) & 0xff));
1077 }
459c5378 1078
cb8dacbf 1079 qla24xx_protect_flash(ha);
459c5378 1080
338c9161
AV		 1081 if (optrom)
1082 dma_free_coherent(&ha->pdev->dev,
1083 OPTROM_BURST_SIZE, optrom, optrom_dma);
1084
459c5378
AV		 1085 return ret;
1086}
1087
1088uint8_t *
7b867cf7 1089qla2x00_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
459c5378
AV		 1090 uint32_t bytes)
1091{
1092 uint32_t i;
1093 uint16_t *wptr;
7b867cf7 1094 struct qla_hw_data *ha = vha->hw;
459c5378
AV		 1095
1096 /* Word reads to NVRAM via registers. */
1097 wptr = (uint16_t *)buf;
1098 qla2x00_lock_nvram_access(ha);
1099 for (i = 0; i < bytes >> 1; i++, naddr++)
1100 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
1101 naddr));
1102 qla2x00_unlock_nvram_access(ha);
1103
1104 return buf;
1105}
1106
1107uint8_t *
7b867cf7 1108qla24xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
459c5378
AV		 1109 uint32_t bytes)
1110{
1111 uint32_t i;
1112 uint32_t *dwptr;
3a03eb79 1113 struct qla_hw_data *ha = vha->hw;
459c5378
AV		 1114
1115 /* Dword reads to flash. */
1116 dwptr = (uint32_t *)buf;
1117 for (i = 0; i < bytes >> 2; i++, naddr++)
3a03eb79
AV		 1118 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1119 nvram_data_addr(ha, naddr)));
459c5378 1120
459c5378
AV		 1121 return buf;
1122}
1123
1124int
7b867cf7 1125qla2x00_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
459c5378
AV		 1126 uint32_t bytes)
1127{
1128 int ret, stat;
1129 uint32_t i;
1130 uint16_t *wptr;
2c96d8d0 1131 unsigned long flags;
7b867cf7 1132 struct qla_hw_data *ha = vha->hw;
459c5378
AV		 1133
1134 ret = QLA_SUCCESS;
1135
2c96d8d0 1136 spin_lock_irqsave(&ha->hardware_lock, flags);
459c5378
AV		 1137 qla2x00_lock_nvram_access(ha);
1138
1139 /* Disable NVRAM write-protection. */
1140 stat = qla2x00_clear_nvram_protection(ha);
1141
1142 wptr = (uint16_t *)buf;
1143 for (i = 0; i < bytes >> 1; i++, naddr++) {
1144 qla2x00_write_nvram_word(ha, naddr,
1145 cpu_to_le16(*wptr));
1146 wptr++;
1147 }
1148
1149 /* Enable NVRAM write-protection. */
1150 qla2x00_set_nvram_protection(ha, stat);
1151
1152 qla2x00_unlock_nvram_access(ha);
2c96d8d0 1153 spin_unlock_irqrestore(&ha->hardware_lock, flags);
459c5378
AV		 1154
1155 return ret;
1156}
1157
1158int
7b867cf7 1159qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
459c5378
AV		 1160 uint32_t bytes)
1161{
1162 int ret;
1163 uint32_t i;
1164 uint32_t *dwptr;
7b867cf7 1165 struct qla_hw_data *ha = vha->hw;
459c5378
AV		 1166 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1167
1168 ret = QLA_SUCCESS;
1169
459c5378
AV		 1170 /* Enable flash write. */
1171 WRT_REG_DWORD(&reg->ctrl_status,
1172 RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1173 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1174
1175 /* Disable NVRAM write-protection. */
3a03eb79
AV		 1176 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1177 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
459c5378
AV		 1178
1179 /* Dword writes to flash. */
1180 dwptr = (uint32_t *)buf;
1181 for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
1182 ret = qla24xx_write_flash_dword(ha,
3a03eb79 1183 nvram_data_addr(ha, naddr), cpu_to_le32(*dwptr));
459c5378 1184 if (ret != QLA_SUCCESS) {
7b867cf7
AC		 1185 DEBUG9(qla_printk("Unable to program nvram address=%x "
1186 "data=%x.\n", naddr, *dwptr));
459c5378
AV		 1187 break;
1188 }
1189 }
1190
1191 /* Enable NVRAM write-protection. */
3a03eb79 1192 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c);
459c5378
AV		 1193
1194 /* Disable flash write. */
1195 WRT_REG_DWORD(&reg->ctrl_status,
1196 RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1197 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1198
459c5378
AV		 1199 return ret;
1200}
f6df144c 1201
c3a2f0df 1202uint8_t *
7b867cf7 1203qla25xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
c3a2f0df
AV		 1204 uint32_t bytes)
1205{
1206 uint32_t i;
1207 uint32_t *dwptr;
7b867cf7 1208 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 1209
1210 /* Dword reads to flash. */
1211 dwptr = (uint32_t *)buf;
1212 for (i = 0; i < bytes >> 2; i++, naddr++)
1213 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
3a03eb79 1214 flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr)));
c3a2f0df
AV		 1215
1216 return buf;
1217}
1218
1219int
7b867cf7 1220qla25xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
c3a2f0df
AV		 1221 uint32_t bytes)
1222{
7b867cf7 1223 struct qla_hw_data *ha = vha->hw;
2c96d8d0
AV		 1224#define RMW_BUFFER_SIZE (64 * 1024)
1225 uint8_t *dbuf;
1226
1227 dbuf = vmalloc(RMW_BUFFER_SIZE);
1228 if (!dbuf)
1229 return QLA_MEMORY_ALLOC_FAILED;
7b867cf7 1230 ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
2c96d8d0
AV		 1231 RMW_BUFFER_SIZE);
1232 memcpy(dbuf + (naddr << 2), buf, bytes);
7b867cf7 1233 ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
2c96d8d0
AV		 1234 RMW_BUFFER_SIZE);
1235 vfree(dbuf);
1236
1237 return QLA_SUCCESS;
c3a2f0df 1238}
f6df144c 1239
1240static inline void
7b867cf7 1241qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
f6df144c 1242{
1243 if (IS_QLA2322(ha)) {
1244 /* Flip all colors. */
1245 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1246 /* Turn off. */
1247 ha->beacon_color_state = 0;
1248 *pflags = GPIO_LED_ALL_OFF;
1249 } else {
1250 /* Turn on. */
1251 ha->beacon_color_state = QLA_LED_ALL_ON;
1252 *pflags = GPIO_LED_RGA_ON;
1253 }
1254 } else {
1255 /* Flip green led only. */
1256 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
1257 /* Turn off. */
1258 ha->beacon_color_state = 0;
1259 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
1260 } else {
1261 /* Turn on. */
1262 ha->beacon_color_state = QLA_LED_GRN_ON;
1263 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
1264 }
1265 }
1266}
1267
948882f6
AV		 1268#define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1269
f6df144c 1270void
7b867cf7 1271qla2x00_beacon_blink(struct scsi_qla_host *vha)
f6df144c 1272{
1273 uint16_t gpio_enable;
1274 uint16_t gpio_data;
1275 uint16_t led_color = 0;
1276 unsigned long flags;
7b867cf7 1277 struct qla_hw_data *ha = vha->hw;
f6df144c 1278 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1279
f6df144c 1280 spin_lock_irqsave(&ha->hardware_lock, flags);
1281
1282 /* Save the Original GPIOE. */
1283 if (ha->pio_address) {
948882f6
AV		 1284 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1285 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
f6df144c 1286 } else {
1287 gpio_enable = RD_REG_WORD(&reg->gpioe);
1288 gpio_data = RD_REG_WORD(&reg->gpiod);
1289 }
1290
1291 /* Set the modified gpio_enable values */
1292 gpio_enable |= GPIO_LED_MASK;
1293
1294 if (ha->pio_address) {
948882f6 1295 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
f6df144c 1296 } else {
1297 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1298 RD_REG_WORD(&reg->gpioe);
1299 }
1300
1301 qla2x00_flip_colors(ha, &led_color);
1302
1303 /* Clear out any previously set LED color. */
1304 gpio_data &= ~GPIO_LED_MASK;
1305
1306 /* Set the new input LED color to GPIOD. */
1307 gpio_data |= led_color;
1308
1309 /* Set the modified gpio_data values */
1310 if (ha->pio_address) {
948882f6 1311 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
f6df144c 1312 } else {
1313 WRT_REG_WORD(&reg->gpiod, gpio_data);
1314 RD_REG_WORD(&reg->gpiod);
1315 }
1316
1317 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1318}
1319
1320int
7b867cf7 1321qla2x00_beacon_on(struct scsi_qla_host *vha)
f6df144c 1322{
1323 uint16_t gpio_enable;
1324 uint16_t gpio_data;
1325 unsigned long flags;
7b867cf7 1326 struct qla_hw_data *ha = vha->hw;
f6df144c 1327 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1328
1329 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1330 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
1331
7b867cf7 1332 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
f6df144c 1333 qla_printk(KERN_WARNING, ha,
1334 "Unable to update fw options (beacon on).\n");
1335 return QLA_FUNCTION_FAILED;
1336 }
1337
f6df144c 1338 /* Turn off LEDs. */
1339 spin_lock_irqsave(&ha->hardware_lock, flags);
1340 if (ha->pio_address) {
948882f6
AV		 1341 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1342 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
f6df144c 1343 } else {
1344 gpio_enable = RD_REG_WORD(&reg->gpioe);
1345 gpio_data = RD_REG_WORD(&reg->gpiod);
1346 }
1347 gpio_enable |= GPIO_LED_MASK;
1348
1349 /* Set the modified gpio_enable values. */
1350 if (ha->pio_address) {
948882f6 1351 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
f6df144c 1352 } else {
1353 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1354 RD_REG_WORD(&reg->gpioe);
1355 }
1356
1357 /* Clear out previously set LED colour. */
1358 gpio_data &= ~GPIO_LED_MASK;
1359 if (ha->pio_address) {
948882f6 1360 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
f6df144c 1361 } else {
1362 WRT_REG_WORD(&reg->gpiod, gpio_data);
1363 RD_REG_WORD(&reg->gpiod);
1364 }
1365 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1366
1367 /*
1368 * Let the per HBA timer kick off the blinking process based on
1369 * the following flags. No need to do anything else now.
1370 */
1371 ha->beacon_blink_led = 1;
1372 ha->beacon_color_state = 0;
1373
1374 return QLA_SUCCESS;
1375}
1376
1377int
7b867cf7 1378qla2x00_beacon_off(struct scsi_qla_host *vha)
f6df144c 1379{
1380 int rval = QLA_SUCCESS;
7b867cf7 1381 struct qla_hw_data *ha = vha->hw;
f6df144c 1382
1383 ha->beacon_blink_led = 0;
1384
1385 /* Set the on flag so when it gets flipped it will be off. */
1386 if (IS_QLA2322(ha))
1387 ha->beacon_color_state = QLA_LED_ALL_ON;
1388 else
1389 ha->beacon_color_state = QLA_LED_GRN_ON;
1390
7b867cf7 1391 ha->isp_ops->beacon_blink(vha); /* This turns green LED off */
f6df144c 1392
1393 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1394 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1395
7b867cf7 1396 rval = qla2x00_set_fw_options(vha, ha->fw_options);
f6df144c 1397 if (rval != QLA_SUCCESS)
1398 qla_printk(KERN_WARNING, ha,
1399 "Unable to update fw options (beacon off).\n");
1400 return rval;
1401}
1402
1403
1404static inline void
7b867cf7 1405qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
f6df144c 1406{
1407 /* Flip all colors. */
1408 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1409 /* Turn off. */
1410 ha->beacon_color_state = 0;
1411 *pflags = 0;
1412 } else {
1413 /* Turn on. */
1414 ha->beacon_color_state = QLA_LED_ALL_ON;
1415 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1416 }
1417}
1418
1419void
7b867cf7 1420qla24xx_beacon_blink(struct scsi_qla_host *vha)
f6df144c 1421{
1422 uint16_t led_color = 0;
1423 uint32_t gpio_data;
1424 unsigned long flags;
7b867cf7 1425 struct qla_hw_data *ha = vha->hw;
f6df144c 1426 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1427
1428 /* Save the Original GPIOD. */
1429 spin_lock_irqsave(&ha->hardware_lock, flags);
1430 gpio_data = RD_REG_DWORD(&reg->gpiod);
1431
1432 /* Enable the gpio_data reg for update. */
1433 gpio_data |= GPDX_LED_UPDATE_MASK;
1434
1435 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1436 gpio_data = RD_REG_DWORD(&reg->gpiod);
1437
1438 /* Set the color bits. */
1439 qla24xx_flip_colors(ha, &led_color);
1440
1441 /* Clear out any previously set LED color. */
1442 gpio_data &= ~GPDX_LED_COLOR_MASK;
1443
1444 /* Set the new input LED color to GPIOD. */
1445 gpio_data |= led_color;
1446
1447 /* Set the modified gpio_data values. */
1448 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1449 gpio_data = RD_REG_DWORD(&reg->gpiod);
1450 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1451}
1452
1453int
7b867cf7 1454qla24xx_beacon_on(struct scsi_qla_host *vha)
f6df144c 1455{
1456 uint32_t gpio_data;
1457 unsigned long flags;
7b867cf7 1458 struct qla_hw_data *ha = vha->hw;
f6df144c 1459 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1460
1461 if (ha->beacon_blink_led == 0) {
1462 /* Enable firmware for update */
1463 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1464
7b867cf7 1465 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS)
f6df144c 1466 return QLA_FUNCTION_FAILED;
1467
7b867cf7 1468 if (qla2x00_get_fw_options(vha, ha->fw_options) !=
f6df144c 1469 QLA_SUCCESS) {
1470 qla_printk(KERN_WARNING, ha,
1471 "Unable to update fw options (beacon on).\n");
1472 return QLA_FUNCTION_FAILED;
1473 }
1474
1475 spin_lock_irqsave(&ha->hardware_lock, flags);
1476 gpio_data = RD_REG_DWORD(&reg->gpiod);
1477
1478 /* Enable the gpio_data reg for update. */
1479 gpio_data |= GPDX_LED_UPDATE_MASK;
1480 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1481 RD_REG_DWORD(&reg->gpiod);
1482
1483 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1484 }
1485
1486 /* So all colors blink together. */
1487 ha->beacon_color_state = 0;
1488
1489 /* Let the per HBA timer kick off the blinking process. */
1490 ha->beacon_blink_led = 1;
1491
1492 return QLA_SUCCESS;
1493}
1494
1495int
7b867cf7 1496qla24xx_beacon_off(struct scsi_qla_host *vha)
f6df144c 1497{
1498 uint32_t gpio_data;
1499 unsigned long flags;
7b867cf7 1500 struct qla_hw_data *ha = vha->hw;
f6df144c 1501 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1502
1503 ha->beacon_blink_led = 0;
1504 ha->beacon_color_state = QLA_LED_ALL_ON;
1505
7b867cf7 1506 ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */
f6df144c 1507
1508 /* Give control back to firmware. */
1509 spin_lock_irqsave(&ha->hardware_lock, flags);
1510 gpio_data = RD_REG_DWORD(&reg->gpiod);
1511
1512 /* Disable the gpio_data reg for update. */
1513 gpio_data &= ~GPDX_LED_UPDATE_MASK;
1514 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1515 RD_REG_DWORD(&reg->gpiod);
1516 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1517
1518 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1519
7b867cf7 1520 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
f6df144c 1521 qla_printk(KERN_WARNING, ha,
1522 "Unable to update fw options (beacon off).\n");
1523 return QLA_FUNCTION_FAILED;
1524 }
1525
7b867cf7 1526 if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
f6df144c 1527 qla_printk(KERN_WARNING, ha,
1528 "Unable to get fw options (beacon off).\n");
1529 return QLA_FUNCTION_FAILED;
1530 }
1531
1532 return QLA_SUCCESS;
1533}
854165f4 1534
1535
1536/*
1537 * Flash support routines
1538 */
1539
1540/**
1541 * qla2x00_flash_enable() - Setup flash for reading and writing.
1542 * @ha: HA context
1543 */
1544static void
7b867cf7 1545qla2x00_flash_enable(struct qla_hw_data *ha)
854165f4 1546{
1547 uint16_t data;
1548 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1549
1550 data = RD_REG_WORD(&reg->ctrl_status);
1551 data |= CSR_FLASH_ENABLE;
1552 WRT_REG_WORD(&reg->ctrl_status, data);
1553 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1554}
1555
1556/**
1557 * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1558 * @ha: HA context
1559 */
1560static void
7b867cf7 1561qla2x00_flash_disable(struct qla_hw_data *ha)
854165f4 1562{
1563 uint16_t data;
1564 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1565
1566 data = RD_REG_WORD(&reg->ctrl_status);
1567 data &= ~(CSR_FLASH_ENABLE);
1568 WRT_REG_WORD(&reg->ctrl_status, data);
1569 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1570}
1571
1572/**
1573 * qla2x00_read_flash_byte() - Reads a byte from flash
1574 * @ha: HA context
1575 * @addr: Address in flash to read
1576 *
1577 * A word is read from the chip, but, only the lower byte is valid.
1578 *
1579 * Returns the byte read from flash @addr.
1580 */
1581static uint8_t
7b867cf7 1582qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr)
854165f4 1583{
1584 uint16_t data;
1585 uint16_t bank_select;
1586 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1587
1588 bank_select = RD_REG_WORD(&reg->ctrl_status);
1589
1590 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1591 /* Specify 64K address range: */
1592 /* clear out Module Select and Flash Address bits [19:16]. */
1593 bank_select &= ~0xf8;
1594 bank_select |= addr >> 12 & 0xf0;
1595 bank_select |= CSR_FLASH_64K_BANK;
1596 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1597 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1598
1599 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1600 data = RD_REG_WORD(&reg->flash_data);
1601
1602 return (uint8_t)data;
1603 }
1604
1605 /* Setup bit 16 of flash address. */
1606 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1607 bank_select |= CSR_FLASH_64K_BANK;
1608 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1609 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1610 } else if (((addr & BIT_16) == 0) &&
1611 (bank_select & CSR_FLASH_64K_BANK)) {
1612 bank_select &= ~(CSR_FLASH_64K_BANK);
1613 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1614 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1615 }
1616
1617 /* Always perform IO mapped accesses to the FLASH registers. */
1618 if (ha->pio_address) {
1619 uint16_t data2;
1620
948882f6 1621 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
854165f4 1622 do {
948882f6 1623 data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
854165f4 1624 barrier();
1625 cpu_relax();
948882f6 1626 data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
854165f4 1627 } while (data != data2);
1628 } else {
1629 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1630 data = qla2x00_debounce_register(&reg->flash_data);
1631 }
1632
1633 return (uint8_t)data;
1634}
1635
1636/**
1637 * qla2x00_write_flash_byte() - Write a byte to flash
1638 * @ha: HA context
1639 * @addr: Address in flash to write
1640 * @data: Data to write
1641 */
1642static void
7b867cf7 1643qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data)
854165f4 1644{
1645 uint16_t bank_select;
1646 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1647
1648 bank_select = RD_REG_WORD(&reg->ctrl_status);
1649 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1650 /* Specify 64K address range: */
1651 /* clear out Module Select and Flash Address bits [19:16]. */
1652 bank_select &= ~0xf8;
1653 bank_select |= addr >> 12 & 0xf0;
1654 bank_select |= CSR_FLASH_64K_BANK;
1655 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1656 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1657
1658 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1659 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1660 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1661 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1662
1663 return;
1664 }
1665
1666 /* Setup bit 16 of flash address. */
1667 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1668 bank_select |= CSR_FLASH_64K_BANK;
1669 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1670 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1671 } else if (((addr & BIT_16) == 0) &&
1672 (bank_select & CSR_FLASH_64K_BANK)) {
1673 bank_select &= ~(CSR_FLASH_64K_BANK);
1674 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1675 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1676 }
1677
1678 /* Always perform IO mapped accesses to the FLASH registers. */
1679 if (ha->pio_address) {
948882f6
AV		 1680 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1681 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
854165f4 1682 } else {
1683 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1684 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1685 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1686 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1687 }
1688}
1689
1690/**
1691 * qla2x00_poll_flash() - Polls flash for completion.
1692 * @ha: HA context
1693 * @addr: Address in flash to poll
1694 * @poll_data: Data to be polled
1695 * @man_id: Flash manufacturer ID
1696 * @flash_id: Flash ID
1697 *
1698 * This function polls the device until bit 7 of what is read matches data
1699 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed
1700 * out (a fatal error). The flash book recommeds reading bit 7 again after
1701 * reading bit 5 as a 1.
1702 *
1703 * Returns 0 on success, else non-zero.
1704 */
1705static int
7b867cf7 1706qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data,
854165f4 1707 uint8_t man_id, uint8_t flash_id)
1708{
1709 int status;
1710 uint8_t flash_data;
1711 uint32_t cnt;
1712
1713 status = 1;
1714
1715 /* Wait for 30 seconds for command to finish. */
1716 poll_data &= BIT_7;
1717 for (cnt = 3000000; cnt; cnt--) {
1718 flash_data = qla2x00_read_flash_byte(ha, addr);
1719 if ((flash_data & BIT_7) == poll_data) {
1720 status = 0;
1721 break;
1722 }
1723
1724 if (man_id != 0x40 && man_id != 0xda) {
1725 if ((flash_data & BIT_5) && cnt > 2)
1726 cnt = 2;
1727 }
1728 udelay(10);
1729 barrier();
40a2e34a 1730 cond_resched();
854165f4 1731 }
1732 return status;
1733}
1734
854165f4 1735/**
1736 * qla2x00_program_flash_address() - Programs a flash address
1737 * @ha: HA context
1738 * @addr: Address in flash to program
1739 * @data: Data to be written in flash
1740 * @man_id: Flash manufacturer ID
1741 * @flash_id: Flash ID
1742 *
1743 * Returns 0 on success, else non-zero.
1744 */
1745static int
7b867cf7
AC		 1746qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr,
1747 uint8_t data, uint8_t man_id, uint8_t flash_id)
854165f4 1748{
1749 /* Write Program Command Sequence. */
1750 if (IS_OEM_001(ha)) {
1751 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1752 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1753 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
1754 qla2x00_write_flash_byte(ha, addr, data);
1755 } else {
1756 if (man_id == 0xda && flash_id == 0xc1) {
1757 qla2x00_write_flash_byte(ha, addr, data);
1758 if (addr & 0x7e)
1759 return 0;
1760 } else {
1761 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1762 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1763 qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
1764 qla2x00_write_flash_byte(ha, addr, data);
1765 }
1766 }
1767
1768 udelay(150);
1769
1770 /* Wait for write to complete. */
1771 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
1772}
1773
1774/**
1775 * qla2x00_erase_flash() - Erase the flash.
1776 * @ha: HA context
1777 * @man_id: Flash manufacturer ID
1778 * @flash_id: Flash ID
1779 *
1780 * Returns 0 on success, else non-zero.
1781 */
1782static int
7b867cf7 1783qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id)
854165f4 1784{
1785 /* Individual Sector Erase Command Sequence */
1786 if (IS_OEM_001(ha)) {
1787 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1788 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1789 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
1790 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1791 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1792 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
1793 } else {
1794 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1795 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1796 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1797 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1798 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1799 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
1800 }
1801
1802 udelay(150);
1803
1804 /* Wait for erase to complete. */
1805 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
1806}
1807
1808/**
1809 * qla2x00_erase_flash_sector() - Erase a flash sector.
1810 * @ha: HA context
1811 * @addr: Flash sector to erase
1812 * @sec_mask: Sector address mask
1813 * @man_id: Flash manufacturer ID
1814 * @flash_id: Flash ID
1815 *
1816 * Returns 0 on success, else non-zero.
1817 */
1818static int
7b867cf7 1819qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr,
854165f4 1820 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
1821{
1822 /* Individual Sector Erase Command Sequence */
1823 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1824 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1825 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1826 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1827 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1828 if (man_id == 0x1f && flash_id == 0x13)
1829 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
1830 else
1831 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
1832
1833 udelay(150);
1834
1835 /* Wait for erase to complete. */
1836 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
1837}
1838
1839/**
1840 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
1841 * @man_id: Flash manufacturer ID
1842 * @flash_id: Flash ID
1843 */
1844static void
7b867cf7 1845qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
854165f4 1846 uint8_t *flash_id)
1847{
1848 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1849 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1850 qla2x00_write_flash_byte(ha, 0x5555, 0x90);
1851 *man_id = qla2x00_read_flash_byte(ha, 0x0000);
1852 *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
1853 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1854 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1855 qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
1856}
1857
30c47662 1858static void
7b867cf7
AC		 1859qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf,
1860 uint32_t saddr, uint32_t length)
30c47662
AV		 1861{
1862 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1863 uint32_t midpoint, ilength;
1864 uint8_t data;
1865
1866 midpoint = length / 2;
1867
1868 WRT_REG_WORD(&reg->nvram, 0);
1869 RD_REG_WORD(&reg->nvram);
1870 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
1871 if (ilength == midpoint) {
1872 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1873 RD_REG_WORD(&reg->nvram);
1874 }
1875 data = qla2x00_read_flash_byte(ha, saddr);
1876 if (saddr % 100)
1877 udelay(10);
1878 *tmp_buf = data;
40a2e34a 1879 cond_resched();
30c47662
AV		 1880 }
1881}
854165f4 1882
1883static inline void
7b867cf7 1884qla2x00_suspend_hba(struct scsi_qla_host *vha)
854165f4 1885{
1886 int cnt;
1887 unsigned long flags;
7b867cf7 1888 struct qla_hw_data *ha = vha->hw;
854165f4 1889 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1890
1891 /* Suspend HBA. */
7b867cf7 1892 scsi_block_requests(vha->host);
fd34f556 1893 ha->isp_ops->disable_intrs(ha);
854165f4 1894 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1895
1896 /* Pause RISC. */
1897 spin_lock_irqsave(&ha->hardware_lock, flags);
1898 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1899 RD_REG_WORD(&reg->hccr);
1900 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1901 for (cnt = 0; cnt < 30000; cnt++) {
1902 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
1903 break;
1904 udelay(100);
1905 }
1906 } else {
1907 udelay(10);
1908 }
1909 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1910}
1911
1912static inline void
7b867cf7 1913qla2x00_resume_hba(struct scsi_qla_host *vha)
854165f4 1914{
7b867cf7
AC		 1915 struct qla_hw_data *ha = vha->hw;
1916
854165f4 1917 /* Resume HBA. */
1918 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
7b867cf7
AC		 1919 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1920 qla2xxx_wake_dpc(vha);
1921 qla2x00_wait_for_hba_online(vha);
1922 scsi_unblock_requests(vha->host);
854165f4 1923}
1924
1925uint8_t *
7b867cf7 1926qla2x00_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
854165f4 1927 uint32_t offset, uint32_t length)
1928{
854165f4 1929 uint32_t addr, midpoint;
1930 uint8_t *data;
7b867cf7 1931 struct qla_hw_data *ha = vha->hw;
854165f4 1932 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1933
1934 /* Suspend HBA. */
7b867cf7 1935 qla2x00_suspend_hba(vha);
854165f4 1936
1937 /* Go with read. */
854165f4 1938 midpoint = ha->optrom_size / 2;
1939
1940 qla2x00_flash_enable(ha);
1941 WRT_REG_WORD(&reg->nvram, 0);
1942 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
1943 for (addr = offset, data = buf; addr < length; addr++, data++) {
1944 if (addr == midpoint) {
1945 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1946 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
1947 }
1948
1949 *data = qla2x00_read_flash_byte(ha, addr);
1950 }
1951 qla2x00_flash_disable(ha);
854165f4 1952
1953 /* Resume HBA. */
7b867cf7 1954 qla2x00_resume_hba(vha);
854165f4 1955
1956 return buf;
1957}
1958
1959int
7b867cf7 1960qla2x00_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
854165f4 1961 uint32_t offset, uint32_t length)
1962{
1963
1964 int rval;
854165f4 1965 uint8_t man_id, flash_id, sec_number, data;
1966 uint16_t wd;
1967 uint32_t addr, liter, sec_mask, rest_addr;
7b867cf7 1968 struct qla_hw_data *ha = vha->hw;
854165f4 1969 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1970
1971 /* Suspend HBA. */
7b867cf7 1972 qla2x00_suspend_hba(vha);
854165f4 1973
1974 rval = QLA_SUCCESS;
1975 sec_number = 0;
1976
1977 /* Reset ISP chip. */
854165f4 1978 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1979 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
1980
1981 /* Go with write. */
1982 qla2x00_flash_enable(ha);
1983 do { /* Loop once to provide quick error exit */
1984 /* Structure of flash memory based on manufacturer */
1985 if (IS_OEM_001(ha)) {
1986 /* OEM variant with special flash part. */
1987 man_id = flash_id = 0;
1988 rest_addr = 0xffff;
1989 sec_mask = 0x10000;
1990 goto update_flash;
1991 }
1992 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
1993 switch (man_id) {
1994 case 0x20: /* ST flash. */
1995 if (flash_id == 0xd2 || flash_id == 0xe3) {
1996 /*
1997 * ST m29w008at part - 64kb sector size with
1998 * 32kb,8kb,8kb,16kb sectors at memory address
1999 * 0xf0000.
2000 */
2001 rest_addr = 0xffff;
2002 sec_mask = 0x10000;
2003 break;
2004 }
2005 /*
2006 * ST m29w010b part - 16kb sector size
2007 * Default to 16kb sectors
2008 */
2009 rest_addr = 0x3fff;
2010 sec_mask = 0x1c000;
2011 break;
2012 case 0x40: /* Mostel flash. */
2013 /* Mostel v29c51001 part - 512 byte sector size. */
2014 rest_addr = 0x1ff;
2015 sec_mask = 0x1fe00;
2016 break;
2017 case 0xbf: /* SST flash. */
2018 /* SST39sf10 part - 4kb sector size. */
2019 rest_addr = 0xfff;
2020 sec_mask = 0x1f000;
2021 break;
2022 case 0xda: /* Winbond flash. */
2023 /* Winbond W29EE011 part - 256 byte sector size. */
2024 rest_addr = 0x7f;
2025 sec_mask = 0x1ff80;
2026 break;
2027 case 0xc2: /* Macronix flash. */
2028 /* 64k sector size. */
2029 if (flash_id == 0x38 || flash_id == 0x4f) {
2030 rest_addr = 0xffff;
2031 sec_mask = 0x10000;
2032 break;
2033 }
2034 /* Fall through... */
2035
2036 case 0x1f: /* Atmel flash. */
2037 /* 512k sector size. */
2038 if (flash_id == 0x13) {
2039 rest_addr = 0x7fffffff;
2040 sec_mask = 0x80000000;
2041 break;
2042 }
2043 /* Fall through... */
2044
2045 case 0x01: /* AMD flash. */
2046 if (flash_id == 0x38 || flash_id == 0x40 ||
2047 flash_id == 0x4f) {
2048 /* Am29LV081 part - 64kb sector size. */
2049 /* Am29LV002BT part - 64kb sector size. */
2050 rest_addr = 0xffff;
2051 sec_mask = 0x10000;
2052 break;
2053 } else if (flash_id == 0x3e) {
2054 /*
2055 * Am29LV008b part - 64kb sector size with
2056 * 32kb,8kb,8kb,16kb sector at memory address
2057 * h0xf0000.
2058 */
2059 rest_addr = 0xffff;
2060 sec_mask = 0x10000;
2061 break;
2062 } else if (flash_id == 0x20 || flash_id == 0x6e) {
2063 /*
2064 * Am29LV010 part or AM29f010 - 16kb sector
2065 * size.
2066 */
2067 rest_addr = 0x3fff;
2068 sec_mask = 0x1c000;
2069 break;
2070 } else if (flash_id == 0x6d) {
2071 /* Am29LV001 part - 8kb sector size. */
2072 rest_addr = 0x1fff;
2073 sec_mask = 0x1e000;
2074 break;
2075 }
2076 default:
2077 /* Default to 16 kb sector size. */
2078 rest_addr = 0x3fff;
2079 sec_mask = 0x1c000;
2080 break;
2081 }
2082
2083update_flash:
2084 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2085 if (qla2x00_erase_flash(ha, man_id, flash_id)) {
2086 rval = QLA_FUNCTION_FAILED;
2087 break;
2088 }
2089 }
2090
2091 for (addr = offset, liter = 0; liter < length; liter++,
2092 addr++) {
2093 data = buf[liter];
2094 /* Are we at the beginning of a sector? */
2095 if ((addr & rest_addr) == 0) {
2096 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2097 if (addr >= 0x10000UL) {
2098 if (((addr >> 12) & 0xf0) &&
2099 ((man_id == 0x01 &&
2100 flash_id == 0x3e) ||
2101 (man_id == 0x20 &&
2102 flash_id == 0xd2))) {
2103 sec_number++;
2104 if (sec_number == 1) {
2105 rest_addr =
2106 0x7fff;
2107 sec_mask =
2108 0x18000;
2109 } else if (
2110 sec_number == 2 ||
2111 sec_number == 3) {
2112 rest_addr =
2113 0x1fff;
2114 sec_mask =
2115 0x1e000;
2116 } else if (
2117 sec_number == 4) {
2118 rest_addr =
2119 0x3fff;
2120 sec_mask =
2121 0x1c000;
2122 }
2123 }
2124 }
2125 } else if (addr == ha->optrom_size / 2) {
2126 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2127 RD_REG_WORD(&reg->nvram);
2128 }
2129
2130 if (flash_id == 0xda && man_id == 0xc1) {
2131 qla2x00_write_flash_byte(ha, 0x5555,
2132 0xaa);
2133 qla2x00_write_flash_byte(ha, 0x2aaa,
2134 0x55);
2135 qla2x00_write_flash_byte(ha, 0x5555,
2136 0xa0);
2137 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
2138 /* Then erase it */
2139 if (qla2x00_erase_flash_sector(ha,
2140 addr, sec_mask, man_id,
2141 flash_id)) {
2142 rval = QLA_FUNCTION_FAILED;
2143 break;
2144 }
2145 if (man_id == 0x01 && flash_id == 0x6d)
2146 sec_number++;
2147 }
2148 }
2149
2150 if (man_id == 0x01 && flash_id == 0x6d) {
2151 if (sec_number == 1 &&
2152 addr == (rest_addr - 1)) {
2153 rest_addr = 0x0fff;
2154 sec_mask = 0x1f000;
2155 } else if (sec_number == 3 && (addr & 0x7ffe)) {
2156 rest_addr = 0x3fff;
2157 sec_mask = 0x1c000;
2158 }
2159 }
2160
2161 if (qla2x00_program_flash_address(ha, addr, data,
2162 man_id, flash_id)) {
2163 rval = QLA_FUNCTION_FAILED;
2164 break;
2165 }
40a2e34a 2166 cond_resched();
854165f4 2167 }
2168 } while (0);
2169 qla2x00_flash_disable(ha);
854165f4 2170
2171 /* Resume HBA. */
7b867cf7 2172 qla2x00_resume_hba(vha);
854165f4 2173
2174 return rval;
2175}
2176
2177uint8_t *
7b867cf7 2178qla24xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
854165f4 2179 uint32_t offset, uint32_t length)
2180{
7b867cf7
AC		 2181 struct qla_hw_data *ha = vha->hw;
2182
854165f4 2183 /* Suspend HBA. */
7b867cf7 2184 scsi_block_requests(vha->host);
854165f4 2185 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2186
2187 /* Go with read. */
7b867cf7 2188 qla24xx_read_flash_data(vha, (uint32_t *)buf, offset >> 2, length >> 2);
854165f4 2189
2190 /* Resume HBA. */
2191 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
7b867cf7 2192 scsi_unblock_requests(vha->host);
854165f4 2193
2194 return buf;
2195}
2196
2197int
7b867cf7 2198qla24xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
854165f4 2199 uint32_t offset, uint32_t length)
2200{
2201 int rval;
7b867cf7 2202 struct qla_hw_data *ha = vha->hw;
854165f4 2203
2204 /* Suspend HBA. */
7b867cf7 2205 scsi_block_requests(vha->host);
854165f4 2206 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2207
2208 /* Go with write. */
7b867cf7 2209 rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, offset >> 2,
854165f4 2210 length >> 2);
2211
2212 /* Resume HBA -- RISC reset needed. */
2213 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
7b867cf7
AC		 2214 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2215 qla2xxx_wake_dpc(vha);
2216 qla2x00_wait_for_hba_online(vha);
2217 scsi_unblock_requests(vha->host);
854165f4 2218
2219 return rval;
2220}
30c47662 2221
338c9161 2222uint8_t *
7b867cf7 2223qla25xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
338c9161
AV		 2224 uint32_t offset, uint32_t length)
2225{
2226 int rval;
2227 dma_addr_t optrom_dma;
2228 void *optrom;
2229 uint8_t *pbuf;
2230 uint32_t faddr, left, burst;
7b867cf7 2231 struct qla_hw_data *ha = vha->hw;
338c9161 2232
b7cc176c 2233 if (offset & 0xfff)
338c9161
AV		 2234 goto slow_read;
2235 if (length < OPTROM_BURST_SIZE)
2236 goto slow_read;
2237
2238 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2239 &optrom_dma, GFP_KERNEL);
2240 if (!optrom) {
2241 qla_printk(KERN_DEBUG, ha,
2242 "Unable to allocate memory for optrom burst read "
2243 "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
2244
2245 goto slow_read;
2246 }
2247
2248 pbuf = buf;
2249 faddr = offset >> 2;
2250 left = length >> 2;
2251 burst = OPTROM_BURST_DWORDS;
2252 while (left != 0) {
2253 if (burst > left)
2254 burst = left;
2255
7b867cf7 2256 rval = qla2x00_dump_ram(vha, optrom_dma,
3a03eb79 2257 flash_data_addr(ha, faddr), burst);
338c9161
AV		 2258 if (rval) {
2259 qla_printk(KERN_WARNING, ha,
2260 "Unable to burst-read optrom segment "
2261 "(%x/%x/%llx).\n", rval,
3a03eb79 2262 flash_data_addr(ha, faddr),
875baf3c 2263 (unsigned long long)optrom_dma);
338c9161
AV		 2264 qla_printk(KERN_WARNING, ha,
2265 "Reverting to slow-read.\n");
2266
2267 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2268 optrom, optrom_dma);
2269 goto slow_read;
2270 }
2271
2272 memcpy(pbuf, optrom, burst * 4);
2273
2274 left -= burst;
2275 faddr += burst;
2276 pbuf += burst * 4;
2277 }
2278
2279 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
2280 optrom_dma);
2281
2282 return buf;
2283
2284slow_read:
7b867cf7 2285 return qla24xx_read_optrom_data(vha, buf, offset, length);
338c9161
AV		 2286}
2287
30c47662
AV		 2288/**
2289 * qla2x00_get_fcode_version() - Determine an FCODE image's version.
2290 * @ha: HA context
2291 * @pcids: Pointer to the FCODE PCI data structure
2292 *
2293 * The process of retrieving the FCODE version information is at best
2294 * described as interesting.
2295 *
2296 * Within the first 100h bytes of the image an ASCII string is present
2297 * which contains several pieces of information including the FCODE
2298 * version. Unfortunately it seems the only reliable way to retrieve
2299 * the version is by scanning for another sentinel within the string,
2300 * the FCODE build date:
2301 *
2302 * ... 2.00.02 10/17/02 ...
2303 *
2304 * Returns QLA_SUCCESS on successful retrieval of version.
2305 */
2306static void
7b867cf7 2307qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids)
30c47662
AV		 2308{
2309 int ret = QLA_FUNCTION_FAILED;
2310 uint32_t istart, iend, iter, vend;
2311 uint8_t do_next, rbyte, *vbyte;
2312
2313 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2314
2315 /* Skip the PCI data structure. */
2316 istart = pcids +
2317 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
2318 qla2x00_read_flash_byte(ha, pcids + 0x0A));
2319 iend = istart + 0x100;
2320 do {
2321 /* Scan for the sentinel date string...eeewww. */
2322 do_next = 0;
2323 iter = istart;
2324 while ((iter < iend) && !do_next) {
2325 iter++;
2326 if (qla2x00_read_flash_byte(ha, iter) == '/') {
2327 if (qla2x00_read_flash_byte(ha, iter + 2) ==
2328 '/')
2329 do_next++;
2330 else if (qla2x00_read_flash_byte(ha,
2331 iter + 3) == '/')
2332 do_next++;
2333 }
2334 }
2335 if (!do_next)
2336 break;
2337
2338 /* Backtrack to previous ' ' (space). */
2339 do_next = 0;
2340 while ((iter > istart) && !do_next) {
2341 iter--;
2342 if (qla2x00_read_flash_byte(ha, iter) == ' ')
2343 do_next++;
2344 }
2345 if (!do_next)
2346 break;
2347
2348 /*
2349 * Mark end of version tag, and find previous ' ' (space) or
2350 * string length (recent FCODE images -- major hack ahead!!!).
2351 */
2352 vend = iter - 1;
2353 do_next = 0;
2354 while ((iter > istart) && !do_next) {
2355 iter--;
2356 rbyte = qla2x00_read_flash_byte(ha, iter);
2357 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
2358 do_next++;
2359 }
2360 if (!do_next)
2361 break;
2362
2363 /* Mark beginning of version tag, and copy data. */
2364 iter++;
2365 if ((vend - iter) &&
2366 ((vend - iter) < sizeof(ha->fcode_revision))) {
2367 vbyte = ha->fcode_revision;
2368 while (iter <= vend) {
2369 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
2370 iter++;
2371 }
2372 ret = QLA_SUCCESS;
2373 }
2374 } while (0);
2375
2376 if (ret != QLA_SUCCESS)
2377 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2378}
2379
2380int
7b867cf7 2381qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
30c47662
AV		 2382{
2383 int ret = QLA_SUCCESS;
2384 uint8_t code_type, last_image;
2385 uint32_t pcihdr, pcids;
2386 uint8_t *dbyte;
2387 uint16_t *dcode;
7b867cf7 2388 struct qla_hw_data *ha = vha->hw;
30c47662
AV		 2389
2390 if (!ha->pio_address || !mbuf)
2391 return QLA_FUNCTION_FAILED;
2392
2393 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2394 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2395 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2396 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2397
2398 qla2x00_flash_enable(ha);
2399
2400 /* Begin with first PCI expansion ROM header. */
2401 pcihdr = 0;
2402 last_image = 1;
2403 do {
2404 /* Verify PCI expansion ROM header. */
2405 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
2406 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2407 /* No signature */
7b867cf7
AC		 2408 DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM "
2409 "signature.\n"));
30c47662
AV		 2410 ret = QLA_FUNCTION_FAILED;
2411 break;
2412 }
2413
2414 /* Locate PCI data structure. */
2415 pcids = pcihdr +
2416 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2417 qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2418
2419 /* Validate signature of PCI data structure. */
2420 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2421 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2422 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2423 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2424 /* Incorrect header. */
7b867cf7
AC		 2425 DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not "
2426 "found pcir_adr=%x.\n", pcids));
30c47662
AV		 2427 ret = QLA_FUNCTION_FAILED;
2428 break;
2429 }
2430
2431 /* Read version */
2432 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2433 switch (code_type) {
2434 case ROM_CODE_TYPE_BIOS:
2435 /* Intel x86, PC-AT compatible. */
2436 ha->bios_revision[0] =
2437 qla2x00_read_flash_byte(ha, pcids + 0x12);
2438 ha->bios_revision[1] =
2439 qla2x00_read_flash_byte(ha, pcids + 0x13);
7b867cf7 2440 DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n",
30c47662
AV		 2441 ha->bios_revision[1], ha->bios_revision[0]));
2442 break;
2443 case ROM_CODE_TYPE_FCODE:
2444 /* Open Firmware standard for PCI (FCode). */
2445 /* Eeeewww... */
2446 qla2x00_get_fcode_version(ha, pcids);
2447 break;
2448 case ROM_CODE_TYPE_EFI:
2449 /* Extensible Firmware Interface (EFI). */
2450 ha->efi_revision[0] =
2451 qla2x00_read_flash_byte(ha, pcids + 0x12);
2452 ha->efi_revision[1] =
2453 qla2x00_read_flash_byte(ha, pcids + 0x13);
7b867cf7 2454 DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n",
30c47662
AV		 2455 ha->efi_revision[1], ha->efi_revision[0]));
2456 break;
2457 default:
7b867cf7
AC		 2458 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code "
2459 "type %x at pcids %x.\n", code_type, pcids));
30c47662
AV		 2460 break;
2461 }
2462
2463 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2464
2465 /* Locate next PCI expansion ROM. */
2466 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2467 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2468 } while (!last_image);
2469
2470 if (IS_QLA2322(ha)) {
2471 /* Read firmware image information. */
2472 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2473 dbyte = mbuf;
2474 memset(dbyte, 0, 8);
2475 dcode = (uint16_t *)dbyte;
2476
c00d8994 2477 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10,
30c47662 2478 8);
7b867cf7
AC		 2479 DEBUG3(qla_printk(KERN_DEBUG, ha, "dumping fw ver from "
2480 "flash:\n"));
30c47662
AV		 2481 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte, 8));
2482
2483 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2484 dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2485 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2486 dcode[3] == 0)) {
7b867cf7
AC		 2487 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw "
2488 "revision at %x.\n", ha->flt_region_fw * 4));
30c47662
AV		 2489 } else {
2490 /* values are in big endian */
2491 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2492 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2493 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
2494 }
2495 }
2496
2497 qla2x00_flash_disable(ha);
2498
2499 return ret;
2500}
2501
2502int
7b867cf7 2503qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
30c47662
AV		 2504{
2505 int ret = QLA_SUCCESS;
2506 uint32_t pcihdr, pcids;
2507 uint32_t *dcode;
2508 uint8_t *bcode;
2509 uint8_t code_type, last_image;
2510 int i;
7b867cf7 2511 struct qla_hw_data *ha = vha->hw;
30c47662
AV		 2512
2513 if (!mbuf)
2514 return QLA_FUNCTION_FAILED;
2515
2516 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2517 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2518 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2519 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2520
2521 dcode = mbuf;
2522
2523 /* Begin with first PCI expansion ROM header. */
c00d8994 2524 pcihdr = ha->flt_region_boot;
30c47662
AV		 2525 last_image = 1;
2526 do {
2527 /* Verify PCI expansion ROM header. */
7b867cf7 2528 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
30c47662
AV		 2529 bcode = mbuf + (pcihdr % 4);
2530 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2531 /* No signature */
7b867cf7
AC		 2532 DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM "
2533 "signature.\n"));
30c47662
AV		 2534 ret = QLA_FUNCTION_FAILED;
2535 break;
2536 }
2537
2538 /* Locate PCI data structure. */
2539 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2540
7b867cf7 2541 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
30c47662
AV		 2542 bcode = mbuf + (pcihdr % 4);
2543
2544 /* Validate signature of PCI data structure. */
2545 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2546 bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2547 /* Incorrect header. */
7b867cf7
AC		 2548 DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not "
2549 "found pcir_adr=%x.\n", pcids));
30c47662
AV		 2550 ret = QLA_FUNCTION_FAILED;
2551 break;
2552 }
2553
2554 /* Read version */
2555 code_type = bcode[0x14];
2556 switch (code_type) {
2557 case ROM_CODE_TYPE_BIOS:
2558 /* Intel x86, PC-AT compatible. */
2559 ha->bios_revision[0] = bcode[0x12];
2560 ha->bios_revision[1] = bcode[0x13];
7b867cf7 2561 DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n",
30c47662
AV		 2562 ha->bios_revision[1], ha->bios_revision[0]));
2563 break;
2564 case ROM_CODE_TYPE_FCODE:
2565 /* Open Firmware standard for PCI (FCode). */
2566 ha->fcode_revision[0] = bcode[0x12];
2567 ha->fcode_revision[1] = bcode[0x13];
7b867cf7 2568 DEBUG3(qla_printk(KERN_DEBUG, ha, "read FCODE %d.%d.\n",
30c47662
AV		 2569 ha->fcode_revision[1], ha->fcode_revision[0]));
2570 break;
2571 case ROM_CODE_TYPE_EFI:
2572 /* Extensible Firmware Interface (EFI). */
2573 ha->efi_revision[0] = bcode[0x12];
2574 ha->efi_revision[1] = bcode[0x13];
7b867cf7 2575 DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n",
30c47662
AV		 2576 ha->efi_revision[1], ha->efi_revision[0]));
2577 break;
2578 default:
7b867cf7
AC		 2579 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code "
2580 "type %x at pcids %x.\n", code_type, pcids));
30c47662
AV		 2581 break;
2582 }
2583
2584 last_image = bcode[0x15] & BIT_7;
2585
2586 /* Locate next PCI expansion ROM. */
2587 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2588 } while (!last_image);
2589
2590 /* Read firmware image information. */
2591 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2592 dcode = mbuf;
2593
7b867cf7 2594 qla24xx_read_flash_data(vha, dcode, ha->flt_region_fw + 4, 4);
30c47662
AV		 2595 for (i = 0; i < 4; i++)
2596 dcode[i] = be32_to_cpu(dcode[i]);
2597
2598 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
2599 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
2600 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2601 dcode[3] == 0)) {
7b867cf7
AC		 2602 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw "
2603 "revision at %x.\n", ha->flt_region_fw * 4));
30c47662
AV		 2604 } else {
2605 ha->fw_revision[0] = dcode[0];
2606 ha->fw_revision[1] = dcode[1];
2607 ha->fw_revision[2] = dcode[2];
2608 ha->fw_revision[3] = dcode[3];
2609 }
2610
2611 return ret;
2612}
cb8dacbf 2613
1ee27146
JC		 2614static int
2615qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end)
2616{
2617 if (pos >= end || *pos != 0x82)
2618 return 0;
2619
2620 pos += 3 + pos[1];
2621 if (pos >= end || *pos != 0x90)
2622 return 0;
2623
2624 pos += 3 + pos[1];
2625 if (pos >= end || *pos != 0x78)
2626 return 0;
2627
2628 return 1;
2629}
2630
2631int
7b867cf7 2632qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size)
1ee27146 2633{
7b867cf7 2634 struct qla_hw_data *ha = vha->hw;
1ee27146
JC		 2635 uint8_t *pos = ha->vpd;
2636 uint8_t *end = pos + ha->vpd_size;
2637 int len = 0;
2638
2639 if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end))
2640 return 0;
2641
2642 while (pos < end && *pos != 0x78) {
2643 len = (*pos == 0x82) ? pos[1] : pos[2];
2644
2645 if (!strncmp(pos, key, strlen(key)))
2646 break;
2647
2648 if (*pos != 0x90 && *pos != 0x91)
2649 pos += len;
2650
2651 pos += 3;
2652 }
2653
2654 if (pos < end - len && *pos != 0x78)
2655 return snprintf(str, size, "%.*s", len, pos + 3);
2656
2657 return 0;
2658}
Linux kernel - Deliverables
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