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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[deliverable/linux.git] / drivers / scsi / qla4xxx / ql4_mbx.c
CommitLineData
afaf5a2d
DS		 1/*
2 * QLogic iSCSI HBA Driver
7d01d069 3 * Copyright (c) 2003-2010 QLogic Corporation
afaf5a2d
DS		 4 *
5 * See LICENSE.qla4xxx for copyright and licensing details.
6 */
7
8#include "ql4_def.h"
c0e344c9
DS		 9#include "ql4_glbl.h"
10#include "ql4_dbg.h"
11#include "ql4_inline.h"
afaf5a2d
DS		 12
13
14/**
15 * qla4xxx_mailbox_command - issues mailbox commands
16 * @ha: Pointer to host adapter structure.
17 * @inCount: number of mailbox registers to load.
18 * @outCount: number of mailbox registers to return.
19 * @mbx_cmd: data pointer for mailbox in registers.
20 * @mbx_sts: data pointer for mailbox out registers.
21 *
70f23fd6 22 * This routine issue mailbox commands and waits for completion.
afaf5a2d
DS		 23 * If outCount is 0, this routine completes successfully WITHOUT waiting
24 * for the mailbox command to complete.
25 **/
f4f5df23
VC		 26int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
27 uint8_t outCount, uint32_t *mbx_cmd,
28 uint32_t *mbx_sts)
afaf5a2d
DS		 29{
30 int status = QLA_ERROR;
31 uint8_t i;
32 u_long wait_count;
33 uint32_t intr_status;
34 unsigned long flags = 0;
99b53bf5 35 uint32_t dev_state;
afaf5a2d
DS		 36
37 /* Make sure that pointers are valid */
38 if (!mbx_cmd || !mbx_sts) {
39 DEBUG2(printk("scsi%ld: %s: Invalid mbx_cmd or mbx_sts "
40 "pointer\n", ha->host_no, __func__));
477ffb9d
DS		 41 return status;
42 }
21033639 43
13483730
MC		 44 if (is_qla40XX(ha)) {
45 if (test_bit(AF_HA_REMOVAL, &ha->flags)) {
46 DEBUG2(ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: "
47 "prematurely completing mbx cmd as "
48 "adapter removal detected\n",
49 ha->host_no, __func__));
50 return status;
51 }
52 }
53
2232be0d
LC		 54 if ((is_aer_supported(ha)) &&
55 (test_bit(AF_PCI_CHANNEL_IO_PERM_FAILURE, &ha->flags))) {
56 DEBUG2(printk(KERN_WARNING "scsi%ld: %s: Perm failure on EEH, "
57 "timeout MBX Exiting.\n", ha->host_no, __func__));
58 return status;
59 }
60
477ffb9d
DS		 61 /* Mailbox code active */
62 wait_count = MBOX_TOV * 100;
63
64 while (wait_count--) {
65 mutex_lock(&ha->mbox_sem);
66 if (!test_bit(AF_MBOX_COMMAND, &ha->flags)) {
67 set_bit(AF_MBOX_COMMAND, &ha->flags);
68 mutex_unlock(&ha->mbox_sem);
69 break;
70 }
71 mutex_unlock(&ha->mbox_sem);
72 if (!wait_count) {
73 DEBUG2(printk("scsi%ld: %s: mbox_sem failed\n",
74 ha->host_no, __func__));
75 return status;
76 }
77 msleep(10);
afaf5a2d
DS		 78 }
79
5f50aa3a
LC		 80 if (is_qla8022(ha)) {
81 if (test_bit(AF_FW_RECOVERY, &ha->flags)) {
82 DEBUG2(ql4_printk(KERN_WARNING, ha,
83 "scsi%ld: %s: prematurely completing mbx cmd as firmware recovery detected\n",
84 ha->host_no, __func__));
85 goto mbox_exit;
86 }
87 /* Do not send any mbx cmd if h/w is in failed state*/
88 qla4_8xxx_idc_lock(ha);
89 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
90 qla4_8xxx_idc_unlock(ha);
91 if (dev_state == QLA82XX_DEV_FAILED) {
92 ql4_printk(KERN_WARNING, ha,
93 "scsi%ld: %s: H/W is in failed state, do not send any mailbox commands\n",
94 ha->host_no, __func__);
95 goto mbox_exit;
96 }
97 }
98
afaf5a2d 99 spin_lock_irqsave(&ha->hardware_lock, flags);
f4f5df23 100
afaf5a2d
DS		 101 ha->mbox_status_count = outCount;
102 for (i = 0; i < outCount; i++)
103 ha->mbox_status[i] = 0;
104
f4f5df23
VC		 105 if (is_qla8022(ha)) {
106 /* Load all mailbox registers, except mailbox 0. */
107 DEBUG5(
108 printk("scsi%ld: %s: Cmd ", ha->host_no, __func__);
109 for (i = 0; i < inCount; i++)
110 printk("mb%d=%04x ", i, mbx_cmd[i]);
111 printk("\n"));
112
113 for (i = 1; i < inCount; i++)
114 writel(mbx_cmd[i], &ha->qla4_8xxx_reg->mailbox_in[i]);
115 writel(mbx_cmd[0], &ha->qla4_8xxx_reg->mailbox_in[0]);
116 readl(&ha->qla4_8xxx_reg->mailbox_in[0]);
117 writel(HINT_MBX_INT_PENDING, &ha->qla4_8xxx_reg->hint);
118 } else {
119 /* Load all mailbox registers, except mailbox 0. */
120 for (i = 1; i < inCount; i++)
121 writel(mbx_cmd[i], &ha->reg->mailbox[i]);
122
123 /* Wakeup firmware */
124 writel(mbx_cmd[0], &ha->reg->mailbox[0]);
125 readl(&ha->reg->mailbox[0]);
126 writel(set_rmask(CSR_INTR_RISC), &ha->reg->ctrl_status);
127 readl(&ha->reg->ctrl_status);
128 }
afaf5a2d 129
afaf5a2d
DS		 130 spin_unlock_irqrestore(&ha->hardware_lock, flags);
131
132 /* Wait for completion */
afaf5a2d
DS		 133
134 /*
135 * If we don't want status, don't wait for the mailbox command to
136 * complete. For example, MBOX_CMD_RESET_FW doesn't return status,
137 * you must poll the inbound Interrupt Mask for completion.
138 */
139 if (outCount == 0) {
140 status = QLA_SUCCESS;
afaf5a2d
DS		 141 goto mbox_exit;
142 }
afaf5a2d 143
f4f5df23
VC		 144 /*
145 * Wait for completion: Poll or completion queue
146 */
147 if (test_bit(AF_IRQ_ATTACHED, &ha->flags) &&
148 test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
149 test_bit(AF_ONLINE, &ha->flags) &&
7eece5a0 150 !test_bit(AF_HA_REMOVAL, &ha->flags)) {
f4f5df23
VC		 151 /* Do not poll for completion. Use completion queue */
152 set_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
153 wait_for_completion_timeout(&ha->mbx_intr_comp, MBOX_TOV * HZ);
154 clear_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
155 } else {
156 /* Poll for command to complete */
157 wait_count = jiffies + MBOX_TOV * HZ;
158 while (test_bit(AF_MBOX_COMMAND_DONE, &ha->flags) == 0) {
159 if (time_after_eq(jiffies, wait_count))
160 break;
2232be0d 161
afaf5a2d
DS		 162 /*
163 * Service the interrupt.
164 * The ISR will save the mailbox status registers
165 * to a temporary storage location in the adapter
166 * structure.
167 */
f4f5df23
VC		 168
169 spin_lock_irqsave(&ha->hardware_lock, flags);
170 if (is_qla8022(ha)) {
171 intr_status =
172 readl(&ha->qla4_8xxx_reg->host_int);
173 if (intr_status & ISRX_82XX_RISC_INT) {
174 ha->mbox_status_count = outCount;
175 intr_status =
176 readl(&ha->qla4_8xxx_reg->host_status);
177 ha->isp_ops->interrupt_service_routine(
178 ha, intr_status);
179 if (test_bit(AF_INTERRUPTS_ON,
180 &ha->flags) &&
181 test_bit(AF_INTx_ENABLED,
182 &ha->flags))
183 qla4_8xxx_wr_32(ha,
184 ha->nx_legacy_intr.tgt_mask_reg,
185 0xfbff);
186 }
187 } else {
188 intr_status = readl(&ha->reg->ctrl_status);
189 if (intr_status & INTR_PENDING) {
190 /*
191 * Service the interrupt.
192 * The ISR will save the mailbox status
193 * registers to a temporary storage
194 * location in the adapter structure.
195 */
196 ha->mbox_status_count = outCount;
197 ha->isp_ops->interrupt_service_routine(
198 ha, intr_status);
199 }
200 }
201 spin_unlock_irqrestore(&ha->hardware_lock, flags);
202 msleep(10);
afaf5a2d 203 }
afaf5a2d 204 }
afaf5a2d
DS		 205
206 /* Check for mailbox timeout. */
207 if (!test_bit(AF_MBOX_COMMAND_DONE, &ha->flags)) {
21033639
NJ		 208 if (is_qla8022(ha) &&
209 test_bit(AF_FW_RECOVERY, &ha->flags)) {
210 DEBUG2(ql4_printk(KERN_INFO, ha,
211 "scsi%ld: %s: prematurely completing mbx cmd as "
212 "firmware recovery detected\n",
213 ha->host_no, __func__));
214 goto mbox_exit;
215 }
afaf5a2d
DS		 216 DEBUG2(printk("scsi%ld: Mailbox Cmd 0x%08X timed out ...,"
217 " Scheduling Adapter Reset\n", ha->host_no,
218 mbx_cmd[0]));
219 ha->mailbox_timeout_count++;
220 mbx_sts[0] = (-1);
221 set_bit(DPC_RESET_HA, &ha->dpc_flags);
e6bd0ebd
GM		 222 if (is_qla8022(ha)) {
223 ql4_printk(KERN_INFO, ha,
224 "disabling pause transmit on port 0 & 1.\n");
225 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
226 CRB_NIU_XG_PAUSE_CTL_P0 |
227 CRB_NIU_XG_PAUSE_CTL_P1);
228 }
afaf5a2d
DS		 229 goto mbox_exit;
230 }
231
232 /*
233 * Copy the mailbox out registers to the caller's mailbox in/out
234 * structure.
235 */
236 spin_lock_irqsave(&ha->hardware_lock, flags);
237 for (i = 0; i < outCount; i++)
238 mbx_sts[i] = ha->mbox_status[i];
239
240 /* Set return status and error flags (if applicable). */
241 switch (ha->mbox_status[0]) {
242 case MBOX_STS_COMMAND_COMPLETE:
243 status = QLA_SUCCESS;
244 break;
245
246 case MBOX_STS_INTERMEDIATE_COMPLETION:
247 status = QLA_SUCCESS;
248 break;
249
250 case MBOX_STS_BUSY:
251 DEBUG2( printk("scsi%ld: %s: Cmd = %08X, ISP BUSY\n",
252 ha->host_no, __func__, mbx_cmd[0]));
253 ha->mailbox_timeout_count++;
254 break;
255
256 default:
257 DEBUG2(printk("scsi%ld: %s: **** FAILED, cmd = %08X, "
258 "sts = %08X ****\n", ha->host_no, __func__,
259 mbx_cmd[0], mbx_sts[0]));
260 break;
261 }
262 spin_unlock_irqrestore(&ha->hardware_lock, flags);
263
264mbox_exit:
477ffb9d 265 mutex_lock(&ha->mbox_sem);
afaf5a2d 266 clear_bit(AF_MBOX_COMMAND, &ha->flags);
afaf5a2d 267 mutex_unlock(&ha->mbox_sem);
477ffb9d 268 clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
afaf5a2d
DS		 269
270 return status;
271}
21033639 272
068237c8
TP		 273/**
274 * qla4xxx_get_minidump_template - Get the firmware template
275 * @ha: Pointer to host adapter structure.
276 * @phys_addr: dma address for template
277 *
278 * Obtain the minidump template from firmware during initialization
279 * as it may not be available when minidump is desired.
280 **/
281int qla4xxx_get_minidump_template(struct scsi_qla_host *ha,
282 dma_addr_t phys_addr)
283{
284 uint32_t mbox_cmd[MBOX_REG_COUNT];
285 uint32_t mbox_sts[MBOX_REG_COUNT];
286 int status;
287
288 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
289 memset(&mbox_sts, 0, sizeof(mbox_sts));
290
291 mbox_cmd[0] = MBOX_CMD_MINIDUMP;
292 mbox_cmd[1] = MINIDUMP_GET_TMPLT_SUBCOMMAND;
293 mbox_cmd[2] = LSDW(phys_addr);
294 mbox_cmd[3] = MSDW(phys_addr);
295 mbox_cmd[4] = ha->fw_dump_tmplt_size;
296 mbox_cmd[5] = 0;
297
298 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
299 &mbox_sts[0]);
300 if (status != QLA_SUCCESS) {
301 DEBUG2(ql4_printk(KERN_INFO, ha,
302 "scsi%ld: %s: Cmd = %08X, mbx[0] = 0x%04x, mbx[1] = 0x%04x\n",
303 ha->host_no, __func__, mbox_cmd[0],
304 mbox_sts[0], mbox_sts[1]));
305 }
306 return status;
307}
308
309/**
310 * qla4xxx_req_template_size - Get minidump template size from firmware.
311 * @ha: Pointer to host adapter structure.
312 **/
313int qla4xxx_req_template_size(struct scsi_qla_host *ha)
314{
315 uint32_t mbox_cmd[MBOX_REG_COUNT];
316 uint32_t mbox_sts[MBOX_REG_COUNT];
317 int status;
318
319 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
320 memset(&mbox_sts, 0, sizeof(mbox_sts));
321
322 mbox_cmd[0] = MBOX_CMD_MINIDUMP;
323 mbox_cmd[1] = MINIDUMP_GET_SIZE_SUBCOMMAND;
324
325 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 8, &mbox_cmd[0],
326 &mbox_sts[0]);
327 if (status == QLA_SUCCESS) {
328 ha->fw_dump_tmplt_size = mbox_sts[1];
329 DEBUG2(ql4_printk(KERN_INFO, ha,
330 "%s: sts[0]=0x%04x, template size=0x%04x, size_cm_02=0x%04x, size_cm_04=0x%04x, size_cm_08=0x%04x, size_cm_10=0x%04x, size_cm_FF=0x%04x, version=0x%04x\n",
331 __func__, mbox_sts[0], mbox_sts[1],
332 mbox_sts[2], mbox_sts[3], mbox_sts[4],
333 mbox_sts[5], mbox_sts[6], mbox_sts[7]));
334 if (ha->fw_dump_tmplt_size == 0)
335 status = QLA_ERROR;
336 } else {
337 ql4_printk(KERN_WARNING, ha,
338 "%s: Error sts[0]=0x%04x, mbx[1]=0x%04x\n",
339 __func__, mbox_sts[0], mbox_sts[1]);
340 status = QLA_ERROR;
341 }
342
343 return status;
344}
345
21033639
NJ		 346void qla4xxx_mailbox_premature_completion(struct scsi_qla_host *ha)
347{
348 set_bit(AF_FW_RECOVERY, &ha->flags);
349 ql4_printk(KERN_INFO, ha, "scsi%ld: %s: set FW RECOVERY!\n",
350 ha->host_no, __func__);
351
352 if (test_bit(AF_MBOX_COMMAND, &ha->flags)) {
353 if (test_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags)) {
354 complete(&ha->mbx_intr_comp);
355 ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
356 "recovery, doing premature completion of "
357 "mbx cmd\n", ha->host_no, __func__);
358
359 } else {
360 set_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
361 ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
362 "recovery, doing premature completion of "
363 "polling mbx cmd\n", ha->host_no, __func__);
364 }
365 }
366}
afaf5a2d 367
f4f5df23 368static uint8_t
2a49a78e
VC		 369qla4xxx_set_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
370 uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
371{
372 memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
373 memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
2657c800
SS		 374
375 if (is_qla8022(ha))
376 qla4_8xxx_wr_32(ha, ha->nx_db_wr_ptr, 0);
377
2a49a78e
VC		 378 mbox_cmd[0] = MBOX_CMD_INITIALIZE_FIRMWARE;
379 mbox_cmd[1] = 0;
380 mbox_cmd[2] = LSDW(init_fw_cb_dma);
381 mbox_cmd[3] = MSDW(init_fw_cb_dma);
382 mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
383 mbox_cmd[5] = (IFCB_VER_MAX << 8) | IFCB_VER_MIN;
384
385 if (qla4xxx_mailbox_command(ha, 6, 6, mbox_cmd, mbox_sts) !=
386 QLA_SUCCESS) {
387 DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
388 "MBOX_CMD_INITIALIZE_FIRMWARE"
389 " failed w/ status %04X\n",
390 ha->host_no, __func__, mbox_sts[0]));
391 return QLA_ERROR;
392 }
393 return QLA_SUCCESS;
394}
395
d00efe3f 396uint8_t
2a49a78e
VC		 397qla4xxx_get_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
398 uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
399{
400 memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
401 memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
402 mbox_cmd[0] = MBOX_CMD_GET_INIT_FW_CTRL_BLOCK;
403 mbox_cmd[2] = LSDW(init_fw_cb_dma);
404 mbox_cmd[3] = MSDW(init_fw_cb_dma);
405 mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
406
407 if (qla4xxx_mailbox_command(ha, 5, 5, mbox_cmd, mbox_sts) !=
408 QLA_SUCCESS) {
409 DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
410 "MBOX_CMD_GET_INIT_FW_CTRL_BLOCK"
411 " failed w/ status %04X\n",
412 ha->host_no, __func__, mbox_sts[0]));
413 return QLA_ERROR;
414 }
415 return QLA_SUCCESS;
416}
417
f4f5df23 418static void
2a49a78e 419qla4xxx_update_local_ip(struct scsi_qla_host *ha,
2bab08fc 420 struct addr_ctrl_blk *init_fw_cb)
2a49a78e 421{
2bab08fc
VC		 422 ha->ip_config.tcp_options = le16_to_cpu(init_fw_cb->ipv4_tcp_opts);
423 ha->ip_config.ipv4_options = le16_to_cpu(init_fw_cb->ipv4_ip_opts);
424 ha->ip_config.ipv4_addr_state =
425 le16_to_cpu(init_fw_cb->ipv4_addr_state);
943c157b
VC		 426 ha->ip_config.eth_mtu_size =
427 le16_to_cpu(init_fw_cb->eth_mtu_size);
2ada7fc5 428 ha->ip_config.ipv4_port = le16_to_cpu(init_fw_cb->ipv4_port);
2bab08fc
VC		 429
430 if (ha->acb_version == ACB_SUPPORTED) {
431 ha->ip_config.ipv6_options = le16_to_cpu(init_fw_cb->ipv6_opts);
432 ha->ip_config.ipv6_addl_options =
433 le16_to_cpu(init_fw_cb->ipv6_addtl_opts);
434 }
435
2a49a78e 436 /* Save IPv4 Address Info */
2bab08fc
VC		 437 memcpy(ha->ip_config.ip_address, init_fw_cb->ipv4_addr,
438 min(sizeof(ha->ip_config.ip_address),
439 sizeof(init_fw_cb->ipv4_addr)));
440 memcpy(ha->ip_config.subnet_mask, init_fw_cb->ipv4_subnet,
441 min(sizeof(ha->ip_config.subnet_mask),
442 sizeof(init_fw_cb->ipv4_subnet)));
443 memcpy(ha->ip_config.gateway, init_fw_cb->ipv4_gw_addr,
444 min(sizeof(ha->ip_config.gateway),
445 sizeof(init_fw_cb->ipv4_gw_addr)));
2a49a78e 446
6ac73e8c
VC		 447 ha->ip_config.ipv4_vlan_tag = be16_to_cpu(init_fw_cb->ipv4_vlan_tag);
448
2a49a78e
VC		 449 if (is_ipv6_enabled(ha)) {
450 /* Save IPv6 Address */
2bab08fc
VC		 451 ha->ip_config.ipv6_link_local_state =
452 le16_to_cpu(init_fw_cb->ipv6_lnk_lcl_addr_state);
453 ha->ip_config.ipv6_addr0_state =
454 le16_to_cpu(init_fw_cb->ipv6_addr0_state);
455 ha->ip_config.ipv6_addr1_state =
456 le16_to_cpu(init_fw_cb->ipv6_addr1_state);
457 ha->ip_config.ipv6_default_router_state =
458 le16_to_cpu(init_fw_cb->ipv6_dflt_rtr_state);
459 ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[0] = 0xFE;
460 ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[1] = 0x80;
461
462 memcpy(&ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[8],
463 init_fw_cb->ipv6_if_id,
464 min(sizeof(ha->ip_config.ipv6_link_local_addr)/2,
465 sizeof(init_fw_cb->ipv6_if_id)));
466 memcpy(&ha->ip_config.ipv6_addr0, init_fw_cb->ipv6_addr0,
467 min(sizeof(ha->ip_config.ipv6_addr0),
468 sizeof(init_fw_cb->ipv6_addr0)));
469 memcpy(&ha->ip_config.ipv6_addr1, init_fw_cb->ipv6_addr1,
470 min(sizeof(ha->ip_config.ipv6_addr1),
471 sizeof(init_fw_cb->ipv6_addr1)));
472 memcpy(&ha->ip_config.ipv6_default_router_addr,
473 init_fw_cb->ipv6_dflt_rtr_addr,
474 min(sizeof(ha->ip_config.ipv6_default_router_addr),
475 sizeof(init_fw_cb->ipv6_dflt_rtr_addr)));
6ac73e8c
VC		 476 ha->ip_config.ipv6_vlan_tag =
477 be16_to_cpu(init_fw_cb->ipv6_vlan_tag);
2ada7fc5 478 ha->ip_config.ipv6_port = le16_to_cpu(init_fw_cb->ipv6_port);
2a49a78e
VC		 479 }
480}
481
d00efe3f 482uint8_t
2a49a78e
VC		 483qla4xxx_update_local_ifcb(struct scsi_qla_host *ha,
484 uint32_t *mbox_cmd,
485 uint32_t *mbox_sts,
486 struct addr_ctrl_blk *init_fw_cb,
487 dma_addr_t init_fw_cb_dma)
488{
489 if (qla4xxx_get_ifcb(ha, mbox_cmd, mbox_sts, init_fw_cb_dma)
490 != QLA_SUCCESS) {
491 DEBUG2(printk(KERN_WARNING
492 "scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
493 ha->host_no, __func__));
494 return QLA_ERROR;
495 }
496
497 DEBUG2(qla4xxx_dump_buffer(init_fw_cb, sizeof(struct addr_ctrl_blk)));
498
499 /* Save some info in adapter structure. */
500 ha->acb_version = init_fw_cb->acb_version;
501 ha->firmware_options = le16_to_cpu(init_fw_cb->fw_options);
2a49a78e
VC		 502 ha->heartbeat_interval = init_fw_cb->hb_interval;
503 memcpy(ha->name_string, init_fw_cb->iscsi_name,
504 min(sizeof(ha->name_string),
505 sizeof(init_fw_cb->iscsi_name)));
13483730 506 ha->def_timeout = le16_to_cpu(init_fw_cb->def_timeout);
2a49a78e
VC		 507 /*memcpy(ha->alias, init_fw_cb->Alias,
508 min(sizeof(ha->alias), sizeof(init_fw_cb->Alias)));*/
509
2a49a78e
VC		 510 qla4xxx_update_local_ip(ha, init_fw_cb);
511
512 return QLA_SUCCESS;
513}
514
afaf5a2d
DS		 515/**
516 * qla4xxx_initialize_fw_cb - initializes firmware control block.
517 * @ha: Pointer to host adapter structure.
518 **/
519int qla4xxx_initialize_fw_cb(struct scsi_qla_host * ha)
520{
2a49a78e 521 struct addr_ctrl_blk *init_fw_cb;
afaf5a2d
DS		 522 dma_addr_t init_fw_cb_dma;
523 uint32_t mbox_cmd[MBOX_REG_COUNT];
524 uint32_t mbox_sts[MBOX_REG_COUNT];
525 int status = QLA_ERROR;
526
527 init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
2a49a78e 528 sizeof(struct addr_ctrl_blk),
afaf5a2d
DS		 529 &init_fw_cb_dma, GFP_KERNEL);
530 if (init_fw_cb == NULL) {
531 DEBUG2(printk("scsi%ld: %s: Unable to alloc init_cb\n",
532 ha->host_no, __func__));
beabe7c1 533 goto exit_init_fw_cb_no_free;
afaf5a2d 534 }
2a49a78e 535 memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
afaf5a2d
DS		 536
537 /* Get Initialize Firmware Control Block. */
538 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
539 memset(&mbox_sts, 0, sizeof(mbox_sts));
c0e344c9 540
2a49a78e 541 if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
afaf5a2d
DS		 542 QLA_SUCCESS) {
543 dma_free_coherent(&ha->pdev->dev,
2a49a78e 544 sizeof(struct addr_ctrl_blk),
afaf5a2d 545 init_fw_cb, init_fw_cb_dma);
2a49a78e 546 goto exit_init_fw_cb;
afaf5a2d
DS		 547 }
548
549 /* Initialize request and response queues. */
550 qla4xxx_init_rings(ha);
551
552 /* Fill in the request and response queue information. */
2a49a78e
VC		 553 init_fw_cb->rqq_consumer_idx = cpu_to_le16(ha->request_out);
554 init_fw_cb->compq_producer_idx = cpu_to_le16(ha->response_in);
555 init_fw_cb->rqq_len = __constant_cpu_to_le16(REQUEST_QUEUE_DEPTH);
556 init_fw_cb->compq_len = __constant_cpu_to_le16(RESPONSE_QUEUE_DEPTH);
557 init_fw_cb->rqq_addr_lo = cpu_to_le32(LSDW(ha->request_dma));
558 init_fw_cb->rqq_addr_hi = cpu_to_le32(MSDW(ha->request_dma));
559 init_fw_cb->compq_addr_lo = cpu_to_le32(LSDW(ha->response_dma));
560 init_fw_cb->compq_addr_hi = cpu_to_le32(MSDW(ha->response_dma));
561 init_fw_cb->shdwreg_addr_lo = cpu_to_le32(LSDW(ha->shadow_regs_dma));
562 init_fw_cb->shdwreg_addr_hi = cpu_to_le32(MSDW(ha->shadow_regs_dma));
afaf5a2d
DS		 563
564 /* Set up required options. */
2a49a78e 565 init_fw_cb->fw_options |=
afaf5a2d
DS		 566 __constant_cpu_to_le16(FWOPT_SESSION_MODE |
567 FWOPT_INITIATOR_MODE);
2657c800
SS		 568
569 if (is_qla8022(ha))
570 init_fw_cb->fw_options |=
571 __constant_cpu_to_le16(FWOPT_ENABLE_CRBDB);
572
2a49a78e 573 init_fw_cb->fw_options &= __constant_cpu_to_le16(~FWOPT_TARGET_MODE);
afaf5a2d 574
d32cee3c
PM		 575 init_fw_cb->add_fw_options = 0;
576 init_fw_cb->add_fw_options |=
b3a271a9
MR		 577 __constant_cpu_to_le16(ADFWOPT_SERIALIZE_TASK_MGMT);
578 init_fw_cb->add_fw_options |=
579 __constant_cpu_to_le16(ADFWOPT_AUTOCONN_DISABLE);
d32cee3c 580
2a49a78e
VC		 581 if (qla4xxx_set_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma)
582 != QLA_SUCCESS) {
583 DEBUG2(printk(KERN_WARNING
584 "scsi%ld: %s: Failed to set init_fw_ctrl_blk\n",
585 ha->host_no, __func__));
586 goto exit_init_fw_cb;
587 }
c0e344c9 588
2a49a78e
VC		 589 if (qla4xxx_update_local_ifcb(ha, &mbox_cmd[0], &mbox_sts[0],
590 init_fw_cb, init_fw_cb_dma) != QLA_SUCCESS) {
591 DEBUG2(printk("scsi%ld: %s: Failed to update local ifcb\n",
592 ha->host_no, __func__));
593 goto exit_init_fw_cb;
afaf5a2d 594 }
2a49a78e
VC		 595 status = QLA_SUCCESS;
596
597exit_init_fw_cb:
598 dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
599 init_fw_cb, init_fw_cb_dma);
beabe7c1 600exit_init_fw_cb_no_free:
afaf5a2d
DS		 601 return status;
602}
603
604/**
605 * qla4xxx_get_dhcp_ip_address - gets HBA ip address via DHCP
606 * @ha: Pointer to host adapter structure.
607 **/
608int qla4xxx_get_dhcp_ip_address(struct scsi_qla_host * ha)
609{
2a49a78e 610 struct addr_ctrl_blk *init_fw_cb;
afaf5a2d
DS		 611 dma_addr_t init_fw_cb_dma;
612 uint32_t mbox_cmd[MBOX_REG_COUNT];
613 uint32_t mbox_sts[MBOX_REG_COUNT];
614
615 init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
2a49a78e 616 sizeof(struct addr_ctrl_blk),
afaf5a2d
DS		 617 &init_fw_cb_dma, GFP_KERNEL);
618 if (init_fw_cb == NULL) {
619 printk("scsi%ld: %s: Unable to alloc init_cb\n", ha->host_no,
620 __func__);
beabe7c1 621 return QLA_ERROR;
afaf5a2d
DS		 622 }
623
624 /* Get Initialize Firmware Control Block. */
2a49a78e
VC		 625 memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
626 if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
afaf5a2d
DS		 627 QLA_SUCCESS) {
628 DEBUG2(printk("scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
629 ha->host_no, __func__));
630 dma_free_coherent(&ha->pdev->dev,
2a49a78e 631 sizeof(struct addr_ctrl_blk),
afaf5a2d
DS		 632 init_fw_cb, init_fw_cb_dma);
633 return QLA_ERROR;
634 }
635
636 /* Save IP Address. */
2a49a78e
VC		 637 qla4xxx_update_local_ip(ha, init_fw_cb);
638 dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
639 init_fw_cb, init_fw_cb_dma);
afaf5a2d
DS		 640
641 return QLA_SUCCESS;
642}
643
644/**
645 * qla4xxx_get_firmware_state - gets firmware state of HBA
646 * @ha: Pointer to host adapter structure.
647 **/
648int qla4xxx_get_firmware_state(struct scsi_qla_host * ha)
649{
650 uint32_t mbox_cmd[MBOX_REG_COUNT];
651 uint32_t mbox_sts[MBOX_REG_COUNT];
652
653 /* Get firmware version */
654 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
655 memset(&mbox_sts, 0, sizeof(mbox_sts));
c0e344c9 656
afaf5a2d 657 mbox_cmd[0] = MBOX_CMD_GET_FW_STATE;
c0e344c9
DS		 658
659 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 4, &mbox_cmd[0], &mbox_sts[0]) !=
afaf5a2d
DS		 660 QLA_SUCCESS) {
661 DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATE failed w/ "
662 "status %04X\n", ha->host_no, __func__,
663 mbox_sts[0]));
664 return QLA_ERROR;
665 }
666 ha->firmware_state = mbox_sts[1];
667 ha->board_id = mbox_sts[2];
668 ha->addl_fw_state = mbox_sts[3];
669 DEBUG2(printk("scsi%ld: %s firmware_state=0x%x\n",
670 ha->host_no, __func__, ha->firmware_state);)
671
f4f5df23 672 return QLA_SUCCESS;
afaf5a2d
DS		 673}
674
675/**
676 * qla4xxx_get_firmware_status - retrieves firmware status
677 * @ha: Pointer to host adapter structure.
678 **/
679int qla4xxx_get_firmware_status(struct scsi_qla_host * ha)
680{
681 uint32_t mbox_cmd[MBOX_REG_COUNT];
682 uint32_t mbox_sts[MBOX_REG_COUNT];
683
684 /* Get firmware version */
685 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
686 memset(&mbox_sts, 0, sizeof(mbox_sts));
c0e344c9 687
afaf5a2d 688 mbox_cmd[0] = MBOX_CMD_GET_FW_STATUS;
c0e344c9
DS		 689
690 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0], &mbox_sts[0]) !=
afaf5a2d
DS		 691 QLA_SUCCESS) {
692 DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATUS failed w/ "
693 "status %04X\n", ha->host_no, __func__,
694 mbox_sts[0]));
695 return QLA_ERROR;
696 }
f4f5df23 697
3573bfb2 698 ql4_printk(KERN_INFO, ha, "%ld firmware IOCBs available (%d).\n",
f581a3f7 699 ha->host_no, mbox_sts[2]);
f4f5df23 700
afaf5a2d
DS		 701 return QLA_SUCCESS;
702}
703
704/**
705 * qla4xxx_get_fwddb_entry - retrieves firmware ddb entry
706 * @ha: Pointer to host adapter structure.
707 * @fw_ddb_index: Firmware's device database index
708 * @fw_ddb_entry: Pointer to firmware's device database entry structure
709 * @num_valid_ddb_entries: Pointer to number of valid ddb entries
710 * @next_ddb_index: Pointer to next valid device database index
711 * @fw_ddb_device_state: Pointer to device state
712 **/
713int qla4xxx_get_fwddb_entry(struct scsi_qla_host *ha,
714 uint16_t fw_ddb_index,
715 struct dev_db_entry *fw_ddb_entry,
716 dma_addr_t fw_ddb_entry_dma,
717 uint32_t *num_valid_ddb_entries,
718 uint32_t *next_ddb_index,
719 uint32_t *fw_ddb_device_state,
720 uint32_t *conn_err_detail,
721 uint16_t *tcp_source_port_num,
722 uint16_t *connection_id)
723{
724 int status = QLA_ERROR;
2a49a78e 725 uint16_t options;
afaf5a2d
DS		 726 uint32_t mbox_cmd[MBOX_REG_COUNT];
727 uint32_t mbox_sts[MBOX_REG_COUNT];
728
729 /* Make sure the device index is valid */
730 if (fw_ddb_index >= MAX_DDB_ENTRIES) {
f4f5df23 731 DEBUG2(printk("scsi%ld: %s: ddb [%d] out of range.\n",
afaf5a2d
DS		 732 ha->host_no, __func__, fw_ddb_index));
733 goto exit_get_fwddb;
734 }
735 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
736 memset(&mbox_sts, 0, sizeof(mbox_sts));
981c982c
LC		 737 if (fw_ddb_entry)
738 memset(fw_ddb_entry, 0, sizeof(struct dev_db_entry));
c0e344c9 739
afaf5a2d
DS		 740 mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY;
741 mbox_cmd[1] = (uint32_t) fw_ddb_index;
742 mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
743 mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
c0e344c9
DS		 744 mbox_cmd[4] = sizeof(struct dev_db_entry);
745
746 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 7, &mbox_cmd[0], &mbox_sts[0]) ==
afaf5a2d
DS		 747 QLA_ERROR) {
748 DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_DATABASE_ENTRY failed"
749 " with status 0x%04X\n", ha->host_no, __func__,
750 mbox_sts[0]));
751 goto exit_get_fwddb;
752 }
753 if (fw_ddb_index != mbox_sts[1]) {
f4f5df23 754 DEBUG2(printk("scsi%ld: %s: ddb mismatch [%d] != [%d].\n",
afaf5a2d
DS		 755 ha->host_no, __func__, fw_ddb_index,
756 mbox_sts[1]));
757 goto exit_get_fwddb;
758 }
759 if (fw_ddb_entry) {
2a49a78e
VC		 760 options = le16_to_cpu(fw_ddb_entry->options);
761 if (options & DDB_OPT_IPV6_DEVICE) {
c2660df3 762 ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
2a49a78e
VC		 763 "Next %d State %04x ConnErr %08x %pI6 "
764 ":%04d \"%s\"\n", __func__, fw_ddb_index,
765 mbox_sts[0], mbox_sts[2], mbox_sts[3],
766 mbox_sts[4], mbox_sts[5],
767 fw_ddb_entry->ip_addr,
768 le16_to_cpu(fw_ddb_entry->port),
769 fw_ddb_entry->iscsi_name);
770 } else {
c2660df3 771 ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
2a49a78e
VC		 772 "Next %d State %04x ConnErr %08x %pI4 "
773 ":%04d \"%s\"\n", __func__, fw_ddb_index,
774 mbox_sts[0], mbox_sts[2], mbox_sts[3],
775 mbox_sts[4], mbox_sts[5],
776 fw_ddb_entry->ip_addr,
777 le16_to_cpu(fw_ddb_entry->port),
778 fw_ddb_entry->iscsi_name);
779 }
afaf5a2d
DS		 780 }
781 if (num_valid_ddb_entries)
782 *num_valid_ddb_entries = mbox_sts[2];
783 if (next_ddb_index)
784 *next_ddb_index = mbox_sts[3];
785 if (fw_ddb_device_state)
786 *fw_ddb_device_state = mbox_sts[4];
787
788 /*
789 * RA: This mailbox has been changed to pass connection error and
790 * details. Its true for ISP4010 as per Version E - Not sure when it
791 * was changed. Get the time2wait from the fw_dd_entry field :
792 * default_time2wait which we call it as minTime2Wait DEV_DB_ENTRY
793 * struct.
794 */
795 if (conn_err_detail)
796 *conn_err_detail = mbox_sts[5];
797 if (tcp_source_port_num)
1482338f 798 *tcp_source_port_num = (uint16_t) (mbox_sts[6] >> 16);
afaf5a2d
DS		 799 if (connection_id)
800 *connection_id = (uint16_t) mbox_sts[6] & 0x00FF;
801 status = QLA_SUCCESS;
802
803exit_get_fwddb:
804 return status;
805}
806
b3a271a9
MR		 807int qla4xxx_conn_open(struct scsi_qla_host *ha, uint16_t fw_ddb_index)
808{
809 uint32_t mbox_cmd[MBOX_REG_COUNT];
810 uint32_t mbox_sts[MBOX_REG_COUNT];
811 int status;
812
813 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
814 memset(&mbox_sts, 0, sizeof(mbox_sts));
815
816 mbox_cmd[0] = MBOX_CMD_CONN_OPEN;
817 mbox_cmd[1] = fw_ddb_index;
818
819 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
820 &mbox_sts[0]);
821 DEBUG2(ql4_printk(KERN_INFO, ha,
822 "%s: status = %d mbx0 = 0x%x mbx1 = 0x%x\n",
823 __func__, status, mbox_sts[0], mbox_sts[1]));
824 return status;
825}
826
afaf5a2d
DS		 827/**
828 * qla4xxx_set_fwddb_entry - sets a ddb entry.
829 * @ha: Pointer to host adapter structure.
830 * @fw_ddb_index: Firmware's device database index
b3a271a9
MR		 831 * @fw_ddb_entry_dma: dma address of ddb entry
832 * @mbx_sts: mailbox 0 to be returned or NULL
afaf5a2d
DS		 833 *
834 * This routine initializes or updates the adapter's device database
b3a271a9 835 * entry for the specified device.
afaf5a2d
DS		 836 **/
837int qla4xxx_set_ddb_entry(struct scsi_qla_host * ha, uint16_t fw_ddb_index,
b3a271a9 838 dma_addr_t fw_ddb_entry_dma, uint32_t *mbx_sts)
afaf5a2d
DS		 839{
840 uint32_t mbox_cmd[MBOX_REG_COUNT];
841 uint32_t mbox_sts[MBOX_REG_COUNT];
f4f5df23 842 int status;
afaf5a2d
DS		 843
844 /* Do not wait for completion. The firmware will send us an
845 * ASTS_DATABASE_CHANGED (0x8014) to notify us of the login status.
846 */
847 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
848 memset(&mbox_sts, 0, sizeof(mbox_sts));
849
850 mbox_cmd[0] = MBOX_CMD_SET_DATABASE_ENTRY;
851 mbox_cmd[1] = (uint32_t) fw_ddb_index;
852 mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
853 mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
c0e344c9 854 mbox_cmd[4] = sizeof(struct dev_db_entry);
afaf5a2d 855
f4f5df23 856 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
b3a271a9
MR		 857 &mbox_sts[0]);
858 if (mbx_sts)
859 *mbx_sts = mbox_sts[0];
f4f5df23
VC		 860 DEBUG2(printk("scsi%ld: %s: status=%d mbx0=0x%x mbx4=0x%x\n",
861 ha->host_no, __func__, status, mbox_sts[0], mbox_sts[4]);)
862
863 return status;
afaf5a2d
DS		 864}
865
b3a271a9
MR		 866int qla4xxx_session_logout_ddb(struct scsi_qla_host *ha,
867 struct ddb_entry *ddb_entry, int options)
868{
869 int status;
870 uint32_t mbox_cmd[MBOX_REG_COUNT];
871 uint32_t mbox_sts[MBOX_REG_COUNT];
872
873 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
874 memset(&mbox_sts, 0, sizeof(mbox_sts));
875
876 mbox_cmd[0] = MBOX_CMD_CONN_CLOSE_SESS_LOGOUT;
877 mbox_cmd[1] = ddb_entry->fw_ddb_index;
878 mbox_cmd[3] = options;
879
880 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
881 &mbox_sts[0]);
882 if (status != QLA_SUCCESS) {
883 DEBUG2(ql4_printk(KERN_INFO, ha,
884 "%s: MBOX_CMD_CONN_CLOSE_SESS_LOGOUT "
885 "failed sts %04X %04X", __func__,
886 mbox_sts[0], mbox_sts[1]));
887 }
888
889 return status;
890}
891
afaf5a2d
DS		 892/**
893 * qla4xxx_get_crash_record - retrieves crash record.
894 * @ha: Pointer to host adapter structure.
895 *
896 * This routine retrieves a crash record from the QLA4010 after an 8002h aen.
897 **/
898void qla4xxx_get_crash_record(struct scsi_qla_host * ha)
899{
900 uint32_t mbox_cmd[MBOX_REG_COUNT];
901 uint32_t mbox_sts[MBOX_REG_COUNT];
902 struct crash_record *crash_record = NULL;
903 dma_addr_t crash_record_dma = 0;
904 uint32_t crash_record_size = 0;
c0e344c9 905
afaf5a2d
DS		 906 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
907 memset(&mbox_sts, 0, sizeof(mbox_cmd));
908
909 /* Get size of crash record. */
910 mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
c0e344c9
DS		 911
912 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
afaf5a2d
DS		 913 QLA_SUCCESS) {
914 DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve size!\n",
915 ha->host_no, __func__));
916 goto exit_get_crash_record;
917 }
918 crash_record_size = mbox_sts[4];
919 if (crash_record_size == 0) {
920 DEBUG2(printk("scsi%ld: %s: ERROR: Crash record size is 0!\n",
921 ha->host_no, __func__));
922 goto exit_get_crash_record;
923 }
924
925 /* Alloc Memory for Crash Record. */
926 crash_record = dma_alloc_coherent(&ha->pdev->dev, crash_record_size,
927 &crash_record_dma, GFP_KERNEL);
928 if (crash_record == NULL)
929 goto exit_get_crash_record;
930
931 /* Get Crash Record. */
c0e344c9
DS		 932 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
933 memset(&mbox_sts, 0, sizeof(mbox_cmd));
934
afaf5a2d
DS		 935 mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
936 mbox_cmd[2] = LSDW(crash_record_dma);
937 mbox_cmd[3] = MSDW(crash_record_dma);
938 mbox_cmd[4] = crash_record_size;
c0e344c9
DS		 939
940 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
afaf5a2d
DS		 941 QLA_SUCCESS)
942 goto exit_get_crash_record;
943
944 /* Dump Crash Record. */
945
946exit_get_crash_record:
947 if (crash_record)
948 dma_free_coherent(&ha->pdev->dev, crash_record_size,
949 crash_record, crash_record_dma);
950}
951
952/**
953 * qla4xxx_get_conn_event_log - retrieves connection event log
954 * @ha: Pointer to host adapter structure.
955 **/
956void qla4xxx_get_conn_event_log(struct scsi_qla_host * ha)
957{
958 uint32_t mbox_cmd[MBOX_REG_COUNT];
959 uint32_t mbox_sts[MBOX_REG_COUNT];
960 struct conn_event_log_entry *event_log = NULL;
961 dma_addr_t event_log_dma = 0;
962 uint32_t event_log_size = 0;
963 uint32_t num_valid_entries;
964 uint32_t oldest_entry = 0;
965 uint32_t max_event_log_entries;
966 uint8_t i;
967
afaf5a2d
DS		 968 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
969 memset(&mbox_sts, 0, sizeof(mbox_cmd));
970
971 /* Get size of crash record. */
972 mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
c0e344c9
DS		 973
974 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
afaf5a2d
DS		 975 QLA_SUCCESS)
976 goto exit_get_event_log;
977
978 event_log_size = mbox_sts[4];
979 if (event_log_size == 0)
980 goto exit_get_event_log;
981
982 /* Alloc Memory for Crash Record. */
983 event_log = dma_alloc_coherent(&ha->pdev->dev, event_log_size,
984 &event_log_dma, GFP_KERNEL);
985 if (event_log == NULL)
986 goto exit_get_event_log;
987
988 /* Get Crash Record. */
c0e344c9
DS		 989 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
990 memset(&mbox_sts, 0, sizeof(mbox_cmd));
991
afaf5a2d
DS		 992 mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
993 mbox_cmd[2] = LSDW(event_log_dma);
994 mbox_cmd[3] = MSDW(event_log_dma);
c0e344c9
DS		 995
996 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
afaf5a2d
DS		 997 QLA_SUCCESS) {
998 DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve event "
999 "log!\n", ha->host_no, __func__));
1000 goto exit_get_event_log;
1001 }
1002
1003 /* Dump Event Log. */
1004 num_valid_entries = mbox_sts[1];
1005
1006 max_event_log_entries = event_log_size /
1007 sizeof(struct conn_event_log_entry);
1008
1009 if (num_valid_entries > max_event_log_entries)
1010 oldest_entry = num_valid_entries % max_event_log_entries;
1011
1012 DEBUG3(printk("scsi%ld: Connection Event Log Dump (%d entries):\n",
1013 ha->host_no, num_valid_entries));
1014
11010fec 1015 if (ql4xextended_error_logging == 3) {
afaf5a2d
DS		 1016 if (oldest_entry == 0) {
1017 /* Circular Buffer has not wrapped around */
1018 for (i=0; i < num_valid_entries; i++) {
1019 qla4xxx_dump_buffer((uint8_t *)event_log+
1020 (i*sizeof(*event_log)),
1021 sizeof(*event_log));
1022 }
1023 }
1024 else {
1025 /* Circular Buffer has wrapped around -
1026 * display accordingly*/
1027 for (i=oldest_entry; i < max_event_log_entries; i++) {
1028 qla4xxx_dump_buffer((uint8_t *)event_log+
1029 (i*sizeof(*event_log)),
1030 sizeof(*event_log));
1031 }
1032 for (i=0; i < oldest_entry; i++) {
1033 qla4xxx_dump_buffer((uint8_t *)event_log+
1034 (i*sizeof(*event_log)),
1035 sizeof(*event_log));
1036 }
1037 }
1038 }
1039
1040exit_get_event_log:
1041 if (event_log)
1042 dma_free_coherent(&ha->pdev->dev, event_log_size, event_log,
1043 event_log_dma);
1044}
1045
09a0f719
VC		 1046/**
1047 * qla4xxx_abort_task - issues Abort Task
1048 * @ha: Pointer to host adapter structure.
1049 * @srb: Pointer to srb entry
1050 *
1051 * This routine performs a LUN RESET on the specified target/lun.
1052 * The caller must ensure that the ddb_entry and lun_entry pointers
1053 * are valid before calling this routine.
1054 **/
1055int qla4xxx_abort_task(struct scsi_qla_host *ha, struct srb *srb)
1056{
1057 uint32_t mbox_cmd[MBOX_REG_COUNT];
1058 uint32_t mbox_sts[MBOX_REG_COUNT];
1059 struct scsi_cmnd *cmd = srb->cmd;
1060 int status = QLA_SUCCESS;
1061 unsigned long flags = 0;
1062 uint32_t index;
1063
1064 /*
1065 * Send abort task command to ISP, so that the ISP will return
1066 * request with ABORT status
1067 */
1068 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1069 memset(&mbox_sts, 0, sizeof(mbox_sts));
1070
1071 spin_lock_irqsave(&ha->hardware_lock, flags);
1072 index = (unsigned long)(unsigned char *)cmd->host_scribble;
1073 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1074
1075 /* Firmware already posted completion on response queue */
1076 if (index == MAX_SRBS)
1077 return status;
1078
1079 mbox_cmd[0] = MBOX_CMD_ABORT_TASK;
6790d4fe 1080 mbox_cmd[1] = srb->ddb->fw_ddb_index;
09a0f719
VC		 1081 mbox_cmd[2] = index;
1082 /* Immediate Command Enable */
1083 mbox_cmd[5] = 0x01;
1084
1085 qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
1086 &mbox_sts[0]);
1087 if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE) {
1088 status = QLA_ERROR;
1089
1090 DEBUG2(printk(KERN_WARNING "scsi%ld:%d:%d: abort task FAILED: "
1091 "mbx0=%04X, mb1=%04X, mb2=%04X, mb3=%04X, mb4=%04X\n",
1092 ha->host_no, cmd->device->id, cmd->device->lun, mbox_sts[0],
1093 mbox_sts[1], mbox_sts[2], mbox_sts[3], mbox_sts[4]));
1094 }
1095
1096 return status;
1097}
1098
afaf5a2d
DS		 1099/**
1100 * qla4xxx_reset_lun - issues LUN Reset
1101 * @ha: Pointer to host adapter structure.
f4f5df23
VC		 1102 * @ddb_entry: Pointer to device database entry
1103 * @lun: lun number
afaf5a2d
DS		 1104 *
1105 * This routine performs a LUN RESET on the specified target/lun.
1106 * The caller must ensure that the ddb_entry and lun_entry pointers
1107 * are valid before calling this routine.
1108 **/
1109int qla4xxx_reset_lun(struct scsi_qla_host * ha, struct ddb_entry * ddb_entry,
1110 int lun)
1111{
1112 uint32_t mbox_cmd[MBOX_REG_COUNT];
1113 uint32_t mbox_sts[MBOX_REG_COUNT];
1114 int status = QLA_SUCCESS;
1115
1116 DEBUG2(printk("scsi%ld:%d:%d: lun reset issued\n", ha->host_no,
f4f5df23 1117 ddb_entry->fw_ddb_index, lun));
afaf5a2d
DS		 1118
1119 /*
1120 * Send lun reset command to ISP, so that the ISP will return all
1121 * outstanding requests with RESET status
1122 */
1123 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1124 memset(&mbox_sts, 0, sizeof(mbox_sts));
c0e344c9 1125
afaf5a2d
DS		 1126 mbox_cmd[0] = MBOX_CMD_LUN_RESET;
1127 mbox_cmd[1] = ddb_entry->fw_ddb_index;
1128 mbox_cmd[2] = lun << 8;
1129 mbox_cmd[5] = 0x01; /* Immediate Command Enable */
c0e344c9
DS		 1130
1131 qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]);
afaf5a2d
DS		 1132 if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
1133 mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
1134 status = QLA_ERROR;
1135
1136 return status;
1137}
1138
ce545039
MC		 1139/**
1140 * qla4xxx_reset_target - issues target Reset
1141 * @ha: Pointer to host adapter structure.
1142 * @db_entry: Pointer to device database entry
1143 * @un_entry: Pointer to lun entry structure
1144 *
1145 * This routine performs a TARGET RESET on the specified target.
1146 * The caller must ensure that the ddb_entry pointers
1147 * are valid before calling this routine.
1148 **/
1149int qla4xxx_reset_target(struct scsi_qla_host *ha,
1150 struct ddb_entry *ddb_entry)
1151{
1152 uint32_t mbox_cmd[MBOX_REG_COUNT];
1153 uint32_t mbox_sts[MBOX_REG_COUNT];
1154 int status = QLA_SUCCESS;
1155
1156 DEBUG2(printk("scsi%ld:%d: target reset issued\n", ha->host_no,
f4f5df23 1157 ddb_entry->fw_ddb_index));
ce545039
MC		 1158
1159 /*
1160 * Send target reset command to ISP, so that the ISP will return all
1161 * outstanding requests with RESET status
1162 */
1163 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1164 memset(&mbox_sts, 0, sizeof(mbox_sts));
1165
1166 mbox_cmd[0] = MBOX_CMD_TARGET_WARM_RESET;
1167 mbox_cmd[1] = ddb_entry->fw_ddb_index;
1168 mbox_cmd[5] = 0x01; /* Immediate Command Enable */
1169
1170 qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
1171 &mbox_sts[0]);
1172 if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
1173 mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
1174 status = QLA_ERROR;
1175
1176 return status;
1177}
afaf5a2d
DS		 1178
1179int qla4xxx_get_flash(struct scsi_qla_host * ha, dma_addr_t dma_addr,
1180 uint32_t offset, uint32_t len)
1181{
1182 uint32_t mbox_cmd[MBOX_REG_COUNT];
1183 uint32_t mbox_sts[MBOX_REG_COUNT];
1184
1185 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1186 memset(&mbox_sts, 0, sizeof(mbox_sts));
c0e344c9 1187
afaf5a2d
DS		 1188 mbox_cmd[0] = MBOX_CMD_READ_FLASH;
1189 mbox_cmd[1] = LSDW(dma_addr);
1190 mbox_cmd[2] = MSDW(dma_addr);
1191 mbox_cmd[3] = offset;
1192 mbox_cmd[4] = len;
c0e344c9
DS		 1193
1194 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0], &mbox_sts[0]) !=
afaf5a2d
DS		 1195 QLA_SUCCESS) {
1196 DEBUG2(printk("scsi%ld: %s: MBOX_CMD_READ_FLASH, failed w/ "
1197 "status %04X %04X, offset %08x, len %08x\n", ha->host_no,
1198 __func__, mbox_sts[0], mbox_sts[1], offset, len));
1199 return QLA_ERROR;
1200 }
1201 return QLA_SUCCESS;
1202}
1203
1204/**
7ad633c0 1205 * qla4xxx_about_firmware - gets FW, iscsi draft and boot loader version
afaf5a2d
DS		 1206 * @ha: Pointer to host adapter structure.
1207 *
7ad633c0
HZ		 1208 * Retrieves the FW version, iSCSI draft version & bootloader version of HBA.
1209 * Mailboxes 2 & 3 may hold an address for data. Make sure that we write 0 to
1210 * those mailboxes, if unused.
afaf5a2d 1211 **/
7ad633c0 1212int qla4xxx_about_firmware(struct scsi_qla_host *ha)
afaf5a2d 1213{
7ad633c0
HZ		 1214 struct about_fw_info *about_fw = NULL;
1215 dma_addr_t about_fw_dma;
afaf5a2d
DS		 1216 uint32_t mbox_cmd[MBOX_REG_COUNT];
1217 uint32_t mbox_sts[MBOX_REG_COUNT];
7ad633c0
HZ		 1218 int status = QLA_ERROR;
1219
1220 about_fw = dma_alloc_coherent(&ha->pdev->dev,
1221 sizeof(struct about_fw_info),
1222 &about_fw_dma, GFP_KERNEL);
1223 if (!about_fw) {
1224 DEBUG2(ql4_printk(KERN_ERR, ha, "%s: Unable to alloc memory "
1225 "for about_fw\n", __func__));
1226 return status;
1227 }
afaf5a2d 1228
7ad633c0 1229 memset(about_fw, 0, sizeof(struct about_fw_info));
afaf5a2d
DS		 1230 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1231 memset(&mbox_sts, 0, sizeof(mbox_sts));
c0e344c9 1232
afaf5a2d 1233 mbox_cmd[0] = MBOX_CMD_ABOUT_FW;
7ad633c0
HZ		 1234 mbox_cmd[2] = LSDW(about_fw_dma);
1235 mbox_cmd[3] = MSDW(about_fw_dma);
1236 mbox_cmd[4] = sizeof(struct about_fw_info);
1237
1238 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
1239 &mbox_cmd[0], &mbox_sts[0]);
1240 if (status != QLA_SUCCESS) {
1241 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_ABOUT_FW "
1242 "failed w/ status %04X\n", __func__,
1243 mbox_sts[0]));
1244 goto exit_about_fw;
afaf5a2d
DS		 1245 }
1246
7ad633c0
HZ		 1247 /* Save version information. */
1248 ha->firmware_version[0] = le16_to_cpu(about_fw->fw_major);
1249 ha->firmware_version[1] = le16_to_cpu(about_fw->fw_minor);
1250 ha->patch_number = le16_to_cpu(about_fw->fw_patch);
1251 ha->build_number = le16_to_cpu(about_fw->fw_build);
1252 ha->iscsi_major = le16_to_cpu(about_fw->iscsi_major);
1253 ha->iscsi_minor = le16_to_cpu(about_fw->iscsi_minor);
1254 ha->bootload_major = le16_to_cpu(about_fw->bootload_major);
1255 ha->bootload_minor = le16_to_cpu(about_fw->bootload_minor);
1256 ha->bootload_patch = le16_to_cpu(about_fw->bootload_patch);
1257 ha->bootload_build = le16_to_cpu(about_fw->bootload_build);
1258 status = QLA_SUCCESS;
afaf5a2d 1259
7ad633c0
HZ		 1260exit_about_fw:
1261 dma_free_coherent(&ha->pdev->dev, sizeof(struct about_fw_info),
1262 about_fw, about_fw_dma);
1263 return status;
afaf5a2d
DS		 1264}
1265
b3a271a9 1266static int qla4xxx_get_default_ddb(struct scsi_qla_host *ha, uint32_t options,
47975477 1267 dma_addr_t dma_addr)
afaf5a2d
DS		 1268{
1269 uint32_t mbox_cmd[MBOX_REG_COUNT];
1270 uint32_t mbox_sts[MBOX_REG_COUNT];
1271
1272 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1273 memset(&mbox_sts, 0, sizeof(mbox_sts));
1274
1275 mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS;
b3a271a9 1276 mbox_cmd[1] = options;
afaf5a2d
DS		 1277 mbox_cmd[2] = LSDW(dma_addr);
1278 mbox_cmd[3] = MSDW(dma_addr);
1279
c0e344c9 1280 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]) !=
afaf5a2d
DS		 1281 QLA_SUCCESS) {
1282 DEBUG2(printk("scsi%ld: %s: failed status %04X\n",
1283 ha->host_no, __func__, mbox_sts[0]));
1284 return QLA_ERROR;
1285 }
1286 return QLA_SUCCESS;
1287}
1288
b3a271a9
MR		 1289int qla4xxx_req_ddb_entry(struct scsi_qla_host *ha, uint32_t ddb_index,
1290 uint32_t *mbx_sts)
afaf5a2d 1291{
b3a271a9 1292 int status;
afaf5a2d
DS		 1293 uint32_t mbox_cmd[MBOX_REG_COUNT];
1294 uint32_t mbox_sts[MBOX_REG_COUNT];
1295
1296 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1297 memset(&mbox_sts, 0, sizeof(mbox_sts));
1298
1299 mbox_cmd[0] = MBOX_CMD_REQUEST_DATABASE_ENTRY;
b3a271a9 1300 mbox_cmd[1] = ddb_index;
afaf5a2d 1301
b3a271a9
MR		 1302 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
1303 &mbox_sts[0]);
1304 if (status != QLA_SUCCESS) {
1305 DEBUG2(ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
1306 __func__, mbox_sts[0]));
afaf5a2d
DS		 1307 }
1308
b3a271a9
MR		 1309 *mbx_sts = mbox_sts[0];
1310 return status;
afaf5a2d
DS		 1311}
1312
b3a271a9
MR		 1313int qla4xxx_clear_ddb_entry(struct scsi_qla_host *ha, uint32_t ddb_index)
1314{
1315 int status;
1316 uint32_t mbox_cmd[MBOX_REG_COUNT];
1317 uint32_t mbox_sts[MBOX_REG_COUNT];
1318
1319 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1320 memset(&mbox_sts, 0, sizeof(mbox_sts));
1321
1322 mbox_cmd[0] = MBOX_CMD_CLEAR_DATABASE_ENTRY;
1323 mbox_cmd[1] = ddb_index;
1324
1325 status = qla4xxx_mailbox_command(ha, 2, 1, &mbox_cmd[0],
1326 &mbox_sts[0]);
1327 if (status != QLA_SUCCESS) {
1328 DEBUG2(ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
1329 __func__, mbox_sts[0]));
1330 }
1331
1332 return status;
1333}
1334
d00efe3f
MC		 1335int qla4xxx_set_flash(struct scsi_qla_host *ha, dma_addr_t dma_addr,
1336 uint32_t offset, uint32_t length, uint32_t options)
1337{
1338 uint32_t mbox_cmd[MBOX_REG_COUNT];
1339 uint32_t mbox_sts[MBOX_REG_COUNT];
1340 int status = QLA_SUCCESS;
1341
1342 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1343 memset(&mbox_sts, 0, sizeof(mbox_sts));
1344
1345 mbox_cmd[0] = MBOX_CMD_WRITE_FLASH;
1346 mbox_cmd[1] = LSDW(dma_addr);
1347 mbox_cmd[2] = MSDW(dma_addr);
1348 mbox_cmd[3] = offset;
1349 mbox_cmd[4] = length;
1350 mbox_cmd[5] = options;
1351
1352 status = qla4xxx_mailbox_command(ha, 6, 2, &mbox_cmd[0], &mbox_sts[0]);
1353 if (status != QLA_SUCCESS) {
1354 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_WRITE_FLASH "
1355 "failed w/ status %04X, mbx1 %04X\n",
1356 __func__, mbox_sts[0], mbox_sts[1]));
1357 }
1358 return status;
1359}
1360
2a991c21
MR		 1361int qla4xxx_bootdb_by_index(struct scsi_qla_host *ha,
1362 struct dev_db_entry *fw_ddb_entry,
1363 dma_addr_t fw_ddb_entry_dma, uint16_t ddb_index)
1364{
1365 uint32_t dev_db_start_offset = FLASH_OFFSET_DB_INFO;
1366 uint32_t dev_db_end_offset;
1367 int status = QLA_ERROR;
1368
1369 memset(fw_ddb_entry, 0, sizeof(*fw_ddb_entry));
1370
1371 dev_db_start_offset += (ddb_index * sizeof(*fw_ddb_entry));
1372 dev_db_end_offset = FLASH_OFFSET_DB_END;
1373
1374 if (dev_db_start_offset > dev_db_end_offset) {
1375 DEBUG2(ql4_printk(KERN_ERR, ha,
1376 "%s:Invalid DDB index %d", __func__,
1377 ddb_index));
1378 goto exit_bootdb_failed;
1379 }
1380
1381 if (qla4xxx_get_flash(ha, fw_ddb_entry_dma, dev_db_start_offset,
1382 sizeof(*fw_ddb_entry)) != QLA_SUCCESS) {
1383 ql4_printk(KERN_ERR, ha, "scsi%ld: %s: Get Flash"
1384 "failed\n", ha->host_no, __func__);
1385 goto exit_bootdb_failed;
1386 }
1387
1388 if (fw_ddb_entry->cookie == DDB_VALID_COOKIE)
1389 status = QLA_SUCCESS;
1390
1391exit_bootdb_failed:
1392 return status;
1393}
1394
1395int qla4xxx_get_chap(struct scsi_qla_host *ha, char *username, char *password,
1396 uint16_t idx)
1397{
1398 int ret = 0;
1399 int rval = QLA_ERROR;
4549415a 1400 uint32_t offset = 0, chap_size;
2a991c21
MR		 1401 struct ql4_chap_table *chap_table;
1402 dma_addr_t chap_dma;
1403
1404 chap_table = dma_pool_alloc(ha->chap_dma_pool, GFP_KERNEL, &chap_dma);
1405 if (chap_table == NULL) {
1406 ret = -ENOMEM;
1407 goto exit_get_chap;
1408 }
1409
4549415a
LC		 1410 chap_size = sizeof(struct ql4_chap_table);
1411 memset(chap_table, 0, chap_size);
1412
1413 if (is_qla40XX(ha))
1414 offset = FLASH_CHAP_OFFSET | (idx * chap_size);
1415 else {
1416 offset = FLASH_RAW_ACCESS_ADDR + (ha->hw.flt_region_chap << 2);
1417 /* flt_chap_size is CHAP table size for both ports
1418 * so divide it by 2 to calculate the offset for second port
1419 */
1420 if (ha->port_num == 1)
1421 offset += (ha->hw.flt_chap_size / 2);
1422 offset += (idx * chap_size);
1423 }
2a991c21 1424
4549415a 1425 rval = qla4xxx_get_flash(ha, chap_dma, offset, chap_size);
2a991c21
MR		 1426 if (rval != QLA_SUCCESS) {
1427 ret = -EINVAL;
1428 goto exit_get_chap;
1429 }
1430
1431 DEBUG2(ql4_printk(KERN_INFO, ha, "Chap Cookie: x%x\n",
1432 __le16_to_cpu(chap_table->cookie)));
1433
1434 if (__le16_to_cpu(chap_table->cookie) != CHAP_VALID_COOKIE) {
1435 ql4_printk(KERN_ERR, ha, "No valid chap entry found\n");
1436 goto exit_get_chap;
1437 }
1438
1439 strncpy(password, chap_table->secret, QL4_CHAP_MAX_SECRET_LEN);
1440 strncpy(username, chap_table->name, QL4_CHAP_MAX_NAME_LEN);
1441 chap_table->cookie = __constant_cpu_to_le16(CHAP_VALID_COOKIE);
1442
1443exit_get_chap:
1444 dma_pool_free(ha->chap_dma_pool, chap_table, chap_dma);
1445 return ret;
1446}
1447
b3a271a9
MR		 1448static int qla4xxx_set_chap(struct scsi_qla_host *ha, char *username,
1449 char *password, uint16_t idx, int bidi)
1450{
1451 int ret = 0;
1452 int rval = QLA_ERROR;
1453 uint32_t offset = 0;
1454 struct ql4_chap_table *chap_table;
1455 dma_addr_t chap_dma;
1456
1457 chap_table = dma_pool_alloc(ha->chap_dma_pool, GFP_KERNEL, &chap_dma);
1458 if (chap_table == NULL) {
1459 ret = -ENOMEM;
1460 goto exit_set_chap;
1461 }
1462
1463 memset(chap_table, 0, sizeof(struct ql4_chap_table));
1464 if (bidi)
1465 chap_table->flags |= BIT_6; /* peer */
1466 else
1467 chap_table->flags |= BIT_7; /* local */
1468 chap_table->secret_len = strlen(password);
1469 strncpy(chap_table->secret, password, MAX_CHAP_SECRET_LEN);
1470 strncpy(chap_table->name, username, MAX_CHAP_NAME_LEN);
1471 chap_table->cookie = __constant_cpu_to_le16(CHAP_VALID_COOKIE);
4549415a 1472 offset = FLASH_CHAP_OFFSET | (idx * sizeof(struct ql4_chap_table));
b3a271a9
MR		 1473 rval = qla4xxx_set_flash(ha, chap_dma, offset,
1474 sizeof(struct ql4_chap_table),
1475 FLASH_OPT_RMW_COMMIT);
4549415a
LC		 1476
1477 if (rval == QLA_SUCCESS && ha->chap_list) {
1478 /* Update ha chap_list cache */
1479 memcpy((struct ql4_chap_table *)ha->chap_list + idx,
1480 chap_table, sizeof(struct ql4_chap_table));
1481 }
b3a271a9
MR		 1482 dma_pool_free(ha->chap_dma_pool, chap_table, chap_dma);
1483 if (rval != QLA_SUCCESS)
1484 ret = -EINVAL;
1485
1486exit_set_chap:
1487 return ret;
1488}
1489
4549415a
LC		 1490/**
1491 * qla4xxx_get_chap_index - Get chap index given username and secret
1492 * @ha: pointer to adapter structure
1493 * @username: CHAP username to be searched
1494 * @password: CHAP password to be searched
1495 * @bidi: Is this a BIDI CHAP
1496 * @chap_index: CHAP index to be returned
1497 *
1498 * Match the username and password in the chap_list, return the index if a
1499 * match is found. If a match is not found then add the entry in FLASH and
1500 * return the index at which entry is written in the FLASH.
1501 **/
fca9f04d
MC		 1502int qla4xxx_get_chap_index(struct scsi_qla_host *ha, char *username,
1503 char *password, int bidi, uint16_t *chap_index)
4549415a
LC		 1504{
1505 int i, rval;
1506 int free_index = -1;
1507 int found_index = 0;
1508 int max_chap_entries = 0;
1509 struct ql4_chap_table *chap_table;
1510
1511 if (is_qla8022(ha))
1512 max_chap_entries = (ha->hw.flt_chap_size / 2) /
1513 sizeof(struct ql4_chap_table);
1514 else
1515 max_chap_entries = MAX_CHAP_ENTRIES_40XX;
1516
1517 if (!ha->chap_list) {
1518 ql4_printk(KERN_ERR, ha, "Do not have CHAP table cache\n");
1519 return QLA_ERROR;
1520 }
1521
fca9f04d
MC		 1522 if (!username || !password) {
1523 ql4_printk(KERN_ERR, ha, "Do not have username and psw\n");
1524 return QLA_ERROR;
1525 }
1526
4549415a
LC		 1527 mutex_lock(&ha->chap_sem);
1528 for (i = 0; i < max_chap_entries; i++) {
1529 chap_table = (struct ql4_chap_table *)ha->chap_list + i;
1530 if (chap_table->cookie !=
1531 __constant_cpu_to_le16(CHAP_VALID_COOKIE)) {
1532 if (i > MAX_RESRV_CHAP_IDX && free_index == -1)
1533 free_index = i;
1534 continue;
1535 }
1536 if (bidi) {
1537 if (chap_table->flags & BIT_7)
1538 continue;
1539 } else {
1540 if (chap_table->flags & BIT_6)
1541 continue;
1542 }
1543 if (!strncmp(chap_table->secret, password,
1544 MAX_CHAP_SECRET_LEN) &&
1545 !strncmp(chap_table->name, username,
1546 MAX_CHAP_NAME_LEN)) {
1547 *chap_index = i;
1548 found_index = 1;
1549 break;
1550 }
1551 }
1552
1553 /* If chap entry is not present and a free index is available then
1554 * write the entry in flash
1555 */
1556 if (!found_index && free_index != -1) {
1557 rval = qla4xxx_set_chap(ha, username, password,
1558 free_index, bidi);
1559 if (!rval) {
1560 *chap_index = free_index;
1561 found_index = 1;
1562 }
1563 }
1564
1565 mutex_unlock(&ha->chap_sem);
1566
1567 if (found_index)
1568 return QLA_SUCCESS;
1569 return QLA_ERROR;
1570}
1571
d00efe3f
MC		 1572int qla4xxx_conn_close_sess_logout(struct scsi_qla_host *ha,
1573 uint16_t fw_ddb_index,
1574 uint16_t connection_id,
1575 uint16_t option)
1576{
1577 uint32_t mbox_cmd[MBOX_REG_COUNT];
1578 uint32_t mbox_sts[MBOX_REG_COUNT];
1579 int status = QLA_SUCCESS;
1580
1581 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1582 memset(&mbox_sts, 0, sizeof(mbox_sts));
1583
1584 mbox_cmd[0] = MBOX_CMD_CONN_CLOSE_SESS_LOGOUT;
1585 mbox_cmd[1] = fw_ddb_index;
1586 mbox_cmd[2] = connection_id;
1587 mbox_cmd[3] = option;
1588
1589 status = qla4xxx_mailbox_command(ha, 4, 2, &mbox_cmd[0], &mbox_sts[0]);
1590 if (status != QLA_SUCCESS) {
1591 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_CONN_CLOSE "
1592 "option %04x failed w/ status %04X %04X\n",
1593 __func__, option, mbox_sts[0], mbox_sts[1]));
1594 }
1595 return status;
1596}
1597
1598int qla4xxx_disable_acb(struct scsi_qla_host *ha)
1599{
1600 uint32_t mbox_cmd[MBOX_REG_COUNT];
1601 uint32_t mbox_sts[MBOX_REG_COUNT];
1602 int status = QLA_SUCCESS;
1603
1604 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1605 memset(&mbox_sts, 0, sizeof(mbox_sts));
1606
1607 mbox_cmd[0] = MBOX_CMD_DISABLE_ACB;
1608
1609 status = qla4xxx_mailbox_command(ha, 8, 5, &mbox_cmd[0], &mbox_sts[0]);
1610 if (status != QLA_SUCCESS) {
1611 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_DISABLE_ACB "
1612 "failed w/ status %04X %04X %04X", __func__,
1613 mbox_sts[0], mbox_sts[1], mbox_sts[2]));
1614 }
1615 return status;
1616}
1617
6085491c
HZ		 1618int qla4xxx_get_acb(struct scsi_qla_host *ha, dma_addr_t acb_dma,
1619 uint32_t acb_type, uint32_t len)
d00efe3f 1620{
6085491c
HZ		 1621 uint32_t mbox_cmd[MBOX_REG_COUNT];
1622 uint32_t mbox_sts[MBOX_REG_COUNT];
d00efe3f
MC		 1623 int status = QLA_SUCCESS;
1624
6085491c
HZ		 1625 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1626 memset(&mbox_sts, 0, sizeof(mbox_sts));
1627
d00efe3f 1628 mbox_cmd[0] = MBOX_CMD_GET_ACB;
6085491c 1629 mbox_cmd[1] = acb_type;
d00efe3f
MC		 1630 mbox_cmd[2] = LSDW(acb_dma);
1631 mbox_cmd[3] = MSDW(acb_dma);
6085491c 1632 mbox_cmd[4] = len;
d00efe3f
MC		 1633
1634 status = qla4xxx_mailbox_command(ha, 5, 5, &mbox_cmd[0], &mbox_sts[0]);
1635 if (status != QLA_SUCCESS) {
1636 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_GET_ACB "
1637 "failed w/ status %04X\n", __func__,
1638 mbox_sts[0]));
1639 }
1640 return status;
1641}
1642
1643int qla4xxx_set_acb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
1644 uint32_t *mbox_sts, dma_addr_t acb_dma)
1645{
1646 int status = QLA_SUCCESS;
1647
1648 memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
1649 memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
1650 mbox_cmd[0] = MBOX_CMD_SET_ACB;
1651 mbox_cmd[1] = 0; /* Primary ACB */
1652 mbox_cmd[2] = LSDW(acb_dma);
1653 mbox_cmd[3] = MSDW(acb_dma);
1654 mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
1655
1656 status = qla4xxx_mailbox_command(ha, 5, 5, &mbox_cmd[0], &mbox_sts[0]);
1657 if (status != QLA_SUCCESS) {
1658 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_SET_ACB "
1659 "failed w/ status %04X\n", __func__,
1660 mbox_sts[0]));
1661 }
1662 return status;
1663}
b3a271a9
MR		 1664
1665int qla4xxx_set_param_ddbentry(struct scsi_qla_host *ha,
1666 struct ddb_entry *ddb_entry,
1667 struct iscsi_cls_conn *cls_conn,
1668 uint32_t *mbx_sts)
1669{
1670 struct dev_db_entry *fw_ddb_entry;
1671 struct iscsi_conn *conn;
1672 struct iscsi_session *sess;
1673 struct qla_conn *qla_conn;
1674 struct sockaddr *dst_addr;
1675 dma_addr_t fw_ddb_entry_dma;
1676 int status = QLA_SUCCESS;
1677 int rval = 0;
1678 struct sockaddr_in *addr;
1679 struct sockaddr_in6 *addr6;
1680 char *ip;
1681 uint16_t iscsi_opts = 0;
1682 uint32_t options = 0;
173269ef 1683 uint16_t idx, *ptid;
b3a271a9
MR		 1684
1685 fw_ddb_entry = dma_alloc_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
1686 &fw_ddb_entry_dma, GFP_KERNEL);
1687 if (!fw_ddb_entry) {
1688 DEBUG2(ql4_printk(KERN_ERR, ha,
1689 "%s: Unable to allocate dma buffer.\n",
1690 __func__));
1691 rval = -ENOMEM;
1692 goto exit_set_param_no_free;
1693 }
1694
1695 conn = cls_conn->dd_data;
1696 qla_conn = conn->dd_data;
1697 sess = conn->session;
1698 dst_addr = &qla_conn->qla_ep->dst_addr;
1699
1700 if (dst_addr->sa_family == AF_INET6)
1701 options |= IPV6_DEFAULT_DDB_ENTRY;
1702
1703 status = qla4xxx_get_default_ddb(ha, options, fw_ddb_entry_dma);
1704 if (status == QLA_ERROR) {
1705 rval = -EINVAL;
1706 goto exit_set_param;
1707 }
1708
173269ef
MR		 1709 ptid = (uint16_t *)&fw_ddb_entry->isid[1];
1710 *ptid = cpu_to_le16((uint16_t)ddb_entry->sess->target_id);
1711
1712 DEBUG2(ql4_printk(KERN_INFO, ha, "ISID [%02x%02x%02x%02x%02x%02x]\n",
1713 fw_ddb_entry->isid[5], fw_ddb_entry->isid[4],
1714 fw_ddb_entry->isid[3], fw_ddb_entry->isid[2],
1715 fw_ddb_entry->isid[1], fw_ddb_entry->isid[0]));
1716
b3a271a9
MR		 1717 iscsi_opts = le16_to_cpu(fw_ddb_entry->iscsi_options);
1718 memset(fw_ddb_entry->iscsi_alias, 0, sizeof(fw_ddb_entry->iscsi_alias));
1719
1720 memset(fw_ddb_entry->iscsi_name, 0, sizeof(fw_ddb_entry->iscsi_name));
1721
1722 if (sess->targetname != NULL) {
1723 memcpy(fw_ddb_entry->iscsi_name, sess->targetname,
1724 min(strlen(sess->targetname),
1725 sizeof(fw_ddb_entry->iscsi_name)));
1726 }
1727
1728 memset(fw_ddb_entry->ip_addr, 0, sizeof(fw_ddb_entry->ip_addr));
1729 memset(fw_ddb_entry->tgt_addr, 0, sizeof(fw_ddb_entry->tgt_addr));
1730
1731 fw_ddb_entry->options = DDB_OPT_TARGET | DDB_OPT_AUTO_SENDTGTS_DISABLE;
1732
1733 if (dst_addr->sa_family == AF_INET) {
1734 addr = (struct sockaddr_in *)dst_addr;
1735 ip = (char *)&addr->sin_addr;
1736 memcpy(fw_ddb_entry->ip_addr, ip, IP_ADDR_LEN);
1737 fw_ddb_entry->port = cpu_to_le16(ntohs(addr->sin_port));
1738 DEBUG2(ql4_printk(KERN_INFO, ha,
1739 "%s: Destination Address [%pI4]: index [%d]\n",
1740 __func__, fw_ddb_entry->ip_addr,
1741 ddb_entry->fw_ddb_index));
1742 } else if (dst_addr->sa_family == AF_INET6) {
1743 addr6 = (struct sockaddr_in6 *)dst_addr;
1744 ip = (char *)&addr6->sin6_addr;
1745 memcpy(fw_ddb_entry->ip_addr, ip, IPv6_ADDR_LEN);
1746 fw_ddb_entry->port = cpu_to_le16(ntohs(addr6->sin6_port));
1747 fw_ddb_entry->options |= DDB_OPT_IPV6_DEVICE;
1748 DEBUG2(ql4_printk(KERN_INFO, ha,
1749 "%s: Destination Address [%pI6]: index [%d]\n",
1750 __func__, fw_ddb_entry->ip_addr,
1751 ddb_entry->fw_ddb_index));
1752 } else {
1753 ql4_printk(KERN_ERR, ha,
1754 "%s: Failed to get IP Address\n",
1755 __func__);
1756 rval = -EINVAL;
1757 goto exit_set_param;
1758 }
1759
b3a271a9
MR		 1760 /* CHAP */
1761 if (sess->username != NULL && sess->password != NULL) {
1762 if (strlen(sess->username) && strlen(sess->password)) {
1763 iscsi_opts |= BIT_7;
b3a271a9 1764
4549415a
LC		 1765 rval = qla4xxx_get_chap_index(ha, sess->username,
1766 sess->password,
1767 LOCAL_CHAP, &idx);
b3a271a9
MR		 1768 if (rval)
1769 goto exit_set_param;
1770
1771 fw_ddb_entry->chap_tbl_idx = cpu_to_le16(idx);
1772 }
1773 }
1774
1775 if (sess->username_in != NULL && sess->password_in != NULL) {
1776 /* Check if BIDI CHAP */
1777 if (strlen(sess->username_in) && strlen(sess->password_in)) {
1778 iscsi_opts |= BIT_4;
4549415a
LC		 1779
1780 rval = qla4xxx_get_chap_index(ha, sess->username_in,
1781 sess->password_in,
1782 BIDI_CHAP, &idx);
b3a271a9
MR		 1783 if (rval)
1784 goto exit_set_param;
1785 }
1786 }
1787
1788 if (sess->initial_r2t_en)
1789 iscsi_opts |= BIT_10;
1790
1791 if (sess->imm_data_en)
1792 iscsi_opts |= BIT_11;
1793
1794 fw_ddb_entry->iscsi_options = cpu_to_le16(iscsi_opts);
1795
1796 if (conn->max_recv_dlength)
1797 fw_ddb_entry->iscsi_max_rcv_data_seg_len =
1798 __constant_cpu_to_le16((conn->max_recv_dlength / BYTE_UNITS));
1799
1800 if (sess->max_r2t)
1801 fw_ddb_entry->iscsi_max_outsnd_r2t = cpu_to_le16(sess->max_r2t);
1802
1803 if (sess->first_burst)
1804 fw_ddb_entry->iscsi_first_burst_len =
1805 __constant_cpu_to_le16((sess->first_burst / BYTE_UNITS));
1806
1807 if (sess->max_burst)
1808 fw_ddb_entry->iscsi_max_burst_len =
1809 __constant_cpu_to_le16((sess->max_burst / BYTE_UNITS));
1810
1811 if (sess->time2wait)
1812 fw_ddb_entry->iscsi_def_time2wait =
1813 cpu_to_le16(sess->time2wait);
1814
1815 if (sess->time2retain)
1816 fw_ddb_entry->iscsi_def_time2retain =
1817 cpu_to_le16(sess->time2retain);
1818
1819 status = qla4xxx_set_ddb_entry(ha, ddb_entry->fw_ddb_index,
1820 fw_ddb_entry_dma, mbx_sts);
1821
1822 if (status != QLA_SUCCESS)
1823 rval = -EINVAL;
1824exit_set_param:
1825 dma_free_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
1826 fw_ddb_entry, fw_ddb_entry_dma);
1827exit_set_param_no_free:
1828 return rval;
1829}
1830
1831int qla4xxx_get_mgmt_data(struct scsi_qla_host *ha, uint16_t fw_ddb_index,
1832 uint16_t stats_size, dma_addr_t stats_dma)
1833{
1834 int status = QLA_SUCCESS;
1835 uint32_t mbox_cmd[MBOX_REG_COUNT];
1836 uint32_t mbox_sts[MBOX_REG_COUNT];
1837
1838 memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
1839 memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
1840 mbox_cmd[0] = MBOX_CMD_GET_MANAGEMENT_DATA;
1841 mbox_cmd[1] = fw_ddb_index;
1842 mbox_cmd[2] = LSDW(stats_dma);
1843 mbox_cmd[3] = MSDW(stats_dma);
1844 mbox_cmd[4] = stats_size;
1845
1846 status = qla4xxx_mailbox_command(ha, 5, 1, &mbox_cmd[0], &mbox_sts[0]);
1847 if (status != QLA_SUCCESS) {
1848 DEBUG2(ql4_printk(KERN_WARNING, ha,
1849 "%s: MBOX_CMD_GET_MANAGEMENT_DATA "
1850 "failed w/ status %04X\n", __func__,
1851 mbox_sts[0]));
1852 }
1853 return status;
1854}
8b0402e1
HZ		 1855
1856int qla4xxx_get_ip_state(struct scsi_qla_host *ha, uint32_t acb_idx,
1857 uint32_t ip_idx, uint32_t *sts)
1858{
1859 uint32_t mbox_cmd[MBOX_REG_COUNT];
1860 uint32_t mbox_sts[MBOX_REG_COUNT];
1861 int status = QLA_SUCCESS;
1862
1863 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1864 memset(&mbox_sts, 0, sizeof(mbox_sts));
1865 mbox_cmd[0] = MBOX_CMD_GET_IP_ADDR_STATE;
1866 mbox_cmd[1] = acb_idx;
1867 mbox_cmd[2] = ip_idx;
1868
1869 status = qla4xxx_mailbox_command(ha, 3, 8, &mbox_cmd[0], &mbox_sts[0]);
1870 if (status != QLA_SUCCESS) {
1871 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: "
1872 "MBOX_CMD_GET_IP_ADDR_STATE failed w/ "
1873 "status %04X\n", __func__, mbox_sts[0]));
1874 }
1875 memcpy(sts, mbox_sts, sizeof(mbox_sts));
1876 return status;
1877}
7c07d139
HZ		 1878
1879int qla4xxx_get_nvram(struct scsi_qla_host *ha, dma_addr_t nvram_dma,
1880 uint32_t offset, uint32_t size)
1881{
1882 int status = QLA_SUCCESS;
1883 uint32_t mbox_cmd[MBOX_REG_COUNT];
1884 uint32_t mbox_sts[MBOX_REG_COUNT];
1885
1886 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1887 memset(&mbox_sts, 0, sizeof(mbox_sts));
1888
1889 mbox_cmd[0] = MBOX_CMD_GET_NVRAM;
1890 mbox_cmd[1] = LSDW(nvram_dma);
1891 mbox_cmd[2] = MSDW(nvram_dma);
1892 mbox_cmd[3] = offset;
1893 mbox_cmd[4] = size;
1894
1895 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
1896 &mbox_sts[0]);
1897 if (status != QLA_SUCCESS) {
1898 DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
1899 "status %04X\n", ha->host_no, __func__,
1900 mbox_sts[0]));
1901 }
1902 return status;
1903}
1904
1905int qla4xxx_set_nvram(struct scsi_qla_host *ha, dma_addr_t nvram_dma,
1906 uint32_t offset, uint32_t size)
1907{
1908 int status = QLA_SUCCESS;
1909 uint32_t mbox_cmd[MBOX_REG_COUNT];
1910 uint32_t mbox_sts[MBOX_REG_COUNT];
1911
1912 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1913 memset(&mbox_sts, 0, sizeof(mbox_sts));
1914
1915 mbox_cmd[0] = MBOX_CMD_SET_NVRAM;
1916 mbox_cmd[1] = LSDW(nvram_dma);
1917 mbox_cmd[2] = MSDW(nvram_dma);
1918 mbox_cmd[3] = offset;
1919 mbox_cmd[4] = size;
1920
1921 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
1922 &mbox_sts[0]);
1923 if (status != QLA_SUCCESS) {
1924 DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
1925 "status %04X\n", ha->host_no, __func__,
1926 mbox_sts[0]));
1927 }
1928 return status;
1929}
5232f801
HZ		 1930
1931int qla4xxx_restore_factory_defaults(struct scsi_qla_host *ha,
1932 uint32_t region, uint32_t field0,
1933 uint32_t field1)
1934{
1935 int status = QLA_SUCCESS;
1936 uint32_t mbox_cmd[MBOX_REG_COUNT];
1937 uint32_t mbox_sts[MBOX_REG_COUNT];
1938
1939 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1940 memset(&mbox_sts, 0, sizeof(mbox_sts));
1941
1942 mbox_cmd[0] = MBOX_CMD_RESTORE_FACTORY_DEFAULTS;
1943 mbox_cmd[3] = region;
1944 mbox_cmd[4] = field0;
1945 mbox_cmd[5] = field1;
1946
1947 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0],
1948 &mbox_sts[0]);
1949 if (status != QLA_SUCCESS) {
1950 DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
1951 "status %04X\n", ha->host_no, __func__,
1952 mbox_sts[0]));
1953 }
1954 return status;
1955}
Linux kernel - Deliverables
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