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[SCSI] qla4xxx: Throttle active IOCBs to firmware limits
[deliverable/linux.git] / drivers / scsi / qla4xxx / ql4_mbx.c
CommitLineData
afaf5a2d
DS		 1/*
2 * QLogic iSCSI HBA Driver
c68cdbf0 3 * Copyright (c) 2003-2012 QLogic Corporation
afaf5a2d
DS		 4 *
5 * See LICENSE.qla4xxx for copyright and licensing details.
6 */
7
8#include "ql4_def.h"
c0e344c9
DS		 9#include "ql4_glbl.h"
10#include "ql4_dbg.h"
11#include "ql4_inline.h"
cfb27874 12#include "ql4_version.h"
afaf5a2d 13
33693c7a
VC		 14void qla4xxx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd,
15 int in_count)
16{
17 int i;
18
19 /* Load all mailbox registers, except mailbox 0. */
20 for (i = 1; i < in_count; i++)
21 writel(mbx_cmd[i], &ha->reg->mailbox[i]);
22
23 /* Wakeup firmware */
24 writel(mbx_cmd[0], &ha->reg->mailbox[0]);
25 readl(&ha->reg->mailbox[0]);
26 writel(set_rmask(CSR_INTR_RISC), &ha->reg->ctrl_status);
27 readl(&ha->reg->ctrl_status);
28}
29
30void qla4xxx_process_mbox_intr(struct scsi_qla_host *ha, int out_count)
31{
32 int intr_status;
33
34 intr_status = readl(&ha->reg->ctrl_status);
35 if (intr_status & INTR_PENDING) {
36 /*
37 * Service the interrupt.
38 * The ISR will save the mailbox status registers
39 * to a temporary storage location in the adapter structure.
40 */
41 ha->mbox_status_count = out_count;
42 ha->isp_ops->interrupt_service_routine(ha, intr_status);
43 }
44}
afaf5a2d 45
5c19b92a
VC		 46/**
47 * qla4xxx_is_intr_poll_mode – Are we allowed to poll for interrupts?
48 * @ha: Pointer to host adapter structure.
49 * @ret: 1=polling mode, 0=non-polling mode
50 **/
51static int qla4xxx_is_intr_poll_mode(struct scsi_qla_host *ha)
52{
53 int rval = 1;
54
55 if (is_qla8032(ha)) {
56 if (test_bit(AF_IRQ_ATTACHED, &ha->flags) &&
57 test_bit(AF_83XX_MBOX_INTR_ON, &ha->flags))
58 rval = 0;
59 } else {
60 if (test_bit(AF_IRQ_ATTACHED, &ha->flags) &&
61 test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
62 test_bit(AF_ONLINE, &ha->flags) &&
63 !test_bit(AF_HA_REMOVAL, &ha->flags))
64 rval = 0;
65 }
66
67 return rval;
68}
69
afaf5a2d
DS		 70/**
71 * qla4xxx_mailbox_command - issues mailbox commands
72 * @ha: Pointer to host adapter structure.
73 * @inCount: number of mailbox registers to load.
74 * @outCount: number of mailbox registers to return.
75 * @mbx_cmd: data pointer for mailbox in registers.
76 * @mbx_sts: data pointer for mailbox out registers.
77 *
70f23fd6 78 * This routine issue mailbox commands and waits for completion.
afaf5a2d
DS		 79 * If outCount is 0, this routine completes successfully WITHOUT waiting
80 * for the mailbox command to complete.
81 **/
f4f5df23
VC		 82int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
83 uint8_t outCount, uint32_t *mbx_cmd,
84 uint32_t *mbx_sts)
afaf5a2d
DS		 85{
86 int status = QLA_ERROR;
87 uint8_t i;
88 u_long wait_count;
afaf5a2d 89 unsigned long flags = 0;
99b53bf5 90 uint32_t dev_state;
afaf5a2d
DS		 91
92 /* Make sure that pointers are valid */
93 if (!mbx_cmd || !mbx_sts) {
94 DEBUG2(printk("scsi%ld: %s: Invalid mbx_cmd or mbx_sts "
95 "pointer\n", ha->host_no, __func__));
477ffb9d
DS		 96 return status;
97 }
21033639 98
13483730
MC		 99 if (is_qla40XX(ha)) {
100 if (test_bit(AF_HA_REMOVAL, &ha->flags)) {
101 DEBUG2(ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: "
102 "prematurely completing mbx cmd as "
103 "adapter removal detected\n",
104 ha->host_no, __func__));
105 return status;
106 }
107 }
108
2232be0d
LC		 109 if ((is_aer_supported(ha)) &&
110 (test_bit(AF_PCI_CHANNEL_IO_PERM_FAILURE, &ha->flags))) {
111 DEBUG2(printk(KERN_WARNING "scsi%ld: %s: Perm failure on EEH, "
112 "timeout MBX Exiting.\n", ha->host_no, __func__));
113 return status;
114 }
115
477ffb9d
DS		 116 /* Mailbox code active */
117 wait_count = MBOX_TOV * 100;
118
119 while (wait_count--) {
120 mutex_lock(&ha->mbox_sem);
121 if (!test_bit(AF_MBOX_COMMAND, &ha->flags)) {
122 set_bit(AF_MBOX_COMMAND, &ha->flags);
123 mutex_unlock(&ha->mbox_sem);
124 break;
125 }
126 mutex_unlock(&ha->mbox_sem);
127 if (!wait_count) {
128 DEBUG2(printk("scsi%ld: %s: mbox_sem failed\n",
129 ha->host_no, __func__));
130 return status;
131 }
132 msleep(10);
afaf5a2d
DS		 133 }
134
6e7b4292 135 if (is_qla80XX(ha)) {
5f50aa3a
LC		 136 if (test_bit(AF_FW_RECOVERY, &ha->flags)) {
137 DEBUG2(ql4_printk(KERN_WARNING, ha,
138 "scsi%ld: %s: prematurely completing mbx cmd as firmware recovery detected\n",
139 ha->host_no, __func__));
140 goto mbox_exit;
141 }
142 /* Do not send any mbx cmd if h/w is in failed state*/
33693c7a
VC		 143 ha->isp_ops->idc_lock(ha);
144 dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
145 ha->isp_ops->idc_unlock(ha);
de8c72da 146 if (dev_state == QLA8XXX_DEV_FAILED) {
5f50aa3a
LC		 147 ql4_printk(KERN_WARNING, ha,
148 "scsi%ld: %s: H/W is in failed state, do not send any mailbox commands\n",
149 ha->host_no, __func__);
150 goto mbox_exit;
151 }
152 }
153
afaf5a2d 154 spin_lock_irqsave(&ha->hardware_lock, flags);
f4f5df23 155
afaf5a2d
DS		 156 ha->mbox_status_count = outCount;
157 for (i = 0; i < outCount; i++)
158 ha->mbox_status[i] = 0;
159
33693c7a
VC		 160 /* Queue the mailbox command to the firmware */
161 ha->isp_ops->queue_mailbox_command(ha, mbx_cmd, inCount);
afaf5a2d 162
afaf5a2d
DS		 163 spin_unlock_irqrestore(&ha->hardware_lock, flags);
164
165 /* Wait for completion */
afaf5a2d
DS		 166
167 /*
168 * If we don't want status, don't wait for the mailbox command to
169 * complete. For example, MBOX_CMD_RESET_FW doesn't return status,
170 * you must poll the inbound Interrupt Mask for completion.
171 */
172 if (outCount == 0) {
173 status = QLA_SUCCESS;
afaf5a2d
DS		 174 goto mbox_exit;
175 }
afaf5a2d 176
f4f5df23
VC		 177 /*
178 * Wait for completion: Poll or completion queue
179 */
5c19b92a 180 if (qla4xxx_is_intr_poll_mode(ha)) {
f4f5df23
VC		 181 /* Poll for command to complete */
182 wait_count = jiffies + MBOX_TOV * HZ;
183 while (test_bit(AF_MBOX_COMMAND_DONE, &ha->flags) == 0) {
184 if (time_after_eq(jiffies, wait_count))
185 break;
afaf5a2d
DS		 186 /*
187 * Service the interrupt.
188 * The ISR will save the mailbox status registers
189 * to a temporary storage location in the adapter
190 * structure.
191 */
f4f5df23 192 spin_lock_irqsave(&ha->hardware_lock, flags);
33693c7a 193 ha->isp_ops->process_mailbox_interrupt(ha, outCount);
f4f5df23
VC		 194 spin_unlock_irqrestore(&ha->hardware_lock, flags);
195 msleep(10);
afaf5a2d 196 }
5c19b92a
VC		 197 } else {
198 /* Do not poll for completion. Use completion queue */
199 set_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
200 wait_for_completion_timeout(&ha->mbx_intr_comp, MBOX_TOV * HZ);
201 clear_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
afaf5a2d 202 }
afaf5a2d
DS		 203
204 /* Check for mailbox timeout. */
205 if (!test_bit(AF_MBOX_COMMAND_DONE, &ha->flags)) {
6e7b4292 206 if (is_qla80XX(ha) &&
21033639
NJ		 207 test_bit(AF_FW_RECOVERY, &ha->flags)) {
208 DEBUG2(ql4_printk(KERN_INFO, ha,
209 "scsi%ld: %s: prematurely completing mbx cmd as "
210 "firmware recovery detected\n",
211 ha->host_no, __func__));
212 goto mbox_exit;
213 }
afaf5a2d
DS		 214 DEBUG2(printk("scsi%ld: Mailbox Cmd 0x%08X timed out ...,"
215 " Scheduling Adapter Reset\n", ha->host_no,
216 mbx_cmd[0]));
217 ha->mailbox_timeout_count++;
218 mbx_sts[0] = (-1);
219 set_bit(DPC_RESET_HA, &ha->dpc_flags);
e6bd0ebd
GM		 220 if (is_qla8022(ha)) {
221 ql4_printk(KERN_INFO, ha,
222 "disabling pause transmit on port 0 & 1.\n");
f8086f4f 223 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
e6bd0ebd
GM		 224 CRB_NIU_XG_PAUSE_CTL_P0 |
225 CRB_NIU_XG_PAUSE_CTL_P1);
546fef27
TP		 226 } else if (is_qla8032(ha)) {
227 ql4_printk(KERN_INFO, ha, " %s: disabling pause transmit on port 0 & 1.\n",
228 __func__);
229 qla4_83xx_disable_pause(ha);
e6bd0ebd 230 }
afaf5a2d
DS		 231 goto mbox_exit;
232 }
233
234 /*
235 * Copy the mailbox out registers to the caller's mailbox in/out
236 * structure.
237 */
238 spin_lock_irqsave(&ha->hardware_lock, flags);
239 for (i = 0; i < outCount; i++)
240 mbx_sts[i] = ha->mbox_status[i];
241
242 /* Set return status and error flags (if applicable). */
243 switch (ha->mbox_status[0]) {
244 case MBOX_STS_COMMAND_COMPLETE:
245 status = QLA_SUCCESS;
246 break;
247
248 case MBOX_STS_INTERMEDIATE_COMPLETION:
249 status = QLA_SUCCESS;
250 break;
251
252 case MBOX_STS_BUSY:
253 DEBUG2( printk("scsi%ld: %s: Cmd = %08X, ISP BUSY\n",
254 ha->host_no, __func__, mbx_cmd[0]));
255 ha->mailbox_timeout_count++;
256 break;
257
258 default:
259 DEBUG2(printk("scsi%ld: %s: **** FAILED, cmd = %08X, "
260 "sts = %08X ****\n", ha->host_no, __func__,
261 mbx_cmd[0], mbx_sts[0]));
262 break;
263 }
264 spin_unlock_irqrestore(&ha->hardware_lock, flags);
265
266mbox_exit:
477ffb9d 267 mutex_lock(&ha->mbox_sem);
afaf5a2d 268 clear_bit(AF_MBOX_COMMAND, &ha->flags);
afaf5a2d 269 mutex_unlock(&ha->mbox_sem);
477ffb9d 270 clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
afaf5a2d
DS		 271
272 return status;
273}
21033639 274
068237c8
TP		 275/**
276 * qla4xxx_get_minidump_template - Get the firmware template
277 * @ha: Pointer to host adapter structure.
278 * @phys_addr: dma address for template
279 *
280 * Obtain the minidump template from firmware during initialization
281 * as it may not be available when minidump is desired.
282 **/
283int qla4xxx_get_minidump_template(struct scsi_qla_host *ha,
284 dma_addr_t phys_addr)
285{
286 uint32_t mbox_cmd[MBOX_REG_COUNT];
287 uint32_t mbox_sts[MBOX_REG_COUNT];
288 int status;
289
290 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
291 memset(&mbox_sts, 0, sizeof(mbox_sts));
292
293 mbox_cmd[0] = MBOX_CMD_MINIDUMP;
294 mbox_cmd[1] = MINIDUMP_GET_TMPLT_SUBCOMMAND;
295 mbox_cmd[2] = LSDW(phys_addr);
296 mbox_cmd[3] = MSDW(phys_addr);
297 mbox_cmd[4] = ha->fw_dump_tmplt_size;
298 mbox_cmd[5] = 0;
299
300 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
301 &mbox_sts[0]);
302 if (status != QLA_SUCCESS) {
303 DEBUG2(ql4_printk(KERN_INFO, ha,
304 "scsi%ld: %s: Cmd = %08X, mbx[0] = 0x%04x, mbx[1] = 0x%04x\n",
305 ha->host_no, __func__, mbox_cmd[0],
306 mbox_sts[0], mbox_sts[1]));
307 }
308 return status;
309}
310
311/**
312 * qla4xxx_req_template_size - Get minidump template size from firmware.
313 * @ha: Pointer to host adapter structure.
314 **/
315int qla4xxx_req_template_size(struct scsi_qla_host *ha)
316{
317 uint32_t mbox_cmd[MBOX_REG_COUNT];
318 uint32_t mbox_sts[MBOX_REG_COUNT];
319 int status;
320
321 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
322 memset(&mbox_sts, 0, sizeof(mbox_sts));
323
324 mbox_cmd[0] = MBOX_CMD_MINIDUMP;
325 mbox_cmd[1] = MINIDUMP_GET_SIZE_SUBCOMMAND;
326
327 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 8, &mbox_cmd[0],
328 &mbox_sts[0]);
329 if (status == QLA_SUCCESS) {
330 ha->fw_dump_tmplt_size = mbox_sts[1];
331 DEBUG2(ql4_printk(KERN_INFO, ha,
332 "%s: sts[0]=0x%04x, template size=0x%04x, size_cm_02=0x%04x, size_cm_04=0x%04x, size_cm_08=0x%04x, size_cm_10=0x%04x, size_cm_FF=0x%04x, version=0x%04x\n",
333 __func__, mbox_sts[0], mbox_sts[1],
334 mbox_sts[2], mbox_sts[3], mbox_sts[4],
335 mbox_sts[5], mbox_sts[6], mbox_sts[7]));
336 if (ha->fw_dump_tmplt_size == 0)
337 status = QLA_ERROR;
338 } else {
339 ql4_printk(KERN_WARNING, ha,
340 "%s: Error sts[0]=0x%04x, mbx[1]=0x%04x\n",
341 __func__, mbox_sts[0], mbox_sts[1]);
342 status = QLA_ERROR;
343 }
344
345 return status;
346}
347
21033639
NJ		 348void qla4xxx_mailbox_premature_completion(struct scsi_qla_host *ha)
349{
350 set_bit(AF_FW_RECOVERY, &ha->flags);
351 ql4_printk(KERN_INFO, ha, "scsi%ld: %s: set FW RECOVERY!\n",
352 ha->host_no, __func__);
353
354 if (test_bit(AF_MBOX_COMMAND, &ha->flags)) {
355 if (test_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags)) {
356 complete(&ha->mbx_intr_comp);
357 ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
358 "recovery, doing premature completion of "
359 "mbx cmd\n", ha->host_no, __func__);
360
361 } else {
362 set_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
363 ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
364 "recovery, doing premature completion of "
365 "polling mbx cmd\n", ha->host_no, __func__);
366 }
367 }
368}
afaf5a2d 369
f4f5df23 370static uint8_t
2a49a78e
VC		 371qla4xxx_set_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
372 uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
373{
374 memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
375 memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
2657c800
SS		 376
377 if (is_qla8022(ha))
f8086f4f 378 qla4_82xx_wr_32(ha, ha->nx_db_wr_ptr, 0);
2657c800 379
2a49a78e
VC		 380 mbox_cmd[0] = MBOX_CMD_INITIALIZE_FIRMWARE;
381 mbox_cmd[1] = 0;
382 mbox_cmd[2] = LSDW(init_fw_cb_dma);
383 mbox_cmd[3] = MSDW(init_fw_cb_dma);
384 mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
385 mbox_cmd[5] = (IFCB_VER_MAX << 8) | IFCB_VER_MIN;
386
387 if (qla4xxx_mailbox_command(ha, 6, 6, mbox_cmd, mbox_sts) !=
388 QLA_SUCCESS) {
389 DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
390 "MBOX_CMD_INITIALIZE_FIRMWARE"
391 " failed w/ status %04X\n",
392 ha->host_no, __func__, mbox_sts[0]));
393 return QLA_ERROR;
394 }
395 return QLA_SUCCESS;
396}
397
d00efe3f 398uint8_t
2a49a78e
VC		 399qla4xxx_get_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
400 uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
401{
402 memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
403 memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
404 mbox_cmd[0] = MBOX_CMD_GET_INIT_FW_CTRL_BLOCK;
405 mbox_cmd[2] = LSDW(init_fw_cb_dma);
406 mbox_cmd[3] = MSDW(init_fw_cb_dma);
407 mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
408
409 if (qla4xxx_mailbox_command(ha, 5, 5, mbox_cmd, mbox_sts) !=
410 QLA_SUCCESS) {
411 DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
412 "MBOX_CMD_GET_INIT_FW_CTRL_BLOCK"
413 " failed w/ status %04X\n",
414 ha->host_no, __func__, mbox_sts[0]));
415 return QLA_ERROR;
416 }
417 return QLA_SUCCESS;
418}
419
f4f5df23 420static void
2a49a78e 421qla4xxx_update_local_ip(struct scsi_qla_host *ha,
2bab08fc 422 struct addr_ctrl_blk *init_fw_cb)
2a49a78e 423{
2bab08fc
VC		 424 ha->ip_config.tcp_options = le16_to_cpu(init_fw_cb->ipv4_tcp_opts);
425 ha->ip_config.ipv4_options = le16_to_cpu(init_fw_cb->ipv4_ip_opts);
426 ha->ip_config.ipv4_addr_state =
427 le16_to_cpu(init_fw_cb->ipv4_addr_state);
943c157b
VC		 428 ha->ip_config.eth_mtu_size =
429 le16_to_cpu(init_fw_cb->eth_mtu_size);
2ada7fc5 430 ha->ip_config.ipv4_port = le16_to_cpu(init_fw_cb->ipv4_port);
2bab08fc
VC		 431
432 if (ha->acb_version == ACB_SUPPORTED) {
433 ha->ip_config.ipv6_options = le16_to_cpu(init_fw_cb->ipv6_opts);
434 ha->ip_config.ipv6_addl_options =
435 le16_to_cpu(init_fw_cb->ipv6_addtl_opts);
436 }
437
2a49a78e 438 /* Save IPv4 Address Info */
2bab08fc
VC		 439 memcpy(ha->ip_config.ip_address, init_fw_cb->ipv4_addr,
440 min(sizeof(ha->ip_config.ip_address),
441 sizeof(init_fw_cb->ipv4_addr)));
442 memcpy(ha->ip_config.subnet_mask, init_fw_cb->ipv4_subnet,
443 min(sizeof(ha->ip_config.subnet_mask),
444 sizeof(init_fw_cb->ipv4_subnet)));
445 memcpy(ha->ip_config.gateway, init_fw_cb->ipv4_gw_addr,
446 min(sizeof(ha->ip_config.gateway),
447 sizeof(init_fw_cb->ipv4_gw_addr)));
2a49a78e 448
6ac73e8c
VC		 449 ha->ip_config.ipv4_vlan_tag = be16_to_cpu(init_fw_cb->ipv4_vlan_tag);
450
2a49a78e
VC		 451 if (is_ipv6_enabled(ha)) {
452 /* Save IPv6 Address */
2bab08fc
VC		 453 ha->ip_config.ipv6_link_local_state =
454 le16_to_cpu(init_fw_cb->ipv6_lnk_lcl_addr_state);
455 ha->ip_config.ipv6_addr0_state =
456 le16_to_cpu(init_fw_cb->ipv6_addr0_state);
457 ha->ip_config.ipv6_addr1_state =
458 le16_to_cpu(init_fw_cb->ipv6_addr1_state);
459 ha->ip_config.ipv6_default_router_state =
460 le16_to_cpu(init_fw_cb->ipv6_dflt_rtr_state);
461 ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[0] = 0xFE;
462 ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[1] = 0x80;
463
464 memcpy(&ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[8],
465 init_fw_cb->ipv6_if_id,
466 min(sizeof(ha->ip_config.ipv6_link_local_addr)/2,
467 sizeof(init_fw_cb->ipv6_if_id)));
468 memcpy(&ha->ip_config.ipv6_addr0, init_fw_cb->ipv6_addr0,
469 min(sizeof(ha->ip_config.ipv6_addr0),
470 sizeof(init_fw_cb->ipv6_addr0)));
471 memcpy(&ha->ip_config.ipv6_addr1, init_fw_cb->ipv6_addr1,
472 min(sizeof(ha->ip_config.ipv6_addr1),
473 sizeof(init_fw_cb->ipv6_addr1)));
474 memcpy(&ha->ip_config.ipv6_default_router_addr,
475 init_fw_cb->ipv6_dflt_rtr_addr,
476 min(sizeof(ha->ip_config.ipv6_default_router_addr),
477 sizeof(init_fw_cb->ipv6_dflt_rtr_addr)));
6ac73e8c
VC		 478 ha->ip_config.ipv6_vlan_tag =
479 be16_to_cpu(init_fw_cb->ipv6_vlan_tag);
2ada7fc5 480 ha->ip_config.ipv6_port = le16_to_cpu(init_fw_cb->ipv6_port);
2a49a78e
VC		 481 }
482}
483
d00efe3f 484uint8_t
2a49a78e
VC		 485qla4xxx_update_local_ifcb(struct scsi_qla_host *ha,
486 uint32_t *mbox_cmd,
487 uint32_t *mbox_sts,
488 struct addr_ctrl_blk *init_fw_cb,
489 dma_addr_t init_fw_cb_dma)
490{
491 if (qla4xxx_get_ifcb(ha, mbox_cmd, mbox_sts, init_fw_cb_dma)
492 != QLA_SUCCESS) {
493 DEBUG2(printk(KERN_WARNING
494 "scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
495 ha->host_no, __func__));
496 return QLA_ERROR;
497 }
498
499 DEBUG2(qla4xxx_dump_buffer(init_fw_cb, sizeof(struct addr_ctrl_blk)));
500
501 /* Save some info in adapter structure. */
502 ha->acb_version = init_fw_cb->acb_version;
503 ha->firmware_options = le16_to_cpu(init_fw_cb->fw_options);
2a49a78e
VC		 504 ha->heartbeat_interval = init_fw_cb->hb_interval;
505 memcpy(ha->name_string, init_fw_cb->iscsi_name,
506 min(sizeof(ha->name_string),
507 sizeof(init_fw_cb->iscsi_name)));
13483730 508 ha->def_timeout = le16_to_cpu(init_fw_cb->def_timeout);
2a49a78e
VC		 509 /*memcpy(ha->alias, init_fw_cb->Alias,
510 min(sizeof(ha->alias), sizeof(init_fw_cb->Alias)));*/
511
2a49a78e
VC		 512 qla4xxx_update_local_ip(ha, init_fw_cb);
513
514 return QLA_SUCCESS;
515}
516
afaf5a2d
DS		 517/**
518 * qla4xxx_initialize_fw_cb - initializes firmware control block.
519 * @ha: Pointer to host adapter structure.
520 **/
521int qla4xxx_initialize_fw_cb(struct scsi_qla_host * ha)
522{
2a49a78e 523 struct addr_ctrl_blk *init_fw_cb;
afaf5a2d
DS		 524 dma_addr_t init_fw_cb_dma;
525 uint32_t mbox_cmd[MBOX_REG_COUNT];
526 uint32_t mbox_sts[MBOX_REG_COUNT];
527 int status = QLA_ERROR;
528
529 init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
2a49a78e 530 sizeof(struct addr_ctrl_blk),
afaf5a2d
DS		 531 &init_fw_cb_dma, GFP_KERNEL);
532 if (init_fw_cb == NULL) {
533 DEBUG2(printk("scsi%ld: %s: Unable to alloc init_cb\n",
534 ha->host_no, __func__));
beabe7c1 535 goto exit_init_fw_cb_no_free;
afaf5a2d 536 }
2a49a78e 537 memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
afaf5a2d
DS		 538
539 /* Get Initialize Firmware Control Block. */
540 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
541 memset(&mbox_sts, 0, sizeof(mbox_sts));
c0e344c9 542
2a49a78e 543 if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
afaf5a2d
DS		 544 QLA_SUCCESS) {
545 dma_free_coherent(&ha->pdev->dev,
2a49a78e 546 sizeof(struct addr_ctrl_blk),
afaf5a2d 547 init_fw_cb, init_fw_cb_dma);
2a49a78e 548 goto exit_init_fw_cb;
afaf5a2d
DS		 549 }
550
551 /* Initialize request and response queues. */
552 qla4xxx_init_rings(ha);
553
554 /* Fill in the request and response queue information. */
2a49a78e
VC		 555 init_fw_cb->rqq_consumer_idx = cpu_to_le16(ha->request_out);
556 init_fw_cb->compq_producer_idx = cpu_to_le16(ha->response_in);
557 init_fw_cb->rqq_len = __constant_cpu_to_le16(REQUEST_QUEUE_DEPTH);
558 init_fw_cb->compq_len = __constant_cpu_to_le16(RESPONSE_QUEUE_DEPTH);
559 init_fw_cb->rqq_addr_lo = cpu_to_le32(LSDW(ha->request_dma));
560 init_fw_cb->rqq_addr_hi = cpu_to_le32(MSDW(ha->request_dma));
561 init_fw_cb->compq_addr_lo = cpu_to_le32(LSDW(ha->response_dma));
562 init_fw_cb->compq_addr_hi = cpu_to_le32(MSDW(ha->response_dma));
563 init_fw_cb->shdwreg_addr_lo = cpu_to_le32(LSDW(ha->shadow_regs_dma));
564 init_fw_cb->shdwreg_addr_hi = cpu_to_le32(MSDW(ha->shadow_regs_dma));
afaf5a2d
DS		 565
566 /* Set up required options. */
2a49a78e 567 init_fw_cb->fw_options |=
afaf5a2d
DS		 568 __constant_cpu_to_le16(FWOPT_SESSION_MODE |
569 FWOPT_INITIATOR_MODE);
2657c800 570
6e7b4292 571 if (is_qla80XX(ha))
2657c800
SS		 572 init_fw_cb->fw_options |=
573 __constant_cpu_to_le16(FWOPT_ENABLE_CRBDB);
574
2a49a78e 575 init_fw_cb->fw_options &= __constant_cpu_to_le16(~FWOPT_TARGET_MODE);
afaf5a2d 576
d32cee3c
PM		 577 init_fw_cb->add_fw_options = 0;
578 init_fw_cb->add_fw_options |=
b3a271a9
MR		 579 __constant_cpu_to_le16(ADFWOPT_SERIALIZE_TASK_MGMT);
580 init_fw_cb->add_fw_options |=
581 __constant_cpu_to_le16(ADFWOPT_AUTOCONN_DISABLE);
d32cee3c 582
2a49a78e
VC		 583 if (qla4xxx_set_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma)
584 != QLA_SUCCESS) {
585 DEBUG2(printk(KERN_WARNING
586 "scsi%ld: %s: Failed to set init_fw_ctrl_blk\n",
587 ha->host_no, __func__));
588 goto exit_init_fw_cb;
589 }
c0e344c9 590
2a49a78e
VC		 591 if (qla4xxx_update_local_ifcb(ha, &mbox_cmd[0], &mbox_sts[0],
592 init_fw_cb, init_fw_cb_dma) != QLA_SUCCESS) {
593 DEBUG2(printk("scsi%ld: %s: Failed to update local ifcb\n",
594 ha->host_no, __func__));
595 goto exit_init_fw_cb;
afaf5a2d 596 }
2a49a78e
VC		 597 status = QLA_SUCCESS;
598
599exit_init_fw_cb:
600 dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
601 init_fw_cb, init_fw_cb_dma);
beabe7c1 602exit_init_fw_cb_no_free:
afaf5a2d
DS		 603 return status;
604}
605
606/**
607 * qla4xxx_get_dhcp_ip_address - gets HBA ip address via DHCP
608 * @ha: Pointer to host adapter structure.
609 **/
610int qla4xxx_get_dhcp_ip_address(struct scsi_qla_host * ha)
611{
2a49a78e 612 struct addr_ctrl_blk *init_fw_cb;
afaf5a2d
DS		 613 dma_addr_t init_fw_cb_dma;
614 uint32_t mbox_cmd[MBOX_REG_COUNT];
615 uint32_t mbox_sts[MBOX_REG_COUNT];
616
617 init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
2a49a78e 618 sizeof(struct addr_ctrl_blk),
afaf5a2d
DS		 619 &init_fw_cb_dma, GFP_KERNEL);
620 if (init_fw_cb == NULL) {
621 printk("scsi%ld: %s: Unable to alloc init_cb\n", ha->host_no,
622 __func__);
beabe7c1 623 return QLA_ERROR;
afaf5a2d
DS		 624 }
625
626 /* Get Initialize Firmware Control Block. */
2a49a78e
VC		 627 memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
628 if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
afaf5a2d
DS		 629 QLA_SUCCESS) {
630 DEBUG2(printk("scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
631 ha->host_no, __func__));
632 dma_free_coherent(&ha->pdev->dev,
2a49a78e 633 sizeof(struct addr_ctrl_blk),
afaf5a2d
DS		 634 init_fw_cb, init_fw_cb_dma);
635 return QLA_ERROR;
636 }
637
638 /* Save IP Address. */
2a49a78e
VC		 639 qla4xxx_update_local_ip(ha, init_fw_cb);
640 dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
641 init_fw_cb, init_fw_cb_dma);
afaf5a2d
DS		 642
643 return QLA_SUCCESS;
644}
645
646/**
647 * qla4xxx_get_firmware_state - gets firmware state of HBA
648 * @ha: Pointer to host adapter structure.
649 **/
650int qla4xxx_get_firmware_state(struct scsi_qla_host * ha)
651{
652 uint32_t mbox_cmd[MBOX_REG_COUNT];
653 uint32_t mbox_sts[MBOX_REG_COUNT];
654
655 /* Get firmware version */
656 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
657 memset(&mbox_sts, 0, sizeof(mbox_sts));
c0e344c9 658
afaf5a2d 659 mbox_cmd[0] = MBOX_CMD_GET_FW_STATE;
c0e344c9
DS		 660
661 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 4, &mbox_cmd[0], &mbox_sts[0]) !=
afaf5a2d
DS		 662 QLA_SUCCESS) {
663 DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATE failed w/ "
664 "status %04X\n", ha->host_no, __func__,
665 mbox_sts[0]));
666 return QLA_ERROR;
667 }
668 ha->firmware_state = mbox_sts[1];
669 ha->board_id = mbox_sts[2];
670 ha->addl_fw_state = mbox_sts[3];
671 DEBUG2(printk("scsi%ld: %s firmware_state=0x%x\n",
672 ha->host_no, __func__, ha->firmware_state);)
673
f4f5df23 674 return QLA_SUCCESS;
afaf5a2d
DS		 675}
676
677/**
678 * qla4xxx_get_firmware_status - retrieves firmware status
679 * @ha: Pointer to host adapter structure.
680 **/
681int qla4xxx_get_firmware_status(struct scsi_qla_host * ha)
682{
683 uint32_t mbox_cmd[MBOX_REG_COUNT];
684 uint32_t mbox_sts[MBOX_REG_COUNT];
685
686 /* Get firmware version */
687 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
688 memset(&mbox_sts, 0, sizeof(mbox_sts));
c0e344c9 689
afaf5a2d 690 mbox_cmd[0] = MBOX_CMD_GET_FW_STATUS;
c0e344c9
DS		 691
692 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0], &mbox_sts[0]) !=
afaf5a2d
DS		 693 QLA_SUCCESS) {
694 DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATUS failed w/ "
695 "status %04X\n", ha->host_no, __func__,
696 mbox_sts[0]));
697 return QLA_ERROR;
698 }
f4f5df23 699
5b1c1bff
KH		 700 /* High-water mark of IOCBs */
701 ha->iocb_hiwat = mbox_sts[2];
702 DEBUG2(ql4_printk(KERN_INFO, ha,
703 "%s: firmware IOCBs available = %d\n", __func__,
704 ha->iocb_hiwat));
705
706 if (ha->iocb_hiwat > IOCB_HIWAT_CUSHION)
707 ha->iocb_hiwat -= IOCB_HIWAT_CUSHION;
708
709 /* Ideally, we should not enter this code, as the # of firmware
710 * IOCBs is hard-coded in the firmware. We set a default
711 * iocb_hiwat here just in case */
712 if (ha->iocb_hiwat == 0) {
713 ha->iocb_hiwat = REQUEST_QUEUE_DEPTH / 4;
714 DEBUG2(ql4_printk(KERN_WARNING, ha,
715 "%s: Setting IOCB's to = %d\n", __func__,
716 ha->iocb_hiwat));
717 }
f4f5df23 718
afaf5a2d
DS		 719 return QLA_SUCCESS;
720}
721
722/**
723 * qla4xxx_get_fwddb_entry - retrieves firmware ddb entry
724 * @ha: Pointer to host adapter structure.
725 * @fw_ddb_index: Firmware's device database index
726 * @fw_ddb_entry: Pointer to firmware's device database entry structure
727 * @num_valid_ddb_entries: Pointer to number of valid ddb entries
728 * @next_ddb_index: Pointer to next valid device database index
729 * @fw_ddb_device_state: Pointer to device state
730 **/
731int qla4xxx_get_fwddb_entry(struct scsi_qla_host *ha,
732 uint16_t fw_ddb_index,
733 struct dev_db_entry *fw_ddb_entry,
734 dma_addr_t fw_ddb_entry_dma,
735 uint32_t *num_valid_ddb_entries,
736 uint32_t *next_ddb_index,
737 uint32_t *fw_ddb_device_state,
738 uint32_t *conn_err_detail,
739 uint16_t *tcp_source_port_num,
740 uint16_t *connection_id)
741{
742 int status = QLA_ERROR;
2a49a78e 743 uint16_t options;
afaf5a2d
DS		 744 uint32_t mbox_cmd[MBOX_REG_COUNT];
745 uint32_t mbox_sts[MBOX_REG_COUNT];
746
747 /* Make sure the device index is valid */
748 if (fw_ddb_index >= MAX_DDB_ENTRIES) {
f4f5df23 749 DEBUG2(printk("scsi%ld: %s: ddb [%d] out of range.\n",
afaf5a2d
DS		 750 ha->host_no, __func__, fw_ddb_index));
751 goto exit_get_fwddb;
752 }
753 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
754 memset(&mbox_sts, 0, sizeof(mbox_sts));
981c982c
LC		 755 if (fw_ddb_entry)
756 memset(fw_ddb_entry, 0, sizeof(struct dev_db_entry));
c0e344c9 757
afaf5a2d
DS		 758 mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY;
759 mbox_cmd[1] = (uint32_t) fw_ddb_index;
760 mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
761 mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
c0e344c9
DS		 762 mbox_cmd[4] = sizeof(struct dev_db_entry);
763
764 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 7, &mbox_cmd[0], &mbox_sts[0]) ==
afaf5a2d
DS		 765 QLA_ERROR) {
766 DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_DATABASE_ENTRY failed"
767 " with status 0x%04X\n", ha->host_no, __func__,
768 mbox_sts[0]));
769 goto exit_get_fwddb;
770 }
771 if (fw_ddb_index != mbox_sts[1]) {
f4f5df23 772 DEBUG2(printk("scsi%ld: %s: ddb mismatch [%d] != [%d].\n",
afaf5a2d
DS		 773 ha->host_no, __func__, fw_ddb_index,
774 mbox_sts[1]));
775 goto exit_get_fwddb;
776 }
777 if (fw_ddb_entry) {
2a49a78e
VC		 778 options = le16_to_cpu(fw_ddb_entry->options);
779 if (options & DDB_OPT_IPV6_DEVICE) {
c2660df3 780 ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
2a49a78e
VC		 781 "Next %d State %04x ConnErr %08x %pI6 "
782 ":%04d \"%s\"\n", __func__, fw_ddb_index,
783 mbox_sts[0], mbox_sts[2], mbox_sts[3],
784 mbox_sts[4], mbox_sts[5],
785 fw_ddb_entry->ip_addr,
786 le16_to_cpu(fw_ddb_entry->port),
787 fw_ddb_entry->iscsi_name);
788 } else {
c2660df3 789 ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
2a49a78e
VC		 790 "Next %d State %04x ConnErr %08x %pI4 "
791 ":%04d \"%s\"\n", __func__, fw_ddb_index,
792 mbox_sts[0], mbox_sts[2], mbox_sts[3],
793 mbox_sts[4], mbox_sts[5],
794 fw_ddb_entry->ip_addr,
795 le16_to_cpu(fw_ddb_entry->port),
796 fw_ddb_entry->iscsi_name);
797 }
afaf5a2d
DS		 798 }
799 if (num_valid_ddb_entries)
800 *num_valid_ddb_entries = mbox_sts[2];
801 if (next_ddb_index)
802 *next_ddb_index = mbox_sts[3];
803 if (fw_ddb_device_state)
804 *fw_ddb_device_state = mbox_sts[4];
805
806 /*
807 * RA: This mailbox has been changed to pass connection error and
808 * details. Its true for ISP4010 as per Version E - Not sure when it
809 * was changed. Get the time2wait from the fw_dd_entry field :
810 * default_time2wait which we call it as minTime2Wait DEV_DB_ENTRY
811 * struct.
812 */
813 if (conn_err_detail)
814 *conn_err_detail = mbox_sts[5];
815 if (tcp_source_port_num)
1482338f 816 *tcp_source_port_num = (uint16_t) (mbox_sts[6] >> 16);
afaf5a2d
DS		 817 if (connection_id)
818 *connection_id = (uint16_t) mbox_sts[6] & 0x00FF;
819 status = QLA_SUCCESS;
820
821exit_get_fwddb:
822 return status;
823}
824
b3a271a9
MR		 825int qla4xxx_conn_open(struct scsi_qla_host *ha, uint16_t fw_ddb_index)
826{
827 uint32_t mbox_cmd[MBOX_REG_COUNT];
828 uint32_t mbox_sts[MBOX_REG_COUNT];
829 int status;
830
831 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
832 memset(&mbox_sts, 0, sizeof(mbox_sts));
833
834 mbox_cmd[0] = MBOX_CMD_CONN_OPEN;
835 mbox_cmd[1] = fw_ddb_index;
836
837 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
838 &mbox_sts[0]);
839 DEBUG2(ql4_printk(KERN_INFO, ha,
840 "%s: status = %d mbx0 = 0x%x mbx1 = 0x%x\n",
841 __func__, status, mbox_sts[0], mbox_sts[1]));
842 return status;
843}
844
afaf5a2d
DS		 845/**
846 * qla4xxx_set_fwddb_entry - sets a ddb entry.
847 * @ha: Pointer to host adapter structure.
848 * @fw_ddb_index: Firmware's device database index
b3a271a9
MR		 849 * @fw_ddb_entry_dma: dma address of ddb entry
850 * @mbx_sts: mailbox 0 to be returned or NULL
afaf5a2d
DS		 851 *
852 * This routine initializes or updates the adapter's device database
b3a271a9 853 * entry for the specified device.
afaf5a2d
DS		 854 **/
855int qla4xxx_set_ddb_entry(struct scsi_qla_host * ha, uint16_t fw_ddb_index,
b3a271a9 856 dma_addr_t fw_ddb_entry_dma, uint32_t *mbx_sts)
afaf5a2d
DS		 857{
858 uint32_t mbox_cmd[MBOX_REG_COUNT];
859 uint32_t mbox_sts[MBOX_REG_COUNT];
f4f5df23 860 int status;
afaf5a2d
DS		 861
862 /* Do not wait for completion. The firmware will send us an
863 * ASTS_DATABASE_CHANGED (0x8014) to notify us of the login status.
864 */
865 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
866 memset(&mbox_sts, 0, sizeof(mbox_sts));
867
868 mbox_cmd[0] = MBOX_CMD_SET_DATABASE_ENTRY;
869 mbox_cmd[1] = (uint32_t) fw_ddb_index;
870 mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
871 mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
c0e344c9 872 mbox_cmd[4] = sizeof(struct dev_db_entry);
afaf5a2d 873
f4f5df23 874 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
b3a271a9
MR		 875 &mbox_sts[0]);
876 if (mbx_sts)
877 *mbx_sts = mbox_sts[0];
f4f5df23
VC		 878 DEBUG2(printk("scsi%ld: %s: status=%d mbx0=0x%x mbx4=0x%x\n",
879 ha->host_no, __func__, status, mbox_sts[0], mbox_sts[4]);)
880
881 return status;
afaf5a2d
DS		 882}
883
b3a271a9
MR		 884int qla4xxx_session_logout_ddb(struct scsi_qla_host *ha,
885 struct ddb_entry *ddb_entry, int options)
886{
887 int status;
888 uint32_t mbox_cmd[MBOX_REG_COUNT];
889 uint32_t mbox_sts[MBOX_REG_COUNT];
890
891 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
892 memset(&mbox_sts, 0, sizeof(mbox_sts));
893
894 mbox_cmd[0] = MBOX_CMD_CONN_CLOSE_SESS_LOGOUT;
895 mbox_cmd[1] = ddb_entry->fw_ddb_index;
896 mbox_cmd[3] = options;
897
898 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
899 &mbox_sts[0]);
900 if (status != QLA_SUCCESS) {
901 DEBUG2(ql4_printk(KERN_INFO, ha,
902 "%s: MBOX_CMD_CONN_CLOSE_SESS_LOGOUT "
903 "failed sts %04X %04X", __func__,
904 mbox_sts[0], mbox_sts[1]));
905 }
906
907 return status;
908}
909
afaf5a2d
DS		 910/**
911 * qla4xxx_get_crash_record - retrieves crash record.
912 * @ha: Pointer to host adapter structure.
913 *
914 * This routine retrieves a crash record from the QLA4010 after an 8002h aen.
915 **/
916void qla4xxx_get_crash_record(struct scsi_qla_host * ha)
917{
918 uint32_t mbox_cmd[MBOX_REG_COUNT];
919 uint32_t mbox_sts[MBOX_REG_COUNT];
920 struct crash_record *crash_record = NULL;
921 dma_addr_t crash_record_dma = 0;
922 uint32_t crash_record_size = 0;
c0e344c9 923
afaf5a2d
DS		 924 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
925 memset(&mbox_sts, 0, sizeof(mbox_cmd));
926
927 /* Get size of crash record. */
928 mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
c0e344c9
DS		 929
930 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
afaf5a2d
DS		 931 QLA_SUCCESS) {
932 DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve size!\n",
933 ha->host_no, __func__));
934 goto exit_get_crash_record;
935 }
936 crash_record_size = mbox_sts[4];
937 if (crash_record_size == 0) {
938 DEBUG2(printk("scsi%ld: %s: ERROR: Crash record size is 0!\n",
939 ha->host_no, __func__));
940 goto exit_get_crash_record;
941 }
942
943 /* Alloc Memory for Crash Record. */
944 crash_record = dma_alloc_coherent(&ha->pdev->dev, crash_record_size,
945 &crash_record_dma, GFP_KERNEL);
946 if (crash_record == NULL)
947 goto exit_get_crash_record;
948
949 /* Get Crash Record. */
c0e344c9
DS		 950 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
951 memset(&mbox_sts, 0, sizeof(mbox_cmd));
952
afaf5a2d
DS		 953 mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
954 mbox_cmd[2] = LSDW(crash_record_dma);
955 mbox_cmd[3] = MSDW(crash_record_dma);
956 mbox_cmd[4] = crash_record_size;
c0e344c9
DS		 957
958 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
afaf5a2d
DS		 959 QLA_SUCCESS)
960 goto exit_get_crash_record;
961
962 /* Dump Crash Record. */
963
964exit_get_crash_record:
965 if (crash_record)
966 dma_free_coherent(&ha->pdev->dev, crash_record_size,
967 crash_record, crash_record_dma);
968}
969
970/**
971 * qla4xxx_get_conn_event_log - retrieves connection event log
972 * @ha: Pointer to host adapter structure.
973 **/
974void qla4xxx_get_conn_event_log(struct scsi_qla_host * ha)
975{
976 uint32_t mbox_cmd[MBOX_REG_COUNT];
977 uint32_t mbox_sts[MBOX_REG_COUNT];
978 struct conn_event_log_entry *event_log = NULL;
979 dma_addr_t event_log_dma = 0;
980 uint32_t event_log_size = 0;
981 uint32_t num_valid_entries;
982 uint32_t oldest_entry = 0;
983 uint32_t max_event_log_entries;
984 uint8_t i;
985
afaf5a2d
DS		 986 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
987 memset(&mbox_sts, 0, sizeof(mbox_cmd));
988
989 /* Get size of crash record. */
990 mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
c0e344c9
DS		 991
992 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
afaf5a2d
DS		 993 QLA_SUCCESS)
994 goto exit_get_event_log;
995
996 event_log_size = mbox_sts[4];
997 if (event_log_size == 0)
998 goto exit_get_event_log;
999
1000 /* Alloc Memory for Crash Record. */
1001 event_log = dma_alloc_coherent(&ha->pdev->dev, event_log_size,
1002 &event_log_dma, GFP_KERNEL);
1003 if (event_log == NULL)
1004 goto exit_get_event_log;
1005
1006 /* Get Crash Record. */
c0e344c9
DS		 1007 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1008 memset(&mbox_sts, 0, sizeof(mbox_cmd));
1009
afaf5a2d
DS		 1010 mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
1011 mbox_cmd[2] = LSDW(event_log_dma);
1012 mbox_cmd[3] = MSDW(event_log_dma);
c0e344c9
DS		 1013
1014 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
afaf5a2d
DS		 1015 QLA_SUCCESS) {
1016 DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve event "
1017 "log!\n", ha->host_no, __func__));
1018 goto exit_get_event_log;
1019 }
1020
1021 /* Dump Event Log. */
1022 num_valid_entries = mbox_sts[1];
1023
1024 max_event_log_entries = event_log_size /
1025 sizeof(struct conn_event_log_entry);
1026
1027 if (num_valid_entries > max_event_log_entries)
1028 oldest_entry = num_valid_entries % max_event_log_entries;
1029
1030 DEBUG3(printk("scsi%ld: Connection Event Log Dump (%d entries):\n",
1031 ha->host_no, num_valid_entries));
1032
11010fec 1033 if (ql4xextended_error_logging == 3) {
afaf5a2d
DS		 1034 if (oldest_entry == 0) {
1035 /* Circular Buffer has not wrapped around */
1036 for (i=0; i < num_valid_entries; i++) {
1037 qla4xxx_dump_buffer((uint8_t *)event_log+
1038 (i*sizeof(*event_log)),
1039 sizeof(*event_log));
1040 }
1041 }
1042 else {
1043 /* Circular Buffer has wrapped around -
1044 * display accordingly*/
1045 for (i=oldest_entry; i < max_event_log_entries; i++) {
1046 qla4xxx_dump_buffer((uint8_t *)event_log+
1047 (i*sizeof(*event_log)),
1048 sizeof(*event_log));
1049 }
1050 for (i=0; i < oldest_entry; i++) {
1051 qla4xxx_dump_buffer((uint8_t *)event_log+
1052 (i*sizeof(*event_log)),
1053 sizeof(*event_log));
1054 }
1055 }
1056 }
1057
1058exit_get_event_log:
1059 if (event_log)
1060 dma_free_coherent(&ha->pdev->dev, event_log_size, event_log,
1061 event_log_dma);
1062}
1063
09a0f719
VC		 1064/**
1065 * qla4xxx_abort_task - issues Abort Task
1066 * @ha: Pointer to host adapter structure.
1067 * @srb: Pointer to srb entry
1068 *
1069 * This routine performs a LUN RESET on the specified target/lun.
1070 * The caller must ensure that the ddb_entry and lun_entry pointers
1071 * are valid before calling this routine.
1072 **/
1073int qla4xxx_abort_task(struct scsi_qla_host *ha, struct srb *srb)
1074{
1075 uint32_t mbox_cmd[MBOX_REG_COUNT];
1076 uint32_t mbox_sts[MBOX_REG_COUNT];
1077 struct scsi_cmnd *cmd = srb->cmd;
1078 int status = QLA_SUCCESS;
1079 unsigned long flags = 0;
1080 uint32_t index;
1081
1082 /*
1083 * Send abort task command to ISP, so that the ISP will return
1084 * request with ABORT status
1085 */
1086 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1087 memset(&mbox_sts, 0, sizeof(mbox_sts));
1088
1089 spin_lock_irqsave(&ha->hardware_lock, flags);
1090 index = (unsigned long)(unsigned char *)cmd->host_scribble;
1091 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1092
1093 /* Firmware already posted completion on response queue */
1094 if (index == MAX_SRBS)
1095 return status;
1096
1097 mbox_cmd[0] = MBOX_CMD_ABORT_TASK;
6790d4fe 1098 mbox_cmd[1] = srb->ddb->fw_ddb_index;
09a0f719
VC		 1099 mbox_cmd[2] = index;
1100 /* Immediate Command Enable */
1101 mbox_cmd[5] = 0x01;
1102
1103 qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
1104 &mbox_sts[0]);
1105 if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE) {
1106 status = QLA_ERROR;
1107
1108 DEBUG2(printk(KERN_WARNING "scsi%ld:%d:%d: abort task FAILED: "
1109 "mbx0=%04X, mb1=%04X, mb2=%04X, mb3=%04X, mb4=%04X\n",
1110 ha->host_no, cmd->device->id, cmd->device->lun, mbox_sts[0],
1111 mbox_sts[1], mbox_sts[2], mbox_sts[3], mbox_sts[4]));
1112 }
1113
1114 return status;
1115}
1116
afaf5a2d
DS		 1117/**
1118 * qla4xxx_reset_lun - issues LUN Reset
1119 * @ha: Pointer to host adapter structure.
f4f5df23
VC		 1120 * @ddb_entry: Pointer to device database entry
1121 * @lun: lun number
afaf5a2d
DS		 1122 *
1123 * This routine performs a LUN RESET on the specified target/lun.
1124 * The caller must ensure that the ddb_entry and lun_entry pointers
1125 * are valid before calling this routine.
1126 **/
1127int qla4xxx_reset_lun(struct scsi_qla_host * ha, struct ddb_entry * ddb_entry,
1128 int lun)
1129{
1130 uint32_t mbox_cmd[MBOX_REG_COUNT];
1131 uint32_t mbox_sts[MBOX_REG_COUNT];
1132 int status = QLA_SUCCESS;
1133
1134 DEBUG2(printk("scsi%ld:%d:%d: lun reset issued\n", ha->host_no,
f4f5df23 1135 ddb_entry->fw_ddb_index, lun));
afaf5a2d
DS		 1136
1137 /*
1138 * Send lun reset command to ISP, so that the ISP will return all
1139 * outstanding requests with RESET status
1140 */
1141 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1142 memset(&mbox_sts, 0, sizeof(mbox_sts));
c0e344c9 1143
afaf5a2d
DS		 1144 mbox_cmd[0] = MBOX_CMD_LUN_RESET;
1145 mbox_cmd[1] = ddb_entry->fw_ddb_index;
1146 mbox_cmd[2] = lun << 8;
1147 mbox_cmd[5] = 0x01; /* Immediate Command Enable */
c0e344c9
DS		 1148
1149 qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]);
afaf5a2d
DS		 1150 if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
1151 mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
1152 status = QLA_ERROR;
1153
1154 return status;
1155}
1156
ce545039
MC		 1157/**
1158 * qla4xxx_reset_target - issues target Reset
1159 * @ha: Pointer to host adapter structure.
1160 * @db_entry: Pointer to device database entry
1161 * @un_entry: Pointer to lun entry structure
1162 *
1163 * This routine performs a TARGET RESET on the specified target.
1164 * The caller must ensure that the ddb_entry pointers
1165 * are valid before calling this routine.
1166 **/
1167int qla4xxx_reset_target(struct scsi_qla_host *ha,
1168 struct ddb_entry *ddb_entry)
1169{
1170 uint32_t mbox_cmd[MBOX_REG_COUNT];
1171 uint32_t mbox_sts[MBOX_REG_COUNT];
1172 int status = QLA_SUCCESS;
1173
1174 DEBUG2(printk("scsi%ld:%d: target reset issued\n", ha->host_no,
f4f5df23 1175 ddb_entry->fw_ddb_index));
ce545039
MC		 1176
1177 /*
1178 * Send target reset command to ISP, so that the ISP will return all
1179 * outstanding requests with RESET status
1180 */
1181 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1182 memset(&mbox_sts, 0, sizeof(mbox_sts));
1183
1184 mbox_cmd[0] = MBOX_CMD_TARGET_WARM_RESET;
1185 mbox_cmd[1] = ddb_entry->fw_ddb_index;
1186 mbox_cmd[5] = 0x01; /* Immediate Command Enable */
1187
1188 qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
1189 &mbox_sts[0]);
1190 if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
1191 mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
1192 status = QLA_ERROR;
1193
1194 return status;
1195}
afaf5a2d
DS		 1196
1197int qla4xxx_get_flash(struct scsi_qla_host * ha, dma_addr_t dma_addr,
1198 uint32_t offset, uint32_t len)
1199{
1200 uint32_t mbox_cmd[MBOX_REG_COUNT];
1201 uint32_t mbox_sts[MBOX_REG_COUNT];
1202
1203 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1204 memset(&mbox_sts, 0, sizeof(mbox_sts));
c0e344c9 1205
afaf5a2d
DS		 1206 mbox_cmd[0] = MBOX_CMD_READ_FLASH;
1207 mbox_cmd[1] = LSDW(dma_addr);
1208 mbox_cmd[2] = MSDW(dma_addr);
1209 mbox_cmd[3] = offset;
1210 mbox_cmd[4] = len;
c0e344c9
DS		 1211
1212 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0], &mbox_sts[0]) !=
afaf5a2d
DS		 1213 QLA_SUCCESS) {
1214 DEBUG2(printk("scsi%ld: %s: MBOX_CMD_READ_FLASH, failed w/ "
1215 "status %04X %04X, offset %08x, len %08x\n", ha->host_no,
1216 __func__, mbox_sts[0], mbox_sts[1], offset, len));
1217 return QLA_ERROR;
1218 }
1219 return QLA_SUCCESS;
1220}
1221
1222/**
7ad633c0 1223 * qla4xxx_about_firmware - gets FW, iscsi draft and boot loader version
afaf5a2d
DS		 1224 * @ha: Pointer to host adapter structure.
1225 *
7ad633c0
HZ		 1226 * Retrieves the FW version, iSCSI draft version & bootloader version of HBA.
1227 * Mailboxes 2 & 3 may hold an address for data. Make sure that we write 0 to
1228 * those mailboxes, if unused.
afaf5a2d 1229 **/
7ad633c0 1230int qla4xxx_about_firmware(struct scsi_qla_host *ha)
afaf5a2d 1231{
7ad633c0
HZ		 1232 struct about_fw_info *about_fw = NULL;
1233 dma_addr_t about_fw_dma;
afaf5a2d
DS		 1234 uint32_t mbox_cmd[MBOX_REG_COUNT];
1235 uint32_t mbox_sts[MBOX_REG_COUNT];
7ad633c0
HZ		 1236 int status = QLA_ERROR;
1237
1238 about_fw = dma_alloc_coherent(&ha->pdev->dev,
1239 sizeof(struct about_fw_info),
1240 &about_fw_dma, GFP_KERNEL);
1241 if (!about_fw) {
1242 DEBUG2(ql4_printk(KERN_ERR, ha, "%s: Unable to alloc memory "
1243 "for about_fw\n", __func__));
1244 return status;
1245 }
afaf5a2d 1246
7ad633c0 1247 memset(about_fw, 0, sizeof(struct about_fw_info));
afaf5a2d
DS		 1248 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1249 memset(&mbox_sts, 0, sizeof(mbox_sts));
c0e344c9 1250
afaf5a2d 1251 mbox_cmd[0] = MBOX_CMD_ABOUT_FW;
7ad633c0
HZ		 1252 mbox_cmd[2] = LSDW(about_fw_dma);
1253 mbox_cmd[3] = MSDW(about_fw_dma);
1254 mbox_cmd[4] = sizeof(struct about_fw_info);
1255
1256 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
1257 &mbox_cmd[0], &mbox_sts[0]);
1258 if (status != QLA_SUCCESS) {
1259 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_ABOUT_FW "
1260 "failed w/ status %04X\n", __func__,
1261 mbox_sts[0]));
1262 goto exit_about_fw;
afaf5a2d
DS		 1263 }
1264
7ad633c0
HZ		 1265 /* Save version information. */
1266 ha->firmware_version[0] = le16_to_cpu(about_fw->fw_major);
1267 ha->firmware_version[1] = le16_to_cpu(about_fw->fw_minor);
1268 ha->patch_number = le16_to_cpu(about_fw->fw_patch);
1269 ha->build_number = le16_to_cpu(about_fw->fw_build);
1270 ha->iscsi_major = le16_to_cpu(about_fw->iscsi_major);
1271 ha->iscsi_minor = le16_to_cpu(about_fw->iscsi_minor);
1272 ha->bootload_major = le16_to_cpu(about_fw->bootload_major);
1273 ha->bootload_minor = le16_to_cpu(about_fw->bootload_minor);
1274 ha->bootload_patch = le16_to_cpu(about_fw->bootload_patch);
1275 ha->bootload_build = le16_to_cpu(about_fw->bootload_build);
1276 status = QLA_SUCCESS;
afaf5a2d 1277
7ad633c0
HZ		 1278exit_about_fw:
1279 dma_free_coherent(&ha->pdev->dev, sizeof(struct about_fw_info),
1280 about_fw, about_fw_dma);
1281 return status;
afaf5a2d
DS		 1282}
1283
b3a271a9 1284static int qla4xxx_get_default_ddb(struct scsi_qla_host *ha, uint32_t options,
47975477 1285 dma_addr_t dma_addr)
afaf5a2d
DS		 1286{
1287 uint32_t mbox_cmd[MBOX_REG_COUNT];
1288 uint32_t mbox_sts[MBOX_REG_COUNT];
1289
1290 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1291 memset(&mbox_sts, 0, sizeof(mbox_sts));
1292
1293 mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS;
b3a271a9 1294 mbox_cmd[1] = options;
afaf5a2d
DS		 1295 mbox_cmd[2] = LSDW(dma_addr);
1296 mbox_cmd[3] = MSDW(dma_addr);
1297
c0e344c9 1298 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]) !=
afaf5a2d
DS		 1299 QLA_SUCCESS) {
1300 DEBUG2(printk("scsi%ld: %s: failed status %04X\n",
1301 ha->host_no, __func__, mbox_sts[0]));
1302 return QLA_ERROR;
1303 }
1304 return QLA_SUCCESS;
1305}
1306
b3a271a9
MR		 1307int qla4xxx_req_ddb_entry(struct scsi_qla_host *ha, uint32_t ddb_index,
1308 uint32_t *mbx_sts)
afaf5a2d 1309{
b3a271a9 1310 int status;
afaf5a2d
DS		 1311 uint32_t mbox_cmd[MBOX_REG_COUNT];
1312 uint32_t mbox_sts[MBOX_REG_COUNT];
1313
1314 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1315 memset(&mbox_sts, 0, sizeof(mbox_sts));
1316
1317 mbox_cmd[0] = MBOX_CMD_REQUEST_DATABASE_ENTRY;
b3a271a9 1318 mbox_cmd[1] = ddb_index;
afaf5a2d 1319
b3a271a9
MR		 1320 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
1321 &mbox_sts[0]);
1322 if (status != QLA_SUCCESS) {
1323 DEBUG2(ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
1324 __func__, mbox_sts[0]));
afaf5a2d
DS		 1325 }
1326
b3a271a9
MR		 1327 *mbx_sts = mbox_sts[0];
1328 return status;
afaf5a2d
DS		 1329}
1330
b3a271a9
MR		 1331int qla4xxx_clear_ddb_entry(struct scsi_qla_host *ha, uint32_t ddb_index)
1332{
1333 int status;
1334 uint32_t mbox_cmd[MBOX_REG_COUNT];
1335 uint32_t mbox_sts[MBOX_REG_COUNT];
1336
1337 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1338 memset(&mbox_sts, 0, sizeof(mbox_sts));
1339
1340 mbox_cmd[0] = MBOX_CMD_CLEAR_DATABASE_ENTRY;
1341 mbox_cmd[1] = ddb_index;
1342
1343 status = qla4xxx_mailbox_command(ha, 2, 1, &mbox_cmd[0],
1344 &mbox_sts[0]);
1345 if (status != QLA_SUCCESS) {
1346 DEBUG2(ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
1347 __func__, mbox_sts[0]));
1348 }
1349
1350 return status;
1351}
1352
d00efe3f
MC		 1353int qla4xxx_set_flash(struct scsi_qla_host *ha, dma_addr_t dma_addr,
1354 uint32_t offset, uint32_t length, uint32_t options)
1355{
1356 uint32_t mbox_cmd[MBOX_REG_COUNT];
1357 uint32_t mbox_sts[MBOX_REG_COUNT];
1358 int status = QLA_SUCCESS;
1359
1360 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1361 memset(&mbox_sts, 0, sizeof(mbox_sts));
1362
1363 mbox_cmd[0] = MBOX_CMD_WRITE_FLASH;
1364 mbox_cmd[1] = LSDW(dma_addr);
1365 mbox_cmd[2] = MSDW(dma_addr);
1366 mbox_cmd[3] = offset;
1367 mbox_cmd[4] = length;
1368 mbox_cmd[5] = options;
1369
1370 status = qla4xxx_mailbox_command(ha, 6, 2, &mbox_cmd[0], &mbox_sts[0]);
1371 if (status != QLA_SUCCESS) {
1372 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_WRITE_FLASH "
1373 "failed w/ status %04X, mbx1 %04X\n",
1374 __func__, mbox_sts[0], mbox_sts[1]));
1375 }
1376 return status;
1377}
1378
2a991c21
MR		 1379int qla4xxx_bootdb_by_index(struct scsi_qla_host *ha,
1380 struct dev_db_entry *fw_ddb_entry,
1381 dma_addr_t fw_ddb_entry_dma, uint16_t ddb_index)
1382{
1383 uint32_t dev_db_start_offset = FLASH_OFFSET_DB_INFO;
1384 uint32_t dev_db_end_offset;
1385 int status = QLA_ERROR;
1386
1387 memset(fw_ddb_entry, 0, sizeof(*fw_ddb_entry));
1388
1389 dev_db_start_offset += (ddb_index * sizeof(*fw_ddb_entry));
1390 dev_db_end_offset = FLASH_OFFSET_DB_END;
1391
1392 if (dev_db_start_offset > dev_db_end_offset) {
1393 DEBUG2(ql4_printk(KERN_ERR, ha,
1394 "%s:Invalid DDB index %d", __func__,
1395 ddb_index));
1396 goto exit_bootdb_failed;
1397 }
1398
1399 if (qla4xxx_get_flash(ha, fw_ddb_entry_dma, dev_db_start_offset,
1400 sizeof(*fw_ddb_entry)) != QLA_SUCCESS) {
1401 ql4_printk(KERN_ERR, ha, "scsi%ld: %s: Get Flash"
1402 "failed\n", ha->host_no, __func__);
1403 goto exit_bootdb_failed;
1404 }
1405
1406 if (fw_ddb_entry->cookie == DDB_VALID_COOKIE)
1407 status = QLA_SUCCESS;
1408
1409exit_bootdb_failed:
1410 return status;
1411}
1412
1413int qla4xxx_get_chap(struct scsi_qla_host *ha, char *username, char *password,
1414 uint16_t idx)
1415{
1416 int ret = 0;
1417 int rval = QLA_ERROR;
4549415a 1418 uint32_t offset = 0, chap_size;
2a991c21
MR		 1419 struct ql4_chap_table *chap_table;
1420 dma_addr_t chap_dma;
1421
1422 chap_table = dma_pool_alloc(ha->chap_dma_pool, GFP_KERNEL, &chap_dma);
1423 if (chap_table == NULL) {
1424 ret = -ENOMEM;
1425 goto exit_get_chap;
1426 }
1427
4549415a
LC		 1428 chap_size = sizeof(struct ql4_chap_table);
1429 memset(chap_table, 0, chap_size);
1430
1431 if (is_qla40XX(ha))
1432 offset = FLASH_CHAP_OFFSET | (idx * chap_size);
1433 else {
1434 offset = FLASH_RAW_ACCESS_ADDR + (ha->hw.flt_region_chap << 2);
1435 /* flt_chap_size is CHAP table size for both ports
1436 * so divide it by 2 to calculate the offset for second port
1437 */
1438 if (ha->port_num == 1)
1439 offset += (ha->hw.flt_chap_size / 2);
1440 offset += (idx * chap_size);
1441 }
2a991c21 1442
4549415a 1443 rval = qla4xxx_get_flash(ha, chap_dma, offset, chap_size);
2a991c21
MR		 1444 if (rval != QLA_SUCCESS) {
1445 ret = -EINVAL;
1446 goto exit_get_chap;
1447 }
1448
1449 DEBUG2(ql4_printk(KERN_INFO, ha, "Chap Cookie: x%x\n",
1450 __le16_to_cpu(chap_table->cookie)));
1451
1452 if (__le16_to_cpu(chap_table->cookie) != CHAP_VALID_COOKIE) {
1453 ql4_printk(KERN_ERR, ha, "No valid chap entry found\n");
1454 goto exit_get_chap;
1455 }
1456
1457 strncpy(password, chap_table->secret, QL4_CHAP_MAX_SECRET_LEN);
1458 strncpy(username, chap_table->name, QL4_CHAP_MAX_NAME_LEN);
1459 chap_table->cookie = __constant_cpu_to_le16(CHAP_VALID_COOKIE);
1460
1461exit_get_chap:
1462 dma_pool_free(ha->chap_dma_pool, chap_table, chap_dma);
1463 return ret;
1464}
1465
b3a271a9
MR		 1466static int qla4xxx_set_chap(struct scsi_qla_host *ha, char *username,
1467 char *password, uint16_t idx, int bidi)
1468{
1469 int ret = 0;
1470 int rval = QLA_ERROR;
1471 uint32_t offset = 0;
1472 struct ql4_chap_table *chap_table;
1473 dma_addr_t chap_dma;
1474
1475 chap_table = dma_pool_alloc(ha->chap_dma_pool, GFP_KERNEL, &chap_dma);
1476 if (chap_table == NULL) {
1477 ret = -ENOMEM;
1478 goto exit_set_chap;
1479 }
1480
1481 memset(chap_table, 0, sizeof(struct ql4_chap_table));
1482 if (bidi)
1483 chap_table->flags |= BIT_6; /* peer */
1484 else
1485 chap_table->flags |= BIT_7; /* local */
1486 chap_table->secret_len = strlen(password);
1487 strncpy(chap_table->secret, password, MAX_CHAP_SECRET_LEN);
1488 strncpy(chap_table->name, username, MAX_CHAP_NAME_LEN);
1489 chap_table->cookie = __constant_cpu_to_le16(CHAP_VALID_COOKIE);
4549415a 1490 offset = FLASH_CHAP_OFFSET | (idx * sizeof(struct ql4_chap_table));
b3a271a9
MR		 1491 rval = qla4xxx_set_flash(ha, chap_dma, offset,
1492 sizeof(struct ql4_chap_table),
1493 FLASH_OPT_RMW_COMMIT);
4549415a
LC		 1494
1495 if (rval == QLA_SUCCESS && ha->chap_list) {
1496 /* Update ha chap_list cache */
1497 memcpy((struct ql4_chap_table *)ha->chap_list + idx,
1498 chap_table, sizeof(struct ql4_chap_table));
1499 }
b3a271a9
MR		 1500 dma_pool_free(ha->chap_dma_pool, chap_table, chap_dma);
1501 if (rval != QLA_SUCCESS)
1502 ret = -EINVAL;
1503
1504exit_set_chap:
1505 return ret;
1506}
1507
4549415a
LC		 1508/**
1509 * qla4xxx_get_chap_index - Get chap index given username and secret
1510 * @ha: pointer to adapter structure
1511 * @username: CHAP username to be searched
1512 * @password: CHAP password to be searched
1513 * @bidi: Is this a BIDI CHAP
1514 * @chap_index: CHAP index to be returned
1515 *
1516 * Match the username and password in the chap_list, return the index if a
1517 * match is found. If a match is not found then add the entry in FLASH and
1518 * return the index at which entry is written in the FLASH.
1519 **/
fca9f04d
MC		 1520int qla4xxx_get_chap_index(struct scsi_qla_host *ha, char *username,
1521 char *password, int bidi, uint16_t *chap_index)
4549415a
LC		 1522{
1523 int i, rval;
1524 int free_index = -1;
1525 int found_index = 0;
1526 int max_chap_entries = 0;
1527 struct ql4_chap_table *chap_table;
1528
1529 if (is_qla8022(ha))
1530 max_chap_entries = (ha->hw.flt_chap_size / 2) /
1531 sizeof(struct ql4_chap_table);
1532 else
1533 max_chap_entries = MAX_CHAP_ENTRIES_40XX;
1534
1535 if (!ha->chap_list) {
1536 ql4_printk(KERN_ERR, ha, "Do not have CHAP table cache\n");
1537 return QLA_ERROR;
1538 }
1539
fca9f04d
MC		 1540 if (!username || !password) {
1541 ql4_printk(KERN_ERR, ha, "Do not have username and psw\n");
1542 return QLA_ERROR;
1543 }
1544
4549415a
LC		 1545 mutex_lock(&ha->chap_sem);
1546 for (i = 0; i < max_chap_entries; i++) {
1547 chap_table = (struct ql4_chap_table *)ha->chap_list + i;
1548 if (chap_table->cookie !=
1549 __constant_cpu_to_le16(CHAP_VALID_COOKIE)) {
1550 if (i > MAX_RESRV_CHAP_IDX && free_index == -1)
1551 free_index = i;
1552 continue;
1553 }
1554 if (bidi) {
1555 if (chap_table->flags & BIT_7)
1556 continue;
1557 } else {
1558 if (chap_table->flags & BIT_6)
1559 continue;
1560 }
1561 if (!strncmp(chap_table->secret, password,
1562 MAX_CHAP_SECRET_LEN) &&
1563 !strncmp(chap_table->name, username,
1564 MAX_CHAP_NAME_LEN)) {
1565 *chap_index = i;
1566 found_index = 1;
1567 break;
1568 }
1569 }
1570
1571 /* If chap entry is not present and a free index is available then
1572 * write the entry in flash
1573 */
1574 if (!found_index && free_index != -1) {
1575 rval = qla4xxx_set_chap(ha, username, password,
1576 free_index, bidi);
1577 if (!rval) {
1578 *chap_index = free_index;
1579 found_index = 1;
1580 }
1581 }
1582
1583 mutex_unlock(&ha->chap_sem);
1584
1585 if (found_index)
1586 return QLA_SUCCESS;
1587 return QLA_ERROR;
1588}
1589
d00efe3f
MC		 1590int qla4xxx_conn_close_sess_logout(struct scsi_qla_host *ha,
1591 uint16_t fw_ddb_index,
1592 uint16_t connection_id,
1593 uint16_t option)
1594{
1595 uint32_t mbox_cmd[MBOX_REG_COUNT];
1596 uint32_t mbox_sts[MBOX_REG_COUNT];
1597 int status = QLA_SUCCESS;
1598
1599 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1600 memset(&mbox_sts, 0, sizeof(mbox_sts));
1601
1602 mbox_cmd[0] = MBOX_CMD_CONN_CLOSE_SESS_LOGOUT;
1603 mbox_cmd[1] = fw_ddb_index;
1604 mbox_cmd[2] = connection_id;
1605 mbox_cmd[3] = option;
1606
1607 status = qla4xxx_mailbox_command(ha, 4, 2, &mbox_cmd[0], &mbox_sts[0]);
1608 if (status != QLA_SUCCESS) {
1609 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_CONN_CLOSE "
1610 "option %04x failed w/ status %04X %04X\n",
1611 __func__, option, mbox_sts[0], mbox_sts[1]));
1612 }
1613 return status;
1614}
1615
1616int qla4xxx_disable_acb(struct scsi_qla_host *ha)
1617{
1618 uint32_t mbox_cmd[MBOX_REG_COUNT];
1619 uint32_t mbox_sts[MBOX_REG_COUNT];
1620 int status = QLA_SUCCESS;
1621
1622 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1623 memset(&mbox_sts, 0, sizeof(mbox_sts));
1624
1625 mbox_cmd[0] = MBOX_CMD_DISABLE_ACB;
1626
1627 status = qla4xxx_mailbox_command(ha, 8, 5, &mbox_cmd[0], &mbox_sts[0]);
1628 if (status != QLA_SUCCESS) {
1629 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_DISABLE_ACB "
1630 "failed w/ status %04X %04X %04X", __func__,
1631 mbox_sts[0], mbox_sts[1], mbox_sts[2]));
1632 }
1633 return status;
1634}
1635
6085491c
HZ		 1636int qla4xxx_get_acb(struct scsi_qla_host *ha, dma_addr_t acb_dma,
1637 uint32_t acb_type, uint32_t len)
d00efe3f 1638{
6085491c
HZ		 1639 uint32_t mbox_cmd[MBOX_REG_COUNT];
1640 uint32_t mbox_sts[MBOX_REG_COUNT];
d00efe3f
MC		 1641 int status = QLA_SUCCESS;
1642
6085491c
HZ		 1643 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1644 memset(&mbox_sts, 0, sizeof(mbox_sts));
1645
d00efe3f 1646 mbox_cmd[0] = MBOX_CMD_GET_ACB;
6085491c 1647 mbox_cmd[1] = acb_type;
d00efe3f
MC		 1648 mbox_cmd[2] = LSDW(acb_dma);
1649 mbox_cmd[3] = MSDW(acb_dma);
6085491c 1650 mbox_cmd[4] = len;
d00efe3f
MC		 1651
1652 status = qla4xxx_mailbox_command(ha, 5, 5, &mbox_cmd[0], &mbox_sts[0]);
1653 if (status != QLA_SUCCESS) {
1654 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_GET_ACB "
1655 "failed w/ status %04X\n", __func__,
1656 mbox_sts[0]));
1657 }
1658 return status;
1659}
1660
1661int qla4xxx_set_acb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
1662 uint32_t *mbox_sts, dma_addr_t acb_dma)
1663{
1664 int status = QLA_SUCCESS;
1665
1666 memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
1667 memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
1668 mbox_cmd[0] = MBOX_CMD_SET_ACB;
1669 mbox_cmd[1] = 0; /* Primary ACB */
1670 mbox_cmd[2] = LSDW(acb_dma);
1671 mbox_cmd[3] = MSDW(acb_dma);
1672 mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
1673
1674 status = qla4xxx_mailbox_command(ha, 5, 5, &mbox_cmd[0], &mbox_sts[0]);
1675 if (status != QLA_SUCCESS) {
1676 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_SET_ACB "
1677 "failed w/ status %04X\n", __func__,
1678 mbox_sts[0]));
1679 }
1680 return status;
1681}
b3a271a9
MR		 1682
1683int qla4xxx_set_param_ddbentry(struct scsi_qla_host *ha,
1684 struct ddb_entry *ddb_entry,
1685 struct iscsi_cls_conn *cls_conn,
1686 uint32_t *mbx_sts)
1687{
1688 struct dev_db_entry *fw_ddb_entry;
1689 struct iscsi_conn *conn;
1690 struct iscsi_session *sess;
1691 struct qla_conn *qla_conn;
1692 struct sockaddr *dst_addr;
1693 dma_addr_t fw_ddb_entry_dma;
1694 int status = QLA_SUCCESS;
1695 int rval = 0;
1696 struct sockaddr_in *addr;
1697 struct sockaddr_in6 *addr6;
1698 char *ip;
1699 uint16_t iscsi_opts = 0;
1700 uint32_t options = 0;
173269ef 1701 uint16_t idx, *ptid;
b3a271a9
MR		 1702
1703 fw_ddb_entry = dma_alloc_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
1704 &fw_ddb_entry_dma, GFP_KERNEL);
1705 if (!fw_ddb_entry) {
1706 DEBUG2(ql4_printk(KERN_ERR, ha,
1707 "%s: Unable to allocate dma buffer.\n",
1708 __func__));
1709 rval = -ENOMEM;
1710 goto exit_set_param_no_free;
1711 }
1712
1713 conn = cls_conn->dd_data;
1714 qla_conn = conn->dd_data;
1715 sess = conn->session;
d46bdeb1 1716 dst_addr = (struct sockaddr *)&qla_conn->qla_ep->dst_addr;
b3a271a9
MR		 1717
1718 if (dst_addr->sa_family == AF_INET6)
1719 options |= IPV6_DEFAULT_DDB_ENTRY;
1720
1721 status = qla4xxx_get_default_ddb(ha, options, fw_ddb_entry_dma);
1722 if (status == QLA_ERROR) {
1723 rval = -EINVAL;
1724 goto exit_set_param;
1725 }
1726
173269ef
MR		 1727 ptid = (uint16_t *)&fw_ddb_entry->isid[1];
1728 *ptid = cpu_to_le16((uint16_t)ddb_entry->sess->target_id);
1729
1730 DEBUG2(ql4_printk(KERN_INFO, ha, "ISID [%02x%02x%02x%02x%02x%02x]\n",
1731 fw_ddb_entry->isid[5], fw_ddb_entry->isid[4],
1732 fw_ddb_entry->isid[3], fw_ddb_entry->isid[2],
1733 fw_ddb_entry->isid[1], fw_ddb_entry->isid[0]));
1734
b3a271a9
MR		 1735 iscsi_opts = le16_to_cpu(fw_ddb_entry->iscsi_options);
1736 memset(fw_ddb_entry->iscsi_alias, 0, sizeof(fw_ddb_entry->iscsi_alias));
1737
1738 memset(fw_ddb_entry->iscsi_name, 0, sizeof(fw_ddb_entry->iscsi_name));
1739
1740 if (sess->targetname != NULL) {
1741 memcpy(fw_ddb_entry->iscsi_name, sess->targetname,
1742 min(strlen(sess->targetname),
1743 sizeof(fw_ddb_entry->iscsi_name)));
1744 }
1745
1746 memset(fw_ddb_entry->ip_addr, 0, sizeof(fw_ddb_entry->ip_addr));
1747 memset(fw_ddb_entry->tgt_addr, 0, sizeof(fw_ddb_entry->tgt_addr));
1748
1749 fw_ddb_entry->options = DDB_OPT_TARGET | DDB_OPT_AUTO_SENDTGTS_DISABLE;
1750
1751 if (dst_addr->sa_family == AF_INET) {
1752 addr = (struct sockaddr_in *)dst_addr;
1753 ip = (char *)&addr->sin_addr;
1754 memcpy(fw_ddb_entry->ip_addr, ip, IP_ADDR_LEN);
1755 fw_ddb_entry->port = cpu_to_le16(ntohs(addr->sin_port));
1756 DEBUG2(ql4_printk(KERN_INFO, ha,
1757 "%s: Destination Address [%pI4]: index [%d]\n",
1758 __func__, fw_ddb_entry->ip_addr,
1759 ddb_entry->fw_ddb_index));
1760 } else if (dst_addr->sa_family == AF_INET6) {
1761 addr6 = (struct sockaddr_in6 *)dst_addr;
1762 ip = (char *)&addr6->sin6_addr;
1763 memcpy(fw_ddb_entry->ip_addr, ip, IPv6_ADDR_LEN);
1764 fw_ddb_entry->port = cpu_to_le16(ntohs(addr6->sin6_port));
1765 fw_ddb_entry->options |= DDB_OPT_IPV6_DEVICE;
1766 DEBUG2(ql4_printk(KERN_INFO, ha,
1767 "%s: Destination Address [%pI6]: index [%d]\n",
1768 __func__, fw_ddb_entry->ip_addr,
1769 ddb_entry->fw_ddb_index));
1770 } else {
1771 ql4_printk(KERN_ERR, ha,
1772 "%s: Failed to get IP Address\n",
1773 __func__);
1774 rval = -EINVAL;
1775 goto exit_set_param;
1776 }
1777
b3a271a9
MR		 1778 /* CHAP */
1779 if (sess->username != NULL && sess->password != NULL) {
1780 if (strlen(sess->username) && strlen(sess->password)) {
1781 iscsi_opts |= BIT_7;
b3a271a9 1782
4549415a
LC		 1783 rval = qla4xxx_get_chap_index(ha, sess->username,
1784 sess->password,
1785 LOCAL_CHAP, &idx);
b3a271a9
MR		 1786 if (rval)
1787 goto exit_set_param;
1788
1789 fw_ddb_entry->chap_tbl_idx = cpu_to_le16(idx);
1790 }
1791 }
1792
1793 if (sess->username_in != NULL && sess->password_in != NULL) {
1794 /* Check if BIDI CHAP */
1795 if (strlen(sess->username_in) && strlen(sess->password_in)) {
1796 iscsi_opts |= BIT_4;
4549415a
LC		 1797
1798 rval = qla4xxx_get_chap_index(ha, sess->username_in,
1799 sess->password_in,
1800 BIDI_CHAP, &idx);
b3a271a9
MR		 1801 if (rval)
1802 goto exit_set_param;
1803 }
1804 }
1805
1806 if (sess->initial_r2t_en)
1807 iscsi_opts |= BIT_10;
1808
1809 if (sess->imm_data_en)
1810 iscsi_opts |= BIT_11;
1811
1812 fw_ddb_entry->iscsi_options = cpu_to_le16(iscsi_opts);
1813
1814 if (conn->max_recv_dlength)
1815 fw_ddb_entry->iscsi_max_rcv_data_seg_len =
1816 __constant_cpu_to_le16((conn->max_recv_dlength / BYTE_UNITS));
1817
1818 if (sess->max_r2t)
1819 fw_ddb_entry->iscsi_max_outsnd_r2t = cpu_to_le16(sess->max_r2t);
1820
1821 if (sess->first_burst)
1822 fw_ddb_entry->iscsi_first_burst_len =
1823 __constant_cpu_to_le16((sess->first_burst / BYTE_UNITS));
1824
1825 if (sess->max_burst)
1826 fw_ddb_entry->iscsi_max_burst_len =
1827 __constant_cpu_to_le16((sess->max_burst / BYTE_UNITS));
1828
1829 if (sess->time2wait)
1830 fw_ddb_entry->iscsi_def_time2wait =
1831 cpu_to_le16(sess->time2wait);
1832
1833 if (sess->time2retain)
1834 fw_ddb_entry->iscsi_def_time2retain =
1835 cpu_to_le16(sess->time2retain);
1836
1837 status = qla4xxx_set_ddb_entry(ha, ddb_entry->fw_ddb_index,
1838 fw_ddb_entry_dma, mbx_sts);
1839
1840 if (status != QLA_SUCCESS)
1841 rval = -EINVAL;
1842exit_set_param:
1843 dma_free_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
1844 fw_ddb_entry, fw_ddb_entry_dma);
1845exit_set_param_no_free:
1846 return rval;
1847}
1848
1849int qla4xxx_get_mgmt_data(struct scsi_qla_host *ha, uint16_t fw_ddb_index,
1850 uint16_t stats_size, dma_addr_t stats_dma)
1851{
1852 int status = QLA_SUCCESS;
1853 uint32_t mbox_cmd[MBOX_REG_COUNT];
1854 uint32_t mbox_sts[MBOX_REG_COUNT];
1855
1856 memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
1857 memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
1858 mbox_cmd[0] = MBOX_CMD_GET_MANAGEMENT_DATA;
1859 mbox_cmd[1] = fw_ddb_index;
1860 mbox_cmd[2] = LSDW(stats_dma);
1861 mbox_cmd[3] = MSDW(stats_dma);
1862 mbox_cmd[4] = stats_size;
1863
1864 status = qla4xxx_mailbox_command(ha, 5, 1, &mbox_cmd[0], &mbox_sts[0]);
1865 if (status != QLA_SUCCESS) {
1866 DEBUG2(ql4_printk(KERN_WARNING, ha,
1867 "%s: MBOX_CMD_GET_MANAGEMENT_DATA "
1868 "failed w/ status %04X\n", __func__,
1869 mbox_sts[0]));
1870 }
1871 return status;
1872}
8b0402e1
HZ		 1873
1874int qla4xxx_get_ip_state(struct scsi_qla_host *ha, uint32_t acb_idx,
1875 uint32_t ip_idx, uint32_t *sts)
1876{
1877 uint32_t mbox_cmd[MBOX_REG_COUNT];
1878 uint32_t mbox_sts[MBOX_REG_COUNT];
1879 int status = QLA_SUCCESS;
1880
1881 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1882 memset(&mbox_sts, 0, sizeof(mbox_sts));
1883 mbox_cmd[0] = MBOX_CMD_GET_IP_ADDR_STATE;
1884 mbox_cmd[1] = acb_idx;
1885 mbox_cmd[2] = ip_idx;
1886
1887 status = qla4xxx_mailbox_command(ha, 3, 8, &mbox_cmd[0], &mbox_sts[0]);
1888 if (status != QLA_SUCCESS) {
1889 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: "
1890 "MBOX_CMD_GET_IP_ADDR_STATE failed w/ "
1891 "status %04X\n", __func__, mbox_sts[0]));
1892 }
1893 memcpy(sts, mbox_sts, sizeof(mbox_sts));
1894 return status;
1895}
7c07d139
HZ		 1896
1897int qla4xxx_get_nvram(struct scsi_qla_host *ha, dma_addr_t nvram_dma,
1898 uint32_t offset, uint32_t size)
1899{
1900 int status = QLA_SUCCESS;
1901 uint32_t mbox_cmd[MBOX_REG_COUNT];
1902 uint32_t mbox_sts[MBOX_REG_COUNT];
1903
1904 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1905 memset(&mbox_sts, 0, sizeof(mbox_sts));
1906
1907 mbox_cmd[0] = MBOX_CMD_GET_NVRAM;
1908 mbox_cmd[1] = LSDW(nvram_dma);
1909 mbox_cmd[2] = MSDW(nvram_dma);
1910 mbox_cmd[3] = offset;
1911 mbox_cmd[4] = size;
1912
1913 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
1914 &mbox_sts[0]);
1915 if (status != QLA_SUCCESS) {
1916 DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
1917 "status %04X\n", ha->host_no, __func__,
1918 mbox_sts[0]));
1919 }
1920 return status;
1921}
1922
1923int qla4xxx_set_nvram(struct scsi_qla_host *ha, dma_addr_t nvram_dma,
1924 uint32_t offset, uint32_t size)
1925{
1926 int status = QLA_SUCCESS;
1927 uint32_t mbox_cmd[MBOX_REG_COUNT];
1928 uint32_t mbox_sts[MBOX_REG_COUNT];
1929
1930 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1931 memset(&mbox_sts, 0, sizeof(mbox_sts));
1932
1933 mbox_cmd[0] = MBOX_CMD_SET_NVRAM;
1934 mbox_cmd[1] = LSDW(nvram_dma);
1935 mbox_cmd[2] = MSDW(nvram_dma);
1936 mbox_cmd[3] = offset;
1937 mbox_cmd[4] = size;
1938
1939 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
1940 &mbox_sts[0]);
1941 if (status != QLA_SUCCESS) {
1942 DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
1943 "status %04X\n", ha->host_no, __func__,
1944 mbox_sts[0]));
1945 }
1946 return status;
1947}
5232f801
HZ		 1948
1949int qla4xxx_restore_factory_defaults(struct scsi_qla_host *ha,
1950 uint32_t region, uint32_t field0,
1951 uint32_t field1)
1952{
1953 int status = QLA_SUCCESS;
1954 uint32_t mbox_cmd[MBOX_REG_COUNT];
1955 uint32_t mbox_sts[MBOX_REG_COUNT];
1956
1957 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1958 memset(&mbox_sts, 0, sizeof(mbox_sts));
1959
1960 mbox_cmd[0] = MBOX_CMD_RESTORE_FACTORY_DEFAULTS;
1961 mbox_cmd[3] = region;
1962 mbox_cmd[4] = field0;
1963 mbox_cmd[5] = field1;
1964
1965 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0],
1966 &mbox_sts[0]);
1967 if (status != QLA_SUCCESS) {
1968 DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
1969 "status %04X\n", ha->host_no, __func__,
1970 mbox_sts[0]));
1971 }
1972 return status;
1973}
cfb27874
MD		 1974
1975/**
1976 * qla4_8xxx_set_param - set driver version in firmware.
1977 * @ha: Pointer to host adapter structure.
1978 * @param: Parameter to set i.e driver version
1979 **/
1980int qla4_8xxx_set_param(struct scsi_qla_host *ha, int param)
1981{
1982 uint32_t mbox_cmd[MBOX_REG_COUNT];
1983 uint32_t mbox_sts[MBOX_REG_COUNT];
1984 uint32_t status;
1985
1986 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1987 memset(&mbox_sts, 0, sizeof(mbox_sts));
1988
1989 mbox_cmd[0] = MBOX_CMD_SET_PARAM;
1990 if (param == SET_DRVR_VERSION) {
1991 mbox_cmd[1] = SET_DRVR_VERSION;
1992 strncpy((char *)&mbox_cmd[2], QLA4XXX_DRIVER_VERSION,
1993 MAX_DRVR_VER_LEN);
1994 } else {
1995 ql4_printk(KERN_ERR, ha, "%s: invalid parameter 0x%x\n",
1996 __func__, param);
1997 status = QLA_ERROR;
1998 goto exit_set_param;
1999 }
2000
2001 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, mbox_cmd,
2002 mbox_sts);
2003 if (status == QLA_ERROR)
2004 ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
2005 __func__, mbox_sts[0]);
2006
2007exit_set_param:
2008 return status;
2009}
320a61de
NJ		 2010
2011/**
2012 * qla4_83xx_post_idc_ack - post IDC ACK
2013 * @ha: Pointer to host adapter structure.
2014 *
2015 * Posts IDC ACK for IDC Request Notification AEN.
2016 **/
2017int qla4_83xx_post_idc_ack(struct scsi_qla_host *ha)
2018{
2019 uint32_t mbox_cmd[MBOX_REG_COUNT];
2020 uint32_t mbox_sts[MBOX_REG_COUNT];
2021 int status;
2022
2023 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2024 memset(&mbox_sts, 0, sizeof(mbox_sts));
2025
2026 mbox_cmd[0] = MBOX_CMD_IDC_ACK;
2027 mbox_cmd[1] = ha->idc_info.request_desc;
2028 mbox_cmd[2] = ha->idc_info.info1;
2029 mbox_cmd[3] = ha->idc_info.info2;
2030 mbox_cmd[4] = ha->idc_info.info3;
2031
2032 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
2033 mbox_cmd, mbox_sts);
2034 if (status == QLA_ERROR)
2035 ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n", __func__,
2036 mbox_sts[0]);
2037 else
2038 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: IDC ACK posted\n",
2039 __func__));
2040
2041 return status;
2042}
Linux kernel - Deliverables
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