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[PATCH] sata_mv: remove local copy of queue indexes
[deliverable/linux.git] / drivers / scsi / sata_mv.c
CommitLineData
20f733e7
BR		 1/*
2 * sata_mv.c - Marvell SATA support
3 *
8b260248 4 * Copyright 2005: EMC Corporation, all rights reserved.
e2b1be56 5 * Copyright 2005 Red Hat, Inc. All rights reserved.
20f733e7
BR		 6 *
7 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/pci.h>
27#include <linux/init.h>
28#include <linux/blkdev.h>
29#include <linux/delay.h>
30#include <linux/interrupt.h>
31#include <linux/sched.h>
32#include <linux/dma-mapping.h>
a9524a76 33#include <linux/device.h>
20f733e7 34#include <scsi/scsi_host.h>
193515d5 35#include <scsi/scsi_cmnd.h>
20f733e7
BR		 36#include <linux/libata.h>
37#include <asm/io.h>
38
39#define DRV_NAME "sata_mv"
e4e7b892 40#define DRV_VERSION "0.6"
20f733e7
BR		 41
42enum {
43 /* BAR's are enumerated in terms of pci_resource_start() terms */
44 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
45 MV_IO_BAR = 2, /* offset 0x18: IO space */
46 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
47
48 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
49 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
50
51 MV_PCI_REG_BASE = 0,
52 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
615ab953
ML		 53 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
54 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
55 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
56 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
57 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
58
20f733e7 59 MV_SATAHC0_REG_BASE = 0x20000,
522479fb 60 MV_FLASH_CTL = 0x1046c,
bca1c4eb
JG		 61 MV_GPIO_PORT_CTL = 0x104f0,
62 MV_RESET_CFG = 0x180d8,
20f733e7
BR		 63
64 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
65 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
66 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
67 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
68
31961943 69 MV_USE_Q_DEPTH = ATA_DEF_QUEUE,
20f733e7 70
31961943
BR		 71 MV_MAX_Q_DEPTH = 32,
72 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
73
74 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
75 * CRPB needs alignment on a 256B boundary. Size == 256B
76 * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB
77 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
78 */
79 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
80 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
81 MV_MAX_SG_CT = 176,
82 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
83 MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ),
84
20f733e7
BR		 85 MV_PORTS_PER_HC = 4,
86 /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
87 MV_PORT_HC_SHIFT = 2,
31961943 88 /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */
20f733e7
BR		 89 MV_PORT_MASK = 3,
90
91 /* Host Flags */
92 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
93 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
31961943 94 MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
50630195
JG		 95 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
96 ATA_FLAG_NO_ATAPI),
47c2b677 97 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
20f733e7 98
31961943
BR		 99 CRQB_FLAG_READ = (1 << 0),
100 CRQB_TAG_SHIFT = 1,
101 CRQB_CMD_ADDR_SHIFT = 8,
102 CRQB_CMD_CS = (0x2 << 11),
103 CRQB_CMD_LAST = (1 << 15),
104
105 CRPB_FLAG_STATUS_SHIFT = 8,
106
107 EPRD_FLAG_END_OF_TBL = (1 << 31),
108
20f733e7
BR		 109 /* PCI interface registers */
110
31961943
BR		 111 PCI_COMMAND_OFS = 0xc00,
112
20f733e7
BR		 113 PCI_MAIN_CMD_STS_OFS = 0xd30,
114 STOP_PCI_MASTER = (1 << 2),
115 PCI_MASTER_EMPTY = (1 << 3),
116 GLOB_SFT_RST = (1 << 4),
117
522479fb
JG		 118 MV_PCI_MODE = 0xd00,
119 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
120 MV_PCI_DISC_TIMER = 0xd04,
121 MV_PCI_MSI_TRIGGER = 0xc38,
122 MV_PCI_SERR_MASK = 0xc28,
123 MV_PCI_XBAR_TMOUT = 0x1d04,
124 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
125 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
126 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
127 MV_PCI_ERR_COMMAND = 0x1d50,
128
129 PCI_IRQ_CAUSE_OFS = 0x1d58,
130 PCI_IRQ_MASK_OFS = 0x1d5c,
20f733e7
BR		 131 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
132
133 HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
134 HC_MAIN_IRQ_MASK_OFS = 0x1d64,
135 PORT0_ERR = (1 << 0), /* shift by port # */
136 PORT0_DONE = (1 << 1), /* shift by port # */
137 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
138 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
139 PCI_ERR = (1 << 18),
140 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
141 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
142 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
143 GPIO_INT = (1 << 22),
144 SELF_INT = (1 << 23),
145 TWSI_INT = (1 << 24),
146 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
8b260248 147 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
20f733e7
BR		 148 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
149 HC_MAIN_RSVD),
150
151 /* SATAHC registers */
152 HC_CFG_OFS = 0,
153
154 HC_IRQ_CAUSE_OFS = 0x14,
31961943 155 CRPB_DMA_DONE = (1 << 0), /* shift by port # */
20f733e7
BR		 156 HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */
157 DEV_IRQ = (1 << 8), /* shift by port # */
158
159 /* Shadow block registers */
31961943
BR		 160 SHD_BLK_OFS = 0x100,
161 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
20f733e7
BR		 162
163 /* SATA registers */
164 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
165 SATA_ACTIVE_OFS = 0x350,
47c2b677 166 PHY_MODE3 = 0x310,
bca1c4eb
JG		 167 PHY_MODE4 = 0x314,
168 PHY_MODE2 = 0x330,
c9d39130
JG		 169 MV5_PHY_MODE = 0x74,
170 MV5_LT_MODE = 0x30,
171 MV5_PHY_CTL = 0x0C,
bca1c4eb
JG		 172 SATA_INTERFACE_CTL = 0x050,
173
174 MV_M2_PREAMP_MASK = 0x7e0,
20f733e7
BR		 175
176 /* Port registers */
177 EDMA_CFG_OFS = 0,
31961943
BR		 178 EDMA_CFG_Q_DEPTH = 0, /* queueing disabled */
179 EDMA_CFG_NCQ = (1 << 5),
180 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
181 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
182 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
20f733e7
BR		 183
184 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
185 EDMA_ERR_IRQ_MASK_OFS = 0xc,
186 EDMA_ERR_D_PAR = (1 << 0),
187 EDMA_ERR_PRD_PAR = (1 << 1),
188 EDMA_ERR_DEV = (1 << 2),
189 EDMA_ERR_DEV_DCON = (1 << 3),
190 EDMA_ERR_DEV_CON = (1 << 4),
191 EDMA_ERR_SERR = (1 << 5),
192 EDMA_ERR_SELF_DIS = (1 << 7),
193 EDMA_ERR_BIST_ASYNC = (1 << 8),
194 EDMA_ERR_CRBQ_PAR = (1 << 9),
195 EDMA_ERR_CRPB_PAR = (1 << 10),
196 EDMA_ERR_INTRL_PAR = (1 << 11),
197 EDMA_ERR_IORDY = (1 << 12),
198 EDMA_ERR_LNK_CTRL_RX = (0xf << 13),
199 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15),
200 EDMA_ERR_LNK_DATA_RX = (0xf << 17),
201 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21),
202 EDMA_ERR_LNK_DATA_TX = (0x1f << 26),
203 EDMA_ERR_TRANS_PROTO = (1 << 31),
8b260248 204 EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
20f733e7
BR		 205 EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR |
206 EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR |
8b260248 207 EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 |
20f733e7 208 EDMA_ERR_LNK_DATA_RX |
8b260248 209 EDMA_ERR_LNK_DATA_TX |
20f733e7
BR		 210 EDMA_ERR_TRANS_PROTO),
211
31961943
BR		 212 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
213 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
31961943
BR		 214
215 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
216 EDMA_REQ_Q_PTR_SHIFT = 5,
217
218 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
219 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
220 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
31961943
BR		 221 EDMA_RSP_Q_PTR_SHIFT = 3,
222
20f733e7
BR		 223 EDMA_CMD_OFS = 0x28,
224 EDMA_EN = (1 << 0),
225 EDMA_DS = (1 << 1),
226 ATA_RST = (1 << 2),
227
c9d39130 228 EDMA_IORDY_TMOUT = 0x34,
bca1c4eb 229 EDMA_ARB_CFG = 0x38,
bca1c4eb 230
31961943
BR		 231 /* Host private flags (hp_flags) */
232 MV_HP_FLAG_MSI = (1 << 0),
47c2b677
JG		 233 MV_HP_ERRATA_50XXB0 = (1 << 1),
234 MV_HP_ERRATA_50XXB2 = (1 << 2),
235 MV_HP_ERRATA_60X1B2 = (1 << 3),
236 MV_HP_ERRATA_60X1C0 = (1 << 4),
e4e7b892
JG		 237 MV_HP_ERRATA_XX42A0 = (1 << 5),
238 MV_HP_50XX = (1 << 6),
239 MV_HP_GEN_IIE = (1 << 7),
20f733e7 240
31961943
BR		 241 /* Port private flags (pp_flags) */
242 MV_PP_FLAG_EDMA_EN = (1 << 0),
243 MV_PP_FLAG_EDMA_DS_ACT = (1 << 1),
20f733e7
BR		 244};
245
c9d39130 246#define IS_50XX(hpriv) ((hpriv)->hp_flags & MV_HP_50XX)
bca1c4eb 247#define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0)
e4e7b892
JG		 248#define IS_GEN_I(hpriv) IS_50XX(hpriv)
249#define IS_GEN_II(hpriv) IS_60XX(hpriv)
250#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
bca1c4eb 251
095fec88
JG		 252enum {
253 /* Our DMA boundary is determined by an ePRD being unable to handle
254 * anything larger than 64KB
255 */
256 MV_DMA_BOUNDARY = 0xffffU,
257
258 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
259
260 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
261};
262
522479fb
JG		 263enum chip_type {
264 chip_504x,
265 chip_508x,
266 chip_5080,
267 chip_604x,
268 chip_608x,
e4e7b892
JG		 269 chip_6042,
270 chip_7042,
522479fb
JG		 271};
272
31961943
BR		 273/* Command ReQuest Block: 32B */
274struct mv_crqb {
275 u32 sg_addr;
276 u32 sg_addr_hi;
277 u16 ctrl_flags;
278 u16 ata_cmd[11];
279};
20f733e7 280
e4e7b892
JG		 281struct mv_crqb_iie {
282 u32 addr;
283 u32 addr_hi;
284 u32 flags;
285 u32 len;
286 u32 ata_cmd[4];
287};
288
31961943
BR		 289/* Command ResPonse Block: 8B */
290struct mv_crpb {
291 u16 id;
292 u16 flags;
293 u32 tmstmp;
20f733e7
BR		 294};
295
31961943
BR		 296/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
297struct mv_sg {
298 u32 addr;
299 u32 flags_size;
300 u32 addr_hi;
301 u32 reserved;
302};
20f733e7 303
31961943
BR		 304struct mv_port_priv {
305 struct mv_crqb *crqb;
306 dma_addr_t crqb_dma;
307 struct mv_crpb *crpb;
308 dma_addr_t crpb_dma;
309 struct mv_sg *sg_tbl;
310 dma_addr_t sg_tbl_dma;
31961943
BR		 311 u32 pp_flags;
312};
313
bca1c4eb
JG		 314struct mv_port_signal {
315 u32 amps;
316 u32 pre;
317};
318
47c2b677
JG		 319struct mv_host_priv;
320struct mv_hw_ops {
2a47ce06
JG		 321 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
322 unsigned int port);
47c2b677
JG		 323 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
324 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
325 void __iomem *mmio);
c9d39130
JG		 326 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
327 unsigned int n_hc);
522479fb
JG		 328 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
329 void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio);
47c2b677
JG		 330};
331
31961943
BR		 332struct mv_host_priv {
333 u32 hp_flags;
bca1c4eb 334 struct mv_port_signal signal[8];
47c2b677 335 const struct mv_hw_ops *ops;
20f733e7
BR		 336};
337
338static void mv_irq_clear(struct ata_port *ap);
339static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
340static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
c9d39130
JG		 341static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
342static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
20f733e7 343static void mv_phy_reset(struct ata_port *ap);
22374677 344static void __mv_phy_reset(struct ata_port *ap, int can_sleep);
31961943
BR		 345static void mv_host_stop(struct ata_host_set *host_set);
346static int mv_port_start(struct ata_port *ap);
347static void mv_port_stop(struct ata_port *ap);
348static void mv_qc_prep(struct ata_queued_cmd *qc);
e4e7b892 349static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
9a3d9eb0 350static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
20f733e7
BR		 351static irqreturn_t mv_interrupt(int irq, void *dev_instance,
352 struct pt_regs *regs);
31961943 353static void mv_eng_timeout(struct ata_port *ap);
20f733e7
BR		 354static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
355
2a47ce06
JG		 356static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
357 unsigned int port);
47c2b677
JG		 358static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
359static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
360 void __iomem *mmio);
c9d39130
JG		 361static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
362 unsigned int n_hc);
522479fb
JG		 363static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
364static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio);
47c2b677 365
2a47ce06
JG		 366static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
367 unsigned int port);
47c2b677
JG		 368static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
369static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
370 void __iomem *mmio);
c9d39130
JG		 371static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
372 unsigned int n_hc);
522479fb
JG		 373static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
374static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio);
c9d39130
JG		 375static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
376 unsigned int port_no);
377static void mv_stop_and_reset(struct ata_port *ap);
47c2b677 378
193515d5 379static struct scsi_host_template mv_sht = {
20f733e7
BR		 380 .module = THIS_MODULE,
381 .name = DRV_NAME,
382 .ioctl = ata_scsi_ioctl,
383 .queuecommand = ata_scsi_queuecmd,
1b723734 384 .can_queue = MV_USE_Q_DEPTH,
20f733e7 385 .this_id = ATA_SHT_THIS_ID,
22374677 386 .sg_tablesize = MV_MAX_SG_CT / 2,
20f733e7
BR		 387 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
388 .emulated = ATA_SHT_EMULATED,
31961943 389 .use_clustering = ATA_SHT_USE_CLUSTERING,
20f733e7
BR		 390 .proc_name = DRV_NAME,
391 .dma_boundary = MV_DMA_BOUNDARY,
392 .slave_configure = ata_scsi_slave_config,
393 .bios_param = ata_std_bios_param,
20f733e7
BR		 394};
395
c9d39130
JG		 396static const struct ata_port_operations mv5_ops = {
397 .port_disable = ata_port_disable,
398
399 .tf_load = ata_tf_load,
400 .tf_read = ata_tf_read,
401 .check_status = ata_check_status,
402 .exec_command = ata_exec_command,
403 .dev_select = ata_std_dev_select,
404
405 .phy_reset = mv_phy_reset,
406
407 .qc_prep = mv_qc_prep,
408 .qc_issue = mv_qc_issue,
409
410 .eng_timeout = mv_eng_timeout,
411
412 .irq_handler = mv_interrupt,
413 .irq_clear = mv_irq_clear,
414
415 .scr_read = mv5_scr_read,
416 .scr_write = mv5_scr_write,
417
418 .port_start = mv_port_start,
419 .port_stop = mv_port_stop,
420 .host_stop = mv_host_stop,
421};
422
423static const struct ata_port_operations mv6_ops = {
20f733e7
BR		 424 .port_disable = ata_port_disable,
425
426 .tf_load = ata_tf_load,
427 .tf_read = ata_tf_read,
428 .check_status = ata_check_status,
429 .exec_command = ata_exec_command,
430 .dev_select = ata_std_dev_select,
431
432 .phy_reset = mv_phy_reset,
433
31961943
BR		 434 .qc_prep = mv_qc_prep,
435 .qc_issue = mv_qc_issue,
20f733e7 436
31961943 437 .eng_timeout = mv_eng_timeout,
20f733e7
BR		 438
439 .irq_handler = mv_interrupt,
440 .irq_clear = mv_irq_clear,
441
442 .scr_read = mv_scr_read,
443 .scr_write = mv_scr_write,
444
31961943
BR		 445 .port_start = mv_port_start,
446 .port_stop = mv_port_stop,
447 .host_stop = mv_host_stop,
20f733e7
BR		 448};
449
e4e7b892
JG		 450static const struct ata_port_operations mv_iie_ops = {
451 .port_disable = ata_port_disable,
452
453 .tf_load = ata_tf_load,
454 .tf_read = ata_tf_read,
455 .check_status = ata_check_status,
456 .exec_command = ata_exec_command,
457 .dev_select = ata_std_dev_select,
458
459 .phy_reset = mv_phy_reset,
460
461 .qc_prep = mv_qc_prep_iie,
462 .qc_issue = mv_qc_issue,
463
464 .eng_timeout = mv_eng_timeout,
465
466 .irq_handler = mv_interrupt,
467 .irq_clear = mv_irq_clear,
468
469 .scr_read = mv_scr_read,
470 .scr_write = mv_scr_write,
471
472 .port_start = mv_port_start,
473 .port_stop = mv_port_stop,
474 .host_stop = mv_host_stop,
475};
476
98ac62de 477static const struct ata_port_info mv_port_info[] = {
20f733e7
BR		 478 { /* chip_504x */
479 .sht = &mv_sht,
31961943
BR		 480 .host_flags = MV_COMMON_FLAGS,
481 .pio_mask = 0x1f, /* pio0-4 */
c9d39130
JG		 482 .udma_mask = 0x7f, /* udma0-6 */
483 .port_ops = &mv5_ops,
20f733e7
BR		 484 },
485 { /* chip_508x */
486 .sht = &mv_sht,
31961943
BR		 487 .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
488 .pio_mask = 0x1f, /* pio0-4 */
c9d39130
JG		 489 .udma_mask = 0x7f, /* udma0-6 */
490 .port_ops = &mv5_ops,
20f733e7 491 },
47c2b677
JG		 492 { /* chip_5080 */
493 .sht = &mv_sht,
494 .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
495 .pio_mask = 0x1f, /* pio0-4 */
c9d39130
JG		 496 .udma_mask = 0x7f, /* udma0-6 */
497 .port_ops = &mv5_ops,
47c2b677 498 },
20f733e7
BR		 499 { /* chip_604x */
500 .sht = &mv_sht,
31961943
BR		 501 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
502 .pio_mask = 0x1f, /* pio0-4 */
503 .udma_mask = 0x7f, /* udma0-6 */
c9d39130 504 .port_ops = &mv6_ops,
20f733e7
BR		 505 },
506 { /* chip_608x */
507 .sht = &mv_sht,
8b260248 508 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
31961943
BR		 509 MV_FLAG_DUAL_HC),
510 .pio_mask = 0x1f, /* pio0-4 */
511 .udma_mask = 0x7f, /* udma0-6 */
c9d39130 512 .port_ops = &mv6_ops,
20f733e7 513 },
e4e7b892
JG		 514 { /* chip_6042 */
515 .sht = &mv_sht,
516 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
517 .pio_mask = 0x1f, /* pio0-4 */
518 .udma_mask = 0x7f, /* udma0-6 */
519 .port_ops = &mv_iie_ops,
520 },
521 { /* chip_7042 */
522 .sht = &mv_sht,
523 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
524 MV_FLAG_DUAL_HC),
525 .pio_mask = 0x1f, /* pio0-4 */
526 .udma_mask = 0x7f, /* udma0-6 */
527 .port_ops = &mv_iie_ops,
528 },
20f733e7
BR		 529};
530
3b7d697d 531static const struct pci_device_id mv_pci_tbl[] = {
20f733e7
BR		 532 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5040), 0, 0, chip_504x},
533 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5041), 0, 0, chip_504x},
47c2b677 534 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5080), 0, 0, chip_5080},
20f733e7
BR		 535 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5081), 0, 0, chip_508x},
536
537 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6040), 0, 0, chip_604x},
538 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6041), 0, 0, chip_604x},
e4e7b892 539 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6042), 0, 0, chip_6042},
20f733e7
BR		 540 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6080), 0, 0, chip_608x},
541 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6081), 0, 0, chip_608x},
29179539
JG		 542
543 {PCI_DEVICE(PCI_VENDOR_ID_ADAPTEC2, 0x0241), 0, 0, chip_604x},
20f733e7
BR		 544 {} /* terminate list */
545};
546
547static struct pci_driver mv_pci_driver = {
548 .name = DRV_NAME,
549 .id_table = mv_pci_tbl,
550 .probe = mv_init_one,
551 .remove = ata_pci_remove_one,
552};
553
47c2b677
JG		 554static const struct mv_hw_ops mv5xxx_ops = {
555 .phy_errata = mv5_phy_errata,
556 .enable_leds = mv5_enable_leds,
557 .read_preamp = mv5_read_preamp,
558 .reset_hc = mv5_reset_hc,
522479fb
JG		 559 .reset_flash = mv5_reset_flash,
560 .reset_bus = mv5_reset_bus,
47c2b677
JG		 561};
562
563static const struct mv_hw_ops mv6xxx_ops = {
564 .phy_errata = mv6_phy_errata,
565 .enable_leds = mv6_enable_leds,
566 .read_preamp = mv6_read_preamp,
567 .reset_hc = mv6_reset_hc,
522479fb
JG		 568 .reset_flash = mv6_reset_flash,
569 .reset_bus = mv_reset_pci_bus,
47c2b677
JG		 570};
571
ddef9bb3
JG		 572/*
573 * module options
574 */
575static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
576
577
20f733e7
BR		 578/*
579 * Functions
580 */
581
582static inline void writelfl(unsigned long data, void __iomem *addr)
583{
584 writel(data, addr);
585 (void) readl(addr); /* flush to avoid PCI posted write */
586}
587
20f733e7
BR		 588static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
589{
590 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
591}
592
c9d39130
JG		 593static inline unsigned int mv_hc_from_port(unsigned int port)
594{
595 return port >> MV_PORT_HC_SHIFT;
596}
597
598static inline unsigned int mv_hardport_from_port(unsigned int port)
599{
600 return port & MV_PORT_MASK;
601}
602
603static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
604 unsigned int port)
605{
606 return mv_hc_base(base, mv_hc_from_port(port));
607}
608
20f733e7
BR		 609static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
610{
c9d39130 611 return mv_hc_base_from_port(base, port) +
8b260248 612 MV_SATAHC_ARBTR_REG_SZ +
c9d39130 613 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
20f733e7
BR		 614}
615
616static inline void __iomem *mv_ap_base(struct ata_port *ap)
617{
618 return mv_port_base(ap->host_set->mmio_base, ap->port_no);
619}
620
bca1c4eb 621static inline int mv_get_hc_count(unsigned long host_flags)
31961943 622{
bca1c4eb 623 return ((host_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
31961943
BR		 624}
625
626static void mv_irq_clear(struct ata_port *ap)
20f733e7 627{
20f733e7
BR		 628}
629
05b308e1
BR		 630/**
631 * mv_start_dma - Enable eDMA engine
632 * @base: port base address
633 * @pp: port private data
634 *
beec7dbc
TH		 635 * Verify the local cache of the eDMA state is accurate with a
636 * WARN_ON.
05b308e1
BR		 637 *
638 * LOCKING:
639 * Inherited from caller.
640 */
afb0edd9 641static void mv_start_dma(void __iomem *base, struct mv_port_priv *pp)
20f733e7 642{
afb0edd9
BR		 643 if (!(MV_PP_FLAG_EDMA_EN & pp->pp_flags)) {
644 writelfl(EDMA_EN, base + EDMA_CMD_OFS);
645 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
646 }
beec7dbc 647 WARN_ON(!(EDMA_EN & readl(base + EDMA_CMD_OFS)));
20f733e7
BR		 648}
649
05b308e1
BR		 650/**
651 * mv_stop_dma - Disable eDMA engine
652 * @ap: ATA channel to manipulate
653 *
beec7dbc
TH		 654 * Verify the local cache of the eDMA state is accurate with a
655 * WARN_ON.
05b308e1
BR		 656 *
657 * LOCKING:
658 * Inherited from caller.
659 */
31961943 660static void mv_stop_dma(struct ata_port *ap)
20f733e7 661{
31961943
BR		 662 void __iomem *port_mmio = mv_ap_base(ap);
663 struct mv_port_priv *pp = ap->private_data;
31961943
BR		 664 u32 reg;
665 int i;
666
afb0edd9
BR		 667 if (MV_PP_FLAG_EDMA_EN & pp->pp_flags) {
668 /* Disable EDMA if active. The disable bit auto clears.
31961943 669 */
31961943
BR		 670 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
671 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
afb0edd9 672 } else {
beec7dbc 673 WARN_ON(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS));
afb0edd9 674 }
8b260248 675
31961943
BR		 676 /* now properly wait for the eDMA to stop */
677 for (i = 1000; i > 0; i--) {
678 reg = readl(port_mmio + EDMA_CMD_OFS);
679 if (!(EDMA_EN & reg)) {
680 break;
681 }
682 udelay(100);
683 }
684
31961943
BR		 685 if (EDMA_EN & reg) {
686 printk(KERN_ERR "ata%u: Unable to stop eDMA\n", ap->id);
afb0edd9 687 /* FIXME: Consider doing a reset here to recover */
31961943 688 }
20f733e7
BR		 689}
690
8a70f8dc 691#ifdef ATA_DEBUG
31961943 692static void mv_dump_mem(void __iomem *start, unsigned bytes)
20f733e7 693{
31961943
BR		 694 int b, w;
695 for (b = 0; b < bytes; ) {
696 DPRINTK("%p: ", start + b);
697 for (w = 0; b < bytes && w < 4; w++) {
698 printk("%08x ",readl(start + b));
699 b += sizeof(u32);
700 }
701 printk("\n");
702 }
31961943 703}
8a70f8dc
JG		 704#endif
705
31961943
BR		 706static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
707{
708#ifdef ATA_DEBUG
709 int b, w;
710 u32 dw;
711 for (b = 0; b < bytes; ) {
712 DPRINTK("%02x: ", b);
713 for (w = 0; b < bytes && w < 4; w++) {
714 (void) pci_read_config_dword(pdev,b,&dw);
715 printk("%08x ",dw);
716 b += sizeof(u32);
717 }
718 printk("\n");
719 }
720#endif
721}
722static void mv_dump_all_regs(void __iomem *mmio_base, int port,
723 struct pci_dev *pdev)
724{
725#ifdef ATA_DEBUG
8b260248 726 void __iomem *hc_base = mv_hc_base(mmio_base,
31961943
BR		 727 port >> MV_PORT_HC_SHIFT);
728 void __iomem *port_base;
729 int start_port, num_ports, p, start_hc, num_hcs, hc;
730
731 if (0 > port) {
732 start_hc = start_port = 0;
733 num_ports = 8; /* shld be benign for 4 port devs */
734 num_hcs = 2;
735 } else {
736 start_hc = port >> MV_PORT_HC_SHIFT;
737 start_port = port;
738 num_ports = num_hcs = 1;
739 }
8b260248 740 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
31961943
BR		 741 num_ports > 1 ? num_ports - 1 : start_port);
742
743 if (NULL != pdev) {
744 DPRINTK("PCI config space regs:\n");
745 mv_dump_pci_cfg(pdev, 0x68);
746 }
747 DPRINTK("PCI regs:\n");
748 mv_dump_mem(mmio_base+0xc00, 0x3c);
749 mv_dump_mem(mmio_base+0xd00, 0x34);
750 mv_dump_mem(mmio_base+0xf00, 0x4);
751 mv_dump_mem(mmio_base+0x1d00, 0x6c);
752 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
d220c37e 753 hc_base = mv_hc_base(mmio_base, hc);
31961943
BR		 754 DPRINTK("HC regs (HC %i):\n", hc);
755 mv_dump_mem(hc_base, 0x1c);
756 }
757 for (p = start_port; p < start_port + num_ports; p++) {
758 port_base = mv_port_base(mmio_base, p);
759 DPRINTK("EDMA regs (port %i):\n",p);
760 mv_dump_mem(port_base, 0x54);
761 DPRINTK("SATA regs (port %i):\n",p);
762 mv_dump_mem(port_base+0x300, 0x60);
763 }
764#endif
20f733e7
BR		 765}
766
767static unsigned int mv_scr_offset(unsigned int sc_reg_in)
768{
769 unsigned int ofs;
770
771 switch (sc_reg_in) {
772 case SCR_STATUS:
773 case SCR_CONTROL:
774 case SCR_ERROR:
775 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
776 break;
777 case SCR_ACTIVE:
778 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
779 break;
780 default:
781 ofs = 0xffffffffU;
782 break;
783 }
784 return ofs;
785}
786
787static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
788{
789 unsigned int ofs = mv_scr_offset(sc_reg_in);
790
791 if (0xffffffffU != ofs) {
792 return readl(mv_ap_base(ap) + ofs);
793 } else {
794 return (u32) ofs;
795 }
796}
797
798static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
799{
800 unsigned int ofs = mv_scr_offset(sc_reg_in);
801
802 if (0xffffffffU != ofs) {
803 writelfl(val, mv_ap_base(ap) + ofs);
804 }
805}
806
05b308e1
BR		 807/**
808 * mv_host_stop - Host specific cleanup/stop routine.
809 * @host_set: host data structure
810 *
811 * Disable ints, cleanup host memory, call general purpose
812 * host_stop.
813 *
814 * LOCKING:
815 * Inherited from caller.
816 */
31961943 817static void mv_host_stop(struct ata_host_set *host_set)
20f733e7 818{
31961943
BR		 819 struct mv_host_priv *hpriv = host_set->private_data;
820 struct pci_dev *pdev = to_pci_dev(host_set->dev);
821
822 if (hpriv->hp_flags & MV_HP_FLAG_MSI) {
823 pci_disable_msi(pdev);
824 } else {
825 pci_intx(pdev, 0);
826 }
827 kfree(hpriv);
828 ata_host_stop(host_set);
829}
830
6037d6bb
JG		 831static inline void mv_priv_free(struct mv_port_priv *pp, struct device *dev)
832{
833 dma_free_coherent(dev, MV_PORT_PRIV_DMA_SZ, pp->crpb, pp->crpb_dma);
834}
835
e4e7b892
JG		 836static void mv_edma_cfg(struct mv_host_priv *hpriv, void __iomem *port_mmio)
837{
838 u32 cfg = readl(port_mmio + EDMA_CFG_OFS);
839
840 /* set up non-NCQ EDMA configuration */
841 cfg &= ~0x1f; /* clear queue depth */
842 cfg &= ~EDMA_CFG_NCQ; /* clear NCQ mode */
843 cfg &= ~(1 << 9); /* disable equeue */
844
845 if (IS_GEN_I(hpriv))
846 cfg |= (1 << 8); /* enab config burst size mask */
847
848 else if (IS_GEN_II(hpriv))
849 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
850
851 else if (IS_GEN_IIE(hpriv)) {
852 cfg |= (1 << 23); /* dis RX PM port mask */
853 cfg &= ~(1 << 16); /* dis FIS-based switching (for now) */
854 cfg &= ~(1 << 19); /* dis 128-entry queue (for now?) */
855 cfg |= (1 << 18); /* enab early completion */
856 cfg |= (1 << 17); /* enab host q cache */
857 cfg |= (1 << 22); /* enab cutthrough */
858 }
859
860 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
861}
862
05b308e1
BR		 863/**
864 * mv_port_start - Port specific init/start routine.
865 * @ap: ATA channel to manipulate
866 *
867 * Allocate and point to DMA memory, init port private memory,
868 * zero indices.
869 *
870 * LOCKING:
871 * Inherited from caller.
872 */
31961943
BR		 873static int mv_port_start(struct ata_port *ap)
874{
875 struct device *dev = ap->host_set->dev;
e4e7b892 876 struct mv_host_priv *hpriv = ap->host_set->private_data;
31961943
BR		 877 struct mv_port_priv *pp;
878 void __iomem *port_mmio = mv_ap_base(ap);
879 void *mem;
880 dma_addr_t mem_dma;
6037d6bb 881 int rc = -ENOMEM;
31961943
BR		 882
883 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
6037d6bb
JG		 884 if (!pp)
885 goto err_out;
31961943
BR		 886 memset(pp, 0, sizeof(*pp));
887
8b260248 888 mem = dma_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma,
31961943 889 GFP_KERNEL);
6037d6bb
JG		 890 if (!mem)
891 goto err_out_pp;
31961943
BR		 892 memset(mem, 0, MV_PORT_PRIV_DMA_SZ);
893
6037d6bb
JG		 894 rc = ata_pad_alloc(ap, dev);
895 if (rc)
896 goto err_out_priv;
897
8b260248 898 /* First item in chunk of DMA memory:
31961943
BR		 899 * 32-slot command request table (CRQB), 32 bytes each in size
900 */
901 pp->crqb = mem;
902 pp->crqb_dma = mem_dma;
903 mem += MV_CRQB_Q_SZ;
904 mem_dma += MV_CRQB_Q_SZ;
905
8b260248 906 /* Second item:
31961943
BR		 907 * 32-slot command response table (CRPB), 8 bytes each in size
908 */
909 pp->crpb = mem;
910 pp->crpb_dma = mem_dma;
911 mem += MV_CRPB_Q_SZ;
912 mem_dma += MV_CRPB_Q_SZ;
913
914 /* Third item:
915 * Table of scatter-gather descriptors (ePRD), 16 bytes each
916 */
917 pp->sg_tbl = mem;
918 pp->sg_tbl_dma = mem_dma;
919
e4e7b892 920 mv_edma_cfg(hpriv, port_mmio);
31961943
BR		 921
922 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
8b260248 923 writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK,
31961943
BR		 924 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
925
e4e7b892
JG		 926 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
927 writelfl(pp->crqb_dma & 0xffffffff,
928 port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
929 else
930 writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
31961943
BR		 931
932 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
e4e7b892
JG		 933
934 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
935 writelfl(pp->crpb_dma & 0xffffffff,
936 port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
937 else
938 writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
939
8b260248 940 writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK,
31961943
BR		 941 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
942
31961943
BR		 943 /* Don't turn on EDMA here...do it before DMA commands only. Else
944 * we'll be unable to send non-data, PIO, etc due to restricted access
945 * to shadow regs.
946 */
947 ap->private_data = pp;
948 return 0;
6037d6bb
JG		 949
950err_out_priv:
951 mv_priv_free(pp, dev);
952err_out_pp:
953 kfree(pp);
954err_out:
955 return rc;
31961943
BR		 956}
957
05b308e1
BR		 958/**
959 * mv_port_stop - Port specific cleanup/stop routine.
960 * @ap: ATA channel to manipulate
961 *
962 * Stop DMA, cleanup port memory.
963 *
964 * LOCKING:
965 * This routine uses the host_set lock to protect the DMA stop.
966 */
31961943
BR		 967static void mv_port_stop(struct ata_port *ap)
968{
969 struct device *dev = ap->host_set->dev;
970 struct mv_port_priv *pp = ap->private_data;
afb0edd9 971 unsigned long flags;
31961943 972
afb0edd9 973 spin_lock_irqsave(&ap->host_set->lock, flags);
31961943 974 mv_stop_dma(ap);
afb0edd9 975 spin_unlock_irqrestore(&ap->host_set->lock, flags);
31961943
BR		 976
977 ap->private_data = NULL;
6037d6bb
JG		 978 ata_pad_free(ap, dev);
979 mv_priv_free(pp, dev);
31961943
BR		 980 kfree(pp);
981}
982
05b308e1
BR		 983/**
984 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
985 * @qc: queued command whose SG list to source from
986 *
987 * Populate the SG list and mark the last entry.
988 *
989 * LOCKING:
990 * Inherited from caller.
991 */
31961943
BR		 992static void mv_fill_sg(struct ata_queued_cmd *qc)
993{
994 struct mv_port_priv *pp = qc->ap->private_data;
972c26bd
JG		 995 unsigned int i = 0;
996 struct scatterlist *sg;
31961943 997
972c26bd 998 ata_for_each_sg(sg, qc) {
31961943 999 dma_addr_t addr;
22374677 1000 u32 sg_len, len, offset;
31961943 1001
972c26bd
JG		 1002 addr = sg_dma_address(sg);
1003 sg_len = sg_dma_len(sg);
31961943 1004
22374677
JG		 1005 while (sg_len) {
1006 offset = addr & MV_DMA_BOUNDARY;
1007 len = sg_len;
1008 if ((offset + sg_len) > 0x10000)
1009 len = 0x10000 - offset;
972c26bd 1010
22374677
JG		 1011 pp->sg_tbl[i].addr = cpu_to_le32(addr & 0xffffffff);
1012 pp->sg_tbl[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
63af2a5c 1013 pp->sg_tbl[i].flags_size = cpu_to_le32(len & 0xffff);
22374677
JG		 1014
1015 sg_len -= len;
1016 addr += len;
1017
1018 if (!sg_len && ata_sg_is_last(sg, qc))
1019 pp->sg_tbl[i].flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
1020
1021 i++;
1022 }
31961943
BR		 1023 }
1024}
1025
a6432436 1026static inline unsigned mv_inc_q_index(unsigned index)
31961943 1027{
a6432436 1028 return (index + 1) & MV_MAX_Q_DEPTH_MASK;
31961943
BR		 1029}
1030
1031static inline void mv_crqb_pack_cmd(u16 *cmdw, u8 data, u8 addr, unsigned last)
1032{
1033 *cmdw = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1034 (last ? CRQB_CMD_LAST : 0);
1035}
1036
05b308e1
BR		 1037/**
1038 * mv_qc_prep - Host specific command preparation.
1039 * @qc: queued command to prepare
1040 *
1041 * This routine simply redirects to the general purpose routine
1042 * if command is not DMA. Else, it handles prep of the CRQB
1043 * (command request block), does some sanity checking, and calls
1044 * the SG load routine.
1045 *
1046 * LOCKING:
1047 * Inherited from caller.
1048 */
31961943
BR		 1049static void mv_qc_prep(struct ata_queued_cmd *qc)
1050{
1051 struct ata_port *ap = qc->ap;
1052 struct mv_port_priv *pp = ap->private_data;
1053 u16 *cw;
1054 struct ata_taskfile *tf;
1055 u16 flags = 0;
a6432436 1056 unsigned in_index;
31961943 1057
e4e7b892 1058 if (ATA_PROT_DMA != qc->tf.protocol)
31961943 1059 return;
20f733e7 1060
31961943
BR		 1061 /* Fill in command request block
1062 */
e4e7b892 1063 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
31961943 1064 flags |= CRQB_FLAG_READ;
beec7dbc 1065 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
31961943
BR		 1066 flags |= qc->tag << CRQB_TAG_SHIFT;
1067
a6432436
ML		 1068 /* get current queue index from hardware */
1069 in_index = (readl(mv_ap_base(ap) + EDMA_REQ_Q_IN_PTR_OFS)
1070 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1071
1072 pp->crqb[in_index].sg_addr =
31961943 1073 cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
a6432436 1074 pp->crqb[in_index].sg_addr_hi =
31961943 1075 cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
a6432436 1076 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
31961943 1077
a6432436 1078 cw = &pp->crqb[in_index].ata_cmd[0];
31961943
BR		 1079 tf = &qc->tf;
1080
1081 /* Sadly, the CRQB cannot accomodate all registers--there are
1082 * only 11 bytes...so we must pick and choose required
1083 * registers based on the command. So, we drop feature and
1084 * hob_feature for [RW] DMA commands, but they are needed for
1085 * NCQ. NCQ will drop hob_nsect.
20f733e7 1086 */
31961943
BR		 1087 switch (tf->command) {
1088 case ATA_CMD_READ:
1089 case ATA_CMD_READ_EXT:
1090 case ATA_CMD_WRITE:
1091 case ATA_CMD_WRITE_EXT:
c15d85c8 1092 case ATA_CMD_WRITE_FUA_EXT:
31961943
BR		 1093 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1094 break;
1095#ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */
1096 case ATA_CMD_FPDMA_READ:
1097 case ATA_CMD_FPDMA_WRITE:
8b260248 1098 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
31961943
BR		 1099 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1100 break;
1101#endif /* FIXME: remove this line when NCQ added */
1102 default:
1103 /* The only other commands EDMA supports in non-queued and
1104 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1105 * of which are defined/used by Linux. If we get here, this
1106 * driver needs work.
1107 *
1108 * FIXME: modify libata to give qc_prep a return value and
1109 * return error here.
1110 */
1111 BUG_ON(tf->command);
1112 break;
1113 }
1114 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1115 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1116 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1117 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1118 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1119 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1120 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1121 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1122 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1123
e4e7b892
JG		 1124 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1125 return;
1126 mv_fill_sg(qc);
1127}
1128
1129/**
1130 * mv_qc_prep_iie - Host specific command preparation.
1131 * @qc: queued command to prepare
1132 *
1133 * This routine simply redirects to the general purpose routine
1134 * if command is not DMA. Else, it handles prep of the CRQB
1135 * (command request block), does some sanity checking, and calls
1136 * the SG load routine.
1137 *
1138 * LOCKING:
1139 * Inherited from caller.
1140 */
1141static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1142{
1143 struct ata_port *ap = qc->ap;
1144 struct mv_port_priv *pp = ap->private_data;
1145 struct mv_crqb_iie *crqb;
1146 struct ata_taskfile *tf;
a6432436 1147 unsigned in_index;
e4e7b892
JG		 1148 u32 flags = 0;
1149
1150 if (ATA_PROT_DMA != qc->tf.protocol)
1151 return;
1152
e4e7b892
JG		 1153 /* Fill in Gen IIE command request block
1154 */
1155 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1156 flags |= CRQB_FLAG_READ;
1157
beec7dbc 1158 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
e4e7b892
JG		 1159 flags |= qc->tag << CRQB_TAG_SHIFT;
1160
a6432436
ML		 1161 /* get current queue index from hardware */
1162 in_index = (readl(mv_ap_base(ap) + EDMA_REQ_Q_IN_PTR_OFS)
1163 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1164
1165 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
e4e7b892
JG		 1166 crqb->addr = cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
1167 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
1168 crqb->flags = cpu_to_le32(flags);
1169
1170 tf = &qc->tf;
1171 crqb->ata_cmd[0] = cpu_to_le32(
1172 (tf->command << 16) |
1173 (tf->feature << 24)
1174 );
1175 crqb->ata_cmd[1] = cpu_to_le32(
1176 (tf->lbal << 0) |
1177 (tf->lbam << 8) |
1178 (tf->lbah << 16) |
1179 (tf->device << 24)
1180 );
1181 crqb->ata_cmd[2] = cpu_to_le32(
1182 (tf->hob_lbal << 0) |
1183 (tf->hob_lbam << 8) |
1184 (tf->hob_lbah << 16) |
1185 (tf->hob_feature << 24)
1186 );
1187 crqb->ata_cmd[3] = cpu_to_le32(
1188 (tf->nsect << 0) |
1189 (tf->hob_nsect << 8)
1190 );
1191
1192 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
31961943 1193 return;
31961943
BR		 1194 mv_fill_sg(qc);
1195}
1196
05b308e1
BR		 1197/**
1198 * mv_qc_issue - Initiate a command to the host
1199 * @qc: queued command to start
1200 *
1201 * This routine simply redirects to the general purpose routine
1202 * if command is not DMA. Else, it sanity checks our local
1203 * caches of the request producer/consumer indices then enables
1204 * DMA and bumps the request producer index.
1205 *
1206 * LOCKING:
1207 * Inherited from caller.
1208 */
9a3d9eb0 1209static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
31961943
BR		 1210{
1211 void __iomem *port_mmio = mv_ap_base(qc->ap);
1212 struct mv_port_priv *pp = qc->ap->private_data;
a6432436 1213 unsigned in_index;
31961943
BR		 1214 u32 in_ptr;
1215
1216 if (ATA_PROT_DMA != qc->tf.protocol) {
1217 /* We're about to send a non-EDMA capable command to the
1218 * port. Turn off EDMA so there won't be problems accessing
1219 * shadow block, etc registers.
1220 */
1221 mv_stop_dma(qc->ap);
1222 return ata_qc_issue_prot(qc);
1223 }
1224
a6432436
ML		 1225 in_ptr = readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1226 in_index = (in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
31961943 1227
31961943 1228 /* until we do queuing, the queue should be empty at this point */
a6432436
ML		 1229 WARN_ON(in_index != ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS)
1230 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
31961943 1231
a6432436 1232 in_index = mv_inc_q_index(in_index); /* now incr producer index */
31961943 1233
afb0edd9 1234 mv_start_dma(port_mmio, pp);
31961943
BR		 1235
1236 /* and write the request in pointer to kick the EDMA to life */
1237 in_ptr &= EDMA_REQ_Q_BASE_LO_MASK;
a6432436 1238 in_ptr |= in_index << EDMA_REQ_Q_PTR_SHIFT;
31961943
BR		 1239 writelfl(in_ptr, port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1240
1241 return 0;
1242}
1243
05b308e1
BR		 1244/**
1245 * mv_get_crpb_status - get status from most recently completed cmd
1246 * @ap: ATA channel to manipulate
1247 *
1248 * This routine is for use when the port is in DMA mode, when it
1249 * will be using the CRPB (command response block) method of
beec7dbc 1250 * returning command completion information. We check indices
05b308e1
BR		 1251 * are good, grab status, and bump the response consumer index to
1252 * prove that we're up to date.
1253 *
1254 * LOCKING:
1255 * Inherited from caller.
1256 */
31961943
BR		 1257static u8 mv_get_crpb_status(struct ata_port *ap)
1258{
1259 void __iomem *port_mmio = mv_ap_base(ap);
1260 struct mv_port_priv *pp = ap->private_data;
a6432436 1261 unsigned out_index;
31961943 1262 u32 out_ptr;
806a6e7a 1263 u8 ata_status;
31961943 1264
a6432436
ML		 1265 out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1266 out_index = (out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
31961943 1267
a6432436
ML		 1268 ata_status = le16_to_cpu(pp->crpb[out_index].flags)
1269 >> CRPB_FLAG_STATUS_SHIFT;
806a6e7a 1270
31961943 1271 /* increment our consumer index... */
a6432436 1272 out_index = mv_inc_q_index(out_index);
8b260248 1273
31961943 1274 /* and, until we do NCQ, there should only be 1 CRPB waiting */
a6432436
ML		 1275 WARN_ON(out_index != ((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
1276 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
31961943
BR		 1277
1278 /* write out our inc'd consumer index so EDMA knows we're caught up */
1279 out_ptr &= EDMA_RSP_Q_BASE_LO_MASK;
a6432436 1280 out_ptr |= out_index << EDMA_RSP_Q_PTR_SHIFT;
31961943
BR		 1281 writelfl(out_ptr, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1282
1283 /* Return ATA status register for completed CRPB */
806a6e7a 1284 return ata_status;
31961943
BR		 1285}
1286
05b308e1
BR		 1287/**
1288 * mv_err_intr - Handle error interrupts on the port
1289 * @ap: ATA channel to manipulate
9b358e30 1290 * @reset_allowed: bool: 0 == don't trigger from reset here
05b308e1
BR		 1291 *
1292 * In most cases, just clear the interrupt and move on. However,
1293 * some cases require an eDMA reset, which is done right before
1294 * the COMRESET in mv_phy_reset(). The SERR case requires a
1295 * clear of pending errors in the SATA SERROR register. Finally,
1296 * if the port disabled DMA, update our cached copy to match.
1297 *
1298 * LOCKING:
1299 * Inherited from caller.
1300 */
9b358e30 1301static void mv_err_intr(struct ata_port *ap, int reset_allowed)
31961943
BR		 1302{
1303 void __iomem *port_mmio = mv_ap_base(ap);
1304 u32 edma_err_cause, serr = 0;
20f733e7
BR		 1305
1306 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1307
1308 if (EDMA_ERR_SERR & edma_err_cause) {
1309 serr = scr_read(ap, SCR_ERROR);
1310 scr_write_flush(ap, SCR_ERROR, serr);
1311 }
afb0edd9
BR		 1312 if (EDMA_ERR_SELF_DIS & edma_err_cause) {
1313 struct mv_port_priv *pp = ap->private_data;
1314 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1315 }
1316 DPRINTK(KERN_ERR "ata%u: port error; EDMA err cause: 0x%08x "
1317 "SERR: 0x%08x\n", ap->id, edma_err_cause, serr);
20f733e7
BR		 1318
1319 /* Clear EDMA now that SERR cleanup done */
1320 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1321
1322 /* check for fatal here and recover if needed */
9b358e30 1323 if (reset_allowed && (EDMA_ERR_FATAL & edma_err_cause))
c9d39130 1324 mv_stop_and_reset(ap);
20f733e7
BR		 1325}
1326
05b308e1
BR		 1327/**
1328 * mv_host_intr - Handle all interrupts on the given host controller
1329 * @host_set: host specific structure
1330 * @relevant: port error bits relevant to this host controller
1331 * @hc: which host controller we're to look at
1332 *
1333 * Read then write clear the HC interrupt status then walk each
1334 * port connected to the HC and see if it needs servicing. Port
1335 * success ints are reported in the HC interrupt status reg, the
1336 * port error ints are reported in the higher level main
1337 * interrupt status register and thus are passed in via the
1338 * 'relevant' argument.
1339 *
1340 * LOCKING:
1341 * Inherited from caller.
1342 */
20f733e7
BR		 1343static void mv_host_intr(struct ata_host_set *host_set, u32 relevant,
1344 unsigned int hc)
1345{
1346 void __iomem *mmio = host_set->mmio_base;
1347 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
20f733e7
BR		 1348 struct ata_queued_cmd *qc;
1349 u32 hc_irq_cause;
31961943 1350 int shift, port, port0, hard_port, handled;
a7dac447 1351 unsigned int err_mask;
20f733e7
BR		 1352
1353 if (hc == 0) {
1354 port0 = 0;
1355 } else {
1356 port0 = MV_PORTS_PER_HC;
1357 }
1358
1359 /* we'll need the HC success int register in most cases */
1360 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1361 if (hc_irq_cause) {
31961943 1362 writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
20f733e7
BR		 1363 }
1364
1365 VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n",
1366 hc,relevant,hc_irq_cause);
1367
1368 for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) {
cd85f6e2 1369 u8 ata_status = 0;
63af2a5c
ML		 1370 struct ata_port *ap = host_set->ports[port];
1371 struct mv_port_priv *pp = ap->private_data;
55d8ca4f 1372
e857f141 1373 hard_port = mv_hardport_from_port(port); /* range 0..3 */
31961943 1374 handled = 0; /* ensure ata_status is set if handled++ */
20f733e7 1375
63af2a5c 1376 /* Note that DEV_IRQ might happen spuriously during EDMA,
e857f141
ML		 1377 * and should be ignored in such cases.
1378 * The cause of this is still under investigation.
63af2a5c
ML		 1379 */
1380 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1381 /* EDMA: check for response queue interrupt */
1382 if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) {
1383 ata_status = mv_get_crpb_status(ap);
1384 handled = 1;
1385 }
1386 } else {
1387 /* PIO: check for device (drive) interrupt */
1388 if ((DEV_IRQ << hard_port) & hc_irq_cause) {
1389 ata_status = readb((void __iomem *)
20f733e7 1390 ap->ioaddr.status_addr);
63af2a5c 1391 handled = 1;
e857f141
ML		 1392 /* ignore spurious intr if drive still BUSY */
1393 if (ata_status & ATA_BUSY) {
1394 ata_status = 0;
1395 handled = 0;
1396 }
63af2a5c 1397 }
20f733e7
BR		 1398 }
1399
63af2a5c 1400 if (ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))
a2c91a88
JG		 1401 continue;
1402
a7dac447
JG		 1403 err_mask = ac_err_mask(ata_status);
1404
31961943 1405 shift = port << 1; /* (port * 2) */
20f733e7
BR		 1406 if (port >= MV_PORTS_PER_HC) {
1407 shift++; /* skip bit 8 in the HC Main IRQ reg */
1408 }
1409 if ((PORT0_ERR << shift) & relevant) {
9b358e30 1410 mv_err_intr(ap, 1);
a7dac447 1411 err_mask |= AC_ERR_OTHER;
63af2a5c 1412 handled = 1;
20f733e7 1413 }
8b260248 1414
63af2a5c 1415 if (handled) {
20f733e7 1416 qc = ata_qc_from_tag(ap, ap->active_tag);
63af2a5c 1417 if (qc && (qc->flags & ATA_QCFLAG_ACTIVE)) {
20f733e7
BR		 1418 VPRINTK("port %u IRQ found for qc, "
1419 "ata_status 0x%x\n", port,ata_status);
20f733e7 1420 /* mark qc status appropriately */
a22e2eb0
AL		 1421 if (!(qc->tf.ctl & ATA_NIEN)) {
1422 qc->err_mask |= err_mask;
1423 ata_qc_complete(qc);
1424 }
20f733e7
BR		 1425 }
1426 }
1427 }
1428 VPRINTK("EXIT\n");
1429}
1430
05b308e1 1431/**
8b260248 1432 * mv_interrupt -
05b308e1
BR		 1433 * @irq: unused
1434 * @dev_instance: private data; in this case the host structure
1435 * @regs: unused
1436 *
1437 * Read the read only register to determine if any host
1438 * controllers have pending interrupts. If so, call lower level
1439 * routine to handle. Also check for PCI errors which are only
1440 * reported here.
1441 *
8b260248 1442 * LOCKING:
05b308e1
BR		 1443 * This routine holds the host_set lock while processing pending
1444 * interrupts.
1445 */
20f733e7
BR		 1446static irqreturn_t mv_interrupt(int irq, void *dev_instance,
1447 struct pt_regs *regs)
1448{
1449 struct ata_host_set *host_set = dev_instance;
1450 unsigned int hc, handled = 0, n_hcs;
31961943 1451 void __iomem *mmio = host_set->mmio_base;
615ab953 1452 struct mv_host_priv *hpriv;
20f733e7
BR		 1453 u32 irq_stat;
1454
20f733e7 1455 irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS);
20f733e7
BR		 1456
1457 /* check the cases where we either have nothing pending or have read
1458 * a bogus register value which can indicate HW removal or PCI fault
1459 */
1460 if (!irq_stat || (0xffffffffU == irq_stat)) {
1461 return IRQ_NONE;
1462 }
1463
31961943 1464 n_hcs = mv_get_hc_count(host_set->ports[0]->flags);
20f733e7
BR		 1465 spin_lock(&host_set->lock);
1466
1467 for (hc = 0; hc < n_hcs; hc++) {
1468 u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT));
1469 if (relevant) {
1470 mv_host_intr(host_set, relevant, hc);
31961943 1471 handled++;
20f733e7
BR		 1472 }
1473 }
615ab953
ML		 1474
1475 hpriv = host_set->private_data;
1476 if (IS_60XX(hpriv)) {
1477 /* deal with the interrupt coalescing bits */
1478 if (irq_stat & (TRAN_LO_DONE | TRAN_HI_DONE | PORTS_0_7_COAL_DONE)) {
1479 writelfl(0, mmio + MV_IRQ_COAL_CAUSE_LO);
1480 writelfl(0, mmio + MV_IRQ_COAL_CAUSE_HI);
1481 writelfl(0, mmio + MV_IRQ_COAL_CAUSE);
1482 }
1483 }
1484
20f733e7 1485 if (PCI_ERR & irq_stat) {
31961943
BR		 1486 printk(KERN_ERR DRV_NAME ": PCI ERROR; PCI IRQ cause=0x%08x\n",
1487 readl(mmio + PCI_IRQ_CAUSE_OFS));
1488
afb0edd9 1489 DPRINTK("All regs @ PCI error\n");
31961943 1490 mv_dump_all_regs(mmio, -1, to_pci_dev(host_set->dev));
20f733e7 1491
31961943
BR		 1492 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
1493 handled++;
1494 }
20f733e7
BR		 1495 spin_unlock(&host_set->lock);
1496
1497 return IRQ_RETVAL(handled);
1498}
1499
c9d39130
JG		 1500static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
1501{
1502 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
1503 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
1504
1505 return hc_mmio + ofs;
1506}
1507
1508static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
1509{
1510 unsigned int ofs;
1511
1512 switch (sc_reg_in) {
1513 case SCR_STATUS:
1514 case SCR_ERROR:
1515 case SCR_CONTROL:
1516 ofs = sc_reg_in * sizeof(u32);
1517 break;
1518 default:
1519 ofs = 0xffffffffU;
1520 break;
1521 }
1522 return ofs;
1523}
1524
1525static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
1526{
1527 void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no);
1528 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1529
1530 if (ofs != 0xffffffffU)
1531 return readl(mmio + ofs);
1532 else
1533 return (u32) ofs;
1534}
1535
1536static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
1537{
1538 void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no);
1539 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1540
1541 if (ofs != 0xffffffffU)
1542 writelfl(val, mmio + ofs);
1543}
1544
522479fb
JG		 1545static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio)
1546{
1547 u8 rev_id;
1548 int early_5080;
1549
1550 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1551
1552 early_5080 = (pdev->device == 0x5080) && (rev_id == 0);
1553
1554 if (!early_5080) {
1555 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1556 tmp |= (1 << 0);
1557 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1558 }
1559
1560 mv_reset_pci_bus(pdev, mmio);
1561}
1562
1563static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1564{
1565 writel(0x0fcfffff, mmio + MV_FLASH_CTL);
1566}
1567
47c2b677 1568static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 1569 void __iomem *mmio)
1570{
c9d39130
JG		 1571 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
1572 u32 tmp;
1573
1574 tmp = readl(phy_mmio + MV5_PHY_MODE);
1575
1576 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
1577 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
ba3fe8fb
JG		 1578}
1579
47c2b677 1580static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 1581{
522479fb
JG		 1582 u32 tmp;
1583
1584 writel(0, mmio + MV_GPIO_PORT_CTL);
1585
1586 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
1587
1588 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1589 tmp |= ~(1 << 0);
1590 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
ba3fe8fb
JG		 1591}
1592
2a47ce06
JG		 1593static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1594 unsigned int port)
bca1c4eb 1595{
c9d39130
JG		 1596 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
1597 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
1598 u32 tmp;
1599 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
1600
1601 if (fix_apm_sq) {
1602 tmp = readl(phy_mmio + MV5_LT_MODE);
1603 tmp |= (1 << 19);
1604 writel(tmp, phy_mmio + MV5_LT_MODE);
1605
1606 tmp = readl(phy_mmio + MV5_PHY_CTL);
1607 tmp &= ~0x3;
1608 tmp |= 0x1;
1609 writel(tmp, phy_mmio + MV5_PHY_CTL);
1610 }
1611
1612 tmp = readl(phy_mmio + MV5_PHY_MODE);
1613 tmp &= ~mask;
1614 tmp |= hpriv->signal[port].pre;
1615 tmp |= hpriv->signal[port].amps;
1616 writel(tmp, phy_mmio + MV5_PHY_MODE);
bca1c4eb
JG		 1617}
1618
c9d39130
JG		 1619
1620#undef ZERO
1621#define ZERO(reg) writel(0, port_mmio + (reg))
1622static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
1623 unsigned int port)
1624{
1625 void __iomem *port_mmio = mv_port_base(mmio, port);
1626
1627 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
1628
1629 mv_channel_reset(hpriv, mmio, port);
1630
1631 ZERO(0x028); /* command */
1632 writel(0x11f, port_mmio + EDMA_CFG_OFS);
1633 ZERO(0x004); /* timer */
1634 ZERO(0x008); /* irq err cause */
1635 ZERO(0x00c); /* irq err mask */
1636 ZERO(0x010); /* rq bah */
1637 ZERO(0x014); /* rq inp */
1638 ZERO(0x018); /* rq outp */
1639 ZERO(0x01c); /* respq bah */
1640 ZERO(0x024); /* respq outp */
1641 ZERO(0x020); /* respq inp */
1642 ZERO(0x02c); /* test control */
1643 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
1644}
1645#undef ZERO
1646
1647#define ZERO(reg) writel(0, hc_mmio + (reg))
1648static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1649 unsigned int hc)
47c2b677 1650{
c9d39130
JG		 1651 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1652 u32 tmp;
1653
1654 ZERO(0x00c);
1655 ZERO(0x010);
1656 ZERO(0x014);
1657 ZERO(0x018);
1658
1659 tmp = readl(hc_mmio + 0x20);
1660 tmp &= 0x1c1c1c1c;
1661 tmp |= 0x03030303;
1662 writel(tmp, hc_mmio + 0x20);
1663}
1664#undef ZERO
1665
1666static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1667 unsigned int n_hc)
1668{
1669 unsigned int hc, port;
1670
1671 for (hc = 0; hc < n_hc; hc++) {
1672 for (port = 0; port < MV_PORTS_PER_HC; port++)
1673 mv5_reset_hc_port(hpriv, mmio,
1674 (hc * MV_PORTS_PER_HC) + port);
1675
1676 mv5_reset_one_hc(hpriv, mmio, hc);
1677 }
1678
1679 return 0;
47c2b677
JG		 1680}
1681
101ffae2
JG		 1682#undef ZERO
1683#define ZERO(reg) writel(0, mmio + (reg))
1684static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio)
1685{
1686 u32 tmp;
1687
1688 tmp = readl(mmio + MV_PCI_MODE);
1689 tmp &= 0xff00ffff;
1690 writel(tmp, mmio + MV_PCI_MODE);
1691
1692 ZERO(MV_PCI_DISC_TIMER);
1693 ZERO(MV_PCI_MSI_TRIGGER);
1694 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
1695 ZERO(HC_MAIN_IRQ_MASK_OFS);
1696 ZERO(MV_PCI_SERR_MASK);
1697 ZERO(PCI_IRQ_CAUSE_OFS);
1698 ZERO(PCI_IRQ_MASK_OFS);
1699 ZERO(MV_PCI_ERR_LOW_ADDRESS);
1700 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
1701 ZERO(MV_PCI_ERR_ATTRIBUTE);
1702 ZERO(MV_PCI_ERR_COMMAND);
1703}
1704#undef ZERO
1705
1706static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1707{
1708 u32 tmp;
1709
1710 mv5_reset_flash(hpriv, mmio);
1711
1712 tmp = readl(mmio + MV_GPIO_PORT_CTL);
1713 tmp &= 0x3;
1714 tmp |= (1 << 5) | (1 << 6);
1715 writel(tmp, mmio + MV_GPIO_PORT_CTL);
1716}
1717
1718/**
1719 * mv6_reset_hc - Perform the 6xxx global soft reset
1720 * @mmio: base address of the HBA
1721 *
1722 * This routine only applies to 6xxx parts.
1723 *
1724 * LOCKING:
1725 * Inherited from caller.
1726 */
c9d39130
JG		 1727static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1728 unsigned int n_hc)
101ffae2
JG		 1729{
1730 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
1731 int i, rc = 0;
1732 u32 t;
1733
1734 /* Following procedure defined in PCI "main command and status
1735 * register" table.
1736 */
1737 t = readl(reg);
1738 writel(t | STOP_PCI_MASTER, reg);
1739
1740 for (i = 0; i < 1000; i++) {
1741 udelay(1);
1742 t = readl(reg);
1743 if (PCI_MASTER_EMPTY & t) {
1744 break;
1745 }
1746 }
1747 if (!(PCI_MASTER_EMPTY & t)) {
1748 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
1749 rc = 1;
1750 goto done;
1751 }
1752
1753 /* set reset */
1754 i = 5;
1755 do {
1756 writel(t | GLOB_SFT_RST, reg);
1757 t = readl(reg);
1758 udelay(1);
1759 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
1760
1761 if (!(GLOB_SFT_RST & t)) {
1762 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
1763 rc = 1;
1764 goto done;
1765 }
1766
1767 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
1768 i = 5;
1769 do {
1770 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
1771 t = readl(reg);
1772 udelay(1);
1773 } while ((GLOB_SFT_RST & t) && (i-- > 0));
1774
1775 if (GLOB_SFT_RST & t) {
1776 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
1777 rc = 1;
1778 }
1779done:
1780 return rc;
1781}
1782
47c2b677 1783static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 1784 void __iomem *mmio)
1785{
1786 void __iomem *port_mmio;
1787 u32 tmp;
1788
ba3fe8fb
JG		 1789 tmp = readl(mmio + MV_RESET_CFG);
1790 if ((tmp & (1 << 0)) == 0) {
47c2b677 1791 hpriv->signal[idx].amps = 0x7 << 8;
ba3fe8fb
JG		 1792 hpriv->signal[idx].pre = 0x1 << 5;
1793 return;
1794 }
1795
1796 port_mmio = mv_port_base(mmio, idx);
1797 tmp = readl(port_mmio + PHY_MODE2);
1798
1799 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
1800 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
1801}
1802
47c2b677 1803static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 1804{
47c2b677 1805 writel(0x00000060, mmio + MV_GPIO_PORT_CTL);
ba3fe8fb
JG		 1806}
1807
c9d39130 1808static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2a47ce06 1809 unsigned int port)
bca1c4eb 1810{
c9d39130
JG		 1811 void __iomem *port_mmio = mv_port_base(mmio, port);
1812
bca1c4eb 1813 u32 hp_flags = hpriv->hp_flags;
47c2b677
JG		 1814 int fix_phy_mode2 =
1815 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
bca1c4eb 1816 int fix_phy_mode4 =
47c2b677
JG		 1817 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1818 u32 m2, tmp;
1819
1820 if (fix_phy_mode2) {
1821 m2 = readl(port_mmio + PHY_MODE2);
1822 m2 &= ~(1 << 16);
1823 m2 |= (1 << 31);
1824 writel(m2, port_mmio + PHY_MODE2);
1825
1826 udelay(200);
1827
1828 m2 = readl(port_mmio + PHY_MODE2);
1829 m2 &= ~((1 << 16) | (1 << 31));
1830 writel(m2, port_mmio + PHY_MODE2);
1831
1832 udelay(200);
1833 }
1834
1835 /* who knows what this magic does */
1836 tmp = readl(port_mmio + PHY_MODE3);
1837 tmp &= ~0x7F800000;
1838 tmp |= 0x2A800000;
1839 writel(tmp, port_mmio + PHY_MODE3);
bca1c4eb
JG		 1840
1841 if (fix_phy_mode4) {
47c2b677 1842 u32 m4;
bca1c4eb
JG		 1843
1844 m4 = readl(port_mmio + PHY_MODE4);
47c2b677
JG		 1845
1846 if (hp_flags & MV_HP_ERRATA_60X1B2)
1847 tmp = readl(port_mmio + 0x310);
bca1c4eb
JG		 1848
1849 m4 = (m4 & ~(1 << 1)) | (1 << 0);
1850
1851 writel(m4, port_mmio + PHY_MODE4);
47c2b677
JG		 1852
1853 if (hp_flags & MV_HP_ERRATA_60X1B2)
1854 writel(tmp, port_mmio + 0x310);
bca1c4eb
JG		 1855 }
1856
1857 /* Revert values of pre-emphasis and signal amps to the saved ones */
1858 m2 = readl(port_mmio + PHY_MODE2);
1859
1860 m2 &= ~MV_M2_PREAMP_MASK;
2a47ce06
JG		 1861 m2 |= hpriv->signal[port].amps;
1862 m2 |= hpriv->signal[port].pre;
47c2b677 1863 m2 &= ~(1 << 16);
bca1c4eb 1864
e4e7b892
JG		 1865 /* according to mvSata 3.6.1, some IIE values are fixed */
1866 if (IS_GEN_IIE(hpriv)) {
1867 m2 &= ~0xC30FF01F;
1868 m2 |= 0x0000900F;
1869 }
1870
bca1c4eb
JG		 1871 writel(m2, port_mmio + PHY_MODE2);
1872}
1873
c9d39130
JG		 1874static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
1875 unsigned int port_no)
1876{
1877 void __iomem *port_mmio = mv_port_base(mmio, port_no);
1878
1879 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
1880
1881 if (IS_60XX(hpriv)) {
1882 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
eb46d684
ML		 1883 ifctl |= (1 << 7); /* enable gen2i speed */
1884 ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */
c9d39130
JG		 1885 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
1886 }
1887
1888 udelay(25); /* allow reset propagation */
1889
1890 /* Spec never mentions clearing the bit. Marvell's driver does
1891 * clear the bit, however.
1892 */
1893 writelfl(0, port_mmio + EDMA_CMD_OFS);
1894
1895 hpriv->ops->phy_errata(hpriv, mmio, port_no);
1896
1897 if (IS_50XX(hpriv))
1898 mdelay(1);
1899}
1900
1901static void mv_stop_and_reset(struct ata_port *ap)
1902{
1903 struct mv_host_priv *hpriv = ap->host_set->private_data;
1904 void __iomem *mmio = ap->host_set->mmio_base;
1905
1906 mv_stop_dma(ap);
1907
1908 mv_channel_reset(hpriv, mmio, ap->port_no);
1909
22374677
JG		 1910 __mv_phy_reset(ap, 0);
1911}
1912
1913static inline void __msleep(unsigned int msec, int can_sleep)
1914{
1915 if (can_sleep)
1916 msleep(msec);
1917 else
1918 mdelay(msec);
c9d39130
JG		 1919}
1920
05b308e1 1921/**
22374677 1922 * __mv_phy_reset - Perform eDMA reset followed by COMRESET
05b308e1
BR		 1923 * @ap: ATA channel to manipulate
1924 *
1925 * Part of this is taken from __sata_phy_reset and modified to
1926 * not sleep since this routine gets called from interrupt level.
1927 *
1928 * LOCKING:
1929 * Inherited from caller. This is coded to safe to call at
1930 * interrupt level, i.e. it does not sleep.
31961943 1931 */
22374677 1932static void __mv_phy_reset(struct ata_port *ap, int can_sleep)
20f733e7 1933{
095fec88 1934 struct mv_port_priv *pp = ap->private_data;
22374677 1935 struct mv_host_priv *hpriv = ap->host_set->private_data;
20f733e7
BR		 1936 void __iomem *port_mmio = mv_ap_base(ap);
1937 struct ata_taskfile tf;
1938 struct ata_device *dev = &ap->device[0];
31961943 1939 unsigned long timeout;
22374677
JG		 1940 int retry = 5;
1941 u32 sstatus;
20f733e7
BR		 1942
1943 VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);
1944
095fec88 1945 DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
31961943
BR		 1946 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1947 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
20f733e7 1948
22374677
JG		 1949 /* Issue COMRESET via SControl */
1950comreset_retry:
31961943 1951 scr_write_flush(ap, SCR_CONTROL, 0x301);
22374677
JG		 1952 __msleep(1, can_sleep);
1953
31961943 1954 scr_write_flush(ap, SCR_CONTROL, 0x300);
22374677
JG		 1955 __msleep(20, can_sleep);
1956
1957 timeout = jiffies + msecs_to_jiffies(200);
31961943 1958 do {
22374677
JG		 1959 sstatus = scr_read(ap, SCR_STATUS) & 0x3;
1960 if ((sstatus == 3) || (sstatus == 0))
31961943 1961 break;
22374677
JG		 1962
1963 __msleep(1, can_sleep);
31961943 1964 } while (time_before(jiffies, timeout));
20f733e7 1965
22374677
JG		 1966 /* work around errata */
1967 if (IS_60XX(hpriv) &&
1968 (sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) &&
1969 (retry-- > 0))
1970 goto comreset_retry;
095fec88
JG		 1971
1972 DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
31961943
BR		 1973 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1974 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1975
1976 if (sata_dev_present(ap)) {
1977 ata_port_probe(ap);
1978 } else {
1979 printk(KERN_INFO "ata%u: no device found (phy stat %08x)\n",
1980 ap->id, scr_read(ap, SCR_STATUS));
1981 ata_port_disable(ap);
20f733e7
BR		 1982 return;
1983 }
31961943 1984 ap->cbl = ATA_CBL_SATA;
20f733e7 1985
22374677
JG		 1986 /* even after SStatus reflects that device is ready,
1987 * it seems to take a while for link to be fully
1988 * established (and thus Status no longer 0x80/0x7F),
1989 * so we poll a bit for that, here.
1990 */
1991 retry = 20;
1992 while (1) {
1993 u8 drv_stat = ata_check_status(ap);
1994 if ((drv_stat != 0x80) && (drv_stat != 0x7f))
1995 break;
1996 __msleep(500, can_sleep);
1997 if (retry-- <= 0)
1998 break;
1999 }
2000
20f733e7
BR		 2001 tf.lbah = readb((void __iomem *) ap->ioaddr.lbah_addr);
2002 tf.lbam = readb((void __iomem *) ap->ioaddr.lbam_addr);
2003 tf.lbal = readb((void __iomem *) ap->ioaddr.lbal_addr);
2004 tf.nsect = readb((void __iomem *) ap->ioaddr.nsect_addr);
2005
2006 dev->class = ata_dev_classify(&tf);
2007 if (!ata_dev_present(dev)) {
2008 VPRINTK("Port disabled post-sig: No device present.\n");
2009 ata_port_disable(ap);
2010 }
095fec88
JG		 2011
2012 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2013
2014 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2015
bca1c4eb 2016 VPRINTK("EXIT\n");
20f733e7
BR		 2017}
2018
22374677
JG		 2019static void mv_phy_reset(struct ata_port *ap)
2020{
2021 __mv_phy_reset(ap, 1);
2022}
2023
05b308e1
BR		 2024/**
2025 * mv_eng_timeout - Routine called by libata when SCSI times out I/O
2026 * @ap: ATA channel to manipulate
2027 *
2028 * Intent is to clear all pending error conditions, reset the
2029 * chip/bus, fail the command, and move on.
2030 *
2031 * LOCKING:
2032 * This routine holds the host_set lock while failing the command.
2033 */
31961943
BR		 2034static void mv_eng_timeout(struct ata_port *ap)
2035{
2036 struct ata_queued_cmd *qc;
31961943
BR		 2037
2038 printk(KERN_ERR "ata%u: Entering mv_eng_timeout\n",ap->id);
2039 DPRINTK("All regs @ start of eng_timeout\n");
8b260248 2040 mv_dump_all_regs(ap->host_set->mmio_base, ap->port_no,
31961943
BR		 2041 to_pci_dev(ap->host_set->dev));
2042
2043 qc = ata_qc_from_tag(ap, ap->active_tag);
2044 printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n",
8b260248 2045 ap->host_set->mmio_base, ap, qc, qc->scsicmd,
31961943
BR		 2046 &qc->scsicmd->cmnd);
2047
9b358e30 2048 mv_err_intr(ap, 0);
c9d39130 2049 mv_stop_and_reset(ap);
31961943 2050
9b358e30
ML		 2051 WARN_ON(!(qc->flags & ATA_QCFLAG_ACTIVE));
2052 if (qc->flags & ATA_QCFLAG_ACTIVE) {
2053 qc->err_mask |= AC_ERR_TIMEOUT;
2054 ata_eh_qc_complete(qc);
2055 }
31961943
BR		 2056}
2057
05b308e1
BR		 2058/**
2059 * mv_port_init - Perform some early initialization on a single port.
2060 * @port: libata data structure storing shadow register addresses
2061 * @port_mmio: base address of the port
2062 *
2063 * Initialize shadow register mmio addresses, clear outstanding
2064 * interrupts on the port, and unmask interrupts for the future
2065 * start of the port.
2066 *
2067 * LOCKING:
2068 * Inherited from caller.
2069 */
31961943 2070static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
20f733e7 2071{
31961943
BR		 2072 unsigned long shd_base = (unsigned long) port_mmio + SHD_BLK_OFS;
2073 unsigned serr_ofs;
2074
8b260248 2075 /* PIO related setup
31961943
BR		 2076 */
2077 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
8b260248 2078 port->error_addr =
31961943
BR		 2079 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2080 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2081 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2082 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2083 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2084 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
8b260248 2085 port->status_addr =
31961943
BR		 2086 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2087 /* special case: control/altstatus doesn't have ATA_REG_ address */
2088 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2089
2090 /* unused: */
20f733e7
BR		 2091 port->cmd_addr = port->bmdma_addr = port->scr_addr = 0;
2092
31961943
BR		 2093 /* Clear any currently outstanding port interrupt conditions */
2094 serr_ofs = mv_scr_offset(SCR_ERROR);
2095 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2096 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2097
20f733e7 2098 /* unmask all EDMA error interrupts */
31961943 2099 writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
20f733e7 2100
8b260248 2101 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
31961943
BR		 2102 readl(port_mmio + EDMA_CFG_OFS),
2103 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2104 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
20f733e7
BR		 2105}
2106
47c2b677 2107static int mv_chip_id(struct pci_dev *pdev, struct mv_host_priv *hpriv,
522479fb 2108 unsigned int board_idx)
bca1c4eb
JG		 2109{
2110 u8 rev_id;
2111 u32 hp_flags = hpriv->hp_flags;
2112
2113 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2114
2115 switch(board_idx) {
47c2b677
JG		 2116 case chip_5080:
2117 hpriv->ops = &mv5xxx_ops;
2118 hp_flags |= MV_HP_50XX;
2119
2120 switch (rev_id) {
2121 case 0x1:
2122 hp_flags |= MV_HP_ERRATA_50XXB0;
2123 break;
2124 case 0x3:
2125 hp_flags |= MV_HP_ERRATA_50XXB2;
2126 break;
2127 default:
2128 dev_printk(KERN_WARNING, &pdev->dev,
2129 "Applying 50XXB2 workarounds to unknown rev\n");
2130 hp_flags |= MV_HP_ERRATA_50XXB2;
2131 break;
2132 }
2133 break;
2134
bca1c4eb
JG		 2135 case chip_504x:
2136 case chip_508x:
47c2b677 2137 hpriv->ops = &mv5xxx_ops;
bca1c4eb
JG		 2138 hp_flags |= MV_HP_50XX;
2139
47c2b677
JG		 2140 switch (rev_id) {
2141 case 0x0:
2142 hp_flags |= MV_HP_ERRATA_50XXB0;
2143 break;
2144 case 0x3:
2145 hp_flags |= MV_HP_ERRATA_50XXB2;
2146 break;
2147 default:
2148 dev_printk(KERN_WARNING, &pdev->dev,
2149 "Applying B2 workarounds to unknown rev\n");
2150 hp_flags |= MV_HP_ERRATA_50XXB2;
2151 break;
bca1c4eb
JG		 2152 }
2153 break;
2154
2155 case chip_604x:
2156 case chip_608x:
47c2b677
JG		 2157 hpriv->ops = &mv6xxx_ops;
2158
bca1c4eb 2159 switch (rev_id) {
47c2b677
JG		 2160 case 0x7:
2161 hp_flags |= MV_HP_ERRATA_60X1B2;
2162 break;
2163 case 0x9:
2164 hp_flags |= MV_HP_ERRATA_60X1C0;
bca1c4eb
JG		 2165 break;
2166 default:
2167 dev_printk(KERN_WARNING, &pdev->dev,
47c2b677
JG		 2168 "Applying B2 workarounds to unknown rev\n");
2169 hp_flags |= MV_HP_ERRATA_60X1B2;
bca1c4eb
JG		 2170 break;
2171 }
2172 break;
2173
e4e7b892
JG		 2174 case chip_7042:
2175 case chip_6042:
2176 hpriv->ops = &mv6xxx_ops;
2177
2178 hp_flags |= MV_HP_GEN_IIE;
2179
2180 switch (rev_id) {
2181 case 0x0:
2182 hp_flags |= MV_HP_ERRATA_XX42A0;
2183 break;
2184 case 0x1:
2185 hp_flags |= MV_HP_ERRATA_60X1C0;
2186 break;
2187 default:
2188 dev_printk(KERN_WARNING, &pdev->dev,
2189 "Applying 60X1C0 workarounds to unknown rev\n");
2190 hp_flags |= MV_HP_ERRATA_60X1C0;
2191 break;
2192 }
2193 break;
2194
bca1c4eb
JG		 2195 default:
2196 printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx);
2197 return 1;
2198 }
2199
2200 hpriv->hp_flags = hp_flags;
2201
2202 return 0;
2203}
2204
05b308e1 2205/**
47c2b677 2206 * mv_init_host - Perform some early initialization of the host.
bca1c4eb 2207 * @pdev: host PCI device
05b308e1
BR		 2208 * @probe_ent: early data struct representing the host
2209 *
2210 * If possible, do an early global reset of the host. Then do
2211 * our port init and clear/unmask all/relevant host interrupts.
2212 *
2213 * LOCKING:
2214 * Inherited from caller.
2215 */
47c2b677 2216static int mv_init_host(struct pci_dev *pdev, struct ata_probe_ent *probe_ent,
bca1c4eb 2217 unsigned int board_idx)
20f733e7
BR		 2218{
2219 int rc = 0, n_hc, port, hc;
2220 void __iomem *mmio = probe_ent->mmio_base;
bca1c4eb
JG		 2221 struct mv_host_priv *hpriv = probe_ent->private_data;
2222
47c2b677
JG		 2223 /* global interrupt mask */
2224 writel(0, mmio + HC_MAIN_IRQ_MASK_OFS);
2225
2226 rc = mv_chip_id(pdev, hpriv, board_idx);
bca1c4eb
JG		 2227 if (rc)
2228 goto done;
2229
2230 n_hc = mv_get_hc_count(probe_ent->host_flags);
2231 probe_ent->n_ports = MV_PORTS_PER_HC * n_hc;
2232
47c2b677
JG		 2233 for (port = 0; port < probe_ent->n_ports; port++)
2234 hpriv->ops->read_preamp(hpriv, port, mmio);
20f733e7 2235
c9d39130 2236 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
47c2b677 2237 if (rc)
20f733e7 2238 goto done;
20f733e7 2239
522479fb
JG		 2240 hpriv->ops->reset_flash(hpriv, mmio);
2241 hpriv->ops->reset_bus(pdev, mmio);
47c2b677 2242 hpriv->ops->enable_leds(hpriv, mmio);
20f733e7
BR		 2243
2244 for (port = 0; port < probe_ent->n_ports; port++) {
2a47ce06 2245 if (IS_60XX(hpriv)) {
c9d39130
JG		 2246 void __iomem *port_mmio = mv_port_base(mmio, port);
2247
2a47ce06 2248 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
eb46d684
ML		 2249 ifctl |= (1 << 7); /* enable gen2i speed */
2250 ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */
2a47ce06
JG		 2251 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
2252 }
2253
c9d39130 2254 hpriv->ops->phy_errata(hpriv, mmio, port);
2a47ce06
JG		 2255 }
2256
2257 for (port = 0; port < probe_ent->n_ports; port++) {
2258 void __iomem *port_mmio = mv_port_base(mmio, port);
31961943 2259 mv_port_init(&probe_ent->port[port], port_mmio);
20f733e7
BR		 2260 }
2261
2262 for (hc = 0; hc < n_hc; hc++) {
31961943
BR		 2263 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2264
2265 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
2266 "(before clear)=0x%08x\n", hc,
2267 readl(hc_mmio + HC_CFG_OFS),
2268 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
2269
2270 /* Clear any currently outstanding hc interrupt conditions */
2271 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
20f733e7
BR		 2272 }
2273
31961943
BR		 2274 /* Clear any currently outstanding host interrupt conditions */
2275 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
2276
2277 /* and unmask interrupt generation for host regs */
2278 writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS);
2279 writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS);
20f733e7
BR		 2280
2281 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
8b260248 2282 "PCI int cause/mask=0x%08x/0x%08x\n",
20f733e7
BR		 2283 readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
2284 readl(mmio + HC_MAIN_IRQ_MASK_OFS),
2285 readl(mmio + PCI_IRQ_CAUSE_OFS),
2286 readl(mmio + PCI_IRQ_MASK_OFS));
bca1c4eb 2287
31961943 2288done:
20f733e7
BR		 2289 return rc;
2290}
2291
05b308e1
BR		 2292/**
2293 * mv_print_info - Dump key info to kernel log for perusal.
2294 * @probe_ent: early data struct representing the host
2295 *
2296 * FIXME: complete this.
2297 *
2298 * LOCKING:
2299 * Inherited from caller.
2300 */
31961943
BR		 2301static void mv_print_info(struct ata_probe_ent *probe_ent)
2302{
2303 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
2304 struct mv_host_priv *hpriv = probe_ent->private_data;
2305 u8 rev_id, scc;
2306 const char *scc_s;
2307
2308 /* Use this to determine the HW stepping of the chip so we know
2309 * what errata to workaround
2310 */
2311 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2312
2313 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
2314 if (scc == 0)
2315 scc_s = "SCSI";
2316 else if (scc == 0x01)
2317 scc_s = "RAID";
2318 else
2319 scc_s = "unknown";
2320
a9524a76
JG		 2321 dev_printk(KERN_INFO, &pdev->dev,
2322 "%u slots %u ports %s mode IRQ via %s\n",
8b260248 2323 (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports,
31961943
BR		 2324 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
2325}
2326
05b308e1
BR		 2327/**
2328 * mv_init_one - handle a positive probe of a Marvell host
2329 * @pdev: PCI device found
2330 * @ent: PCI device ID entry for the matched host
2331 *
2332 * LOCKING:
2333 * Inherited from caller.
2334 */
20f733e7
BR		 2335static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2336{
2337 static int printed_version = 0;
2338 struct ata_probe_ent *probe_ent = NULL;
2339 struct mv_host_priv *hpriv;
2340 unsigned int board_idx = (unsigned int)ent->driver_data;
2341 void __iomem *mmio_base;
31961943 2342 int pci_dev_busy = 0, rc;
20f733e7 2343
a9524a76
JG		 2344 if (!printed_version++)
2345 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
20f733e7 2346
20f733e7
BR		 2347 rc = pci_enable_device(pdev);
2348 if (rc) {
2349 return rc;
2350 }
eb46d684 2351 pci_set_master(pdev);
20f733e7
BR		 2352
2353 rc = pci_request_regions(pdev, DRV_NAME);
2354 if (rc) {
2355 pci_dev_busy = 1;
2356 goto err_out;
2357 }
2358
20f733e7
BR		 2359 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
2360 if (probe_ent == NULL) {
2361 rc = -ENOMEM;
2362 goto err_out_regions;
2363 }
2364
2365 memset(probe_ent, 0, sizeof(*probe_ent));
2366 probe_ent->dev = pci_dev_to_dev(pdev);
2367 INIT_LIST_HEAD(&probe_ent->node);
2368
31961943 2369 mmio_base = pci_iomap(pdev, MV_PRIMARY_BAR, 0);
20f733e7
BR		 2370 if (mmio_base == NULL) {
2371 rc = -ENOMEM;
2372 goto err_out_free_ent;
2373 }
2374
2375 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
2376 if (!hpriv) {
2377 rc = -ENOMEM;
2378 goto err_out_iounmap;
2379 }
2380 memset(hpriv, 0, sizeof(*hpriv));
2381
2382 probe_ent->sht = mv_port_info[board_idx].sht;
2383 probe_ent->host_flags = mv_port_info[board_idx].host_flags;
2384 probe_ent->pio_mask = mv_port_info[board_idx].pio_mask;
2385 probe_ent->udma_mask = mv_port_info[board_idx].udma_mask;
2386 probe_ent->port_ops = mv_port_info[board_idx].port_ops;
2387
2388 probe_ent->irq = pdev->irq;
2389 probe_ent->irq_flags = SA_SHIRQ;
2390 probe_ent->mmio_base = mmio_base;
2391 probe_ent->private_data = hpriv;
2392
2393 /* initialize adapter */
47c2b677 2394 rc = mv_init_host(pdev, probe_ent, board_idx);
20f733e7
BR		 2395 if (rc) {
2396 goto err_out_hpriv;
2397 }
20f733e7 2398
31961943 2399 /* Enable interrupts */
ddef9bb3 2400 if (msi && pci_enable_msi(pdev) == 0) {
31961943
BR		 2401 hpriv->hp_flags |= MV_HP_FLAG_MSI;
2402 } else {
2403 pci_intx(pdev, 1);
20f733e7
BR		 2404 }
2405
31961943
BR		 2406 mv_dump_pci_cfg(pdev, 0x68);
2407 mv_print_info(probe_ent);
2408
2409 if (ata_device_add(probe_ent) == 0) {
2410 rc = -ENODEV; /* No devices discovered */
2411 goto err_out_dev_add;
2412 }
20f733e7 2413
31961943 2414 kfree(probe_ent);
20f733e7
BR		 2415 return 0;
2416
31961943
BR		 2417err_out_dev_add:
2418 if (MV_HP_FLAG_MSI & hpriv->hp_flags) {
2419 pci_disable_msi(pdev);
2420 } else {
2421 pci_intx(pdev, 0);
2422 }
2423err_out_hpriv:
20f733e7 2424 kfree(hpriv);
31961943
BR		 2425err_out_iounmap:
2426 pci_iounmap(pdev, mmio_base);
2427err_out_free_ent:
20f733e7 2428 kfree(probe_ent);
31961943 2429err_out_regions:
20f733e7 2430 pci_release_regions(pdev);
31961943 2431err_out:
20f733e7
BR		 2432 if (!pci_dev_busy) {
2433 pci_disable_device(pdev);
2434 }
2435
2436 return rc;
2437}
2438
2439static int __init mv_init(void)
2440{
2441 return pci_module_init(&mv_pci_driver);
2442}
2443
2444static void __exit mv_exit(void)
2445{
2446 pci_unregister_driver(&mv_pci_driver);
2447}
2448
2449MODULE_AUTHOR("Brett Russ");
2450MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
2451MODULE_LICENSE("GPL");
2452MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
2453MODULE_VERSION(DRV_VERSION);
2454
ddef9bb3
JG		 2455module_param(msi, int, 0444);
2456MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
2457
20f733e7
BR		 2458module_init(mv_init);
2459module_exit(mv_exit);
Linux kernel - Deliverables
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