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[PATCH] libata: Marvell spinlock fixes and simplification
[deliverable/linux.git] / drivers / scsi / sata_mv.c
CommitLineData
20f733e7
BR		 1/*
2 * sata_mv.c - Marvell SATA support
3 *
4 * Copyright 2005: EMC Corporation, all rights reserved.
5 *
6 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/pci.h>
26#include <linux/init.h>
27#include <linux/blkdev.h>
28#include <linux/delay.h>
29#include <linux/interrupt.h>
30#include <linux/sched.h>
31#include <linux/dma-mapping.h>
32#include "scsi.h"
33#include <scsi/scsi_host.h>
34#include <linux/libata.h>
35#include <asm/io.h>
36
37#define DRV_NAME "sata_mv"
afb0edd9 38#define DRV_VERSION "0.23"
20f733e7
BR		 39
40enum {
41 /* BAR's are enumerated in terms of pci_resource_start() terms */
42 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
43 MV_IO_BAR = 2, /* offset 0x18: IO space */
44 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
45
46 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
47 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
48
49 MV_PCI_REG_BASE = 0,
50 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
51 MV_SATAHC0_REG_BASE = 0x20000,
52
53 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
54 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
55 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
56 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
57
31961943 58 MV_USE_Q_DEPTH = ATA_DEF_QUEUE,
20f733e7 59
31961943
BR		 60 MV_MAX_Q_DEPTH = 32,
61 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
62
63 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
64 * CRPB needs alignment on a 256B boundary. Size == 256B
65 * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB
66 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
67 */
68 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
69 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
70 MV_MAX_SG_CT = 176,
71 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
72 MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ),
73
74 /* Our DMA boundary is determined by an ePRD being unable to handle
75 * anything larger than 64KB
76 */
77 MV_DMA_BOUNDARY = 0xffffU,
20f733e7
BR		 78
79 MV_PORTS_PER_HC = 4,
80 /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
81 MV_PORT_HC_SHIFT = 2,
31961943 82 /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */
20f733e7
BR		 83 MV_PORT_MASK = 3,
84
85 /* Host Flags */
86 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
87 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
31961943
BR		 88 MV_FLAG_GLBL_SFT_RST = (1 << 28), /* Global Soft Reset support */
89 MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
90 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO),
91 MV_6XXX_FLAGS = (MV_FLAG_IRQ_COALESCE |
92 MV_FLAG_GLBL_SFT_RST),
20f733e7
BR		 93
94 chip_504x = 0,
95 chip_508x = 1,
96 chip_604x = 2,
97 chip_608x = 3,
98
31961943
BR		 99 CRQB_FLAG_READ = (1 << 0),
100 CRQB_TAG_SHIFT = 1,
101 CRQB_CMD_ADDR_SHIFT = 8,
102 CRQB_CMD_CS = (0x2 << 11),
103 CRQB_CMD_LAST = (1 << 15),
104
105 CRPB_FLAG_STATUS_SHIFT = 8,
106
107 EPRD_FLAG_END_OF_TBL = (1 << 31),
108
20f733e7
BR		 109 /* PCI interface registers */
110
31961943
BR		 111 PCI_COMMAND_OFS = 0xc00,
112
20f733e7
BR		 113 PCI_MAIN_CMD_STS_OFS = 0xd30,
114 STOP_PCI_MASTER = (1 << 2),
115 PCI_MASTER_EMPTY = (1 << 3),
116 GLOB_SFT_RST = (1 << 4),
117
118 PCI_IRQ_CAUSE_OFS = 0x1d58,
119 PCI_IRQ_MASK_OFS = 0x1d5c,
120 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
121
122 HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
123 HC_MAIN_IRQ_MASK_OFS = 0x1d64,
124 PORT0_ERR = (1 << 0), /* shift by port # */
125 PORT0_DONE = (1 << 1), /* shift by port # */
126 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
127 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
128 PCI_ERR = (1 << 18),
129 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
130 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
131 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
132 GPIO_INT = (1 << 22),
133 SELF_INT = (1 << 23),
134 TWSI_INT = (1 << 24),
135 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
136 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
137 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
138 HC_MAIN_RSVD),
139
140 /* SATAHC registers */
141 HC_CFG_OFS = 0,
142
143 HC_IRQ_CAUSE_OFS = 0x14,
31961943 144 CRPB_DMA_DONE = (1 << 0), /* shift by port # */
20f733e7
BR		 145 HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */
146 DEV_IRQ = (1 << 8), /* shift by port # */
147
148 /* Shadow block registers */
31961943
BR		 149 SHD_BLK_OFS = 0x100,
150 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
20f733e7
BR		 151
152 /* SATA registers */
153 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
154 SATA_ACTIVE_OFS = 0x350,
155
156 /* Port registers */
157 EDMA_CFG_OFS = 0,
31961943
BR		 158 EDMA_CFG_Q_DEPTH = 0, /* queueing disabled */
159 EDMA_CFG_NCQ = (1 << 5),
160 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
161 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
162 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
20f733e7
BR		 163
164 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
165 EDMA_ERR_IRQ_MASK_OFS = 0xc,
166 EDMA_ERR_D_PAR = (1 << 0),
167 EDMA_ERR_PRD_PAR = (1 << 1),
168 EDMA_ERR_DEV = (1 << 2),
169 EDMA_ERR_DEV_DCON = (1 << 3),
170 EDMA_ERR_DEV_CON = (1 << 4),
171 EDMA_ERR_SERR = (1 << 5),
172 EDMA_ERR_SELF_DIS = (1 << 7),
173 EDMA_ERR_BIST_ASYNC = (1 << 8),
174 EDMA_ERR_CRBQ_PAR = (1 << 9),
175 EDMA_ERR_CRPB_PAR = (1 << 10),
176 EDMA_ERR_INTRL_PAR = (1 << 11),
177 EDMA_ERR_IORDY = (1 << 12),
178 EDMA_ERR_LNK_CTRL_RX = (0xf << 13),
179 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15),
180 EDMA_ERR_LNK_DATA_RX = (0xf << 17),
181 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21),
182 EDMA_ERR_LNK_DATA_TX = (0x1f << 26),
183 EDMA_ERR_TRANS_PROTO = (1 << 31),
184 EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
185 EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR |
186 EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR |
187 EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 |
188 EDMA_ERR_LNK_DATA_RX |
189 EDMA_ERR_LNK_DATA_TX |
190 EDMA_ERR_TRANS_PROTO),
191
31961943
BR		 192 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
193 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
194 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
195
196 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
197 EDMA_REQ_Q_PTR_SHIFT = 5,
198
199 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
200 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
201 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
202 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
203 EDMA_RSP_Q_PTR_SHIFT = 3,
204
20f733e7
BR		 205 EDMA_CMD_OFS = 0x28,
206 EDMA_EN = (1 << 0),
207 EDMA_DS = (1 << 1),
208 ATA_RST = (1 << 2),
209
31961943
BR		 210 /* Host private flags (hp_flags) */
211 MV_HP_FLAG_MSI = (1 << 0),
20f733e7 212
31961943
BR		 213 /* Port private flags (pp_flags) */
214 MV_PP_FLAG_EDMA_EN = (1 << 0),
215 MV_PP_FLAG_EDMA_DS_ACT = (1 << 1),
20f733e7
BR		 216};
217
31961943
BR		 218/* Command ReQuest Block: 32B */
219struct mv_crqb {
220 u32 sg_addr;
221 u32 sg_addr_hi;
222 u16 ctrl_flags;
223 u16 ata_cmd[11];
224};
20f733e7 225
31961943
BR		 226/* Command ResPonse Block: 8B */
227struct mv_crpb {
228 u16 id;
229 u16 flags;
230 u32 tmstmp;
20f733e7
BR		 231};
232
31961943
BR		 233/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
234struct mv_sg {
235 u32 addr;
236 u32 flags_size;
237 u32 addr_hi;
238 u32 reserved;
239};
20f733e7 240
31961943
BR		 241struct mv_port_priv {
242 struct mv_crqb *crqb;
243 dma_addr_t crqb_dma;
244 struct mv_crpb *crpb;
245 dma_addr_t crpb_dma;
246 struct mv_sg *sg_tbl;
247 dma_addr_t sg_tbl_dma;
248
249 unsigned req_producer; /* cp of req_in_ptr */
250 unsigned rsp_consumer; /* cp of rsp_out_ptr */
251 u32 pp_flags;
252};
253
254struct mv_host_priv {
255 u32 hp_flags;
20f733e7
BR		 256};
257
258static void mv_irq_clear(struct ata_port *ap);
259static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
260static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
31961943 261static u8 mv_check_err(struct ata_port *ap);
20f733e7 262static void mv_phy_reset(struct ata_port *ap);
31961943
BR		 263static void mv_host_stop(struct ata_host_set *host_set);
264static int mv_port_start(struct ata_port *ap);
265static void mv_port_stop(struct ata_port *ap);
266static void mv_qc_prep(struct ata_queued_cmd *qc);
267static int mv_qc_issue(struct ata_queued_cmd *qc);
20f733e7
BR		 268static irqreturn_t mv_interrupt(int irq, void *dev_instance,
269 struct pt_regs *regs);
31961943 270static void mv_eng_timeout(struct ata_port *ap);
20f733e7
BR		 271static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
272
273static Scsi_Host_Template mv_sht = {
274 .module = THIS_MODULE,
275 .name = DRV_NAME,
276 .ioctl = ata_scsi_ioctl,
277 .queuecommand = ata_scsi_queuecmd,
278 .eh_strategy_handler = ata_scsi_error,
31961943 279 .can_queue = MV_USE_Q_DEPTH,
20f733e7 280 .this_id = ATA_SHT_THIS_ID,
31961943 281 .sg_tablesize = MV_MAX_SG_CT,
20f733e7
BR		 282 .max_sectors = ATA_MAX_SECTORS,
283 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
284 .emulated = ATA_SHT_EMULATED,
31961943 285 .use_clustering = ATA_SHT_USE_CLUSTERING,
20f733e7
BR		 286 .proc_name = DRV_NAME,
287 .dma_boundary = MV_DMA_BOUNDARY,
288 .slave_configure = ata_scsi_slave_config,
289 .bios_param = ata_std_bios_param,
290 .ordered_flush = 1,
291};
292
293static struct ata_port_operations mv_ops = {
294 .port_disable = ata_port_disable,
295
296 .tf_load = ata_tf_load,
297 .tf_read = ata_tf_read,
298 .check_status = ata_check_status,
31961943 299 .check_err = mv_check_err,
20f733e7
BR		 300 .exec_command = ata_exec_command,
301 .dev_select = ata_std_dev_select,
302
303 .phy_reset = mv_phy_reset,
304
31961943
BR		 305 .qc_prep = mv_qc_prep,
306 .qc_issue = mv_qc_issue,
20f733e7 307
31961943 308 .eng_timeout = mv_eng_timeout,
20f733e7
BR		 309
310 .irq_handler = mv_interrupt,
311 .irq_clear = mv_irq_clear,
312
313 .scr_read = mv_scr_read,
314 .scr_write = mv_scr_write,
315
31961943
BR		 316 .port_start = mv_port_start,
317 .port_stop = mv_port_stop,
318 .host_stop = mv_host_stop,
20f733e7
BR		 319};
320
321static struct ata_port_info mv_port_info[] = {
322 { /* chip_504x */
323 .sht = &mv_sht,
31961943
BR		 324 .host_flags = MV_COMMON_FLAGS,
325 .pio_mask = 0x1f, /* pio0-4 */
326 .udma_mask = 0, /* 0x7f (udma0-6 disabled for now) */
20f733e7
BR		 327 .port_ops = &mv_ops,
328 },
329 { /* chip_508x */
330 .sht = &mv_sht,
31961943
BR		 331 .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
332 .pio_mask = 0x1f, /* pio0-4 */
333 .udma_mask = 0, /* 0x7f (udma0-6 disabled for now) */
20f733e7
BR		 334 .port_ops = &mv_ops,
335 },
336 { /* chip_604x */
337 .sht = &mv_sht,
31961943
BR		 338 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
339 .pio_mask = 0x1f, /* pio0-4 */
340 .udma_mask = 0x7f, /* udma0-6 */
20f733e7
BR		 341 .port_ops = &mv_ops,
342 },
343 { /* chip_608x */
344 .sht = &mv_sht,
31961943
BR		 345 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
346 MV_FLAG_DUAL_HC),
347 .pio_mask = 0x1f, /* pio0-4 */
348 .udma_mask = 0x7f, /* udma0-6 */
20f733e7
BR		 349 .port_ops = &mv_ops,
350 },
351};
352
353static struct pci_device_id mv_pci_tbl[] = {
354 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5040), 0, 0, chip_504x},
355 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5041), 0, 0, chip_504x},
356 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5080), 0, 0, chip_508x},
357 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5081), 0, 0, chip_508x},
358
359 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6040), 0, 0, chip_604x},
360 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6041), 0, 0, chip_604x},
361 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6080), 0, 0, chip_608x},
362 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6081), 0, 0, chip_608x},
363 {} /* terminate list */
364};
365
366static struct pci_driver mv_pci_driver = {
367 .name = DRV_NAME,
368 .id_table = mv_pci_tbl,
369 .probe = mv_init_one,
370 .remove = ata_pci_remove_one,
371};
372
373/*
374 * Functions
375 */
376
377static inline void writelfl(unsigned long data, void __iomem *addr)
378{
379 writel(data, addr);
380 (void) readl(addr); /* flush to avoid PCI posted write */
381}
382
20f733e7
BR		 383static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
384{
385 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
386}
387
388static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
389{
390 return (mv_hc_base(base, port >> MV_PORT_HC_SHIFT) +
391 MV_SATAHC_ARBTR_REG_SZ +
392 ((port & MV_PORT_MASK) * MV_PORT_REG_SZ));
393}
394
395static inline void __iomem *mv_ap_base(struct ata_port *ap)
396{
397 return mv_port_base(ap->host_set->mmio_base, ap->port_no);
398}
399
31961943
BR		 400static inline int mv_get_hc_count(unsigned long hp_flags)
401{
402 return ((hp_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
403}
404
405static void mv_irq_clear(struct ata_port *ap)
20f733e7 406{
20f733e7
BR		 407}
408
afb0edd9 409static void mv_start_dma(void __iomem *base, struct mv_port_priv *pp)
20f733e7 410{
afb0edd9
BR		 411 if (!(MV_PP_FLAG_EDMA_EN & pp->pp_flags)) {
412 writelfl(EDMA_EN, base + EDMA_CMD_OFS);
413 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
414 }
415 assert(EDMA_EN & readl(base + EDMA_CMD_OFS));
20f733e7
BR		 416}
417
31961943 418static void mv_stop_dma(struct ata_port *ap)
20f733e7 419{
31961943
BR		 420 void __iomem *port_mmio = mv_ap_base(ap);
421 struct mv_port_priv *pp = ap->private_data;
31961943
BR		 422 u32 reg;
423 int i;
424
afb0edd9
BR		 425 if (MV_PP_FLAG_EDMA_EN & pp->pp_flags) {
426 /* Disable EDMA if active. The disable bit auto clears.
31961943 427 */
31961943
BR		 428 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
429 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
afb0edd9
BR		 430 } else {
431 assert(!(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS)));
432 }
31961943
BR		 433
434 /* now properly wait for the eDMA to stop */
435 for (i = 1000; i > 0; i--) {
436 reg = readl(port_mmio + EDMA_CMD_OFS);
437 if (!(EDMA_EN & reg)) {
438 break;
439 }
440 udelay(100);
441 }
442
31961943
BR		 443 if (EDMA_EN & reg) {
444 printk(KERN_ERR "ata%u: Unable to stop eDMA\n", ap->id);
afb0edd9 445 /* FIXME: Consider doing a reset here to recover */
31961943 446 }
20f733e7
BR		 447}
448
31961943 449static void mv_dump_mem(void __iomem *start, unsigned bytes)
20f733e7 450{
31961943
BR		 451#ifdef ATA_DEBUG
452 int b, w;
453 for (b = 0; b < bytes; ) {
454 DPRINTK("%p: ", start + b);
455 for (w = 0; b < bytes && w < 4; w++) {
456 printk("%08x ",readl(start + b));
457 b += sizeof(u32);
458 }
459 printk("\n");
460 }
461#endif
462}
463static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
464{
465#ifdef ATA_DEBUG
466 int b, w;
467 u32 dw;
468 for (b = 0; b < bytes; ) {
469 DPRINTK("%02x: ", b);
470 for (w = 0; b < bytes && w < 4; w++) {
471 (void) pci_read_config_dword(pdev,b,&dw);
472 printk("%08x ",dw);
473 b += sizeof(u32);
474 }
475 printk("\n");
476 }
477#endif
478}
479static void mv_dump_all_regs(void __iomem *mmio_base, int port,
480 struct pci_dev *pdev)
481{
482#ifdef ATA_DEBUG
483 void __iomem *hc_base = mv_hc_base(mmio_base,
484 port >> MV_PORT_HC_SHIFT);
485 void __iomem *port_base;
486 int start_port, num_ports, p, start_hc, num_hcs, hc;
487
488 if (0 > port) {
489 start_hc = start_port = 0;
490 num_ports = 8; /* shld be benign for 4 port devs */
491 num_hcs = 2;
492 } else {
493 start_hc = port >> MV_PORT_HC_SHIFT;
494 start_port = port;
495 num_ports = num_hcs = 1;
496 }
497 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
498 num_ports > 1 ? num_ports - 1 : start_port);
499
500 if (NULL != pdev) {
501 DPRINTK("PCI config space regs:\n");
502 mv_dump_pci_cfg(pdev, 0x68);
503 }
504 DPRINTK("PCI regs:\n");
505 mv_dump_mem(mmio_base+0xc00, 0x3c);
506 mv_dump_mem(mmio_base+0xd00, 0x34);
507 mv_dump_mem(mmio_base+0xf00, 0x4);
508 mv_dump_mem(mmio_base+0x1d00, 0x6c);
509 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
510 hc_base = mv_hc_base(mmio_base, port >> MV_PORT_HC_SHIFT);
511 DPRINTK("HC regs (HC %i):\n", hc);
512 mv_dump_mem(hc_base, 0x1c);
513 }
514 for (p = start_port; p < start_port + num_ports; p++) {
515 port_base = mv_port_base(mmio_base, p);
516 DPRINTK("EDMA regs (port %i):\n",p);
517 mv_dump_mem(port_base, 0x54);
518 DPRINTK("SATA regs (port %i):\n",p);
519 mv_dump_mem(port_base+0x300, 0x60);
520 }
521#endif
20f733e7
BR		 522}
523
524static unsigned int mv_scr_offset(unsigned int sc_reg_in)
525{
526 unsigned int ofs;
527
528 switch (sc_reg_in) {
529 case SCR_STATUS:
530 case SCR_CONTROL:
531 case SCR_ERROR:
532 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
533 break;
534 case SCR_ACTIVE:
535 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
536 break;
537 default:
538 ofs = 0xffffffffU;
539 break;
540 }
541 return ofs;
542}
543
544static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
545{
546 unsigned int ofs = mv_scr_offset(sc_reg_in);
547
548 if (0xffffffffU != ofs) {
549 return readl(mv_ap_base(ap) + ofs);
550 } else {
551 return (u32) ofs;
552 }
553}
554
555static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
556{
557 unsigned int ofs = mv_scr_offset(sc_reg_in);
558
559 if (0xffffffffU != ofs) {
560 writelfl(val, mv_ap_base(ap) + ofs);
561 }
562}
563
31961943
BR		 564/* This routine only applies to 6xxx parts */
565static int mv_global_soft_reset(void __iomem *mmio_base)
20f733e7
BR		 566{
567 void __iomem *reg = mmio_base + PCI_MAIN_CMD_STS_OFS;
568 int i, rc = 0;
569 u32 t;
570
20f733e7
BR		 571 /* Following procedure defined in PCI "main command and status
572 * register" table.
573 */
574 t = readl(reg);
575 writel(t | STOP_PCI_MASTER, reg);
576
31961943
BR		 577 for (i = 0; i < 1000; i++) {
578 udelay(1);
20f733e7
BR		 579 t = readl(reg);
580 if (PCI_MASTER_EMPTY & t) {
581 break;
582 }
583 }
584 if (!(PCI_MASTER_EMPTY & t)) {
31961943
BR		 585 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
586 rc = 1;
20f733e7
BR		 587 goto done;
588 }
589
590 /* set reset */
591 i = 5;
592 do {
593 writel(t | GLOB_SFT_RST, reg);
594 t = readl(reg);
595 udelay(1);
596 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
597
598 if (!(GLOB_SFT_RST & t)) {
31961943
BR		 599 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
600 rc = 1;
20f733e7
BR		 601 goto done;
602 }
603
31961943 604 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
20f733e7
BR		 605 i = 5;
606 do {
31961943 607 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
20f733e7
BR		 608 t = readl(reg);
609 udelay(1);
610 } while ((GLOB_SFT_RST & t) && (i-- > 0));
611
612 if (GLOB_SFT_RST & t) {
31961943
BR		 613 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
614 rc = 1;
20f733e7 615 }
31961943 616done:
20f733e7
BR		 617 return rc;
618}
619
31961943 620static void mv_host_stop(struct ata_host_set *host_set)
20f733e7 621{
31961943
BR		 622 struct mv_host_priv *hpriv = host_set->private_data;
623 struct pci_dev *pdev = to_pci_dev(host_set->dev);
624
625 if (hpriv->hp_flags & MV_HP_FLAG_MSI) {
626 pci_disable_msi(pdev);
627 } else {
628 pci_intx(pdev, 0);
629 }
630 kfree(hpriv);
631 ata_host_stop(host_set);
632}
633
634static int mv_port_start(struct ata_port *ap)
635{
636 struct device *dev = ap->host_set->dev;
637 struct mv_port_priv *pp;
638 void __iomem *port_mmio = mv_ap_base(ap);
639 void *mem;
640 dma_addr_t mem_dma;
641
642 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
643 if (!pp) {
644 return -ENOMEM;
645 }
646 memset(pp, 0, sizeof(*pp));
647
648 mem = dma_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma,
649 GFP_KERNEL);
650 if (!mem) {
651 kfree(pp);
652 return -ENOMEM;
653 }
654 memset(mem, 0, MV_PORT_PRIV_DMA_SZ);
655
656 /* First item in chunk of DMA memory:
657 * 32-slot command request table (CRQB), 32 bytes each in size
658 */
659 pp->crqb = mem;
660 pp->crqb_dma = mem_dma;
661 mem += MV_CRQB_Q_SZ;
662 mem_dma += MV_CRQB_Q_SZ;
663
664 /* Second item:
665 * 32-slot command response table (CRPB), 8 bytes each in size
666 */
667 pp->crpb = mem;
668 pp->crpb_dma = mem_dma;
669 mem += MV_CRPB_Q_SZ;
670 mem_dma += MV_CRPB_Q_SZ;
671
672 /* Third item:
673 * Table of scatter-gather descriptors (ePRD), 16 bytes each
674 */
675 pp->sg_tbl = mem;
676 pp->sg_tbl_dma = mem_dma;
677
678 writelfl(EDMA_CFG_Q_DEPTH | EDMA_CFG_RD_BRST_EXT |
679 EDMA_CFG_WR_BUFF_LEN, port_mmio + EDMA_CFG_OFS);
680
681 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
682 writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK,
683 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
684
685 writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
686 writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
687
688 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
689 writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK,
690 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
691
692 pp->req_producer = pp->rsp_consumer = 0;
693
694 /* Don't turn on EDMA here...do it before DMA commands only. Else
695 * we'll be unable to send non-data, PIO, etc due to restricted access
696 * to shadow regs.
697 */
698 ap->private_data = pp;
699 return 0;
700}
701
702static void mv_port_stop(struct ata_port *ap)
703{
704 struct device *dev = ap->host_set->dev;
705 struct mv_port_priv *pp = ap->private_data;
afb0edd9 706 unsigned long flags;
31961943 707
afb0edd9 708 spin_lock_irqsave(&ap->host_set->lock, flags);
31961943 709 mv_stop_dma(ap);
afb0edd9 710 spin_unlock_irqrestore(&ap->host_set->lock, flags);
31961943
BR		 711
712 ap->private_data = NULL;
713 dma_free_coherent(dev, MV_PORT_PRIV_DMA_SZ, pp->crpb, pp->crpb_dma);
714 kfree(pp);
715}
716
717static void mv_fill_sg(struct ata_queued_cmd *qc)
718{
719 struct mv_port_priv *pp = qc->ap->private_data;
720 unsigned int i;
721
722 for (i = 0; i < qc->n_elem; i++) {
723 u32 sg_len;
724 dma_addr_t addr;
725
726 addr = sg_dma_address(&qc->sg[i]);
727 sg_len = sg_dma_len(&qc->sg[i]);
728
729 pp->sg_tbl[i].addr = cpu_to_le32(addr & 0xffffffff);
730 pp->sg_tbl[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
731 assert(0 == (sg_len & ~MV_DMA_BOUNDARY));
732 pp->sg_tbl[i].flags_size = cpu_to_le32(sg_len);
733 }
734 if (0 < qc->n_elem) {
735 pp->sg_tbl[qc->n_elem - 1].flags_size |= EPRD_FLAG_END_OF_TBL;
736 }
737}
738
739static inline unsigned mv_inc_q_index(unsigned *index)
740{
741 *index = (*index + 1) & MV_MAX_Q_DEPTH_MASK;
742 return *index;
743}
744
745static inline void mv_crqb_pack_cmd(u16 *cmdw, u8 data, u8 addr, unsigned last)
746{
747 *cmdw = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
748 (last ? CRQB_CMD_LAST : 0);
749}
750
751static void mv_qc_prep(struct ata_queued_cmd *qc)
752{
753 struct ata_port *ap = qc->ap;
754 struct mv_port_priv *pp = ap->private_data;
755 u16 *cw;
756 struct ata_taskfile *tf;
757 u16 flags = 0;
758
759 if (ATA_PROT_DMA != qc->tf.protocol) {
760 return;
761 }
20f733e7 762
31961943
BR		 763 /* the req producer index should be the same as we remember it */
764 assert(((readl(mv_ap_base(qc->ap) + EDMA_REQ_Q_IN_PTR_OFS) >>
765 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
766 pp->req_producer);
767
768 /* Fill in command request block
769 */
770 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
771 flags |= CRQB_FLAG_READ;
772 }
773 assert(MV_MAX_Q_DEPTH > qc->tag);
774 flags |= qc->tag << CRQB_TAG_SHIFT;
775
776 pp->crqb[pp->req_producer].sg_addr =
777 cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
778 pp->crqb[pp->req_producer].sg_addr_hi =
779 cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
780 pp->crqb[pp->req_producer].ctrl_flags = cpu_to_le16(flags);
781
782 cw = &pp->crqb[pp->req_producer].ata_cmd[0];
783 tf = &qc->tf;
784
785 /* Sadly, the CRQB cannot accomodate all registers--there are
786 * only 11 bytes...so we must pick and choose required
787 * registers based on the command. So, we drop feature and
788 * hob_feature for [RW] DMA commands, but they are needed for
789 * NCQ. NCQ will drop hob_nsect.
20f733e7 790 */
31961943
BR		 791 switch (tf->command) {
792 case ATA_CMD_READ:
793 case ATA_CMD_READ_EXT:
794 case ATA_CMD_WRITE:
795 case ATA_CMD_WRITE_EXT:
796 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
797 break;
798#ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */
799 case ATA_CMD_FPDMA_READ:
800 case ATA_CMD_FPDMA_WRITE:
801 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
802 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
803 break;
804#endif /* FIXME: remove this line when NCQ added */
805 default:
806 /* The only other commands EDMA supports in non-queued and
807 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
808 * of which are defined/used by Linux. If we get here, this
809 * driver needs work.
810 *
811 * FIXME: modify libata to give qc_prep a return value and
812 * return error here.
813 */
814 BUG_ON(tf->command);
815 break;
816 }
817 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
818 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
819 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
820 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
821 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
822 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
823 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
824 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
825 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
826
827 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) {
828 return;
829 }
830 mv_fill_sg(qc);
831}
832
833static int mv_qc_issue(struct ata_queued_cmd *qc)
834{
835 void __iomem *port_mmio = mv_ap_base(qc->ap);
836 struct mv_port_priv *pp = qc->ap->private_data;
837 u32 in_ptr;
838
839 if (ATA_PROT_DMA != qc->tf.protocol) {
840 /* We're about to send a non-EDMA capable command to the
841 * port. Turn off EDMA so there won't be problems accessing
842 * shadow block, etc registers.
843 */
844 mv_stop_dma(qc->ap);
845 return ata_qc_issue_prot(qc);
846 }
847
848 in_ptr = readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
849
850 /* the req producer index should be the same as we remember it */
851 assert(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
852 pp->req_producer);
853 /* until we do queuing, the queue should be empty at this point */
854 assert(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
855 ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS) >>
856 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
857
858 mv_inc_q_index(&pp->req_producer); /* now incr producer index */
859
afb0edd9 860 mv_start_dma(port_mmio, pp);
31961943
BR		 861
862 /* and write the request in pointer to kick the EDMA to life */
863 in_ptr &= EDMA_REQ_Q_BASE_LO_MASK;
864 in_ptr |= pp->req_producer << EDMA_REQ_Q_PTR_SHIFT;
865 writelfl(in_ptr, port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
866
867 return 0;
868}
869
870static u8 mv_get_crpb_status(struct ata_port *ap)
871{
872 void __iomem *port_mmio = mv_ap_base(ap);
873 struct mv_port_priv *pp = ap->private_data;
874 u32 out_ptr;
875
876 out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
877
878 /* the response consumer index should be the same as we remember it */
879 assert(((out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
880 pp->rsp_consumer);
881
882 /* increment our consumer index... */
883 pp->rsp_consumer = mv_inc_q_index(&pp->rsp_consumer);
884
885 /* and, until we do NCQ, there should only be 1 CRPB waiting */
886 assert(((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) >>
887 EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
888 pp->rsp_consumer);
889
890 /* write out our inc'd consumer index so EDMA knows we're caught up */
891 out_ptr &= EDMA_RSP_Q_BASE_LO_MASK;
892 out_ptr |= pp->rsp_consumer << EDMA_RSP_Q_PTR_SHIFT;
893 writelfl(out_ptr, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
894
895 /* Return ATA status register for completed CRPB */
896 return (pp->crpb[pp->rsp_consumer].flags >> CRPB_FLAG_STATUS_SHIFT);
897}
898
899static void mv_err_intr(struct ata_port *ap)
900{
901 void __iomem *port_mmio = mv_ap_base(ap);
902 u32 edma_err_cause, serr = 0;
20f733e7
BR		 903
904 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
905
906 if (EDMA_ERR_SERR & edma_err_cause) {
907 serr = scr_read(ap, SCR_ERROR);
908 scr_write_flush(ap, SCR_ERROR, serr);
909 }
afb0edd9
BR		 910 if (EDMA_ERR_SELF_DIS & edma_err_cause) {
911 struct mv_port_priv *pp = ap->private_data;
912 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
913 }
914 DPRINTK(KERN_ERR "ata%u: port error; EDMA err cause: 0x%08x "
915 "SERR: 0x%08x\n", ap->id, edma_err_cause, serr);
20f733e7
BR		 916
917 /* Clear EDMA now that SERR cleanup done */
918 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
919
920 /* check for fatal here and recover if needed */
921 if (EDMA_ERR_FATAL & edma_err_cause) {
922 mv_phy_reset(ap);
923 }
924}
925
31961943 926/* Handle any outstanding interrupts in a single SATAHC */
20f733e7
BR		 927static void mv_host_intr(struct ata_host_set *host_set, u32 relevant,
928 unsigned int hc)
929{
930 void __iomem *mmio = host_set->mmio_base;
931 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
932 struct ata_port *ap;
933 struct ata_queued_cmd *qc;
934 u32 hc_irq_cause;
31961943
BR		 935 int shift, port, port0, hard_port, handled;
936 u8 ata_status = 0;
20f733e7
BR		 937
938 if (hc == 0) {
939 port0 = 0;
940 } else {
941 port0 = MV_PORTS_PER_HC;
942 }
943
944 /* we'll need the HC success int register in most cases */
945 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
946 if (hc_irq_cause) {
31961943 947 writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
20f733e7
BR		 948 }
949
950 VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n",
951 hc,relevant,hc_irq_cause);
952
953 for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) {
954 ap = host_set->ports[port];
955 hard_port = port & MV_PORT_MASK; /* range 0-3 */
31961943 956 handled = 0; /* ensure ata_status is set if handled++ */
20f733e7 957
31961943
BR		 958 if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) {
959 /* new CRPB on the queue; just one at a time until NCQ
960 */
961 ata_status = mv_get_crpb_status(ap);
962 handled++;
963 } else if ((DEV_IRQ << hard_port) & hc_irq_cause) {
964 /* received ATA IRQ; read the status reg to clear INTRQ
20f733e7
BR		 965 */
966 ata_status = readb((void __iomem *)
967 ap->ioaddr.status_addr);
31961943 968 handled++;
20f733e7
BR		 969 }
970
31961943 971 shift = port << 1; /* (port * 2) */
20f733e7
BR		 972 if (port >= MV_PORTS_PER_HC) {
973 shift++; /* skip bit 8 in the HC Main IRQ reg */
974 }
975 if ((PORT0_ERR << shift) & relevant) {
976 mv_err_intr(ap);
31961943 977 /* OR in ATA_ERR to ensure libata knows we took one */
20f733e7
BR		 978 ata_status = readb((void __iomem *)
979 ap->ioaddr.status_addr) | ATA_ERR;
31961943 980 handled++;
20f733e7
BR		 981 }
982
31961943 983 if (handled && ap) {
20f733e7
BR		 984 qc = ata_qc_from_tag(ap, ap->active_tag);
985 if (NULL != qc) {
986 VPRINTK("port %u IRQ found for qc, "
987 "ata_status 0x%x\n", port,ata_status);
20f733e7
BR		 988 /* mark qc status appropriately */
989 ata_qc_complete(qc, ata_status);
990 }
991 }
992 }
993 VPRINTK("EXIT\n");
994}
995
996static irqreturn_t mv_interrupt(int irq, void *dev_instance,
997 struct pt_regs *regs)
998{
999 struct ata_host_set *host_set = dev_instance;
1000 unsigned int hc, handled = 0, n_hcs;
31961943 1001 void __iomem *mmio = host_set->mmio_base;
20f733e7
BR		 1002 u32 irq_stat;
1003
20f733e7 1004 irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS);
20f733e7
BR		 1005
1006 /* check the cases where we either have nothing pending or have read
1007 * a bogus register value which can indicate HW removal or PCI fault
1008 */
1009 if (!irq_stat || (0xffffffffU == irq_stat)) {
1010 return IRQ_NONE;
1011 }
1012
31961943 1013 n_hcs = mv_get_hc_count(host_set->ports[0]->flags);
20f733e7
BR		 1014 spin_lock(&host_set->lock);
1015
1016 for (hc = 0; hc < n_hcs; hc++) {
1017 u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT));
1018 if (relevant) {
1019 mv_host_intr(host_set, relevant, hc);
31961943 1020 handled++;
20f733e7
BR		 1021 }
1022 }
1023 if (PCI_ERR & irq_stat) {
31961943
BR		 1024 printk(KERN_ERR DRV_NAME ": PCI ERROR; PCI IRQ cause=0x%08x\n",
1025 readl(mmio + PCI_IRQ_CAUSE_OFS));
1026
afb0edd9 1027 DPRINTK("All regs @ PCI error\n");
31961943 1028 mv_dump_all_regs(mmio, -1, to_pci_dev(host_set->dev));
20f733e7 1029
31961943
BR		 1030 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
1031 handled++;
1032 }
20f733e7
BR		 1033 spin_unlock(&host_set->lock);
1034
1035 return IRQ_RETVAL(handled);
1036}
1037
31961943
BR		 1038static u8 mv_check_err(struct ata_port *ap)
1039{
1040 mv_stop_dma(ap); /* can't read shadow regs if DMA on */
1041 return readb((void __iomem *) ap->ioaddr.error_addr);
1042}
1043
1044/* Part of this is taken from __sata_phy_reset and modified to not sleep
1045 * since this routine gets called from interrupt level.
1046 */
20f733e7
BR		 1047static void mv_phy_reset(struct ata_port *ap)
1048{
1049 void __iomem *port_mmio = mv_ap_base(ap);
1050 struct ata_taskfile tf;
1051 struct ata_device *dev = &ap->device[0];
31961943 1052 unsigned long timeout;
20f733e7
BR		 1053
1054 VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);
1055
31961943 1056 mv_stop_dma(ap);
20f733e7 1057
31961943 1058 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
20f733e7
BR		 1059 udelay(25); /* allow reset propagation */
1060
1061 /* Spec never mentions clearing the bit. Marvell's driver does
1062 * clear the bit, however.
1063 */
31961943 1064 writelfl(0, port_mmio + EDMA_CMD_OFS);
20f733e7 1065
31961943
BR		 1066 VPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
1067 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1068 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
20f733e7
BR		 1069
1070 /* proceed to init communications via the scr_control reg */
31961943
BR		 1071 scr_write_flush(ap, SCR_CONTROL, 0x301);
1072 mdelay(1);
1073 scr_write_flush(ap, SCR_CONTROL, 0x300);
1074 timeout = jiffies + (HZ * 1);
1075 do {
1076 mdelay(10);
1077 if ((scr_read(ap, SCR_STATUS) & 0xf) != 1)
1078 break;
1079 } while (time_before(jiffies, timeout));
20f733e7 1080
31961943
BR		 1081 VPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
1082 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1083 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1084
1085 if (sata_dev_present(ap)) {
1086 ata_port_probe(ap);
1087 } else {
1088 printk(KERN_INFO "ata%u: no device found (phy stat %08x)\n",
1089 ap->id, scr_read(ap, SCR_STATUS));
1090 ata_port_disable(ap);
20f733e7
BR		 1091 return;
1092 }
31961943 1093 ap->cbl = ATA_CBL_SATA;
20f733e7
BR		 1094
1095 tf.lbah = readb((void __iomem *) ap->ioaddr.lbah_addr);
1096 tf.lbam = readb((void __iomem *) ap->ioaddr.lbam_addr);
1097 tf.lbal = readb((void __iomem *) ap->ioaddr.lbal_addr);
1098 tf.nsect = readb((void __iomem *) ap->ioaddr.nsect_addr);
1099
1100 dev->class = ata_dev_classify(&tf);
1101 if (!ata_dev_present(dev)) {
1102 VPRINTK("Port disabled post-sig: No device present.\n");
1103 ata_port_disable(ap);
1104 }
1105 VPRINTK("EXIT\n");
1106}
1107
31961943
BR		 1108static void mv_eng_timeout(struct ata_port *ap)
1109{
1110 struct ata_queued_cmd *qc;
1111 unsigned long flags;
1112
1113 printk(KERN_ERR "ata%u: Entering mv_eng_timeout\n",ap->id);
1114 DPRINTK("All regs @ start of eng_timeout\n");
1115 mv_dump_all_regs(ap->host_set->mmio_base, ap->port_no,
1116 to_pci_dev(ap->host_set->dev));
1117
1118 qc = ata_qc_from_tag(ap, ap->active_tag);
1119 printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n",
1120 ap->host_set->mmio_base, ap, qc, qc->scsicmd,
1121 &qc->scsicmd->cmnd);
1122
1123 mv_err_intr(ap);
1124 mv_phy_reset(ap);
1125
1126 if (!qc) {
1127 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
1128 ap->id);
1129 } else {
1130 /* hack alert! We cannot use the supplied completion
1131 * function from inside the ->eh_strategy_handler() thread.
1132 * libata is the only user of ->eh_strategy_handler() in
1133 * any kernel, so the default scsi_done() assumes it is
1134 * not being called from the SCSI EH.
1135 */
1136 spin_lock_irqsave(&ap->host_set->lock, flags);
1137 qc->scsidone = scsi_finish_command;
1138 ata_qc_complete(qc, ATA_ERR);
1139 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1140 }
1141}
1142
1143static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
20f733e7 1144{
31961943
BR		 1145 unsigned long shd_base = (unsigned long) port_mmio + SHD_BLK_OFS;
1146 unsigned serr_ofs;
1147
1148 /* PIO related setup
1149 */
1150 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
1151 port->error_addr =
1152 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
1153 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
1154 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
1155 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
1156 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
1157 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
1158 port->status_addr =
1159 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
1160 /* special case: control/altstatus doesn't have ATA_REG_ address */
1161 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
1162
1163 /* unused: */
20f733e7
BR		 1164 port->cmd_addr = port->bmdma_addr = port->scr_addr = 0;
1165
31961943
BR		 1166 /* Clear any currently outstanding port interrupt conditions */
1167 serr_ofs = mv_scr_offset(SCR_ERROR);
1168 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
1169 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1170
20f733e7 1171 /* unmask all EDMA error interrupts */
31961943 1172 writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
20f733e7
BR		 1173
1174 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
31961943
BR		 1175 readl(port_mmio + EDMA_CFG_OFS),
1176 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
1177 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
20f733e7
BR		 1178}
1179
1180static int mv_host_init(struct ata_probe_ent *probe_ent)
1181{
1182 int rc = 0, n_hc, port, hc;
1183 void __iomem *mmio = probe_ent->mmio_base;
1184 void __iomem *port_mmio;
1185
31961943
BR		 1186 if ((MV_FLAG_GLBL_SFT_RST & probe_ent->host_flags) &&
1187 mv_global_soft_reset(probe_ent->mmio_base)) {
20f733e7
BR		 1188 rc = 1;
1189 goto done;
1190 }
1191
1192 n_hc = mv_get_hc_count(probe_ent->host_flags);
1193 probe_ent->n_ports = MV_PORTS_PER_HC * n_hc;
1194
1195 for (port = 0; port < probe_ent->n_ports; port++) {
1196 port_mmio = mv_port_base(mmio, port);
31961943 1197 mv_port_init(&probe_ent->port[port], port_mmio);
20f733e7
BR		 1198 }
1199
1200 for (hc = 0; hc < n_hc; hc++) {
31961943
BR		 1201 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1202
1203 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
1204 "(before clear)=0x%08x\n", hc,
1205 readl(hc_mmio + HC_CFG_OFS),
1206 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
1207
1208 /* Clear any currently outstanding hc interrupt conditions */
1209 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
20f733e7
BR		 1210 }
1211
31961943
BR		 1212 /* Clear any currently outstanding host interrupt conditions */
1213 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
1214
1215 /* and unmask interrupt generation for host regs */
1216 writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS);
1217 writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS);
20f733e7
BR		 1218
1219 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
1220 "PCI int cause/mask=0x%08x/0x%08x\n",
1221 readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
1222 readl(mmio + HC_MAIN_IRQ_MASK_OFS),
1223 readl(mmio + PCI_IRQ_CAUSE_OFS),
1224 readl(mmio + PCI_IRQ_MASK_OFS));
31961943 1225done:
20f733e7
BR		 1226 return rc;
1227}
1228
31961943
BR		 1229/* FIXME: complete this */
1230static void mv_print_info(struct ata_probe_ent *probe_ent)
1231{
1232 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1233 struct mv_host_priv *hpriv = probe_ent->private_data;
1234 u8 rev_id, scc;
1235 const char *scc_s;
1236
1237 /* Use this to determine the HW stepping of the chip so we know
1238 * what errata to workaround
1239 */
1240 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1241
1242 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
1243 if (scc == 0)
1244 scc_s = "SCSI";
1245 else if (scc == 0x01)
1246 scc_s = "RAID";
1247 else
1248 scc_s = "unknown";
1249
1250 printk(KERN_INFO DRV_NAME
1251 "(%s) %u slots %u ports %s mode IRQ via %s\n",
1252 pci_name(pdev), (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports,
1253 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
1254}
1255
20f733e7
BR		 1256static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1257{
1258 static int printed_version = 0;
1259 struct ata_probe_ent *probe_ent = NULL;
1260 struct mv_host_priv *hpriv;
1261 unsigned int board_idx = (unsigned int)ent->driver_data;
1262 void __iomem *mmio_base;
31961943 1263 int pci_dev_busy = 0, rc;
20f733e7
BR		 1264
1265 if (!printed_version++) {
31961943 1266 printk(KERN_INFO DRV_NAME " version " DRV_VERSION "\n");
20f733e7
BR		 1267 }
1268
20f733e7
BR		 1269 rc = pci_enable_device(pdev);
1270 if (rc) {
1271 return rc;
1272 }
1273
1274 rc = pci_request_regions(pdev, DRV_NAME);
1275 if (rc) {
1276 pci_dev_busy = 1;
1277 goto err_out;
1278 }
1279
20f733e7
BR		 1280 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1281 if (probe_ent == NULL) {
1282 rc = -ENOMEM;
1283 goto err_out_regions;
1284 }
1285
1286 memset(probe_ent, 0, sizeof(*probe_ent));
1287 probe_ent->dev = pci_dev_to_dev(pdev);
1288 INIT_LIST_HEAD(&probe_ent->node);
1289
31961943 1290 mmio_base = pci_iomap(pdev, MV_PRIMARY_BAR, 0);
20f733e7
BR		 1291 if (mmio_base == NULL) {
1292 rc = -ENOMEM;
1293 goto err_out_free_ent;
1294 }
1295
1296 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1297 if (!hpriv) {
1298 rc = -ENOMEM;
1299 goto err_out_iounmap;
1300 }
1301 memset(hpriv, 0, sizeof(*hpriv));
1302
1303 probe_ent->sht = mv_port_info[board_idx].sht;
1304 probe_ent->host_flags = mv_port_info[board_idx].host_flags;
1305 probe_ent->pio_mask = mv_port_info[board_idx].pio_mask;
1306 probe_ent->udma_mask = mv_port_info[board_idx].udma_mask;
1307 probe_ent->port_ops = mv_port_info[board_idx].port_ops;
1308
1309 probe_ent->irq = pdev->irq;
1310 probe_ent->irq_flags = SA_SHIRQ;
1311 probe_ent->mmio_base = mmio_base;
1312 probe_ent->private_data = hpriv;
1313
1314 /* initialize adapter */
1315 rc = mv_host_init(probe_ent);
1316 if (rc) {
1317 goto err_out_hpriv;
1318 }
20f733e7 1319
31961943
BR		 1320 /* Enable interrupts */
1321 if (pci_enable_msi(pdev) == 0) {
1322 hpriv->hp_flags |= MV_HP_FLAG_MSI;
1323 } else {
1324 pci_intx(pdev, 1);
20f733e7
BR		 1325 }
1326
31961943
BR		 1327 mv_dump_pci_cfg(pdev, 0x68);
1328 mv_print_info(probe_ent);
1329
1330 if (ata_device_add(probe_ent) == 0) {
1331 rc = -ENODEV; /* No devices discovered */
1332 goto err_out_dev_add;
1333 }
20f733e7 1334
31961943 1335 kfree(probe_ent);
20f733e7
BR		 1336 return 0;
1337
31961943
BR		 1338err_out_dev_add:
1339 if (MV_HP_FLAG_MSI & hpriv->hp_flags) {
1340 pci_disable_msi(pdev);
1341 } else {
1342 pci_intx(pdev, 0);
1343 }
1344err_out_hpriv:
20f733e7 1345 kfree(hpriv);
31961943
BR		 1346err_out_iounmap:
1347 pci_iounmap(pdev, mmio_base);
1348err_out_free_ent:
20f733e7 1349 kfree(probe_ent);
31961943 1350err_out_regions:
20f733e7 1351 pci_release_regions(pdev);
31961943 1352err_out:
20f733e7
BR		 1353 if (!pci_dev_busy) {
1354 pci_disable_device(pdev);
1355 }
1356
1357 return rc;
1358}
1359
1360static int __init mv_init(void)
1361{
1362 return pci_module_init(&mv_pci_driver);
1363}
1364
1365static void __exit mv_exit(void)
1366{
1367 pci_unregister_driver(&mv_pci_driver);
1368}
1369
1370MODULE_AUTHOR("Brett Russ");
1371MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
1372MODULE_LICENSE("GPL");
1373MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
1374MODULE_VERSION(DRV_VERSION);
1375
1376module_init(mv_init);
1377module_exit(mv_exit);
Linux kernel - Deliverables
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