[deliverable/linux.git] / drivers / scsi / sata_nv.c

/*
 *  sata_nv.c - NVIDIA nForce SATA
 *
 *  Copyright 2004 NVIDIA Corp.  All rights reserved.
 *  Copyright 2004 Andrew Chew
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *  No hardware documentation available outside of NVIDIA.
 *  This driver programs the NVIDIA SATA controller in a similar
 *  fashion as with other PCI IDE BMDMA controllers, with a few
 *  NV-specific details such as register offsets, SATA phy location,
 *  hotplug info, etc.
 *
 */

#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME			"sata_nv"
#define DRV_VERSION			"0.9"

enum {
	NV_PORTS			= 2,
	NV_PIO_MASK			= 0x1f,
	NV_MWDMA_MASK			= 0x07,
	NV_UDMA_MASK			= 0x7f,
	NV_PORT0_SCR_REG_OFFSET		= 0x00,
	NV_PORT1_SCR_REG_OFFSET		= 0x40,

	NV_INT_STATUS			= 0x10,
	NV_INT_STATUS_CK804		= 0x440,
	NV_INT_STATUS_PDEV_INT		= 0x01,
	NV_INT_STATUS_PDEV_PM		= 0x02,
	NV_INT_STATUS_PDEV_ADDED	= 0x04,
	NV_INT_STATUS_PDEV_REMOVED	= 0x08,
	NV_INT_STATUS_SDEV_INT		= 0x10,
	NV_INT_STATUS_SDEV_PM		= 0x20,
	NV_INT_STATUS_SDEV_ADDED	= 0x40,
	NV_INT_STATUS_SDEV_REMOVED	= 0x80,
	NV_INT_STATUS_PDEV_HOTPLUG	= (NV_INT_STATUS_PDEV_ADDED |
					   NV_INT_STATUS_PDEV_REMOVED),
	NV_INT_STATUS_SDEV_HOTPLUG	= (NV_INT_STATUS_SDEV_ADDED |
					   NV_INT_STATUS_SDEV_REMOVED),
	NV_INT_STATUS_HOTPLUG		= (NV_INT_STATUS_PDEV_HOTPLUG |
					   NV_INT_STATUS_SDEV_HOTPLUG),

	NV_INT_ENABLE			= 0x11,
	NV_INT_ENABLE_CK804		= 0x441,
	NV_INT_ENABLE_PDEV_MASK		= 0x01,
	NV_INT_ENABLE_PDEV_PM		= 0x02,
	NV_INT_ENABLE_PDEV_ADDED	= 0x04,
	NV_INT_ENABLE_PDEV_REMOVED	= 0x08,
	NV_INT_ENABLE_SDEV_MASK		= 0x10,
	NV_INT_ENABLE_SDEV_PM		= 0x20,
	NV_INT_ENABLE_SDEV_ADDED	= 0x40,
	NV_INT_ENABLE_SDEV_REMOVED	= 0x80,
	NV_INT_ENABLE_PDEV_HOTPLUG	= (NV_INT_ENABLE_PDEV_ADDED |
					   NV_INT_ENABLE_PDEV_REMOVED),
	NV_INT_ENABLE_SDEV_HOTPLUG	= (NV_INT_ENABLE_SDEV_ADDED |
					   NV_INT_ENABLE_SDEV_REMOVED),
	NV_INT_ENABLE_HOTPLUG		= (NV_INT_ENABLE_PDEV_HOTPLUG |
					   NV_INT_ENABLE_SDEV_HOTPLUG),

	NV_INT_CONFIG			= 0x12,
	NV_INT_CONFIG_METHD		= 0x01, // 0 = INT, 1 = SMI

	// For PCI config register 20
	NV_MCP_SATA_CFG_20		= 0x50,
	NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04,
};

static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
static irqreturn_t nv_interrupt (int irq, void *dev_instance,
				 struct pt_regs *regs);
static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg);
static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
static void nv_host_stop (struct ata_host_set *host_set);
static void nv_enable_hotplug(struct ata_probe_ent *probe_ent);
static void nv_disable_hotplug(struct ata_host_set *host_set);
static int nv_check_hotplug(struct ata_host_set *host_set);
static void nv_enable_hotplug_ck804(struct ata_probe_ent *probe_ent);
static void nv_disable_hotplug_ck804(struct ata_host_set *host_set);
static int nv_check_hotplug_ck804(struct ata_host_set *host_set);

enum nv_host_type
{
	GENERIC,
	NFORCE2,
	NFORCE3,
	CK804
};

static const struct pci_device_id nv_pci_tbl[] = {
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE2 },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
	{ PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
		PCI_ANY_ID, PCI_ANY_ID,
		PCI_CLASS_STORAGE_IDE<<8, 0xffff00, GENERIC },
	{ PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
		PCI_ANY_ID, PCI_ANY_ID,
		PCI_CLASS_STORAGE_RAID<<8, 0xffff00, GENERIC },
	{ 0, } /* terminate list */
};

struct nv_host_desc
{
	enum nv_host_type	host_type;
	void			(*enable_hotplug)(struct ata_probe_ent *probe_ent);
	void			(*disable_hotplug)(struct ata_host_set *host_set);
	int			(*check_hotplug)(struct ata_host_set *host_set);

};
static struct nv_host_desc nv_device_tbl[] = {
	{
		.host_type	= GENERIC,
		.enable_hotplug	= NULL,
		.disable_hotplug= NULL,
		.check_hotplug	= NULL,
	},
	{
		.host_type	= NFORCE2,
		.enable_hotplug	= nv_enable_hotplug,
		.disable_hotplug= nv_disable_hotplug,
		.check_hotplug	= nv_check_hotplug,
	},
	{
		.host_type	= NFORCE3,
		.enable_hotplug	= nv_enable_hotplug,
		.disable_hotplug= nv_disable_hotplug,
		.check_hotplug	= nv_check_hotplug,
	},
	{	.host_type	= CK804,
		.enable_hotplug	= nv_enable_hotplug_ck804,
		.disable_hotplug= nv_disable_hotplug_ck804,
		.check_hotplug	= nv_check_hotplug_ck804,
	},
};

struct nv_host
{
	struct nv_host_desc	*host_desc;
	unsigned long		host_flags;
};

static struct pci_driver nv_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= nv_pci_tbl,
	.probe			= nv_init_one,
	.remove			= ata_pci_remove_one,
};

static struct scsi_host_template nv_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.bios_param		= ata_std_bios_param,
};

static const struct ata_port_operations nv_ops = {
	.port_disable		= ata_port_disable,
	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.exec_command		= ata_exec_command,
	.check_status		= ata_check_status,
	.dev_select		= ata_std_dev_select,
	.phy_reset		= sata_phy_reset,
	.bmdma_setup		= ata_bmdma_setup,
	.bmdma_start		= ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
	.eng_timeout		= ata_eng_timeout,
	.irq_handler		= nv_interrupt,
	.irq_clear		= ata_bmdma_irq_clear,
	.scr_read		= nv_scr_read,
	.scr_write		= nv_scr_write,
	.port_start		= ata_port_start,
	.port_stop		= ata_port_stop,
	.host_stop		= nv_host_stop,
};

/* FIXME: The hardware provides the necessary SATA PHY controls
 * to support ATA_FLAG_SATA_RESET.  However, it is currently
 * necessary to disable that flag, to solve misdetection problems.
 * See http://bugme.osdl.org/show_bug.cgi?id=3352 for more info.
 *
 * This problem really needs to be investigated further.  But in the
 * meantime, we avoid ATA_FLAG_SATA_RESET to get people working.
 */
static struct ata_port_info nv_port_info = {
	.sht		= &nv_sht,
	.host_flags	= ATA_FLAG_SATA |
			  /* ATA_FLAG_SATA_RESET | */
			  ATA_FLAG_SRST |
			  ATA_FLAG_NO_LEGACY,
	.pio_mask	= NV_PIO_MASK,
	.mwdma_mask	= NV_MWDMA_MASK,
	.udma_mask	= NV_UDMA_MASK,
	.port_ops	= &nv_ops,
};

MODULE_AUTHOR("NVIDIA");
MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
MODULE_VERSION(DRV_VERSION);

static irqreturn_t nv_interrupt (int irq, void *dev_instance,
				 struct pt_regs *regs)
{
	struct ata_host_set *host_set = dev_instance;
	struct nv_host *host = host_set->private_data;
	unsigned int i;
	unsigned int handled = 0;
	unsigned long flags;

	spin_lock_irqsave(&host_set->lock, flags);

	for (i = 0; i < host_set->n_ports; i++) {
		struct ata_port *ap;

		ap = host_set->ports[i];
		if (ap &&
		    !(ap->flags & (ATA_FLAG_DISABLED | ATA_FLAG_NOINTR))) {
			struct ata_queued_cmd *qc;

			qc = ata_qc_from_tag(ap, ap->active_tag);
			if (qc && (!(qc->tf.ctl & ATA_NIEN)))
				handled += ata_host_intr(ap, qc);
			else
				// No request pending?  Clear interrupt status
				// anyway, in case there's one pending.
				ap->ops->check_status(ap);
		}

	}

	if (host->host_desc->check_hotplug)
		handled += host->host_desc->check_hotplug(host_set);

	spin_unlock_irqrestore(&host_set->lock, flags);

	return IRQ_RETVAL(handled);
}

static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg)
{
	if (sc_reg > SCR_CONTROL)
		return 0xffffffffU;

	return ioread32((void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
}

static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
{
	if (sc_reg > SCR_CONTROL)
		return;

	iowrite32(val, (void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
}

static void nv_host_stop (struct ata_host_set *host_set)
{
	struct nv_host *host = host_set->private_data;

	// Disable hotplug event interrupts.
	if (host->host_desc->disable_hotplug)
		host->host_desc->disable_hotplug(host_set);

	kfree(host);

	ata_pci_host_stop(host_set);
}

static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static int printed_version = 0;
	struct nv_host *host;
	struct ata_port_info *ppi;
	struct ata_probe_ent *probe_ent;
	int pci_dev_busy = 0;
	int rc;
	u32 bar;
	unsigned long base;

        // Make sure this is a SATA controller by counting the number of bars
        // (NVIDIA SATA controllers will always have six bars).  Otherwise,
        // it's an IDE controller and we ignore it.
	for (bar=0; bar<6; bar++)
		if (pci_resource_start(pdev, bar) == 0)
			return -ENODEV;

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");

	rc = pci_enable_device(pdev);
	if (rc)
		goto err_out;

	rc = pci_request_regions(pdev, DRV_NAME);
	if (rc) {
		pci_dev_busy = 1;
		goto err_out_disable;
	}

	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		goto err_out_regions;
	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		goto err_out_regions;

	rc = -ENOMEM;

	ppi = &nv_port_info;
	probe_ent = ata_pci_init_native_mode(pdev, &ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
	if (!probe_ent)
		goto err_out_regions;

	host = kmalloc(sizeof(struct nv_host), GFP_KERNEL);
	if (!host)
		goto err_out_free_ent;

	memset(host, 0, sizeof(struct nv_host));
	host->host_desc = &nv_device_tbl[ent->driver_data];

	probe_ent->private_data = host;

	probe_ent->mmio_base = pci_iomap(pdev, 5, 0);
	if (!probe_ent->mmio_base) {
		rc = -EIO;
		goto err_out_free_host;
	}

	base = (unsigned long)probe_ent->mmio_base;

	probe_ent->port[0].scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
	probe_ent->port[1].scr_addr = base + NV_PORT1_SCR_REG_OFFSET;

	pci_set_master(pdev);

	rc = ata_device_add(probe_ent);
	if (rc != NV_PORTS)
		goto err_out_iounmap;

	// Enable hotplug event interrupts.
	if (host->host_desc->enable_hotplug)
		host->host_desc->enable_hotplug(probe_ent);

	kfree(probe_ent);

	return 0;

err_out_iounmap:
	pci_iounmap(pdev, probe_ent->mmio_base);
err_out_free_host:
	kfree(host);
err_out_free_ent:
	kfree(probe_ent);
err_out_regions:
	pci_release_regions(pdev);
err_out_disable:
	if (!pci_dev_busy)
		pci_disable_device(pdev);
err_out:
	return rc;
}

static void nv_enable_hotplug(struct ata_probe_ent *probe_ent)
{
	u8 intr_mask;

	outb(NV_INT_STATUS_HOTPLUG,
		probe_ent->port[0].scr_addr + NV_INT_STATUS);

	intr_mask = inb(probe_ent->port[0].scr_addr + NV_INT_ENABLE);
	intr_mask |= NV_INT_ENABLE_HOTPLUG;

	outb(intr_mask, probe_ent->port[0].scr_addr + NV_INT_ENABLE);
}

static void nv_disable_hotplug(struct ata_host_set *host_set)
{
	u8 intr_mask;

	intr_mask = inb(host_set->ports[0]->ioaddr.scr_addr + NV_INT_ENABLE);

	intr_mask &= ~(NV_INT_ENABLE_HOTPLUG);

	outb(intr_mask, host_set->ports[0]->ioaddr.scr_addr + NV_INT_ENABLE);
}

static int nv_check_hotplug(struct ata_host_set *host_set)
{
	u8 intr_status;

	intr_status = inb(host_set->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);

	// Clear interrupt status.
	outb(0xff, host_set->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);

	if (intr_status & NV_INT_STATUS_HOTPLUG) {
		if (intr_status & NV_INT_STATUS_PDEV_ADDED)
			printk(KERN_WARNING "nv_sata: "
				"Primary device added\n");

		if (intr_status & NV_INT_STATUS_PDEV_REMOVED)
			printk(KERN_WARNING "nv_sata: "
				"Primary device removed\n");

		if (intr_status & NV_INT_STATUS_SDEV_ADDED)
			printk(KERN_WARNING "nv_sata: "
				"Secondary device added\n");

		if (intr_status & NV_INT_STATUS_SDEV_REMOVED)
			printk(KERN_WARNING "nv_sata: "
				"Secondary device removed\n");

		return 1;
	}

	return 0;
}

static void nv_enable_hotplug_ck804(struct ata_probe_ent *probe_ent)
{
	struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
	u8 intr_mask;
	u8 regval;

	pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
	regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
	pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);

	writeb(NV_INT_STATUS_HOTPLUG, probe_ent->mmio_base + NV_INT_STATUS_CK804);

	intr_mask = readb(probe_ent->mmio_base + NV_INT_ENABLE_CK804);
	intr_mask |= NV_INT_ENABLE_HOTPLUG;

	writeb(intr_mask, probe_ent->mmio_base + NV_INT_ENABLE_CK804);
}

static void nv_disable_hotplug_ck804(struct ata_host_set *host_set)
{
	struct pci_dev *pdev = to_pci_dev(host_set->dev);
	u8 intr_mask;
	u8 regval;

	intr_mask = readb(host_set->mmio_base + NV_INT_ENABLE_CK804);

	intr_mask &= ~(NV_INT_ENABLE_HOTPLUG);

	writeb(intr_mask, host_set->mmio_base + NV_INT_ENABLE_CK804);

	pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
	regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
	pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
}

static int nv_check_hotplug_ck804(struct ata_host_set *host_set)
{
	u8 intr_status;

	intr_status = readb(host_set->mmio_base + NV_INT_STATUS_CK804);

	// Clear interrupt status.
	writeb(0xff, host_set->mmio_base + NV_INT_STATUS_CK804);

	if (intr_status & NV_INT_STATUS_HOTPLUG) {
		if (intr_status & NV_INT_STATUS_PDEV_ADDED)
			printk(KERN_WARNING "nv_sata: "
				"Primary device added\n");

		if (intr_status & NV_INT_STATUS_PDEV_REMOVED)
			printk(KERN_WARNING "nv_sata: "
				"Primary device removed\n");

		if (intr_status & NV_INT_STATUS_SDEV_ADDED)
			printk(KERN_WARNING "nv_sata: "
				"Secondary device added\n");

		if (intr_status & NV_INT_STATUS_SDEV_REMOVED)
			printk(KERN_WARNING "nv_sata: "
				"Secondary device removed\n");

		return 1;
	}

	return 0;
}

static int __init nv_init(void)
{
	return pci_module_init(&nv_pci_driver);
}

static void __exit nv_exit(void)
{
	pci_unregister_driver(&nv_pci_driver);
}

module_init(nv_init);
module_exit(nv_exit);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* sata_nv.c - NVIDIA nForce SATA
	3	*
	4	* Copyright 2004 NVIDIA Corp. All rights reserved.
	5	* Copyright 2004 Andrew Chew
	6	*
aa7e16d6 JG	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2, or (at your option)
	11	* any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; see the file COPYING. If not, write to
	20	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
1da177e4	21	*
af36d7f0 JG	22	*
	23	* libata documentation is available via 'make {ps\|pdf}docs',
	24	* as Documentation/DocBook/libata.*
	25	*
	26	* No hardware documentation available outside of NVIDIA.
	27	* This driver programs the NVIDIA SATA controller in a similar
	28	* fashion as with other PCI IDE BMDMA controllers, with a few
	29	* NV-specific details such as register offsets, SATA phy location,
	30	* hotplug info, etc.
	31	*
1da177e4 LT	32	*/
	33
	34	#include <linux/config.h>
	35	#include <linux/kernel.h>
	36	#include <linux/module.h>
	37	#include <linux/pci.h>
	38	#include <linux/init.h>
	39	#include <linux/blkdev.h>
	40	#include <linux/delay.h>
	41	#include <linux/interrupt.h>
a9524a76	42	#include <linux/device.h>
1da177e4 LT	43	#include <scsi/scsi_host.h>
	44	#include <linux/libata.h>
	45
	46	#define DRV_NAME "sata_nv"
af64371a	47	#define DRV_VERSION "0.9"
1da177e4	48
10ad05df JG	49	enum {
	50	NV_PORTS = 2,
	51	NV_PIO_MASK = 0x1f,
	52	NV_MWDMA_MASK = 0x07,
	53	NV_UDMA_MASK = 0x7f,
	54	NV_PORT0_SCR_REG_OFFSET = 0x00,
	55	NV_PORT1_SCR_REG_OFFSET = 0x40,
1da177e4	56
10ad05df JG	57	NV_INT_STATUS = 0x10,
	58	NV_INT_STATUS_CK804 = 0x440,
	59	NV_INT_STATUS_PDEV_INT = 0x01,
	60	NV_INT_STATUS_PDEV_PM = 0x02,
	61	NV_INT_STATUS_PDEV_ADDED = 0x04,
	62	NV_INT_STATUS_PDEV_REMOVED = 0x08,
	63	NV_INT_STATUS_SDEV_INT = 0x10,
	64	NV_INT_STATUS_SDEV_PM = 0x20,
	65	NV_INT_STATUS_SDEV_ADDED = 0x40,
	66	NV_INT_STATUS_SDEV_REMOVED = 0x80,
	67	NV_INT_STATUS_PDEV_HOTPLUG = (NV_INT_STATUS_PDEV_ADDED \|
	68	NV_INT_STATUS_PDEV_REMOVED),
	69	NV_INT_STATUS_SDEV_HOTPLUG = (NV_INT_STATUS_SDEV_ADDED \|
	70	NV_INT_STATUS_SDEV_REMOVED),
	71	NV_INT_STATUS_HOTPLUG = (NV_INT_STATUS_PDEV_HOTPLUG \|
	72	NV_INT_STATUS_SDEV_HOTPLUG),
1da177e4	73
10ad05df JG	74	NV_INT_ENABLE = 0x11,
	75	NV_INT_ENABLE_CK804 = 0x441,
	76	NV_INT_ENABLE_PDEV_MASK = 0x01,
	77	NV_INT_ENABLE_PDEV_PM = 0x02,
	78	NV_INT_ENABLE_PDEV_ADDED = 0x04,
	79	NV_INT_ENABLE_PDEV_REMOVED = 0x08,
	80	NV_INT_ENABLE_SDEV_MASK = 0x10,
	81	NV_INT_ENABLE_SDEV_PM = 0x20,
	82	NV_INT_ENABLE_SDEV_ADDED = 0x40,
	83	NV_INT_ENABLE_SDEV_REMOVED = 0x80,
	84	NV_INT_ENABLE_PDEV_HOTPLUG = (NV_INT_ENABLE_PDEV_ADDED \|
	85	NV_INT_ENABLE_PDEV_REMOVED),
	86	NV_INT_ENABLE_SDEV_HOTPLUG = (NV_INT_ENABLE_SDEV_ADDED \|
	87	NV_INT_ENABLE_SDEV_REMOVED),
	88	NV_INT_ENABLE_HOTPLUG = (NV_INT_ENABLE_PDEV_HOTPLUG \|
	89	NV_INT_ENABLE_SDEV_HOTPLUG),
1da177e4	90
10ad05df JG	91	NV_INT_CONFIG = 0x12,
10ad05df JG	92	NV_INT_CONFIG_METHD = 0x01, // 0 = INT, 1 = SMI
1da177e4	93
10ad05df JG	94	// For PCI config register 20
	95	NV_MCP_SATA_CFG_20 = 0x50,
	96	NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04,
	97	};
1da177e4 LT	98
	99	static int nv_init_one (struct pci_dev pdev, const struct pci_device_id ent);
	100	static irqreturn_t nv_interrupt (int irq, void *dev_instance,
	101	struct pt_regs *regs);
	102	static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg);
	103	static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
	104	static void nv_host_stop (struct ata_host_set *host_set);
	105	static void nv_enable_hotplug(struct ata_probe_ent *probe_ent);
	106	static void nv_disable_hotplug(struct ata_host_set *host_set);
b887030a	107	static int nv_check_hotplug(struct ata_host_set *host_set);
1da177e4 LT	108	static void nv_enable_hotplug_ck804(struct ata_probe_ent *probe_ent);
1da177e4 LT	109	static void nv_disable_hotplug_ck804(struct ata_host_set *host_set);
b887030a	110	static int nv_check_hotplug_ck804(struct ata_host_set *host_set);
1da177e4 LT	111
	112	enum nv_host_type
	113	{
	114	GENERIC,
	115	NFORCE2,
	116	NFORCE3,
e710245b	117	CK804
1da177e4 LT	118	};
1da177e4 LT	119
3b7d697d	120	static const struct pci_device_id nv_pci_tbl[] = {
1da177e4 LT	121	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA,
	122	PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE2 },
	123	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA,
	124	PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
	125	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2,
	126	PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
	127	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA,
	128	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
	129	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2,
	130	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
	131	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA,
	132	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
	133	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2,
	134	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
541134cf	135	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA,
e710245b	136	PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
541134cf	137	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2,
e710245b	138	PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
541134cf	139	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA,
e710245b	140	PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
e86ee668	141	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2,
e710245b	142	PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
1da177e4 LT	143	{ PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
	144	PCI_ANY_ID, PCI_ANY_ID,
	145	PCI_CLASS_STORAGE_IDE<<8, 0xffff00, GENERIC },
541134cf DD	146	{ PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
	147	PCI_ANY_ID, PCI_ANY_ID,
	148	PCI_CLASS_STORAGE_RAID<<8, 0xffff00, GENERIC },
1da177e4 LT	149	{ 0, } /* terminate list */
	150	};
	151
1da177e4 LT	152	struct nv_host_desc
	153	{
	154	enum nv_host_type host_type;
	155	void (enable_hotplug)(struct ata_probe_ent probe_ent);
	156	void (disable_hotplug)(struct ata_host_set host_set);
b887030a	157	int (check_hotplug)(struct ata_host_set host_set);
1da177e4 LT	158
	159	};
	160	static struct nv_host_desc nv_device_tbl[] = {
	161	{
	162	.host_type = GENERIC,
	163	.enable_hotplug = NULL,
	164	.disable_hotplug= NULL,
	165	.check_hotplug = NULL,
	166	},
	167	{
	168	.host_type = NFORCE2,
	169	.enable_hotplug = nv_enable_hotplug,
	170	.disable_hotplug= nv_disable_hotplug,
	171	.check_hotplug = nv_check_hotplug,
	172	},
	173	{
	174	.host_type = NFORCE3,
	175	.enable_hotplug = nv_enable_hotplug,
	176	.disable_hotplug= nv_disable_hotplug,
	177	.check_hotplug = nv_check_hotplug,
	178	},
	179	{ .host_type = CK804,
	180	.enable_hotplug = nv_enable_hotplug_ck804,
	181	.disable_hotplug= nv_disable_hotplug_ck804,
	182	.check_hotplug = nv_check_hotplug_ck804,
	183	},
	184	};
	185
	186	struct nv_host
	187	{
	188	struct nv_host_desc *host_desc;
	189	unsigned long host_flags;
	190	};
	191
	192	static struct pci_driver nv_pci_driver = {
	193	.name = DRV_NAME,
	194	.id_table = nv_pci_tbl,
	195	.probe = nv_init_one,
	196	.remove = ata_pci_remove_one,
	197	};
	198
193515d5	199	static struct scsi_host_template nv_sht = {
1da177e4 LT	200	.module = THIS_MODULE,
	201	.name = DRV_NAME,
	202	.ioctl = ata_scsi_ioctl,
	203	.queuecommand = ata_scsi_queuecmd,
1da177e4 LT	204	.can_queue = ATA_DEF_QUEUE,
	205	.this_id = ATA_SHT_THIS_ID,
	206	.sg_tablesize = LIBATA_MAX_PRD,
1da177e4 LT	207	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	208	.emulated = ATA_SHT_EMULATED,
	209	.use_clustering = ATA_SHT_USE_CLUSTERING,
	210	.proc_name = DRV_NAME,
	211	.dma_boundary = ATA_DMA_BOUNDARY,
	212	.slave_configure = ata_scsi_slave_config,
	213	.bios_param = ata_std_bios_param,
1da177e4 LT	214	};
1da177e4 LT	215
057ace5e	216	static const struct ata_port_operations nv_ops = {
1da177e4 LT	217	.port_disable = ata_port_disable,
	218	.tf_load = ata_tf_load,
	219	.tf_read = ata_tf_read,
	220	.exec_command = ata_exec_command,
	221	.check_status = ata_check_status,
	222	.dev_select = ata_std_dev_select,
	223	.phy_reset = sata_phy_reset,
	224	.bmdma_setup = ata_bmdma_setup,
	225	.bmdma_start = ata_bmdma_start,
	226	.bmdma_stop = ata_bmdma_stop,
	227	.bmdma_status = ata_bmdma_status,
	228	.qc_prep = ata_qc_prep,
	229	.qc_issue = ata_qc_issue_prot,
	230	.eng_timeout = ata_eng_timeout,
	231	.irq_handler = nv_interrupt,
	232	.irq_clear = ata_bmdma_irq_clear,
	233	.scr_read = nv_scr_read,
	234	.scr_write = nv_scr_write,
	235	.port_start = ata_port_start,
	236	.port_stop = ata_port_stop,
	237	.host_stop = nv_host_stop,
	238	};
	239
	240	/* FIXME: The hardware provides the necessary SATA PHY controls
	241	* to support ATA_FLAG_SATA_RESET. However, it is currently
	242	* necessary to disable that flag, to solve misdetection problems.
	243	* See http://bugme.osdl.org/show_bug.cgi?id=3352 for more info.
	244	*
	245	* This problem really needs to be investigated further. But in the
	246	* meantime, we avoid ATA_FLAG_SATA_RESET to get people working.
	247	*/
	248	static struct ata_port_info nv_port_info = {
	249	.sht = &nv_sht,
	250	.host_flags = ATA_FLAG_SATA \|
	251	/* ATA_FLAG_SATA_RESET \| */
	252	ATA_FLAG_SRST \|
	253	ATA_FLAG_NO_LEGACY,
	254	.pio_mask = NV_PIO_MASK,
	255	.mwdma_mask = NV_MWDMA_MASK,
	256	.udma_mask = NV_UDMA_MASK,
	257	.port_ops = &nv_ops,
	258	};
	259
	260	MODULE_AUTHOR("NVIDIA");
	261	MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
	262	MODULE_LICENSE("GPL");
	263	MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
	264	MODULE_VERSION(DRV_VERSION);
	265
	266	static irqreturn_t nv_interrupt (int irq, void *dev_instance,
	267	struct pt_regs *regs)
	268	{
	269	struct ata_host_set *host_set = dev_instance;
	270	struct nv_host *host = host_set->private_data;
	271	unsigned int i;
	272	unsigned int handled = 0;
	273	unsigned long flags;
	274
	275	spin_lock_irqsave(&host_set->lock, flags);
	276
	277	for (i = 0; i < host_set->n_ports; i++) {
	278	struct ata_port *ap;
	279
	280	ap = host_set->ports[i];
c1389503	281	if (ap &&
198e0fed	282	!(ap->flags & (ATA_FLAG_DISABLED \| ATA_FLAG_NOINTR))) {
1da177e4 LT	283	struct ata_queued_cmd *qc;
	284
	285	qc = ata_qc_from_tag(ap, ap->active_tag);
	286	if (qc && (!(qc->tf.ctl & ATA_NIEN)))
	287	handled += ata_host_intr(ap, qc);
b887030a AC	288	else
	289	// No request pending? Clear interrupt status
	290	// anyway, in case there's one pending.
	291	ap->ops->check_status(ap);
1da177e4 LT	292	}
	293
	294	}
	295
	296	if (host->host_desc->check_hotplug)
b887030a	297	handled += host->host_desc->check_hotplug(host_set);
1da177e4 LT	298
	299	spin_unlock_irqrestore(&host_set->lock, flags);
	300
	301	return IRQ_RETVAL(handled);
	302	}
	303
	304	static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg)
	305	{
1da177e4 LT	306	if (sc_reg > SCR_CONTROL)
	307	return 0xffffffffU;
	308
02cbd926	309	return ioread32((void __iomem )ap->ioaddr.scr_addr + (sc_reg 4));
1da177e4 LT	310	}
	311
	312	static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
	313	{
1da177e4 LT	314	if (sc_reg > SCR_CONTROL)
	315	return;
	316
02cbd926	317	iowrite32(val, (void __iomem )ap->ioaddr.scr_addr + (sc_reg 4));
1da177e4 LT	318	}
	319
	320	static void nv_host_stop (struct ata_host_set *host_set)
	321	{
	322	struct nv_host *host = host_set->private_data;
	323
	324	// Disable hotplug event interrupts.
	325	if (host->host_desc->disable_hotplug)
	326	host->host_desc->disable_hotplug(host_set);
	327
	328	kfree(host);
aa8f0dc6	329
02cbd926	330	ata_pci_host_stop(host_set);
1da177e4 LT	331	}
	332
	333	static int nv_init_one (struct pci_dev pdev, const struct pci_device_id ent)
	334	{
	335	static int printed_version = 0;
	336	struct nv_host *host;
	337	struct ata_port_info *ppi;
	338	struct ata_probe_ent *probe_ent;
	339	int pci_dev_busy = 0;
	340	int rc;
	341	u32 bar;
02cbd926	342	unsigned long base;
1da177e4 LT	343
	344	// Make sure this is a SATA controller by counting the number of bars
	345	// (NVIDIA SATA controllers will always have six bars). Otherwise,
	346	// it's an IDE controller and we ignore it.
	347	for (bar=0; bar<6; bar++)
	348	if (pci_resource_start(pdev, bar) == 0)
	349	return -ENODEV;
	350
	351	if (!printed_version++)
a9524a76	352	dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 LT	353
	354	rc = pci_enable_device(pdev);
	355	if (rc)
	356	goto err_out;
	357
	358	rc = pci_request_regions(pdev, DRV_NAME);
	359	if (rc) {
	360	pci_dev_busy = 1;
	361	goto err_out_disable;
	362	}
	363
	364	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	365	if (rc)
	366	goto err_out_regions;
	367	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	368	if (rc)
	369	goto err_out_regions;
	370
	371	rc = -ENOMEM;
	372
	373	ppi = &nv_port_info;
47a86593	374	probe_ent = ata_pci_init_native_mode(pdev, &ppi, ATA_PORT_PRIMARY \| ATA_PORT_SECONDARY);
1da177e4 LT	375	if (!probe_ent)
	376	goto err_out_regions;
	377
	378	host = kmalloc(sizeof(struct nv_host), GFP_KERNEL);
	379	if (!host)
	380	goto err_out_free_ent;
	381
	382	memset(host, 0, sizeof(struct nv_host));
	383	host->host_desc = &nv_device_tbl[ent->driver_data];
	384
	385	probe_ent->private_data = host;
	386
02cbd926 JG	387	probe_ent->mmio_base = pci_iomap(pdev, 5, 0);
	388	if (!probe_ent->mmio_base) {
	389	rc = -EIO;
	390	goto err_out_free_host;
	391	}
1da177e4	392
02cbd926	393	base = (unsigned long)probe_ent->mmio_base;
1da177e4	394
02cbd926 JG	395	probe_ent->port[0].scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
02cbd926 JG	396	probe_ent->port[1].scr_addr = base + NV_PORT1_SCR_REG_OFFSET;
1da177e4 LT	397
	398	pci_set_master(pdev);
	399
	400	rc = ata_device_add(probe_ent);
	401	if (rc != NV_PORTS)
	402	goto err_out_iounmap;
	403
	404	// Enable hotplug event interrupts.
	405	if (host->host_desc->enable_hotplug)
	406	host->host_desc->enable_hotplug(probe_ent);
	407
	408	kfree(probe_ent);
	409
	410	return 0;
	411
	412	err_out_iounmap:
02cbd926	413	pci_iounmap(pdev, probe_ent->mmio_base);
1da177e4 LT	414	err_out_free_host:
	415	kfree(host);
	416	err_out_free_ent:
	417	kfree(probe_ent);
	418	err_out_regions:
	419	pci_release_regions(pdev);
	420	err_out_disable:
	421	if (!pci_dev_busy)
	422	pci_disable_device(pdev);
	423	err_out:
	424	return rc;
	425	}
	426
	427	static void nv_enable_hotplug(struct ata_probe_ent *probe_ent)
	428	{
	429	u8 intr_mask;
	430
	431	outb(NV_INT_STATUS_HOTPLUG,
	432	probe_ent->port[0].scr_addr + NV_INT_STATUS);
	433
	434	intr_mask = inb(probe_ent->port[0].scr_addr + NV_INT_ENABLE);
	435	intr_mask \|= NV_INT_ENABLE_HOTPLUG;
	436
	437	outb(intr_mask, probe_ent->port[0].scr_addr + NV_INT_ENABLE);
	438	}
	439
	440	static void nv_disable_hotplug(struct ata_host_set *host_set)
	441	{
	442	u8 intr_mask;
	443
	444	intr_mask = inb(host_set->ports[0]->ioaddr.scr_addr + NV_INT_ENABLE);
	445
	446	intr_mask &= ~(NV_INT_ENABLE_HOTPLUG);
	447
	448	outb(intr_mask, host_set->ports[0]->ioaddr.scr_addr + NV_INT_ENABLE);
	449	}
	450
b887030a	451	static int nv_check_hotplug(struct ata_host_set *host_set)
1da177e4 LT	452	{
	453	u8 intr_status;
	454
	455	intr_status = inb(host_set->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
	456
	457	// Clear interrupt status.
	458	outb(0xff, host_set->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
	459
	460	if (intr_status & NV_INT_STATUS_HOTPLUG) {
	461	if (intr_status & NV_INT_STATUS_PDEV_ADDED)
	462	printk(KERN_WARNING "nv_sata: "
	463	"Primary device added\n");
	464
	465	if (intr_status & NV_INT_STATUS_PDEV_REMOVED)
	466	printk(KERN_WARNING "nv_sata: "
	467	"Primary device removed\n");
	468
	469	if (intr_status & NV_INT_STATUS_SDEV_ADDED)
	470	printk(KERN_WARNING "nv_sata: "
	471	"Secondary device added\n");
	472
	473	if (intr_status & NV_INT_STATUS_SDEV_REMOVED)
	474	printk(KERN_WARNING "nv_sata: "
	475	"Secondary device removed\n");
b887030a AC	476
b887030a AC	477	return 1;
1da177e4	478	}
b887030a AC	479
b887030a AC	480	return 0;
1da177e4 LT	481	}
	482
	483	static void nv_enable_hotplug_ck804(struct ata_probe_ent *probe_ent)
	484	{
	485	struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
	486	u8 intr_mask;
	487	u8 regval;
	488
	489	pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
	490	regval \|= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
	491	pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
	492
	493	writeb(NV_INT_STATUS_HOTPLUG, probe_ent->mmio_base + NV_INT_STATUS_CK804);
	494
	495	intr_mask = readb(probe_ent->mmio_base + NV_INT_ENABLE_CK804);
	496	intr_mask \|= NV_INT_ENABLE_HOTPLUG;
	497
	498	writeb(intr_mask, probe_ent->mmio_base + NV_INT_ENABLE_CK804);
	499	}
	500
	501	static void nv_disable_hotplug_ck804(struct ata_host_set *host_set)
	502	{
	503	struct pci_dev *pdev = to_pci_dev(host_set->dev);
	504	u8 intr_mask;
	505	u8 regval;
	506
	507	intr_mask = readb(host_set->mmio_base + NV_INT_ENABLE_CK804);
	508
	509	intr_mask &= ~(NV_INT_ENABLE_HOTPLUG);
	510
	511	writeb(intr_mask, host_set->mmio_base + NV_INT_ENABLE_CK804);
	512
	513	pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
	514	regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
	515	pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
	516	}
	517
b887030a	518	static int nv_check_hotplug_ck804(struct ata_host_set *host_set)
1da177e4 LT	519	{
	520	u8 intr_status;
	521
	522	intr_status = readb(host_set->mmio_base + NV_INT_STATUS_CK804);
	523
	524	// Clear interrupt status.
	525	writeb(0xff, host_set->mmio_base + NV_INT_STATUS_CK804);
	526
	527	if (intr_status & NV_INT_STATUS_HOTPLUG) {
	528	if (intr_status & NV_INT_STATUS_PDEV_ADDED)
	529	printk(KERN_WARNING "nv_sata: "
	530	"Primary device added\n");
	531
	532	if (intr_status & NV_INT_STATUS_PDEV_REMOVED)
	533	printk(KERN_WARNING "nv_sata: "
	534	"Primary device removed\n");
	535
	536	if (intr_status & NV_INT_STATUS_SDEV_ADDED)
	537	printk(KERN_WARNING "nv_sata: "
	538	"Secondary device added\n");
	539
	540	if (intr_status & NV_INT_STATUS_SDEV_REMOVED)
	541	printk(KERN_WARNING "nv_sata: "
	542	"Secondary device removed\n");
b887030a AC	543
b887030a AC	544	return 1;
1da177e4	545	}
b887030a AC	546
b887030a AC	547	return 0;
1da177e4 LT	548	}
	549
	550	static int __init nv_init(void)
	551	{
	552	return pci_module_init(&nv_pci_driver);
	553	}
	554
	555	static void __exit nv_exit(void)
	556	{
	557	pci_unregister_driver(&nv_pci_driver);
	558	}
	559
	560	module_init(nv_init);
	561	module_exit(nv_exit);