[deliverable/linux.git] / drivers / scsi / sata_nv.c

/*
 *  sata_nv.c - NVIDIA nForce SATA
 *
 *  Copyright 2004 NVIDIA Corp.  All rights reserved.
 *  Copyright 2004 Andrew Chew
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *  No hardware documentation available outside of NVIDIA.
 *  This driver programs the NVIDIA SATA controller in a similar
 *  fashion as with other PCI IDE BMDMA controllers, with a few
 *  NV-specific details such as register offsets, SATA phy location,
 *  hotplug info, etc.
 *
 */

#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME			"sata_nv"
#define DRV_VERSION			"0.9"

enum {
	NV_PORTS			= 2,
	NV_PIO_MASK			= 0x1f,
	NV_MWDMA_MASK			= 0x07,
	NV_UDMA_MASK			= 0x7f,
	NV_PORT0_SCR_REG_OFFSET		= 0x00,
	NV_PORT1_SCR_REG_OFFSET		= 0x40,

	NV_INT_STATUS			= 0x10,
	NV_INT_STATUS_CK804		= 0x440,
	NV_INT_STATUS_PDEV_INT		= 0x01,
	NV_INT_STATUS_PDEV_PM		= 0x02,
	NV_INT_STATUS_PDEV_ADDED	= 0x04,
	NV_INT_STATUS_PDEV_REMOVED	= 0x08,
	NV_INT_STATUS_SDEV_INT		= 0x10,
	NV_INT_STATUS_SDEV_PM		= 0x20,
	NV_INT_STATUS_SDEV_ADDED	= 0x40,
	NV_INT_STATUS_SDEV_REMOVED	= 0x80,

	NV_INT_ENABLE			= 0x11,
	NV_INT_ENABLE_CK804		= 0x441,
	NV_INT_ENABLE_PDEV_MASK		= 0x01,
	NV_INT_ENABLE_PDEV_PM		= 0x02,
	NV_INT_ENABLE_PDEV_ADDED	= 0x04,
	NV_INT_ENABLE_PDEV_REMOVED	= 0x08,
	NV_INT_ENABLE_SDEV_MASK		= 0x10,
	NV_INT_ENABLE_SDEV_PM		= 0x20,
	NV_INT_ENABLE_SDEV_ADDED	= 0x40,
	NV_INT_ENABLE_SDEV_REMOVED	= 0x80,

	NV_INT_CONFIG			= 0x12,
	NV_INT_CONFIG_METHD		= 0x01, // 0 = INT, 1 = SMI

	// For PCI config register 20
	NV_MCP_SATA_CFG_20		= 0x50,
	NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04,
};

static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
static irqreturn_t nv_interrupt (int irq, void *dev_instance,
				 struct pt_regs *regs);
static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg);
static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
static void nv_host_stop (struct ata_host_set *host_set);

enum nv_host_type
{
	GENERIC,
	NFORCE2,
	NFORCE3,
	CK804
};

static const struct pci_device_id nv_pci_tbl[] = {
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE2 },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
	{ PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
		PCI_ANY_ID, PCI_ANY_ID,
		PCI_CLASS_STORAGE_IDE<<8, 0xffff00, GENERIC },
	{ PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
		PCI_ANY_ID, PCI_ANY_ID,
		PCI_CLASS_STORAGE_RAID<<8, 0xffff00, GENERIC },
	{ 0, } /* terminate list */
};

struct nv_host_desc
{
	enum nv_host_type	host_type;
};
static struct nv_host_desc nv_device_tbl[] = {
	{
		.host_type	= GENERIC,
	},
	{
		.host_type	= NFORCE2,
	},
	{
		.host_type	= NFORCE3,
	},
	{	.host_type	= CK804,
	},
};

struct nv_host
{
	struct nv_host_desc	*host_desc;
	unsigned long		host_flags;
};

static struct pci_driver nv_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= nv_pci_tbl,
	.probe			= nv_init_one,
	.remove			= ata_pci_remove_one,
};

static struct scsi_host_template nv_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.slave_destroy		= ata_scsi_slave_destroy,
	.bios_param		= ata_std_bios_param,
};

static const struct ata_port_operations nv_ops = {
	.port_disable		= ata_port_disable,
	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.exec_command		= ata_exec_command,
	.check_status		= ata_check_status,
	.dev_select		= ata_std_dev_select,
	.phy_reset		= sata_phy_reset,
	.bmdma_setup		= ata_bmdma_setup,
	.bmdma_start		= ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
	.eng_timeout		= ata_eng_timeout,
	.data_xfer		= ata_pio_data_xfer,
	.irq_handler		= nv_interrupt,
	.irq_clear		= ata_bmdma_irq_clear,
	.scr_read		= nv_scr_read,
	.scr_write		= nv_scr_write,
	.port_start		= ata_port_start,
	.port_stop		= ata_port_stop,
	.host_stop		= nv_host_stop,
};

/* FIXME: The hardware provides the necessary SATA PHY controls
 * to support ATA_FLAG_SATA_RESET.  However, it is currently
 * necessary to disable that flag, to solve misdetection problems.
 * See http://bugme.osdl.org/show_bug.cgi?id=3352 for more info.
 *
 * This problem really needs to be investigated further.  But in the
 * meantime, we avoid ATA_FLAG_SATA_RESET to get people working.
 */
static struct ata_port_info nv_port_info = {
	.sht		= &nv_sht,
	.host_flags	= ATA_FLAG_SATA |
			  /* ATA_FLAG_SATA_RESET | */
			  ATA_FLAG_SRST |
			  ATA_FLAG_NO_LEGACY,
	.pio_mask	= NV_PIO_MASK,
	.mwdma_mask	= NV_MWDMA_MASK,
	.udma_mask	= NV_UDMA_MASK,
	.port_ops	= &nv_ops,
};

MODULE_AUTHOR("NVIDIA");
MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
MODULE_VERSION(DRV_VERSION);

static irqreturn_t nv_interrupt (int irq, void *dev_instance,
				 struct pt_regs *regs)
{
	struct ata_host_set *host_set = dev_instance;
	unsigned int i;
	unsigned int handled = 0;
	unsigned long flags;

	spin_lock_irqsave(&host_set->lock, flags);

	for (i = 0; i < host_set->n_ports; i++) {
		struct ata_port *ap;

		ap = host_set->ports[i];
		if (ap &&
		    !(ap->flags & ATA_FLAG_DISABLED)) {
			struct ata_queued_cmd *qc;

			qc = ata_qc_from_tag(ap, ap->active_tag);
			if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
				handled += ata_host_intr(ap, qc);
			else
				// No request pending?  Clear interrupt status
				// anyway, in case there's one pending.
				ap->ops->check_status(ap);
		}

	}

	spin_unlock_irqrestore(&host_set->lock, flags);

	return IRQ_RETVAL(handled);
}

static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg)
{
	if (sc_reg > SCR_CONTROL)
		return 0xffffffffU;

	return ioread32((void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
}

static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
{
	if (sc_reg > SCR_CONTROL)
		return;

	iowrite32(val, (void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
}

static void nv_host_stop (struct ata_host_set *host_set)
{
	struct nv_host *host = host_set->private_data;

	kfree(host);

	ata_pci_host_stop(host_set);
}

static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static int printed_version = 0;
	struct nv_host *host;
	struct ata_port_info *ppi;
	struct ata_probe_ent *probe_ent;
	int pci_dev_busy = 0;
	int rc;
	u32 bar;
	unsigned long base;

        // Make sure this is a SATA controller by counting the number of bars
        // (NVIDIA SATA controllers will always have six bars).  Otherwise,
        // it's an IDE controller and we ignore it.
	for (bar=0; bar<6; bar++)
		if (pci_resource_start(pdev, bar) == 0)
			return -ENODEV;

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");

	rc = pci_enable_device(pdev);
	if (rc)
		goto err_out;

	rc = pci_request_regions(pdev, DRV_NAME);
	if (rc) {
		pci_dev_busy = 1;
		goto err_out_disable;
	}

	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		goto err_out_regions;
	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		goto err_out_regions;

	rc = -ENOMEM;

	ppi = &nv_port_info;
	probe_ent = ata_pci_init_native_mode(pdev, &ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
	if (!probe_ent)
		goto err_out_regions;

	host = kmalloc(sizeof(struct nv_host), GFP_KERNEL);
	if (!host)
		goto err_out_free_ent;

	memset(host, 0, sizeof(struct nv_host));
	host->host_desc = &nv_device_tbl[ent->driver_data];

	probe_ent->private_data = host;

	probe_ent->mmio_base = pci_iomap(pdev, 5, 0);
	if (!probe_ent->mmio_base) {
		rc = -EIO;
		goto err_out_free_host;
	}

	base = (unsigned long)probe_ent->mmio_base;

	probe_ent->port[0].scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
	probe_ent->port[1].scr_addr = base + NV_PORT1_SCR_REG_OFFSET;

	pci_set_master(pdev);

	rc = ata_device_add(probe_ent);
	if (rc != NV_PORTS)
		goto err_out_iounmap;

	kfree(probe_ent);

	return 0;

err_out_iounmap:
	pci_iounmap(pdev, probe_ent->mmio_base);
err_out_free_host:
	kfree(host);
err_out_free_ent:
	kfree(probe_ent);
err_out_regions:
	pci_release_regions(pdev);
err_out_disable:
	if (!pci_dev_busy)
		pci_disable_device(pdev);
err_out:
	return rc;
}

static int __init nv_init(void)
{
	return pci_module_init(&nv_pci_driver);
}

static void __exit nv_exit(void)
{
	pci_unregister_driver(&nv_pci_driver);
}

module_init(nv_init);
module_exit(nv_exit);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* sata_nv.c - NVIDIA nForce SATA
	3	*
	4	* Copyright 2004 NVIDIA Corp. All rights reserved.
	5	* Copyright 2004 Andrew Chew
	6	*
aa7e16d6 JG	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2, or (at your option)
	11	* any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; see the file COPYING. If not, write to
	20	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
1da177e4	21	*
af36d7f0 JG	22	*
	23	* libata documentation is available via 'make {ps\|pdf}docs',
	24	* as Documentation/DocBook/libata.*
	25	*
	26	* No hardware documentation available outside of NVIDIA.
	27	* This driver programs the NVIDIA SATA controller in a similar
	28	* fashion as with other PCI IDE BMDMA controllers, with a few
	29	* NV-specific details such as register offsets, SATA phy location,
	30	* hotplug info, etc.
	31	*
1da177e4 LT	32	*/
	33
	34	#include <linux/config.h>
	35	#include <linux/kernel.h>
	36	#include <linux/module.h>
	37	#include <linux/pci.h>
	38	#include <linux/init.h>
	39	#include <linux/blkdev.h>
	40	#include <linux/delay.h>
	41	#include <linux/interrupt.h>
a9524a76	42	#include <linux/device.h>
1da177e4 LT	43	#include <scsi/scsi_host.h>
	44	#include <linux/libata.h>
	45
	46	#define DRV_NAME "sata_nv"
af64371a	47	#define DRV_VERSION "0.9"
1da177e4	48
10ad05df JG	49	enum {
	50	NV_PORTS = 2,
	51	NV_PIO_MASK = 0x1f,
	52	NV_MWDMA_MASK = 0x07,
	53	NV_UDMA_MASK = 0x7f,
	54	NV_PORT0_SCR_REG_OFFSET = 0x00,
	55	NV_PORT1_SCR_REG_OFFSET = 0x40,
1da177e4	56
10ad05df JG	57	NV_INT_STATUS = 0x10,
	58	NV_INT_STATUS_CK804 = 0x440,
	59	NV_INT_STATUS_PDEV_INT = 0x01,
	60	NV_INT_STATUS_PDEV_PM = 0x02,
	61	NV_INT_STATUS_PDEV_ADDED = 0x04,
	62	NV_INT_STATUS_PDEV_REMOVED = 0x08,
	63	NV_INT_STATUS_SDEV_INT = 0x10,
	64	NV_INT_STATUS_SDEV_PM = 0x20,
	65	NV_INT_STATUS_SDEV_ADDED = 0x40,
	66	NV_INT_STATUS_SDEV_REMOVED = 0x80,
1da177e4	67
10ad05df JG	68	NV_INT_ENABLE = 0x11,
	69	NV_INT_ENABLE_CK804 = 0x441,
	70	NV_INT_ENABLE_PDEV_MASK = 0x01,
	71	NV_INT_ENABLE_PDEV_PM = 0x02,
	72	NV_INT_ENABLE_PDEV_ADDED = 0x04,
	73	NV_INT_ENABLE_PDEV_REMOVED = 0x08,
	74	NV_INT_ENABLE_SDEV_MASK = 0x10,
	75	NV_INT_ENABLE_SDEV_PM = 0x20,
	76	NV_INT_ENABLE_SDEV_ADDED = 0x40,
	77	NV_INT_ENABLE_SDEV_REMOVED = 0x80,
1da177e4	78
10ad05df JG	79	NV_INT_CONFIG = 0x12,
10ad05df JG	80	NV_INT_CONFIG_METHD = 0x01, // 0 = INT, 1 = SMI
1da177e4	81
10ad05df JG	82	// For PCI config register 20
	83	NV_MCP_SATA_CFG_20 = 0x50,
	84	NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04,
	85	};
1da177e4 LT	86
	87	static int nv_init_one (struct pci_dev pdev, const struct pci_device_id ent);
	88	static irqreturn_t nv_interrupt (int irq, void *dev_instance,
	89	struct pt_regs *regs);
	90	static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg);
	91	static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
	92	static void nv_host_stop (struct ata_host_set *host_set);
1da177e4 LT	93
	94	enum nv_host_type
	95	{
	96	GENERIC,
	97	NFORCE2,
	98	NFORCE3,
e710245b	99	CK804
1da177e4 LT	100	};
1da177e4 LT	101
3b7d697d	102	static const struct pci_device_id nv_pci_tbl[] = {
1da177e4 LT	103	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA,
	104	PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE2 },
	105	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA,
	106	PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
	107	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2,
	108	PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
	109	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA,
	110	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
	111	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2,
	112	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
	113	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA,
	114	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
	115	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2,
	116	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
541134cf	117	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA,
e710245b	118	PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
541134cf	119	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2,
e710245b	120	PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
541134cf	121	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA,
e710245b	122	PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
e86ee668	123	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2,
e710245b	124	PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
4c5c8161 AC	125	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA,
	126	PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
	127	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2,
	128	PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
	129	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3,
	130	PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
1da177e4 LT	131	{ PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
	132	PCI_ANY_ID, PCI_ANY_ID,
	133	PCI_CLASS_STORAGE_IDE<<8, 0xffff00, GENERIC },
541134cf DD	134	{ PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
	135	PCI_ANY_ID, PCI_ANY_ID,
	136	PCI_CLASS_STORAGE_RAID<<8, 0xffff00, GENERIC },
1da177e4 LT	137	{ 0, } /* terminate list */
	138	};
	139
1da177e4 LT	140	struct nv_host_desc
	141	{
	142	enum nv_host_type host_type;
1da177e4 LT	143	};
	144	static struct nv_host_desc nv_device_tbl[] = {
	145	{
	146	.host_type = GENERIC,
1da177e4 LT	147	},
	148	{
	149	.host_type = NFORCE2,
1da177e4 LT	150	},
	151	{
	152	.host_type = NFORCE3,
1da177e4 LT	153	},
1da177e4 LT	154	{ .host_type = CK804,
1da177e4 LT	155	},
	156	};
	157
	158	struct nv_host
	159	{
	160	struct nv_host_desc *host_desc;
	161	unsigned long host_flags;
	162	};
	163
	164	static struct pci_driver nv_pci_driver = {
	165	.name = DRV_NAME,
	166	.id_table = nv_pci_tbl,
	167	.probe = nv_init_one,
	168	.remove = ata_pci_remove_one,
	169	};
	170
193515d5	171	static struct scsi_host_template nv_sht = {
1da177e4 LT	172	.module = THIS_MODULE,
	173	.name = DRV_NAME,
	174	.ioctl = ata_scsi_ioctl,
	175	.queuecommand = ata_scsi_queuecmd,
1da177e4 LT	176	.can_queue = ATA_DEF_QUEUE,
	177	.this_id = ATA_SHT_THIS_ID,
	178	.sg_tablesize = LIBATA_MAX_PRD,
1da177e4 LT	179	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	180	.emulated = ATA_SHT_EMULATED,
	181	.use_clustering = ATA_SHT_USE_CLUSTERING,
	182	.proc_name = DRV_NAME,
	183	.dma_boundary = ATA_DMA_BOUNDARY,
	184	.slave_configure = ata_scsi_slave_config,
ccf68c34	185	.slave_destroy = ata_scsi_slave_destroy,
1da177e4	186	.bios_param = ata_std_bios_param,
1da177e4 LT	187	};
1da177e4 LT	188
057ace5e	189	static const struct ata_port_operations nv_ops = {
1da177e4 LT	190	.port_disable = ata_port_disable,
	191	.tf_load = ata_tf_load,
	192	.tf_read = ata_tf_read,
	193	.exec_command = ata_exec_command,
	194	.check_status = ata_check_status,
	195	.dev_select = ata_std_dev_select,
	196	.phy_reset = sata_phy_reset,
	197	.bmdma_setup = ata_bmdma_setup,
	198	.bmdma_start = ata_bmdma_start,
	199	.bmdma_stop = ata_bmdma_stop,
	200	.bmdma_status = ata_bmdma_status,
	201	.qc_prep = ata_qc_prep,
	202	.qc_issue = ata_qc_issue_prot,
	203	.eng_timeout = ata_eng_timeout,
a6b2c5d4	204	.data_xfer = ata_pio_data_xfer,
1da177e4 LT	205	.irq_handler = nv_interrupt,
	206	.irq_clear = ata_bmdma_irq_clear,
	207	.scr_read = nv_scr_read,
	208	.scr_write = nv_scr_write,
	209	.port_start = ata_port_start,
	210	.port_stop = ata_port_stop,
	211	.host_stop = nv_host_stop,
	212	};
	213
	214	/* FIXME: The hardware provides the necessary SATA PHY controls
	215	* to support ATA_FLAG_SATA_RESET. However, it is currently
	216	* necessary to disable that flag, to solve misdetection problems.
	217	* See http://bugme.osdl.org/show_bug.cgi?id=3352 for more info.
	218	*
	219	* This problem really needs to be investigated further. But in the
	220	* meantime, we avoid ATA_FLAG_SATA_RESET to get people working.
	221	*/
	222	static struct ata_port_info nv_port_info = {
	223	.sht = &nv_sht,
	224	.host_flags = ATA_FLAG_SATA \|
	225	/* ATA_FLAG_SATA_RESET \| */
	226	ATA_FLAG_SRST \|
	227	ATA_FLAG_NO_LEGACY,
	228	.pio_mask = NV_PIO_MASK,
	229	.mwdma_mask = NV_MWDMA_MASK,
	230	.udma_mask = NV_UDMA_MASK,
	231	.port_ops = &nv_ops,
	232	};
	233
	234	MODULE_AUTHOR("NVIDIA");
	235	MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
	236	MODULE_LICENSE("GPL");
	237	MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
	238	MODULE_VERSION(DRV_VERSION);
	239
	240	static irqreturn_t nv_interrupt (int irq, void *dev_instance,
	241	struct pt_regs *regs)
	242	{
	243	struct ata_host_set *host_set = dev_instance;
1da177e4 LT	244	unsigned int i;
	245	unsigned int handled = 0;
	246	unsigned long flags;
	247
	248	spin_lock_irqsave(&host_set->lock, flags);
	249
	250	for (i = 0; i < host_set->n_ports; i++) {
	251	struct ata_port *ap;
	252
	253	ap = host_set->ports[i];
c1389503	254	if (ap &&
029f5468	255	!(ap->flags & ATA_FLAG_DISABLED)) {
1da177e4 LT	256	struct ata_queued_cmd *qc;
	257
	258	qc = ata_qc_from_tag(ap, ap->active_tag);
e50362ec	259	if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
1da177e4	260	handled += ata_host_intr(ap, qc);
b887030a AC	261	else
	262	// No request pending? Clear interrupt status
	263	// anyway, in case there's one pending.
	264	ap->ops->check_status(ap);
1da177e4 LT	265	}
	266
	267	}
	268
1da177e4 LT	269	spin_unlock_irqrestore(&host_set->lock, flags);
	270
	271	return IRQ_RETVAL(handled);
	272	}
	273
	274	static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg)
	275	{
1da177e4 LT	276	if (sc_reg > SCR_CONTROL)
	277	return 0xffffffffU;
	278
02cbd926	279	return ioread32((void __iomem )ap->ioaddr.scr_addr + (sc_reg 4));
1da177e4 LT	280	}
	281
	282	static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
	283	{
1da177e4 LT	284	if (sc_reg > SCR_CONTROL)
	285	return;
	286
02cbd926	287	iowrite32(val, (void __iomem )ap->ioaddr.scr_addr + (sc_reg 4));
1da177e4 LT	288	}
	289
	290	static void nv_host_stop (struct ata_host_set *host_set)
	291	{
	292	struct nv_host *host = host_set->private_data;
	293
1da177e4	294	kfree(host);
aa8f0dc6	295
02cbd926	296	ata_pci_host_stop(host_set);
1da177e4 LT	297	}
	298
	299	static int nv_init_one (struct pci_dev pdev, const struct pci_device_id ent)
	300	{
	301	static int printed_version = 0;
	302	struct nv_host *host;
	303	struct ata_port_info *ppi;
	304	struct ata_probe_ent *probe_ent;
	305	int pci_dev_busy = 0;
	306	int rc;
	307	u32 bar;
02cbd926	308	unsigned long base;
1da177e4 LT	309
	310	// Make sure this is a SATA controller by counting the number of bars
	311	// (NVIDIA SATA controllers will always have six bars). Otherwise,
	312	// it's an IDE controller and we ignore it.
	313	for (bar=0; bar<6; bar++)
	314	if (pci_resource_start(pdev, bar) == 0)
	315	return -ENODEV;
	316
	317	if (!printed_version++)
a9524a76	318	dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 LT	319
	320	rc = pci_enable_device(pdev);
	321	if (rc)
	322	goto err_out;
	323
	324	rc = pci_request_regions(pdev, DRV_NAME);
	325	if (rc) {
	326	pci_dev_busy = 1;
	327	goto err_out_disable;
	328	}
	329
	330	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	331	if (rc)
	332	goto err_out_regions;
	333	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	334	if (rc)
	335	goto err_out_regions;
	336
	337	rc = -ENOMEM;
	338
	339	ppi = &nv_port_info;
47a86593	340	probe_ent = ata_pci_init_native_mode(pdev, &ppi, ATA_PORT_PRIMARY \| ATA_PORT_SECONDARY);
1da177e4 LT	341	if (!probe_ent)
	342	goto err_out_regions;
	343
	344	host = kmalloc(sizeof(struct nv_host), GFP_KERNEL);
	345	if (!host)
	346	goto err_out_free_ent;
	347
	348	memset(host, 0, sizeof(struct nv_host));
	349	host->host_desc = &nv_device_tbl[ent->driver_data];
	350
	351	probe_ent->private_data = host;
	352
02cbd926 JG	353	probe_ent->mmio_base = pci_iomap(pdev, 5, 0);
	354	if (!probe_ent->mmio_base) {
	355	rc = -EIO;
	356	goto err_out_free_host;
	357	}
1da177e4	358
02cbd926	359	base = (unsigned long)probe_ent->mmio_base;
1da177e4	360
02cbd926 JG	361	probe_ent->port[0].scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
02cbd926 JG	362	probe_ent->port[1].scr_addr = base + NV_PORT1_SCR_REG_OFFSET;
1da177e4 LT	363
	364	pci_set_master(pdev);
	365
	366	rc = ata_device_add(probe_ent);
	367	if (rc != NV_PORTS)
	368	goto err_out_iounmap;
	369
1da177e4 LT	370	kfree(probe_ent);
	371
	372	return 0;
	373
	374	err_out_iounmap:
02cbd926	375	pci_iounmap(pdev, probe_ent->mmio_base);
1da177e4 LT	376	err_out_free_host:
	377	kfree(host);
	378	err_out_free_ent:
	379	kfree(probe_ent);
	380	err_out_regions:
	381	pci_release_regions(pdev);
	382	err_out_disable:
	383	if (!pci_dev_busy)
	384	pci_disable_device(pdev);
	385	err_out:
	386	return rc;
	387	}
	388
1da177e4 LT	389	static int __init nv_init(void)
	390	{
	391	return pci_module_init(&nv_pci_driver);
	392	}
	393
	394	static void __exit nv_exit(void)
	395	{
	396	pci_unregister_driver(&nv_pci_driver);
	397	}
	398
	399	module_init(nv_init);
	400	module_exit(nv_exit);