[deliverable/linux.git] / drivers / scsi / sata_nv.c

/*
 *  sata_nv.c - NVIDIA nForce SATA
 *
 *  Copyright 2004 NVIDIA Corp.  All rights reserved.
 *  Copyright 2004 Andrew Chew
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *  No hardware documentation available outside of NVIDIA.
 *  This driver programs the NVIDIA SATA controller in a similar
 *  fashion as with other PCI IDE BMDMA controllers, with a few
 *  NV-specific details such as register offsets, SATA phy location,
 *  hotplug info, etc.
 *
 */

#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME			"sata_nv"
#define DRV_VERSION			"0.9"

enum {
	NV_PORTS			= 2,
	NV_PIO_MASK			= 0x1f,
	NV_MWDMA_MASK			= 0x07,
	NV_UDMA_MASK			= 0x7f,
	NV_PORT0_SCR_REG_OFFSET		= 0x00,
	NV_PORT1_SCR_REG_OFFSET		= 0x40,

	/* INT_STATUS/ENABLE */
	NV_INT_STATUS			= 0x10,
	NV_INT_ENABLE			= 0x11,
	NV_INT_STATUS_CK804		= 0x440,
	NV_INT_ENABLE_CK804		= 0x441,

	/* INT_STATUS/ENABLE bits */
	NV_INT_DEV			= 0x01,
	NV_INT_PM			= 0x02,
	NV_INT_ADDED			= 0x04,
	NV_INT_REMOVED			= 0x08,

	NV_INT_PORT_SHIFT		= 4,	/* each port occupies 4 bits */

	NV_INT_ALL			= 0x0f,
	NV_INT_MASK			= NV_INT_DEV |
					  NV_INT_ADDED | NV_INT_REMOVED,

	/* INT_CONFIG */
	NV_INT_CONFIG			= 0x12,
	NV_INT_CONFIG_METHD		= 0x01, // 0 = INT, 1 = SMI

	// For PCI config register 20
	NV_MCP_SATA_CFG_20		= 0x50,
	NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04,
};

static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
static void nv_ck804_host_stop(struct ata_host_set *host_set);
static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance,
					struct pt_regs *regs);
static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance,
				    struct pt_regs *regs);
static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance,
				      struct pt_regs *regs);
static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg);
static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);

static void nv_nf2_freeze(struct ata_port *ap);
static void nv_nf2_thaw(struct ata_port *ap);
static void nv_ck804_freeze(struct ata_port *ap);
static void nv_ck804_thaw(struct ata_port *ap);
static void nv_error_handler(struct ata_port *ap);

enum nv_host_type
{
	GENERIC,
	NFORCE2,
	NFORCE3 = NFORCE2,	/* NF2 == NF3 as far as sata_nv is concerned */
	CK804
};

static const struct pci_device_id nv_pci_tbl[] = {
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE2 },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
	{ PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
		PCI_ANY_ID, PCI_ANY_ID,
		PCI_CLASS_STORAGE_IDE<<8, 0xffff00, GENERIC },
	{ PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
		PCI_ANY_ID, PCI_ANY_ID,
		PCI_CLASS_STORAGE_RAID<<8, 0xffff00, GENERIC },
	{ 0, } /* terminate list */
};

static struct pci_driver nv_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= nv_pci_tbl,
	.probe			= nv_init_one,
	.remove			= ata_pci_remove_one,
};

static struct scsi_host_template nv_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.slave_destroy		= ata_scsi_slave_destroy,
	.bios_param		= ata_std_bios_param,
};

static const struct ata_port_operations nv_generic_ops = {
	.port_disable		= ata_port_disable,
	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.exec_command		= ata_exec_command,
	.check_status		= ata_check_status,
	.dev_select		= ata_std_dev_select,
	.bmdma_setup		= ata_bmdma_setup,
	.bmdma_start		= ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
	.freeze			= ata_bmdma_freeze,
	.thaw			= ata_bmdma_thaw,
	.error_handler		= nv_error_handler,
	.post_internal_cmd	= ata_bmdma_post_internal_cmd,
	.data_xfer		= ata_pio_data_xfer,
	.irq_handler		= nv_generic_interrupt,
	.irq_clear		= ata_bmdma_irq_clear,
	.scr_read		= nv_scr_read,
	.scr_write		= nv_scr_write,
	.port_start		= ata_port_start,
	.port_stop		= ata_port_stop,
	.host_stop		= ata_pci_host_stop,
};

static const struct ata_port_operations nv_nf2_ops = {
	.port_disable		= ata_port_disable,
	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.exec_command		= ata_exec_command,
	.check_status		= ata_check_status,
	.dev_select		= ata_std_dev_select,
	.bmdma_setup		= ata_bmdma_setup,
	.bmdma_start		= ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
	.freeze			= nv_nf2_freeze,
	.thaw			= nv_nf2_thaw,
	.error_handler		= nv_error_handler,
	.post_internal_cmd	= ata_bmdma_post_internal_cmd,
	.data_xfer		= ata_pio_data_xfer,
	.irq_handler		= nv_nf2_interrupt,
	.irq_clear		= ata_bmdma_irq_clear,
	.scr_read		= nv_scr_read,
	.scr_write		= nv_scr_write,
	.port_start		= ata_port_start,
	.port_stop		= ata_port_stop,
	.host_stop		= ata_pci_host_stop,
};

static const struct ata_port_operations nv_ck804_ops = {
	.port_disable		= ata_port_disable,
	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.exec_command		= ata_exec_command,
	.check_status		= ata_check_status,
	.dev_select		= ata_std_dev_select,
	.bmdma_setup		= ata_bmdma_setup,
	.bmdma_start		= ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
	.freeze			= nv_ck804_freeze,
	.thaw			= nv_ck804_thaw,
	.error_handler		= nv_error_handler,
	.post_internal_cmd	= ata_bmdma_post_internal_cmd,
	.data_xfer		= ata_pio_data_xfer,
	.irq_handler		= nv_ck804_interrupt,
	.irq_clear		= ata_bmdma_irq_clear,
	.scr_read		= nv_scr_read,
	.scr_write		= nv_scr_write,
	.port_start		= ata_port_start,
	.port_stop		= ata_port_stop,
	.host_stop		= nv_ck804_host_stop,
};

static struct ata_port_info nv_port_info[] = {
	/* generic */
	{
		.sht		= &nv_sht,
		.host_flags	= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
		.pio_mask	= NV_PIO_MASK,
		.mwdma_mask	= NV_MWDMA_MASK,
		.udma_mask	= NV_UDMA_MASK,
		.port_ops	= &nv_generic_ops,
	},
	/* nforce2/3 */
	{
		.sht		= &nv_sht,
		.host_flags	= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
		.pio_mask	= NV_PIO_MASK,
		.mwdma_mask	= NV_MWDMA_MASK,
		.udma_mask	= NV_UDMA_MASK,
		.port_ops	= &nv_nf2_ops,
	},
	/* ck804 */
	{
		.sht		= &nv_sht,
		.host_flags	= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
		.pio_mask	= NV_PIO_MASK,
		.mwdma_mask	= NV_MWDMA_MASK,
		.udma_mask	= NV_UDMA_MASK,
		.port_ops	= &nv_ck804_ops,
	},
};

MODULE_AUTHOR("NVIDIA");
MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
MODULE_VERSION(DRV_VERSION);

static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance,
					struct pt_regs *regs)
{
	struct ata_host_set *host_set = dev_instance;
	unsigned int i;
	unsigned int handled = 0;
	unsigned long flags;

	spin_lock_irqsave(&host_set->lock, flags);

	for (i = 0; i < host_set->n_ports; i++) {
		struct ata_port *ap;

		ap = host_set->ports[i];
		if (ap &&
		    !(ap->flags & ATA_FLAG_DISABLED)) {
			struct ata_queued_cmd *qc;

			qc = ata_qc_from_tag(ap, ap->active_tag);
			if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
				handled += ata_host_intr(ap, qc);
			else
				// No request pending?  Clear interrupt status
				// anyway, in case there's one pending.
				ap->ops->check_status(ap);
		}

	}

	spin_unlock_irqrestore(&host_set->lock, flags);

	return IRQ_RETVAL(handled);
}

static int nv_host_intr(struct ata_port *ap, u8 irq_stat)
{
	struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
	int handled;

	/* freeze if hotplugged */
	if (unlikely(irq_stat & (NV_INT_ADDED | NV_INT_REMOVED))) {
		ata_port_freeze(ap);
		return 1;
	}

	/* bail out if not our interrupt */
	if (!(irq_stat & NV_INT_DEV))
		return 0;

	/* DEV interrupt w/ no active qc? */
	if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
		ata_check_status(ap);
		return 1;
	}

	/* handle interrupt */
	handled = ata_host_intr(ap, qc);
	if (unlikely(!handled)) {
		/* spurious, clear it */
		ata_check_status(ap);
	}

	return 1;
}

static irqreturn_t nv_do_interrupt(struct ata_host_set *host_set, u8 irq_stat)
{
	int i, handled = 0;

	for (i = 0; i < host_set->n_ports; i++) {
		struct ata_port *ap = host_set->ports[i];

		if (ap && !(ap->flags & ATA_FLAG_DISABLED))
			handled += nv_host_intr(ap, irq_stat);

		irq_stat >>= NV_INT_PORT_SHIFT;
	}

	return IRQ_RETVAL(handled);
}

static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance,
				    struct pt_regs *regs)
{
	struct ata_host_set *host_set = dev_instance;
	u8 irq_stat;
	irqreturn_t ret;

	spin_lock(&host_set->lock);
	irq_stat = inb(host_set->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
	ret = nv_do_interrupt(host_set, irq_stat);
	spin_unlock(&host_set->lock);

	return ret;
}

static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance,
				      struct pt_regs *regs)
{
	struct ata_host_set *host_set = dev_instance;
	u8 irq_stat;
	irqreturn_t ret;

	spin_lock(&host_set->lock);
	irq_stat = readb(host_set->mmio_base + NV_INT_STATUS_CK804);
	ret = nv_do_interrupt(host_set, irq_stat);
	spin_unlock(&host_set->lock);

	return ret;
}

static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg)
{
	if (sc_reg > SCR_CONTROL)
		return 0xffffffffU;

	return ioread32((void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
}

static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
{
	if (sc_reg > SCR_CONTROL)
		return;

	iowrite32(val, (void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
}

static void nv_nf2_freeze(struct ata_port *ap)
{
	unsigned long scr_addr = ap->host_set->ports[0]->ioaddr.scr_addr;
	int shift = ap->port_no * NV_INT_PORT_SHIFT;
	u8 mask;

	mask = inb(scr_addr + NV_INT_ENABLE);
	mask &= ~(NV_INT_ALL << shift);
	outb(mask, scr_addr + NV_INT_ENABLE);
}

static void nv_nf2_thaw(struct ata_port *ap)
{
	unsigned long scr_addr = ap->host_set->ports[0]->ioaddr.scr_addr;
	int shift = ap->port_no * NV_INT_PORT_SHIFT;
	u8 mask;

	outb(NV_INT_ALL << shift, scr_addr + NV_INT_STATUS);

	mask = inb(scr_addr + NV_INT_ENABLE);
	mask |= (NV_INT_MASK << shift);
	outb(mask, scr_addr + NV_INT_ENABLE);
}

static void nv_ck804_freeze(struct ata_port *ap)
{
	void __iomem *mmio_base = ap->host_set->mmio_base;
	int shift = ap->port_no * NV_INT_PORT_SHIFT;
	u8 mask;

	mask = readb(mmio_base + NV_INT_ENABLE_CK804);
	mask &= ~(NV_INT_ALL << shift);
	writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
}

static void nv_ck804_thaw(struct ata_port *ap)
{
	void __iomem *mmio_base = ap->host_set->mmio_base;
	int shift = ap->port_no * NV_INT_PORT_SHIFT;
	u8 mask;

	writeb(NV_INT_ALL << shift, mmio_base + NV_INT_STATUS_CK804);

	mask = readb(mmio_base + NV_INT_ENABLE_CK804);
	mask |= (NV_INT_MASK << shift);
	writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
}

static int nv_hardreset(struct ata_port *ap, unsigned int *class)
{
	unsigned int dummy;

	/* SATA hardreset fails to retrieve proper device signature on
	 * some controllers.  Don't classify on hardreset.  For more
	 * info, see http://bugme.osdl.org/show_bug.cgi?id=3352
	 */
	return sata_std_hardreset(ap, &dummy);
}

static void nv_error_handler(struct ata_port *ap)
{
	ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,
			   nv_hardreset, ata_std_postreset);
}

static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static int printed_version = 0;
	struct ata_port_info *ppi;
	struct ata_probe_ent *probe_ent;
	int pci_dev_busy = 0;
	int rc;
	u32 bar;
	unsigned long base;

        // Make sure this is a SATA controller by counting the number of bars
        // (NVIDIA SATA controllers will always have six bars).  Otherwise,
        // it's an IDE controller and we ignore it.
	for (bar=0; bar<6; bar++)
		if (pci_resource_start(pdev, bar) == 0)
			return -ENODEV;

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");

	rc = pci_enable_device(pdev);
	if (rc)
		goto err_out;

	rc = pci_request_regions(pdev, DRV_NAME);
	if (rc) {
		pci_dev_busy = 1;
		goto err_out_disable;
	}

	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		goto err_out_regions;
	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		goto err_out_regions;

	rc = -ENOMEM;

	ppi = &nv_port_info[ent->driver_data];
	probe_ent = ata_pci_init_native_mode(pdev, &ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
	if (!probe_ent)
		goto err_out_regions;

	probe_ent->mmio_base = pci_iomap(pdev, 5, 0);
	if (!probe_ent->mmio_base) {
		rc = -EIO;
		goto err_out_free_ent;
	}

	base = (unsigned long)probe_ent->mmio_base;

	probe_ent->port[0].scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
	probe_ent->port[1].scr_addr = base + NV_PORT1_SCR_REG_OFFSET;

	/* enable SATA space for CK804 */
	if (ent->driver_data == CK804) {
		u8 regval;

		pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
		regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
		pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
	}

	pci_set_master(pdev);

	rc = ata_device_add(probe_ent);
	if (rc != NV_PORTS)
		goto err_out_iounmap;

	kfree(probe_ent);

	return 0;

err_out_iounmap:
	pci_iounmap(pdev, probe_ent->mmio_base);
err_out_free_ent:
	kfree(probe_ent);
err_out_regions:
	pci_release_regions(pdev);
err_out_disable:
	if (!pci_dev_busy)
		pci_disable_device(pdev);
err_out:
	return rc;
}

static void nv_ck804_host_stop(struct ata_host_set *host_set)
{
	struct pci_dev *pdev = to_pci_dev(host_set->dev);
	u8 regval;

	/* disable SATA space for CK804 */
	pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
	regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
	pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);

	ata_pci_host_stop(host_set);
}

static int __init nv_init(void)
{
	return pci_module_init(&nv_pci_driver);
}

static void __exit nv_exit(void)
{
	pci_unregister_driver(&nv_pci_driver);
}

module_init(nv_init);
module_exit(nv_exit);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* sata_nv.c - NVIDIA nForce SATA
	3	*
	4	* Copyright 2004 NVIDIA Corp. All rights reserved.
	5	* Copyright 2004 Andrew Chew
	6	*
aa7e16d6 JG	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2, or (at your option)
	11	* any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; see the file COPYING. If not, write to
	20	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
1da177e4	21	*
af36d7f0 JG	22	*
	23	* libata documentation is available via 'make {ps\|pdf}docs',
	24	* as Documentation/DocBook/libata.*
	25	*
	26	* No hardware documentation available outside of NVIDIA.
	27	* This driver programs the NVIDIA SATA controller in a similar
	28	* fashion as with other PCI IDE BMDMA controllers, with a few
	29	* NV-specific details such as register offsets, SATA phy location,
	30	* hotplug info, etc.
	31	*
1da177e4 LT	32	*/
	33
	34	#include <linux/config.h>
	35	#include <linux/kernel.h>
	36	#include <linux/module.h>
	37	#include <linux/pci.h>
	38	#include <linux/init.h>
	39	#include <linux/blkdev.h>
	40	#include <linux/delay.h>
	41	#include <linux/interrupt.h>
a9524a76	42	#include <linux/device.h>
1da177e4 LT	43	#include <scsi/scsi_host.h>
	44	#include <linux/libata.h>
	45
	46	#define DRV_NAME "sata_nv"
af64371a	47	#define DRV_VERSION "0.9"
1da177e4	48
10ad05df JG	49	enum {
	50	NV_PORTS = 2,
	51	NV_PIO_MASK = 0x1f,
	52	NV_MWDMA_MASK = 0x07,
	53	NV_UDMA_MASK = 0x7f,
	54	NV_PORT0_SCR_REG_OFFSET = 0x00,
	55	NV_PORT1_SCR_REG_OFFSET = 0x40,
1da177e4	56
27e4b274	57	/* INT_STATUS/ENABLE */
10ad05df	58	NV_INT_STATUS = 0x10,
10ad05df	59	NV_INT_ENABLE = 0x11,
27e4b274	60	NV_INT_STATUS_CK804 = 0x440,
10ad05df	61	NV_INT_ENABLE_CK804 = 0x441,
1da177e4	62
27e4b274 TH	63	/* INT_STATUS/ENABLE bits */
	64	NV_INT_DEV = 0x01,
	65	NV_INT_PM = 0x02,
	66	NV_INT_ADDED = 0x04,
	67	NV_INT_REMOVED = 0x08,
	68
	69	NV_INT_PORT_SHIFT = 4, /* each port occupies 4 bits */
	70
39f87582	71	NV_INT_ALL = 0x0f,
5a44efff TH	72	NV_INT_MASK = NV_INT_DEV \|
5a44efff TH	73	NV_INT_ADDED \| NV_INT_REMOVED,
39f87582	74
27e4b274	75	/* INT_CONFIG */
10ad05df JG	76	NV_INT_CONFIG = 0x12,
10ad05df JG	77	NV_INT_CONFIG_METHD = 0x01, // 0 = INT, 1 = SMI
1da177e4	78
10ad05df JG	79	// For PCI config register 20
	80	NV_MCP_SATA_CFG_20 = 0x50,
	81	NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04,
	82	};
1da177e4 LT	83
1da177e4 LT	84	static int nv_init_one (struct pci_dev pdev, const struct pci_device_id ent);
ada364e8 TH	85	static void nv_ck804_host_stop(struct ata_host_set *host_set);
	86	static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance,
	87	struct pt_regs *regs);
	88	static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance,
	89	struct pt_regs *regs);
	90	static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance,
	91	struct pt_regs *regs);
1da177e4 LT	92	static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg);
1da177e4 LT	93	static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
1da177e4	94
39f87582 TH	95	static void nv_nf2_freeze(struct ata_port *ap);
	96	static void nv_nf2_thaw(struct ata_port *ap);
	97	static void nv_ck804_freeze(struct ata_port *ap);
	98	static void nv_ck804_thaw(struct ata_port *ap);
	99	static void nv_error_handler(struct ata_port *ap);
	100
1da177e4 LT	101	enum nv_host_type
	102	{
	103	GENERIC,
	104	NFORCE2,
27e4b274	105	NFORCE3 = NFORCE2, /* NF2 == NF3 as far as sata_nv is concerned */
e710245b	106	CK804
1da177e4 LT	107	};
1da177e4 LT	108
3b7d697d	109	static const struct pci_device_id nv_pci_tbl[] = {
1da177e4 LT	110	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA,
	111	PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE2 },
	112	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA,
	113	PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
	114	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2,
	115	PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
	116	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA,
	117	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
	118	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2,
	119	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
	120	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA,
	121	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
	122	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2,
	123	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
541134cf	124	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA,
e710245b	125	PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
541134cf	126	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2,
e710245b	127	PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
541134cf	128	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA,
e710245b	129	PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
e86ee668	130	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2,
e710245b	131	PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
4c5c8161 AC	132	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA,
	133	PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
	134	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2,
	135	PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
	136	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3,
	137	PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
1da177e4 LT	138	{ PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
	139	PCI_ANY_ID, PCI_ANY_ID,
	140	PCI_CLASS_STORAGE_IDE<<8, 0xffff00, GENERIC },
541134cf DD	141	{ PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
	142	PCI_ANY_ID, PCI_ANY_ID,
	143	PCI_CLASS_STORAGE_RAID<<8, 0xffff00, GENERIC },
1da177e4 LT	144	{ 0, } /* terminate list */
	145	};
	146
1da177e4 LT	147	static struct pci_driver nv_pci_driver = {
	148	.name = DRV_NAME,
	149	.id_table = nv_pci_tbl,
	150	.probe = nv_init_one,
	151	.remove = ata_pci_remove_one,
	152	};
	153
193515d5	154	static struct scsi_host_template nv_sht = {
1da177e4 LT	155	.module = THIS_MODULE,
	156	.name = DRV_NAME,
	157	.ioctl = ata_scsi_ioctl,
	158	.queuecommand = ata_scsi_queuecmd,
1da177e4 LT	159	.can_queue = ATA_DEF_QUEUE,
	160	.this_id = ATA_SHT_THIS_ID,
	161	.sg_tablesize = LIBATA_MAX_PRD,
1da177e4 LT	162	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	163	.emulated = ATA_SHT_EMULATED,
	164	.use_clustering = ATA_SHT_USE_CLUSTERING,
	165	.proc_name = DRV_NAME,
	166	.dma_boundary = ATA_DMA_BOUNDARY,
	167	.slave_configure = ata_scsi_slave_config,
ccf68c34	168	.slave_destroy = ata_scsi_slave_destroy,
1da177e4	169	.bios_param = ata_std_bios_param,
1da177e4 LT	170	};
1da177e4 LT	171
ada364e8	172	static const struct ata_port_operations nv_generic_ops = {
1da177e4 LT	173	.port_disable = ata_port_disable,
	174	.tf_load = ata_tf_load,
	175	.tf_read = ata_tf_read,
	176	.exec_command = ata_exec_command,
	177	.check_status = ata_check_status,
	178	.dev_select = ata_std_dev_select,
1da177e4 LT	179	.bmdma_setup = ata_bmdma_setup,
	180	.bmdma_start = ata_bmdma_start,
	181	.bmdma_stop = ata_bmdma_stop,
	182	.bmdma_status = ata_bmdma_status,
	183	.qc_prep = ata_qc_prep,
	184	.qc_issue = ata_qc_issue_prot,
39f87582 TH	185	.freeze = ata_bmdma_freeze,
	186	.thaw = ata_bmdma_thaw,
	187	.error_handler = nv_error_handler,
	188	.post_internal_cmd = ata_bmdma_post_internal_cmd,
a6b2c5d4	189	.data_xfer = ata_pio_data_xfer,
ada364e8	190	.irq_handler = nv_generic_interrupt,
1da177e4 LT	191	.irq_clear = ata_bmdma_irq_clear,
	192	.scr_read = nv_scr_read,
	193	.scr_write = nv_scr_write,
	194	.port_start = ata_port_start,
	195	.port_stop = ata_port_stop,
e6faf082	196	.host_stop = ata_pci_host_stop,
1da177e4 LT	197	};
1da177e4 LT	198
ada364e8 TH	199	static const struct ata_port_operations nv_nf2_ops = {
	200	.port_disable = ata_port_disable,
	201	.tf_load = ata_tf_load,
	202	.tf_read = ata_tf_read,
	203	.exec_command = ata_exec_command,
	204	.check_status = ata_check_status,
	205	.dev_select = ata_std_dev_select,
ada364e8 TH	206	.bmdma_setup = ata_bmdma_setup,
	207	.bmdma_start = ata_bmdma_start,
	208	.bmdma_stop = ata_bmdma_stop,
	209	.bmdma_status = ata_bmdma_status,
	210	.qc_prep = ata_qc_prep,
	211	.qc_issue = ata_qc_issue_prot,
39f87582 TH	212	.freeze = nv_nf2_freeze,
	213	.thaw = nv_nf2_thaw,
	214	.error_handler = nv_error_handler,
	215	.post_internal_cmd = ata_bmdma_post_internal_cmd,
ada364e8 TH	216	.data_xfer = ata_pio_data_xfer,
	217	.irq_handler = nv_nf2_interrupt,
	218	.irq_clear = ata_bmdma_irq_clear,
	219	.scr_read = nv_scr_read,
	220	.scr_write = nv_scr_write,
	221	.port_start = ata_port_start,
	222	.port_stop = ata_port_stop,
	223	.host_stop = ata_pci_host_stop,
	224	};
	225
	226	static const struct ata_port_operations nv_ck804_ops = {
	227	.port_disable = ata_port_disable,
	228	.tf_load = ata_tf_load,
	229	.tf_read = ata_tf_read,
	230	.exec_command = ata_exec_command,
	231	.check_status = ata_check_status,
	232	.dev_select = ata_std_dev_select,
ada364e8 TH	233	.bmdma_setup = ata_bmdma_setup,
	234	.bmdma_start = ata_bmdma_start,
	235	.bmdma_stop = ata_bmdma_stop,
	236	.bmdma_status = ata_bmdma_status,
	237	.qc_prep = ata_qc_prep,
	238	.qc_issue = ata_qc_issue_prot,
39f87582 TH	239	.freeze = nv_ck804_freeze,
	240	.thaw = nv_ck804_thaw,
	241	.error_handler = nv_error_handler,
	242	.post_internal_cmd = ata_bmdma_post_internal_cmd,
ada364e8 TH	243	.data_xfer = ata_pio_data_xfer,
	244	.irq_handler = nv_ck804_interrupt,
	245	.irq_clear = ata_bmdma_irq_clear,
	246	.scr_read = nv_scr_read,
	247	.scr_write = nv_scr_write,
	248	.port_start = ata_port_start,
	249	.port_stop = ata_port_stop,
	250	.host_stop = nv_ck804_host_stop,
	251	};
	252
ada364e8 TH	253	static struct ata_port_info nv_port_info[] = {
	254	/* generic */
	255	{
	256	.sht = &nv_sht,
39f87582	257	.host_flags = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY,
ada364e8 TH	258	.pio_mask = NV_PIO_MASK,
	259	.mwdma_mask = NV_MWDMA_MASK,
	260	.udma_mask = NV_UDMA_MASK,
	261	.port_ops = &nv_generic_ops,
	262	},
	263	/* nforce2/3 */
	264	{
	265	.sht = &nv_sht,
39f87582	266	.host_flags = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY,
ada364e8 TH	267	.pio_mask = NV_PIO_MASK,
	268	.mwdma_mask = NV_MWDMA_MASK,
	269	.udma_mask = NV_UDMA_MASK,
	270	.port_ops = &nv_nf2_ops,
	271	},
	272	/* ck804 */
	273	{
	274	.sht = &nv_sht,
39f87582	275	.host_flags = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY,
ada364e8 TH	276	.pio_mask = NV_PIO_MASK,
	277	.mwdma_mask = NV_MWDMA_MASK,
	278	.udma_mask = NV_UDMA_MASK,
	279	.port_ops = &nv_ck804_ops,
	280	},
1da177e4 LT	281	};
	282
	283	MODULE_AUTHOR("NVIDIA");
	284	MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
	285	MODULE_LICENSE("GPL");
	286	MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
	287	MODULE_VERSION(DRV_VERSION);
	288
ada364e8 TH	289	static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance,
ada364e8 TH	290	struct pt_regs *regs)
1da177e4 LT	291	{
1da177e4 LT	292	struct ata_host_set *host_set = dev_instance;
1da177e4 LT	293	unsigned int i;
	294	unsigned int handled = 0;
	295	unsigned long flags;
	296
	297	spin_lock_irqsave(&host_set->lock, flags);
	298
	299	for (i = 0; i < host_set->n_ports; i++) {
	300	struct ata_port *ap;
	301
	302	ap = host_set->ports[i];
c1389503	303	if (ap &&
029f5468	304	!(ap->flags & ATA_FLAG_DISABLED)) {
1da177e4 LT	305	struct ata_queued_cmd *qc;
	306
	307	qc = ata_qc_from_tag(ap, ap->active_tag);
e50362ec	308	if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
1da177e4	309	handled += ata_host_intr(ap, qc);
b887030a AC	310	else
	311	// No request pending? Clear interrupt status
	312	// anyway, in case there's one pending.
	313	ap->ops->check_status(ap);
1da177e4 LT	314	}
	315
	316	}
	317
1da177e4 LT	318	spin_unlock_irqrestore(&host_set->lock, flags);
	319
	320	return IRQ_RETVAL(handled);
	321	}
	322
ada364e8 TH	323	static int nv_host_intr(struct ata_port *ap, u8 irq_stat)
	324	{
	325	struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
	326	int handled;
	327
5a44efff TH	328	/* freeze if hotplugged */
	329	if (unlikely(irq_stat & (NV_INT_ADDED \| NV_INT_REMOVED))) {
	330	ata_port_freeze(ap);
	331	return 1;
	332	}
	333
ada364e8 TH	334	/* bail out if not our interrupt */
	335	if (!(irq_stat & NV_INT_DEV))
	336	return 0;
	337
	338	/* DEV interrupt w/ no active qc? */
	339	if (unlikely(!qc \|\| (qc->tf.flags & ATA_TFLAG_POLLING))) {
	340	ata_check_status(ap);
	341	return 1;
	342	}
	343
	344	/* handle interrupt */
	345	handled = ata_host_intr(ap, qc);
	346	if (unlikely(!handled)) {
	347	/* spurious, clear it */
	348	ata_check_status(ap);
	349	}
	350
	351	return 1;
	352	}
	353
	354	static irqreturn_t nv_do_interrupt(struct ata_host_set *host_set, u8 irq_stat)
	355	{
	356	int i, handled = 0;
	357
	358	for (i = 0; i < host_set->n_ports; i++) {
	359	struct ata_port *ap = host_set->ports[i];
	360
	361	if (ap && !(ap->flags & ATA_FLAG_DISABLED))
	362	handled += nv_host_intr(ap, irq_stat);
	363
	364	irq_stat >>= NV_INT_PORT_SHIFT;
	365	}
	366
	367	return IRQ_RETVAL(handled);
	368	}
	369
	370	static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance,
	371	struct pt_regs *regs)
	372	{
	373	struct ata_host_set *host_set = dev_instance;
ada364e8 TH	374	u8 irq_stat;
	375	irqreturn_t ret;
	376
c5fa46e1	377	spin_lock(&host_set->lock);
ada364e8 TH	378	irq_stat = inb(host_set->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
ada364e8 TH	379	ret = nv_do_interrupt(host_set, irq_stat);
c5fa46e1	380	spin_unlock(&host_set->lock);
ada364e8 TH	381
	382	return ret;
	383	}
	384
	385	static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance,
	386	struct pt_regs *regs)
	387	{
	388	struct ata_host_set *host_set = dev_instance;
ada364e8 TH	389	u8 irq_stat;
	390	irqreturn_t ret;
	391
c5fa46e1	392	spin_lock(&host_set->lock);
ada364e8 TH	393	irq_stat = readb(host_set->mmio_base + NV_INT_STATUS_CK804);
ada364e8 TH	394	ret = nv_do_interrupt(host_set, irq_stat);
c5fa46e1	395	spin_unlock(&host_set->lock);
ada364e8 TH	396
	397	return ret;
	398	}
	399
1da177e4 LT	400	static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg)
1da177e4 LT	401	{
1da177e4 LT	402	if (sc_reg > SCR_CONTROL)
	403	return 0xffffffffU;
	404
02cbd926	405	return ioread32((void __iomem )ap->ioaddr.scr_addr + (sc_reg 4));
1da177e4 LT	406	}
	407
	408	static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
	409	{
1da177e4 LT	410	if (sc_reg > SCR_CONTROL)
	411	return;
	412
02cbd926	413	iowrite32(val, (void __iomem )ap->ioaddr.scr_addr + (sc_reg 4));
1da177e4 LT	414	}
1da177e4 LT	415
39f87582 TH	416	static void nv_nf2_freeze(struct ata_port *ap)
	417	{
	418	unsigned long scr_addr = ap->host_set->ports[0]->ioaddr.scr_addr;
	419	int shift = ap->port_no * NV_INT_PORT_SHIFT;
	420	u8 mask;
	421
	422	mask = inb(scr_addr + NV_INT_ENABLE);
	423	mask &= ~(NV_INT_ALL << shift);
	424	outb(mask, scr_addr + NV_INT_ENABLE);
	425	}
	426
	427	static void nv_nf2_thaw(struct ata_port *ap)
	428	{
	429	unsigned long scr_addr = ap->host_set->ports[0]->ioaddr.scr_addr;
	430	int shift = ap->port_no * NV_INT_PORT_SHIFT;
	431	u8 mask;
	432
	433	outb(NV_INT_ALL << shift, scr_addr + NV_INT_STATUS);
	434
	435	mask = inb(scr_addr + NV_INT_ENABLE);
	436	mask \|= (NV_INT_MASK << shift);
	437	outb(mask, scr_addr + NV_INT_ENABLE);
	438	}
	439
	440	static void nv_ck804_freeze(struct ata_port *ap)
	441	{
	442	void __iomem *mmio_base = ap->host_set->mmio_base;
	443	int shift = ap->port_no * NV_INT_PORT_SHIFT;
	444	u8 mask;
	445
	446	mask = readb(mmio_base + NV_INT_ENABLE_CK804);
	447	mask &= ~(NV_INT_ALL << shift);
	448	writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
	449	}
	450
	451	static void nv_ck804_thaw(struct ata_port *ap)
	452	{
	453	void __iomem *mmio_base = ap->host_set->mmio_base;
	454	int shift = ap->port_no * NV_INT_PORT_SHIFT;
	455	u8 mask;
	456
	457	writeb(NV_INT_ALL << shift, mmio_base + NV_INT_STATUS_CK804);
	458
	459	mask = readb(mmio_base + NV_INT_ENABLE_CK804);
	460	mask \|= (NV_INT_MASK << shift);
	461	writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
	462	}
	463
	464	static int nv_hardreset(struct ata_port ap, unsigned int class)
	465	{
	466	unsigned int dummy;
	467
	468	/* SATA hardreset fails to retrieve proper device signature on
	469	* some controllers. Don't classify on hardreset. For more
	470	* info, see http://bugme.osdl.org/show_bug.cgi?id=3352
	471	*/
	472	return sata_std_hardreset(ap, &dummy);
	473	}
	474
	475	static void nv_error_handler(struct ata_port *ap)
	476	{
	477	ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,
	478	nv_hardreset, ata_std_postreset);
	479	}
480
1da177e4 LT	481	static int nv_init_one (struct pci_dev pdev, const struct pci_device_id ent)
	482	{
	483	static int printed_version = 0;
1da177e4 LT	484	struct ata_port_info *ppi;
	485	struct ata_probe_ent *probe_ent;
	486	int pci_dev_busy = 0;
	487	int rc;
	488	u32 bar;
02cbd926	489	unsigned long base;
1da177e4 LT	490
	491	// Make sure this is a SATA controller by counting the number of bars
	492	// (NVIDIA SATA controllers will always have six bars). Otherwise,
	493	// it's an IDE controller and we ignore it.
	494	for (bar=0; bar<6; bar++)
	495	if (pci_resource_start(pdev, bar) == 0)
	496	return -ENODEV;
	497
	498	if (!printed_version++)
a9524a76	499	dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 LT	500
	501	rc = pci_enable_device(pdev);
	502	if (rc)
	503	goto err_out;
	504
	505	rc = pci_request_regions(pdev, DRV_NAME);
	506	if (rc) {
	507	pci_dev_busy = 1;
	508	goto err_out_disable;
	509	}
	510
	511	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	512	if (rc)
	513	goto err_out_regions;
	514	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	515	if (rc)
	516	goto err_out_regions;
	517
	518	rc = -ENOMEM;
	519
ada364e8	520	ppi = &nv_port_info[ent->driver_data];
47a86593	521	probe_ent = ata_pci_init_native_mode(pdev, &ppi, ATA_PORT_PRIMARY \| ATA_PORT_SECONDARY);
1da177e4 LT	522	if (!probe_ent)
	523	goto err_out_regions;
	524
02cbd926 JG	525	probe_ent->mmio_base = pci_iomap(pdev, 5, 0);
	526	if (!probe_ent->mmio_base) {
	527	rc = -EIO;
e6faf082	528	goto err_out_free_ent;
02cbd926	529	}
1da177e4	530
02cbd926	531	base = (unsigned long)probe_ent->mmio_base;
1da177e4	532
02cbd926 JG	533	probe_ent->port[0].scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
02cbd926 JG	534	probe_ent->port[1].scr_addr = base + NV_PORT1_SCR_REG_OFFSET;
1da177e4	535
ada364e8 TH	536	/* enable SATA space for CK804 */
	537	if (ent->driver_data == CK804) {
	538	u8 regval;
	539
	540	pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
	541	regval \|= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
	542	pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
	543	}
	544
1da177e4 LT	545	pci_set_master(pdev);
	546
	547	rc = ata_device_add(probe_ent);
	548	if (rc != NV_PORTS)
	549	goto err_out_iounmap;
	550
1da177e4 LT	551	kfree(probe_ent);
	552
	553	return 0;
	554
	555	err_out_iounmap:
02cbd926	556	pci_iounmap(pdev, probe_ent->mmio_base);
1da177e4 LT	557	err_out_free_ent:
	558	kfree(probe_ent);
	559	err_out_regions:
	560	pci_release_regions(pdev);
	561	err_out_disable:
	562	if (!pci_dev_busy)
	563	pci_disable_device(pdev);
	564	err_out:
	565	return rc;
	566	}
	567
ada364e8 TH	568	static void nv_ck804_host_stop(struct ata_host_set *host_set)
	569	{
	570	struct pci_dev *pdev = to_pci_dev(host_set->dev);
	571	u8 regval;
	572
	573	/* disable SATA space for CK804 */
	574	pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
	575	regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
	576	pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
	577
	578	ata_pci_host_stop(host_set);
	579	}
	580
1da177e4 LT	581	static int __init nv_init(void)
	582	{
	583	return pci_module_init(&nv_pci_driver);
	584	}
	585
	586	static void __exit nv_exit(void)
	587	{
	588	pci_unregister_driver(&nv_pci_driver);
	589	}
	590
	591	module_init(nv_init);
	592	module_exit(nv_exit);