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[libata ata_piix] fix native mode probe, after recent updates
[deliverable/linux.git] / drivers / scsi / sata_promise.c
CommitLineData
1da177e4
LT		 1/*
2 * sata_promise.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc.
9 *
1da177e4 10 *
af36d7f0
JG		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware information only available under NDA.
1da177e4
LT		 30 *
31 */
32
33#include <linux/kernel.h>
34#include <linux/module.h>
35#include <linux/pci.h>
36#include <linux/init.h>
37#include <linux/blkdev.h>
38#include <linux/delay.h>
39#include <linux/interrupt.h>
40#include <linux/sched.h>
41#include "scsi.h"
42#include <scsi/scsi_host.h>
43#include <linux/libata.h>
44#include <asm/io.h>
45#include "sata_promise.h"
46
47#define DRV_NAME "sata_promise"
6885433c 48#define DRV_VERSION "1.02"
1da177e4
LT		 49
50
51enum {
52 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
53 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
54 PDC_TBG_MODE = 0x41, /* TBG mode */
55 PDC_FLASH_CTL = 0x44, /* Flash control register */
56 PDC_PCI_CTL = 0x48, /* PCI control and status register */
57 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
58 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
59 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
60 PDC_SLEW_CTL = 0x470, /* slew rate control reg */
61
62 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
63 (1<<8) | (1<<9) | (1<<10),
64
65 board_2037x = 0, /* FastTrak S150 TX2plus */
66 board_20319 = 1, /* FastTrak S150 TX4 */
f497ba73 67 board_20619 = 2, /* FastTrak TX4000 */
1da177e4
LT		 68
69 PDC_HAS_PATA = (1 << 1), /* PDC20375 has PATA */
70
71 PDC_RESET = (1 << 11), /* HDMA reset */
72};
73
74
75struct pdc_port_priv {
76 u8 *pkt;
77 dma_addr_t pkt_dma;
78};
79
80static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
81static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
82static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
83static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
84static void pdc_eng_timeout(struct ata_port *ap);
85static int pdc_port_start(struct ata_port *ap);
86static void pdc_port_stop(struct ata_port *ap);
2cba582a
JG		 87static void pdc_pata_phy_reset(struct ata_port *ap);
88static void pdc_sata_phy_reset(struct ata_port *ap);
1da177e4 89static void pdc_qc_prep(struct ata_queued_cmd *qc);
057ace5e
JG		 90static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
91static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
1da177e4
LT		 92static void pdc_irq_clear(struct ata_port *ap);
93static int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
94
374b1873 95
1da177e4
LT		 96static Scsi_Host_Template pdc_ata_sht = {
97 .module = THIS_MODULE,
98 .name = DRV_NAME,
99 .ioctl = ata_scsi_ioctl,
100 .queuecommand = ata_scsi_queuecmd,
101 .eh_strategy_handler = ata_scsi_error,
102 .can_queue = ATA_DEF_QUEUE,
103 .this_id = ATA_SHT_THIS_ID,
104 .sg_tablesize = LIBATA_MAX_PRD,
105 .max_sectors = ATA_MAX_SECTORS,
106 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
107 .emulated = ATA_SHT_EMULATED,
108 .use_clustering = ATA_SHT_USE_CLUSTERING,
109 .proc_name = DRV_NAME,
110 .dma_boundary = ATA_DMA_BOUNDARY,
111 .slave_configure = ata_scsi_slave_config,
112 .bios_param = ata_std_bios_param,
113 .ordered_flush = 1,
114};
115
057ace5e 116static const struct ata_port_operations pdc_sata_ops = {
1da177e4
LT		 117 .port_disable = ata_port_disable,
118 .tf_load = pdc_tf_load_mmio,
119 .tf_read = ata_tf_read,
120 .check_status = ata_check_status,
121 .exec_command = pdc_exec_command_mmio,
122 .dev_select = ata_std_dev_select,
2cba582a
JG		 123
124 .phy_reset = pdc_sata_phy_reset,
125
1da177e4
LT		 126 .qc_prep = pdc_qc_prep,
127 .qc_issue = pdc_qc_issue_prot,
128 .eng_timeout = pdc_eng_timeout,
129 .irq_handler = pdc_interrupt,
130 .irq_clear = pdc_irq_clear,
2cba582a 131
1da177e4
LT		 132 .scr_read = pdc_sata_scr_read,
133 .scr_write = pdc_sata_scr_write,
134 .port_start = pdc_port_start,
135 .port_stop = pdc_port_stop,
374b1873 136 .host_stop = ata_pci_host_stop,
1da177e4
LT		 137};
138
057ace5e 139static const struct ata_port_operations pdc_pata_ops = {
2cba582a
JG		 140 .port_disable = ata_port_disable,
141 .tf_load = pdc_tf_load_mmio,
142 .tf_read = ata_tf_read,
143 .check_status = ata_check_status,
144 .exec_command = pdc_exec_command_mmio,
145 .dev_select = ata_std_dev_select,
146
147 .phy_reset = pdc_pata_phy_reset,
148
149 .qc_prep = pdc_qc_prep,
150 .qc_issue = pdc_qc_issue_prot,
151 .eng_timeout = pdc_eng_timeout,
152 .irq_handler = pdc_interrupt,
153 .irq_clear = pdc_irq_clear,
154
155 .port_start = pdc_port_start,
156 .port_stop = pdc_port_stop,
374b1873 157 .host_stop = ata_pci_host_stop,
2cba582a
JG		 158};
159
1da177e4
LT		 160static struct ata_port_info pdc_port_info[] = {
161 /* board_2037x */
162 {
163 .sht = &pdc_ata_sht,
164 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
165 ATA_FLAG_SRST | ATA_FLAG_MMIO,
166 .pio_mask = 0x1f, /* pio0-4 */
167 .mwdma_mask = 0x07, /* mwdma0-2 */
168 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
2cba582a 169 .port_ops = &pdc_sata_ops,
1da177e4
LT		 170 },
171
172 /* board_20319 */
173 {
174 .sht = &pdc_ata_sht,
175 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
176 ATA_FLAG_SRST | ATA_FLAG_MMIO,
177 .pio_mask = 0x1f, /* pio0-4 */
178 .mwdma_mask = 0x07, /* mwdma0-2 */
179 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
2cba582a 180 .port_ops = &pdc_sata_ops,
1da177e4 181 },
f497ba73
TL		 182
183 /* board_20619 */
184 {
185 .sht = &pdc_ata_sht,
186 .host_flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SRST |
187 ATA_FLAG_MMIO | ATA_FLAG_SLAVE_POSS,
188 .pio_mask = 0x1f, /* pio0-4 */
189 .mwdma_mask = 0x07, /* mwdma0-2 */
190 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
2cba582a 191 .port_ops = &pdc_pata_ops,
f497ba73 192 },
1da177e4
LT		 193};
194
195static struct pci_device_id pdc_ata_pci_tbl[] = {
196 { PCI_VENDOR_ID_PROMISE, 0x3371, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
197 board_2037x },
07c1da23
JG		 198 { PCI_VENDOR_ID_PROMISE, 0x3570, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
199 board_2037x },
4c3a53d4
FJ		 200 { PCI_VENDOR_ID_PROMISE, 0x3571, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
201 board_2037x },
1da177e4
LT		 202 { PCI_VENDOR_ID_PROMISE, 0x3373, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
203 board_2037x },
204 { PCI_VENDOR_ID_PROMISE, 0x3375, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
205 board_2037x },
206 { PCI_VENDOR_ID_PROMISE, 0x3376, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
207 board_2037x },
208 { PCI_VENDOR_ID_PROMISE, 0x3574, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
209 board_2037x },
210 { PCI_VENDOR_ID_PROMISE, 0x3d75, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
211 board_2037x },
c45154a3
EK		 212 { PCI_VENDOR_ID_PROMISE, 0x3d73, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
213 board_2037x },
1da177e4
LT		 214
215 { PCI_VENDOR_ID_PROMISE, 0x3318, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
216 board_20319 },
217 { PCI_VENDOR_ID_PROMISE, 0x3319, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
218 board_20319 },
93090495
DD		 219 { PCI_VENDOR_ID_PROMISE, 0x3519, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
220 board_20319 },
08b791c0
OM		 221 { PCI_VENDOR_ID_PROMISE, 0x3d17, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
222 board_20319 },
1da177e4
LT		 223 { PCI_VENDOR_ID_PROMISE, 0x3d18, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
224 board_20319 },
225
f497ba73
TL		 226 { PCI_VENDOR_ID_PROMISE, 0x6629, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
227 board_20619 },
228
1da177e4
LT		 229 { } /* terminate list */
230};
231
232
233static struct pci_driver pdc_ata_pci_driver = {
234 .name = DRV_NAME,
235 .id_table = pdc_ata_pci_tbl,
236 .probe = pdc_ata_init_one,
237 .remove = ata_pci_remove_one,
238};
239
240
241static int pdc_port_start(struct ata_port *ap)
242{
243 struct device *dev = ap->host_set->dev;
244 struct pdc_port_priv *pp;
245 int rc;
246
247 rc = ata_port_start(ap);
248 if (rc)
249 return rc;
250
251 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
252 if (!pp) {
253 rc = -ENOMEM;
254 goto err_out;
255 }
256 memset(pp, 0, sizeof(*pp));
257
258 pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
259 if (!pp->pkt) {
260 rc = -ENOMEM;
261 goto err_out_kfree;
262 }
263
264 ap->private_data = pp;
265
266 return 0;
267
268err_out_kfree:
269 kfree(pp);
270err_out:
271 ata_port_stop(ap);
272 return rc;
273}
274
275
276static void pdc_port_stop(struct ata_port *ap)
277{
278 struct device *dev = ap->host_set->dev;
279 struct pdc_port_priv *pp = ap->private_data;
280
281 ap->private_data = NULL;
282 dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
283 kfree(pp);
284 ata_port_stop(ap);
285}
286
287
288static void pdc_reset_port(struct ata_port *ap)
289{
ea6ba10b 290 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT;
1da177e4
LT		 291 unsigned int i;
292 u32 tmp;
293
294 for (i = 11; i > 0; i--) {
295 tmp = readl(mmio);
296 if (tmp & PDC_RESET)
297 break;
298
299 udelay(100);
300
301 tmp |= PDC_RESET;
302 writel(tmp, mmio);
303 }
304
305 tmp &= ~PDC_RESET;
306 writel(tmp, mmio);
307 readl(mmio); /* flush */
308}
309
2cba582a 310static void pdc_sata_phy_reset(struct ata_port *ap)
1da177e4
LT		 311{
312 pdc_reset_port(ap);
313 sata_phy_reset(ap);
314}
315
2cba582a
JG		 316static void pdc_pata_phy_reset(struct ata_port *ap)
317{
318 /* FIXME: add cable detect. Don't assume 40-pin cable */
319 ap->cbl = ATA_CBL_PATA40;
320 ap->udma_mask &= ATA_UDMA_MASK_40C;
321
322 pdc_reset_port(ap);
323 ata_port_probe(ap);
324 ata_bus_reset(ap);
325}
326
1da177e4
LT		 327static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
328{
329 if (sc_reg > SCR_CONTROL)
330 return 0xffffffffU;
b181d3b0 331 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
1da177e4
LT		 332}
333
334
335static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
336 u32 val)
337{
338 if (sc_reg > SCR_CONTROL)
339 return;
b181d3b0 340 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
1da177e4
LT		 341}
342
343static void pdc_qc_prep(struct ata_queued_cmd *qc)
344{
345 struct pdc_port_priv *pp = qc->ap->private_data;
346 unsigned int i;
347
348 VPRINTK("ENTER\n");
349
350 switch (qc->tf.protocol) {
351 case ATA_PROT_DMA:
352 ata_qc_prep(qc);
353 /* fall through */
354
355 case ATA_PROT_NODATA:
356 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
357 qc->dev->devno, pp->pkt);
358
359 if (qc->tf.flags & ATA_TFLAG_LBA48)
360 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
361 else
362 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
363
364 pdc_pkt_footer(&qc->tf, pp->pkt, i);
365 break;
366
367 default:
368 break;
369 }
370}
371
372static void pdc_eng_timeout(struct ata_port *ap)
373{
b8f6153e 374 struct ata_host_set *host_set = ap->host_set;
1da177e4
LT		 375 u8 drv_stat;
376 struct ata_queued_cmd *qc;
b8f6153e 377 unsigned long flags;
1da177e4
LT		 378
379 DPRINTK("ENTER\n");
380
b8f6153e
JG		 381 spin_lock_irqsave(&host_set->lock, flags);
382
1da177e4
LT		 383 qc = ata_qc_from_tag(ap, ap->active_tag);
384 if (!qc) {
385 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
386 ap->id);
387 goto out;
388 }
389
390 /* hack alert! We cannot use the supplied completion
391 * function from inside the ->eh_strategy_handler() thread.
392 * libata is the only user of ->eh_strategy_handler() in
393 * any kernel, so the default scsi_done() assumes it is
394 * not being called from the SCSI EH.
395 */
396 qc->scsidone = scsi_finish_command;
397
398 switch (qc->tf.protocol) {
399 case ATA_PROT_DMA:
400 case ATA_PROT_NODATA:
401 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
a7dac447
JG		 402 drv_stat = ata_wait_idle(ap);
403 ata_qc_complete(qc, __ac_err_mask(drv_stat));
1da177e4
LT		 404 break;
405
406 default:
407 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
408
409 printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
410 ap->id, qc->tf.command, drv_stat);
411
a7dac447 412 ata_qc_complete(qc, ac_err_mask(drv_stat));
1da177e4
LT		 413 break;
414 }
415
416out:
b8f6153e 417 spin_unlock_irqrestore(&host_set->lock, flags);
1da177e4
LT		 418 DPRINTK("EXIT\n");
419}
420
421static inline unsigned int pdc_host_intr( struct ata_port *ap,
422 struct ata_queued_cmd *qc)
423{
a7dac447 424 unsigned int handled = 0, err_mask = 0;
1da177e4 425 u32 tmp;
ea6ba10b 426 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
1da177e4
LT		 427
428 tmp = readl(mmio);
429 if (tmp & PDC_ERR_MASK) {
a7dac447 430 err_mask = AC_ERR_DEV;
1da177e4
LT		 431 pdc_reset_port(ap);
432 }
433
434 switch (qc->tf.protocol) {
435 case ATA_PROT_DMA:
436 case ATA_PROT_NODATA:
a7dac447
JG		 437 err_mask |= ac_err_mask(ata_wait_idle(ap));
438 ata_qc_complete(qc, err_mask);
1da177e4
LT		 439 handled = 1;
440 break;
441
442 default:
ee500aab
AL		 443 ap->stats.idle_irq++;
444 break;
1da177e4
LT		 445 }
446
ee500aab 447 return handled;
1da177e4
LT		 448}
449
450static void pdc_irq_clear(struct ata_port *ap)
451{
452 struct ata_host_set *host_set = ap->host_set;
ea6ba10b 453 void __iomem *mmio = host_set->mmio_base;
1da177e4
LT		 454
455 readl(mmio + PDC_INT_SEQMASK);
456}
457
458static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
459{
460 struct ata_host_set *host_set = dev_instance;
461 struct ata_port *ap;
462 u32 mask = 0;
463 unsigned int i, tmp;
464 unsigned int handled = 0;
ea6ba10b 465 void __iomem *mmio_base;
1da177e4
LT		 466
467 VPRINTK("ENTER\n");
468
469 if (!host_set || !host_set->mmio_base) {
470 VPRINTK("QUICK EXIT\n");
471 return IRQ_NONE;
472 }
473
474 mmio_base = host_set->mmio_base;
475
476 /* reading should also clear interrupts */
477 mask = readl(mmio_base + PDC_INT_SEQMASK);
478
479 if (mask == 0xffffffff) {
480 VPRINTK("QUICK EXIT 2\n");
481 return IRQ_NONE;
482 }
483 mask &= 0xffff; /* only 16 tags possible */
484 if (!mask) {
485 VPRINTK("QUICK EXIT 3\n");
486 return IRQ_NONE;
487 }
488
489 spin_lock(&host_set->lock);
490
491 writel(mask, mmio_base + PDC_INT_SEQMASK);
492
493 for (i = 0; i < host_set->n_ports; i++) {
494 VPRINTK("port %u\n", i);
495 ap = host_set->ports[i];
496 tmp = mask & (1 << (i + 1));
c1389503
TH		 497 if (tmp && ap &&
498 !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
1da177e4
LT		 499 struct ata_queued_cmd *qc;
500
501 qc = ata_qc_from_tag(ap, ap->active_tag);
502 if (qc && (!(qc->tf.ctl & ATA_NIEN)))
503 handled += pdc_host_intr(ap, qc);
504 }
505 }
506
507 spin_unlock(&host_set->lock);
508
509 VPRINTK("EXIT\n");
510
511 return IRQ_RETVAL(handled);
512}
513
514static inline void pdc_packet_start(struct ata_queued_cmd *qc)
515{
516 struct ata_port *ap = qc->ap;
517 struct pdc_port_priv *pp = ap->private_data;
518 unsigned int port_no = ap->port_no;
519 u8 seq = (u8) (port_no + 1);
520
521 VPRINTK("ENTER, ap %p\n", ap);
522
523 writel(0x00000001, ap->host_set->mmio_base + (seq * 4));
524 readl(ap->host_set->mmio_base + (seq * 4)); /* flush */
525
526 pp->pkt[2] = seq;
527 wmb(); /* flush PRD, pkt writes */
b181d3b0
AV		 528 writel(pp->pkt_dma, (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
529 readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
1da177e4
LT		 530}
531
532static int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
533{
534 switch (qc->tf.protocol) {
535 case ATA_PROT_DMA:
536 case ATA_PROT_NODATA:
537 pdc_packet_start(qc);
538 return 0;
539
540 case ATA_PROT_ATAPI_DMA:
541 BUG();
542 break;
543
544 default:
545 break;
546 }
547
548 return ata_qc_issue_prot(qc);
549}
550
057ace5e 551static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 552{
553 WARN_ON (tf->protocol == ATA_PROT_DMA ||
554 tf->protocol == ATA_PROT_NODATA);
555 ata_tf_load(ap, tf);
556}
557
558
057ace5e 559static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 560{
561 WARN_ON (tf->protocol == ATA_PROT_DMA ||
562 tf->protocol == ATA_PROT_NODATA);
563 ata_exec_command(ap, tf);
564}
565
566
567static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base)
568{
569 port->cmd_addr = base;
570 port->data_addr = base;
571 port->feature_addr =
572 port->error_addr = base + 0x4;
573 port->nsect_addr = base + 0x8;
574 port->lbal_addr = base + 0xc;
575 port->lbam_addr = base + 0x10;
576 port->lbah_addr = base + 0x14;
577 port->device_addr = base + 0x18;
578 port->command_addr =
579 port->status_addr = base + 0x1c;
580 port->altstatus_addr =
581 port->ctl_addr = base + 0x38;
582}
583
584
585static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
586{
ea6ba10b 587 void __iomem *mmio = pe->mmio_base;
1da177e4
LT		 588 u32 tmp;
589
590 /*
591 * Except for the hotplug stuff, this is voodoo from the
592 * Promise driver. Label this entire section
593 * "TODO: figure out why we do this"
594 */
595
596 /* change FIFO_SHD to 8 dwords, enable BMR_BURST */
597 tmp = readl(mmio + PDC_FLASH_CTL);
598 tmp |= 0x12000; /* bit 16 (fifo 8 dw) and 13 (bmr burst?) */
599 writel(tmp, mmio + PDC_FLASH_CTL);
600
601 /* clear plug/unplug flags for all ports */
602 tmp = readl(mmio + PDC_SATA_PLUG_CSR);
603 writel(tmp | 0xff, mmio + PDC_SATA_PLUG_CSR);
604
605 /* mask plug/unplug ints */
606 tmp = readl(mmio + PDC_SATA_PLUG_CSR);
607 writel(tmp | 0xff0000, mmio + PDC_SATA_PLUG_CSR);
608
609 /* reduce TBG clock to 133 Mhz. */
610 tmp = readl(mmio + PDC_TBG_MODE);
611 tmp &= ~0x30000; /* clear bit 17, 16*/
612 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
613 writel(tmp, mmio + PDC_TBG_MODE);
614
615 readl(mmio + PDC_TBG_MODE); /* flush */
616 msleep(10);
617
618 /* adjust slew rate control register. */
619 tmp = readl(mmio + PDC_SLEW_CTL);
620 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
621 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
622 writel(tmp, mmio + PDC_SLEW_CTL);
623}
624
625static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
626{
627 static int printed_version;
628 struct ata_probe_ent *probe_ent = NULL;
629 unsigned long base;
ea6ba10b 630 void __iomem *mmio_base;
1da177e4
LT		 631 unsigned int board_idx = (unsigned int) ent->driver_data;
632 int pci_dev_busy = 0;
633 int rc;
634
635 if (!printed_version++)
636 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
637
638 /*
639 * If this driver happens to only be useful on Apple's K2, then
640 * we should check that here as it has a normal Serverworks ID
641 */
642 rc = pci_enable_device(pdev);
643 if (rc)
644 return rc;
645
646 rc = pci_request_regions(pdev, DRV_NAME);
647 if (rc) {
648 pci_dev_busy = 1;
649 goto err_out;
650 }
651
652 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
653 if (rc)
654 goto err_out_regions;
655 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
656 if (rc)
657 goto err_out_regions;
658
659 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
660 if (probe_ent == NULL) {
661 rc = -ENOMEM;
662 goto err_out_regions;
663 }
664
665 memset(probe_ent, 0, sizeof(*probe_ent));
666 probe_ent->dev = pci_dev_to_dev(pdev);
667 INIT_LIST_HEAD(&probe_ent->node);
668
374b1873 669 mmio_base = pci_iomap(pdev, 3, 0);
1da177e4
LT		 670 if (mmio_base == NULL) {
671 rc = -ENOMEM;
672 goto err_out_free_ent;
673 }
674 base = (unsigned long) mmio_base;
675
676 probe_ent->sht = pdc_port_info[board_idx].sht;
677 probe_ent->host_flags = pdc_port_info[board_idx].host_flags;
678 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
679 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
680 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
681 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
682
683 probe_ent->irq = pdev->irq;
684 probe_ent->irq_flags = SA_SHIRQ;
685 probe_ent->mmio_base = mmio_base;
686
687 pdc_ata_setup_port(&probe_ent->port[0], base + 0x200);
688 pdc_ata_setup_port(&probe_ent->port[1], base + 0x280);
689
690 probe_ent->port[0].scr_addr = base + 0x400;
691 probe_ent->port[1].scr_addr = base + 0x500;
692
693 /* notice 4-port boards */
694 switch (board_idx) {
695 case board_20319:
696 probe_ent->n_ports = 4;
697
698 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
699 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
700
701 probe_ent->port[2].scr_addr = base + 0x600;
702 probe_ent->port[3].scr_addr = base + 0x700;
703 break;
704 case board_2037x:
705 probe_ent->n_ports = 2;
706 break;
f497ba73
TL		 707 case board_20619:
708 probe_ent->n_ports = 4;
709
710 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
711 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
712
713 probe_ent->port[2].scr_addr = base + 0x600;
714 probe_ent->port[3].scr_addr = base + 0x700;
715 break;
1da177e4
LT		 716 default:
717 BUG();
718 break;
719 }
720
721 pci_set_master(pdev);
722
723 /* initialize adapter */
724 pdc_host_init(board_idx, probe_ent);
725
726 /* FIXME: check ata_device_add return value */
727 ata_device_add(probe_ent);
728 kfree(probe_ent);
729
730 return 0;
731
732err_out_free_ent:
733 kfree(probe_ent);
734err_out_regions:
735 pci_release_regions(pdev);
736err_out:
737 if (!pci_dev_busy)
738 pci_disable_device(pdev);
739 return rc;
740}
741
742
743static int __init pdc_ata_init(void)
744{
745 return pci_module_init(&pdc_ata_pci_driver);
746}
747
748
749static void __exit pdc_ata_exit(void)
750{
751 pci_unregister_driver(&pdc_ata_pci_driver);
752}
753
754
755MODULE_AUTHOR("Jeff Garzik");
f497ba73 756MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1da177e4
LT		 757MODULE_LICENSE("GPL");
758MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
759MODULE_VERSION(DRV_VERSION);
760
761module_init(pdc_ata_init);
762module_exit(pdc_ata_exit);
Linux kernel - Deliverables
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