Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * sata_sil.c - Silicon Image SATA | |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
af36d7f0 | 8 | * Copyright 2003-2005 Red Hat, Inc. |
1da177e4 LT |
9 | * Copyright 2003 Benjamin Herrenschmidt |
10 | * | |
af36d7f0 JG |
11 | * |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2, or (at your option) | |
15 | * any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; see the file COPYING. If not, write to | |
24 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
26 | * | |
27 | * libata documentation is available via 'make {ps|pdf}docs', | |
28 | * as Documentation/DocBook/libata.* | |
1da177e4 | 29 | * |
953d1137 JG |
30 | * Documentation for SiI 3112: |
31 | * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2 | |
32 | * | |
33 | * Other errata and documentation available under NDA. | |
34 | * | |
1da177e4 LT |
35 | */ |
36 | ||
37 | #include <linux/kernel.h> | |
38 | #include <linux/module.h> | |
39 | #include <linux/pci.h> | |
40 | #include <linux/init.h> | |
41 | #include <linux/blkdev.h> | |
42 | #include <linux/delay.h> | |
43 | #include <linux/interrupt.h> | |
a9524a76 | 44 | #include <linux/device.h> |
1da177e4 LT |
45 | #include <scsi/scsi_host.h> |
46 | #include <linux/libata.h> | |
47 | ||
48 | #define DRV_NAME "sata_sil" | |
49 | #define DRV_VERSION "0.9" | |
50 | ||
51 | enum { | |
e653a1e6 TH |
52 | /* |
53 | * host flags | |
54 | */ | |
e4e10e3e | 55 | SIL_FLAG_RERR_ON_DMA_ACT = (1 << 29), |
e4deec63 | 56 | SIL_FLAG_MOD15WRITE = (1 << 30), |
e653a1e6 TH |
57 | SIL_DFL_HOST_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
58 | ATA_FLAG_MMIO, | |
e4deec63 | 59 | |
e653a1e6 TH |
60 | /* |
61 | * Controller IDs | |
62 | */ | |
1da177e4 | 63 | sil_3112 = 0, |
81c2af35 TH |
64 | sil_3512 = 1, |
65 | sil_3114 = 2, | |
1da177e4 | 66 | |
e653a1e6 TH |
67 | /* |
68 | * Register offsets | |
69 | */ | |
1da177e4 | 70 | SIL_SYSCFG = 0x48, |
e653a1e6 TH |
71 | |
72 | /* | |
73 | * Register bits | |
74 | */ | |
75 | /* SYSCFG */ | |
1da177e4 LT |
76 | SIL_MASK_IDE0_INT = (1 << 22), |
77 | SIL_MASK_IDE1_INT = (1 << 23), | |
78 | SIL_MASK_IDE2_INT = (1 << 24), | |
79 | SIL_MASK_IDE3_INT = (1 << 25), | |
80 | SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT, | |
81 | SIL_MASK_4PORT = SIL_MASK_2PORT | | |
82 | SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT, | |
83 | ||
e653a1e6 | 84 | /* BMDMA/BMDMA2 */ |
1da177e4 | 85 | SIL_INTR_STEERING = (1 << 1), |
e653a1e6 TH |
86 | |
87 | /* | |
88 | * Others | |
89 | */ | |
1da177e4 LT |
90 | SIL_QUIRK_MOD15WRITE = (1 << 0), |
91 | SIL_QUIRK_UDMA5MAX = (1 << 1), | |
92 | }; | |
93 | ||
94 | static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
95 | static void sil_dev_config(struct ata_port *ap, struct ata_device *dev); | |
96 | static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg); | |
97 | static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | |
98 | static void sil_post_set_mode (struct ata_port *ap); | |
99 | ||
374b1873 | 100 | |
3b7d697d | 101 | static const struct pci_device_id sil_pci_tbl[] = { |
81c2af35 TH |
102 | { 0x1095, 0x3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 }, |
103 | { 0x1095, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 }, | |
0ee304d5 | 104 | { 0x1095, 0x3512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3512 }, |
1da177e4 | 105 | { 0x1095, 0x3114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3114 }, |
81c2af35 TH |
106 | { 0x1002, 0x436e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 }, |
107 | { 0x1002, 0x4379, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 }, | |
108 | { 0x1002, 0x437a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 }, | |
1da177e4 LT |
109 | { } /* terminate list */ |
110 | }; | |
111 | ||
112 | ||
113 | /* TODO firmware versions should be added - eric */ | |
114 | static const struct sil_drivelist { | |
115 | const char * product; | |
116 | unsigned int quirk; | |
117 | } sil_blacklist [] = { | |
118 | { "ST320012AS", SIL_QUIRK_MOD15WRITE }, | |
119 | { "ST330013AS", SIL_QUIRK_MOD15WRITE }, | |
120 | { "ST340017AS", SIL_QUIRK_MOD15WRITE }, | |
121 | { "ST360015AS", SIL_QUIRK_MOD15WRITE }, | |
122 | { "ST380013AS", SIL_QUIRK_MOD15WRITE }, | |
123 | { "ST380023AS", SIL_QUIRK_MOD15WRITE }, | |
124 | { "ST3120023AS", SIL_QUIRK_MOD15WRITE }, | |
125 | { "ST3160023AS", SIL_QUIRK_MOD15WRITE }, | |
126 | { "ST3120026AS", SIL_QUIRK_MOD15WRITE }, | |
127 | { "ST3200822AS", SIL_QUIRK_MOD15WRITE }, | |
128 | { "ST340014ASL", SIL_QUIRK_MOD15WRITE }, | |
129 | { "ST360014ASL", SIL_QUIRK_MOD15WRITE }, | |
130 | { "ST380011ASL", SIL_QUIRK_MOD15WRITE }, | |
131 | { "ST3120022ASL", SIL_QUIRK_MOD15WRITE }, | |
132 | { "ST3160021ASL", SIL_QUIRK_MOD15WRITE }, | |
133 | { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX }, | |
134 | { } | |
135 | }; | |
136 | ||
137 | static struct pci_driver sil_pci_driver = { | |
138 | .name = DRV_NAME, | |
139 | .id_table = sil_pci_tbl, | |
140 | .probe = sil_init_one, | |
141 | .remove = ata_pci_remove_one, | |
142 | }; | |
143 | ||
193515d5 | 144 | static struct scsi_host_template sil_sht = { |
1da177e4 LT |
145 | .module = THIS_MODULE, |
146 | .name = DRV_NAME, | |
147 | .ioctl = ata_scsi_ioctl, | |
148 | .queuecommand = ata_scsi_queuecmd, | |
149 | .eh_strategy_handler = ata_scsi_error, | |
150 | .can_queue = ATA_DEF_QUEUE, | |
151 | .this_id = ATA_SHT_THIS_ID, | |
152 | .sg_tablesize = LIBATA_MAX_PRD, | |
1da177e4 LT |
153 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
154 | .emulated = ATA_SHT_EMULATED, | |
155 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
156 | .proc_name = DRV_NAME, | |
157 | .dma_boundary = ATA_DMA_BOUNDARY, | |
158 | .slave_configure = ata_scsi_slave_config, | |
159 | .bios_param = ata_std_bios_param, | |
1da177e4 LT |
160 | }; |
161 | ||
057ace5e | 162 | static const struct ata_port_operations sil_ops = { |
1da177e4 LT |
163 | .port_disable = ata_port_disable, |
164 | .dev_config = sil_dev_config, | |
165 | .tf_load = ata_tf_load, | |
166 | .tf_read = ata_tf_read, | |
167 | .check_status = ata_check_status, | |
168 | .exec_command = ata_exec_command, | |
169 | .dev_select = ata_std_dev_select, | |
531db7aa | 170 | .probe_reset = ata_std_probe_reset, |
1da177e4 LT |
171 | .post_set_mode = sil_post_set_mode, |
172 | .bmdma_setup = ata_bmdma_setup, | |
173 | .bmdma_start = ata_bmdma_start, | |
174 | .bmdma_stop = ata_bmdma_stop, | |
175 | .bmdma_status = ata_bmdma_status, | |
176 | .qc_prep = ata_qc_prep, | |
177 | .qc_issue = ata_qc_issue_prot, | |
178 | .eng_timeout = ata_eng_timeout, | |
179 | .irq_handler = ata_interrupt, | |
180 | .irq_clear = ata_bmdma_irq_clear, | |
181 | .scr_read = sil_scr_read, | |
182 | .scr_write = sil_scr_write, | |
183 | .port_start = ata_port_start, | |
184 | .port_stop = ata_port_stop, | |
374b1873 | 185 | .host_stop = ata_pci_host_stop, |
1da177e4 LT |
186 | }; |
187 | ||
98ac62de | 188 | static const struct ata_port_info sil_port_info[] = { |
1da177e4 | 189 | /* sil_3112 */ |
e4deec63 TH |
190 | { |
191 | .sht = &sil_sht, | |
e653a1e6 | 192 | .host_flags = SIL_DFL_HOST_FLAGS | SIL_FLAG_MOD15WRITE, |
e4deec63 TH |
193 | .pio_mask = 0x1f, /* pio0-4 */ |
194 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
195 | .udma_mask = 0x3f, /* udma0-5 */ | |
196 | .port_ops = &sil_ops, | |
0ee304d5 TH |
197 | }, |
198 | /* sil_3512 */ | |
1da177e4 LT |
199 | { |
200 | .sht = &sil_sht, | |
e653a1e6 | 201 | .host_flags = SIL_DFL_HOST_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT, |
0ee304d5 TH |
202 | .pio_mask = 0x1f, /* pio0-4 */ |
203 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
204 | .udma_mask = 0x3f, /* udma0-5 */ | |
205 | .port_ops = &sil_ops, | |
206 | }, | |
207 | /* sil_3114 */ | |
1da177e4 LT |
208 | { |
209 | .sht = &sil_sht, | |
e653a1e6 | 210 | .host_flags = SIL_DFL_HOST_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT, |
1da177e4 LT |
211 | .pio_mask = 0x1f, /* pio0-4 */ |
212 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
213 | .udma_mask = 0x3f, /* udma0-5 */ | |
214 | .port_ops = &sil_ops, | |
215 | }, | |
216 | }; | |
217 | ||
218 | /* per-port register offsets */ | |
219 | /* TODO: we can probably calculate rather than use a table */ | |
220 | static const struct { | |
221 | unsigned long tf; /* ATA taskfile register block */ | |
222 | unsigned long ctl; /* ATA control/altstatus register block */ | |
223 | unsigned long bmdma; /* DMA register block */ | |
48d4ef2a | 224 | unsigned long fifo_cfg; /* FIFO Valid Byte Count and Control */ |
1da177e4 LT |
225 | unsigned long scr; /* SATA control register block */ |
226 | unsigned long sien; /* SATA Interrupt Enable register */ | |
227 | unsigned long xfer_mode;/* data transfer mode register */ | |
e4e10e3e | 228 | unsigned long sfis_cfg; /* SATA FIS reception config register */ |
1da177e4 LT |
229 | } sil_port[] = { |
230 | /* port 0 ... */ | |
48d4ef2a TH |
231 | { 0x80, 0x8A, 0x00, 0x40, 0x100, 0x148, 0xb4, 0x14c }, |
232 | { 0xC0, 0xCA, 0x08, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc }, | |
233 | { 0x280, 0x28A, 0x200, 0x240, 0x300, 0x348, 0x2b4, 0x34c }, | |
234 | { 0x2C0, 0x2CA, 0x208, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc }, | |
1da177e4 LT |
235 | /* ... port 3 */ |
236 | }; | |
237 | ||
238 | MODULE_AUTHOR("Jeff Garzik"); | |
239 | MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller"); | |
240 | MODULE_LICENSE("GPL"); | |
241 | MODULE_DEVICE_TABLE(pci, sil_pci_tbl); | |
242 | MODULE_VERSION(DRV_VERSION); | |
243 | ||
51e9f2ff JG |
244 | static int slow_down = 0; |
245 | module_param(slow_down, int, 0444); | |
246 | MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)"); | |
247 | ||
374b1873 | 248 | |
1da177e4 LT |
249 | static unsigned char sil_get_device_cache_line(struct pci_dev *pdev) |
250 | { | |
251 | u8 cache_line = 0; | |
252 | pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line); | |
253 | return cache_line; | |
254 | } | |
255 | ||
256 | static void sil_post_set_mode (struct ata_port *ap) | |
257 | { | |
258 | struct ata_host_set *host_set = ap->host_set; | |
259 | struct ata_device *dev; | |
ea6ba10b JG |
260 | void __iomem *addr = |
261 | host_set->mmio_base + sil_port[ap->port_no].xfer_mode; | |
1da177e4 LT |
262 | u32 tmp, dev_mode[2]; |
263 | unsigned int i; | |
264 | ||
265 | for (i = 0; i < 2; i++) { | |
266 | dev = &ap->device[i]; | |
267 | if (!ata_dev_present(dev)) | |
268 | dev_mode[i] = 0; /* PIO0/1/2 */ | |
269 | else if (dev->flags & ATA_DFLAG_PIO) | |
270 | dev_mode[i] = 1; /* PIO3/4 */ | |
271 | else | |
272 | dev_mode[i] = 3; /* UDMA */ | |
273 | /* value 2 indicates MDMA */ | |
274 | } | |
275 | ||
276 | tmp = readl(addr); | |
277 | tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0)); | |
278 | tmp |= dev_mode[0]; | |
279 | tmp |= (dev_mode[1] << 4); | |
280 | writel(tmp, addr); | |
281 | readl(addr); /* flush */ | |
282 | } | |
283 | ||
284 | static inline unsigned long sil_scr_addr(struct ata_port *ap, unsigned int sc_reg) | |
285 | { | |
286 | unsigned long offset = ap->ioaddr.scr_addr; | |
287 | ||
288 | switch (sc_reg) { | |
289 | case SCR_STATUS: | |
290 | return offset + 4; | |
291 | case SCR_ERROR: | |
292 | return offset + 8; | |
293 | case SCR_CONTROL: | |
294 | return offset; | |
295 | default: | |
296 | /* do nothing */ | |
297 | break; | |
298 | } | |
299 | ||
300 | return 0; | |
301 | } | |
302 | ||
303 | static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg) | |
304 | { | |
9aa36e89 | 305 | void __iomem *mmio = (void __iomem *) sil_scr_addr(ap, sc_reg); |
1da177e4 LT |
306 | if (mmio) |
307 | return readl(mmio); | |
308 | return 0xffffffffU; | |
309 | } | |
310 | ||
311 | static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) | |
312 | { | |
9aa36e89 | 313 | void *mmio = (void __iomem *) sil_scr_addr(ap, sc_reg); |
1da177e4 LT |
314 | if (mmio) |
315 | writel(val, mmio); | |
316 | } | |
317 | ||
318 | /** | |
319 | * sil_dev_config - Apply device/host-specific errata fixups | |
320 | * @ap: Port containing device to be examined | |
321 | * @dev: Device to be examined | |
322 | * | |
323 | * After the IDENTIFY [PACKET] DEVICE step is complete, and a | |
324 | * device is known to be present, this function is called. | |
325 | * We apply two errata fixups which are specific to Silicon Image, | |
326 | * a Seagate and a Maxtor fixup. | |
327 | * | |
328 | * For certain Seagate devices, we must limit the maximum sectors | |
329 | * to under 8K. | |
330 | * | |
331 | * For certain Maxtor devices, we must not program the drive | |
332 | * beyond udma5. | |
333 | * | |
334 | * Both fixups are unfairly pessimistic. As soon as I get more | |
335 | * information on these errata, I will create a more exhaustive | |
336 | * list, and apply the fixups to only the specific | |
337 | * devices/hosts/firmwares that need it. | |
338 | * | |
339 | * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted | |
340 | * The Maxtor quirk is in the blacklist, but I'm keeping the original | |
341 | * pessimistic fix for the following reasons... | |
342 | * - There seems to be less info on it, only one device gleaned off the | |
343 | * Windows driver, maybe only one is affected. More info would be greatly | |
344 | * appreciated. | |
345 | * - But then again UDMA5 is hardly anything to complain about | |
346 | */ | |
347 | static void sil_dev_config(struct ata_port *ap, struct ata_device *dev) | |
348 | { | |
349 | unsigned int n, quirks = 0; | |
2e02671d | 350 | unsigned char model_num[41]; |
1da177e4 | 351 | |
6a62a04d | 352 | ata_id_c_string(dev->id, model_num, ATA_ID_PROD_OFS, sizeof(model_num)); |
1da177e4 | 353 | |
8a60a071 | 354 | for (n = 0; sil_blacklist[n].product; n++) |
2e02671d | 355 | if (!strcmp(sil_blacklist[n].product, model_num)) { |
1da177e4 LT |
356 | quirks = sil_blacklist[n].quirk; |
357 | break; | |
358 | } | |
8a60a071 | 359 | |
1da177e4 | 360 | /* limit requests to 15 sectors */ |
51e9f2ff JG |
361 | if (slow_down || |
362 | ((ap->flags & SIL_FLAG_MOD15WRITE) && | |
363 | (quirks & SIL_QUIRK_MOD15WRITE))) { | |
364 | printk(KERN_INFO "ata%u(%u): applying Seagate errata fix (mod15write workaround)\n", | |
1da177e4 | 365 | ap->id, dev->devno); |
b00eec1d | 366 | dev->max_sectors = 15; |
1da177e4 LT |
367 | return; |
368 | } | |
369 | ||
370 | /* limit to udma5 */ | |
371 | if (quirks & SIL_QUIRK_UDMA5MAX) { | |
372 | printk(KERN_INFO "ata%u(%u): applying Maxtor errata fix %s\n", | |
2e02671d | 373 | ap->id, dev->devno, model_num); |
5a529139 | 374 | dev->udma_mask &= ATA_UDMA5; |
1da177e4 LT |
375 | return; |
376 | } | |
377 | } | |
378 | ||
379 | static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
380 | { | |
381 | static int printed_version; | |
382 | struct ata_probe_ent *probe_ent = NULL; | |
383 | unsigned long base; | |
ea6ba10b | 384 | void __iomem *mmio_base; |
1da177e4 LT |
385 | int rc; |
386 | unsigned int i; | |
387 | int pci_dev_busy = 0; | |
388 | u32 tmp, irq_mask; | |
389 | u8 cls; | |
390 | ||
391 | if (!printed_version++) | |
a9524a76 | 392 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 LT |
393 | |
394 | /* | |
395 | * If this driver happens to only be useful on Apple's K2, then | |
396 | * we should check that here as it has a normal Serverworks ID | |
397 | */ | |
398 | rc = pci_enable_device(pdev); | |
399 | if (rc) | |
400 | return rc; | |
401 | ||
402 | rc = pci_request_regions(pdev, DRV_NAME); | |
403 | if (rc) { | |
404 | pci_dev_busy = 1; | |
405 | goto err_out; | |
406 | } | |
407 | ||
408 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
409 | if (rc) | |
410 | goto err_out_regions; | |
411 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
412 | if (rc) | |
413 | goto err_out_regions; | |
414 | ||
9a531443 | 415 | probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL); |
1da177e4 LT |
416 | if (probe_ent == NULL) { |
417 | rc = -ENOMEM; | |
418 | goto err_out_regions; | |
419 | } | |
420 | ||
1da177e4 LT |
421 | INIT_LIST_HEAD(&probe_ent->node); |
422 | probe_ent->dev = pci_dev_to_dev(pdev); | |
423 | probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops; | |
424 | probe_ent->sht = sil_port_info[ent->driver_data].sht; | |
425 | probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2; | |
426 | probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask; | |
427 | probe_ent->mwdma_mask = sil_port_info[ent->driver_data].mwdma_mask; | |
428 | probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask; | |
429 | probe_ent->irq = pdev->irq; | |
430 | probe_ent->irq_flags = SA_SHIRQ; | |
431 | probe_ent->host_flags = sil_port_info[ent->driver_data].host_flags; | |
432 | ||
374b1873 | 433 | mmio_base = pci_iomap(pdev, 5, 0); |
1da177e4 LT |
434 | if (mmio_base == NULL) { |
435 | rc = -ENOMEM; | |
436 | goto err_out_free_ent; | |
437 | } | |
438 | ||
439 | probe_ent->mmio_base = mmio_base; | |
440 | ||
441 | base = (unsigned long) mmio_base; | |
442 | ||
443 | for (i = 0; i < probe_ent->n_ports; i++) { | |
444 | probe_ent->port[i].cmd_addr = base + sil_port[i].tf; | |
445 | probe_ent->port[i].altstatus_addr = | |
446 | probe_ent->port[i].ctl_addr = base + sil_port[i].ctl; | |
447 | probe_ent->port[i].bmdma_addr = base + sil_port[i].bmdma; | |
448 | probe_ent->port[i].scr_addr = base + sil_port[i].scr; | |
449 | ata_std_ports(&probe_ent->port[i]); | |
450 | } | |
451 | ||
452 | /* Initialize FIFO PCI bus arbitration */ | |
453 | cls = sil_get_device_cache_line(pdev); | |
454 | if (cls) { | |
455 | cls >>= 3; | |
456 | cls++; /* cls = (line_size/8)+1 */ | |
48d4ef2a TH |
457 | for (i = 0; i < probe_ent->n_ports; i++) |
458 | writew(cls << 8 | cls, | |
459 | mmio_base + sil_port[i].fifo_cfg); | |
1da177e4 | 460 | } else |
a9524a76 | 461 | dev_printk(KERN_WARNING, &pdev->dev, |
48d4ef2a | 462 | "cache line size not set. Driver may not function\n"); |
1da177e4 | 463 | |
e4e10e3e TH |
464 | /* Apply R_ERR on DMA activate FIS errata workaround */ |
465 | if (probe_ent->host_flags & SIL_FLAG_RERR_ON_DMA_ACT) { | |
466 | int cnt; | |
467 | ||
468 | for (i = 0, cnt = 0; i < probe_ent->n_ports; i++) { | |
469 | tmp = readl(mmio_base + sil_port[i].sfis_cfg); | |
470 | if ((tmp & 0x3) != 0x01) | |
471 | continue; | |
472 | if (!cnt) | |
473 | dev_printk(KERN_INFO, &pdev->dev, | |
474 | "Applying R_ERR on DMA activate " | |
475 | "FIS errata fix\n"); | |
476 | writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg); | |
477 | cnt++; | |
478 | } | |
479 | } | |
480 | ||
1da177e4 LT |
481 | if (ent->driver_data == sil_3114) { |
482 | irq_mask = SIL_MASK_4PORT; | |
483 | ||
484 | /* flip the magic "make 4 ports work" bit */ | |
48d4ef2a | 485 | tmp = readl(mmio_base + sil_port[2].bmdma); |
1da177e4 LT |
486 | if ((tmp & SIL_INTR_STEERING) == 0) |
487 | writel(tmp | SIL_INTR_STEERING, | |
48d4ef2a | 488 | mmio_base + sil_port[2].bmdma); |
1da177e4 LT |
489 | |
490 | } else { | |
491 | irq_mask = SIL_MASK_2PORT; | |
492 | } | |
493 | ||
494 | /* make sure IDE0/1/2/3 interrupts are not masked */ | |
495 | tmp = readl(mmio_base + SIL_SYSCFG); | |
496 | if (tmp & irq_mask) { | |
497 | tmp &= ~irq_mask; | |
498 | writel(tmp, mmio_base + SIL_SYSCFG); | |
499 | readl(mmio_base + SIL_SYSCFG); /* flush */ | |
500 | } | |
501 | ||
502 | /* mask all SATA phy-related interrupts */ | |
503 | /* TODO: unmask bit 6 (SError N bit) for hotplug */ | |
504 | for (i = 0; i < probe_ent->n_ports; i++) | |
505 | writel(0, mmio_base + sil_port[i].sien); | |
506 | ||
507 | pci_set_master(pdev); | |
508 | ||
509 | /* FIXME: check ata_device_add return value */ | |
510 | ata_device_add(probe_ent); | |
511 | kfree(probe_ent); | |
512 | ||
513 | return 0; | |
514 | ||
515 | err_out_free_ent: | |
516 | kfree(probe_ent); | |
517 | err_out_regions: | |
518 | pci_release_regions(pdev); | |
519 | err_out: | |
520 | if (!pci_dev_busy) | |
521 | pci_disable_device(pdev); | |
522 | return rc; | |
523 | } | |
524 | ||
525 | static int __init sil_init(void) | |
526 | { | |
527 | return pci_module_init(&sil_pci_driver); | |
528 | } | |
529 | ||
530 | static void __exit sil_exit(void) | |
531 | { | |
532 | pci_unregister_driver(&sil_pci_driver); | |
533 | } | |
534 | ||
535 | ||
536 | module_init(sil_init); | |
537 | module_exit(sil_exit); |