projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[PATCH] sata_sil24: rename PORT_PRB to PORT_LRAM and add PORT_LRAM_SLOT_SZ
[deliverable/linux.git] / drivers / scsi / sata_sil24.c
CommitLineData
edb33667
TH		 1/*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
edb33667
TH		 8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
11 * later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 */
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/pci.h>
23#include <linux/blkdev.h>
24#include <linux/delay.h>
25#include <linux/interrupt.h>
26#include <linux/dma-mapping.h>
a9524a76 27#include <linux/device.h>
edb33667 28#include <scsi/scsi_host.h>
193515d5 29#include <scsi/scsi_cmnd.h>
edb33667
TH		 30#include <linux/libata.h>
31#include <asm/io.h>
32
33#define DRV_NAME "sata_sil24"
af64371a 34#define DRV_VERSION "0.24"
edb33667 35
edb33667
TH		 36/*
37 * Port request block (PRB) 32 bytes
38 */
39struct sil24_prb {
40 u16 ctrl;
41 u16 prot;
42 u32 rx_cnt;
43 u8 fis[6 * 4];
44};
45
46/*
47 * Scatter gather entry (SGE) 16 bytes
48 */
49struct sil24_sge {
50 u64 addr;
51 u32 cnt;
52 u32 flags;
53};
54
55/*
56 * Port multiplier
57 */
58struct sil24_port_multiplier {
59 u32 diag;
60 u32 sactive;
61};
62
63enum {
64 /*
65 * Global controller registers (128 bytes @ BAR0)
66 */
67 /* 32 bit regs */
68 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
69 HOST_CTRL = 0x40,
70 HOST_IRQ_STAT = 0x44,
71 HOST_PHY_CFG = 0x48,
72 HOST_BIST_CTRL = 0x50,
73 HOST_BIST_PTRN = 0x54,
74 HOST_BIST_STAT = 0x58,
75 HOST_MEM_BIST_STAT = 0x5c,
76 HOST_FLASH_CMD = 0x70,
77 /* 8 bit regs */
78 HOST_FLASH_DATA = 0x74,
79 HOST_TRANSITION_DETECT = 0x75,
80 HOST_GPIO_CTRL = 0x76,
81 HOST_I2C_ADDR = 0x78, /* 32 bit */
82 HOST_I2C_DATA = 0x7c,
83 HOST_I2C_XFER_CNT = 0x7e,
84 HOST_I2C_CTRL = 0x7f,
85
86 /* HOST_SLOT_STAT bits */
87 HOST_SSTAT_ATTN = (1 << 31),
88
7dafc3fd
TH		 89 /* HOST_CTRL bits */
90 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
91 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
92 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
93 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
94 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
95
edb33667
TH		 96 /*
97 * Port registers
98 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
99 */
100 PORT_REGS_SIZE = 0x2000,
135da345
TH		 101
102 PORT_LRAM = 0x0000, /* 31 LRAM slots and PM regs */
103 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
edb33667
TH		 104
105 PORT_PM = 0x0f80, /* 8 bytes PM * 16 (128 bytes) */
106 /* 32 bit regs */
83bbecc9
TH		 107 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
108 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
109 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
110 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
111 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
edb33667 112 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
83bbecc9
TH		 113 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
114 PORT_CMD_ERR = 0x1024, /* command error number */
edb33667
TH		 115 PORT_FIS_CFG = 0x1028,
116 PORT_FIFO_THRES = 0x102c,
117 /* 16 bit regs */
118 PORT_DECODE_ERR_CNT = 0x1040,
119 PORT_DECODE_ERR_THRESH = 0x1042,
120 PORT_CRC_ERR_CNT = 0x1044,
121 PORT_CRC_ERR_THRESH = 0x1046,
122 PORT_HSHK_ERR_CNT = 0x1048,
123 PORT_HSHK_ERR_THRESH = 0x104a,
124 /* 32 bit regs */
125 PORT_PHY_CFG = 0x1050,
126 PORT_SLOT_STAT = 0x1800,
127 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
128 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
129 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
130 PORT_SCONTROL = 0x1f00,
131 PORT_SSTATUS = 0x1f04,
132 PORT_SERROR = 0x1f08,
133 PORT_SACTIVE = 0x1f0c,
134
135 /* PORT_CTRL_STAT bits */
136 PORT_CS_PORT_RST = (1 << 0), /* port reset */
137 PORT_CS_DEV_RST = (1 << 1), /* device reset */
138 PORT_CS_INIT = (1 << 2), /* port initialize */
139 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
d10cb35a 140 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
e382eb1d
TH		 141 PORT_CS_RESUME = (1 << 6), /* port resume */
142 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
143 PORT_CS_PM_EN = (1 << 13), /* port multiplier enable */
144 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
edb33667
TH		 145
146 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
147 /* bits[11:0] are masked */
148 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
149 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
150 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
151 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
152 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
153 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
7dafc3fd
TH		 154 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
155 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
156 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
157 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
158 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
3b9f1d0f 159 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
edb33667 160
88ce7550
TH		 161 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
162 PORT_IRQ_DEV_XCHG | PORT_IRQ_UNK_FIS,
163
edb33667
TH		 164 /* bits[27:16] are unmasked (raw) */
165 PORT_IRQ_RAW_SHIFT = 16,
166 PORT_IRQ_MASKED_MASK = 0x7ff,
167 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
168
169 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
170 PORT_IRQ_STEER_SHIFT = 30,
171 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
172
173 /* PORT_CMD_ERR constants */
174 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
175 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
176 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
177 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
178 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
179 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
180 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
181 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
182 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
183 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
184 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
185 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
186 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
187 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
188 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
189 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
190 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
191 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
192 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
64008802 193 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
edb33667 194 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
83bbecc9 195 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
edb33667 196
d10cb35a
TH		 197 /* bits of PRB control field */
198 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
199 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
200 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
201 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
202 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
203
204 /* PRB protocol field */
205 PRB_PROT_PACKET = (1 << 0),
206 PRB_PROT_TCQ = (1 << 1),
207 PRB_PROT_NCQ = (1 << 2),
208 PRB_PROT_READ = (1 << 3),
209 PRB_PROT_WRITE = (1 << 4),
210 PRB_PROT_TRANSPARENT = (1 << 5),
211
edb33667
TH		 212 /*
213 * Other constants
214 */
215 SGE_TRM = (1 << 31), /* Last SGE in chain */
d10cb35a
TH		 216 SGE_LNK = (1 << 30), /* linked list
217 Points to SGT, not SGE */
218 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
219 data address ignored */
edb33667 220
aee10a03
TH		 221 SIL24_MAX_CMDS = 31,
222
edb33667
TH		 223 /* board id */
224 BID_SIL3124 = 0,
225 BID_SIL3132 = 1,
042c21fd 226 BID_SIL3131 = 2,
edb33667 227
9466d85b
TH		 228 /* host flags */
229 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
aee10a03
TH		 230 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
231 ATA_FLAG_NCQ,
37024e8e 232 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
9466d85b 233
edb33667
TH		 234 IRQ_STAT_4PORTS = 0xf,
235};
236
69ad185f 237struct sil24_ata_block {
edb33667
TH		 238 struct sil24_prb prb;
239 struct sil24_sge sge[LIBATA_MAX_PRD];
240};
241
69ad185f
TH		 242struct sil24_atapi_block {
243 struct sil24_prb prb;
244 u8 cdb[16];
245 struct sil24_sge sge[LIBATA_MAX_PRD - 1];
246};
247
248union sil24_cmd_block {
249 struct sil24_ata_block ata;
250 struct sil24_atapi_block atapi;
251};
252
88ce7550
TH		 253static struct sil24_cerr_info {
254 unsigned int err_mask, action;
255 const char *desc;
256} sil24_cerr_db[] = {
257 [0] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
258 "device error" },
259 [PORT_CERR_DEV] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
260 "device error via D2H FIS" },
261 [PORT_CERR_SDB] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
262 "device error via SDB FIS" },
263 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
264 "error in data FIS" },
265 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
266 "failed to transmit command FIS" },
267 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
268 "protocol mismatch" },
269 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
270 "data directon mismatch" },
271 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
272 "ran out of SGEs while writing" },
273 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
274 "ran out of SGEs while reading" },
275 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
276 "invalid data directon for ATAPI CDB" },
277 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
278 "SGT no on qword boundary" },
279 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
280 "PCI target abort while fetching SGT" },
281 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
282 "PCI master abort while fetching SGT" },
283 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
284 "PCI parity error while fetching SGT" },
285 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
286 "PRB not on qword boundary" },
287 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
288 "PCI target abort while fetching PRB" },
289 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
290 "PCI master abort while fetching PRB" },
291 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
292 "PCI parity error while fetching PRB" },
293 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
294 "undefined error while transferring data" },
295 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
296 "PCI target abort while transferring data" },
297 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
298 "PCI master abort while transferring data" },
299 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
300 "PCI parity error while transferring data" },
301 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
302 "FIS received while sending service FIS" },
303};
304
edb33667
TH		 305/*
306 * ap->private_data
307 *
308 * The preview driver always returned 0 for status. We emulate it
309 * here from the previous interrupt.
310 */
311struct sil24_port_priv {
69ad185f 312 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
edb33667 313 dma_addr_t cmd_block_dma; /* DMA base addr for them */
6a575fa9 314 struct ata_taskfile tf; /* Cached taskfile registers */
edb33667
TH		 315};
316
317/* ap->host_set->private_data */
318struct sil24_host_priv {
4b4a5eae
AV		 319 void __iomem *host_base; /* global controller control (128 bytes @BAR0) */
320 void __iomem *port_base; /* port registers (4 * 8192 bytes @BAR2) */
edb33667
TH		 321};
322
69ad185f 323static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev);
edb33667 324static u8 sil24_check_status(struct ata_port *ap);
edb33667
TH		 325static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg);
326static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
7f726d12 327static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
07b73470 328static int sil24_probe_reset(struct ata_port *ap, unsigned int *classes);
edb33667 329static void sil24_qc_prep(struct ata_queued_cmd *qc);
9a3d9eb0 330static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
edb33667 331static void sil24_irq_clear(struct ata_port *ap);
edb33667 332static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
88ce7550
TH		 333static void sil24_freeze(struct ata_port *ap);
334static void sil24_thaw(struct ata_port *ap);
335static void sil24_error_handler(struct ata_port *ap);
336static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
edb33667
TH		 337static int sil24_port_start(struct ata_port *ap);
338static void sil24_port_stop(struct ata_port *ap);
339static void sil24_host_stop(struct ata_host_set *host_set);
340static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
341
3b7d697d 342static const struct pci_device_id sil24_pci_tbl[] = {
edb33667 343 { 0x1095, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 },
4b9d7e04 344 { 0x8086, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 },
edb33667 345 { 0x1095, 0x3132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3132 },
042c21fd
TH		 346 { 0x1095, 0x3131, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
347 { 0x1095, 0x3531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
1fcce839 348 { } /* terminate list */
edb33667
TH		 349};
350
351static struct pci_driver sil24_pci_driver = {
352 .name = DRV_NAME,
353 .id_table = sil24_pci_tbl,
354 .probe = sil24_init_one,
355 .remove = ata_pci_remove_one, /* safe? */
356};
357
193515d5 358static struct scsi_host_template sil24_sht = {
edb33667
TH		 359 .module = THIS_MODULE,
360 .name = DRV_NAME,
361 .ioctl = ata_scsi_ioctl,
362 .queuecommand = ata_scsi_queuecmd,
aee10a03
TH		 363 .change_queue_depth = ata_scsi_change_queue_depth,
364 .can_queue = SIL24_MAX_CMDS,
edb33667
TH		 365 .this_id = ATA_SHT_THIS_ID,
366 .sg_tablesize = LIBATA_MAX_PRD,
edb33667
TH		 367 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
368 .emulated = ATA_SHT_EMULATED,
369 .use_clustering = ATA_SHT_USE_CLUSTERING,
370 .proc_name = DRV_NAME,
371 .dma_boundary = ATA_DMA_BOUNDARY,
372 .slave_configure = ata_scsi_slave_config,
373 .bios_param = ata_std_bios_param,
edb33667
TH		 374};
375
057ace5e 376static const struct ata_port_operations sil24_ops = {
edb33667
TH		 377 .port_disable = ata_port_disable,
378
69ad185f
TH		 379 .dev_config = sil24_dev_config,
380
edb33667
TH		 381 .check_status = sil24_check_status,
382 .check_altstatus = sil24_check_status,
edb33667
TH		 383 .dev_select = ata_noop_dev_select,
384
7f726d12
TH		 385 .tf_read = sil24_tf_read,
386
07b73470 387 .probe_reset = sil24_probe_reset,
edb33667
TH		 388
389 .qc_prep = sil24_qc_prep,
390 .qc_issue = sil24_qc_issue,
391
edb33667
TH		 392 .irq_handler = sil24_interrupt,
393 .irq_clear = sil24_irq_clear,
394
395 .scr_read = sil24_scr_read,
396 .scr_write = sil24_scr_write,
397
88ce7550
TH		 398 .freeze = sil24_freeze,
399 .thaw = sil24_thaw,
400 .error_handler = sil24_error_handler,
401 .post_internal_cmd = sil24_post_internal_cmd,
402
edb33667
TH		 403 .port_start = sil24_port_start,
404 .port_stop = sil24_port_stop,
405 .host_stop = sil24_host_stop,
406};
407
042c21fd
TH		 408/*
409 * Use bits 30-31 of host_flags to encode available port numbers.
410 * Current maxium is 4.
411 */
412#define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
413#define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
414
edb33667
TH		 415static struct ata_port_info sil24_port_info[] = {
416 /* sil_3124 */
417 {
418 .sht = &sil24_sht,
37024e8e
TH		 419 .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
420 SIL24_FLAG_PCIX_IRQ_WOC,
edb33667
TH		 421 .pio_mask = 0x1f, /* pio0-4 */
422 .mwdma_mask = 0x07, /* mwdma0-2 */
423 .udma_mask = 0x3f, /* udma0-5 */
424 .port_ops = &sil24_ops,
425 },
2e9edbf8 426 /* sil_3132 */
edb33667
TH		 427 {
428 .sht = &sil24_sht,
9466d85b 429 .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
042c21fd
TH		 430 .pio_mask = 0x1f, /* pio0-4 */
431 .mwdma_mask = 0x07, /* mwdma0-2 */
432 .udma_mask = 0x3f, /* udma0-5 */
433 .port_ops = &sil24_ops,
434 },
435 /* sil_3131/sil_3531 */
436 {
437 .sht = &sil24_sht,
9466d85b 438 .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
edb33667
TH		 439 .pio_mask = 0x1f, /* pio0-4 */
440 .mwdma_mask = 0x07, /* mwdma0-2 */
441 .udma_mask = 0x3f, /* udma0-5 */
442 .port_ops = &sil24_ops,
443 },
444};
445
aee10a03
TH		 446static int sil24_tag(int tag)
447{
448 if (unlikely(ata_tag_internal(tag)))
449 return 0;
450 return tag;
451}
452
69ad185f
TH		 453static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev)
454{
455 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
456
6e7846e9 457 if (dev->cdb_len == 16)
69ad185f
TH		 458 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
459 else
460 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
461}
462
6a575fa9
TH		 463static inline void sil24_update_tf(struct ata_port *ap)
464{
465 struct sil24_port_priv *pp = ap->private_data;
4b4a5eae
AV		 466 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
467 struct sil24_prb __iomem *prb = port;
468 u8 fis[6 * 4];
6a575fa9 469
4b4a5eae
AV		 470 memcpy_fromio(fis, prb->fis, 6 * 4);
471 ata_tf_from_fis(fis, &pp->tf);
6a575fa9
TH		 472}
473
edb33667
TH		 474static u8 sil24_check_status(struct ata_port *ap)
475{
6a575fa9
TH		 476 struct sil24_port_priv *pp = ap->private_data;
477 return pp->tf.command;
edb33667
TH		 478}
479
edb33667
TH		 480static int sil24_scr_map[] = {
481 [SCR_CONTROL] = 0,
482 [SCR_STATUS] = 1,
483 [SCR_ERROR] = 2,
484 [SCR_ACTIVE] = 3,
485};
486
487static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg)
488{
4b4a5eae 489 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
edb33667 490 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
4b4a5eae 491 void __iomem *addr;
edb33667
TH		 492 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
493 return readl(scr_addr + sil24_scr_map[sc_reg] * 4);
494 }
495 return 0xffffffffU;
496}
497
498static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
499{
4b4a5eae 500 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
edb33667 501 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
4b4a5eae 502 void __iomem *addr;
edb33667
TH		 503 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
504 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
505 }
506}
507
7f726d12
TH		 508static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
509{
510 struct sil24_port_priv *pp = ap->private_data;
511 *tf = pp->tf;
512}
513
b5bc421c
TH		 514static int sil24_init_port(struct ata_port *ap)
515{
516 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
517 u32 tmp;
518
519 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
520 ata_wait_register(port + PORT_CTRL_STAT,
521 PORT_CS_INIT, PORT_CS_INIT, 10, 100);
522 tmp = ata_wait_register(port + PORT_CTRL_STAT,
523 PORT_CS_RDY, 0, 10, 100);
524
525 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
526 return -EIO;
527 return 0;
528}
529
2bf2cb26 530static int sil24_softreset(struct ata_port *ap, unsigned int *class)
edb33667 531{
ca45160d
TH		 532 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
533 struct sil24_port_priv *pp = ap->private_data;
69ad185f 534 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
ca45160d 535 dma_addr_t paddr = pp->cmd_block_dma;
88ce7550 536 u32 mask, irq_stat;
643be977 537 const char *reason;
ca45160d 538
07b73470
TH		 539 DPRINTK("ENTER\n");
540
81952c54 541 if (ata_port_offline(ap)) {
10d996ad
TH		 542 DPRINTK("PHY reports no device\n");
543 *class = ATA_DEV_NONE;
544 goto out;
545 }
546
2555d6c2
TH		 547 /* put the port into known state */
548 if (sil24_init_port(ap)) {
549 reason ="port not ready";
550 goto err;
551 }
552
0eaa6058 553 /* do SRST */
bad28a37 554 prb->ctrl = cpu_to_le16(PRB_CTRL_SRST);
ca45160d
TH		 555 prb->fis[1] = 0; /* no PM yet */
556
557 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
26ec634c 558 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
ca45160d 559
7dd29dd6
TH		 560 mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
561 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, mask, 0x0,
562 100, ATA_TMOUT_BOOT / HZ * 1000);
ca45160d 563
7dd29dd6
TH		 564 writel(irq_stat, port + PORT_IRQ_STAT); /* clear IRQs */
565 irq_stat >>= PORT_IRQ_RAW_SHIFT;
ca45160d 566
10d996ad 567 if (!(irq_stat & PORT_IRQ_COMPLETE)) {
643be977
TH		 568 if (irq_stat & PORT_IRQ_ERROR)
569 reason = "SRST command error";
570 else
571 reason = "timeout";
572 goto err;
07b73470 573 }
10d996ad
TH		 574
575 sil24_update_tf(ap);
576 *class = ata_dev_classify(&pp->tf);
577
07b73470
TH		 578 if (*class == ATA_DEV_UNKNOWN)
579 *class = ATA_DEV_NONE;
ca45160d 580
10d996ad 581 out:
07b73470 582 DPRINTK("EXIT, class=%u\n", *class);
ca45160d 583 return 0;
643be977
TH		 584
585 err:
f15a1daf 586 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
643be977 587 return -EIO;
ca45160d
TH		 588}
589
2bf2cb26 590static int sil24_hardreset(struct ata_port *ap, unsigned int *class)
489ff4c7 591{
ecc2e2b9
TH		 592 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
593 const char *reason;
594 int tout_msec;
595 u32 tmp;
596
597 /* sil24 does the right thing(tm) without any protection */
3c567b7d 598 sata_set_spd(ap);
ecc2e2b9
TH		 599
600 tout_msec = 100;
81952c54 601 if (ata_port_online(ap))
ecc2e2b9
TH		 602 tout_msec = 5000;
603
604 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
605 tmp = ata_wait_register(port + PORT_CTRL_STAT,
606 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, tout_msec);
607
608 /* SStatus oscillates between zero and valid status for short
609 * duration after DEV_RST, give it time to settle.
610 */
611 msleep(100);
612
613 if (tmp & PORT_CS_DEV_RST) {
81952c54 614 if (ata_port_offline(ap))
ecc2e2b9
TH		 615 return 0;
616 reason = "link not ready";
617 goto err;
618 }
619
620 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
621 reason = "device not ready";
622 goto err;
623 }
489ff4c7 624
ecc2e2b9
TH		 625 /* sil24 doesn't report device class code after hardreset,
626 * leave *class alone.
627 */
628 return 0;
629
630 err:
f15a1daf 631 ata_port_printk(ap, KERN_ERR, "hardreset failed (%s)\n", reason);
ecc2e2b9 632 return -EIO;
489ff4c7
TH		 633}
634
07b73470 635static int sil24_probe_reset(struct ata_port *ap, unsigned int *classes)
ca45160d 636{
07b73470 637 return ata_drive_probe_reset(ap, ata_std_probeinit,
489ff4c7 638 sil24_softreset, sil24_hardreset,
07b73470 639 ata_std_postreset, classes);
edb33667
TH		 640}
641
642static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
69ad185f 643 struct sil24_sge *sge)
edb33667 644{
972c26bd
JG		 645 struct scatterlist *sg;
646 unsigned int idx = 0;
edb33667 647
972c26bd 648 ata_for_each_sg(sg, qc) {
edb33667
TH		 649 sge->addr = cpu_to_le64(sg_dma_address(sg));
650 sge->cnt = cpu_to_le32(sg_dma_len(sg));
972c26bd
JG		 651 if (ata_sg_is_last(sg, qc))
652 sge->flags = cpu_to_le32(SGE_TRM);
653 else
654 sge->flags = 0;
655
656 sge++;
657 idx++;
edb33667
TH		 658 }
659}
660
661static void sil24_qc_prep(struct ata_queued_cmd *qc)
662{
663 struct ata_port *ap = qc->ap;
664 struct sil24_port_priv *pp = ap->private_data;
aee10a03 665 union sil24_cmd_block *cb;
69ad185f
TH		 666 struct sil24_prb *prb;
667 struct sil24_sge *sge;
bad28a37 668 u16 ctrl = 0;
edb33667 669
aee10a03
TH		 670 cb = &pp->cmd_block[sil24_tag(qc->tag)];
671
edb33667
TH		 672 switch (qc->tf.protocol) {
673 case ATA_PROT_PIO:
674 case ATA_PROT_DMA:
aee10a03 675 case ATA_PROT_NCQ:
edb33667 676 case ATA_PROT_NODATA:
69ad185f
TH		 677 prb = &cb->ata.prb;
678 sge = cb->ata.sge;
edb33667 679 break;
69ad185f
TH		 680
681 case ATA_PROT_ATAPI:
682 case ATA_PROT_ATAPI_DMA:
683 case ATA_PROT_ATAPI_NODATA:
684 prb = &cb->atapi.prb;
685 sge = cb->atapi.sge;
686 memset(cb->atapi.cdb, 0, 32);
6e7846e9 687 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
69ad185f
TH		 688
689 if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) {
690 if (qc->tf.flags & ATA_TFLAG_WRITE)
bad28a37 691 ctrl = PRB_CTRL_PACKET_WRITE;
69ad185f 692 else
bad28a37
TH		 693 ctrl = PRB_CTRL_PACKET_READ;
694 }
69ad185f
TH		 695 break;
696
edb33667 697 default:
69ad185f
TH		 698 prb = NULL; /* shut up, gcc */
699 sge = NULL;
edb33667
TH		 700 BUG();
701 }
702
bad28a37 703 prb->ctrl = cpu_to_le16(ctrl);
edb33667
TH		 704 ata_tf_to_fis(&qc->tf, prb->fis, 0);
705
706 if (qc->flags & ATA_QCFLAG_DMAMAP)
69ad185f 707 sil24_fill_sg(qc, sge);
edb33667
TH		 708}
709
9a3d9eb0 710static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
edb33667
TH		 711{
712 struct ata_port *ap = qc->ap;
713 struct sil24_port_priv *pp = ap->private_data;
aee10a03
TH		 714 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
715 unsigned int tag = sil24_tag(qc->tag);
716 dma_addr_t paddr;
717 void __iomem *activate;
edb33667 718
aee10a03
TH		 719 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
720 activate = port + PORT_CMD_ACTIVATE + tag * 8;
721
722 writel((u32)paddr, activate);
723 writel((u64)paddr >> 32, activate + 4);
26ec634c 724
edb33667
TH		 725 return 0;
726}
727
728static void sil24_irq_clear(struct ata_port *ap)
729{
730 /* unused */
731}
732
88ce7550 733static void sil24_freeze(struct ata_port *ap)
7d1ce682 734{
88ce7550 735 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
7d1ce682 736
88ce7550
TH		 737 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
738 * PORT_IRQ_ENABLE instead.
739 */
740 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
7d1ce682
TH		 741}
742
88ce7550 743static void sil24_thaw(struct ata_port *ap)
edb33667 744{
88ce7550 745 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
edb33667
TH		 746 u32 tmp;
747
88ce7550
TH		 748 /* clear IRQ */
749 tmp = readl(port + PORT_IRQ_STAT);
750 writel(tmp, port + PORT_IRQ_STAT);
edb33667 751
88ce7550
TH		 752 /* turn IRQ back on */
753 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
edb33667
TH		 754}
755
88ce7550 756static void sil24_error_intr(struct ata_port *ap)
8746618d 757{
4b4a5eae 758 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
88ce7550
TH		 759 struct ata_eh_info *ehi = &ap->eh_info;
760 int freeze = 0;
761 u32 irq_stat;
8746618d 762
88ce7550 763 /* on error, we need to clear IRQ explicitly */
8746618d 764 irq_stat = readl(port + PORT_IRQ_STAT);
88ce7550 765 writel(irq_stat, port + PORT_IRQ_STAT);
ad6e90f6 766
88ce7550
TH		 767 /* first, analyze and record host port events */
768 ata_ehi_clear_desc(ehi);
ad6e90f6 769
88ce7550 770 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
8746618d 771
88ce7550
TH		 772 if (irq_stat & PORT_IRQ_DEV_XCHG) {
773 ehi->err_mask |= AC_ERR_ATA_BUS;
774 /* sil24 doesn't recover very well from phy
775 * disconnection with a softreset. Force hardreset.
6a575fa9 776 */
88ce7550
TH		 777 ehi->action |= ATA_EH_HARDRESET;
778 ata_ehi_push_desc(ehi, ", device_exchanged");
779 freeze = 1;
6a575fa9
TH		 780 }
781
88ce7550
TH		 782 if (irq_stat & PORT_IRQ_UNK_FIS) {
783 ehi->err_mask |= AC_ERR_HSM;
784 ehi->action |= ATA_EH_SOFTRESET;
785 ata_ehi_push_desc(ehi , ", unknown FIS");
786 freeze = 1;
787 }
788
789 /* deal with command error */
790 if (irq_stat & PORT_IRQ_ERROR) {
791 struct sil24_cerr_info *ci = NULL;
792 unsigned int err_mask = 0, action = 0;
793 struct ata_queued_cmd *qc;
794 u32 cerr;
795
796 /* analyze CMD_ERR */
797 cerr = readl(port + PORT_CMD_ERR);
798 if (cerr < ARRAY_SIZE(sil24_cerr_db))
799 ci = &sil24_cerr_db[cerr];
800
801 if (ci && ci->desc) {
802 err_mask |= ci->err_mask;
803 action |= ci->action;
804 ata_ehi_push_desc(ehi, ", %s", ci->desc);
805 } else {
806 err_mask |= AC_ERR_OTHER;
807 action |= ATA_EH_SOFTRESET;
808 ata_ehi_push_desc(ehi, ", unknown command error %d",
809 cerr);
810 }
811
812 /* record error info */
813 qc = ata_qc_from_tag(ap, ap->active_tag);
814 if (qc) {
88ce7550
TH		 815 sil24_update_tf(ap);
816 qc->err_mask |= err_mask;
817 } else
818 ehi->err_mask |= err_mask;
819
820 ehi->action |= action;
a22e2eb0 821 }
88ce7550
TH		 822
823 /* freeze or abort */
824 if (freeze)
825 ata_port_freeze(ap);
826 else
827 ata_port_abort(ap);
8746618d
TH		 828}
829
aee10a03
TH		 830static void sil24_finish_qc(struct ata_queued_cmd *qc)
831{
832 if (qc->flags & ATA_QCFLAG_RESULT_TF)
833 sil24_update_tf(qc->ap);
834}
835
edb33667
TH		 836static inline void sil24_host_intr(struct ata_port *ap)
837{
4b4a5eae 838 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
aee10a03
TH		 839 u32 slot_stat, qc_active;
840 int rc;
edb33667
TH		 841
842 slot_stat = readl(port + PORT_SLOT_STAT);
37024e8e 843
88ce7550
TH		 844 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
845 sil24_error_intr(ap);
846 return;
847 }
848
849 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
850 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
37024e8e 851
aee10a03
TH		 852 qc_active = slot_stat & ~HOST_SSTAT_ATTN;
853 rc = ata_qc_complete_multiple(ap, qc_active, sil24_finish_qc);
854 if (rc > 0)
855 return;
856 if (rc < 0) {
857 struct ata_eh_info *ehi = &ap->eh_info;
858 ehi->err_mask |= AC_ERR_HSM;
859 ehi->action |= ATA_EH_SOFTRESET;
860 ata_port_freeze(ap);
88ce7550
TH		 861 return;
862 }
863
864 if (ata_ratelimit())
865 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
aee10a03
TH		 866 "(slot_stat 0x%x active_tag %d sactive 0x%x)\n",
867 slot_stat, ap->active_tag, ap->sactive);
edb33667
TH		 868}
869
870static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
871{
872 struct ata_host_set *host_set = dev_instance;
873 struct sil24_host_priv *hpriv = host_set->private_data;
874 unsigned handled = 0;
875 u32 status;
876 int i;
877
878 status = readl(hpriv->host_base + HOST_IRQ_STAT);
879
06460aea
TH		 880 if (status == 0xffffffff) {
881 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
882 "PCI fault or device removal?\n");
883 goto out;
884 }
885
edb33667
TH		 886 if (!(status & IRQ_STAT_4PORTS))
887 goto out;
888
889 spin_lock(&host_set->lock);
890
891 for (i = 0; i < host_set->n_ports; i++)
892 if (status & (1 << i)) {
893 struct ata_port *ap = host_set->ports[i];
198e0fed 894 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
edb33667 895 sil24_host_intr(host_set->ports[i]);
3cc4571c
TH		 896 handled++;
897 } else
898 printk(KERN_ERR DRV_NAME
899 ": interrupt from disabled port %d\n", i);
edb33667
TH		 900 }
901
902 spin_unlock(&host_set->lock);
903 out:
904 return IRQ_RETVAL(handled);
905}
906
88ce7550
TH		 907static void sil24_error_handler(struct ata_port *ap)
908{
909 struct ata_eh_context *ehc = &ap->eh_context;
910
911 if (sil24_init_port(ap)) {
912 ata_eh_freeze_port(ap);
913 ehc->i.action |= ATA_EH_HARDRESET;
914 }
915
916 /* perform recovery */
f5914a46
TH		 917 ata_do_eh(ap, ata_std_prereset, sil24_softreset, sil24_hardreset,
918 ata_std_postreset);
88ce7550
TH		 919}
920
921static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
922{
923 struct ata_port *ap = qc->ap;
924
925 if (qc->flags & ATA_QCFLAG_FAILED)
926 qc->err_mask |= AC_ERR_OTHER;
927
928 /* make DMA engine forget about the failed command */
929 if (qc->err_mask)
930 sil24_init_port(ap);
931}
932
6037d6bb
JG		 933static inline void sil24_cblk_free(struct sil24_port_priv *pp, struct device *dev)
934{
aee10a03 935 const size_t cb_size = sizeof(*pp->cmd_block) * SIL24_MAX_CMDS;
6037d6bb
JG		 936
937 dma_free_coherent(dev, cb_size, pp->cmd_block, pp->cmd_block_dma);
938}
939
edb33667
TH		 940static int sil24_port_start(struct ata_port *ap)
941{
942 struct device *dev = ap->host_set->dev;
edb33667 943 struct sil24_port_priv *pp;
69ad185f 944 union sil24_cmd_block *cb;
aee10a03 945 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
edb33667 946 dma_addr_t cb_dma;
6037d6bb 947 int rc = -ENOMEM;
edb33667 948
6037d6bb 949 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
edb33667 950 if (!pp)
6037d6bb 951 goto err_out;
edb33667 952
6a575fa9
TH		 953 pp->tf.command = ATA_DRDY;
954
edb33667 955 cb = dma_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
6037d6bb
JG		 956 if (!cb)
957 goto err_out_pp;
edb33667
TH		 958 memset(cb, 0, cb_size);
959
6037d6bb
JG		 960 rc = ata_pad_alloc(ap, dev);
961 if (rc)
962 goto err_out_pad;
963
edb33667
TH		 964 pp->cmd_block = cb;
965 pp->cmd_block_dma = cb_dma;
966
967 ap->private_data = pp;
968
969 return 0;
6037d6bb
JG		 970
971err_out_pad:
972 sil24_cblk_free(pp, dev);
973err_out_pp:
974 kfree(pp);
975err_out:
976 return rc;
edb33667
TH		 977}
978
979static void sil24_port_stop(struct ata_port *ap)
980{
981 struct device *dev = ap->host_set->dev;
982 struct sil24_port_priv *pp = ap->private_data;
edb33667 983
6037d6bb 984 sil24_cblk_free(pp, dev);
e9c05afa 985 ata_pad_free(ap, dev);
edb33667
TH		 986 kfree(pp);
987}
988
989static void sil24_host_stop(struct ata_host_set *host_set)
990{
991 struct sil24_host_priv *hpriv = host_set->private_data;
142877b0 992 struct pci_dev *pdev = to_pci_dev(host_set->dev);
edb33667 993
142877b0
JG		 994 pci_iounmap(pdev, hpriv->host_base);
995 pci_iounmap(pdev, hpriv->port_base);
edb33667
TH		 996 kfree(hpriv);
997}
998
999static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1000{
1001 static int printed_version = 0;
1002 unsigned int board_id = (unsigned int)ent->driver_data;
042c21fd 1003 struct ata_port_info *pinfo = &sil24_port_info[board_id];
edb33667
TH		 1004 struct ata_probe_ent *probe_ent = NULL;
1005 struct sil24_host_priv *hpriv = NULL;
4b4a5eae
AV		 1006 void __iomem *host_base = NULL;
1007 void __iomem *port_base = NULL;
edb33667 1008 int i, rc;
37024e8e 1009 u32 tmp;
edb33667
TH		 1010
1011 if (!printed_version++)
a9524a76 1012 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
edb33667
TH		 1013
1014 rc = pci_enable_device(pdev);
1015 if (rc)
1016 return rc;
1017
1018 rc = pci_request_regions(pdev, DRV_NAME);
1019 if (rc)
1020 goto out_disable;
1021
1022 rc = -ENOMEM;
142877b0
JG		 1023 /* map mmio registers */
1024 host_base = pci_iomap(pdev, 0, 0);
edb33667
TH		 1025 if (!host_base)
1026 goto out_free;
142877b0 1027 port_base = pci_iomap(pdev, 2, 0);
edb33667
TH		 1028 if (!port_base)
1029 goto out_free;
1030
1031 /* allocate & init probe_ent and hpriv */
142877b0 1032 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
edb33667
TH		 1033 if (!probe_ent)
1034 goto out_free;
1035
142877b0 1036 hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
edb33667
TH		 1037 if (!hpriv)
1038 goto out_free;
1039
edb33667
TH		 1040 probe_ent->dev = pci_dev_to_dev(pdev);
1041 INIT_LIST_HEAD(&probe_ent->node);
1042
042c21fd
TH		 1043 probe_ent->sht = pinfo->sht;
1044 probe_ent->host_flags = pinfo->host_flags;
1045 probe_ent->pio_mask = pinfo->pio_mask;
fbfda6e7 1046 probe_ent->mwdma_mask = pinfo->mwdma_mask;
042c21fd
TH		 1047 probe_ent->udma_mask = pinfo->udma_mask;
1048 probe_ent->port_ops = pinfo->port_ops;
1049 probe_ent->n_ports = SIL24_FLAG2NPORTS(pinfo->host_flags);
edb33667
TH		 1050
1051 probe_ent->irq = pdev->irq;
1052 probe_ent->irq_flags = SA_SHIRQ;
1053 probe_ent->mmio_base = port_base;
1054 probe_ent->private_data = hpriv;
1055
edb33667
TH		 1056 hpriv->host_base = host_base;
1057 hpriv->port_base = port_base;
1058
1059 /*
1060 * Configure the device
1061 */
26ec634c
TH		 1062 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1063 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1064 if (rc) {
1065 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1066 if (rc) {
1067 dev_printk(KERN_ERR, &pdev->dev,
1068 "64-bit DMA enable failed\n");
1069 goto out_free;
1070 }
1071 }
1072 } else {
1073 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1074 if (rc) {
1075 dev_printk(KERN_ERR, &pdev->dev,
1076 "32-bit DMA enable failed\n");
1077 goto out_free;
1078 }
1079 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1080 if (rc) {
1081 dev_printk(KERN_ERR, &pdev->dev,
1082 "32-bit consistent DMA enable failed\n");
1083 goto out_free;
1084 }
edb33667
TH		 1085 }
1086
1087 /* GPIO off */
1088 writel(0, host_base + HOST_FLASH_CMD);
1089
37024e8e
TH		 1090 /* Apply workaround for completion IRQ loss on PCI-X errata */
1091 if (probe_ent->host_flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1092 tmp = readl(host_base + HOST_CTRL);
1093 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1094 dev_printk(KERN_INFO, &pdev->dev,
1095 "Applying completion IRQ loss on PCI-X "
1096 "errata fix\n");
1097 else
1098 probe_ent->host_flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1099 }
1100
7dd29dd6 1101 /* clear global reset & mask interrupts during initialization */
edb33667
TH		 1102 writel(0, host_base + HOST_CTRL);
1103
1104 for (i = 0; i < probe_ent->n_ports; i++) {
4b4a5eae 1105 void __iomem *port = port_base + i * PORT_REGS_SIZE;
edb33667 1106 unsigned long portu = (unsigned long)port;
edb33667 1107
135da345 1108 probe_ent->port[i].cmd_addr = portu;
edb33667
TH		 1109 probe_ent->port[i].scr_addr = portu + PORT_SCONTROL;
1110
1111 ata_std_ports(&probe_ent->port[i]);
1112
1113 /* Initial PHY setting */
1114 writel(0x20c, port + PORT_PHY_CFG);
1115
1116 /* Clear port RST */
1117 tmp = readl(port + PORT_CTRL_STAT);
1118 if (tmp & PORT_CS_PORT_RST) {
1119 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
7dd29dd6
TH		 1120 tmp = ata_wait_register(port + PORT_CTRL_STAT,
1121 PORT_CS_PORT_RST,
1122 PORT_CS_PORT_RST, 10, 100);
edb33667 1123 if (tmp & PORT_CS_PORT_RST)
a9524a76
JG		 1124 dev_printk(KERN_ERR, &pdev->dev,
1125 "failed to clear port RST\n");
edb33667
TH		 1126 }
1127
37024e8e
TH		 1128 /* Configure IRQ WoC */
1129 if (probe_ent->host_flags & SIL24_FLAG_PCIX_IRQ_WOC)
1130 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
1131 else
1132 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
1133
edb33667
TH		 1134 /* Zero error counters. */
1135 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
1136 writel(0x8000, port + PORT_CRC_ERR_THRESH);
1137 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
1138 writel(0x0000, port + PORT_DECODE_ERR_CNT);
1139 writel(0x0000, port + PORT_CRC_ERR_CNT);
1140 writel(0x0000, port + PORT_HSHK_ERR_CNT);
1141
26ec634c
TH		 1142 /* Always use 64bit activation */
1143 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
edb33667 1144
923f1225
TH		 1145 /* Clear port multiplier enable and resume bits */
1146 writel(PORT_CS_PM_EN | PORT_CS_RESUME, port + PORT_CTRL_CLR);
edb33667
TH		 1147 }
1148
1149 /* Turn on interrupts */
1150 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1151
1152 pci_set_master(pdev);
1153
1483467f 1154 /* FIXME: check ata_device_add return value */
edb33667
TH		 1155 ata_device_add(probe_ent);
1156
1157 kfree(probe_ent);
1158 return 0;
1159
1160 out_free:
1161 if (host_base)
142877b0 1162 pci_iounmap(pdev, host_base);
edb33667 1163 if (port_base)
142877b0 1164 pci_iounmap(pdev, port_base);
edb33667
TH		 1165 kfree(probe_ent);
1166 kfree(hpriv);
1167 pci_release_regions(pdev);
1168 out_disable:
1169 pci_disable_device(pdev);
1170 return rc;
1171}
1172
1173static int __init sil24_init(void)
1174{
1175 return pci_module_init(&sil24_pci_driver);
1176}
1177
1178static void __exit sil24_exit(void)
1179{
1180 pci_unregister_driver(&sil24_pci_driver);
1181}
1182
1183MODULE_AUTHOR("Tejun Heo");
1184MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1185MODULE_LICENSE("GPL");
1186MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1187
1188module_init(sil24_init);
1189module_exit(sil24_exit);
Linux kernel - Deliverables
This page took 0.140426 seconds and 5 git commands to generate.