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[libata sata_sil24] nit pickings
[deliverable/linux.git] / drivers / scsi / sata_sil24.c
CommitLineData
edb33667
TH		 1/*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
8 * NOTE: No NCQ/ATAPI support yet. The preview driver didn't support
9 * NCQ nor ATAPI, and, unfortunately, I couldn't find out how to make
10 * those work. Enabling those shouldn't be difficult. Basic
11 * structure is all there (in libata-dev tree). If you have any
12 * information about this hardware, please contact me or linux-ide.
13 * Info is needed on...
14 *
15 * - How to issue tagged commands and turn on sactive on issue accordingly.
16 * - Where to put an ATAPI command and how to tell the device to send it.
17 * - How to enable/use 64bit.
18 *
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the
21 * Free Software Foundation; either version 2, or (at your option) any
22 * later version.
23 *
24 * This program is distributed in the hope that it will be useful, but
25 * WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
27 * General Public License for more details.
28 *
29 */
30
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/pci.h>
34#include <linux/blkdev.h>
35#include <linux/delay.h>
36#include <linux/interrupt.h>
37#include <linux/dma-mapping.h>
38#include <scsi/scsi_host.h>
39#include "scsi.h"
40#include <linux/libata.h>
41#include <asm/io.h>
42
43#define DRV_NAME "sata_sil24"
6a575fa9 44#define DRV_VERSION "0.22" /* Silicon Image's preview driver was 0.10 */
edb33667 45
edb33667
TH		 46/*
47 * Port request block (PRB) 32 bytes
48 */
49struct sil24_prb {
50 u16 ctrl;
51 u16 prot;
52 u32 rx_cnt;
53 u8 fis[6 * 4];
54};
55
56/*
57 * Scatter gather entry (SGE) 16 bytes
58 */
59struct sil24_sge {
60 u64 addr;
61 u32 cnt;
62 u32 flags;
63};
64
65/*
66 * Port multiplier
67 */
68struct sil24_port_multiplier {
69 u32 diag;
70 u32 sactive;
71};
72
73enum {
74 /*
75 * Global controller registers (128 bytes @ BAR0)
76 */
77 /* 32 bit regs */
78 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
79 HOST_CTRL = 0x40,
80 HOST_IRQ_STAT = 0x44,
81 HOST_PHY_CFG = 0x48,
82 HOST_BIST_CTRL = 0x50,
83 HOST_BIST_PTRN = 0x54,
84 HOST_BIST_STAT = 0x58,
85 HOST_MEM_BIST_STAT = 0x5c,
86 HOST_FLASH_CMD = 0x70,
87 /* 8 bit regs */
88 HOST_FLASH_DATA = 0x74,
89 HOST_TRANSITION_DETECT = 0x75,
90 HOST_GPIO_CTRL = 0x76,
91 HOST_I2C_ADDR = 0x78, /* 32 bit */
92 HOST_I2C_DATA = 0x7c,
93 HOST_I2C_XFER_CNT = 0x7e,
94 HOST_I2C_CTRL = 0x7f,
95
96 /* HOST_SLOT_STAT bits */
97 HOST_SSTAT_ATTN = (1 << 31),
98
99 /*
100 * Port registers
101 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
102 */
103 PORT_REGS_SIZE = 0x2000,
104 PORT_PRB = 0x0000, /* (32 bytes PRB + 16 bytes SGEs * 6) * 31 (3968 bytes) */
edb33667
TH		 105
106 PORT_PM = 0x0f80, /* 8 bytes PM * 16 (128 bytes) */
107 /* 32 bit regs */
83bbecc9
TH		 108 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
109 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
110 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
111 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
112 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
edb33667 113 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
83bbecc9
TH		 114 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
115 PORT_CMD_ERR = 0x1024, /* command error number */
edb33667
TH		 116 PORT_FIS_CFG = 0x1028,
117 PORT_FIFO_THRES = 0x102c,
118 /* 16 bit regs */
119 PORT_DECODE_ERR_CNT = 0x1040,
120 PORT_DECODE_ERR_THRESH = 0x1042,
121 PORT_CRC_ERR_CNT = 0x1044,
122 PORT_CRC_ERR_THRESH = 0x1046,
123 PORT_HSHK_ERR_CNT = 0x1048,
124 PORT_HSHK_ERR_THRESH = 0x104a,
125 /* 32 bit regs */
126 PORT_PHY_CFG = 0x1050,
127 PORT_SLOT_STAT = 0x1800,
128 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
129 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
130 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
131 PORT_SCONTROL = 0x1f00,
132 PORT_SSTATUS = 0x1f04,
133 PORT_SERROR = 0x1f08,
134 PORT_SACTIVE = 0x1f0c,
135
136 /* PORT_CTRL_STAT bits */
137 PORT_CS_PORT_RST = (1 << 0), /* port reset */
138 PORT_CS_DEV_RST = (1 << 1), /* device reset */
139 PORT_CS_INIT = (1 << 2), /* port initialize */
140 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
e382eb1d
TH		 141 PORT_CS_RESUME = (1 << 6), /* port resume */
142 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
143 PORT_CS_PM_EN = (1 << 13), /* port multiplier enable */
144 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
edb33667
TH		 145
146 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
147 /* bits[11:0] are masked */
148 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
149 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
150 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
151 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
152 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
153 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
154 PORT_IRQ_UNK_FIS = (1 << 6), /* Unknown FIS received */
155 PORT_IRQ_SDB_FIS = (1 << 11), /* SDB FIS received */
156
157 /* bits[27:16] are unmasked (raw) */
158 PORT_IRQ_RAW_SHIFT = 16,
159 PORT_IRQ_MASKED_MASK = 0x7ff,
160 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
161
162 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
163 PORT_IRQ_STEER_SHIFT = 30,
164 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
165
166 /* PORT_CMD_ERR constants */
167 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
168 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
169 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
170 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
171 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
172 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
173 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
174 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
175 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
176 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
177 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
178 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
179 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
180 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
181 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
182 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
183 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
184 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
185 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
186 PORT_CERR_XFR_MSGABRT = 34, /* PSD ecode 10 - master abort */
187 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
83bbecc9 188 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
edb33667
TH		 189
190 /*
191 * Other constants
192 */
193 SGE_TRM = (1 << 31), /* Last SGE in chain */
194 PRB_SOFT_RST = (1 << 7), /* Soft reset request (ign BSY?) */
195
196 /* board id */
197 BID_SIL3124 = 0,
198 BID_SIL3132 = 1,
199
200 IRQ_STAT_4PORTS = 0xf,
201};
202
203struct sil24_cmd_block {
204 struct sil24_prb prb;
205 struct sil24_sge sge[LIBATA_MAX_PRD];
206};
207
208/*
209 * ap->private_data
210 *
211 * The preview driver always returned 0 for status. We emulate it
212 * here from the previous interrupt.
213 */
214struct sil24_port_priv {
edb33667
TH		 215 struct sil24_cmd_block *cmd_block; /* 32 cmd blocks */
216 dma_addr_t cmd_block_dma; /* DMA base addr for them */
6a575fa9 217 struct ata_taskfile tf; /* Cached taskfile registers */
edb33667
TH		 218};
219
220/* ap->host_set->private_data */
221struct sil24_host_priv {
222 void *host_base; /* global controller control (128 bytes @BAR0) */
223 void *port_base; /* port registers (4 * 8192 bytes @BAR2) */
224};
225
226static u8 sil24_check_status(struct ata_port *ap);
227static u8 sil24_check_err(struct ata_port *ap);
228static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg);
229static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
7f726d12 230static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
edb33667
TH		 231static void sil24_phy_reset(struct ata_port *ap);
232static void sil24_qc_prep(struct ata_queued_cmd *qc);
233static int sil24_qc_issue(struct ata_queued_cmd *qc);
234static void sil24_irq_clear(struct ata_port *ap);
235static void sil24_eng_timeout(struct ata_port *ap);
236static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
237static int sil24_port_start(struct ata_port *ap);
238static void sil24_port_stop(struct ata_port *ap);
239static void sil24_host_stop(struct ata_host_set *host_set);
240static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
241
242static struct pci_device_id sil24_pci_tbl[] = {
243 { 0x1095, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 },
244 { 0x1095, 0x3132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3132 },
1fcce839 245 { } /* terminate list */
edb33667
TH		 246};
247
248static struct pci_driver sil24_pci_driver = {
249 .name = DRV_NAME,
250 .id_table = sil24_pci_tbl,
251 .probe = sil24_init_one,
252 .remove = ata_pci_remove_one, /* safe? */
253};
254
255static Scsi_Host_Template sil24_sht = {
256 .module = THIS_MODULE,
257 .name = DRV_NAME,
258 .ioctl = ata_scsi_ioctl,
259 .queuecommand = ata_scsi_queuecmd,
260 .eh_strategy_handler = ata_scsi_error,
261 .can_queue = ATA_DEF_QUEUE,
262 .this_id = ATA_SHT_THIS_ID,
263 .sg_tablesize = LIBATA_MAX_PRD,
264 .max_sectors = ATA_MAX_SECTORS,
265 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
266 .emulated = ATA_SHT_EMULATED,
267 .use_clustering = ATA_SHT_USE_CLUSTERING,
268 .proc_name = DRV_NAME,
269 .dma_boundary = ATA_DMA_BOUNDARY,
270 .slave_configure = ata_scsi_slave_config,
271 .bios_param = ata_std_bios_param,
272 .ordered_flush = 1, /* NCQ not supported yet */
273};
274
275static struct ata_port_operations sil24_ops = {
276 .port_disable = ata_port_disable,
277
278 .check_status = sil24_check_status,
279 .check_altstatus = sil24_check_status,
280 .check_err = sil24_check_err,
281 .dev_select = ata_noop_dev_select,
282
7f726d12
TH		 283 .tf_read = sil24_tf_read,
284
edb33667
TH		 285 .phy_reset = sil24_phy_reset,
286
287 .qc_prep = sil24_qc_prep,
288 .qc_issue = sil24_qc_issue,
289
290 .eng_timeout = sil24_eng_timeout,
291
292 .irq_handler = sil24_interrupt,
293 .irq_clear = sil24_irq_clear,
294
295 .scr_read = sil24_scr_read,
296 .scr_write = sil24_scr_write,
297
298 .port_start = sil24_port_start,
299 .port_stop = sil24_port_stop,
300 .host_stop = sil24_host_stop,
301};
302
303static struct ata_port_info sil24_port_info[] = {
304 /* sil_3124 */
305 {
306 .sht = &sil24_sht,
307 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
308 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
309 ATA_FLAG_PIO_DMA,
310 .pio_mask = 0x1f, /* pio0-4 */
311 .mwdma_mask = 0x07, /* mwdma0-2 */
312 .udma_mask = 0x3f, /* udma0-5 */
313 .port_ops = &sil24_ops,
314 },
315 /* sil_3132 */
316 {
317 .sht = &sil24_sht,
318 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
319 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
320 ATA_FLAG_PIO_DMA,
321 .pio_mask = 0x1f, /* pio0-4 */
322 .mwdma_mask = 0x07, /* mwdma0-2 */
323 .udma_mask = 0x3f, /* udma0-5 */
324 .port_ops = &sil24_ops,
325 },
326};
327
6a575fa9
TH		 328static inline void sil24_update_tf(struct ata_port *ap)
329{
330 struct sil24_port_priv *pp = ap->private_data;
331 void *port = (void *)ap->ioaddr.cmd_addr;
332 struct sil24_prb *prb = port;
333
334 ata_tf_from_fis(prb->fis, &pp->tf);
335}
336
edb33667
TH		 337static u8 sil24_check_status(struct ata_port *ap)
338{
6a575fa9
TH		 339 struct sil24_port_priv *pp = ap->private_data;
340 return pp->tf.command;
edb33667
TH		 341}
342
343static u8 sil24_check_err(struct ata_port *ap)
344{
6a575fa9
TH		 345 struct sil24_port_priv *pp = ap->private_data;
346 return pp->tf.feature;
edb33667
TH		 347}
348
349static int sil24_scr_map[] = {
350 [SCR_CONTROL] = 0,
351 [SCR_STATUS] = 1,
352 [SCR_ERROR] = 2,
353 [SCR_ACTIVE] = 3,
354};
355
356static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg)
357{
358 void *scr_addr = (void *)ap->ioaddr.scr_addr;
359 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
360 void *addr;
361 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
362 return readl(scr_addr + sil24_scr_map[sc_reg] * 4);
363 }
364 return 0xffffffffU;
365}
366
367static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
368{
369 void *scr_addr = (void *)ap->ioaddr.scr_addr;
370 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
371 void *addr;
372 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
373 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
374 }
375}
376
7f726d12
TH		 377static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
378{
379 struct sil24_port_priv *pp = ap->private_data;
380 *tf = pp->tf;
381}
382
edb33667
TH		 383static void sil24_phy_reset(struct ata_port *ap)
384{
385 __sata_phy_reset(ap);
386 /*
387 * No ATAPI yet. Just unconditionally indicate ATA device.
388 * If ATAPI device is attached, it will fail ATA_CMD_ID_ATA
389 * and libata core will ignore the device.
390 */
391 if (!(ap->flags & ATA_FLAG_PORT_DISABLED))
392 ap->device[0].class = ATA_DEV_ATA;
393}
394
395static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
396 struct sil24_cmd_block *cb)
397{
398 struct scatterlist *sg = qc->sg;
399 struct sil24_sge *sge = cb->sge;
400 unsigned i;
401
402 for (i = 0; i < qc->n_elem; i++, sg++, sge++) {
403 sge->addr = cpu_to_le64(sg_dma_address(sg));
404 sge->cnt = cpu_to_le32(sg_dma_len(sg));
405 sge->flags = 0;
406 sge->flags = i < qc->n_elem - 1 ? 0 : cpu_to_le32(SGE_TRM);
407 }
408}
409
410static void sil24_qc_prep(struct ata_queued_cmd *qc)
411{
412 struct ata_port *ap = qc->ap;
413 struct sil24_port_priv *pp = ap->private_data;
414 struct sil24_cmd_block *cb = pp->cmd_block + qc->tag;
415 struct sil24_prb *prb = &cb->prb;
416
417 switch (qc->tf.protocol) {
418 case ATA_PROT_PIO:
419 case ATA_PROT_DMA:
420 case ATA_PROT_NODATA:
421 break;
422 default:
423 /* ATAPI isn't supported yet */
424 BUG();
425 }
426
427 ata_tf_to_fis(&qc->tf, prb->fis, 0);
428
429 if (qc->flags & ATA_QCFLAG_DMAMAP)
430 sil24_fill_sg(qc, cb);
431}
432
433static int sil24_qc_issue(struct ata_queued_cmd *qc)
434{
435 struct ata_port *ap = qc->ap;
4f50c3cb 436 void *port = (void *)ap->ioaddr.cmd_addr;
edb33667
TH		 437 struct sil24_port_priv *pp = ap->private_data;
438 dma_addr_t paddr = pp->cmd_block_dma + qc->tag * sizeof(*pp->cmd_block);
439
4f50c3cb 440 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
edb33667
TH		 441 return 0;
442}
443
444static void sil24_irq_clear(struct ata_port *ap)
445{
446 /* unused */
447}
448
923f1225 449static int __sil24_reset_controller(void *port)
edb33667 450{
edb33667
TH		 451 int cnt;
452 u32 tmp;
453
edb33667
TH		 454 /* Reset controller state. Is this correct? */
455 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
456 readl(port + PORT_CTRL_STAT); /* sync */
457
458 /* Max ~100ms */
459 for (cnt = 0; cnt < 1000; cnt++) {
460 udelay(100);
461 tmp = readl(port + PORT_CTRL_STAT);
462 if (!(tmp & PORT_CS_DEV_RST))
463 break;
464 }
923f1225 465
edb33667 466 if (tmp & PORT_CS_DEV_RST)
923f1225
TH		 467 return -1;
468 return 0;
469}
470
471static void sil24_reset_controller(struct ata_port *ap)
472{
473 printk(KERN_NOTICE DRV_NAME
474 " ata%u: resetting controller...\n", ap->id);
475 if (__sil24_reset_controller((void *)ap->ioaddr.cmd_addr))
476 printk(KERN_ERR DRV_NAME
477 " ata%u: failed to reset controller\n", ap->id);
edb33667
TH		 478}
479
480static void sil24_eng_timeout(struct ata_port *ap)
481{
482 struct ata_queued_cmd *qc;
483
484 qc = ata_qc_from_tag(ap, ap->active_tag);
485 if (!qc) {
486 printk(KERN_ERR "ata%u: BUG: tiemout without command\n",
487 ap->id);
488 return;
489 }
490
491 /*
492 * hack alert! We cannot use the supplied completion
493 * function from inside the ->eh_strategy_handler() thread.
494 * libata is the only user of ->eh_strategy_handler() in
495 * any kernel, so the default scsi_done() assumes it is
496 * not being called from the SCSI EH.
497 */
498 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
499 qc->scsidone = scsi_finish_command;
500 ata_qc_complete(qc, ATA_ERR);
501
502 sil24_reset_controller(ap);
503}
504
8746618d
TH		 505static void sil24_error_intr(struct ata_port *ap, u32 slot_stat)
506{
507 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
6a575fa9 508 struct sil24_port_priv *pp = ap->private_data;
4f50c3cb 509 void *port = (void *)ap->ioaddr.cmd_addr;
8746618d
TH		 510 u32 irq_stat, cmd_err, sstatus, serror;
511
512 irq_stat = readl(port + PORT_IRQ_STAT);
ad6e90f6
TH		 513 writel(irq_stat, port + PORT_IRQ_STAT); /* clear irq */
514
515 if (!(irq_stat & PORT_IRQ_ERROR)) {
516 /* ignore non-completion, non-error irqs for now */
517 printk(KERN_WARNING DRV_NAME
518 "ata%u: non-error exception irq (irq_stat %x)\n",
519 ap->id, irq_stat);
520 return;
521 }
522
8746618d
TH		 523 cmd_err = readl(port + PORT_CMD_ERR);
524 sstatus = readl(port + PORT_SSTATUS);
525 serror = readl(port + PORT_SERROR);
8746618d
TH		 526 if (serror)
527 writel(serror, port + PORT_SERROR);
528
529 printk(KERN_ERR DRV_NAME " ata%u: error interrupt on port%d\n"
530 " stat=0x%x irq=0x%x cmd_err=%d sstatus=0x%x serror=0x%x\n",
531 ap->id, ap->port_no, slot_stat, irq_stat, cmd_err, sstatus, serror);
532
6a575fa9
TH		 533 if (cmd_err == PORT_CERR_DEV || cmd_err == PORT_CERR_SDB) {
534 /*
535 * Device is reporting error, tf registers are valid.
536 */
537 sil24_update_tf(ap);
538 } else {
539 /*
540 * Other errors. libata currently doesn't have any
541 * mechanism to report these errors. Just turn on
542 * ATA_ERR.
543 */
544 pp->tf.command = ATA_ERR;
545 }
546
8746618d 547 if (qc)
6a575fa9 548 ata_qc_complete(qc, pp->tf.command);
8746618d
TH		 549
550 sil24_reset_controller(ap);
551}
552
edb33667
TH		 553static inline void sil24_host_intr(struct ata_port *ap)
554{
555 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
4f50c3cb 556 void *port = (void *)ap->ioaddr.cmd_addr;
edb33667
TH		 557 u32 slot_stat;
558
559 slot_stat = readl(port + PORT_SLOT_STAT);
560 if (!(slot_stat & HOST_SSTAT_ATTN)) {
6a575fa9
TH		 561 struct sil24_port_priv *pp = ap->private_data;
562 /*
563 * !HOST_SSAT_ATTN guarantees successful completion,
564 * so reading back tf registers is unnecessary for
565 * most commands. TODO: read tf registers for
566 * commands which require these values on successful
567 * completion (EXECUTE DEVICE DIAGNOSTIC, CHECK POWER,
568 * DEVICE RESET and READ PORT MULTIPLIER (any more?).
569 */
570 sil24_update_tf(ap);
571
edb33667 572 if (qc)
6a575fa9 573 ata_qc_complete(qc, pp->tf.command);
8746618d
TH		 574 } else
575 sil24_error_intr(ap, slot_stat);
edb33667
TH		 576}
577
578static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
579{
580 struct ata_host_set *host_set = dev_instance;
581 struct sil24_host_priv *hpriv = host_set->private_data;
582 unsigned handled = 0;
583 u32 status;
584 int i;
585
586 status = readl(hpriv->host_base + HOST_IRQ_STAT);
587
06460aea
TH		 588 if (status == 0xffffffff) {
589 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
590 "PCI fault or device removal?\n");
591 goto out;
592 }
593
edb33667
TH		 594 if (!(status & IRQ_STAT_4PORTS))
595 goto out;
596
597 spin_lock(&host_set->lock);
598
599 for (i = 0; i < host_set->n_ports; i++)
600 if (status & (1 << i)) {
601 struct ata_port *ap = host_set->ports[i];
3cc4571c 602 if (ap && !(ap->flags & ATA_FLAG_PORT_DISABLED)) {
edb33667 603 sil24_host_intr(host_set->ports[i]);
3cc4571c
TH		 604 handled++;
605 } else
606 printk(KERN_ERR DRV_NAME
607 ": interrupt from disabled port %d\n", i);
edb33667
TH		 608 }
609
610 spin_unlock(&host_set->lock);
611 out:
612 return IRQ_RETVAL(handled);
613}
614
615static int sil24_port_start(struct ata_port *ap)
616{
617 struct device *dev = ap->host_set->dev;
edb33667
TH		 618 struct sil24_port_priv *pp;
619 struct sil24_cmd_block *cb;
620 size_t cb_size = sizeof(*cb);
621 dma_addr_t cb_dma;
622
623 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
624 if (!pp)
625 return -ENOMEM;
626 memset(pp, 0, sizeof(*pp));
627
6a575fa9
TH		 628 pp->tf.command = ATA_DRDY;
629
edb33667
TH		 630 cb = dma_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
631 if (!cb) {
632 kfree(pp);
633 return -ENOMEM;
634 }
635 memset(cb, 0, cb_size);
636
edb33667
TH		 637 pp->cmd_block = cb;
638 pp->cmd_block_dma = cb_dma;
639
640 ap->private_data = pp;
641
642 return 0;
643}
644
645static void sil24_port_stop(struct ata_port *ap)
646{
647 struct device *dev = ap->host_set->dev;
648 struct sil24_port_priv *pp = ap->private_data;
649 size_t cb_size = sizeof(*pp->cmd_block);
650
651 dma_free_coherent(dev, cb_size, pp->cmd_block, pp->cmd_block_dma);
652 kfree(pp);
653}
654
655static void sil24_host_stop(struct ata_host_set *host_set)
656{
657 struct sil24_host_priv *hpriv = host_set->private_data;
658
659 iounmap(hpriv->host_base);
660 iounmap(hpriv->port_base);
661 kfree(hpriv);
662}
663
664static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
665{
666 static int printed_version = 0;
667 unsigned int board_id = (unsigned int)ent->driver_data;
668 struct ata_probe_ent *probe_ent = NULL;
669 struct sil24_host_priv *hpriv = NULL;
670 void *host_base = NULL, *port_base = NULL;
671 int i, rc;
672
673 if (!printed_version++)
674 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
675
676 rc = pci_enable_device(pdev);
677 if (rc)
678 return rc;
679
680 rc = pci_request_regions(pdev, DRV_NAME);
681 if (rc)
682 goto out_disable;
683
684 rc = -ENOMEM;
685 /* ioremap mmio registers */
686 host_base = ioremap(pci_resource_start(pdev, 0),
687 pci_resource_len(pdev, 0));
688 if (!host_base)
689 goto out_free;
690 port_base = ioremap(pci_resource_start(pdev, 2),
691 pci_resource_len(pdev, 2));
692 if (!port_base)
693 goto out_free;
694
695 /* allocate & init probe_ent and hpriv */
696 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
697 if (!probe_ent)
698 goto out_free;
699
700 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
701 if (!hpriv)
702 goto out_free;
703
704 memset(probe_ent, 0, sizeof(*probe_ent));
705 probe_ent->dev = pci_dev_to_dev(pdev);
706 INIT_LIST_HEAD(&probe_ent->node);
707
708 probe_ent->sht = sil24_port_info[board_id].sht;
709 probe_ent->host_flags = sil24_port_info[board_id].host_flags;
710 probe_ent->pio_mask = sil24_port_info[board_id].pio_mask;
711 probe_ent->udma_mask = sil24_port_info[board_id].udma_mask;
712 probe_ent->port_ops = sil24_port_info[board_id].port_ops;
713 probe_ent->n_ports = (board_id == BID_SIL3124) ? 4 : 2;
714
715 probe_ent->irq = pdev->irq;
716 probe_ent->irq_flags = SA_SHIRQ;
717 probe_ent->mmio_base = port_base;
718 probe_ent->private_data = hpriv;
719
720 memset(hpriv, 0, sizeof(*hpriv));
721 hpriv->host_base = host_base;
722 hpriv->port_base = port_base;
723
724 /*
725 * Configure the device
726 */
727 /*
728 * FIXME: This device is certainly 64-bit capable. We just
729 * don't know how to use it. After fixing 32bit activation in
730 * this function, enable 64bit masks here.
731 */
732 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
733 if (rc) {
734 printk(KERN_ERR DRV_NAME "(%s): 32-bit DMA enable failed\n",
735 pci_name(pdev));
736 goto out_free;
737 }
738 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
739 if (rc) {
740 printk(KERN_ERR DRV_NAME "(%s): 32-bit consistent DMA enable failed\n",
741 pci_name(pdev));
742 goto out_free;
743 }
744
745 /* GPIO off */
746 writel(0, host_base + HOST_FLASH_CMD);
747
748 /* Mask interrupts during initialization */
749 writel(0, host_base + HOST_CTRL);
750
751 for (i = 0; i < probe_ent->n_ports; i++) {
752 void *port = port_base + i * PORT_REGS_SIZE;
753 unsigned long portu = (unsigned long)port;
754 u32 tmp;
755 int cnt;
756
4f50c3cb 757 probe_ent->port[i].cmd_addr = portu + PORT_PRB;
edb33667
TH		 758 probe_ent->port[i].scr_addr = portu + PORT_SCONTROL;
759
760 ata_std_ports(&probe_ent->port[i]);
761
762 /* Initial PHY setting */
763 writel(0x20c, port + PORT_PHY_CFG);
764
765 /* Clear port RST */
766 tmp = readl(port + PORT_CTRL_STAT);
767 if (tmp & PORT_CS_PORT_RST) {
768 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
769 readl(port + PORT_CTRL_STAT); /* sync */
770 for (cnt = 0; cnt < 10; cnt++) {
771 msleep(10);
772 tmp = readl(port + PORT_CTRL_STAT);
773 if (!(tmp & PORT_CS_PORT_RST))
774 break;
775 }
776 if (tmp & PORT_CS_PORT_RST)
777 printk(KERN_ERR DRV_NAME
778 "(%s): failed to clear port RST\n",
779 pci_name(pdev));
780 }
781
782 /* Zero error counters. */
783 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
784 writel(0x8000, port + PORT_CRC_ERR_THRESH);
785 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
786 writel(0x0000, port + PORT_DECODE_ERR_CNT);
787 writel(0x0000, port + PORT_CRC_ERR_CNT);
788 writel(0x0000, port + PORT_HSHK_ERR_CNT);
789
790 /* FIXME: 32bit activation? */
791 writel(0, port + PORT_ACTIVATE_UPPER_ADDR);
792 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_STAT);
793
794 /* Configure interrupts */
795 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
796 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | PORT_IRQ_SDB_FIS,
797 port + PORT_IRQ_ENABLE_SET);
798
799 /* Clear interrupts */
800 writel(0x0fff0fff, port + PORT_IRQ_STAT);
801 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
923f1225
TH		 802
803 /* Clear port multiplier enable and resume bits */
804 writel(PORT_CS_PM_EN | PORT_CS_RESUME, port + PORT_CTRL_CLR);
805
806 /* Reset itself */
807 if (__sil24_reset_controller(port))
808 printk(KERN_ERR DRV_NAME
809 "(%s): failed to reset controller\n",
810 pci_name(pdev));
edb33667
TH		 811 }
812
813 /* Turn on interrupts */
814 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
815
816 pci_set_master(pdev);
817
1483467f 818 /* FIXME: check ata_device_add return value */
edb33667
TH		 819 ata_device_add(probe_ent);
820
821 kfree(probe_ent);
822 return 0;
823
824 out_free:
825 if (host_base)
826 iounmap(host_base);
827 if (port_base)
828 iounmap(port_base);
829 kfree(probe_ent);
830 kfree(hpriv);
831 pci_release_regions(pdev);
832 out_disable:
833 pci_disable_device(pdev);
834 return rc;
835}
836
837static int __init sil24_init(void)
838{
839 return pci_module_init(&sil24_pci_driver);
840}
841
842static void __exit sil24_exit(void)
843{
844 pci_unregister_driver(&sil24_pci_driver);
845}
846
847MODULE_AUTHOR("Tejun Heo");
848MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
849MODULE_LICENSE("GPL");
850MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
851
852module_init(sil24_init);
853module_exit(sil24_exit);
Linux kernel - Deliverables
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