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edb33667 TH |
1 | /* |
2 | * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers | |
3 | * | |
4 | * Copyright 2005 Tejun Heo | |
5 | * | |
6 | * Based on preview driver from Silicon Image. | |
7 | * | |
edb33667 TH |
8 | * This program is free software; you can redistribute it and/or modify it |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2, or (at your option) any | |
11 | * later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <linux/kernel.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/pci.h> | |
23 | #include <linux/blkdev.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/dma-mapping.h> | |
a9524a76 | 27 | #include <linux/device.h> |
edb33667 | 28 | #include <scsi/scsi_host.h> |
193515d5 | 29 | #include <scsi/scsi_cmnd.h> |
edb33667 TH |
30 | #include <linux/libata.h> |
31 | #include <asm/io.h> | |
32 | ||
33 | #define DRV_NAME "sata_sil24" | |
69ad185f | 34 | #define DRV_VERSION "0.23" |
edb33667 | 35 | |
edb33667 TH |
36 | /* |
37 | * Port request block (PRB) 32 bytes | |
38 | */ | |
39 | struct sil24_prb { | |
40 | u16 ctrl; | |
41 | u16 prot; | |
42 | u32 rx_cnt; | |
43 | u8 fis[6 * 4]; | |
44 | }; | |
45 | ||
46 | /* | |
47 | * Scatter gather entry (SGE) 16 bytes | |
48 | */ | |
49 | struct sil24_sge { | |
50 | u64 addr; | |
51 | u32 cnt; | |
52 | u32 flags; | |
53 | }; | |
54 | ||
55 | /* | |
56 | * Port multiplier | |
57 | */ | |
58 | struct sil24_port_multiplier { | |
59 | u32 diag; | |
60 | u32 sactive; | |
61 | }; | |
62 | ||
63 | enum { | |
64 | /* | |
65 | * Global controller registers (128 bytes @ BAR0) | |
66 | */ | |
67 | /* 32 bit regs */ | |
68 | HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */ | |
69 | HOST_CTRL = 0x40, | |
70 | HOST_IRQ_STAT = 0x44, | |
71 | HOST_PHY_CFG = 0x48, | |
72 | HOST_BIST_CTRL = 0x50, | |
73 | HOST_BIST_PTRN = 0x54, | |
74 | HOST_BIST_STAT = 0x58, | |
75 | HOST_MEM_BIST_STAT = 0x5c, | |
76 | HOST_FLASH_CMD = 0x70, | |
77 | /* 8 bit regs */ | |
78 | HOST_FLASH_DATA = 0x74, | |
79 | HOST_TRANSITION_DETECT = 0x75, | |
80 | HOST_GPIO_CTRL = 0x76, | |
81 | HOST_I2C_ADDR = 0x78, /* 32 bit */ | |
82 | HOST_I2C_DATA = 0x7c, | |
83 | HOST_I2C_XFER_CNT = 0x7e, | |
84 | HOST_I2C_CTRL = 0x7f, | |
85 | ||
86 | /* HOST_SLOT_STAT bits */ | |
87 | HOST_SSTAT_ATTN = (1 << 31), | |
88 | ||
89 | /* | |
90 | * Port registers | |
91 | * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2) | |
92 | */ | |
93 | PORT_REGS_SIZE = 0x2000, | |
94 | PORT_PRB = 0x0000, /* (32 bytes PRB + 16 bytes SGEs * 6) * 31 (3968 bytes) */ | |
edb33667 TH |
95 | |
96 | PORT_PM = 0x0f80, /* 8 bytes PM * 16 (128 bytes) */ | |
97 | /* 32 bit regs */ | |
83bbecc9 TH |
98 | PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */ |
99 | PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */ | |
100 | PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */ | |
101 | PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */ | |
102 | PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */ | |
edb33667 | 103 | PORT_ACTIVATE_UPPER_ADDR= 0x101c, |
83bbecc9 TH |
104 | PORT_EXEC_FIFO = 0x1020, /* command execution fifo */ |
105 | PORT_CMD_ERR = 0x1024, /* command error number */ | |
edb33667 TH |
106 | PORT_FIS_CFG = 0x1028, |
107 | PORT_FIFO_THRES = 0x102c, | |
108 | /* 16 bit regs */ | |
109 | PORT_DECODE_ERR_CNT = 0x1040, | |
110 | PORT_DECODE_ERR_THRESH = 0x1042, | |
111 | PORT_CRC_ERR_CNT = 0x1044, | |
112 | PORT_CRC_ERR_THRESH = 0x1046, | |
113 | PORT_HSHK_ERR_CNT = 0x1048, | |
114 | PORT_HSHK_ERR_THRESH = 0x104a, | |
115 | /* 32 bit regs */ | |
116 | PORT_PHY_CFG = 0x1050, | |
117 | PORT_SLOT_STAT = 0x1800, | |
118 | PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */ | |
119 | PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */ | |
120 | PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */ | |
121 | PORT_SCONTROL = 0x1f00, | |
122 | PORT_SSTATUS = 0x1f04, | |
123 | PORT_SERROR = 0x1f08, | |
124 | PORT_SACTIVE = 0x1f0c, | |
125 | ||
126 | /* PORT_CTRL_STAT bits */ | |
127 | PORT_CS_PORT_RST = (1 << 0), /* port reset */ | |
128 | PORT_CS_DEV_RST = (1 << 1), /* device reset */ | |
129 | PORT_CS_INIT = (1 << 2), /* port initialize */ | |
130 | PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */ | |
d10cb35a | 131 | PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */ |
e382eb1d TH |
132 | PORT_CS_RESUME = (1 << 6), /* port resume */ |
133 | PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */ | |
134 | PORT_CS_PM_EN = (1 << 13), /* port multiplier enable */ | |
135 | PORT_CS_RDY = (1 << 31), /* port ready to accept commands */ | |
edb33667 TH |
136 | |
137 | /* PORT_IRQ_STAT/ENABLE_SET/CLR */ | |
138 | /* bits[11:0] are masked */ | |
139 | PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */ | |
140 | PORT_IRQ_ERROR = (1 << 1), /* command execution error */ | |
141 | PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */ | |
142 | PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */ | |
143 | PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */ | |
144 | PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */ | |
145 | PORT_IRQ_UNK_FIS = (1 << 6), /* Unknown FIS received */ | |
146 | PORT_IRQ_SDB_FIS = (1 << 11), /* SDB FIS received */ | |
147 | ||
148 | /* bits[27:16] are unmasked (raw) */ | |
149 | PORT_IRQ_RAW_SHIFT = 16, | |
150 | PORT_IRQ_MASKED_MASK = 0x7ff, | |
151 | PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT), | |
152 | ||
153 | /* ENABLE_SET/CLR specific, intr steering - 2 bit field */ | |
154 | PORT_IRQ_STEER_SHIFT = 30, | |
155 | PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT), | |
156 | ||
157 | /* PORT_CMD_ERR constants */ | |
158 | PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */ | |
159 | PORT_CERR_SDB = 2, /* Error bit in SDB FIS */ | |
160 | PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */ | |
161 | PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */ | |
162 | PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */ | |
163 | PORT_CERR_DIRECTION = 6, /* Data direction mismatch */ | |
164 | PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */ | |
165 | PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */ | |
166 | PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */ | |
167 | PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */ | |
168 | PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */ | |
169 | PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */ | |
170 | PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */ | |
171 | PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */ | |
172 | PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */ | |
173 | PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */ | |
174 | PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */ | |
175 | PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */ | |
176 | PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */ | |
177 | PORT_CERR_XFR_MSGABRT = 34, /* PSD ecode 10 - master abort */ | |
178 | PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */ | |
83bbecc9 | 179 | PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */ |
edb33667 | 180 | |
d10cb35a TH |
181 | /* bits of PRB control field */ |
182 | PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */ | |
183 | PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */ | |
184 | PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */ | |
185 | PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */ | |
186 | PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */ | |
187 | ||
188 | /* PRB protocol field */ | |
189 | PRB_PROT_PACKET = (1 << 0), | |
190 | PRB_PROT_TCQ = (1 << 1), | |
191 | PRB_PROT_NCQ = (1 << 2), | |
192 | PRB_PROT_READ = (1 << 3), | |
193 | PRB_PROT_WRITE = (1 << 4), | |
194 | PRB_PROT_TRANSPARENT = (1 << 5), | |
195 | ||
edb33667 TH |
196 | /* |
197 | * Other constants | |
198 | */ | |
199 | SGE_TRM = (1 << 31), /* Last SGE in chain */ | |
d10cb35a TH |
200 | SGE_LNK = (1 << 30), /* linked list |
201 | Points to SGT, not SGE */ | |
202 | SGE_DRD = (1 << 29), /* discard data read (/dev/null) | |
203 | data address ignored */ | |
edb33667 TH |
204 | |
205 | /* board id */ | |
206 | BID_SIL3124 = 0, | |
207 | BID_SIL3132 = 1, | |
042c21fd | 208 | BID_SIL3131 = 2, |
edb33667 TH |
209 | |
210 | IRQ_STAT_4PORTS = 0xf, | |
211 | }; | |
212 | ||
69ad185f | 213 | struct sil24_ata_block { |
edb33667 TH |
214 | struct sil24_prb prb; |
215 | struct sil24_sge sge[LIBATA_MAX_PRD]; | |
216 | }; | |
217 | ||
69ad185f TH |
218 | struct sil24_atapi_block { |
219 | struct sil24_prb prb; | |
220 | u8 cdb[16]; | |
221 | struct sil24_sge sge[LIBATA_MAX_PRD - 1]; | |
222 | }; | |
223 | ||
224 | union sil24_cmd_block { | |
225 | struct sil24_ata_block ata; | |
226 | struct sil24_atapi_block atapi; | |
227 | }; | |
228 | ||
edb33667 TH |
229 | /* |
230 | * ap->private_data | |
231 | * | |
232 | * The preview driver always returned 0 for status. We emulate it | |
233 | * here from the previous interrupt. | |
234 | */ | |
235 | struct sil24_port_priv { | |
69ad185f | 236 | union sil24_cmd_block *cmd_block; /* 32 cmd blocks */ |
edb33667 | 237 | dma_addr_t cmd_block_dma; /* DMA base addr for them */ |
6a575fa9 | 238 | struct ata_taskfile tf; /* Cached taskfile registers */ |
edb33667 TH |
239 | }; |
240 | ||
241 | /* ap->host_set->private_data */ | |
242 | struct sil24_host_priv { | |
4b4a5eae AV |
243 | void __iomem *host_base; /* global controller control (128 bytes @BAR0) */ |
244 | void __iomem *port_base; /* port registers (4 * 8192 bytes @BAR2) */ | |
edb33667 TH |
245 | }; |
246 | ||
69ad185f | 247 | static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev); |
edb33667 | 248 | static u8 sil24_check_status(struct ata_port *ap); |
edb33667 TH |
249 | static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg); |
250 | static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val); | |
7f726d12 | 251 | static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf); |
07b73470 | 252 | static int sil24_probe_reset(struct ata_port *ap, unsigned int *classes); |
edb33667 | 253 | static void sil24_qc_prep(struct ata_queued_cmd *qc); |
9a3d9eb0 | 254 | static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc); |
edb33667 TH |
255 | static void sil24_irq_clear(struct ata_port *ap); |
256 | static void sil24_eng_timeout(struct ata_port *ap); | |
257 | static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs); | |
258 | static int sil24_port_start(struct ata_port *ap); | |
259 | static void sil24_port_stop(struct ata_port *ap); | |
260 | static void sil24_host_stop(struct ata_host_set *host_set); | |
261 | static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); | |
262 | ||
3b7d697d | 263 | static const struct pci_device_id sil24_pci_tbl[] = { |
edb33667 | 264 | { 0x1095, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 }, |
4b9d7e04 | 265 | { 0x8086, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 }, |
edb33667 | 266 | { 0x1095, 0x3132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3132 }, |
042c21fd TH |
267 | { 0x1095, 0x3131, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 }, |
268 | { 0x1095, 0x3531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 }, | |
1fcce839 | 269 | { } /* terminate list */ |
edb33667 TH |
270 | }; |
271 | ||
272 | static struct pci_driver sil24_pci_driver = { | |
273 | .name = DRV_NAME, | |
274 | .id_table = sil24_pci_tbl, | |
275 | .probe = sil24_init_one, | |
276 | .remove = ata_pci_remove_one, /* safe? */ | |
277 | }; | |
278 | ||
193515d5 | 279 | static struct scsi_host_template sil24_sht = { |
edb33667 TH |
280 | .module = THIS_MODULE, |
281 | .name = DRV_NAME, | |
282 | .ioctl = ata_scsi_ioctl, | |
283 | .queuecommand = ata_scsi_queuecmd, | |
284 | .eh_strategy_handler = ata_scsi_error, | |
285 | .can_queue = ATA_DEF_QUEUE, | |
286 | .this_id = ATA_SHT_THIS_ID, | |
287 | .sg_tablesize = LIBATA_MAX_PRD, | |
edb33667 TH |
288 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
289 | .emulated = ATA_SHT_EMULATED, | |
290 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
291 | .proc_name = DRV_NAME, | |
292 | .dma_boundary = ATA_DMA_BOUNDARY, | |
293 | .slave_configure = ata_scsi_slave_config, | |
294 | .bios_param = ata_std_bios_param, | |
edb33667 TH |
295 | }; |
296 | ||
057ace5e | 297 | static const struct ata_port_operations sil24_ops = { |
edb33667 TH |
298 | .port_disable = ata_port_disable, |
299 | ||
69ad185f TH |
300 | .dev_config = sil24_dev_config, |
301 | ||
edb33667 TH |
302 | .check_status = sil24_check_status, |
303 | .check_altstatus = sil24_check_status, | |
edb33667 TH |
304 | .dev_select = ata_noop_dev_select, |
305 | ||
7f726d12 TH |
306 | .tf_read = sil24_tf_read, |
307 | ||
07b73470 | 308 | .probe_reset = sil24_probe_reset, |
edb33667 TH |
309 | |
310 | .qc_prep = sil24_qc_prep, | |
311 | .qc_issue = sil24_qc_issue, | |
312 | ||
313 | .eng_timeout = sil24_eng_timeout, | |
314 | ||
315 | .irq_handler = sil24_interrupt, | |
316 | .irq_clear = sil24_irq_clear, | |
317 | ||
318 | .scr_read = sil24_scr_read, | |
319 | .scr_write = sil24_scr_write, | |
320 | ||
321 | .port_start = sil24_port_start, | |
322 | .port_stop = sil24_port_stop, | |
323 | .host_stop = sil24_host_stop, | |
324 | }; | |
325 | ||
042c21fd TH |
326 | /* |
327 | * Use bits 30-31 of host_flags to encode available port numbers. | |
328 | * Current maxium is 4. | |
329 | */ | |
330 | #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30) | |
331 | #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1) | |
332 | ||
edb33667 TH |
333 | static struct ata_port_info sil24_port_info[] = { |
334 | /* sil_3124 */ | |
335 | { | |
336 | .sht = &sil24_sht, | |
337 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
07b73470 TH |
338 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | |
339 | SIL24_NPORTS2FLAG(4), | |
edb33667 TH |
340 | .pio_mask = 0x1f, /* pio0-4 */ |
341 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
342 | .udma_mask = 0x3f, /* udma0-5 */ | |
343 | .port_ops = &sil24_ops, | |
344 | }, | |
2e9edbf8 | 345 | /* sil_3132 */ |
edb33667 TH |
346 | { |
347 | .sht = &sil24_sht, | |
348 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
07b73470 TH |
349 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | |
350 | SIL24_NPORTS2FLAG(2), | |
042c21fd TH |
351 | .pio_mask = 0x1f, /* pio0-4 */ |
352 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
353 | .udma_mask = 0x3f, /* udma0-5 */ | |
354 | .port_ops = &sil24_ops, | |
355 | }, | |
356 | /* sil_3131/sil_3531 */ | |
357 | { | |
358 | .sht = &sil24_sht, | |
359 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
07b73470 TH |
360 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | |
361 | SIL24_NPORTS2FLAG(1), | |
edb33667 TH |
362 | .pio_mask = 0x1f, /* pio0-4 */ |
363 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
364 | .udma_mask = 0x3f, /* udma0-5 */ | |
365 | .port_ops = &sil24_ops, | |
366 | }, | |
367 | }; | |
368 | ||
69ad185f TH |
369 | static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev) |
370 | { | |
371 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; | |
372 | ||
6e7846e9 | 373 | if (dev->cdb_len == 16) |
69ad185f TH |
374 | writel(PORT_CS_CDB16, port + PORT_CTRL_STAT); |
375 | else | |
376 | writel(PORT_CS_CDB16, port + PORT_CTRL_CLR); | |
377 | } | |
378 | ||
6a575fa9 TH |
379 | static inline void sil24_update_tf(struct ata_port *ap) |
380 | { | |
381 | struct sil24_port_priv *pp = ap->private_data; | |
4b4a5eae AV |
382 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
383 | struct sil24_prb __iomem *prb = port; | |
384 | u8 fis[6 * 4]; | |
6a575fa9 | 385 | |
4b4a5eae AV |
386 | memcpy_fromio(fis, prb->fis, 6 * 4); |
387 | ata_tf_from_fis(fis, &pp->tf); | |
6a575fa9 TH |
388 | } |
389 | ||
edb33667 TH |
390 | static u8 sil24_check_status(struct ata_port *ap) |
391 | { | |
6a575fa9 TH |
392 | struct sil24_port_priv *pp = ap->private_data; |
393 | return pp->tf.command; | |
edb33667 TH |
394 | } |
395 | ||
edb33667 TH |
396 | static int sil24_scr_map[] = { |
397 | [SCR_CONTROL] = 0, | |
398 | [SCR_STATUS] = 1, | |
399 | [SCR_ERROR] = 2, | |
400 | [SCR_ACTIVE] = 3, | |
401 | }; | |
402 | ||
403 | static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg) | |
404 | { | |
4b4a5eae | 405 | void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr; |
edb33667 | 406 | if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { |
4b4a5eae | 407 | void __iomem *addr; |
edb33667 TH |
408 | addr = scr_addr + sil24_scr_map[sc_reg] * 4; |
409 | return readl(scr_addr + sil24_scr_map[sc_reg] * 4); | |
410 | } | |
411 | return 0xffffffffU; | |
412 | } | |
413 | ||
414 | static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val) | |
415 | { | |
4b4a5eae | 416 | void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr; |
edb33667 | 417 | if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { |
4b4a5eae | 418 | void __iomem *addr; |
edb33667 TH |
419 | addr = scr_addr + sil24_scr_map[sc_reg] * 4; |
420 | writel(val, scr_addr + sil24_scr_map[sc_reg] * 4); | |
421 | } | |
422 | } | |
423 | ||
7f726d12 TH |
424 | static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
425 | { | |
426 | struct sil24_port_priv *pp = ap->private_data; | |
427 | *tf = pp->tf; | |
428 | } | |
429 | ||
07b73470 TH |
430 | static int sil24_softreset(struct ata_port *ap, int verbose, |
431 | unsigned int *class) | |
edb33667 | 432 | { |
ca45160d TH |
433 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
434 | struct sil24_port_priv *pp = ap->private_data; | |
69ad185f | 435 | struct sil24_prb *prb = &pp->cmd_block[0].ata.prb; |
ca45160d | 436 | dma_addr_t paddr = pp->cmd_block_dma; |
8645984c | 437 | unsigned long timeout = jiffies + ATA_TMOUT_BOOT * HZ; |
ca45160d | 438 | u32 irq_enable, irq_stat; |
ca45160d | 439 | |
07b73470 TH |
440 | DPRINTK("ENTER\n"); |
441 | ||
10d996ad TH |
442 | if (!sata_dev_present(ap)) { |
443 | DPRINTK("PHY reports no device\n"); | |
444 | *class = ATA_DEV_NONE; | |
445 | goto out; | |
446 | } | |
447 | ||
ca45160d TH |
448 | /* temporarily turn off IRQs during SRST */ |
449 | irq_enable = readl(port + PORT_IRQ_ENABLE_SET); | |
450 | writel(irq_enable, port + PORT_IRQ_ENABLE_CLR); | |
451 | ||
edb33667 | 452 | /* |
ca45160d TH |
453 | * XXX: Not sure whether the following sleep is needed or not. |
454 | * The original driver had it. So.... | |
edb33667 | 455 | */ |
ca45160d TH |
456 | msleep(10); |
457 | ||
458 | prb->ctrl = PRB_CTRL_SRST; | |
459 | prb->fis[1] = 0; /* no PM yet */ | |
460 | ||
461 | writel((u32)paddr, port + PORT_CMD_ACTIVATE); | |
462 | ||
8645984c | 463 | do { |
ca45160d TH |
464 | irq_stat = readl(port + PORT_IRQ_STAT); |
465 | writel(irq_stat, port + PORT_IRQ_STAT); /* clear irq */ | |
466 | ||
467 | irq_stat >>= PORT_IRQ_RAW_SHIFT; | |
468 | if (irq_stat & (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR)) | |
469 | break; | |
470 | ||
8645984c TH |
471 | msleep(100); |
472 | } while (time_before(jiffies, timeout)); | |
ca45160d TH |
473 | |
474 | /* restore IRQs */ | |
475 | writel(irq_enable, port + PORT_IRQ_ENABLE_SET); | |
476 | ||
10d996ad TH |
477 | if (!(irq_stat & PORT_IRQ_COMPLETE)) { |
478 | DPRINTK("EXIT, srst failed\n"); | |
479 | return -EIO; | |
07b73470 | 480 | } |
10d996ad TH |
481 | |
482 | sil24_update_tf(ap); | |
483 | *class = ata_dev_classify(&pp->tf); | |
484 | ||
07b73470 TH |
485 | if (*class == ATA_DEV_UNKNOWN) |
486 | *class = ATA_DEV_NONE; | |
ca45160d | 487 | |
10d996ad | 488 | out: |
07b73470 | 489 | DPRINTK("EXIT, class=%u\n", *class); |
ca45160d TH |
490 | return 0; |
491 | } | |
492 | ||
489ff4c7 TH |
493 | static int sil24_hardreset(struct ata_port *ap, int verbose, |
494 | unsigned int *class) | |
495 | { | |
496 | unsigned int dummy_class; | |
497 | ||
498 | /* sil24 doesn't report device signature after hard reset */ | |
499 | return sata_std_hardreset(ap, verbose, &dummy_class); | |
500 | } | |
501 | ||
07b73470 | 502 | static int sil24_probe_reset(struct ata_port *ap, unsigned int *classes) |
ca45160d | 503 | { |
07b73470 | 504 | return ata_drive_probe_reset(ap, ata_std_probeinit, |
489ff4c7 | 505 | sil24_softreset, sil24_hardreset, |
07b73470 | 506 | ata_std_postreset, classes); |
edb33667 TH |
507 | } |
508 | ||
509 | static inline void sil24_fill_sg(struct ata_queued_cmd *qc, | |
69ad185f | 510 | struct sil24_sge *sge) |
edb33667 | 511 | { |
972c26bd JG |
512 | struct scatterlist *sg; |
513 | unsigned int idx = 0; | |
edb33667 | 514 | |
972c26bd | 515 | ata_for_each_sg(sg, qc) { |
edb33667 TH |
516 | sge->addr = cpu_to_le64(sg_dma_address(sg)); |
517 | sge->cnt = cpu_to_le32(sg_dma_len(sg)); | |
972c26bd JG |
518 | if (ata_sg_is_last(sg, qc)) |
519 | sge->flags = cpu_to_le32(SGE_TRM); | |
520 | else | |
521 | sge->flags = 0; | |
522 | ||
523 | sge++; | |
524 | idx++; | |
edb33667 TH |
525 | } |
526 | } | |
527 | ||
528 | static void sil24_qc_prep(struct ata_queued_cmd *qc) | |
529 | { | |
530 | struct ata_port *ap = qc->ap; | |
531 | struct sil24_port_priv *pp = ap->private_data; | |
69ad185f TH |
532 | union sil24_cmd_block *cb = pp->cmd_block + qc->tag; |
533 | struct sil24_prb *prb; | |
534 | struct sil24_sge *sge; | |
edb33667 TH |
535 | |
536 | switch (qc->tf.protocol) { | |
537 | case ATA_PROT_PIO: | |
538 | case ATA_PROT_DMA: | |
539 | case ATA_PROT_NODATA: | |
69ad185f TH |
540 | prb = &cb->ata.prb; |
541 | sge = cb->ata.sge; | |
542 | prb->ctrl = 0; | |
edb33667 | 543 | break; |
69ad185f TH |
544 | |
545 | case ATA_PROT_ATAPI: | |
546 | case ATA_PROT_ATAPI_DMA: | |
547 | case ATA_PROT_ATAPI_NODATA: | |
548 | prb = &cb->atapi.prb; | |
549 | sge = cb->atapi.sge; | |
550 | memset(cb->atapi.cdb, 0, 32); | |
6e7846e9 | 551 | memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len); |
69ad185f TH |
552 | |
553 | if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) { | |
554 | if (qc->tf.flags & ATA_TFLAG_WRITE) | |
555 | prb->ctrl = PRB_CTRL_PACKET_WRITE; | |
556 | else | |
557 | prb->ctrl = PRB_CTRL_PACKET_READ; | |
558 | } else | |
559 | prb->ctrl = 0; | |
560 | ||
561 | break; | |
562 | ||
edb33667 | 563 | default: |
69ad185f TH |
564 | prb = NULL; /* shut up, gcc */ |
565 | sge = NULL; | |
edb33667 TH |
566 | BUG(); |
567 | } | |
568 | ||
569 | ata_tf_to_fis(&qc->tf, prb->fis, 0); | |
570 | ||
571 | if (qc->flags & ATA_QCFLAG_DMAMAP) | |
69ad185f | 572 | sil24_fill_sg(qc, sge); |
edb33667 TH |
573 | } |
574 | ||
9a3d9eb0 | 575 | static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc) |
edb33667 TH |
576 | { |
577 | struct ata_port *ap = qc->ap; | |
4b4a5eae | 578 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
edb33667 TH |
579 | struct sil24_port_priv *pp = ap->private_data; |
580 | dma_addr_t paddr = pp->cmd_block_dma + qc->tag * sizeof(*pp->cmd_block); | |
581 | ||
4f50c3cb | 582 | writel((u32)paddr, port + PORT_CMD_ACTIVATE); |
edb33667 TH |
583 | return 0; |
584 | } | |
585 | ||
586 | static void sil24_irq_clear(struct ata_port *ap) | |
587 | { | |
588 | /* unused */ | |
589 | } | |
590 | ||
7d1ce682 TH |
591 | static int __sil24_restart_controller(void __iomem *port) |
592 | { | |
593 | u32 tmp; | |
594 | int cnt; | |
595 | ||
596 | writel(PORT_CS_INIT, port + PORT_CTRL_STAT); | |
597 | ||
598 | /* Max ~10ms */ | |
599 | for (cnt = 0; cnt < 10000; cnt++) { | |
600 | tmp = readl(port + PORT_CTRL_STAT); | |
601 | if (tmp & PORT_CS_RDY) | |
602 | return 0; | |
603 | udelay(1); | |
604 | } | |
605 | ||
606 | return -1; | |
607 | } | |
608 | ||
609 | static void sil24_restart_controller(struct ata_port *ap) | |
610 | { | |
611 | if (__sil24_restart_controller((void __iomem *)ap->ioaddr.cmd_addr)) | |
612 | printk(KERN_ERR DRV_NAME | |
613 | " ata%u: failed to restart controller\n", ap->id); | |
614 | } | |
615 | ||
4b4a5eae | 616 | static int __sil24_reset_controller(void __iomem *port) |
edb33667 | 617 | { |
edb33667 TH |
618 | int cnt; |
619 | u32 tmp; | |
620 | ||
edb33667 TH |
621 | /* Reset controller state. Is this correct? */ |
622 | writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT); | |
623 | readl(port + PORT_CTRL_STAT); /* sync */ | |
624 | ||
625 | /* Max ~100ms */ | |
626 | for (cnt = 0; cnt < 1000; cnt++) { | |
627 | udelay(100); | |
628 | tmp = readl(port + PORT_CTRL_STAT); | |
629 | if (!(tmp & PORT_CS_DEV_RST)) | |
630 | break; | |
631 | } | |
923f1225 | 632 | |
edb33667 | 633 | if (tmp & PORT_CS_DEV_RST) |
923f1225 | 634 | return -1; |
7d1ce682 TH |
635 | |
636 | if (tmp & PORT_CS_RDY) | |
637 | return 0; | |
638 | ||
639 | return __sil24_restart_controller(port); | |
923f1225 TH |
640 | } |
641 | ||
642 | static void sil24_reset_controller(struct ata_port *ap) | |
643 | { | |
644 | printk(KERN_NOTICE DRV_NAME | |
645 | " ata%u: resetting controller...\n", ap->id); | |
4b4a5eae | 646 | if (__sil24_reset_controller((void __iomem *)ap->ioaddr.cmd_addr)) |
923f1225 TH |
647 | printk(KERN_ERR DRV_NAME |
648 | " ata%u: failed to reset controller\n", ap->id); | |
edb33667 TH |
649 | } |
650 | ||
651 | static void sil24_eng_timeout(struct ata_port *ap) | |
652 | { | |
653 | struct ata_queued_cmd *qc; | |
654 | ||
655 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
edb33667 | 656 | |
edb33667 | 657 | printk(KERN_ERR "ata%u: command timeout\n", ap->id); |
11a56d24 | 658 | qc->err_mask |= AC_ERR_TIMEOUT; |
a72ec4ce | 659 | ata_eh_qc_complete(qc); |
edb33667 TH |
660 | |
661 | sil24_reset_controller(ap); | |
662 | } | |
663 | ||
8746618d TH |
664 | static void sil24_error_intr(struct ata_port *ap, u32 slot_stat) |
665 | { | |
666 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag); | |
6a575fa9 | 667 | struct sil24_port_priv *pp = ap->private_data; |
4b4a5eae | 668 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
8746618d | 669 | u32 irq_stat, cmd_err, sstatus, serror; |
a7dac447 | 670 | unsigned int err_mask; |
8746618d TH |
671 | |
672 | irq_stat = readl(port + PORT_IRQ_STAT); | |
ad6e90f6 TH |
673 | writel(irq_stat, port + PORT_IRQ_STAT); /* clear irq */ |
674 | ||
675 | if (!(irq_stat & PORT_IRQ_ERROR)) { | |
676 | /* ignore non-completion, non-error irqs for now */ | |
677 | printk(KERN_WARNING DRV_NAME | |
678 | "ata%u: non-error exception irq (irq_stat %x)\n", | |
679 | ap->id, irq_stat); | |
680 | return; | |
681 | } | |
682 | ||
8746618d TH |
683 | cmd_err = readl(port + PORT_CMD_ERR); |
684 | sstatus = readl(port + PORT_SSTATUS); | |
685 | serror = readl(port + PORT_SERROR); | |
8746618d TH |
686 | if (serror) |
687 | writel(serror, port + PORT_SERROR); | |
688 | ||
c0ab4242 TH |
689 | /* |
690 | * Don't log ATAPI device errors. They're supposed to happen | |
691 | * and any serious errors will be logged using sense data by | |
692 | * the SCSI layer. | |
693 | */ | |
694 | if (ap->device[0].class != ATA_DEV_ATAPI || cmd_err > PORT_CERR_SDB) | |
695 | printk("ata%u: error interrupt on port%d\n" | |
696 | " stat=0x%x irq=0x%x cmd_err=%d sstatus=0x%x serror=0x%x\n", | |
697 | ap->id, ap->port_no, slot_stat, irq_stat, cmd_err, sstatus, serror); | |
8746618d | 698 | |
6a575fa9 TH |
699 | if (cmd_err == PORT_CERR_DEV || cmd_err == PORT_CERR_SDB) { |
700 | /* | |
701 | * Device is reporting error, tf registers are valid. | |
702 | */ | |
703 | sil24_update_tf(ap); | |
a7dac447 | 704 | err_mask = ac_err_mask(pp->tf.command); |
7d1ce682 | 705 | sil24_restart_controller(ap); |
6a575fa9 TH |
706 | } else { |
707 | /* | |
708 | * Other errors. libata currently doesn't have any | |
709 | * mechanism to report these errors. Just turn on | |
710 | * ATA_ERR. | |
711 | */ | |
a7dac447 | 712 | err_mask = AC_ERR_OTHER; |
7d1ce682 | 713 | sil24_reset_controller(ap); |
6a575fa9 TH |
714 | } |
715 | ||
a22e2eb0 AL |
716 | if (qc) { |
717 | qc->err_mask |= err_mask; | |
718 | ata_qc_complete(qc); | |
719 | } | |
8746618d TH |
720 | } |
721 | ||
edb33667 TH |
722 | static inline void sil24_host_intr(struct ata_port *ap) |
723 | { | |
724 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag); | |
4b4a5eae | 725 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
edb33667 TH |
726 | u32 slot_stat; |
727 | ||
728 | slot_stat = readl(port + PORT_SLOT_STAT); | |
729 | if (!(slot_stat & HOST_SSTAT_ATTN)) { | |
6a575fa9 TH |
730 | struct sil24_port_priv *pp = ap->private_data; |
731 | /* | |
732 | * !HOST_SSAT_ATTN guarantees successful completion, | |
733 | * so reading back tf registers is unnecessary for | |
734 | * most commands. TODO: read tf registers for | |
735 | * commands which require these values on successful | |
736 | * completion (EXECUTE DEVICE DIAGNOSTIC, CHECK POWER, | |
737 | * DEVICE RESET and READ PORT MULTIPLIER (any more?). | |
738 | */ | |
739 | sil24_update_tf(ap); | |
740 | ||
a22e2eb0 AL |
741 | if (qc) { |
742 | qc->err_mask |= ac_err_mask(pp->tf.command); | |
743 | ata_qc_complete(qc); | |
744 | } | |
8746618d TH |
745 | } else |
746 | sil24_error_intr(ap, slot_stat); | |
edb33667 TH |
747 | } |
748 | ||
749 | static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs) | |
750 | { | |
751 | struct ata_host_set *host_set = dev_instance; | |
752 | struct sil24_host_priv *hpriv = host_set->private_data; | |
753 | unsigned handled = 0; | |
754 | u32 status; | |
755 | int i; | |
756 | ||
757 | status = readl(hpriv->host_base + HOST_IRQ_STAT); | |
758 | ||
06460aea TH |
759 | if (status == 0xffffffff) { |
760 | printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, " | |
761 | "PCI fault or device removal?\n"); | |
762 | goto out; | |
763 | } | |
764 | ||
edb33667 TH |
765 | if (!(status & IRQ_STAT_4PORTS)) |
766 | goto out; | |
767 | ||
768 | spin_lock(&host_set->lock); | |
769 | ||
770 | for (i = 0; i < host_set->n_ports; i++) | |
771 | if (status & (1 << i)) { | |
772 | struct ata_port *ap = host_set->ports[i]; | |
198e0fed | 773 | if (ap && !(ap->flags & ATA_FLAG_DISABLED)) { |
edb33667 | 774 | sil24_host_intr(host_set->ports[i]); |
3cc4571c TH |
775 | handled++; |
776 | } else | |
777 | printk(KERN_ERR DRV_NAME | |
778 | ": interrupt from disabled port %d\n", i); | |
edb33667 TH |
779 | } |
780 | ||
781 | spin_unlock(&host_set->lock); | |
782 | out: | |
783 | return IRQ_RETVAL(handled); | |
784 | } | |
785 | ||
6037d6bb JG |
786 | static inline void sil24_cblk_free(struct sil24_port_priv *pp, struct device *dev) |
787 | { | |
788 | const size_t cb_size = sizeof(*pp->cmd_block); | |
789 | ||
790 | dma_free_coherent(dev, cb_size, pp->cmd_block, pp->cmd_block_dma); | |
791 | } | |
792 | ||
edb33667 TH |
793 | static int sil24_port_start(struct ata_port *ap) |
794 | { | |
795 | struct device *dev = ap->host_set->dev; | |
edb33667 | 796 | struct sil24_port_priv *pp; |
69ad185f | 797 | union sil24_cmd_block *cb; |
edb33667 TH |
798 | size_t cb_size = sizeof(*cb); |
799 | dma_addr_t cb_dma; | |
6037d6bb | 800 | int rc = -ENOMEM; |
edb33667 | 801 | |
6037d6bb | 802 | pp = kzalloc(sizeof(*pp), GFP_KERNEL); |
edb33667 | 803 | if (!pp) |
6037d6bb | 804 | goto err_out; |
edb33667 | 805 | |
6a575fa9 TH |
806 | pp->tf.command = ATA_DRDY; |
807 | ||
edb33667 | 808 | cb = dma_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL); |
6037d6bb JG |
809 | if (!cb) |
810 | goto err_out_pp; | |
edb33667 TH |
811 | memset(cb, 0, cb_size); |
812 | ||
6037d6bb JG |
813 | rc = ata_pad_alloc(ap, dev); |
814 | if (rc) | |
815 | goto err_out_pad; | |
816 | ||
edb33667 TH |
817 | pp->cmd_block = cb; |
818 | pp->cmd_block_dma = cb_dma; | |
819 | ||
820 | ap->private_data = pp; | |
821 | ||
822 | return 0; | |
6037d6bb JG |
823 | |
824 | err_out_pad: | |
825 | sil24_cblk_free(pp, dev); | |
826 | err_out_pp: | |
827 | kfree(pp); | |
828 | err_out: | |
829 | return rc; | |
edb33667 TH |
830 | } |
831 | ||
832 | static void sil24_port_stop(struct ata_port *ap) | |
833 | { | |
834 | struct device *dev = ap->host_set->dev; | |
835 | struct sil24_port_priv *pp = ap->private_data; | |
edb33667 | 836 | |
6037d6bb | 837 | sil24_cblk_free(pp, dev); |
e9c05afa | 838 | ata_pad_free(ap, dev); |
edb33667 TH |
839 | kfree(pp); |
840 | } | |
841 | ||
842 | static void sil24_host_stop(struct ata_host_set *host_set) | |
843 | { | |
844 | struct sil24_host_priv *hpriv = host_set->private_data; | |
142877b0 | 845 | struct pci_dev *pdev = to_pci_dev(host_set->dev); |
edb33667 | 846 | |
142877b0 JG |
847 | pci_iounmap(pdev, hpriv->host_base); |
848 | pci_iounmap(pdev, hpriv->port_base); | |
edb33667 TH |
849 | kfree(hpriv); |
850 | } | |
851 | ||
852 | static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |
853 | { | |
854 | static int printed_version = 0; | |
855 | unsigned int board_id = (unsigned int)ent->driver_data; | |
042c21fd | 856 | struct ata_port_info *pinfo = &sil24_port_info[board_id]; |
edb33667 TH |
857 | struct ata_probe_ent *probe_ent = NULL; |
858 | struct sil24_host_priv *hpriv = NULL; | |
4b4a5eae AV |
859 | void __iomem *host_base = NULL; |
860 | void __iomem *port_base = NULL; | |
edb33667 TH |
861 | int i, rc; |
862 | ||
863 | if (!printed_version++) | |
a9524a76 | 864 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
edb33667 TH |
865 | |
866 | rc = pci_enable_device(pdev); | |
867 | if (rc) | |
868 | return rc; | |
869 | ||
870 | rc = pci_request_regions(pdev, DRV_NAME); | |
871 | if (rc) | |
872 | goto out_disable; | |
873 | ||
874 | rc = -ENOMEM; | |
142877b0 JG |
875 | /* map mmio registers */ |
876 | host_base = pci_iomap(pdev, 0, 0); | |
edb33667 TH |
877 | if (!host_base) |
878 | goto out_free; | |
142877b0 | 879 | port_base = pci_iomap(pdev, 2, 0); |
edb33667 TH |
880 | if (!port_base) |
881 | goto out_free; | |
882 | ||
883 | /* allocate & init probe_ent and hpriv */ | |
142877b0 | 884 | probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL); |
edb33667 TH |
885 | if (!probe_ent) |
886 | goto out_free; | |
887 | ||
142877b0 | 888 | hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL); |
edb33667 TH |
889 | if (!hpriv) |
890 | goto out_free; | |
891 | ||
edb33667 TH |
892 | probe_ent->dev = pci_dev_to_dev(pdev); |
893 | INIT_LIST_HEAD(&probe_ent->node); | |
894 | ||
042c21fd TH |
895 | probe_ent->sht = pinfo->sht; |
896 | probe_ent->host_flags = pinfo->host_flags; | |
897 | probe_ent->pio_mask = pinfo->pio_mask; | |
fbfda6e7 | 898 | probe_ent->mwdma_mask = pinfo->mwdma_mask; |
042c21fd TH |
899 | probe_ent->udma_mask = pinfo->udma_mask; |
900 | probe_ent->port_ops = pinfo->port_ops; | |
901 | probe_ent->n_ports = SIL24_FLAG2NPORTS(pinfo->host_flags); | |
edb33667 TH |
902 | |
903 | probe_ent->irq = pdev->irq; | |
904 | probe_ent->irq_flags = SA_SHIRQ; | |
905 | probe_ent->mmio_base = port_base; | |
906 | probe_ent->private_data = hpriv; | |
907 | ||
edb33667 TH |
908 | hpriv->host_base = host_base; |
909 | hpriv->port_base = port_base; | |
910 | ||
911 | /* | |
912 | * Configure the device | |
913 | */ | |
914 | /* | |
915 | * FIXME: This device is certainly 64-bit capable. We just | |
916 | * don't know how to use it. After fixing 32bit activation in | |
917 | * this function, enable 64bit masks here. | |
918 | */ | |
919 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
920 | if (rc) { | |
a9524a76 JG |
921 | dev_printk(KERN_ERR, &pdev->dev, |
922 | "32-bit DMA enable failed\n"); | |
edb33667 TH |
923 | goto out_free; |
924 | } | |
925 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
926 | if (rc) { | |
a9524a76 JG |
927 | dev_printk(KERN_ERR, &pdev->dev, |
928 | "32-bit consistent DMA enable failed\n"); | |
edb33667 TH |
929 | goto out_free; |
930 | } | |
931 | ||
932 | /* GPIO off */ | |
933 | writel(0, host_base + HOST_FLASH_CMD); | |
934 | ||
935 | /* Mask interrupts during initialization */ | |
936 | writel(0, host_base + HOST_CTRL); | |
937 | ||
938 | for (i = 0; i < probe_ent->n_ports; i++) { | |
4b4a5eae | 939 | void __iomem *port = port_base + i * PORT_REGS_SIZE; |
edb33667 TH |
940 | unsigned long portu = (unsigned long)port; |
941 | u32 tmp; | |
942 | int cnt; | |
943 | ||
4f50c3cb | 944 | probe_ent->port[i].cmd_addr = portu + PORT_PRB; |
edb33667 TH |
945 | probe_ent->port[i].scr_addr = portu + PORT_SCONTROL; |
946 | ||
947 | ata_std_ports(&probe_ent->port[i]); | |
948 | ||
949 | /* Initial PHY setting */ | |
950 | writel(0x20c, port + PORT_PHY_CFG); | |
951 | ||
952 | /* Clear port RST */ | |
953 | tmp = readl(port + PORT_CTRL_STAT); | |
954 | if (tmp & PORT_CS_PORT_RST) { | |
955 | writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR); | |
956 | readl(port + PORT_CTRL_STAT); /* sync */ | |
957 | for (cnt = 0; cnt < 10; cnt++) { | |
958 | msleep(10); | |
959 | tmp = readl(port + PORT_CTRL_STAT); | |
960 | if (!(tmp & PORT_CS_PORT_RST)) | |
961 | break; | |
962 | } | |
963 | if (tmp & PORT_CS_PORT_RST) | |
a9524a76 JG |
964 | dev_printk(KERN_ERR, &pdev->dev, |
965 | "failed to clear port RST\n"); | |
edb33667 TH |
966 | } |
967 | ||
968 | /* Zero error counters. */ | |
969 | writel(0x8000, port + PORT_DECODE_ERR_THRESH); | |
970 | writel(0x8000, port + PORT_CRC_ERR_THRESH); | |
971 | writel(0x8000, port + PORT_HSHK_ERR_THRESH); | |
972 | writel(0x0000, port + PORT_DECODE_ERR_CNT); | |
973 | writel(0x0000, port + PORT_CRC_ERR_CNT); | |
974 | writel(0x0000, port + PORT_HSHK_ERR_CNT); | |
975 | ||
976 | /* FIXME: 32bit activation? */ | |
977 | writel(0, port + PORT_ACTIVATE_UPPER_ADDR); | |
978 | writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_STAT); | |
979 | ||
980 | /* Configure interrupts */ | |
981 | writel(0xffff, port + PORT_IRQ_ENABLE_CLR); | |
982 | writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | PORT_IRQ_SDB_FIS, | |
983 | port + PORT_IRQ_ENABLE_SET); | |
984 | ||
985 | /* Clear interrupts */ | |
986 | writel(0x0fff0fff, port + PORT_IRQ_STAT); | |
987 | writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR); | |
923f1225 TH |
988 | |
989 | /* Clear port multiplier enable and resume bits */ | |
990 | writel(PORT_CS_PM_EN | PORT_CS_RESUME, port + PORT_CTRL_CLR); | |
991 | ||
992 | /* Reset itself */ | |
993 | if (__sil24_reset_controller(port)) | |
a9524a76 JG |
994 | dev_printk(KERN_ERR, &pdev->dev, |
995 | "failed to reset controller\n"); | |
edb33667 TH |
996 | } |
997 | ||
998 | /* Turn on interrupts */ | |
999 | writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL); | |
1000 | ||
1001 | pci_set_master(pdev); | |
1002 | ||
1483467f | 1003 | /* FIXME: check ata_device_add return value */ |
edb33667 TH |
1004 | ata_device_add(probe_ent); |
1005 | ||
1006 | kfree(probe_ent); | |
1007 | return 0; | |
1008 | ||
1009 | out_free: | |
1010 | if (host_base) | |
142877b0 | 1011 | pci_iounmap(pdev, host_base); |
edb33667 | 1012 | if (port_base) |
142877b0 | 1013 | pci_iounmap(pdev, port_base); |
edb33667 TH |
1014 | kfree(probe_ent); |
1015 | kfree(hpriv); | |
1016 | pci_release_regions(pdev); | |
1017 | out_disable: | |
1018 | pci_disable_device(pdev); | |
1019 | return rc; | |
1020 | } | |
1021 | ||
1022 | static int __init sil24_init(void) | |
1023 | { | |
1024 | return pci_module_init(&sil24_pci_driver); | |
1025 | } | |
1026 | ||
1027 | static void __exit sil24_exit(void) | |
1028 | { | |
1029 | pci_unregister_driver(&sil24_pci_driver); | |
1030 | } | |
1031 | ||
1032 | MODULE_AUTHOR("Tejun Heo"); | |
1033 | MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver"); | |
1034 | MODULE_LICENSE("GPL"); | |
1035 | MODULE_DEVICE_TABLE(pci, sil24_pci_tbl); | |
1036 | ||
1037 | module_init(sil24_init); | |
1038 | module_exit(sil24_exit); |