projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[PATCH] sil24: add sil24_restart_controller
[deliverable/linux.git] / drivers / scsi / sata_sil24.c
CommitLineData
edb33667
TH		 1/*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
8 * NOTE: No NCQ/ATAPI support yet. The preview driver didn't support
9 * NCQ nor ATAPI, and, unfortunately, I couldn't find out how to make
10 * those work. Enabling those shouldn't be difficult. Basic
11 * structure is all there (in libata-dev tree). If you have any
12 * information about this hardware, please contact me or linux-ide.
13 * Info is needed on...
14 *
15 * - How to issue tagged commands and turn on sactive on issue accordingly.
16 * - Where to put an ATAPI command and how to tell the device to send it.
17 * - How to enable/use 64bit.
18 *
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the
21 * Free Software Foundation; either version 2, or (at your option) any
22 * later version.
23 *
24 * This program is distributed in the hope that it will be useful, but
25 * WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
27 * General Public License for more details.
28 *
29 */
30
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/pci.h>
34#include <linux/blkdev.h>
35#include <linux/delay.h>
36#include <linux/interrupt.h>
37#include <linux/dma-mapping.h>
a9524a76 38#include <linux/device.h>
edb33667 39#include <scsi/scsi_host.h>
193515d5 40#include <scsi/scsi_cmnd.h>
edb33667
TH		 41#include <linux/libata.h>
42#include <asm/io.h>
43
44#define DRV_NAME "sata_sil24"
6a575fa9 45#define DRV_VERSION "0.22" /* Silicon Image's preview driver was 0.10 */
edb33667 46
edb33667
TH		 47/*
48 * Port request block (PRB) 32 bytes
49 */
50struct sil24_prb {
51 u16 ctrl;
52 u16 prot;
53 u32 rx_cnt;
54 u8 fis[6 * 4];
55};
56
57/*
58 * Scatter gather entry (SGE) 16 bytes
59 */
60struct sil24_sge {
61 u64 addr;
62 u32 cnt;
63 u32 flags;
64};
65
66/*
67 * Port multiplier
68 */
69struct sil24_port_multiplier {
70 u32 diag;
71 u32 sactive;
72};
73
74enum {
75 /*
76 * Global controller registers (128 bytes @ BAR0)
77 */
78 /* 32 bit regs */
79 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
80 HOST_CTRL = 0x40,
81 HOST_IRQ_STAT = 0x44,
82 HOST_PHY_CFG = 0x48,
83 HOST_BIST_CTRL = 0x50,
84 HOST_BIST_PTRN = 0x54,
85 HOST_BIST_STAT = 0x58,
86 HOST_MEM_BIST_STAT = 0x5c,
87 HOST_FLASH_CMD = 0x70,
88 /* 8 bit regs */
89 HOST_FLASH_DATA = 0x74,
90 HOST_TRANSITION_DETECT = 0x75,
91 HOST_GPIO_CTRL = 0x76,
92 HOST_I2C_ADDR = 0x78, /* 32 bit */
93 HOST_I2C_DATA = 0x7c,
94 HOST_I2C_XFER_CNT = 0x7e,
95 HOST_I2C_CTRL = 0x7f,
96
97 /* HOST_SLOT_STAT bits */
98 HOST_SSTAT_ATTN = (1 << 31),
99
100 /*
101 * Port registers
102 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
103 */
104 PORT_REGS_SIZE = 0x2000,
105 PORT_PRB = 0x0000, /* (32 bytes PRB + 16 bytes SGEs * 6) * 31 (3968 bytes) */
edb33667
TH		 106
107 PORT_PM = 0x0f80, /* 8 bytes PM * 16 (128 bytes) */
108 /* 32 bit regs */
83bbecc9
TH		 109 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
110 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
111 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
112 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
113 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
edb33667 114 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
83bbecc9
TH		 115 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
116 PORT_CMD_ERR = 0x1024, /* command error number */
edb33667
TH		 117 PORT_FIS_CFG = 0x1028,
118 PORT_FIFO_THRES = 0x102c,
119 /* 16 bit regs */
120 PORT_DECODE_ERR_CNT = 0x1040,
121 PORT_DECODE_ERR_THRESH = 0x1042,
122 PORT_CRC_ERR_CNT = 0x1044,
123 PORT_CRC_ERR_THRESH = 0x1046,
124 PORT_HSHK_ERR_CNT = 0x1048,
125 PORT_HSHK_ERR_THRESH = 0x104a,
126 /* 32 bit regs */
127 PORT_PHY_CFG = 0x1050,
128 PORT_SLOT_STAT = 0x1800,
129 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
130 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
131 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
132 PORT_SCONTROL = 0x1f00,
133 PORT_SSTATUS = 0x1f04,
134 PORT_SERROR = 0x1f08,
135 PORT_SACTIVE = 0x1f0c,
136
137 /* PORT_CTRL_STAT bits */
138 PORT_CS_PORT_RST = (1 << 0), /* port reset */
139 PORT_CS_DEV_RST = (1 << 1), /* device reset */
140 PORT_CS_INIT = (1 << 2), /* port initialize */
141 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
d10cb35a 142 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
e382eb1d
TH		 143 PORT_CS_RESUME = (1 << 6), /* port resume */
144 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
145 PORT_CS_PM_EN = (1 << 13), /* port multiplier enable */
146 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
edb33667
TH		 147
148 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
149 /* bits[11:0] are masked */
150 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
151 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
152 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
153 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
154 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
155 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
156 PORT_IRQ_UNK_FIS = (1 << 6), /* Unknown FIS received */
157 PORT_IRQ_SDB_FIS = (1 << 11), /* SDB FIS received */
158
159 /* bits[27:16] are unmasked (raw) */
160 PORT_IRQ_RAW_SHIFT = 16,
161 PORT_IRQ_MASKED_MASK = 0x7ff,
162 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
163
164 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
165 PORT_IRQ_STEER_SHIFT = 30,
166 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
167
168 /* PORT_CMD_ERR constants */
169 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
170 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
171 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
172 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
173 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
174 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
175 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
176 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
177 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
178 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
179 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
180 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
181 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
182 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
183 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
184 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
185 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
186 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
187 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
188 PORT_CERR_XFR_MSGABRT = 34, /* PSD ecode 10 - master abort */
189 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
83bbecc9 190 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
edb33667 191
d10cb35a
TH		 192 /* bits of PRB control field */
193 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
194 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
195 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
196 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
197 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
198
199 /* PRB protocol field */
200 PRB_PROT_PACKET = (1 << 0),
201 PRB_PROT_TCQ = (1 << 1),
202 PRB_PROT_NCQ = (1 << 2),
203 PRB_PROT_READ = (1 << 3),
204 PRB_PROT_WRITE = (1 << 4),
205 PRB_PROT_TRANSPARENT = (1 << 5),
206
edb33667
TH		 207 /*
208 * Other constants
209 */
210 SGE_TRM = (1 << 31), /* Last SGE in chain */
d10cb35a
TH		 211 SGE_LNK = (1 << 30), /* linked list
212 Points to SGT, not SGE */
213 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
214 data address ignored */
edb33667
TH		 215
216 /* board id */
217 BID_SIL3124 = 0,
218 BID_SIL3132 = 1,
042c21fd 219 BID_SIL3131 = 2,
edb33667
TH		 220
221 IRQ_STAT_4PORTS = 0xf,
222};
223
224struct sil24_cmd_block {
225 struct sil24_prb prb;
226 struct sil24_sge sge[LIBATA_MAX_PRD];
227};
228
229/*
230 * ap->private_data
231 *
232 * The preview driver always returned 0 for status. We emulate it
233 * here from the previous interrupt.
234 */
235struct sil24_port_priv {
edb33667
TH		 236 struct sil24_cmd_block *cmd_block; /* 32 cmd blocks */
237 dma_addr_t cmd_block_dma; /* DMA base addr for them */
6a575fa9 238 struct ata_taskfile tf; /* Cached taskfile registers */
edb33667
TH		 239};
240
241/* ap->host_set->private_data */
242struct sil24_host_priv {
4b4a5eae
AV		 243 void __iomem *host_base; /* global controller control (128 bytes @BAR0) */
244 void __iomem *port_base; /* port registers (4 * 8192 bytes @BAR2) */
edb33667
TH		 245};
246
247static u8 sil24_check_status(struct ata_port *ap);
edb33667
TH		 248static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg);
249static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
7f726d12 250static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
edb33667
TH		 251static void sil24_phy_reset(struct ata_port *ap);
252static void sil24_qc_prep(struct ata_queued_cmd *qc);
253static int sil24_qc_issue(struct ata_queued_cmd *qc);
254static void sil24_irq_clear(struct ata_port *ap);
255static void sil24_eng_timeout(struct ata_port *ap);
256static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
257static int sil24_port_start(struct ata_port *ap);
258static void sil24_port_stop(struct ata_port *ap);
259static void sil24_host_stop(struct ata_host_set *host_set);
260static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
261
3b7d697d 262static const struct pci_device_id sil24_pci_tbl[] = {
edb33667
TH		 263 { 0x1095, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 },
264 { 0x1095, 0x3132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3132 },
042c21fd
TH		 265 { 0x1095, 0x3131, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
266 { 0x1095, 0x3531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
1fcce839 267 { } /* terminate list */
edb33667
TH		 268};
269
270static struct pci_driver sil24_pci_driver = {
271 .name = DRV_NAME,
272 .id_table = sil24_pci_tbl,
273 .probe = sil24_init_one,
274 .remove = ata_pci_remove_one, /* safe? */
275};
276
193515d5 277static struct scsi_host_template sil24_sht = {
edb33667
TH		 278 .module = THIS_MODULE,
279 .name = DRV_NAME,
280 .ioctl = ata_scsi_ioctl,
281 .queuecommand = ata_scsi_queuecmd,
282 .eh_strategy_handler = ata_scsi_error,
283 .can_queue = ATA_DEF_QUEUE,
284 .this_id = ATA_SHT_THIS_ID,
285 .sg_tablesize = LIBATA_MAX_PRD,
286 .max_sectors = ATA_MAX_SECTORS,
287 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
288 .emulated = ATA_SHT_EMULATED,
289 .use_clustering = ATA_SHT_USE_CLUSTERING,
290 .proc_name = DRV_NAME,
291 .dma_boundary = ATA_DMA_BOUNDARY,
292 .slave_configure = ata_scsi_slave_config,
293 .bios_param = ata_std_bios_param,
294 .ordered_flush = 1, /* NCQ not supported yet */
295};
296
057ace5e 297static const struct ata_port_operations sil24_ops = {
edb33667
TH		 298 .port_disable = ata_port_disable,
299
300 .check_status = sil24_check_status,
301 .check_altstatus = sil24_check_status,
edb33667
TH		 302 .dev_select = ata_noop_dev_select,
303
7f726d12
TH		 304 .tf_read = sil24_tf_read,
305
edb33667
TH		 306 .phy_reset = sil24_phy_reset,
307
308 .qc_prep = sil24_qc_prep,
309 .qc_issue = sil24_qc_issue,
310
311 .eng_timeout = sil24_eng_timeout,
312
313 .irq_handler = sil24_interrupt,
314 .irq_clear = sil24_irq_clear,
315
316 .scr_read = sil24_scr_read,
317 .scr_write = sil24_scr_write,
318
319 .port_start = sil24_port_start,
320 .port_stop = sil24_port_stop,
321 .host_stop = sil24_host_stop,
322};
323
042c21fd
TH		 324/*
325 * Use bits 30-31 of host_flags to encode available port numbers.
326 * Current maxium is 4.
327 */
328#define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
329#define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
330
edb33667
TH		 331static struct ata_port_info sil24_port_info[] = {
332 /* sil_3124 */
333 {
334 .sht = &sil24_sht,
335 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
336 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
042c21fd 337 ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(4),
edb33667
TH		 338 .pio_mask = 0x1f, /* pio0-4 */
339 .mwdma_mask = 0x07, /* mwdma0-2 */
340 .udma_mask = 0x3f, /* udma0-5 */
341 .port_ops = &sil24_ops,
342 },
343 /* sil_3132 */
344 {
345 .sht = &sil24_sht,
346 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
347 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
042c21fd
TH		 348 ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(2),
349 .pio_mask = 0x1f, /* pio0-4 */
350 .mwdma_mask = 0x07, /* mwdma0-2 */
351 .udma_mask = 0x3f, /* udma0-5 */
352 .port_ops = &sil24_ops,
353 },
354 /* sil_3131/sil_3531 */
355 {
356 .sht = &sil24_sht,
357 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
358 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
359 ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(1),
edb33667
TH		 360 .pio_mask = 0x1f, /* pio0-4 */
361 .mwdma_mask = 0x07, /* mwdma0-2 */
362 .udma_mask = 0x3f, /* udma0-5 */
363 .port_ops = &sil24_ops,
364 },
365};
366
6a575fa9
TH		 367static inline void sil24_update_tf(struct ata_port *ap)
368{
369 struct sil24_port_priv *pp = ap->private_data;
4b4a5eae
AV		 370 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
371 struct sil24_prb __iomem *prb = port;
372 u8 fis[6 * 4];
6a575fa9 373
4b4a5eae
AV		 374 memcpy_fromio(fis, prb->fis, 6 * 4);
375 ata_tf_from_fis(fis, &pp->tf);
6a575fa9
TH		 376}
377
edb33667
TH		 378static u8 sil24_check_status(struct ata_port *ap)
379{
6a575fa9
TH		 380 struct sil24_port_priv *pp = ap->private_data;
381 return pp->tf.command;
edb33667
TH		 382}
383
edb33667
TH		 384static int sil24_scr_map[] = {
385 [SCR_CONTROL] = 0,
386 [SCR_STATUS] = 1,
387 [SCR_ERROR] = 2,
388 [SCR_ACTIVE] = 3,
389};
390
391static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg)
392{
4b4a5eae 393 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
edb33667 394 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
4b4a5eae 395 void __iomem *addr;
edb33667
TH		 396 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
397 return readl(scr_addr + sil24_scr_map[sc_reg] * 4);
398 }
399 return 0xffffffffU;
400}
401
402static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
403{
4b4a5eae 404 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
edb33667 405 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
4b4a5eae 406 void __iomem *addr;
edb33667
TH		 407 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
408 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
409 }
410}
411
7f726d12
TH		 412static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
413{
414 struct sil24_port_priv *pp = ap->private_data;
415 *tf = pp->tf;
416}
417
edb33667
TH		 418static void sil24_phy_reset(struct ata_port *ap)
419{
420 __sata_phy_reset(ap);
421 /*
422 * No ATAPI yet. Just unconditionally indicate ATA device.
423 * If ATAPI device is attached, it will fail ATA_CMD_ID_ATA
424 * and libata core will ignore the device.
425 */
426 if (!(ap->flags & ATA_FLAG_PORT_DISABLED))
427 ap->device[0].class = ATA_DEV_ATA;
428}
429
430static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
431 struct sil24_cmd_block *cb)
432{
edb33667 433 struct sil24_sge *sge = cb->sge;
972c26bd
JG		 434 struct scatterlist *sg;
435 unsigned int idx = 0;
edb33667 436
972c26bd 437 ata_for_each_sg(sg, qc) {
edb33667
TH		 438 sge->addr = cpu_to_le64(sg_dma_address(sg));
439 sge->cnt = cpu_to_le32(sg_dma_len(sg));
972c26bd
JG		 440 if (ata_sg_is_last(sg, qc))
441 sge->flags = cpu_to_le32(SGE_TRM);
442 else
443 sge->flags = 0;
444
445 sge++;
446 idx++;
edb33667
TH		 447 }
448}
449
450static void sil24_qc_prep(struct ata_queued_cmd *qc)
451{
452 struct ata_port *ap = qc->ap;
453 struct sil24_port_priv *pp = ap->private_data;
454 struct sil24_cmd_block *cb = pp->cmd_block + qc->tag;
455 struct sil24_prb *prb = &cb->prb;
456
457 switch (qc->tf.protocol) {
458 case ATA_PROT_PIO:
459 case ATA_PROT_DMA:
460 case ATA_PROT_NODATA:
461 break;
462 default:
463 /* ATAPI isn't supported yet */
464 BUG();
465 }
466
467 ata_tf_to_fis(&qc->tf, prb->fis, 0);
468
469 if (qc->flags & ATA_QCFLAG_DMAMAP)
470 sil24_fill_sg(qc, cb);
471}
472
473static int sil24_qc_issue(struct ata_queued_cmd *qc)
474{
475 struct ata_port *ap = qc->ap;
4b4a5eae 476 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
edb33667
TH		 477 struct sil24_port_priv *pp = ap->private_data;
478 dma_addr_t paddr = pp->cmd_block_dma + qc->tag * sizeof(*pp->cmd_block);
479
4f50c3cb 480 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
edb33667
TH		 481 return 0;
482}
483
484static void sil24_irq_clear(struct ata_port *ap)
485{
486 /* unused */
487}
488
7d1ce682
TH		 489static int __sil24_restart_controller(void __iomem *port)
490{
491 u32 tmp;
492 int cnt;
493
494 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
495
496 /* Max ~10ms */
497 for (cnt = 0; cnt < 10000; cnt++) {
498 tmp = readl(port + PORT_CTRL_STAT);
499 if (tmp & PORT_CS_RDY)
500 return 0;
501 udelay(1);
502 }
503
504 return -1;
505}
506
507static void sil24_restart_controller(struct ata_port *ap)
508{
509 if (__sil24_restart_controller((void __iomem *)ap->ioaddr.cmd_addr))
510 printk(KERN_ERR DRV_NAME
511 " ata%u: failed to restart controller\n", ap->id);
512}
513
4b4a5eae 514static int __sil24_reset_controller(void __iomem *port)
edb33667 515{
edb33667
TH		 516 int cnt;
517 u32 tmp;
518
edb33667
TH		 519 /* Reset controller state. Is this correct? */
520 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
521 readl(port + PORT_CTRL_STAT); /* sync */
522
523 /* Max ~100ms */
524 for (cnt = 0; cnt < 1000; cnt++) {
525 udelay(100);
526 tmp = readl(port + PORT_CTRL_STAT);
527 if (!(tmp & PORT_CS_DEV_RST))
528 break;
529 }
923f1225 530
edb33667 531 if (tmp & PORT_CS_DEV_RST)
923f1225 532 return -1;
7d1ce682
TH		 533
534 if (tmp & PORT_CS_RDY)
535 return 0;
536
537 return __sil24_restart_controller(port);
923f1225
TH		 538}
539
540static void sil24_reset_controller(struct ata_port *ap)
541{
542 printk(KERN_NOTICE DRV_NAME
543 " ata%u: resetting controller...\n", ap->id);
4b4a5eae 544 if (__sil24_reset_controller((void __iomem *)ap->ioaddr.cmd_addr))
923f1225
TH		 545 printk(KERN_ERR DRV_NAME
546 " ata%u: failed to reset controller\n", ap->id);
edb33667
TH		 547}
548
549static void sil24_eng_timeout(struct ata_port *ap)
550{
551 struct ata_queued_cmd *qc;
552
553 qc = ata_qc_from_tag(ap, ap->active_tag);
554 if (!qc) {
a7dac447 555 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
edb33667
TH		 556 ap->id);
557 return;
558 }
559
560 /*
561 * hack alert! We cannot use the supplied completion
562 * function from inside the ->eh_strategy_handler() thread.
563 * libata is the only user of ->eh_strategy_handler() in
564 * any kernel, so the default scsi_done() assumes it is
565 * not being called from the SCSI EH.
566 */
567 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
568 qc->scsidone = scsi_finish_command;
a7dac447 569 ata_qc_complete(qc, AC_ERR_OTHER);
edb33667
TH		 570
571 sil24_reset_controller(ap);
572}
573
8746618d
TH		 574static void sil24_error_intr(struct ata_port *ap, u32 slot_stat)
575{
576 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
6a575fa9 577 struct sil24_port_priv *pp = ap->private_data;
4b4a5eae 578 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
8746618d 579 u32 irq_stat, cmd_err, sstatus, serror;
a7dac447 580 unsigned int err_mask;
8746618d
TH		 581
582 irq_stat = readl(port + PORT_IRQ_STAT);
ad6e90f6
TH		 583 writel(irq_stat, port + PORT_IRQ_STAT); /* clear irq */
584
585 if (!(irq_stat & PORT_IRQ_ERROR)) {
586 /* ignore non-completion, non-error irqs for now */
587 printk(KERN_WARNING DRV_NAME
588 "ata%u: non-error exception irq (irq_stat %x)\n",
589 ap->id, irq_stat);
590 return;
591 }
592
8746618d
TH		 593 cmd_err = readl(port + PORT_CMD_ERR);
594 sstatus = readl(port + PORT_SSTATUS);
595 serror = readl(port + PORT_SERROR);
8746618d
TH		 596 if (serror)
597 writel(serror, port + PORT_SERROR);
598
599 printk(KERN_ERR DRV_NAME " ata%u: error interrupt on port%d\n"
600 " stat=0x%x irq=0x%x cmd_err=%d sstatus=0x%x serror=0x%x\n",
601 ap->id, ap->port_no, slot_stat, irq_stat, cmd_err, sstatus, serror);
602
6a575fa9
TH		 603 if (cmd_err == PORT_CERR_DEV || cmd_err == PORT_CERR_SDB) {
604 /*
605 * Device is reporting error, tf registers are valid.
606 */
607 sil24_update_tf(ap);
a7dac447 608 err_mask = ac_err_mask(pp->tf.command);
7d1ce682 609 sil24_restart_controller(ap);
6a575fa9
TH		 610 } else {
611 /*
612 * Other errors. libata currently doesn't have any
613 * mechanism to report these errors. Just turn on
614 * ATA_ERR.
615 */
a7dac447 616 err_mask = AC_ERR_OTHER;
7d1ce682 617 sil24_reset_controller(ap);
6a575fa9
TH		 618 }
619
8746618d 620 if (qc)
a7dac447 621 ata_qc_complete(qc, err_mask);
8746618d
TH		 622}
623
edb33667
TH		 624static inline void sil24_host_intr(struct ata_port *ap)
625{
626 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
4b4a5eae 627 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
edb33667
TH		 628 u32 slot_stat;
629
630 slot_stat = readl(port + PORT_SLOT_STAT);
631 if (!(slot_stat & HOST_SSTAT_ATTN)) {
6a575fa9
TH		 632 struct sil24_port_priv *pp = ap->private_data;
633 /*
634 * !HOST_SSAT_ATTN guarantees successful completion,
635 * so reading back tf registers is unnecessary for
636 * most commands. TODO: read tf registers for
637 * commands which require these values on successful
638 * completion (EXECUTE DEVICE DIAGNOSTIC, CHECK POWER,
639 * DEVICE RESET and READ PORT MULTIPLIER (any more?).
640 */
641 sil24_update_tf(ap);
642
edb33667 643 if (qc)
a7dac447 644 ata_qc_complete(qc, ac_err_mask(pp->tf.command));
8746618d
TH		 645 } else
646 sil24_error_intr(ap, slot_stat);
edb33667
TH		 647}
648
649static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
650{
651 struct ata_host_set *host_set = dev_instance;
652 struct sil24_host_priv *hpriv = host_set->private_data;
653 unsigned handled = 0;
654 u32 status;
655 int i;
656
657 status = readl(hpriv->host_base + HOST_IRQ_STAT);
658
06460aea
TH		 659 if (status == 0xffffffff) {
660 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
661 "PCI fault or device removal?\n");
662 goto out;
663 }
664
edb33667
TH		 665 if (!(status & IRQ_STAT_4PORTS))
666 goto out;
667
668 spin_lock(&host_set->lock);
669
670 for (i = 0; i < host_set->n_ports; i++)
671 if (status & (1 << i)) {
672 struct ata_port *ap = host_set->ports[i];
3cc4571c 673 if (ap && !(ap->flags & ATA_FLAG_PORT_DISABLED)) {
edb33667 674 sil24_host_intr(host_set->ports[i]);
3cc4571c
TH		 675 handled++;
676 } else
677 printk(KERN_ERR DRV_NAME
678 ": interrupt from disabled port %d\n", i);
edb33667
TH		 679 }
680
681 spin_unlock(&host_set->lock);
682 out:
683 return IRQ_RETVAL(handled);
684}
685
6037d6bb
JG		 686static inline void sil24_cblk_free(struct sil24_port_priv *pp, struct device *dev)
687{
688 const size_t cb_size = sizeof(*pp->cmd_block);
689
690 dma_free_coherent(dev, cb_size, pp->cmd_block, pp->cmd_block_dma);
691}
692
edb33667
TH		 693static int sil24_port_start(struct ata_port *ap)
694{
695 struct device *dev = ap->host_set->dev;
edb33667
TH		 696 struct sil24_port_priv *pp;
697 struct sil24_cmd_block *cb;
698 size_t cb_size = sizeof(*cb);
699 dma_addr_t cb_dma;
6037d6bb 700 int rc = -ENOMEM;
edb33667 701
6037d6bb 702 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
edb33667 703 if (!pp)
6037d6bb 704 goto err_out;
edb33667 705
6a575fa9
TH		 706 pp->tf.command = ATA_DRDY;
707
edb33667 708 cb = dma_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
6037d6bb
JG		 709 if (!cb)
710 goto err_out_pp;
edb33667
TH		 711 memset(cb, 0, cb_size);
712
6037d6bb
JG		 713 rc = ata_pad_alloc(ap, dev);
714 if (rc)
715 goto err_out_pad;
716
edb33667
TH		 717 pp->cmd_block = cb;
718 pp->cmd_block_dma = cb_dma;
719
720 ap->private_data = pp;
721
722 return 0;
6037d6bb
JG		 723
724err_out_pad:
725 sil24_cblk_free(pp, dev);
726err_out_pp:
727 kfree(pp);
728err_out:
729 return rc;
edb33667
TH		 730}
731
732static void sil24_port_stop(struct ata_port *ap)
733{
734 struct device *dev = ap->host_set->dev;
735 struct sil24_port_priv *pp = ap->private_data;
edb33667 736
6037d6bb 737 sil24_cblk_free(pp, dev);
e9c05afa 738 ata_pad_free(ap, dev);
edb33667
TH		 739 kfree(pp);
740}
741
742static void sil24_host_stop(struct ata_host_set *host_set)
743{
744 struct sil24_host_priv *hpriv = host_set->private_data;
745
746 iounmap(hpriv->host_base);
747 iounmap(hpriv->port_base);
748 kfree(hpriv);
749}
750
751static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
752{
753 static int printed_version = 0;
754 unsigned int board_id = (unsigned int)ent->driver_data;
042c21fd 755 struct ata_port_info *pinfo = &sil24_port_info[board_id];
edb33667
TH		 756 struct ata_probe_ent *probe_ent = NULL;
757 struct sil24_host_priv *hpriv = NULL;
4b4a5eae
AV		 758 void __iomem *host_base = NULL;
759 void __iomem *port_base = NULL;
edb33667
TH		 760 int i, rc;
761
762 if (!printed_version++)
a9524a76 763 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
edb33667
TH		 764
765 rc = pci_enable_device(pdev);
766 if (rc)
767 return rc;
768
769 rc = pci_request_regions(pdev, DRV_NAME);
770 if (rc)
771 goto out_disable;
772
773 rc = -ENOMEM;
774 /* ioremap mmio registers */
775 host_base = ioremap(pci_resource_start(pdev, 0),
776 pci_resource_len(pdev, 0));
777 if (!host_base)
778 goto out_free;
779 port_base = ioremap(pci_resource_start(pdev, 2),
780 pci_resource_len(pdev, 2));
781 if (!port_base)
782 goto out_free;
783
784 /* allocate & init probe_ent and hpriv */
785 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
786 if (!probe_ent)
787 goto out_free;
788
789 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
790 if (!hpriv)
791 goto out_free;
792
793 memset(probe_ent, 0, sizeof(*probe_ent));
794 probe_ent->dev = pci_dev_to_dev(pdev);
795 INIT_LIST_HEAD(&probe_ent->node);
796
042c21fd
TH		 797 probe_ent->sht = pinfo->sht;
798 probe_ent->host_flags = pinfo->host_flags;
799 probe_ent->pio_mask = pinfo->pio_mask;
800 probe_ent->udma_mask = pinfo->udma_mask;
801 probe_ent->port_ops = pinfo->port_ops;
802 probe_ent->n_ports = SIL24_FLAG2NPORTS(pinfo->host_flags);
edb33667
TH		 803
804 probe_ent->irq = pdev->irq;
805 probe_ent->irq_flags = SA_SHIRQ;
806 probe_ent->mmio_base = port_base;
807 probe_ent->private_data = hpriv;
808
809 memset(hpriv, 0, sizeof(*hpriv));
810 hpriv->host_base = host_base;
811 hpriv->port_base = port_base;
812
813 /*
814 * Configure the device
815 */
816 /*
817 * FIXME: This device is certainly 64-bit capable. We just
818 * don't know how to use it. After fixing 32bit activation in
819 * this function, enable 64bit masks here.
820 */
821 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
822 if (rc) {
a9524a76
JG		 823 dev_printk(KERN_ERR, &pdev->dev,
824 "32-bit DMA enable failed\n");
edb33667
TH		 825 goto out_free;
826 }
827 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
828 if (rc) {
a9524a76
JG		 829 dev_printk(KERN_ERR, &pdev->dev,
830 "32-bit consistent DMA enable failed\n");
edb33667
TH		 831 goto out_free;
832 }
833
834 /* GPIO off */
835 writel(0, host_base + HOST_FLASH_CMD);
836
837 /* Mask interrupts during initialization */
838 writel(0, host_base + HOST_CTRL);
839
840 for (i = 0; i < probe_ent->n_ports; i++) {
4b4a5eae 841 void __iomem *port = port_base + i * PORT_REGS_SIZE;
edb33667
TH		 842 unsigned long portu = (unsigned long)port;
843 u32 tmp;
844 int cnt;
845
4f50c3cb 846 probe_ent->port[i].cmd_addr = portu + PORT_PRB;
edb33667
TH		 847 probe_ent->port[i].scr_addr = portu + PORT_SCONTROL;
848
849 ata_std_ports(&probe_ent->port[i]);
850
851 /* Initial PHY setting */
852 writel(0x20c, port + PORT_PHY_CFG);
853
854 /* Clear port RST */
855 tmp = readl(port + PORT_CTRL_STAT);
856 if (tmp & PORT_CS_PORT_RST) {
857 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
858 readl(port + PORT_CTRL_STAT); /* sync */
859 for (cnt = 0; cnt < 10; cnt++) {
860 msleep(10);
861 tmp = readl(port + PORT_CTRL_STAT);
862 if (!(tmp & PORT_CS_PORT_RST))
863 break;
864 }
865 if (tmp & PORT_CS_PORT_RST)
a9524a76
JG		 866 dev_printk(KERN_ERR, &pdev->dev,
867 "failed to clear port RST\n");
edb33667
TH		 868 }
869
870 /* Zero error counters. */
871 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
872 writel(0x8000, port + PORT_CRC_ERR_THRESH);
873 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
874 writel(0x0000, port + PORT_DECODE_ERR_CNT);
875 writel(0x0000, port + PORT_CRC_ERR_CNT);
876 writel(0x0000, port + PORT_HSHK_ERR_CNT);
877
878 /* FIXME: 32bit activation? */
879 writel(0, port + PORT_ACTIVATE_UPPER_ADDR);
880 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_STAT);
881
882 /* Configure interrupts */
883 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
884 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | PORT_IRQ_SDB_FIS,
885 port + PORT_IRQ_ENABLE_SET);
886
887 /* Clear interrupts */
888 writel(0x0fff0fff, port + PORT_IRQ_STAT);
889 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
923f1225
TH		 890
891 /* Clear port multiplier enable and resume bits */
892 writel(PORT_CS_PM_EN | PORT_CS_RESUME, port + PORT_CTRL_CLR);
893
894 /* Reset itself */
895 if (__sil24_reset_controller(port))
a9524a76
JG		 896 dev_printk(KERN_ERR, &pdev->dev,
897 "failed to reset controller\n");
edb33667
TH		 898 }
899
900 /* Turn on interrupts */
901 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
902
903 pci_set_master(pdev);
904
1483467f 905 /* FIXME: check ata_device_add return value */
edb33667
TH		 906 ata_device_add(probe_ent);
907
908 kfree(probe_ent);
909 return 0;
910
911 out_free:
912 if (host_base)
913 iounmap(host_base);
914 if (port_base)
915 iounmap(port_base);
916 kfree(probe_ent);
917 kfree(hpriv);
918 pci_release_regions(pdev);
919 out_disable:
920 pci_disable_device(pdev);
921 return rc;
922}
923
924static int __init sil24_init(void)
925{
926 return pci_module_init(&sil24_pci_driver);
927}
928
929static void __exit sil24_exit(void)
930{
931 pci_unregister_driver(&sil24_pci_driver);
932}
933
934MODULE_AUTHOR("Tejun Heo");
935MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
936MODULE_LICENSE("GPL");
937MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
938
939module_init(sil24_init);
940module_exit(sil24_exit);
Linux kernel - Deliverables
This page took 0.082518 seconds and 5 git commands to generate.