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edb33667 TH |
1 | /* |
2 | * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers | |
3 | * | |
4 | * Copyright 2005 Tejun Heo | |
5 | * | |
6 | * Based on preview driver from Silicon Image. | |
7 | * | |
8 | * NOTE: No NCQ/ATAPI support yet. The preview driver didn't support | |
9 | * NCQ nor ATAPI, and, unfortunately, I couldn't find out how to make | |
10 | * those work. Enabling those shouldn't be difficult. Basic | |
11 | * structure is all there (in libata-dev tree). If you have any | |
12 | * information about this hardware, please contact me or linux-ide. | |
13 | * Info is needed on... | |
14 | * | |
15 | * - How to issue tagged commands and turn on sactive on issue accordingly. | |
16 | * - Where to put an ATAPI command and how to tell the device to send it. | |
17 | * - How to enable/use 64bit. | |
18 | * | |
19 | * This program is free software; you can redistribute it and/or modify it | |
20 | * under the terms of the GNU General Public License as published by the | |
21 | * Free Software Foundation; either version 2, or (at your option) any | |
22 | * later version. | |
23 | * | |
24 | * This program is distributed in the hope that it will be useful, but | |
25 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
26 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
27 | * General Public License for more details. | |
28 | * | |
29 | */ | |
30 | ||
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/pci.h> | |
34 | #include <linux/blkdev.h> | |
35 | #include <linux/delay.h> | |
36 | #include <linux/interrupt.h> | |
37 | #include <linux/dma-mapping.h> | |
a9524a76 | 38 | #include <linux/device.h> |
edb33667 TH |
39 | #include <scsi/scsi_host.h> |
40 | #include "scsi.h" | |
41 | #include <linux/libata.h> | |
42 | #include <asm/io.h> | |
43 | ||
44 | #define DRV_NAME "sata_sil24" | |
6a575fa9 | 45 | #define DRV_VERSION "0.22" /* Silicon Image's preview driver was 0.10 */ |
edb33667 | 46 | |
edb33667 TH |
47 | /* |
48 | * Port request block (PRB) 32 bytes | |
49 | */ | |
50 | struct sil24_prb { | |
51 | u16 ctrl; | |
52 | u16 prot; | |
53 | u32 rx_cnt; | |
54 | u8 fis[6 * 4]; | |
55 | }; | |
56 | ||
57 | /* | |
58 | * Scatter gather entry (SGE) 16 bytes | |
59 | */ | |
60 | struct sil24_sge { | |
61 | u64 addr; | |
62 | u32 cnt; | |
63 | u32 flags; | |
64 | }; | |
65 | ||
66 | /* | |
67 | * Port multiplier | |
68 | */ | |
69 | struct sil24_port_multiplier { | |
70 | u32 diag; | |
71 | u32 sactive; | |
72 | }; | |
73 | ||
74 | enum { | |
75 | /* | |
76 | * Global controller registers (128 bytes @ BAR0) | |
77 | */ | |
78 | /* 32 bit regs */ | |
79 | HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */ | |
80 | HOST_CTRL = 0x40, | |
81 | HOST_IRQ_STAT = 0x44, | |
82 | HOST_PHY_CFG = 0x48, | |
83 | HOST_BIST_CTRL = 0x50, | |
84 | HOST_BIST_PTRN = 0x54, | |
85 | HOST_BIST_STAT = 0x58, | |
86 | HOST_MEM_BIST_STAT = 0x5c, | |
87 | HOST_FLASH_CMD = 0x70, | |
88 | /* 8 bit regs */ | |
89 | HOST_FLASH_DATA = 0x74, | |
90 | HOST_TRANSITION_DETECT = 0x75, | |
91 | HOST_GPIO_CTRL = 0x76, | |
92 | HOST_I2C_ADDR = 0x78, /* 32 bit */ | |
93 | HOST_I2C_DATA = 0x7c, | |
94 | HOST_I2C_XFER_CNT = 0x7e, | |
95 | HOST_I2C_CTRL = 0x7f, | |
96 | ||
97 | /* HOST_SLOT_STAT bits */ | |
98 | HOST_SSTAT_ATTN = (1 << 31), | |
99 | ||
100 | /* | |
101 | * Port registers | |
102 | * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2) | |
103 | */ | |
104 | PORT_REGS_SIZE = 0x2000, | |
105 | PORT_PRB = 0x0000, /* (32 bytes PRB + 16 bytes SGEs * 6) * 31 (3968 bytes) */ | |
edb33667 TH |
106 | |
107 | PORT_PM = 0x0f80, /* 8 bytes PM * 16 (128 bytes) */ | |
108 | /* 32 bit regs */ | |
83bbecc9 TH |
109 | PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */ |
110 | PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */ | |
111 | PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */ | |
112 | PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */ | |
113 | PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */ | |
edb33667 | 114 | PORT_ACTIVATE_UPPER_ADDR= 0x101c, |
83bbecc9 TH |
115 | PORT_EXEC_FIFO = 0x1020, /* command execution fifo */ |
116 | PORT_CMD_ERR = 0x1024, /* command error number */ | |
edb33667 TH |
117 | PORT_FIS_CFG = 0x1028, |
118 | PORT_FIFO_THRES = 0x102c, | |
119 | /* 16 bit regs */ | |
120 | PORT_DECODE_ERR_CNT = 0x1040, | |
121 | PORT_DECODE_ERR_THRESH = 0x1042, | |
122 | PORT_CRC_ERR_CNT = 0x1044, | |
123 | PORT_CRC_ERR_THRESH = 0x1046, | |
124 | PORT_HSHK_ERR_CNT = 0x1048, | |
125 | PORT_HSHK_ERR_THRESH = 0x104a, | |
126 | /* 32 bit regs */ | |
127 | PORT_PHY_CFG = 0x1050, | |
128 | PORT_SLOT_STAT = 0x1800, | |
129 | PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */ | |
130 | PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */ | |
131 | PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */ | |
132 | PORT_SCONTROL = 0x1f00, | |
133 | PORT_SSTATUS = 0x1f04, | |
134 | PORT_SERROR = 0x1f08, | |
135 | PORT_SACTIVE = 0x1f0c, | |
136 | ||
137 | /* PORT_CTRL_STAT bits */ | |
138 | PORT_CS_PORT_RST = (1 << 0), /* port reset */ | |
139 | PORT_CS_DEV_RST = (1 << 1), /* device reset */ | |
140 | PORT_CS_INIT = (1 << 2), /* port initialize */ | |
141 | PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */ | |
e382eb1d TH |
142 | PORT_CS_RESUME = (1 << 6), /* port resume */ |
143 | PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */ | |
144 | PORT_CS_PM_EN = (1 << 13), /* port multiplier enable */ | |
145 | PORT_CS_RDY = (1 << 31), /* port ready to accept commands */ | |
edb33667 TH |
146 | |
147 | /* PORT_IRQ_STAT/ENABLE_SET/CLR */ | |
148 | /* bits[11:0] are masked */ | |
149 | PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */ | |
150 | PORT_IRQ_ERROR = (1 << 1), /* command execution error */ | |
151 | PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */ | |
152 | PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */ | |
153 | PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */ | |
154 | PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */ | |
155 | PORT_IRQ_UNK_FIS = (1 << 6), /* Unknown FIS received */ | |
156 | PORT_IRQ_SDB_FIS = (1 << 11), /* SDB FIS received */ | |
157 | ||
158 | /* bits[27:16] are unmasked (raw) */ | |
159 | PORT_IRQ_RAW_SHIFT = 16, | |
160 | PORT_IRQ_MASKED_MASK = 0x7ff, | |
161 | PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT), | |
162 | ||
163 | /* ENABLE_SET/CLR specific, intr steering - 2 bit field */ | |
164 | PORT_IRQ_STEER_SHIFT = 30, | |
165 | PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT), | |
166 | ||
167 | /* PORT_CMD_ERR constants */ | |
168 | PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */ | |
169 | PORT_CERR_SDB = 2, /* Error bit in SDB FIS */ | |
170 | PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */ | |
171 | PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */ | |
172 | PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */ | |
173 | PORT_CERR_DIRECTION = 6, /* Data direction mismatch */ | |
174 | PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */ | |
175 | PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */ | |
176 | PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */ | |
177 | PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */ | |
178 | PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */ | |
179 | PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */ | |
180 | PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */ | |
181 | PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */ | |
182 | PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */ | |
183 | PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */ | |
184 | PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */ | |
185 | PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */ | |
186 | PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */ | |
187 | PORT_CERR_XFR_MSGABRT = 34, /* PSD ecode 10 - master abort */ | |
188 | PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */ | |
83bbecc9 | 189 | PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */ |
edb33667 TH |
190 | |
191 | /* | |
192 | * Other constants | |
193 | */ | |
194 | SGE_TRM = (1 << 31), /* Last SGE in chain */ | |
195 | PRB_SOFT_RST = (1 << 7), /* Soft reset request (ign BSY?) */ | |
196 | ||
197 | /* board id */ | |
198 | BID_SIL3124 = 0, | |
199 | BID_SIL3132 = 1, | |
042c21fd | 200 | BID_SIL3131 = 2, |
edb33667 TH |
201 | |
202 | IRQ_STAT_4PORTS = 0xf, | |
203 | }; | |
204 | ||
205 | struct sil24_cmd_block { | |
206 | struct sil24_prb prb; | |
207 | struct sil24_sge sge[LIBATA_MAX_PRD]; | |
208 | }; | |
209 | ||
210 | /* | |
211 | * ap->private_data | |
212 | * | |
213 | * The preview driver always returned 0 for status. We emulate it | |
214 | * here from the previous interrupt. | |
215 | */ | |
216 | struct sil24_port_priv { | |
edb33667 TH |
217 | struct sil24_cmd_block *cmd_block; /* 32 cmd blocks */ |
218 | dma_addr_t cmd_block_dma; /* DMA base addr for them */ | |
6a575fa9 | 219 | struct ata_taskfile tf; /* Cached taskfile registers */ |
edb33667 TH |
220 | }; |
221 | ||
222 | /* ap->host_set->private_data */ | |
223 | struct sil24_host_priv { | |
4b4a5eae AV |
224 | void __iomem *host_base; /* global controller control (128 bytes @BAR0) */ |
225 | void __iomem *port_base; /* port registers (4 * 8192 bytes @BAR2) */ | |
edb33667 TH |
226 | }; |
227 | ||
228 | static u8 sil24_check_status(struct ata_port *ap); | |
edb33667 TH |
229 | static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg); |
230 | static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val); | |
7f726d12 | 231 | static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf); |
edb33667 TH |
232 | static void sil24_phy_reset(struct ata_port *ap); |
233 | static void sil24_qc_prep(struct ata_queued_cmd *qc); | |
234 | static int sil24_qc_issue(struct ata_queued_cmd *qc); | |
235 | static void sil24_irq_clear(struct ata_port *ap); | |
236 | static void sil24_eng_timeout(struct ata_port *ap); | |
237 | static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs); | |
238 | static int sil24_port_start(struct ata_port *ap); | |
239 | static void sil24_port_stop(struct ata_port *ap); | |
240 | static void sil24_host_stop(struct ata_host_set *host_set); | |
241 | static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); | |
242 | ||
243 | static struct pci_device_id sil24_pci_tbl[] = { | |
244 | { 0x1095, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 }, | |
245 | { 0x1095, 0x3132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3132 }, | |
042c21fd TH |
246 | { 0x1095, 0x3131, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 }, |
247 | { 0x1095, 0x3531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 }, | |
1fcce839 | 248 | { } /* terminate list */ |
edb33667 TH |
249 | }; |
250 | ||
251 | static struct pci_driver sil24_pci_driver = { | |
252 | .name = DRV_NAME, | |
253 | .id_table = sil24_pci_tbl, | |
254 | .probe = sil24_init_one, | |
255 | .remove = ata_pci_remove_one, /* safe? */ | |
256 | }; | |
257 | ||
258 | static Scsi_Host_Template sil24_sht = { | |
259 | .module = THIS_MODULE, | |
260 | .name = DRV_NAME, | |
261 | .ioctl = ata_scsi_ioctl, | |
262 | .queuecommand = ata_scsi_queuecmd, | |
263 | .eh_strategy_handler = ata_scsi_error, | |
264 | .can_queue = ATA_DEF_QUEUE, | |
265 | .this_id = ATA_SHT_THIS_ID, | |
266 | .sg_tablesize = LIBATA_MAX_PRD, | |
267 | .max_sectors = ATA_MAX_SECTORS, | |
268 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, | |
269 | .emulated = ATA_SHT_EMULATED, | |
270 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
271 | .proc_name = DRV_NAME, | |
272 | .dma_boundary = ATA_DMA_BOUNDARY, | |
273 | .slave_configure = ata_scsi_slave_config, | |
274 | .bios_param = ata_std_bios_param, | |
275 | .ordered_flush = 1, /* NCQ not supported yet */ | |
276 | }; | |
277 | ||
057ace5e | 278 | static const struct ata_port_operations sil24_ops = { |
edb33667 TH |
279 | .port_disable = ata_port_disable, |
280 | ||
281 | .check_status = sil24_check_status, | |
282 | .check_altstatus = sil24_check_status, | |
edb33667 TH |
283 | .dev_select = ata_noop_dev_select, |
284 | ||
7f726d12 TH |
285 | .tf_read = sil24_tf_read, |
286 | ||
edb33667 TH |
287 | .phy_reset = sil24_phy_reset, |
288 | ||
289 | .qc_prep = sil24_qc_prep, | |
290 | .qc_issue = sil24_qc_issue, | |
291 | ||
292 | .eng_timeout = sil24_eng_timeout, | |
293 | ||
294 | .irq_handler = sil24_interrupt, | |
295 | .irq_clear = sil24_irq_clear, | |
296 | ||
297 | .scr_read = sil24_scr_read, | |
298 | .scr_write = sil24_scr_write, | |
299 | ||
300 | .port_start = sil24_port_start, | |
301 | .port_stop = sil24_port_stop, | |
302 | .host_stop = sil24_host_stop, | |
303 | }; | |
304 | ||
042c21fd TH |
305 | /* |
306 | * Use bits 30-31 of host_flags to encode available port numbers. | |
307 | * Current maxium is 4. | |
308 | */ | |
309 | #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30) | |
310 | #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1) | |
311 | ||
edb33667 TH |
312 | static struct ata_port_info sil24_port_info[] = { |
313 | /* sil_3124 */ | |
314 | { | |
315 | .sht = &sil24_sht, | |
316 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
317 | ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO | | |
042c21fd | 318 | ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(4), |
edb33667 TH |
319 | .pio_mask = 0x1f, /* pio0-4 */ |
320 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
321 | .udma_mask = 0x3f, /* udma0-5 */ | |
322 | .port_ops = &sil24_ops, | |
323 | }, | |
324 | /* sil_3132 */ | |
325 | { | |
326 | .sht = &sil24_sht, | |
327 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
328 | ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO | | |
042c21fd TH |
329 | ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(2), |
330 | .pio_mask = 0x1f, /* pio0-4 */ | |
331 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
332 | .udma_mask = 0x3f, /* udma0-5 */ | |
333 | .port_ops = &sil24_ops, | |
334 | }, | |
335 | /* sil_3131/sil_3531 */ | |
336 | { | |
337 | .sht = &sil24_sht, | |
338 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
339 | ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO | | |
340 | ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(1), | |
edb33667 TH |
341 | .pio_mask = 0x1f, /* pio0-4 */ |
342 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
343 | .udma_mask = 0x3f, /* udma0-5 */ | |
344 | .port_ops = &sil24_ops, | |
345 | }, | |
346 | }; | |
347 | ||
6a575fa9 TH |
348 | static inline void sil24_update_tf(struct ata_port *ap) |
349 | { | |
350 | struct sil24_port_priv *pp = ap->private_data; | |
4b4a5eae AV |
351 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
352 | struct sil24_prb __iomem *prb = port; | |
353 | u8 fis[6 * 4]; | |
6a575fa9 | 354 | |
4b4a5eae AV |
355 | memcpy_fromio(fis, prb->fis, 6 * 4); |
356 | ata_tf_from_fis(fis, &pp->tf); | |
6a575fa9 TH |
357 | } |
358 | ||
edb33667 TH |
359 | static u8 sil24_check_status(struct ata_port *ap) |
360 | { | |
6a575fa9 TH |
361 | struct sil24_port_priv *pp = ap->private_data; |
362 | return pp->tf.command; | |
edb33667 TH |
363 | } |
364 | ||
edb33667 TH |
365 | static int sil24_scr_map[] = { |
366 | [SCR_CONTROL] = 0, | |
367 | [SCR_STATUS] = 1, | |
368 | [SCR_ERROR] = 2, | |
369 | [SCR_ACTIVE] = 3, | |
370 | }; | |
371 | ||
372 | static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg) | |
373 | { | |
4b4a5eae | 374 | void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr; |
edb33667 | 375 | if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { |
4b4a5eae | 376 | void __iomem *addr; |
edb33667 TH |
377 | addr = scr_addr + sil24_scr_map[sc_reg] * 4; |
378 | return readl(scr_addr + sil24_scr_map[sc_reg] * 4); | |
379 | } | |
380 | return 0xffffffffU; | |
381 | } | |
382 | ||
383 | static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val) | |
384 | { | |
4b4a5eae | 385 | void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr; |
edb33667 | 386 | if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { |
4b4a5eae | 387 | void __iomem *addr; |
edb33667 TH |
388 | addr = scr_addr + sil24_scr_map[sc_reg] * 4; |
389 | writel(val, scr_addr + sil24_scr_map[sc_reg] * 4); | |
390 | } | |
391 | } | |
392 | ||
7f726d12 TH |
393 | static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
394 | { | |
395 | struct sil24_port_priv *pp = ap->private_data; | |
396 | *tf = pp->tf; | |
397 | } | |
398 | ||
edb33667 TH |
399 | static void sil24_phy_reset(struct ata_port *ap) |
400 | { | |
401 | __sata_phy_reset(ap); | |
402 | /* | |
403 | * No ATAPI yet. Just unconditionally indicate ATA device. | |
404 | * If ATAPI device is attached, it will fail ATA_CMD_ID_ATA | |
405 | * and libata core will ignore the device. | |
406 | */ | |
407 | if (!(ap->flags & ATA_FLAG_PORT_DISABLED)) | |
408 | ap->device[0].class = ATA_DEV_ATA; | |
409 | } | |
410 | ||
411 | static inline void sil24_fill_sg(struct ata_queued_cmd *qc, | |
412 | struct sil24_cmd_block *cb) | |
413 | { | |
414 | struct scatterlist *sg = qc->sg; | |
415 | struct sil24_sge *sge = cb->sge; | |
416 | unsigned i; | |
417 | ||
418 | for (i = 0; i < qc->n_elem; i++, sg++, sge++) { | |
419 | sge->addr = cpu_to_le64(sg_dma_address(sg)); | |
420 | sge->cnt = cpu_to_le32(sg_dma_len(sg)); | |
421 | sge->flags = 0; | |
422 | sge->flags = i < qc->n_elem - 1 ? 0 : cpu_to_le32(SGE_TRM); | |
423 | } | |
424 | } | |
425 | ||
426 | static void sil24_qc_prep(struct ata_queued_cmd *qc) | |
427 | { | |
428 | struct ata_port *ap = qc->ap; | |
429 | struct sil24_port_priv *pp = ap->private_data; | |
430 | struct sil24_cmd_block *cb = pp->cmd_block + qc->tag; | |
431 | struct sil24_prb *prb = &cb->prb; | |
432 | ||
433 | switch (qc->tf.protocol) { | |
434 | case ATA_PROT_PIO: | |
435 | case ATA_PROT_DMA: | |
436 | case ATA_PROT_NODATA: | |
437 | break; | |
438 | default: | |
439 | /* ATAPI isn't supported yet */ | |
440 | BUG(); | |
441 | } | |
442 | ||
443 | ata_tf_to_fis(&qc->tf, prb->fis, 0); | |
444 | ||
445 | if (qc->flags & ATA_QCFLAG_DMAMAP) | |
446 | sil24_fill_sg(qc, cb); | |
447 | } | |
448 | ||
449 | static int sil24_qc_issue(struct ata_queued_cmd *qc) | |
450 | { | |
451 | struct ata_port *ap = qc->ap; | |
4b4a5eae | 452 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
edb33667 TH |
453 | struct sil24_port_priv *pp = ap->private_data; |
454 | dma_addr_t paddr = pp->cmd_block_dma + qc->tag * sizeof(*pp->cmd_block); | |
455 | ||
4f50c3cb | 456 | writel((u32)paddr, port + PORT_CMD_ACTIVATE); |
edb33667 TH |
457 | return 0; |
458 | } | |
459 | ||
460 | static void sil24_irq_clear(struct ata_port *ap) | |
461 | { | |
462 | /* unused */ | |
463 | } | |
464 | ||
4b4a5eae | 465 | static int __sil24_reset_controller(void __iomem *port) |
edb33667 | 466 | { |
edb33667 TH |
467 | int cnt; |
468 | u32 tmp; | |
469 | ||
edb33667 TH |
470 | /* Reset controller state. Is this correct? */ |
471 | writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT); | |
472 | readl(port + PORT_CTRL_STAT); /* sync */ | |
473 | ||
474 | /* Max ~100ms */ | |
475 | for (cnt = 0; cnt < 1000; cnt++) { | |
476 | udelay(100); | |
477 | tmp = readl(port + PORT_CTRL_STAT); | |
478 | if (!(tmp & PORT_CS_DEV_RST)) | |
479 | break; | |
480 | } | |
923f1225 | 481 | |
edb33667 | 482 | if (tmp & PORT_CS_DEV_RST) |
923f1225 TH |
483 | return -1; |
484 | return 0; | |
485 | } | |
486 | ||
487 | static void sil24_reset_controller(struct ata_port *ap) | |
488 | { | |
489 | printk(KERN_NOTICE DRV_NAME | |
490 | " ata%u: resetting controller...\n", ap->id); | |
4b4a5eae | 491 | if (__sil24_reset_controller((void __iomem *)ap->ioaddr.cmd_addr)) |
923f1225 TH |
492 | printk(KERN_ERR DRV_NAME |
493 | " ata%u: failed to reset controller\n", ap->id); | |
edb33667 TH |
494 | } |
495 | ||
496 | static void sil24_eng_timeout(struct ata_port *ap) | |
497 | { | |
498 | struct ata_queued_cmd *qc; | |
499 | ||
500 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
501 | if (!qc) { | |
a7dac447 | 502 | printk(KERN_ERR "ata%u: BUG: timeout without command\n", |
edb33667 TH |
503 | ap->id); |
504 | return; | |
505 | } | |
506 | ||
507 | /* | |
508 | * hack alert! We cannot use the supplied completion | |
509 | * function from inside the ->eh_strategy_handler() thread. | |
510 | * libata is the only user of ->eh_strategy_handler() in | |
511 | * any kernel, so the default scsi_done() assumes it is | |
512 | * not being called from the SCSI EH. | |
513 | */ | |
514 | printk(KERN_ERR "ata%u: command timeout\n", ap->id); | |
515 | qc->scsidone = scsi_finish_command; | |
a7dac447 | 516 | ata_qc_complete(qc, AC_ERR_OTHER); |
edb33667 TH |
517 | |
518 | sil24_reset_controller(ap); | |
519 | } | |
520 | ||
8746618d TH |
521 | static void sil24_error_intr(struct ata_port *ap, u32 slot_stat) |
522 | { | |
523 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag); | |
6a575fa9 | 524 | struct sil24_port_priv *pp = ap->private_data; |
4b4a5eae | 525 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
8746618d | 526 | u32 irq_stat, cmd_err, sstatus, serror; |
a7dac447 | 527 | unsigned int err_mask; |
8746618d TH |
528 | |
529 | irq_stat = readl(port + PORT_IRQ_STAT); | |
ad6e90f6 TH |
530 | writel(irq_stat, port + PORT_IRQ_STAT); /* clear irq */ |
531 | ||
532 | if (!(irq_stat & PORT_IRQ_ERROR)) { | |
533 | /* ignore non-completion, non-error irqs for now */ | |
534 | printk(KERN_WARNING DRV_NAME | |
535 | "ata%u: non-error exception irq (irq_stat %x)\n", | |
536 | ap->id, irq_stat); | |
537 | return; | |
538 | } | |
539 | ||
8746618d TH |
540 | cmd_err = readl(port + PORT_CMD_ERR); |
541 | sstatus = readl(port + PORT_SSTATUS); | |
542 | serror = readl(port + PORT_SERROR); | |
8746618d TH |
543 | if (serror) |
544 | writel(serror, port + PORT_SERROR); | |
545 | ||
546 | printk(KERN_ERR DRV_NAME " ata%u: error interrupt on port%d\n" | |
547 | " stat=0x%x irq=0x%x cmd_err=%d sstatus=0x%x serror=0x%x\n", | |
548 | ap->id, ap->port_no, slot_stat, irq_stat, cmd_err, sstatus, serror); | |
549 | ||
6a575fa9 TH |
550 | if (cmd_err == PORT_CERR_DEV || cmd_err == PORT_CERR_SDB) { |
551 | /* | |
552 | * Device is reporting error, tf registers are valid. | |
553 | */ | |
554 | sil24_update_tf(ap); | |
a7dac447 | 555 | err_mask = ac_err_mask(pp->tf.command); |
6a575fa9 TH |
556 | } else { |
557 | /* | |
558 | * Other errors. libata currently doesn't have any | |
559 | * mechanism to report these errors. Just turn on | |
560 | * ATA_ERR. | |
561 | */ | |
a7dac447 | 562 | err_mask = AC_ERR_OTHER; |
6a575fa9 TH |
563 | } |
564 | ||
8746618d | 565 | if (qc) |
a7dac447 | 566 | ata_qc_complete(qc, err_mask); |
8746618d TH |
567 | |
568 | sil24_reset_controller(ap); | |
569 | } | |
570 | ||
edb33667 TH |
571 | static inline void sil24_host_intr(struct ata_port *ap) |
572 | { | |
573 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag); | |
4b4a5eae | 574 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
edb33667 TH |
575 | u32 slot_stat; |
576 | ||
577 | slot_stat = readl(port + PORT_SLOT_STAT); | |
578 | if (!(slot_stat & HOST_SSTAT_ATTN)) { | |
6a575fa9 TH |
579 | struct sil24_port_priv *pp = ap->private_data; |
580 | /* | |
581 | * !HOST_SSAT_ATTN guarantees successful completion, | |
582 | * so reading back tf registers is unnecessary for | |
583 | * most commands. TODO: read tf registers for | |
584 | * commands which require these values on successful | |
585 | * completion (EXECUTE DEVICE DIAGNOSTIC, CHECK POWER, | |
586 | * DEVICE RESET and READ PORT MULTIPLIER (any more?). | |
587 | */ | |
588 | sil24_update_tf(ap); | |
589 | ||
edb33667 | 590 | if (qc) |
a7dac447 | 591 | ata_qc_complete(qc, ac_err_mask(pp->tf.command)); |
8746618d TH |
592 | } else |
593 | sil24_error_intr(ap, slot_stat); | |
edb33667 TH |
594 | } |
595 | ||
596 | static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs) | |
597 | { | |
598 | struct ata_host_set *host_set = dev_instance; | |
599 | struct sil24_host_priv *hpriv = host_set->private_data; | |
600 | unsigned handled = 0; | |
601 | u32 status; | |
602 | int i; | |
603 | ||
604 | status = readl(hpriv->host_base + HOST_IRQ_STAT); | |
605 | ||
06460aea TH |
606 | if (status == 0xffffffff) { |
607 | printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, " | |
608 | "PCI fault or device removal?\n"); | |
609 | goto out; | |
610 | } | |
611 | ||
edb33667 TH |
612 | if (!(status & IRQ_STAT_4PORTS)) |
613 | goto out; | |
614 | ||
615 | spin_lock(&host_set->lock); | |
616 | ||
617 | for (i = 0; i < host_set->n_ports; i++) | |
618 | if (status & (1 << i)) { | |
619 | struct ata_port *ap = host_set->ports[i]; | |
3cc4571c | 620 | if (ap && !(ap->flags & ATA_FLAG_PORT_DISABLED)) { |
edb33667 | 621 | sil24_host_intr(host_set->ports[i]); |
3cc4571c TH |
622 | handled++; |
623 | } else | |
624 | printk(KERN_ERR DRV_NAME | |
625 | ": interrupt from disabled port %d\n", i); | |
edb33667 TH |
626 | } |
627 | ||
628 | spin_unlock(&host_set->lock); | |
629 | out: | |
630 | return IRQ_RETVAL(handled); | |
631 | } | |
632 | ||
633 | static int sil24_port_start(struct ata_port *ap) | |
634 | { | |
635 | struct device *dev = ap->host_set->dev; | |
edb33667 TH |
636 | struct sil24_port_priv *pp; |
637 | struct sil24_cmd_block *cb; | |
638 | size_t cb_size = sizeof(*cb); | |
639 | dma_addr_t cb_dma; | |
640 | ||
641 | pp = kmalloc(sizeof(*pp), GFP_KERNEL); | |
642 | if (!pp) | |
643 | return -ENOMEM; | |
644 | memset(pp, 0, sizeof(*pp)); | |
645 | ||
6a575fa9 TH |
646 | pp->tf.command = ATA_DRDY; |
647 | ||
edb33667 TH |
648 | cb = dma_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL); |
649 | if (!cb) { | |
650 | kfree(pp); | |
651 | return -ENOMEM; | |
652 | } | |
653 | memset(cb, 0, cb_size); | |
654 | ||
edb33667 TH |
655 | pp->cmd_block = cb; |
656 | pp->cmd_block_dma = cb_dma; | |
657 | ||
658 | ap->private_data = pp; | |
659 | ||
660 | return 0; | |
661 | } | |
662 | ||
663 | static void sil24_port_stop(struct ata_port *ap) | |
664 | { | |
665 | struct device *dev = ap->host_set->dev; | |
666 | struct sil24_port_priv *pp = ap->private_data; | |
667 | size_t cb_size = sizeof(*pp->cmd_block); | |
668 | ||
669 | dma_free_coherent(dev, cb_size, pp->cmd_block, pp->cmd_block_dma); | |
670 | kfree(pp); | |
671 | } | |
672 | ||
673 | static void sil24_host_stop(struct ata_host_set *host_set) | |
674 | { | |
675 | struct sil24_host_priv *hpriv = host_set->private_data; | |
676 | ||
677 | iounmap(hpriv->host_base); | |
678 | iounmap(hpriv->port_base); | |
679 | kfree(hpriv); | |
680 | } | |
681 | ||
682 | static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |
683 | { | |
684 | static int printed_version = 0; | |
685 | unsigned int board_id = (unsigned int)ent->driver_data; | |
042c21fd | 686 | struct ata_port_info *pinfo = &sil24_port_info[board_id]; |
edb33667 TH |
687 | struct ata_probe_ent *probe_ent = NULL; |
688 | struct sil24_host_priv *hpriv = NULL; | |
4b4a5eae AV |
689 | void __iomem *host_base = NULL; |
690 | void __iomem *port_base = NULL; | |
edb33667 TH |
691 | int i, rc; |
692 | ||
693 | if (!printed_version++) | |
a9524a76 | 694 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
edb33667 TH |
695 | |
696 | rc = pci_enable_device(pdev); | |
697 | if (rc) | |
698 | return rc; | |
699 | ||
700 | rc = pci_request_regions(pdev, DRV_NAME); | |
701 | if (rc) | |
702 | goto out_disable; | |
703 | ||
704 | rc = -ENOMEM; | |
705 | /* ioremap mmio registers */ | |
706 | host_base = ioremap(pci_resource_start(pdev, 0), | |
707 | pci_resource_len(pdev, 0)); | |
708 | if (!host_base) | |
709 | goto out_free; | |
710 | port_base = ioremap(pci_resource_start(pdev, 2), | |
711 | pci_resource_len(pdev, 2)); | |
712 | if (!port_base) | |
713 | goto out_free; | |
714 | ||
715 | /* allocate & init probe_ent and hpriv */ | |
716 | probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL); | |
717 | if (!probe_ent) | |
718 | goto out_free; | |
719 | ||
720 | hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL); | |
721 | if (!hpriv) | |
722 | goto out_free; | |
723 | ||
724 | memset(probe_ent, 0, sizeof(*probe_ent)); | |
725 | probe_ent->dev = pci_dev_to_dev(pdev); | |
726 | INIT_LIST_HEAD(&probe_ent->node); | |
727 | ||
042c21fd TH |
728 | probe_ent->sht = pinfo->sht; |
729 | probe_ent->host_flags = pinfo->host_flags; | |
730 | probe_ent->pio_mask = pinfo->pio_mask; | |
731 | probe_ent->udma_mask = pinfo->udma_mask; | |
732 | probe_ent->port_ops = pinfo->port_ops; | |
733 | probe_ent->n_ports = SIL24_FLAG2NPORTS(pinfo->host_flags); | |
edb33667 TH |
734 | |
735 | probe_ent->irq = pdev->irq; | |
736 | probe_ent->irq_flags = SA_SHIRQ; | |
737 | probe_ent->mmio_base = port_base; | |
738 | probe_ent->private_data = hpriv; | |
739 | ||
740 | memset(hpriv, 0, sizeof(*hpriv)); | |
741 | hpriv->host_base = host_base; | |
742 | hpriv->port_base = port_base; | |
743 | ||
744 | /* | |
745 | * Configure the device | |
746 | */ | |
747 | /* | |
748 | * FIXME: This device is certainly 64-bit capable. We just | |
749 | * don't know how to use it. After fixing 32bit activation in | |
750 | * this function, enable 64bit masks here. | |
751 | */ | |
752 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
753 | if (rc) { | |
a9524a76 JG |
754 | dev_printk(KERN_ERR, &pdev->dev, |
755 | "32-bit DMA enable failed\n"); | |
edb33667 TH |
756 | goto out_free; |
757 | } | |
758 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
759 | if (rc) { | |
a9524a76 JG |
760 | dev_printk(KERN_ERR, &pdev->dev, |
761 | "32-bit consistent DMA enable failed\n"); | |
edb33667 TH |
762 | goto out_free; |
763 | } | |
764 | ||
765 | /* GPIO off */ | |
766 | writel(0, host_base + HOST_FLASH_CMD); | |
767 | ||
768 | /* Mask interrupts during initialization */ | |
769 | writel(0, host_base + HOST_CTRL); | |
770 | ||
771 | for (i = 0; i < probe_ent->n_ports; i++) { | |
4b4a5eae | 772 | void __iomem *port = port_base + i * PORT_REGS_SIZE; |
edb33667 TH |
773 | unsigned long portu = (unsigned long)port; |
774 | u32 tmp; | |
775 | int cnt; | |
776 | ||
4f50c3cb | 777 | probe_ent->port[i].cmd_addr = portu + PORT_PRB; |
edb33667 TH |
778 | probe_ent->port[i].scr_addr = portu + PORT_SCONTROL; |
779 | ||
780 | ata_std_ports(&probe_ent->port[i]); | |
781 | ||
782 | /* Initial PHY setting */ | |
783 | writel(0x20c, port + PORT_PHY_CFG); | |
784 | ||
785 | /* Clear port RST */ | |
786 | tmp = readl(port + PORT_CTRL_STAT); | |
787 | if (tmp & PORT_CS_PORT_RST) { | |
788 | writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR); | |
789 | readl(port + PORT_CTRL_STAT); /* sync */ | |
790 | for (cnt = 0; cnt < 10; cnt++) { | |
791 | msleep(10); | |
792 | tmp = readl(port + PORT_CTRL_STAT); | |
793 | if (!(tmp & PORT_CS_PORT_RST)) | |
794 | break; | |
795 | } | |
796 | if (tmp & PORT_CS_PORT_RST) | |
a9524a76 JG |
797 | dev_printk(KERN_ERR, &pdev->dev, |
798 | "failed to clear port RST\n"); | |
edb33667 TH |
799 | } |
800 | ||
801 | /* Zero error counters. */ | |
802 | writel(0x8000, port + PORT_DECODE_ERR_THRESH); | |
803 | writel(0x8000, port + PORT_CRC_ERR_THRESH); | |
804 | writel(0x8000, port + PORT_HSHK_ERR_THRESH); | |
805 | writel(0x0000, port + PORT_DECODE_ERR_CNT); | |
806 | writel(0x0000, port + PORT_CRC_ERR_CNT); | |
807 | writel(0x0000, port + PORT_HSHK_ERR_CNT); | |
808 | ||
809 | /* FIXME: 32bit activation? */ | |
810 | writel(0, port + PORT_ACTIVATE_UPPER_ADDR); | |
811 | writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_STAT); | |
812 | ||
813 | /* Configure interrupts */ | |
814 | writel(0xffff, port + PORT_IRQ_ENABLE_CLR); | |
815 | writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | PORT_IRQ_SDB_FIS, | |
816 | port + PORT_IRQ_ENABLE_SET); | |
817 | ||
818 | /* Clear interrupts */ | |
819 | writel(0x0fff0fff, port + PORT_IRQ_STAT); | |
820 | writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR); | |
923f1225 TH |
821 | |
822 | /* Clear port multiplier enable and resume bits */ | |
823 | writel(PORT_CS_PM_EN | PORT_CS_RESUME, port + PORT_CTRL_CLR); | |
824 | ||
825 | /* Reset itself */ | |
826 | if (__sil24_reset_controller(port)) | |
a9524a76 JG |
827 | dev_printk(KERN_ERR, &pdev->dev, |
828 | "failed to reset controller\n"); | |
edb33667 TH |
829 | } |
830 | ||
831 | /* Turn on interrupts */ | |
832 | writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL); | |
833 | ||
834 | pci_set_master(pdev); | |
835 | ||
1483467f | 836 | /* FIXME: check ata_device_add return value */ |
edb33667 TH |
837 | ata_device_add(probe_ent); |
838 | ||
839 | kfree(probe_ent); | |
840 | return 0; | |
841 | ||
842 | out_free: | |
843 | if (host_base) | |
844 | iounmap(host_base); | |
845 | if (port_base) | |
846 | iounmap(port_base); | |
847 | kfree(probe_ent); | |
848 | kfree(hpriv); | |
849 | pci_release_regions(pdev); | |
850 | out_disable: | |
851 | pci_disable_device(pdev); | |
852 | return rc; | |
853 | } | |
854 | ||
855 | static int __init sil24_init(void) | |
856 | { | |
857 | return pci_module_init(&sil24_pci_driver); | |
858 | } | |
859 | ||
860 | static void __exit sil24_exit(void) | |
861 | { | |
862 | pci_unregister_driver(&sil24_pci_driver); | |
863 | } | |
864 | ||
865 | MODULE_AUTHOR("Tejun Heo"); | |
866 | MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver"); | |
867 | MODULE_LICENSE("GPL"); | |
868 | MODULE_DEVICE_TABLE(pci, sil24_pci_tbl); | |
869 | ||
870 | module_init(sil24_init); | |
871 | module_exit(sil24_exit); |