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[PATCH] libata: set default cbl in probeinit
[deliverable/linux.git] / drivers / scsi / sata_sil24.c
CommitLineData
edb33667
TH		 1/*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
edb33667
TH		 8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
11 * later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 */
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/pci.h>
23#include <linux/blkdev.h>
24#include <linux/delay.h>
25#include <linux/interrupt.h>
26#include <linux/dma-mapping.h>
a9524a76 27#include <linux/device.h>
edb33667 28#include <scsi/scsi_host.h>
193515d5 29#include <scsi/scsi_cmnd.h>
edb33667
TH		 30#include <linux/libata.h>
31#include <asm/io.h>
32
33#define DRV_NAME "sata_sil24"
af64371a 34#define DRV_VERSION "0.24"
edb33667 35
edb33667
TH		 36/*
37 * Port request block (PRB) 32 bytes
38 */
39struct sil24_prb {
40 u16 ctrl;
41 u16 prot;
42 u32 rx_cnt;
43 u8 fis[6 * 4];
44};
45
46/*
47 * Scatter gather entry (SGE) 16 bytes
48 */
49struct sil24_sge {
50 u64 addr;
51 u32 cnt;
52 u32 flags;
53};
54
55/*
56 * Port multiplier
57 */
58struct sil24_port_multiplier {
59 u32 diag;
60 u32 sactive;
61};
62
63enum {
64 /*
65 * Global controller registers (128 bytes @ BAR0)
66 */
67 /* 32 bit regs */
68 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
69 HOST_CTRL = 0x40,
70 HOST_IRQ_STAT = 0x44,
71 HOST_PHY_CFG = 0x48,
72 HOST_BIST_CTRL = 0x50,
73 HOST_BIST_PTRN = 0x54,
74 HOST_BIST_STAT = 0x58,
75 HOST_MEM_BIST_STAT = 0x5c,
76 HOST_FLASH_CMD = 0x70,
77 /* 8 bit regs */
78 HOST_FLASH_DATA = 0x74,
79 HOST_TRANSITION_DETECT = 0x75,
80 HOST_GPIO_CTRL = 0x76,
81 HOST_I2C_ADDR = 0x78, /* 32 bit */
82 HOST_I2C_DATA = 0x7c,
83 HOST_I2C_XFER_CNT = 0x7e,
84 HOST_I2C_CTRL = 0x7f,
85
86 /* HOST_SLOT_STAT bits */
87 HOST_SSTAT_ATTN = (1 << 31),
88
89 /*
90 * Port registers
91 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
92 */
93 PORT_REGS_SIZE = 0x2000,
94 PORT_PRB = 0x0000, /* (32 bytes PRB + 16 bytes SGEs * 6) * 31 (3968 bytes) */
edb33667
TH		 95
96 PORT_PM = 0x0f80, /* 8 bytes PM * 16 (128 bytes) */
97 /* 32 bit regs */
83bbecc9
TH		 98 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
99 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
100 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
101 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
102 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
edb33667 103 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
83bbecc9
TH		 104 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
105 PORT_CMD_ERR = 0x1024, /* command error number */
edb33667
TH		 106 PORT_FIS_CFG = 0x1028,
107 PORT_FIFO_THRES = 0x102c,
108 /* 16 bit regs */
109 PORT_DECODE_ERR_CNT = 0x1040,
110 PORT_DECODE_ERR_THRESH = 0x1042,
111 PORT_CRC_ERR_CNT = 0x1044,
112 PORT_CRC_ERR_THRESH = 0x1046,
113 PORT_HSHK_ERR_CNT = 0x1048,
114 PORT_HSHK_ERR_THRESH = 0x104a,
115 /* 32 bit regs */
116 PORT_PHY_CFG = 0x1050,
117 PORT_SLOT_STAT = 0x1800,
118 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
119 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
120 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
121 PORT_SCONTROL = 0x1f00,
122 PORT_SSTATUS = 0x1f04,
123 PORT_SERROR = 0x1f08,
124 PORT_SACTIVE = 0x1f0c,
125
126 /* PORT_CTRL_STAT bits */
127 PORT_CS_PORT_RST = (1 << 0), /* port reset */
128 PORT_CS_DEV_RST = (1 << 1), /* device reset */
129 PORT_CS_INIT = (1 << 2), /* port initialize */
130 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
d10cb35a 131 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
e382eb1d
TH		 132 PORT_CS_RESUME = (1 << 6), /* port resume */
133 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
134 PORT_CS_PM_EN = (1 << 13), /* port multiplier enable */
135 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
edb33667
TH		 136
137 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
138 /* bits[11:0] are masked */
139 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
140 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
141 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
142 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
143 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
144 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
145 PORT_IRQ_UNK_FIS = (1 << 6), /* Unknown FIS received */
146 PORT_IRQ_SDB_FIS = (1 << 11), /* SDB FIS received */
147
148 /* bits[27:16] are unmasked (raw) */
149 PORT_IRQ_RAW_SHIFT = 16,
150 PORT_IRQ_MASKED_MASK = 0x7ff,
151 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
152
153 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
154 PORT_IRQ_STEER_SHIFT = 30,
155 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
156
157 /* PORT_CMD_ERR constants */
158 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
159 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
160 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
161 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
162 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
163 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
164 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
165 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
166 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
167 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
168 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
169 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
170 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
171 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
172 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
173 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
174 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
175 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
176 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
177 PORT_CERR_XFR_MSGABRT = 34, /* PSD ecode 10 - master abort */
178 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
83bbecc9 179 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
edb33667 180
d10cb35a
TH		 181 /* bits of PRB control field */
182 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
183 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
184 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
185 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
186 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
187
188 /* PRB protocol field */
189 PRB_PROT_PACKET = (1 << 0),
190 PRB_PROT_TCQ = (1 << 1),
191 PRB_PROT_NCQ = (1 << 2),
192 PRB_PROT_READ = (1 << 3),
193 PRB_PROT_WRITE = (1 << 4),
194 PRB_PROT_TRANSPARENT = (1 << 5),
195
edb33667
TH		 196 /*
197 * Other constants
198 */
199 SGE_TRM = (1 << 31), /* Last SGE in chain */
d10cb35a
TH		 200 SGE_LNK = (1 << 30), /* linked list
201 Points to SGT, not SGE */
202 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
203 data address ignored */
edb33667
TH		 204
205 /* board id */
206 BID_SIL3124 = 0,
207 BID_SIL3132 = 1,
042c21fd 208 BID_SIL3131 = 2,
edb33667
TH		 209
210 IRQ_STAT_4PORTS = 0xf,
211};
212
69ad185f 213struct sil24_ata_block {
edb33667
TH		 214 struct sil24_prb prb;
215 struct sil24_sge sge[LIBATA_MAX_PRD];
216};
217
69ad185f
TH		 218struct sil24_atapi_block {
219 struct sil24_prb prb;
220 u8 cdb[16];
221 struct sil24_sge sge[LIBATA_MAX_PRD - 1];
222};
223
224union sil24_cmd_block {
225 struct sil24_ata_block ata;
226 struct sil24_atapi_block atapi;
227};
228
edb33667
TH		 229/*
230 * ap->private_data
231 *
232 * The preview driver always returned 0 for status. We emulate it
233 * here from the previous interrupt.
234 */
235struct sil24_port_priv {
69ad185f 236 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
edb33667 237 dma_addr_t cmd_block_dma; /* DMA base addr for them */
6a575fa9 238 struct ata_taskfile tf; /* Cached taskfile registers */
edb33667
TH		 239};
240
241/* ap->host_set->private_data */
242struct sil24_host_priv {
4b4a5eae
AV		 243 void __iomem *host_base; /* global controller control (128 bytes @BAR0) */
244 void __iomem *port_base; /* port registers (4 * 8192 bytes @BAR2) */
edb33667
TH		 245};
246
69ad185f 247static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev);
edb33667 248static u8 sil24_check_status(struct ata_port *ap);
edb33667
TH		 249static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg);
250static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
7f726d12 251static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
07b73470 252static int sil24_probe_reset(struct ata_port *ap, unsigned int *classes);
edb33667 253static void sil24_qc_prep(struct ata_queued_cmd *qc);
9a3d9eb0 254static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
edb33667
TH		 255static void sil24_irq_clear(struct ata_port *ap);
256static void sil24_eng_timeout(struct ata_port *ap);
257static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
258static int sil24_port_start(struct ata_port *ap);
259static void sil24_port_stop(struct ata_port *ap);
260static void sil24_host_stop(struct ata_host_set *host_set);
261static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
262
3b7d697d 263static const struct pci_device_id sil24_pci_tbl[] = {
edb33667 264 { 0x1095, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 },
4b9d7e04 265 { 0x8086, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 },
edb33667 266 { 0x1095, 0x3132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3132 },
042c21fd
TH		 267 { 0x1095, 0x3131, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
268 { 0x1095, 0x3531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
1fcce839 269 { } /* terminate list */
edb33667
TH		 270};
271
272static struct pci_driver sil24_pci_driver = {
273 .name = DRV_NAME,
274 .id_table = sil24_pci_tbl,
275 .probe = sil24_init_one,
276 .remove = ata_pci_remove_one, /* safe? */
277};
278
193515d5 279static struct scsi_host_template sil24_sht = {
edb33667
TH		 280 .module = THIS_MODULE,
281 .name = DRV_NAME,
282 .ioctl = ata_scsi_ioctl,
283 .queuecommand = ata_scsi_queuecmd,
edb33667
TH		 284 .can_queue = ATA_DEF_QUEUE,
285 .this_id = ATA_SHT_THIS_ID,
286 .sg_tablesize = LIBATA_MAX_PRD,
edb33667
TH		 287 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
288 .emulated = ATA_SHT_EMULATED,
289 .use_clustering = ATA_SHT_USE_CLUSTERING,
290 .proc_name = DRV_NAME,
291 .dma_boundary = ATA_DMA_BOUNDARY,
292 .slave_configure = ata_scsi_slave_config,
293 .bios_param = ata_std_bios_param,
edb33667
TH		 294};
295
057ace5e 296static const struct ata_port_operations sil24_ops = {
edb33667
TH		 297 .port_disable = ata_port_disable,
298
69ad185f
TH		 299 .dev_config = sil24_dev_config,
300
edb33667
TH		 301 .check_status = sil24_check_status,
302 .check_altstatus = sil24_check_status,
edb33667
TH		 303 .dev_select = ata_noop_dev_select,
304
7f726d12
TH		 305 .tf_read = sil24_tf_read,
306
07b73470 307 .probe_reset = sil24_probe_reset,
edb33667
TH		 308
309 .qc_prep = sil24_qc_prep,
310 .qc_issue = sil24_qc_issue,
311
312 .eng_timeout = sil24_eng_timeout,
313
314 .irq_handler = sil24_interrupt,
315 .irq_clear = sil24_irq_clear,
316
317 .scr_read = sil24_scr_read,
318 .scr_write = sil24_scr_write,
319
320 .port_start = sil24_port_start,
321 .port_stop = sil24_port_stop,
322 .host_stop = sil24_host_stop,
323};
324
042c21fd
TH		 325/*
326 * Use bits 30-31 of host_flags to encode available port numbers.
327 * Current maxium is 4.
328 */
329#define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
330#define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
331
edb33667
TH		 332static struct ata_port_info sil24_port_info[] = {
333 /* sil_3124 */
334 {
335 .sht = &sil24_sht,
336 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
07b73470
TH		 337 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
338 SIL24_NPORTS2FLAG(4),
edb33667
TH		 339 .pio_mask = 0x1f, /* pio0-4 */
340 .mwdma_mask = 0x07, /* mwdma0-2 */
341 .udma_mask = 0x3f, /* udma0-5 */
342 .port_ops = &sil24_ops,
343 },
2e9edbf8 344 /* sil_3132 */
edb33667
TH		 345 {
346 .sht = &sil24_sht,
347 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
07b73470
TH		 348 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
349 SIL24_NPORTS2FLAG(2),
042c21fd
TH		 350 .pio_mask = 0x1f, /* pio0-4 */
351 .mwdma_mask = 0x07, /* mwdma0-2 */
352 .udma_mask = 0x3f, /* udma0-5 */
353 .port_ops = &sil24_ops,
354 },
355 /* sil_3131/sil_3531 */
356 {
357 .sht = &sil24_sht,
358 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
07b73470
TH		 359 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
360 SIL24_NPORTS2FLAG(1),
edb33667
TH		 361 .pio_mask = 0x1f, /* pio0-4 */
362 .mwdma_mask = 0x07, /* mwdma0-2 */
363 .udma_mask = 0x3f, /* udma0-5 */
364 .port_ops = &sil24_ops,
365 },
366};
367
69ad185f
TH		 368static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev)
369{
370 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
371
6e7846e9 372 if (dev->cdb_len == 16)
69ad185f
TH		 373 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
374 else
375 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
376}
377
6a575fa9
TH		 378static inline void sil24_update_tf(struct ata_port *ap)
379{
380 struct sil24_port_priv *pp = ap->private_data;
4b4a5eae
AV		 381 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
382 struct sil24_prb __iomem *prb = port;
383 u8 fis[6 * 4];
6a575fa9 384
4b4a5eae
AV		 385 memcpy_fromio(fis, prb->fis, 6 * 4);
386 ata_tf_from_fis(fis, &pp->tf);
6a575fa9
TH		 387}
388
edb33667
TH		 389static u8 sil24_check_status(struct ata_port *ap)
390{
6a575fa9
TH		 391 struct sil24_port_priv *pp = ap->private_data;
392 return pp->tf.command;
edb33667
TH		 393}
394
edb33667
TH		 395static int sil24_scr_map[] = {
396 [SCR_CONTROL] = 0,
397 [SCR_STATUS] = 1,
398 [SCR_ERROR] = 2,
399 [SCR_ACTIVE] = 3,
400};
401
402static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg)
403{
4b4a5eae 404 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
edb33667 405 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
4b4a5eae 406 void __iomem *addr;
edb33667
TH		 407 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
408 return readl(scr_addr + sil24_scr_map[sc_reg] * 4);
409 }
410 return 0xffffffffU;
411}
412
413static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
414{
4b4a5eae 415 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
edb33667 416 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
4b4a5eae 417 void __iomem *addr;
edb33667
TH		 418 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
419 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
420 }
421}
422
7f726d12
TH		 423static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
424{
425 struct sil24_port_priv *pp = ap->private_data;
426 *tf = pp->tf;
427}
428
07b73470
TH		 429static int sil24_softreset(struct ata_port *ap, int verbose,
430 unsigned int *class)
edb33667 431{
ca45160d
TH		 432 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
433 struct sil24_port_priv *pp = ap->private_data;
69ad185f 434 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
ca45160d 435 dma_addr_t paddr = pp->cmd_block_dma;
8645984c 436 unsigned long timeout = jiffies + ATA_TMOUT_BOOT * HZ;
ca45160d 437 u32 irq_enable, irq_stat;
ca45160d 438
07b73470
TH		 439 DPRINTK("ENTER\n");
440
10d996ad
TH		 441 if (!sata_dev_present(ap)) {
442 DPRINTK("PHY reports no device\n");
443 *class = ATA_DEV_NONE;
444 goto out;
445 }
446
ca45160d
TH		 447 /* temporarily turn off IRQs during SRST */
448 irq_enable = readl(port + PORT_IRQ_ENABLE_SET);
449 writel(irq_enable, port + PORT_IRQ_ENABLE_CLR);
450
edb33667 451 /*
ca45160d
TH		 452 * XXX: Not sure whether the following sleep is needed or not.
453 * The original driver had it. So....
edb33667 454 */
ca45160d
TH		 455 msleep(10);
456
457 prb->ctrl = PRB_CTRL_SRST;
458 prb->fis[1] = 0; /* no PM yet */
459
460 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
461
8645984c 462 do {
ca45160d
TH		 463 irq_stat = readl(port + PORT_IRQ_STAT);
464 writel(irq_stat, port + PORT_IRQ_STAT); /* clear irq */
465
466 irq_stat >>= PORT_IRQ_RAW_SHIFT;
467 if (irq_stat & (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR))
468 break;
469
8645984c
TH		 470 msleep(100);
471 } while (time_before(jiffies, timeout));
ca45160d
TH		 472
473 /* restore IRQs */
474 writel(irq_enable, port + PORT_IRQ_ENABLE_SET);
475
10d996ad
TH		 476 if (!(irq_stat & PORT_IRQ_COMPLETE)) {
477 DPRINTK("EXIT, srst failed\n");
478 return -EIO;
07b73470 479 }
10d996ad
TH		 480
481 sil24_update_tf(ap);
482 *class = ata_dev_classify(&pp->tf);
483
07b73470
TH		 484 if (*class == ATA_DEV_UNKNOWN)
485 *class = ATA_DEV_NONE;
ca45160d 486
10d996ad 487 out:
07b73470 488 DPRINTK("EXIT, class=%u\n", *class);
ca45160d
TH		 489 return 0;
490}
491
489ff4c7
TH		 492static int sil24_hardreset(struct ata_port *ap, int verbose,
493 unsigned int *class)
494{
495 unsigned int dummy_class;
496
497 /* sil24 doesn't report device signature after hard reset */
498 return sata_std_hardreset(ap, verbose, &dummy_class);
499}
500
07b73470 501static int sil24_probe_reset(struct ata_port *ap, unsigned int *classes)
ca45160d 502{
07b73470 503 return ata_drive_probe_reset(ap, ata_std_probeinit,
489ff4c7 504 sil24_softreset, sil24_hardreset,
07b73470 505 ata_std_postreset, classes);
edb33667
TH		 506}
507
508static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
69ad185f 509 struct sil24_sge *sge)
edb33667 510{
972c26bd
JG		 511 struct scatterlist *sg;
512 unsigned int idx = 0;
edb33667 513
972c26bd 514 ata_for_each_sg(sg, qc) {
edb33667
TH		 515 sge->addr = cpu_to_le64(sg_dma_address(sg));
516 sge->cnt = cpu_to_le32(sg_dma_len(sg));
972c26bd
JG		 517 if (ata_sg_is_last(sg, qc))
518 sge->flags = cpu_to_le32(SGE_TRM);
519 else
520 sge->flags = 0;
521
522 sge++;
523 idx++;
edb33667
TH		 524 }
525}
526
527static void sil24_qc_prep(struct ata_queued_cmd *qc)
528{
529 struct ata_port *ap = qc->ap;
530 struct sil24_port_priv *pp = ap->private_data;
69ad185f
TH		 531 union sil24_cmd_block *cb = pp->cmd_block + qc->tag;
532 struct sil24_prb *prb;
533 struct sil24_sge *sge;
edb33667
TH		 534
535 switch (qc->tf.protocol) {
536 case ATA_PROT_PIO:
537 case ATA_PROT_DMA:
538 case ATA_PROT_NODATA:
69ad185f
TH		 539 prb = &cb->ata.prb;
540 sge = cb->ata.sge;
541 prb->ctrl = 0;
edb33667 542 break;
69ad185f
TH		 543
544 case ATA_PROT_ATAPI:
545 case ATA_PROT_ATAPI_DMA:
546 case ATA_PROT_ATAPI_NODATA:
547 prb = &cb->atapi.prb;
548 sge = cb->atapi.sge;
549 memset(cb->atapi.cdb, 0, 32);
6e7846e9 550 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
69ad185f
TH		 551
552 if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) {
553 if (qc->tf.flags & ATA_TFLAG_WRITE)
554 prb->ctrl = PRB_CTRL_PACKET_WRITE;
555 else
556 prb->ctrl = PRB_CTRL_PACKET_READ;
557 } else
558 prb->ctrl = 0;
559
560 break;
561
edb33667 562 default:
69ad185f
TH		 563 prb = NULL; /* shut up, gcc */
564 sge = NULL;
edb33667
TH		 565 BUG();
566 }
567
568 ata_tf_to_fis(&qc->tf, prb->fis, 0);
569
570 if (qc->flags & ATA_QCFLAG_DMAMAP)
69ad185f 571 sil24_fill_sg(qc, sge);
edb33667
TH		 572}
573
9a3d9eb0 574static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
edb33667
TH		 575{
576 struct ata_port *ap = qc->ap;
4b4a5eae 577 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
edb33667
TH		 578 struct sil24_port_priv *pp = ap->private_data;
579 dma_addr_t paddr = pp->cmd_block_dma + qc->tag * sizeof(*pp->cmd_block);
580
4f50c3cb 581 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
edb33667
TH		 582 return 0;
583}
584
585static void sil24_irq_clear(struct ata_port *ap)
586{
587 /* unused */
588}
589
7d1ce682
TH		 590static int __sil24_restart_controller(void __iomem *port)
591{
592 u32 tmp;
593 int cnt;
594
595 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
596
597 /* Max ~10ms */
598 for (cnt = 0; cnt < 10000; cnt++) {
599 tmp = readl(port + PORT_CTRL_STAT);
600 if (tmp & PORT_CS_RDY)
601 return 0;
602 udelay(1);
603 }
604
605 return -1;
606}
607
608static void sil24_restart_controller(struct ata_port *ap)
609{
610 if (__sil24_restart_controller((void __iomem *)ap->ioaddr.cmd_addr))
611 printk(KERN_ERR DRV_NAME
612 " ata%u: failed to restart controller\n", ap->id);
613}
614
4b4a5eae 615static int __sil24_reset_controller(void __iomem *port)
edb33667 616{
edb33667
TH		 617 int cnt;
618 u32 tmp;
619
edb33667
TH		 620 /* Reset controller state. Is this correct? */
621 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
622 readl(port + PORT_CTRL_STAT); /* sync */
623
624 /* Max ~100ms */
625 for (cnt = 0; cnt < 1000; cnt++) {
626 udelay(100);
627 tmp = readl(port + PORT_CTRL_STAT);
628 if (!(tmp & PORT_CS_DEV_RST))
629 break;
630 }
923f1225 631
edb33667 632 if (tmp & PORT_CS_DEV_RST)
923f1225 633 return -1;
7d1ce682
TH		 634
635 if (tmp & PORT_CS_RDY)
636 return 0;
637
638 return __sil24_restart_controller(port);
923f1225
TH		 639}
640
641static void sil24_reset_controller(struct ata_port *ap)
642{
643 printk(KERN_NOTICE DRV_NAME
644 " ata%u: resetting controller...\n", ap->id);
4b4a5eae 645 if (__sil24_reset_controller((void __iomem *)ap->ioaddr.cmd_addr))
923f1225
TH		 646 printk(KERN_ERR DRV_NAME
647 " ata%u: failed to reset controller\n", ap->id);
edb33667
TH		 648}
649
650static void sil24_eng_timeout(struct ata_port *ap)
651{
652 struct ata_queued_cmd *qc;
653
654 qc = ata_qc_from_tag(ap, ap->active_tag);
edb33667 655
edb33667 656 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
11a56d24 657 qc->err_mask |= AC_ERR_TIMEOUT;
a72ec4ce 658 ata_eh_qc_complete(qc);
edb33667
TH		 659
660 sil24_reset_controller(ap);
661}
662
8746618d
TH		 663static void sil24_error_intr(struct ata_port *ap, u32 slot_stat)
664{
665 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
6a575fa9 666 struct sil24_port_priv *pp = ap->private_data;
4b4a5eae 667 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
8746618d 668 u32 irq_stat, cmd_err, sstatus, serror;
a7dac447 669 unsigned int err_mask;
8746618d
TH		 670
671 irq_stat = readl(port + PORT_IRQ_STAT);
ad6e90f6
TH		 672 writel(irq_stat, port + PORT_IRQ_STAT); /* clear irq */
673
674 if (!(irq_stat & PORT_IRQ_ERROR)) {
675 /* ignore non-completion, non-error irqs for now */
676 printk(KERN_WARNING DRV_NAME
677 "ata%u: non-error exception irq (irq_stat %x)\n",
678 ap->id, irq_stat);
679 return;
680 }
681
8746618d
TH		 682 cmd_err = readl(port + PORT_CMD_ERR);
683 sstatus = readl(port + PORT_SSTATUS);
684 serror = readl(port + PORT_SERROR);
8746618d
TH		 685 if (serror)
686 writel(serror, port + PORT_SERROR);
687
c0ab4242
TH		 688 /*
689 * Don't log ATAPI device errors. They're supposed to happen
690 * and any serious errors will be logged using sense data by
691 * the SCSI layer.
692 */
693 if (ap->device[0].class != ATA_DEV_ATAPI || cmd_err > PORT_CERR_SDB)
694 printk("ata%u: error interrupt on port%d\n"
695 " stat=0x%x irq=0x%x cmd_err=%d sstatus=0x%x serror=0x%x\n",
696 ap->id, ap->port_no, slot_stat, irq_stat, cmd_err, sstatus, serror);
8746618d 697
6a575fa9
TH		 698 if (cmd_err == PORT_CERR_DEV || cmd_err == PORT_CERR_SDB) {
699 /*
700 * Device is reporting error, tf registers are valid.
701 */
702 sil24_update_tf(ap);
a7dac447 703 err_mask = ac_err_mask(pp->tf.command);
7d1ce682 704 sil24_restart_controller(ap);
6a575fa9
TH		 705 } else {
706 /*
707 * Other errors. libata currently doesn't have any
708 * mechanism to report these errors. Just turn on
709 * ATA_ERR.
710 */
a7dac447 711 err_mask = AC_ERR_OTHER;
7d1ce682 712 sil24_reset_controller(ap);
6a575fa9
TH		 713 }
714
a22e2eb0
AL		 715 if (qc) {
716 qc->err_mask |= err_mask;
717 ata_qc_complete(qc);
718 }
8746618d
TH		 719}
720
edb33667
TH		 721static inline void sil24_host_intr(struct ata_port *ap)
722{
723 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
4b4a5eae 724 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
edb33667
TH		 725 u32 slot_stat;
726
727 slot_stat = readl(port + PORT_SLOT_STAT);
728 if (!(slot_stat & HOST_SSTAT_ATTN)) {
6a575fa9
TH		 729 struct sil24_port_priv *pp = ap->private_data;
730 /*
731 * !HOST_SSAT_ATTN guarantees successful completion,
732 * so reading back tf registers is unnecessary for
733 * most commands. TODO: read tf registers for
734 * commands which require these values on successful
735 * completion (EXECUTE DEVICE DIAGNOSTIC, CHECK POWER,
736 * DEVICE RESET and READ PORT MULTIPLIER (any more?).
737 */
738 sil24_update_tf(ap);
739
a22e2eb0
AL		 740 if (qc) {
741 qc->err_mask |= ac_err_mask(pp->tf.command);
742 ata_qc_complete(qc);
743 }
8746618d
TH		 744 } else
745 sil24_error_intr(ap, slot_stat);
edb33667
TH		 746}
747
748static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
749{
750 struct ata_host_set *host_set = dev_instance;
751 struct sil24_host_priv *hpriv = host_set->private_data;
752 unsigned handled = 0;
753 u32 status;
754 int i;
755
756 status = readl(hpriv->host_base + HOST_IRQ_STAT);
757
06460aea
TH		 758 if (status == 0xffffffff) {
759 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
760 "PCI fault or device removal?\n");
761 goto out;
762 }
763
edb33667
TH		 764 if (!(status & IRQ_STAT_4PORTS))
765 goto out;
766
767 spin_lock(&host_set->lock);
768
769 for (i = 0; i < host_set->n_ports; i++)
770 if (status & (1 << i)) {
771 struct ata_port *ap = host_set->ports[i];
198e0fed 772 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
edb33667 773 sil24_host_intr(host_set->ports[i]);
3cc4571c
TH		 774 handled++;
775 } else
776 printk(KERN_ERR DRV_NAME
777 ": interrupt from disabled port %d\n", i);
edb33667
TH		 778 }
779
780 spin_unlock(&host_set->lock);
781 out:
782 return IRQ_RETVAL(handled);
783}
784
6037d6bb
JG		 785static inline void sil24_cblk_free(struct sil24_port_priv *pp, struct device *dev)
786{
787 const size_t cb_size = sizeof(*pp->cmd_block);
788
789 dma_free_coherent(dev, cb_size, pp->cmd_block, pp->cmd_block_dma);
790}
791
edb33667
TH		 792static int sil24_port_start(struct ata_port *ap)
793{
794 struct device *dev = ap->host_set->dev;
edb33667 795 struct sil24_port_priv *pp;
69ad185f 796 union sil24_cmd_block *cb;
edb33667
TH		 797 size_t cb_size = sizeof(*cb);
798 dma_addr_t cb_dma;
6037d6bb 799 int rc = -ENOMEM;
edb33667 800
6037d6bb 801 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
edb33667 802 if (!pp)
6037d6bb 803 goto err_out;
edb33667 804
6a575fa9
TH		 805 pp->tf.command = ATA_DRDY;
806
edb33667 807 cb = dma_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
6037d6bb
JG		 808 if (!cb)
809 goto err_out_pp;
edb33667
TH		 810 memset(cb, 0, cb_size);
811
6037d6bb
JG		 812 rc = ata_pad_alloc(ap, dev);
813 if (rc)
814 goto err_out_pad;
815
edb33667
TH		 816 pp->cmd_block = cb;
817 pp->cmd_block_dma = cb_dma;
818
819 ap->private_data = pp;
820
821 return 0;
6037d6bb
JG		 822
823err_out_pad:
824 sil24_cblk_free(pp, dev);
825err_out_pp:
826 kfree(pp);
827err_out:
828 return rc;
edb33667
TH		 829}
830
831static void sil24_port_stop(struct ata_port *ap)
832{
833 struct device *dev = ap->host_set->dev;
834 struct sil24_port_priv *pp = ap->private_data;
edb33667 835
6037d6bb 836 sil24_cblk_free(pp, dev);
e9c05afa 837 ata_pad_free(ap, dev);
edb33667
TH		 838 kfree(pp);
839}
840
841static void sil24_host_stop(struct ata_host_set *host_set)
842{
843 struct sil24_host_priv *hpriv = host_set->private_data;
142877b0 844 struct pci_dev *pdev = to_pci_dev(host_set->dev);
edb33667 845
142877b0
JG		 846 pci_iounmap(pdev, hpriv->host_base);
847 pci_iounmap(pdev, hpriv->port_base);
edb33667
TH		 848 kfree(hpriv);
849}
850
851static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
852{
853 static int printed_version = 0;
854 unsigned int board_id = (unsigned int)ent->driver_data;
042c21fd 855 struct ata_port_info *pinfo = &sil24_port_info[board_id];
edb33667
TH		 856 struct ata_probe_ent *probe_ent = NULL;
857 struct sil24_host_priv *hpriv = NULL;
4b4a5eae
AV		 858 void __iomem *host_base = NULL;
859 void __iomem *port_base = NULL;
edb33667
TH		 860 int i, rc;
861
862 if (!printed_version++)
a9524a76 863 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
edb33667
TH		 864
865 rc = pci_enable_device(pdev);
866 if (rc)
867 return rc;
868
869 rc = pci_request_regions(pdev, DRV_NAME);
870 if (rc)
871 goto out_disable;
872
873 rc = -ENOMEM;
142877b0
JG		 874 /* map mmio registers */
875 host_base = pci_iomap(pdev, 0, 0);
edb33667
TH		 876 if (!host_base)
877 goto out_free;
142877b0 878 port_base = pci_iomap(pdev, 2, 0);
edb33667
TH		 879 if (!port_base)
880 goto out_free;
881
882 /* allocate & init probe_ent and hpriv */
142877b0 883 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
edb33667
TH		 884 if (!probe_ent)
885 goto out_free;
886
142877b0 887 hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
edb33667
TH		 888 if (!hpriv)
889 goto out_free;
890
edb33667
TH		 891 probe_ent->dev = pci_dev_to_dev(pdev);
892 INIT_LIST_HEAD(&probe_ent->node);
893
042c21fd
TH		 894 probe_ent->sht = pinfo->sht;
895 probe_ent->host_flags = pinfo->host_flags;
896 probe_ent->pio_mask = pinfo->pio_mask;
fbfda6e7 897 probe_ent->mwdma_mask = pinfo->mwdma_mask;
042c21fd
TH		 898 probe_ent->udma_mask = pinfo->udma_mask;
899 probe_ent->port_ops = pinfo->port_ops;
900 probe_ent->n_ports = SIL24_FLAG2NPORTS(pinfo->host_flags);
edb33667
TH		 901
902 probe_ent->irq = pdev->irq;
903 probe_ent->irq_flags = SA_SHIRQ;
904 probe_ent->mmio_base = port_base;
905 probe_ent->private_data = hpriv;
906
edb33667
TH		 907 hpriv->host_base = host_base;
908 hpriv->port_base = port_base;
909
910 /*
911 * Configure the device
912 */
913 /*
914 * FIXME: This device is certainly 64-bit capable. We just
915 * don't know how to use it. After fixing 32bit activation in
916 * this function, enable 64bit masks here.
917 */
918 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
919 if (rc) {
a9524a76
JG		 920 dev_printk(KERN_ERR, &pdev->dev,
921 "32-bit DMA enable failed\n");
edb33667
TH		 922 goto out_free;
923 }
924 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
925 if (rc) {
a9524a76
JG		 926 dev_printk(KERN_ERR, &pdev->dev,
927 "32-bit consistent DMA enable failed\n");
edb33667
TH		 928 goto out_free;
929 }
930
931 /* GPIO off */
932 writel(0, host_base + HOST_FLASH_CMD);
933
934 /* Mask interrupts during initialization */
935 writel(0, host_base + HOST_CTRL);
936
937 for (i = 0; i < probe_ent->n_ports; i++) {
4b4a5eae 938 void __iomem *port = port_base + i * PORT_REGS_SIZE;
edb33667
TH		 939 unsigned long portu = (unsigned long)port;
940 u32 tmp;
941 int cnt;
942
4f50c3cb 943 probe_ent->port[i].cmd_addr = portu + PORT_PRB;
edb33667
TH		 944 probe_ent->port[i].scr_addr = portu + PORT_SCONTROL;
945
946 ata_std_ports(&probe_ent->port[i]);
947
948 /* Initial PHY setting */
949 writel(0x20c, port + PORT_PHY_CFG);
950
951 /* Clear port RST */
952 tmp = readl(port + PORT_CTRL_STAT);
953 if (tmp & PORT_CS_PORT_RST) {
954 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
955 readl(port + PORT_CTRL_STAT); /* sync */
956 for (cnt = 0; cnt < 10; cnt++) {
957 msleep(10);
958 tmp = readl(port + PORT_CTRL_STAT);
959 if (!(tmp & PORT_CS_PORT_RST))
960 break;
961 }
962 if (tmp & PORT_CS_PORT_RST)
a9524a76
JG		 963 dev_printk(KERN_ERR, &pdev->dev,
964 "failed to clear port RST\n");
edb33667
TH		 965 }
966
967 /* Zero error counters. */
968 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
969 writel(0x8000, port + PORT_CRC_ERR_THRESH);
970 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
971 writel(0x0000, port + PORT_DECODE_ERR_CNT);
972 writel(0x0000, port + PORT_CRC_ERR_CNT);
973 writel(0x0000, port + PORT_HSHK_ERR_CNT);
974
975 /* FIXME: 32bit activation? */
976 writel(0, port + PORT_ACTIVATE_UPPER_ADDR);
977 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_STAT);
978
979 /* Configure interrupts */
980 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
981 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | PORT_IRQ_SDB_FIS,
982 port + PORT_IRQ_ENABLE_SET);
983
984 /* Clear interrupts */
985 writel(0x0fff0fff, port + PORT_IRQ_STAT);
986 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
923f1225
TH		 987
988 /* Clear port multiplier enable and resume bits */
989 writel(PORT_CS_PM_EN | PORT_CS_RESUME, port + PORT_CTRL_CLR);
990
991 /* Reset itself */
992 if (__sil24_reset_controller(port))
a9524a76
JG		 993 dev_printk(KERN_ERR, &pdev->dev,
994 "failed to reset controller\n");
edb33667
TH		 995 }
996
997 /* Turn on interrupts */
998 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
999
1000 pci_set_master(pdev);
1001
1483467f 1002 /* FIXME: check ata_device_add return value */
edb33667
TH		 1003 ata_device_add(probe_ent);
1004
1005 kfree(probe_ent);
1006 return 0;
1007
1008 out_free:
1009 if (host_base)
142877b0 1010 pci_iounmap(pdev, host_base);
edb33667 1011 if (port_base)
142877b0 1012 pci_iounmap(pdev, port_base);
edb33667
TH		 1013 kfree(probe_ent);
1014 kfree(hpriv);
1015 pci_release_regions(pdev);
1016 out_disable:
1017 pci_disable_device(pdev);
1018 return rc;
1019}
1020
1021static int __init sil24_init(void)
1022{
1023 return pci_module_init(&sil24_pci_driver);
1024}
1025
1026static void __exit sil24_exit(void)
1027{
1028 pci_unregister_driver(&sil24_pci_driver);
1029}
1030
1031MODULE_AUTHOR("Tejun Heo");
1032MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1033MODULE_LICENSE("GPL");
1034MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1035
1036module_init(sil24_init);
1037module_exit(sil24_exit);
Linux kernel - Deliverables
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