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1da177e4 LT |
1 | /* |
2 | * sata_sis.c - Silicon Integrated Systems SATA | |
3 | * | |
4 | * Maintained by: Uwe Koziolek | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2004 Uwe Koziolek | |
9 | * | |
af36d7f0 JG |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * Hardware documentation available under NDA. | |
1da177e4 LT |
30 | * |
31 | */ | |
32 | ||
33 | #include <linux/config.h> | |
34 | #include <linux/kernel.h> | |
35 | #include <linux/module.h> | |
36 | #include <linux/pci.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/blkdev.h> | |
39 | #include <linux/delay.h> | |
40 | #include <linux/interrupt.h> | |
a9524a76 | 41 | #include <linux/device.h> |
1da177e4 LT |
42 | #include <scsi/scsi_host.h> |
43 | #include <linux/libata.h> | |
44 | ||
45 | #define DRV_NAME "sata_sis" | |
46 | #define DRV_VERSION "0.5" | |
47 | ||
48 | enum { | |
49 | sis_180 = 0, | |
50 | SIS_SCR_PCI_BAR = 5, | |
51 | ||
52 | /* PCI configuration registers */ | |
53 | SIS_GENCTL = 0x54, /* IDE General Control register */ | |
54 | SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */ | |
f2c853bc AP |
55 | SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */ |
56 | SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */ | |
57 | SIS_PMR = 0x90, /* port mapping register */ | |
8add7885 | 58 | SIS_PMR_COMBINED = 0x30, |
1da177e4 LT |
59 | |
60 | /* random bits */ | |
61 | SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */ | |
62 | ||
63 | GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */ | |
64 | }; | |
65 | ||
66 | static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
67 | static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg); | |
68 | static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | |
69 | ||
3b7d697d | 70 | static const struct pci_device_id sis_pci_tbl[] = { |
1da177e4 LT |
71 | { PCI_VENDOR_ID_SI, 0x180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 }, |
72 | { PCI_VENDOR_ID_SI, 0x181, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 }, | |
f2c853bc | 73 | { PCI_VENDOR_ID_SI, 0x182, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 }, |
1da177e4 LT |
74 | { } /* terminate list */ |
75 | }; | |
76 | ||
77 | ||
78 | static struct pci_driver sis_pci_driver = { | |
79 | .name = DRV_NAME, | |
80 | .id_table = sis_pci_tbl, | |
81 | .probe = sis_init_one, | |
82 | .remove = ata_pci_remove_one, | |
83 | }; | |
84 | ||
193515d5 | 85 | static struct scsi_host_template sis_sht = { |
1da177e4 LT |
86 | .module = THIS_MODULE, |
87 | .name = DRV_NAME, | |
88 | .ioctl = ata_scsi_ioctl, | |
89 | .queuecommand = ata_scsi_queuecmd, | |
1da177e4 LT |
90 | .can_queue = ATA_DEF_QUEUE, |
91 | .this_id = ATA_SHT_THIS_ID, | |
92 | .sg_tablesize = ATA_MAX_PRD, | |
1da177e4 LT |
93 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
94 | .emulated = ATA_SHT_EMULATED, | |
95 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
96 | .proc_name = DRV_NAME, | |
97 | .dma_boundary = ATA_DMA_BOUNDARY, | |
98 | .slave_configure = ata_scsi_slave_config, | |
99 | .bios_param = ata_std_bios_param, | |
1da177e4 LT |
100 | }; |
101 | ||
057ace5e | 102 | static const struct ata_port_operations sis_ops = { |
1da177e4 LT |
103 | .port_disable = ata_port_disable, |
104 | .tf_load = ata_tf_load, | |
105 | .tf_read = ata_tf_read, | |
106 | .check_status = ata_check_status, | |
107 | .exec_command = ata_exec_command, | |
108 | .dev_select = ata_std_dev_select, | |
109 | .phy_reset = sata_phy_reset, | |
110 | .bmdma_setup = ata_bmdma_setup, | |
111 | .bmdma_start = ata_bmdma_start, | |
112 | .bmdma_stop = ata_bmdma_stop, | |
113 | .bmdma_status = ata_bmdma_status, | |
114 | .qc_prep = ata_qc_prep, | |
115 | .qc_issue = ata_qc_issue_prot, | |
116 | .eng_timeout = ata_eng_timeout, | |
117 | .irq_handler = ata_interrupt, | |
118 | .irq_clear = ata_bmdma_irq_clear, | |
119 | .scr_read = sis_scr_read, | |
120 | .scr_write = sis_scr_write, | |
121 | .port_start = ata_port_start, | |
122 | .port_stop = ata_port_stop, | |
aa8f0dc6 | 123 | .host_stop = ata_host_stop, |
1da177e4 LT |
124 | }; |
125 | ||
126 | static struct ata_port_info sis_port_info = { | |
127 | .sht = &sis_sht, | |
128 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_SATA_RESET | | |
129 | ATA_FLAG_NO_LEGACY, | |
130 | .pio_mask = 0x1f, | |
131 | .mwdma_mask = 0x7, | |
132 | .udma_mask = 0x7f, | |
133 | .port_ops = &sis_ops, | |
134 | }; | |
135 | ||
136 | ||
137 | MODULE_AUTHOR("Uwe Koziolek"); | |
138 | MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller"); | |
139 | MODULE_LICENSE("GPL"); | |
140 | MODULE_DEVICE_TABLE(pci, sis_pci_tbl); | |
141 | MODULE_VERSION(DRV_VERSION); | |
142 | ||
f2c853bc | 143 | static unsigned int get_scr_cfg_addr(unsigned int port_no, unsigned int sc_reg, int device) |
1da177e4 LT |
144 | { |
145 | unsigned int addr = SIS_SCR_BASE + (4 * sc_reg); | |
146 | ||
8add7885 | 147 | if (port_no) { |
f2c853bc AP |
148 | if (device == 0x182) |
149 | addr += SIS182_SATA1_OFS; | |
150 | else | |
151 | addr += SIS180_SATA1_OFS; | |
8add7885 JG |
152 | } |
153 | ||
1da177e4 LT |
154 | return addr; |
155 | } | |
156 | ||
157 | static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg) | |
158 | { | |
159 | struct pci_dev *pdev = to_pci_dev(ap->host_set->dev); | |
f2c853bc | 160 | unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, sc_reg, pdev->device); |
668e4bc7 | 161 | u32 val, val2 = 0; |
f2c853bc | 162 | u8 pmr; |
1da177e4 LT |
163 | |
164 | if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */ | |
165 | return 0xffffffff; | |
f2c853bc AP |
166 | |
167 | pci_read_config_byte(pdev, SIS_PMR, &pmr); | |
8add7885 | 168 | |
1da177e4 | 169 | pci_read_config_dword(pdev, cfg_addr, &val); |
f2c853bc | 170 | |
8add7885 | 171 | if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED)) |
f2c853bc AP |
172 | pci_read_config_dword(pdev, cfg_addr+0x10, &val2); |
173 | ||
174 | return val|val2; | |
1da177e4 LT |
175 | } |
176 | ||
177 | static void sis_scr_cfg_write (struct ata_port *ap, unsigned int scr, u32 val) | |
178 | { | |
179 | struct pci_dev *pdev = to_pci_dev(ap->host_set->dev); | |
f2c853bc AP |
180 | unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, scr, pdev->device); |
181 | u8 pmr; | |
1da177e4 LT |
182 | |
183 | if (scr == SCR_ERROR) /* doesn't exist in PCI cfg space */ | |
184 | return; | |
f2c853bc AP |
185 | |
186 | pci_read_config_byte(pdev, SIS_PMR, &pmr); | |
8add7885 | 187 | |
1da177e4 | 188 | pci_write_config_dword(pdev, cfg_addr, val); |
f2c853bc AP |
189 | |
190 | if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED)) | |
191 | pci_write_config_dword(pdev, cfg_addr+0x10, val); | |
1da177e4 LT |
192 | } |
193 | ||
194 | static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg) | |
195 | { | |
f2c853bc | 196 | struct pci_dev *pdev = to_pci_dev(ap->host_set->dev); |
8add7885 | 197 | u32 val, val2 = 0; |
f2c853bc AP |
198 | u8 pmr; |
199 | ||
1da177e4 LT |
200 | if (sc_reg > SCR_CONTROL) |
201 | return 0xffffffffU; | |
202 | ||
203 | if (ap->flags & SIS_FLAG_CFGSCR) | |
204 | return sis_scr_cfg_read(ap, sc_reg); | |
f2c853bc AP |
205 | |
206 | pci_read_config_byte(pdev, SIS_PMR, &pmr); | |
207 | ||
208 | val = inl(ap->ioaddr.scr_addr + (sc_reg * 4)); | |
209 | ||
210 | if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED)) | |
8add7885 | 211 | val2 = inl(ap->ioaddr.scr_addr + (sc_reg * 4) + 0x10); |
f2c853bc | 212 | |
8add7885 | 213 | return val | val2; |
1da177e4 LT |
214 | } |
215 | ||
216 | static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) | |
217 | { | |
f2c853bc AP |
218 | struct pci_dev *pdev = to_pci_dev(ap->host_set->dev); |
219 | u8 pmr; | |
220 | ||
1da177e4 LT |
221 | if (sc_reg > SCR_CONTROL) |
222 | return; | |
223 | ||
f2c853bc | 224 | pci_read_config_byte(pdev, SIS_PMR, &pmr); |
8add7885 | 225 | |
1da177e4 LT |
226 | if (ap->flags & SIS_FLAG_CFGSCR) |
227 | sis_scr_cfg_write(ap, sc_reg, val); | |
f2c853bc | 228 | else { |
1da177e4 | 229 | outl(val, ap->ioaddr.scr_addr + (sc_reg * 4)); |
f2c853bc AP |
230 | if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED)) |
231 | outl(val, ap->ioaddr.scr_addr + (sc_reg * 4)+0x10); | |
232 | } | |
1da177e4 LT |
233 | } |
234 | ||
1da177e4 LT |
235 | static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) |
236 | { | |
a9524a76 | 237 | static int printed_version; |
1da177e4 LT |
238 | struct ata_probe_ent *probe_ent = NULL; |
239 | int rc; | |
240 | u32 genctl; | |
241 | struct ata_port_info *ppi; | |
242 | int pci_dev_busy = 0; | |
f2c853bc AP |
243 | u8 pmr; |
244 | u8 port2_start; | |
1da177e4 | 245 | |
a9524a76 JG |
246 | if (!printed_version++) |
247 | dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); | |
248 | ||
1da177e4 LT |
249 | rc = pci_enable_device(pdev); |
250 | if (rc) | |
251 | return rc; | |
252 | ||
253 | rc = pci_request_regions(pdev, DRV_NAME); | |
254 | if (rc) { | |
255 | pci_dev_busy = 1; | |
256 | goto err_out; | |
257 | } | |
258 | ||
259 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
260 | if (rc) | |
261 | goto err_out_regions; | |
262 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
263 | if (rc) | |
264 | goto err_out_regions; | |
265 | ||
266 | ppi = &sis_port_info; | |
47a86593 | 267 | probe_ent = ata_pci_init_native_mode(pdev, &ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY); |
1da177e4 LT |
268 | if (!probe_ent) { |
269 | rc = -ENOMEM; | |
270 | goto err_out_regions; | |
271 | } | |
272 | ||
273 | /* check and see if the SCRs are in IO space or PCI cfg space */ | |
274 | pci_read_config_dword(pdev, SIS_GENCTL, &genctl); | |
275 | if ((genctl & GENCTL_IOMAPPED_SCR) == 0) | |
276 | probe_ent->host_flags |= SIS_FLAG_CFGSCR; | |
8a60a071 | 277 | |
1da177e4 LT |
278 | /* if hardware thinks SCRs are in IO space, but there are |
279 | * no IO resources assigned, change to PCI cfg space. | |
280 | */ | |
281 | if ((!(probe_ent->host_flags & SIS_FLAG_CFGSCR)) && | |
282 | ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) || | |
283 | (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) { | |
284 | genctl &= ~GENCTL_IOMAPPED_SCR; | |
285 | pci_write_config_dword(pdev, SIS_GENCTL, genctl); | |
286 | probe_ent->host_flags |= SIS_FLAG_CFGSCR; | |
287 | } | |
288 | ||
f2c853bc AP |
289 | pci_read_config_byte(pdev, SIS_PMR, &pmr); |
290 | if (ent->device != 0x182) { | |
291 | if ((pmr & SIS_PMR_COMBINED) == 0) { | |
a9524a76 JG |
292 | dev_printk(KERN_INFO, &pdev->dev, |
293 | "Detected SiS 180/181 chipset in SATA mode\n"); | |
39eb936c | 294 | port2_start = 64; |
f2c853bc AP |
295 | } |
296 | else { | |
a9524a76 JG |
297 | dev_printk(KERN_INFO, &pdev->dev, |
298 | "Detected SiS 180/181 chipset in combined mode\n"); | |
f2c853bc AP |
299 | port2_start=0; |
300 | } | |
301 | } | |
302 | else { | |
a9524a76 | 303 | dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182 chipset\n"); |
f2c853bc AP |
304 | port2_start = 0x20; |
305 | } | |
306 | ||
1da177e4 LT |
307 | if (!(probe_ent->host_flags & SIS_FLAG_CFGSCR)) { |
308 | probe_ent->port[0].scr_addr = | |
309 | pci_resource_start(pdev, SIS_SCR_PCI_BAR); | |
310 | probe_ent->port[1].scr_addr = | |
f2c853bc | 311 | pci_resource_start(pdev, SIS_SCR_PCI_BAR) + port2_start; |
1da177e4 LT |
312 | } |
313 | ||
314 | pci_set_master(pdev); | |
a04ce0ff | 315 | pci_intx(pdev, 1); |
1da177e4 LT |
316 | |
317 | /* FIXME: check ata_device_add return value */ | |
318 | ata_device_add(probe_ent); | |
319 | kfree(probe_ent); | |
320 | ||
321 | return 0; | |
322 | ||
323 | err_out_regions: | |
324 | pci_release_regions(pdev); | |
325 | ||
326 | err_out: | |
327 | if (!pci_dev_busy) | |
328 | pci_disable_device(pdev); | |
329 | return rc; | |
330 | ||
331 | } | |
332 | ||
333 | static int __init sis_init(void) | |
334 | { | |
335 | return pci_module_init(&sis_pci_driver); | |
336 | } | |
337 | ||
338 | static void __exit sis_exit(void) | |
339 | { | |
340 | pci_unregister_driver(&sis_pci_driver); | |
341 | } | |
342 | ||
343 | module_init(sis_init); | |
344 | module_exit(sis_exit); | |
345 |