Commit | Line | Data |
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5a25ba16 JG |
1 | /* |
2 | * SuperTrak EX Series Storage Controller driver for Linux | |
3 | * | |
bd5cd9cd | 4 | * Copyright (C) 2005-2009 Promise Technology Inc. |
5a25ba16 JG |
5 | * |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * Written By: | |
12 | * Ed Lin <promise_linux@promise.com> | |
13 | * | |
5a25ba16 JG |
14 | */ |
15 | ||
16 | #include <linux/init.h> | |
17 | #include <linux/errno.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/delay.h> | |
5a25ba16 JG |
20 | #include <linux/time.h> |
21 | #include <linux/pci.h> | |
22 | #include <linux/blkdev.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/types.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/spinlock.h> | |
27 | #include <asm/io.h> | |
28 | #include <asm/irq.h> | |
29 | #include <asm/byteorder.h> | |
30 | #include <scsi/scsi.h> | |
31 | #include <scsi/scsi_device.h> | |
32 | #include <scsi/scsi_cmnd.h> | |
33 | #include <scsi/scsi_host.h> | |
cf355883 | 34 | #include <scsi/scsi_tcq.h> |
c25da0af | 35 | #include <scsi/scsi_dbg.h> |
11002fbc | 36 | #include <scsi/scsi_eh.h> |
5a25ba16 JG |
37 | |
38 | #define DRV_NAME "stex" | |
bd5cd9cd ELP |
39 | #define ST_DRIVER_VERSION "4.6.0000.1" |
40 | #define ST_VER_MAJOR 4 | |
c25da0af | 41 | #define ST_VER_MINOR 6 |
5a25ba16 | 42 | #define ST_OEM 0 |
fb4f66be | 43 | #define ST_BUILD_VER 1 |
5a25ba16 JG |
44 | |
45 | enum { | |
46 | /* MU register offset */ | |
47 | IMR0 = 0x10, /* MU_INBOUND_MESSAGE_REG0 */ | |
48 | IMR1 = 0x14, /* MU_INBOUND_MESSAGE_REG1 */ | |
49 | OMR0 = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */ | |
50 | OMR1 = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */ | |
51 | IDBL = 0x20, /* MU_INBOUND_DOORBELL */ | |
52 | IIS = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */ | |
53 | IIM = 0x28, /* MU_INBOUND_INTERRUPT_MASK */ | |
54 | ODBL = 0x2c, /* MU_OUTBOUND_DOORBELL */ | |
55 | OIS = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */ | |
56 | OIM = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */ | |
57 | ||
58 | /* MU register value */ | |
59 | MU_INBOUND_DOORBELL_HANDSHAKE = 1, | |
60 | MU_INBOUND_DOORBELL_REQHEADCHANGED = 2, | |
61 | MU_INBOUND_DOORBELL_STATUSTAILCHANGED = 4, | |
62 | MU_INBOUND_DOORBELL_HMUSTOPPED = 8, | |
63 | MU_INBOUND_DOORBELL_RESET = 16, | |
64 | ||
65 | MU_OUTBOUND_DOORBELL_HANDSHAKE = 1, | |
66 | MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = 2, | |
67 | MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED = 4, | |
68 | MU_OUTBOUND_DOORBELL_BUSCHANGE = 8, | |
69 | MU_OUTBOUND_DOORBELL_HASEVENT = 16, | |
70 | ||
71 | /* MU status code */ | |
72 | MU_STATE_STARTING = 1, | |
73 | MU_STATE_FMU_READY_FOR_HANDSHAKE = 2, | |
74 | MU_STATE_SEND_HANDSHAKE_FRAME = 3, | |
75 | MU_STATE_STARTED = 4, | |
76 | MU_STATE_RESETTING = 5, | |
77 | ||
76fbf96f | 78 | MU_MAX_DELAY = 120, |
5a25ba16 | 79 | MU_HANDSHAKE_SIGNATURE = 0x55aaaa55, |
529e7a62 | 80 | MU_HANDSHAKE_SIGNATURE_HALF = 0x5a5a0000, |
76fbf96f | 81 | MU_HARD_RESET_WAIT = 30000, |
5a25ba16 JG |
82 | HMU_PARTNER_TYPE = 2, |
83 | ||
84 | /* firmware returned values */ | |
85 | SRB_STATUS_SUCCESS = 0x01, | |
86 | SRB_STATUS_ERROR = 0x04, | |
87 | SRB_STATUS_BUSY = 0x05, | |
88 | SRB_STATUS_INVALID_REQUEST = 0x06, | |
89 | SRB_STATUS_SELECTION_TIMEOUT = 0x0A, | |
90 | SRB_SEE_SENSE = 0x80, | |
91 | ||
92 | /* task attribute */ | |
93 | TASK_ATTRIBUTE_SIMPLE = 0x0, | |
94 | TASK_ATTRIBUTE_HEADOFQUEUE = 0x1, | |
95 | TASK_ATTRIBUTE_ORDERED = 0x2, | |
96 | TASK_ATTRIBUTE_ACA = 0x4, | |
97 | ||
98 | /* request count, etc. */ | |
99 | MU_MAX_REQUEST = 32, | |
5a25ba16 JG |
100 | |
101 | /* one message wasted, use MU_MAX_REQUEST+1 | |
102 | to handle MU_MAX_REQUEST messages */ | |
103 | MU_REQ_COUNT = (MU_MAX_REQUEST + 1), | |
104 | MU_STATUS_COUNT = (MU_MAX_REQUEST + 1), | |
105 | ||
7cfe99a5 | 106 | STEX_CDB_LENGTH = 16, |
5a25ba16 JG |
107 | REQ_VARIABLE_LEN = 1024, |
108 | STATUS_VAR_LEN = 128, | |
109 | ST_CAN_QUEUE = MU_MAX_REQUEST, | |
110 | ST_CMD_PER_LUN = MU_MAX_REQUEST, | |
111 | ST_MAX_SG = 32, | |
112 | ||
113 | /* sg flags */ | |
114 | SG_CF_EOT = 0x80, /* end of table */ | |
115 | SG_CF_64B = 0x40, /* 64 bit item */ | |
116 | SG_CF_HOST = 0x20, /* sg in host memory */ | |
7cfe99a5 ELP |
117 | MSG_DATA_DIR_ND = 0, |
118 | MSG_DATA_DIR_IN = 1, | |
119 | MSG_DATA_DIR_OUT = 2, | |
5a25ba16 | 120 | |
5a25ba16 JG |
121 | st_shasta = 0, |
122 | st_vsc = 1, | |
94e9108b EL |
123 | st_vsc1 = 2, |
124 | st_yosemite = 3, | |
62e5b3d8 | 125 | st_seq = 4, |
5a25ba16 JG |
126 | |
127 | PASSTHRU_REQ_TYPE = 0x00000001, | |
128 | PASSTHRU_REQ_NO_WAKEUP = 0x00000100, | |
7cfe99a5 | 129 | ST_INTERNAL_TIMEOUT = 180, |
5a25ba16 | 130 | |
fb4f66be EL |
131 | ST_TO_CMD = 0, |
132 | ST_FROM_CMD = 1, | |
133 | ||
5a25ba16 | 134 | /* vendor specific commands of Promise */ |
fb4f66be EL |
135 | MGT_CMD = 0xd8, |
136 | SINBAND_MGT_CMD = 0xd9, | |
5a25ba16 JG |
137 | ARRAY_CMD = 0xe0, |
138 | CONTROLLER_CMD = 0xe1, | |
139 | DEBUGGING_CMD = 0xe2, | |
140 | PASSTHRU_CMD = 0xe3, | |
141 | ||
142 | PASSTHRU_GET_ADAPTER = 0x05, | |
143 | PASSTHRU_GET_DRVVER = 0x10, | |
fb4f66be EL |
144 | |
145 | CTLR_CONFIG_CMD = 0x03, | |
146 | CTLR_SHUTDOWN = 0x0d, | |
147 | ||
5a25ba16 JG |
148 | CTLR_POWER_STATE_CHANGE = 0x0e, |
149 | CTLR_POWER_SAVING = 0x01, | |
150 | ||
151 | PASSTHRU_SIGNATURE = 0x4e415041, | |
fb4f66be | 152 | MGT_CMD_SIGNATURE = 0xba, |
5a25ba16 JG |
153 | |
154 | INQUIRY_EVPD = 0x01, | |
94e9108b EL |
155 | |
156 | ST_ADDITIONAL_MEM = 0x200000, | |
5a25ba16 JG |
157 | }; |
158 | ||
159 | struct st_sgitem { | |
160 | u8 ctrl; /* SG_CF_xxx */ | |
161 | u8 reserved[3]; | |
162 | __le32 count; | |
163 | __le32 addr; | |
164 | __le32 addr_hi; | |
165 | }; | |
166 | ||
167 | struct st_sgtable { | |
168 | __le16 sg_count; | |
169 | __le16 max_sg_count; | |
170 | __le32 sz_in_byte; | |
171 | struct st_sgitem table[ST_MAX_SG]; | |
172 | }; | |
173 | ||
174 | struct handshake_frame { | |
175 | __le32 rb_phy; /* request payload queue physical address */ | |
176 | __le32 rb_phy_hi; | |
177 | __le16 req_sz; /* size of each request payload */ | |
178 | __le16 req_cnt; /* count of reqs the buffer can hold */ | |
179 | __le16 status_sz; /* size of each status payload */ | |
180 | __le16 status_cnt; /* count of status the buffer can hold */ | |
181 | __le32 hosttime; /* seconds from Jan 1, 1970 (GMT) */ | |
182 | __le32 hosttime_hi; | |
183 | u8 partner_type; /* who sends this frame */ | |
184 | u8 reserved0[7]; | |
185 | __le32 partner_ver_major; | |
186 | __le32 partner_ver_minor; | |
187 | __le32 partner_ver_oem; | |
188 | __le32 partner_ver_build; | |
94e9108b EL |
189 | __le32 extra_offset; /* NEW */ |
190 | __le32 extra_size; /* NEW */ | |
191 | u32 reserved1[2]; | |
5a25ba16 JG |
192 | }; |
193 | ||
194 | struct req_msg { | |
195 | __le16 tag; | |
196 | u8 lun; | |
197 | u8 target; | |
198 | u8 task_attr; | |
199 | u8 task_manage; | |
7cfe99a5 | 200 | u8 data_dir; |
f903d7b7 | 201 | u8 payload_sz; /* payload size in 4-byte, not used */ |
5a25ba16 JG |
202 | u8 cdb[STEX_CDB_LENGTH]; |
203 | u8 variable[REQ_VARIABLE_LEN]; | |
204 | }; | |
205 | ||
206 | struct status_msg { | |
207 | __le16 tag; | |
208 | u8 lun; | |
209 | u8 target; | |
210 | u8 srb_status; | |
211 | u8 scsi_status; | |
212 | u8 reserved; | |
213 | u8 payload_sz; /* payload size in 4-byte */ | |
214 | u8 variable[STATUS_VAR_LEN]; | |
215 | }; | |
216 | ||
217 | struct ver_info { | |
218 | u32 major; | |
219 | u32 minor; | |
220 | u32 oem; | |
221 | u32 build; | |
222 | u32 reserved[2]; | |
223 | }; | |
224 | ||
225 | struct st_frame { | |
226 | u32 base[6]; | |
227 | u32 rom_addr; | |
228 | ||
229 | struct ver_info drv_ver; | |
230 | struct ver_info bios_ver; | |
231 | ||
232 | u32 bus; | |
233 | u32 slot; | |
234 | u32 irq_level; | |
235 | u32 irq_vec; | |
236 | u32 id; | |
237 | u32 subid; | |
238 | ||
239 | u32 dimm_size; | |
240 | u8 dimm_type; | |
241 | u8 reserved[3]; | |
242 | ||
243 | u32 channel; | |
244 | u32 reserved1; | |
245 | }; | |
246 | ||
247 | struct st_drvver { | |
248 | u32 major; | |
249 | u32 minor; | |
250 | u32 oem; | |
251 | u32 build; | |
252 | u32 signature[2]; | |
253 | u8 console_id; | |
254 | u8 host_no; | |
255 | u8 reserved0[2]; | |
256 | u32 reserved[3]; | |
257 | }; | |
258 | ||
259 | #define MU_REQ_BUFFER_SIZE (MU_REQ_COUNT * sizeof(struct req_msg)) | |
260 | #define MU_STATUS_BUFFER_SIZE (MU_STATUS_COUNT * sizeof(struct status_msg)) | |
261 | #define MU_BUFFER_SIZE (MU_REQ_BUFFER_SIZE + MU_STATUS_BUFFER_SIZE) | |
e8a091b3 | 262 | #define STEX_EXTRA_SIZE sizeof(struct st_frame) |
fb4f66be | 263 | #define STEX_BUFFER_SIZE (MU_BUFFER_SIZE + STEX_EXTRA_SIZE) |
5a25ba16 JG |
264 | |
265 | struct st_ccb { | |
266 | struct req_msg *req; | |
267 | struct scsi_cmnd *cmd; | |
268 | ||
269 | void *sense_buffer; | |
270 | unsigned int sense_bufflen; | |
271 | int sg_count; | |
272 | ||
273 | u32 req_type; | |
274 | u8 srb_status; | |
275 | u8 scsi_status; | |
276 | }; | |
277 | ||
278 | struct st_hba { | |
279 | void __iomem *mmio_base; /* iomapped PCI memory space */ | |
280 | void *dma_mem; | |
281 | dma_addr_t dma_handle; | |
94e9108b | 282 | size_t dma_size; |
5a25ba16 JG |
283 | |
284 | struct Scsi_Host *host; | |
285 | struct pci_dev *pdev; | |
286 | ||
5a25ba16 JG |
287 | u32 req_head; |
288 | u32 req_tail; | |
289 | u32 status_head; | |
290 | u32 status_tail; | |
291 | ||
292 | struct status_msg *status_buffer; | |
293 | void *copy_buffer; /* temp buffer for driver-handled commands */ | |
294 | struct st_ccb ccb[MU_MAX_REQUEST]; | |
295 | struct st_ccb *wait_ccb; | |
296 | wait_queue_head_t waitq; | |
297 | ||
298 | unsigned int mu_status; | |
299 | int out_req_cnt; | |
300 | ||
301 | unsigned int cardtype; | |
302 | }; | |
303 | ||
304 | static const char console_inq_page[] = | |
305 | { | |
306 | 0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30, | |
307 | 0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20, /* "Promise " */ | |
308 | 0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E, /* "RAID Con" */ | |
309 | 0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20, /* "sole " */ | |
310 | 0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20, /* "1.00 " */ | |
311 | 0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D, /* "SX/RSAF-" */ | |
312 | 0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20, /* "TE1.00 " */ | |
313 | 0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20 | |
314 | }; | |
315 | ||
316 | MODULE_AUTHOR("Ed Lin"); | |
317 | MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers"); | |
318 | MODULE_LICENSE("GPL"); | |
319 | MODULE_VERSION(ST_DRIVER_VERSION); | |
320 | ||
321 | static void stex_gettime(__le32 *time) | |
322 | { | |
323 | struct timeval tv; | |
5a25ba16 | 324 | |
7cfe99a5 | 325 | do_gettimeofday(&tv); |
5a25ba16 JG |
326 | *time = cpu_to_le32(tv.tv_sec & 0xffffffff); |
327 | *(time + 1) = cpu_to_le32((tv.tv_sec >> 16) >> 16); | |
328 | } | |
329 | ||
5a25ba16 JG |
330 | static struct status_msg *stex_get_status(struct st_hba *hba) |
331 | { | |
332 | struct status_msg *status = | |
333 | hba->status_buffer + hba->status_tail; | |
334 | ||
335 | ++hba->status_tail; | |
336 | hba->status_tail %= MU_STATUS_COUNT; | |
337 | ||
338 | return status; | |
339 | } | |
340 | ||
5a25ba16 JG |
341 | static void stex_invalid_field(struct scsi_cmnd *cmd, |
342 | void (*done)(struct scsi_cmnd *)) | |
343 | { | |
11002fbc FT |
344 | cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION; |
345 | ||
7cfe99a5 | 346 | /* "Invalid field in cdb" */ |
11002fbc FT |
347 | scsi_build_sense_buffer(0, cmd->sense_buffer, ILLEGAL_REQUEST, 0x24, |
348 | 0x0); | |
5a25ba16 JG |
349 | done(cmd); |
350 | } | |
351 | ||
352 | static struct req_msg *stex_alloc_req(struct st_hba *hba) | |
353 | { | |
354 | struct req_msg *req = ((struct req_msg *)hba->dma_mem) + | |
355 | hba->req_head; | |
356 | ||
357 | ++hba->req_head; | |
358 | hba->req_head %= MU_REQ_COUNT; | |
359 | ||
360 | return req; | |
361 | } | |
362 | ||
363 | static int stex_map_sg(struct st_hba *hba, | |
364 | struct req_msg *req, struct st_ccb *ccb) | |
365 | { | |
5a25ba16 | 366 | struct scsi_cmnd *cmd; |
d5587d5d | 367 | struct scatterlist *sg; |
5a25ba16 | 368 | struct st_sgtable *dst; |
d5587d5d | 369 | int i, nseg; |
5a25ba16 JG |
370 | |
371 | cmd = ccb->cmd; | |
372 | dst = (struct st_sgtable *)req->variable; | |
373 | dst->max_sg_count = cpu_to_le16(ST_MAX_SG); | |
d5587d5d | 374 | dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd)); |
5a25ba16 | 375 | |
d5587d5d FT |
376 | nseg = scsi_dma_map(cmd); |
377 | if (nseg < 0) | |
378 | return -EIO; | |
379 | if (nseg) { | |
380 | ccb->sg_count = nseg; | |
381 | dst->sg_count = cpu_to_le16((u16)nseg); | |
5a25ba16 | 382 | |
d5587d5d FT |
383 | scsi_for_each_sg(cmd, sg, nseg, i) { |
384 | dst->table[i].count = cpu_to_le32((u32)sg_dma_len(sg)); | |
5a25ba16 | 385 | dst->table[i].addr = |
d5587d5d | 386 | cpu_to_le32(sg_dma_address(sg) & 0xffffffff); |
5a25ba16 | 387 | dst->table[i].addr_hi = |
d5587d5d | 388 | cpu_to_le32((sg_dma_address(sg) >> 16) >> 16); |
5a25ba16 JG |
389 | dst->table[i].ctrl = SG_CF_64B | SG_CF_HOST; |
390 | } | |
391 | dst->table[--i].ctrl |= SG_CF_EOT; | |
5a25ba16 JG |
392 | } |
393 | ||
5a25ba16 JG |
394 | return 0; |
395 | } | |
396 | ||
5a25ba16 JG |
397 | static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb) |
398 | { | |
399 | struct st_frame *p; | |
400 | size_t count = sizeof(struct st_frame); | |
401 | ||
402 | p = hba->copy_buffer; | |
31fe47d4 | 403 | count = scsi_sg_copy_to_buffer(ccb->cmd, p, count); |
5a25ba16 JG |
404 | memset(p->base, 0, sizeof(u32)*6); |
405 | *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0); | |
406 | p->rom_addr = 0; | |
407 | ||
408 | p->drv_ver.major = ST_VER_MAJOR; | |
409 | p->drv_ver.minor = ST_VER_MINOR; | |
410 | p->drv_ver.oem = ST_OEM; | |
411 | p->drv_ver.build = ST_BUILD_VER; | |
412 | ||
413 | p->bus = hba->pdev->bus->number; | |
414 | p->slot = hba->pdev->devfn; | |
415 | p->irq_level = 0; | |
416 | p->irq_vec = hba->pdev->irq; | |
417 | p->id = hba->pdev->vendor << 16 | hba->pdev->device; | |
418 | p->subid = | |
419 | hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device; | |
420 | ||
31fe47d4 | 421 | count = scsi_sg_copy_from_buffer(ccb->cmd, p, count); |
5a25ba16 JG |
422 | } |
423 | ||
424 | static void | |
425 | stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag) | |
426 | { | |
427 | req->tag = cpu_to_le16(tag); | |
428 | req->task_attr = TASK_ATTRIBUTE_SIMPLE; | |
429 | req->task_manage = 0; /* not supported yet */ | |
5a25ba16 JG |
430 | |
431 | hba->ccb[tag].req = req; | |
432 | hba->out_req_cnt++; | |
433 | ||
434 | writel(hba->req_head, hba->mmio_base + IMR0); | |
435 | writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL); | |
436 | readl(hba->mmio_base + IDBL); /* flush */ | |
437 | } | |
438 | ||
cf355883 EL |
439 | static int |
440 | stex_slave_alloc(struct scsi_device *sdev) | |
441 | { | |
442 | /* Cheat: usually extracted from Inquiry data */ | |
443 | sdev->tagged_supported = 1; | |
444 | ||
5d90027f | 445 | scsi_activate_tcq(sdev, ST_CMD_PER_LUN); |
cf355883 EL |
446 | |
447 | return 0; | |
448 | } | |
449 | ||
5a25ba16 JG |
450 | static int |
451 | stex_slave_config(struct scsi_device *sdev) | |
452 | { | |
453 | sdev->use_10_for_rw = 1; | |
454 | sdev->use_10_for_ms = 1; | |
dc5c49bf | 455 | blk_queue_rq_timeout(sdev->request_queue, 60 * HZ); |
cf355883 EL |
456 | sdev->tagged_supported = 1; |
457 | ||
5a25ba16 JG |
458 | return 0; |
459 | } | |
460 | ||
461 | static void | |
462 | stex_slave_destroy(struct scsi_device *sdev) | |
463 | { | |
cf355883 | 464 | scsi_deactivate_tcq(sdev, 1); |
5a25ba16 JG |
465 | } |
466 | ||
467 | static int | |
468 | stex_queuecommand(struct scsi_cmnd *cmd, void (* done)(struct scsi_cmnd *)) | |
469 | { | |
470 | struct st_hba *hba; | |
471 | struct Scsi_Host *host; | |
472 | unsigned int id,lun; | |
473 | struct req_msg *req; | |
474 | u16 tag; | |
7cfe99a5 | 475 | |
5a25ba16 JG |
476 | host = cmd->device->host; |
477 | id = cmd->device->id; | |
e0b2e597 | 478 | lun = cmd->device->lun; |
5a25ba16 JG |
479 | hba = (struct st_hba *) &host->hostdata[0]; |
480 | ||
481 | switch (cmd->cmnd[0]) { | |
482 | case MODE_SENSE_10: | |
483 | { | |
484 | static char ms10_caching_page[12] = | |
485 | { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 }; | |
486 | unsigned char page; | |
7cfe99a5 | 487 | |
5a25ba16 JG |
488 | page = cmd->cmnd[2] & 0x3f; |
489 | if (page == 0x8 || page == 0x3f) { | |
31fe47d4 FT |
490 | scsi_sg_copy_from_buffer(cmd, ms10_caching_page, |
491 | sizeof(ms10_caching_page)); | |
5a25ba16 JG |
492 | cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8; |
493 | done(cmd); | |
494 | } else | |
495 | stex_invalid_field(cmd, done); | |
496 | return 0; | |
497 | } | |
e0b2e597 EL |
498 | case REPORT_LUNS: |
499 | /* | |
500 | * The shasta firmware does not report actual luns in the | |
501 | * target, so fail the command to force sequential lun scan. | |
502 | * Also, the console device does not support this command. | |
503 | */ | |
504 | if (hba->cardtype == st_shasta || id == host->max_id - 1) { | |
505 | stex_invalid_field(cmd, done); | |
506 | return 0; | |
507 | } | |
508 | break; | |
d116a7bc EL |
509 | case TEST_UNIT_READY: |
510 | if (id == host->max_id - 1) { | |
511 | cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8; | |
512 | done(cmd); | |
513 | return 0; | |
514 | } | |
515 | break; | |
5a25ba16 | 516 | case INQUIRY: |
e0b2e597 | 517 | if (id != host->max_id - 1) |
5a25ba16 JG |
518 | break; |
519 | if (lun == 0 && (cmd->cmnd[1] & INQUIRY_EVPD) == 0) { | |
31fe47d4 FT |
520 | scsi_sg_copy_from_buffer(cmd, (void *)console_inq_page, |
521 | sizeof(console_inq_page)); | |
5a25ba16 JG |
522 | cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8; |
523 | done(cmd); | |
524 | } else | |
525 | stex_invalid_field(cmd, done); | |
526 | return 0; | |
527 | case PASSTHRU_CMD: | |
528 | if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) { | |
529 | struct st_drvver ver; | |
26106e3c | 530 | size_t cp_len = sizeof(ver); |
7cfe99a5 | 531 | |
5a25ba16 JG |
532 | ver.major = ST_VER_MAJOR; |
533 | ver.minor = ST_VER_MINOR; | |
534 | ver.oem = ST_OEM; | |
535 | ver.build = ST_BUILD_VER; | |
536 | ver.signature[0] = PASSTHRU_SIGNATURE; | |
e0b2e597 | 537 | ver.console_id = host->max_id - 1; |
5a25ba16 | 538 | ver.host_no = hba->host->host_no; |
31fe47d4 | 539 | cp_len = scsi_sg_copy_from_buffer(cmd, &ver, cp_len); |
26106e3c | 540 | cmd->result = sizeof(ver) == cp_len ? |
5a25ba16 JG |
541 | DID_OK << 16 | COMMAND_COMPLETE << 8 : |
542 | DID_ERROR << 16 | COMMAND_COMPLETE << 8; | |
543 | done(cmd); | |
544 | return 0; | |
545 | } | |
546 | default: | |
547 | break; | |
548 | } | |
549 | ||
550 | cmd->scsi_done = done; | |
551 | ||
cf355883 EL |
552 | tag = cmd->request->tag; |
553 | ||
554 | if (unlikely(tag >= host->can_queue)) | |
5a25ba16 JG |
555 | return SCSI_MLQUEUE_HOST_BUSY; |
556 | ||
557 | req = stex_alloc_req(hba); | |
fb4f66be | 558 | |
e0b2e597 EL |
559 | req->lun = lun; |
560 | req->target = id; | |
5a25ba16 JG |
561 | |
562 | /* cdb */ | |
563 | memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH); | |
564 | ||
7cfe99a5 ELP |
565 | if (cmd->sc_data_direction == DMA_FROM_DEVICE) |
566 | req->data_dir = MSG_DATA_DIR_IN; | |
567 | else if (cmd->sc_data_direction == DMA_TO_DEVICE) | |
568 | req->data_dir = MSG_DATA_DIR_OUT; | |
569 | else | |
570 | req->data_dir = MSG_DATA_DIR_ND; | |
571 | ||
5a25ba16 JG |
572 | hba->ccb[tag].cmd = cmd; |
573 | hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE; | |
574 | hba->ccb[tag].sense_buffer = cmd->sense_buffer; | |
575 | hba->ccb[tag].req_type = 0; | |
576 | ||
577 | if (cmd->sc_data_direction != DMA_NONE) | |
578 | stex_map_sg(hba, req, &hba->ccb[tag]); | |
579 | ||
580 | stex_send_cmd(hba, req, tag); | |
581 | return 0; | |
582 | } | |
583 | ||
5a25ba16 JG |
584 | static void stex_scsi_done(struct st_ccb *ccb) |
585 | { | |
586 | struct scsi_cmnd *cmd = ccb->cmd; | |
587 | int result; | |
588 | ||
589 | if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) { | |
590 | result = ccb->scsi_status; | |
591 | switch (ccb->scsi_status) { | |
592 | case SAM_STAT_GOOD: | |
593 | result |= DID_OK << 16 | COMMAND_COMPLETE << 8; | |
594 | break; | |
595 | case SAM_STAT_CHECK_CONDITION: | |
596 | result |= DRIVER_SENSE << 24; | |
597 | break; | |
598 | case SAM_STAT_BUSY: | |
599 | result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8; | |
600 | break; | |
601 | default: | |
602 | result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8; | |
603 | break; | |
604 | } | |
605 | } | |
606 | else if (ccb->srb_status & SRB_SEE_SENSE) | |
607 | result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION; | |
608 | else switch (ccb->srb_status) { | |
609 | case SRB_STATUS_SELECTION_TIMEOUT: | |
610 | result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8; | |
611 | break; | |
612 | case SRB_STATUS_BUSY: | |
613 | result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8; | |
614 | break; | |
615 | case SRB_STATUS_INVALID_REQUEST: | |
616 | case SRB_STATUS_ERROR: | |
617 | default: | |
618 | result = DID_ERROR << 16 | COMMAND_COMPLETE << 8; | |
619 | break; | |
620 | } | |
621 | ||
622 | cmd->result = result; | |
623 | cmd->scsi_done(cmd); | |
624 | } | |
625 | ||
626 | static void stex_copy_data(struct st_ccb *ccb, | |
627 | struct status_msg *resp, unsigned int variable) | |
628 | { | |
629 | size_t count = variable; | |
7cfe99a5 | 630 | |
5a25ba16 JG |
631 | if (resp->scsi_status != SAM_STAT_GOOD) { |
632 | if (ccb->sense_buffer != NULL) | |
633 | memcpy(ccb->sense_buffer, resp->variable, | |
634 | min(variable, ccb->sense_bufflen)); | |
635 | return; | |
636 | } | |
637 | ||
638 | if (ccb->cmd == NULL) | |
639 | return; | |
31fe47d4 | 640 | count = scsi_sg_copy_from_buffer(ccb->cmd, resp->variable, count); |
fb4f66be EL |
641 | } |
642 | ||
643 | static void stex_ys_commands(struct st_hba *hba, | |
644 | struct st_ccb *ccb, struct status_msg *resp) | |
645 | { | |
fb4f66be EL |
646 | if (ccb->cmd->cmnd[0] == MGT_CMD && |
647 | resp->scsi_status != SAM_STAT_CHECK_CONDITION) { | |
968a5763 EL |
648 | scsi_set_resid(ccb->cmd, scsi_bufflen(ccb->cmd) - |
649 | le32_to_cpu(*(__le32 *)&resp->variable[0])); | |
fb4f66be | 650 | } |
5a25ba16 JG |
651 | } |
652 | ||
653 | static void stex_mu_intr(struct st_hba *hba, u32 doorbell) | |
654 | { | |
655 | void __iomem *base = hba->mmio_base; | |
656 | struct status_msg *resp; | |
657 | struct st_ccb *ccb; | |
658 | unsigned int size; | |
659 | u16 tag; | |
660 | ||
661 | if (!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED)) | |
662 | return; | |
663 | ||
664 | /* status payloads */ | |
665 | hba->status_head = readl(base + OMR1); | |
666 | if (unlikely(hba->status_head >= MU_STATUS_COUNT)) { | |
667 | printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n", | |
668 | pci_name(hba->pdev)); | |
669 | return; | |
670 | } | |
671 | ||
fb4f66be EL |
672 | /* |
673 | * it's not a valid status payload if: | |
674 | * 1. there are no pending requests(e.g. during init stage) | |
675 | * 2. there are some pending requests, but the controller is in | |
676 | * reset status, and its type is not st_yosemite | |
677 | * firmware of st_yosemite in reset status will return pending requests | |
678 | * to driver, so we allow it to pass | |
679 | */ | |
680 | if (unlikely(hba->out_req_cnt <= 0 || | |
681 | (hba->mu_status == MU_STATE_RESETTING && | |
682 | hba->cardtype != st_yosemite))) { | |
5a25ba16 JG |
683 | hba->status_tail = hba->status_head; |
684 | goto update_status; | |
685 | } | |
686 | ||
687 | while (hba->status_tail != hba->status_head) { | |
688 | resp = stex_get_status(hba); | |
689 | tag = le16_to_cpu(resp->tag); | |
cf355883 | 690 | if (unlikely(tag >= hba->host->can_queue)) { |
5a25ba16 JG |
691 | printk(KERN_WARNING DRV_NAME |
692 | "(%s): invalid tag\n", pci_name(hba->pdev)); | |
693 | continue; | |
694 | } | |
5a25ba16 | 695 | |
5a25ba16 JG |
696 | ccb = &hba->ccb[tag]; |
697 | if (hba->wait_ccb == ccb) | |
698 | hba->wait_ccb = NULL; | |
699 | if (unlikely(ccb->req == NULL)) { | |
700 | printk(KERN_WARNING DRV_NAME | |
701 | "(%s): lagging req\n", pci_name(hba->pdev)); | |
fb4f66be | 702 | hba->out_req_cnt--; |
5a25ba16 JG |
703 | continue; |
704 | } | |
705 | ||
706 | size = resp->payload_sz * sizeof(u32); /* payload size */ | |
707 | if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN || | |
708 | size > sizeof(*resp))) { | |
709 | printk(KERN_WARNING DRV_NAME "(%s): bad status size\n", | |
710 | pci_name(hba->pdev)); | |
711 | } else { | |
712 | size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */ | |
713 | if (size) | |
714 | stex_copy_data(ccb, resp, size); | |
715 | } | |
716 | ||
dd48ebf7 | 717 | ccb->req = NULL; |
5a25ba16 JG |
718 | ccb->srb_status = resp->srb_status; |
719 | ccb->scsi_status = resp->scsi_status; | |
720 | ||
cf355883 | 721 | if (likely(ccb->cmd != NULL)) { |
fb4f66be EL |
722 | if (hba->cardtype == st_yosemite) |
723 | stex_ys_commands(hba, ccb, resp); | |
724 | ||
cf355883 EL |
725 | if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD && |
726 | ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER)) | |
727 | stex_controller_info(hba, ccb); | |
fb4f66be | 728 | |
d5587d5d | 729 | scsi_dma_unmap(ccb->cmd); |
cf355883 EL |
730 | stex_scsi_done(ccb); |
731 | hba->out_req_cnt--; | |
732 | } else if (ccb->req_type & PASSTHRU_REQ_TYPE) { | |
733 | hba->out_req_cnt--; | |
5a25ba16 JG |
734 | if (ccb->req_type & PASSTHRU_REQ_NO_WAKEUP) { |
735 | ccb->req_type = 0; | |
736 | continue; | |
737 | } | |
738 | ccb->req_type = 0; | |
739 | if (waitqueue_active(&hba->waitq)) | |
740 | wake_up(&hba->waitq); | |
5a25ba16 | 741 | } |
5a25ba16 JG |
742 | } |
743 | ||
744 | update_status: | |
745 | writel(hba->status_head, base + IMR1); | |
746 | readl(base + IMR1); /* flush */ | |
747 | } | |
748 | ||
7d12e780 | 749 | static irqreturn_t stex_intr(int irq, void *__hba) |
5a25ba16 JG |
750 | { |
751 | struct st_hba *hba = __hba; | |
752 | void __iomem *base = hba->mmio_base; | |
753 | u32 data; | |
754 | unsigned long flags; | |
755 | int handled = 0; | |
756 | ||
757 | spin_lock_irqsave(hba->host->host_lock, flags); | |
758 | ||
759 | data = readl(base + ODBL); | |
760 | ||
761 | if (data && data != 0xffffffff) { | |
762 | /* clear the interrupt */ | |
763 | writel(data, base + ODBL); | |
764 | readl(base + ODBL); /* flush */ | |
765 | stex_mu_intr(hba, data); | |
766 | handled = 1; | |
767 | } | |
768 | ||
769 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
770 | ||
771 | return IRQ_RETVAL(handled); | |
772 | } | |
773 | ||
774 | static int stex_handshake(struct st_hba *hba) | |
775 | { | |
776 | void __iomem *base = hba->mmio_base; | |
777 | struct handshake_frame *h; | |
778 | dma_addr_t status_phys; | |
529e7a62 | 779 | u32 data; |
76fbf96f | 780 | unsigned long before; |
5a25ba16 JG |
781 | |
782 | if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) { | |
783 | writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL); | |
784 | readl(base + IDBL); | |
76fbf96f EL |
785 | before = jiffies; |
786 | while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) { | |
787 | if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) { | |
788 | printk(KERN_ERR DRV_NAME | |
789 | "(%s): no handshake signature\n", | |
790 | pci_name(hba->pdev)); | |
791 | return -1; | |
792 | } | |
5a25ba16 JG |
793 | rmb(); |
794 | msleep(1); | |
795 | } | |
5a25ba16 JG |
796 | } |
797 | ||
798 | udelay(10); | |
799 | ||
529e7a62 EL |
800 | data = readl(base + OMR1); |
801 | if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) { | |
802 | data &= 0x0000ffff; | |
803 | if (hba->host->can_queue > data) | |
804 | hba->host->can_queue = data; | |
805 | } | |
806 | ||
5a25ba16 JG |
807 | h = (struct handshake_frame *)(hba->dma_mem + MU_REQ_BUFFER_SIZE); |
808 | h->rb_phy = cpu_to_le32(hba->dma_handle); | |
809 | h->rb_phy_hi = cpu_to_le32((hba->dma_handle >> 16) >> 16); | |
810 | h->req_sz = cpu_to_le16(sizeof(struct req_msg)); | |
811 | h->req_cnt = cpu_to_le16(MU_REQ_COUNT); | |
812 | h->status_sz = cpu_to_le16(sizeof(struct status_msg)); | |
813 | h->status_cnt = cpu_to_le16(MU_STATUS_COUNT); | |
814 | stex_gettime(&h->hosttime); | |
815 | h->partner_type = HMU_PARTNER_TYPE; | |
94e9108b EL |
816 | if (hba->dma_size > STEX_BUFFER_SIZE) { |
817 | h->extra_offset = cpu_to_le32(STEX_BUFFER_SIZE); | |
818 | h->extra_size = cpu_to_le32(ST_ADDITIONAL_MEM); | |
819 | } else | |
820 | h->extra_offset = h->extra_size = 0; | |
5a25ba16 JG |
821 | |
822 | status_phys = hba->dma_handle + MU_REQ_BUFFER_SIZE; | |
823 | writel(status_phys, base + IMR0); | |
824 | readl(base + IMR0); | |
825 | writel((status_phys >> 16) >> 16, base + IMR1); | |
826 | readl(base + IMR1); | |
827 | ||
828 | writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */ | |
829 | readl(base + OMR0); | |
830 | writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL); | |
831 | readl(base + IDBL); /* flush */ | |
832 | ||
833 | udelay(10); | |
76fbf96f EL |
834 | before = jiffies; |
835 | while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) { | |
836 | if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) { | |
837 | printk(KERN_ERR DRV_NAME | |
838 | "(%s): no signature after handshake frame\n", | |
839 | pci_name(hba->pdev)); | |
840 | return -1; | |
841 | } | |
5a25ba16 JG |
842 | rmb(); |
843 | msleep(1); | |
844 | } | |
845 | ||
5a25ba16 JG |
846 | writel(0, base + IMR0); |
847 | readl(base + IMR0); | |
848 | writel(0, base + OMR0); | |
849 | readl(base + OMR0); | |
850 | writel(0, base + IMR1); | |
851 | readl(base + IMR1); | |
852 | writel(0, base + OMR1); | |
853 | readl(base + OMR1); /* flush */ | |
854 | hba->mu_status = MU_STATE_STARTED; | |
855 | return 0; | |
856 | } | |
857 | ||
858 | static int stex_abort(struct scsi_cmnd *cmd) | |
859 | { | |
860 | struct Scsi_Host *host = cmd->device->host; | |
861 | struct st_hba *hba = (struct st_hba *)host->hostdata; | |
cf355883 | 862 | u16 tag = cmd->request->tag; |
5a25ba16 JG |
863 | void __iomem *base; |
864 | u32 data; | |
865 | int result = SUCCESS; | |
866 | unsigned long flags; | |
c25da0af EL |
867 | |
868 | printk(KERN_INFO DRV_NAME | |
869 | "(%s): aborting command\n", pci_name(hba->pdev)); | |
870 | scsi_print_command(cmd); | |
871 | ||
5a25ba16 JG |
872 | base = hba->mmio_base; |
873 | spin_lock_irqsave(host->host_lock, flags); | |
cf355883 EL |
874 | if (tag < host->can_queue && hba->ccb[tag].cmd == cmd) |
875 | hba->wait_ccb = &hba->ccb[tag]; | |
876 | else { | |
877 | for (tag = 0; tag < host->can_queue; tag++) | |
878 | if (hba->ccb[tag].cmd == cmd) { | |
879 | hba->wait_ccb = &hba->ccb[tag]; | |
880 | break; | |
881 | } | |
882 | if (tag >= host->can_queue) | |
883 | goto out; | |
884 | } | |
5a25ba16 JG |
885 | |
886 | data = readl(base + ODBL); | |
887 | if (data == 0 || data == 0xffffffff) | |
888 | goto fail_out; | |
889 | ||
890 | writel(data, base + ODBL); | |
891 | readl(base + ODBL); /* flush */ | |
892 | ||
893 | stex_mu_intr(hba, data); | |
894 | ||
895 | if (hba->wait_ccb == NULL) { | |
896 | printk(KERN_WARNING DRV_NAME | |
897 | "(%s): lost interrupt\n", pci_name(hba->pdev)); | |
898 | goto out; | |
899 | } | |
900 | ||
901 | fail_out: | |
d5587d5d | 902 | scsi_dma_unmap(cmd); |
5a25ba16 JG |
903 | hba->wait_ccb->req = NULL; /* nullify the req's future return */ |
904 | hba->wait_ccb = NULL; | |
905 | result = FAILED; | |
906 | out: | |
907 | spin_unlock_irqrestore(host->host_lock, flags); | |
908 | return result; | |
909 | } | |
910 | ||
911 | static void stex_hard_reset(struct st_hba *hba) | |
912 | { | |
913 | struct pci_bus *bus; | |
914 | int i; | |
915 | u16 pci_cmd; | |
916 | u8 pci_bctl; | |
917 | ||
918 | for (i = 0; i < 16; i++) | |
919 | pci_read_config_dword(hba->pdev, i * 4, | |
920 | &hba->pdev->saved_config_space[i]); | |
921 | ||
922 | /* Reset secondary bus. Our controller(MU/ATU) is the only device on | |
923 | secondary bus. Consult Intel 80331/3 developer's manual for detail */ | |
924 | bus = hba->pdev->bus; | |
925 | pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl); | |
926 | pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET; | |
927 | pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl); | |
69f4a513 EL |
928 | |
929 | /* | |
930 | * 1 ms may be enough for 8-port controllers. But 16-port controllers | |
931 | * require more time to finish bus reset. Use 100 ms here for safety | |
932 | */ | |
933 | msleep(100); | |
5a25ba16 JG |
934 | pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET; |
935 | pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl); | |
936 | ||
76fbf96f | 937 | for (i = 0; i < MU_HARD_RESET_WAIT; i++) { |
5a25ba16 | 938 | pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd); |
47c4f997 | 939 | if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER)) |
5a25ba16 JG |
940 | break; |
941 | msleep(1); | |
942 | } | |
943 | ||
944 | ssleep(5); | |
945 | for (i = 0; i < 16; i++) | |
946 | pci_write_config_dword(hba->pdev, i * 4, | |
947 | hba->pdev->saved_config_space[i]); | |
948 | } | |
949 | ||
950 | static int stex_reset(struct scsi_cmnd *cmd) | |
951 | { | |
952 | struct st_hba *hba; | |
953 | unsigned long flags; | |
fb4f66be | 954 | unsigned long before; |
7cfe99a5 | 955 | |
5a25ba16 JG |
956 | hba = (struct st_hba *) &cmd->device->host->hostdata[0]; |
957 | ||
c25da0af EL |
958 | printk(KERN_INFO DRV_NAME |
959 | "(%s): resetting host\n", pci_name(hba->pdev)); | |
960 | scsi_print_command(cmd); | |
961 | ||
5a25ba16 JG |
962 | hba->mu_status = MU_STATE_RESETTING; |
963 | ||
964 | if (hba->cardtype == st_shasta) | |
965 | stex_hard_reset(hba); | |
966 | ||
fb4f66be EL |
967 | if (hba->cardtype != st_yosemite) { |
968 | if (stex_handshake(hba)) { | |
969 | printk(KERN_WARNING DRV_NAME | |
970 | "(%s): resetting: handshake failed\n", | |
971 | pci_name(hba->pdev)); | |
972 | return FAILED; | |
973 | } | |
974 | spin_lock_irqsave(hba->host->host_lock, flags); | |
975 | hba->req_head = 0; | |
976 | hba->req_tail = 0; | |
977 | hba->status_head = 0; | |
978 | hba->status_tail = 0; | |
979 | hba->out_req_cnt = 0; | |
980 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
981 | return SUCCESS; | |
5a25ba16 | 982 | } |
5a25ba16 | 983 | |
fb4f66be EL |
984 | /* st_yosemite */ |
985 | writel(MU_INBOUND_DOORBELL_RESET, hba->mmio_base + IDBL); | |
986 | readl(hba->mmio_base + IDBL); /* flush */ | |
987 | before = jiffies; | |
988 | while (hba->out_req_cnt > 0) { | |
989 | if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) { | |
990 | printk(KERN_WARNING DRV_NAME | |
991 | "(%s): reset timeout\n", pci_name(hba->pdev)); | |
992 | return FAILED; | |
993 | } | |
994 | msleep(1); | |
995 | } | |
996 | ||
997 | hba->mu_status = MU_STATE_STARTED; | |
5a25ba16 JG |
998 | return SUCCESS; |
999 | } | |
1000 | ||
1001 | static int stex_biosparam(struct scsi_device *sdev, | |
1002 | struct block_device *bdev, sector_t capacity, int geom[]) | |
1003 | { | |
b4b8bed1 | 1004 | int heads = 255, sectors = 63; |
5a25ba16 JG |
1005 | |
1006 | if (capacity < 0x200000) { | |
1007 | heads = 64; | |
1008 | sectors = 32; | |
1009 | } | |
1010 | ||
b4b8bed1 | 1011 | sector_div(capacity, heads * sectors); |
5a25ba16 JG |
1012 | |
1013 | geom[0] = heads; | |
1014 | geom[1] = sectors; | |
b4b8bed1 | 1015 | geom[2] = capacity; |
5a25ba16 JG |
1016 | |
1017 | return 0; | |
1018 | } | |
1019 | ||
1020 | static struct scsi_host_template driver_template = { | |
1021 | .module = THIS_MODULE, | |
1022 | .name = DRV_NAME, | |
1023 | .proc_name = DRV_NAME, | |
1024 | .bios_param = stex_biosparam, | |
1025 | .queuecommand = stex_queuecommand, | |
cf355883 | 1026 | .slave_alloc = stex_slave_alloc, |
5a25ba16 JG |
1027 | .slave_configure = stex_slave_config, |
1028 | .slave_destroy = stex_slave_destroy, | |
1029 | .eh_abort_handler = stex_abort, | |
1030 | .eh_host_reset_handler = stex_reset, | |
1031 | .can_queue = ST_CAN_QUEUE, | |
1032 | .this_id = -1, | |
1033 | .sg_tablesize = ST_MAX_SG, | |
1034 | .cmd_per_lun = ST_CMD_PER_LUN, | |
1035 | }; | |
1036 | ||
1037 | static int stex_set_dma_mask(struct pci_dev * pdev) | |
1038 | { | |
1039 | int ret; | |
7cfe99a5 | 1040 | |
5a25ba16 JG |
1041 | if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) |
1042 | && !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) | |
1043 | return 0; | |
1044 | ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
1045 | if (!ret) | |
1046 | ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
1047 | return ret; | |
1048 | } | |
1049 | ||
1050 | static int __devinit | |
1051 | stex_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |
1052 | { | |
1053 | struct st_hba *hba; | |
1054 | struct Scsi_Host *host; | |
1055 | int err; | |
1056 | ||
1057 | err = pci_enable_device(pdev); | |
1058 | if (err) | |
1059 | return err; | |
1060 | ||
1061 | pci_set_master(pdev); | |
1062 | ||
1063 | host = scsi_host_alloc(&driver_template, sizeof(struct st_hba)); | |
1064 | ||
1065 | if (!host) { | |
1066 | printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n", | |
1067 | pci_name(pdev)); | |
1068 | err = -ENOMEM; | |
1069 | goto out_disable; | |
1070 | } | |
1071 | ||
1072 | hba = (struct st_hba *)host->hostdata; | |
1073 | memset(hba, 0, sizeof(struct st_hba)); | |
1074 | ||
1075 | err = pci_request_regions(pdev, DRV_NAME); | |
1076 | if (err < 0) { | |
1077 | printk(KERN_ERR DRV_NAME "(%s): request regions failed\n", | |
1078 | pci_name(pdev)); | |
1079 | goto out_scsi_host_put; | |
1080 | } | |
1081 | ||
25729a7f | 1082 | hba->mmio_base = pci_ioremap_bar(pdev, 0); |
5a25ba16 JG |
1083 | if ( !hba->mmio_base) { |
1084 | printk(KERN_ERR DRV_NAME "(%s): memory map failed\n", | |
1085 | pci_name(pdev)); | |
1086 | err = -ENOMEM; | |
1087 | goto out_release_regions; | |
1088 | } | |
1089 | ||
1090 | err = stex_set_dma_mask(pdev); | |
1091 | if (err) { | |
1092 | printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n", | |
1093 | pci_name(pdev)); | |
1094 | goto out_iounmap; | |
1095 | } | |
1096 | ||
94e9108b | 1097 | hba->cardtype = (unsigned int) id->driver_data; |
7cfe99a5 | 1098 | if (hba->cardtype == st_vsc && (pdev->subsystem_device & 1)) |
94e9108b | 1099 | hba->cardtype = st_vsc1; |
62e5b3d8 | 1100 | hba->dma_size = (hba->cardtype == st_vsc1 || hba->cardtype == st_seq) ? |
94e9108b | 1101 | (STEX_BUFFER_SIZE + ST_ADDITIONAL_MEM) : (STEX_BUFFER_SIZE); |
5a25ba16 | 1102 | hba->dma_mem = dma_alloc_coherent(&pdev->dev, |
94e9108b | 1103 | hba->dma_size, &hba->dma_handle, GFP_KERNEL); |
5a25ba16 JG |
1104 | if (!hba->dma_mem) { |
1105 | err = -ENOMEM; | |
1106 | printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n", | |
1107 | pci_name(pdev)); | |
1108 | goto out_iounmap; | |
1109 | } | |
1110 | ||
1111 | hba->status_buffer = | |
1112 | (struct status_msg *)(hba->dma_mem + MU_REQ_BUFFER_SIZE); | |
1113 | hba->copy_buffer = hba->dma_mem + MU_BUFFER_SIZE; | |
1114 | hba->mu_status = MU_STATE_STARTING; | |
1115 | ||
e0b2e597 EL |
1116 | if (hba->cardtype == st_shasta) { |
1117 | host->max_lun = 8; | |
1118 | host->max_id = 16 + 1; | |
1119 | } else if (hba->cardtype == st_yosemite) { | |
e8a091b3 | 1120 | host->max_lun = 256; |
e0b2e597 EL |
1121 | host->max_id = 1 + 1; |
1122 | } else { | |
62e5b3d8 | 1123 | /* st_vsc , st_vsc1 and st_seq */ |
e0b2e597 EL |
1124 | host->max_lun = 1; |
1125 | host->max_id = 128 + 1; | |
1126 | } | |
1127 | host->max_channel = 0; | |
5a25ba16 JG |
1128 | host->unique_id = host->host_no; |
1129 | host->max_cmd_len = STEX_CDB_LENGTH; | |
1130 | ||
1131 | hba->host = host; | |
1132 | hba->pdev = pdev; | |
1133 | init_waitqueue_head(&hba->waitq); | |
1134 | ||
1135 | err = request_irq(pdev->irq, stex_intr, IRQF_SHARED, DRV_NAME, hba); | |
1136 | if (err) { | |
1137 | printk(KERN_ERR DRV_NAME "(%s): request irq failed\n", | |
1138 | pci_name(pdev)); | |
1139 | goto out_pci_free; | |
1140 | } | |
1141 | ||
1142 | err = stex_handshake(hba); | |
1143 | if (err) | |
1144 | goto out_free_irq; | |
1145 | ||
529e7a62 | 1146 | err = scsi_init_shared_tag_map(host, host->can_queue); |
deb81d80 | 1147 | if (err) { |
cf355883 EL |
1148 | printk(KERN_ERR DRV_NAME "(%s): init shared queue failed\n", |
1149 | pci_name(pdev)); | |
1150 | goto out_free_irq; | |
1151 | } | |
1152 | ||
5a25ba16 JG |
1153 | pci_set_drvdata(pdev, hba); |
1154 | ||
1155 | err = scsi_add_host(host, &pdev->dev); | |
1156 | if (err) { | |
1157 | printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n", | |
1158 | pci_name(pdev)); | |
1159 | goto out_free_irq; | |
1160 | } | |
1161 | ||
1162 | scsi_scan_host(host); | |
1163 | ||
1164 | return 0; | |
1165 | ||
1166 | out_free_irq: | |
1167 | free_irq(pdev->irq, hba); | |
1168 | out_pci_free: | |
94e9108b | 1169 | dma_free_coherent(&pdev->dev, hba->dma_size, |
5a25ba16 JG |
1170 | hba->dma_mem, hba->dma_handle); |
1171 | out_iounmap: | |
1172 | iounmap(hba->mmio_base); | |
1173 | out_release_regions: | |
1174 | pci_release_regions(pdev); | |
1175 | out_scsi_host_put: | |
1176 | scsi_host_put(host); | |
1177 | out_disable: | |
1178 | pci_disable_device(pdev); | |
1179 | ||
1180 | return err; | |
1181 | } | |
1182 | ||
1183 | static void stex_hba_stop(struct st_hba *hba) | |
1184 | { | |
1185 | struct req_msg *req; | |
1186 | unsigned long flags; | |
1187 | unsigned long before; | |
cf355883 | 1188 | u16 tag = 0; |
5a25ba16 JG |
1189 | |
1190 | spin_lock_irqsave(hba->host->host_lock, flags); | |
1191 | req = stex_alloc_req(hba); | |
1192 | memset(req->cdb, 0, STEX_CDB_LENGTH); | |
1193 | ||
fb4f66be EL |
1194 | if (hba->cardtype == st_yosemite) { |
1195 | req->cdb[0] = MGT_CMD; | |
1196 | req->cdb[1] = MGT_CMD_SIGNATURE; | |
1197 | req->cdb[2] = CTLR_CONFIG_CMD; | |
1198 | req->cdb[3] = CTLR_SHUTDOWN; | |
1199 | } else { | |
1200 | req->cdb[0] = CONTROLLER_CMD; | |
1201 | req->cdb[1] = CTLR_POWER_STATE_CHANGE; | |
1202 | req->cdb[2] = CTLR_POWER_SAVING; | |
1203 | } | |
5a25ba16 JG |
1204 | |
1205 | hba->ccb[tag].cmd = NULL; | |
1206 | hba->ccb[tag].sg_count = 0; | |
1207 | hba->ccb[tag].sense_bufflen = 0; | |
1208 | hba->ccb[tag].sense_buffer = NULL; | |
1209 | hba->ccb[tag].req_type |= PASSTHRU_REQ_TYPE; | |
1210 | ||
1211 | stex_send_cmd(hba, req, tag); | |
1212 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
1213 | ||
cf355883 EL |
1214 | before = jiffies; |
1215 | while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) { | |
1216 | if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) | |
1217 | return; | |
1218 | msleep(10); | |
1219 | } | |
5a25ba16 JG |
1220 | } |
1221 | ||
1222 | static void stex_hba_free(struct st_hba *hba) | |
1223 | { | |
1224 | free_irq(hba->pdev->irq, hba); | |
1225 | ||
1226 | iounmap(hba->mmio_base); | |
1227 | ||
1228 | pci_release_regions(hba->pdev); | |
1229 | ||
94e9108b | 1230 | dma_free_coherent(&hba->pdev->dev, hba->dma_size, |
5a25ba16 JG |
1231 | hba->dma_mem, hba->dma_handle); |
1232 | } | |
1233 | ||
1234 | static void stex_remove(struct pci_dev *pdev) | |
1235 | { | |
1236 | struct st_hba *hba = pci_get_drvdata(pdev); | |
1237 | ||
1238 | scsi_remove_host(hba->host); | |
1239 | ||
1240 | pci_set_drvdata(pdev, NULL); | |
1241 | ||
1242 | stex_hba_stop(hba); | |
1243 | ||
1244 | stex_hba_free(hba); | |
1245 | ||
1246 | scsi_host_put(hba->host); | |
1247 | ||
1248 | pci_disable_device(pdev); | |
1249 | } | |
1250 | ||
1251 | static void stex_shutdown(struct pci_dev *pdev) | |
1252 | { | |
1253 | struct st_hba *hba = pci_get_drvdata(pdev); | |
1254 | ||
1255 | stex_hba_stop(hba); | |
1256 | } | |
1257 | ||
1258 | static struct pci_device_id stex_pci_tbl[] = { | |
ee926b27 EL |
1259 | /* st_shasta */ |
1260 | { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1261 | st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */ | |
1262 | { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1263 | st_shasta }, /* SuperTrak EX12350 */ | |
1264 | { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1265 | st_shasta }, /* SuperTrak EX4350 */ | |
1266 | { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1267 | st_shasta }, /* SuperTrak EX24350 */ | |
1268 | ||
1269 | /* st_vsc */ | |
1270 | { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc }, | |
1271 | ||
1272 | /* st_yosemite */ | |
e8a091b3 | 1273 | { 0x105a, 0x8650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_yosemite }, |
62e5b3d8 ELP |
1274 | |
1275 | /* st_seq */ | |
1276 | { 0x105a, 0x3360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_seq }, | |
5a25ba16 JG |
1277 | { } /* terminate list */ |
1278 | }; | |
1279 | MODULE_DEVICE_TABLE(pci, stex_pci_tbl); | |
1280 | ||
1281 | static struct pci_driver stex_pci_driver = { | |
1282 | .name = DRV_NAME, | |
1283 | .id_table = stex_pci_tbl, | |
1284 | .probe = stex_probe, | |
1285 | .remove = __devexit_p(stex_remove), | |
1286 | .shutdown = stex_shutdown, | |
1287 | }; | |
1288 | ||
1289 | static int __init stex_init(void) | |
1290 | { | |
1291 | printk(KERN_INFO DRV_NAME | |
1292 | ": Promise SuperTrak EX Driver version: %s\n", | |
1293 | ST_DRIVER_VERSION); | |
1294 | ||
1295 | return pci_register_driver(&stex_pci_driver); | |
1296 | } | |
1297 | ||
1298 | static void __exit stex_exit(void) | |
1299 | { | |
1300 | pci_unregister_driver(&stex_pci_driver); | |
1301 | } | |
1302 | ||
1303 | module_init(stex_init); | |
1304 | module_exit(stex_exit); |