Commit | Line | Data |
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5a25ba16 JG |
1 | /* |
2 | * SuperTrak EX Series Storage Controller driver for Linux | |
3 | * | |
bd5cd9cd | 4 | * Copyright (C) 2005-2009 Promise Technology Inc. |
5a25ba16 JG |
5 | * |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * Written By: | |
12 | * Ed Lin <promise_linux@promise.com> | |
13 | * | |
5a25ba16 JG |
14 | */ |
15 | ||
16 | #include <linux/init.h> | |
17 | #include <linux/errno.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/delay.h> | |
5a25ba16 JG |
20 | #include <linux/time.h> |
21 | #include <linux/pci.h> | |
22 | #include <linux/blkdev.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/types.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/spinlock.h> | |
27 | #include <asm/io.h> | |
28 | #include <asm/irq.h> | |
29 | #include <asm/byteorder.h> | |
30 | #include <scsi/scsi.h> | |
31 | #include <scsi/scsi_device.h> | |
32 | #include <scsi/scsi_cmnd.h> | |
33 | #include <scsi/scsi_host.h> | |
cf355883 | 34 | #include <scsi/scsi_tcq.h> |
c25da0af | 35 | #include <scsi/scsi_dbg.h> |
11002fbc | 36 | #include <scsi/scsi_eh.h> |
5a25ba16 JG |
37 | |
38 | #define DRV_NAME "stex" | |
05b4460b EL |
39 | #define ST_DRIVER_VERSION "4.6.0000.3" |
40 | #define ST_VER_MAJOR 4 | |
41 | #define ST_VER_MINOR 6 | |
42 | #define ST_OEM 0 | |
43 | #define ST_BUILD_VER 3 | |
5a25ba16 JG |
44 | |
45 | enum { | |
46 | /* MU register offset */ | |
47 | IMR0 = 0x10, /* MU_INBOUND_MESSAGE_REG0 */ | |
48 | IMR1 = 0x14, /* MU_INBOUND_MESSAGE_REG1 */ | |
49 | OMR0 = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */ | |
50 | OMR1 = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */ | |
51 | IDBL = 0x20, /* MU_INBOUND_DOORBELL */ | |
52 | IIS = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */ | |
53 | IIM = 0x28, /* MU_INBOUND_INTERRUPT_MASK */ | |
54 | ODBL = 0x2c, /* MU_OUTBOUND_DOORBELL */ | |
55 | OIS = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */ | |
56 | OIM = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */ | |
57 | ||
0f3f6ee6 EL |
58 | YH2I_INT = 0x20, |
59 | YINT_EN = 0x34, | |
60 | YI2H_INT = 0x9c, | |
61 | YI2H_INT_C = 0xa0, | |
62 | YH2I_REQ = 0xc0, | |
63 | YH2I_REQ_HI = 0xc4, | |
64 | ||
5a25ba16 JG |
65 | /* MU register value */ |
66 | MU_INBOUND_DOORBELL_HANDSHAKE = 1, | |
67 | MU_INBOUND_DOORBELL_REQHEADCHANGED = 2, | |
68 | MU_INBOUND_DOORBELL_STATUSTAILCHANGED = 4, | |
69 | MU_INBOUND_DOORBELL_HMUSTOPPED = 8, | |
70 | MU_INBOUND_DOORBELL_RESET = 16, | |
71 | ||
72 | MU_OUTBOUND_DOORBELL_HANDSHAKE = 1, | |
73 | MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = 2, | |
74 | MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED = 4, | |
75 | MU_OUTBOUND_DOORBELL_BUSCHANGE = 8, | |
76 | MU_OUTBOUND_DOORBELL_HASEVENT = 16, | |
77 | ||
78 | /* MU status code */ | |
79 | MU_STATE_STARTING = 1, | |
80 | MU_STATE_FMU_READY_FOR_HANDSHAKE = 2, | |
81 | MU_STATE_SEND_HANDSHAKE_FRAME = 3, | |
82 | MU_STATE_STARTED = 4, | |
83 | MU_STATE_RESETTING = 5, | |
84 | ||
76fbf96f | 85 | MU_MAX_DELAY = 120, |
5a25ba16 | 86 | MU_HANDSHAKE_SIGNATURE = 0x55aaaa55, |
529e7a62 | 87 | MU_HANDSHAKE_SIGNATURE_HALF = 0x5a5a0000, |
76fbf96f | 88 | MU_HARD_RESET_WAIT = 30000, |
5a25ba16 JG |
89 | HMU_PARTNER_TYPE = 2, |
90 | ||
91 | /* firmware returned values */ | |
92 | SRB_STATUS_SUCCESS = 0x01, | |
93 | SRB_STATUS_ERROR = 0x04, | |
94 | SRB_STATUS_BUSY = 0x05, | |
95 | SRB_STATUS_INVALID_REQUEST = 0x06, | |
96 | SRB_STATUS_SELECTION_TIMEOUT = 0x0A, | |
97 | SRB_SEE_SENSE = 0x80, | |
98 | ||
99 | /* task attribute */ | |
100 | TASK_ATTRIBUTE_SIMPLE = 0x0, | |
101 | TASK_ATTRIBUTE_HEADOFQUEUE = 0x1, | |
102 | TASK_ATTRIBUTE_ORDERED = 0x2, | |
103 | TASK_ATTRIBUTE_ACA = 0x4, | |
104 | ||
0f3f6ee6 EL |
105 | SS_STS_NORMAL = 0x80000000, |
106 | SS_STS_DONE = 0x40000000, | |
107 | SS_STS_HANDSHAKE = 0x20000000, | |
108 | ||
109 | SS_HEAD_HANDSHAKE = 0x80, | |
110 | ||
7cfe99a5 | 111 | STEX_CDB_LENGTH = 16, |
5a25ba16 | 112 | STATUS_VAR_LEN = 128, |
5a25ba16 JG |
113 | |
114 | /* sg flags */ | |
115 | SG_CF_EOT = 0x80, /* end of table */ | |
116 | SG_CF_64B = 0x40, /* 64 bit item */ | |
117 | SG_CF_HOST = 0x20, /* sg in host memory */ | |
7cfe99a5 ELP |
118 | MSG_DATA_DIR_ND = 0, |
119 | MSG_DATA_DIR_IN = 1, | |
120 | MSG_DATA_DIR_OUT = 2, | |
5a25ba16 | 121 | |
5a25ba16 JG |
122 | st_shasta = 0, |
123 | st_vsc = 1, | |
591a3a5f EL |
124 | st_yosemite = 2, |
125 | st_seq = 3, | |
0f3f6ee6 | 126 | st_yel = 4, |
5a25ba16 JG |
127 | |
128 | PASSTHRU_REQ_TYPE = 0x00000001, | |
129 | PASSTHRU_REQ_NO_WAKEUP = 0x00000100, | |
7cfe99a5 | 130 | ST_INTERNAL_TIMEOUT = 180, |
5a25ba16 | 131 | |
fb4f66be EL |
132 | ST_TO_CMD = 0, |
133 | ST_FROM_CMD = 1, | |
134 | ||
5a25ba16 | 135 | /* vendor specific commands of Promise */ |
fb4f66be EL |
136 | MGT_CMD = 0xd8, |
137 | SINBAND_MGT_CMD = 0xd9, | |
5a25ba16 JG |
138 | ARRAY_CMD = 0xe0, |
139 | CONTROLLER_CMD = 0xe1, | |
140 | DEBUGGING_CMD = 0xe2, | |
141 | PASSTHRU_CMD = 0xe3, | |
142 | ||
143 | PASSTHRU_GET_ADAPTER = 0x05, | |
144 | PASSTHRU_GET_DRVVER = 0x10, | |
fb4f66be EL |
145 | |
146 | CTLR_CONFIG_CMD = 0x03, | |
147 | CTLR_SHUTDOWN = 0x0d, | |
148 | ||
5a25ba16 JG |
149 | CTLR_POWER_STATE_CHANGE = 0x0e, |
150 | CTLR_POWER_SAVING = 0x01, | |
151 | ||
152 | PASSTHRU_SIGNATURE = 0x4e415041, | |
fb4f66be | 153 | MGT_CMD_SIGNATURE = 0xba, |
5a25ba16 JG |
154 | |
155 | INQUIRY_EVPD = 0x01, | |
94e9108b EL |
156 | |
157 | ST_ADDITIONAL_MEM = 0x200000, | |
5a25ba16 JG |
158 | }; |
159 | ||
160 | struct st_sgitem { | |
161 | u8 ctrl; /* SG_CF_xxx */ | |
162 | u8 reserved[3]; | |
163 | __le32 count; | |
f1498161 | 164 | __le64 addr; |
5a25ba16 JG |
165 | }; |
166 | ||
0f3f6ee6 EL |
167 | struct st_ss_sgitem { |
168 | __le32 addr; | |
169 | __le32 addr_hi; | |
170 | __le32 count; | |
171 | }; | |
172 | ||
5a25ba16 JG |
173 | struct st_sgtable { |
174 | __le16 sg_count; | |
175 | __le16 max_sg_count; | |
176 | __le32 sz_in_byte; | |
5a25ba16 JG |
177 | }; |
178 | ||
0f3f6ee6 EL |
179 | struct st_msg_header { |
180 | __le64 handle; | |
181 | u8 flag; | |
182 | u8 channel; | |
183 | __le16 timeout; | |
184 | u32 reserved; | |
185 | }; | |
186 | ||
5a25ba16 | 187 | struct handshake_frame { |
f1498161 | 188 | __le64 rb_phy; /* request payload queue physical address */ |
5a25ba16 JG |
189 | __le16 req_sz; /* size of each request payload */ |
190 | __le16 req_cnt; /* count of reqs the buffer can hold */ | |
191 | __le16 status_sz; /* size of each status payload */ | |
192 | __le16 status_cnt; /* count of status the buffer can hold */ | |
f1498161 | 193 | __le64 hosttime; /* seconds from Jan 1, 1970 (GMT) */ |
5a25ba16 JG |
194 | u8 partner_type; /* who sends this frame */ |
195 | u8 reserved0[7]; | |
196 | __le32 partner_ver_major; | |
197 | __le32 partner_ver_minor; | |
198 | __le32 partner_ver_oem; | |
199 | __le32 partner_ver_build; | |
94e9108b EL |
200 | __le32 extra_offset; /* NEW */ |
201 | __le32 extra_size; /* NEW */ | |
0f3f6ee6 EL |
202 | __le32 scratch_size; |
203 | u32 reserved1; | |
5a25ba16 JG |
204 | }; |
205 | ||
206 | struct req_msg { | |
207 | __le16 tag; | |
208 | u8 lun; | |
209 | u8 target; | |
210 | u8 task_attr; | |
211 | u8 task_manage; | |
7cfe99a5 | 212 | u8 data_dir; |
f903d7b7 | 213 | u8 payload_sz; /* payload size in 4-byte, not used */ |
5a25ba16 | 214 | u8 cdb[STEX_CDB_LENGTH]; |
591a3a5f | 215 | u32 variable[0]; |
5a25ba16 JG |
216 | }; |
217 | ||
218 | struct status_msg { | |
219 | __le16 tag; | |
220 | u8 lun; | |
221 | u8 target; | |
222 | u8 srb_status; | |
223 | u8 scsi_status; | |
224 | u8 reserved; | |
225 | u8 payload_sz; /* payload size in 4-byte */ | |
226 | u8 variable[STATUS_VAR_LEN]; | |
227 | }; | |
228 | ||
229 | struct ver_info { | |
230 | u32 major; | |
231 | u32 minor; | |
232 | u32 oem; | |
233 | u32 build; | |
234 | u32 reserved[2]; | |
235 | }; | |
236 | ||
237 | struct st_frame { | |
238 | u32 base[6]; | |
239 | u32 rom_addr; | |
240 | ||
241 | struct ver_info drv_ver; | |
242 | struct ver_info bios_ver; | |
243 | ||
244 | u32 bus; | |
245 | u32 slot; | |
246 | u32 irq_level; | |
247 | u32 irq_vec; | |
248 | u32 id; | |
249 | u32 subid; | |
250 | ||
251 | u32 dimm_size; | |
252 | u8 dimm_type; | |
253 | u8 reserved[3]; | |
254 | ||
255 | u32 channel; | |
256 | u32 reserved1; | |
257 | }; | |
258 | ||
259 | struct st_drvver { | |
260 | u32 major; | |
261 | u32 minor; | |
262 | u32 oem; | |
263 | u32 build; | |
264 | u32 signature[2]; | |
265 | u8 console_id; | |
266 | u8 host_no; | |
267 | u8 reserved0[2]; | |
268 | u32 reserved[3]; | |
269 | }; | |
270 | ||
5a25ba16 JG |
271 | struct st_ccb { |
272 | struct req_msg *req; | |
273 | struct scsi_cmnd *cmd; | |
274 | ||
275 | void *sense_buffer; | |
276 | unsigned int sense_bufflen; | |
277 | int sg_count; | |
278 | ||
279 | u32 req_type; | |
280 | u8 srb_status; | |
281 | u8 scsi_status; | |
f1498161 | 282 | u8 reserved[2]; |
5a25ba16 JG |
283 | }; |
284 | ||
285 | struct st_hba { | |
286 | void __iomem *mmio_base; /* iomapped PCI memory space */ | |
287 | void *dma_mem; | |
288 | dma_addr_t dma_handle; | |
94e9108b | 289 | size_t dma_size; |
5a25ba16 JG |
290 | |
291 | struct Scsi_Host *host; | |
292 | struct pci_dev *pdev; | |
293 | ||
0f3f6ee6 EL |
294 | struct req_msg * (*alloc_rq) (struct st_hba *); |
295 | int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *); | |
296 | void (*send) (struct st_hba *, struct req_msg *, u16); | |
297 | ||
5a25ba16 JG |
298 | u32 req_head; |
299 | u32 req_tail; | |
300 | u32 status_head; | |
301 | u32 status_tail; | |
302 | ||
303 | struct status_msg *status_buffer; | |
304 | void *copy_buffer; /* temp buffer for driver-handled commands */ | |
591a3a5f | 305 | struct st_ccb *ccb; |
5a25ba16 | 306 | struct st_ccb *wait_ccb; |
0f3f6ee6 | 307 | __le32 *scratch; |
5a25ba16 JG |
308 | |
309 | unsigned int mu_status; | |
5a25ba16 | 310 | unsigned int cardtype; |
99946f81 EL |
311 | int msi_enabled; |
312 | int out_req_cnt; | |
591a3a5f EL |
313 | u32 extra_offset; |
314 | u16 rq_count; | |
315 | u16 rq_size; | |
316 | u16 sts_count; | |
317 | }; | |
318 | ||
319 | struct st_card_info { | |
0f3f6ee6 EL |
320 | struct req_msg * (*alloc_rq) (struct st_hba *); |
321 | int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *); | |
322 | void (*send) (struct st_hba *, struct req_msg *, u16); | |
591a3a5f EL |
323 | unsigned int max_id; |
324 | unsigned int max_lun; | |
325 | unsigned int max_channel; | |
326 | u16 rq_count; | |
327 | u16 rq_size; | |
328 | u16 sts_count; | |
5a25ba16 JG |
329 | }; |
330 | ||
99946f81 EL |
331 | static int msi; |
332 | module_param(msi, int, 0); | |
333 | MODULE_PARM_DESC(msi, "Enable Message Signaled Interrupts(0=off, 1=on)"); | |
334 | ||
5a25ba16 JG |
335 | static const char console_inq_page[] = |
336 | { | |
337 | 0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30, | |
338 | 0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20, /* "Promise " */ | |
339 | 0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E, /* "RAID Con" */ | |
340 | 0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20, /* "sole " */ | |
341 | 0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20, /* "1.00 " */ | |
342 | 0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D, /* "SX/RSAF-" */ | |
343 | 0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20, /* "TE1.00 " */ | |
344 | 0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20 | |
345 | }; | |
346 | ||
347 | MODULE_AUTHOR("Ed Lin"); | |
348 | MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers"); | |
349 | MODULE_LICENSE("GPL"); | |
350 | MODULE_VERSION(ST_DRIVER_VERSION); | |
351 | ||
f1498161 | 352 | static void stex_gettime(__le64 *time) |
5a25ba16 JG |
353 | { |
354 | struct timeval tv; | |
5a25ba16 | 355 | |
7cfe99a5 | 356 | do_gettimeofday(&tv); |
f1498161 | 357 | *time = cpu_to_le64(tv.tv_sec); |
5a25ba16 JG |
358 | } |
359 | ||
5a25ba16 JG |
360 | static struct status_msg *stex_get_status(struct st_hba *hba) |
361 | { | |
f1498161 | 362 | struct status_msg *status = hba->status_buffer + hba->status_tail; |
5a25ba16 JG |
363 | |
364 | ++hba->status_tail; | |
591a3a5f | 365 | hba->status_tail %= hba->sts_count+1; |
5a25ba16 JG |
366 | |
367 | return status; | |
368 | } | |
369 | ||
5a25ba16 JG |
370 | static void stex_invalid_field(struct scsi_cmnd *cmd, |
371 | void (*done)(struct scsi_cmnd *)) | |
372 | { | |
11002fbc FT |
373 | cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION; |
374 | ||
7cfe99a5 | 375 | /* "Invalid field in cdb" */ |
11002fbc FT |
376 | scsi_build_sense_buffer(0, cmd->sense_buffer, ILLEGAL_REQUEST, 0x24, |
377 | 0x0); | |
5a25ba16 JG |
378 | done(cmd); |
379 | } | |
380 | ||
381 | static struct req_msg *stex_alloc_req(struct st_hba *hba) | |
382 | { | |
591a3a5f | 383 | struct req_msg *req = hba->dma_mem + hba->req_head * hba->rq_size; |
5a25ba16 JG |
384 | |
385 | ++hba->req_head; | |
591a3a5f | 386 | hba->req_head %= hba->rq_count+1; |
5a25ba16 JG |
387 | |
388 | return req; | |
389 | } | |
390 | ||
0f3f6ee6 EL |
391 | static struct req_msg *stex_ss_alloc_req(struct st_hba *hba) |
392 | { | |
393 | return (struct req_msg *)(hba->dma_mem + | |
394 | hba->req_head * hba->rq_size + sizeof(struct st_msg_header)); | |
395 | } | |
396 | ||
5a25ba16 JG |
397 | static int stex_map_sg(struct st_hba *hba, |
398 | struct req_msg *req, struct st_ccb *ccb) | |
399 | { | |
5a25ba16 | 400 | struct scsi_cmnd *cmd; |
d5587d5d | 401 | struct scatterlist *sg; |
5a25ba16 | 402 | struct st_sgtable *dst; |
f1498161 | 403 | struct st_sgitem *table; |
d5587d5d | 404 | int i, nseg; |
5a25ba16 JG |
405 | |
406 | cmd = ccb->cmd; | |
d5587d5d | 407 | nseg = scsi_dma_map(cmd); |
f1498161 | 408 | BUG_ON(nseg < 0); |
d5587d5d | 409 | if (nseg) { |
f1498161 EL |
410 | dst = (struct st_sgtable *)req->variable; |
411 | ||
d5587d5d FT |
412 | ccb->sg_count = nseg; |
413 | dst->sg_count = cpu_to_le16((u16)nseg); | |
f1498161 EL |
414 | dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize); |
415 | dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd)); | |
5a25ba16 | 416 | |
f1498161 | 417 | table = (struct st_sgitem *)(dst + 1); |
d5587d5d | 418 | scsi_for_each_sg(cmd, sg, nseg, i) { |
f1498161 EL |
419 | table[i].count = cpu_to_le32((u32)sg_dma_len(sg)); |
420 | table[i].addr = cpu_to_le64(sg_dma_address(sg)); | |
421 | table[i].ctrl = SG_CF_64B | SG_CF_HOST; | |
5a25ba16 | 422 | } |
f1498161 | 423 | table[--i].ctrl |= SG_CF_EOT; |
5a25ba16 JG |
424 | } |
425 | ||
f1498161 | 426 | return nseg; |
5a25ba16 JG |
427 | } |
428 | ||
0f3f6ee6 EL |
429 | static int stex_ss_map_sg(struct st_hba *hba, |
430 | struct req_msg *req, struct st_ccb *ccb) | |
431 | { | |
432 | struct scsi_cmnd *cmd; | |
433 | struct scatterlist *sg; | |
434 | struct st_sgtable *dst; | |
435 | struct st_ss_sgitem *table; | |
436 | int i, nseg; | |
437 | ||
438 | cmd = ccb->cmd; | |
439 | nseg = scsi_dma_map(cmd); | |
440 | BUG_ON(nseg < 0); | |
441 | if (nseg) { | |
442 | dst = (struct st_sgtable *)req->variable; | |
443 | ||
444 | ccb->sg_count = nseg; | |
445 | dst->sg_count = cpu_to_le16((u16)nseg); | |
446 | dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize); | |
447 | dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd)); | |
448 | ||
449 | table = (struct st_ss_sgitem *)(dst + 1); | |
450 | scsi_for_each_sg(cmd, sg, nseg, i) { | |
451 | table[i].count = cpu_to_le32((u32)sg_dma_len(sg)); | |
452 | table[i].addr = | |
453 | cpu_to_le32(sg_dma_address(sg) & 0xffffffff); | |
454 | table[i].addr_hi = | |
455 | cpu_to_le32((sg_dma_address(sg) >> 16) >> 16); | |
456 | } | |
457 | } | |
458 | ||
459 | return nseg; | |
460 | } | |
461 | ||
5a25ba16 JG |
462 | static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb) |
463 | { | |
464 | struct st_frame *p; | |
465 | size_t count = sizeof(struct st_frame); | |
466 | ||
467 | p = hba->copy_buffer; | |
f1498161 | 468 | scsi_sg_copy_to_buffer(ccb->cmd, p, count); |
5a25ba16 JG |
469 | memset(p->base, 0, sizeof(u32)*6); |
470 | *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0); | |
471 | p->rom_addr = 0; | |
472 | ||
473 | p->drv_ver.major = ST_VER_MAJOR; | |
474 | p->drv_ver.minor = ST_VER_MINOR; | |
475 | p->drv_ver.oem = ST_OEM; | |
476 | p->drv_ver.build = ST_BUILD_VER; | |
477 | ||
478 | p->bus = hba->pdev->bus->number; | |
479 | p->slot = hba->pdev->devfn; | |
480 | p->irq_level = 0; | |
481 | p->irq_vec = hba->pdev->irq; | |
482 | p->id = hba->pdev->vendor << 16 | hba->pdev->device; | |
483 | p->subid = | |
484 | hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device; | |
485 | ||
f1498161 | 486 | scsi_sg_copy_from_buffer(ccb->cmd, p, count); |
5a25ba16 JG |
487 | } |
488 | ||
489 | static void | |
490 | stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag) | |
491 | { | |
492 | req->tag = cpu_to_le16(tag); | |
5a25ba16 JG |
493 | |
494 | hba->ccb[tag].req = req; | |
495 | hba->out_req_cnt++; | |
496 | ||
497 | writel(hba->req_head, hba->mmio_base + IMR0); | |
498 | writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL); | |
499 | readl(hba->mmio_base + IDBL); /* flush */ | |
500 | } | |
501 | ||
0f3f6ee6 EL |
502 | static void |
503 | stex_ss_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag) | |
504 | { | |
505 | struct scsi_cmnd *cmd; | |
506 | struct st_msg_header *msg_h; | |
507 | dma_addr_t addr; | |
508 | ||
509 | req->tag = cpu_to_le16(tag); | |
510 | ||
511 | hba->ccb[tag].req = req; | |
512 | hba->out_req_cnt++; | |
513 | ||
514 | cmd = hba->ccb[tag].cmd; | |
515 | msg_h = (struct st_msg_header *)req - 1; | |
516 | if (likely(cmd)) { | |
517 | msg_h->channel = (u8)cmd->device->channel; | |
518 | msg_h->timeout = cpu_to_le16(cmd->request->timeout/HZ); | |
519 | } | |
520 | addr = hba->dma_handle + hba->req_head * hba->rq_size; | |
521 | addr += (hba->ccb[tag].sg_count+4)/11; | |
522 | msg_h->handle = cpu_to_le64(addr); | |
523 | ||
524 | ++hba->req_head; | |
525 | hba->req_head %= hba->rq_count+1; | |
526 | ||
527 | writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI); | |
528 | readl(hba->mmio_base + YH2I_REQ_HI); /* flush */ | |
529 | writel(addr, hba->mmio_base + YH2I_REQ); | |
530 | readl(hba->mmio_base + YH2I_REQ); /* flush */ | |
531 | } | |
532 | ||
cf355883 EL |
533 | static int |
534 | stex_slave_alloc(struct scsi_device *sdev) | |
535 | { | |
536 | /* Cheat: usually extracted from Inquiry data */ | |
537 | sdev->tagged_supported = 1; | |
538 | ||
f1498161 | 539 | scsi_activate_tcq(sdev, sdev->host->can_queue); |
cf355883 EL |
540 | |
541 | return 0; | |
542 | } | |
543 | ||
5a25ba16 JG |
544 | static int |
545 | stex_slave_config(struct scsi_device *sdev) | |
546 | { | |
547 | sdev->use_10_for_rw = 1; | |
548 | sdev->use_10_for_ms = 1; | |
dc5c49bf | 549 | blk_queue_rq_timeout(sdev->request_queue, 60 * HZ); |
cf355883 EL |
550 | sdev->tagged_supported = 1; |
551 | ||
5a25ba16 JG |
552 | return 0; |
553 | } | |
554 | ||
555 | static void | |
556 | stex_slave_destroy(struct scsi_device *sdev) | |
557 | { | |
cf355883 | 558 | scsi_deactivate_tcq(sdev, 1); |
5a25ba16 JG |
559 | } |
560 | ||
561 | static int | |
562 | stex_queuecommand(struct scsi_cmnd *cmd, void (* done)(struct scsi_cmnd *)) | |
563 | { | |
564 | struct st_hba *hba; | |
565 | struct Scsi_Host *host; | |
f1498161 | 566 | unsigned int id, lun; |
5a25ba16 JG |
567 | struct req_msg *req; |
568 | u16 tag; | |
7cfe99a5 | 569 | |
5a25ba16 JG |
570 | host = cmd->device->host; |
571 | id = cmd->device->id; | |
e0b2e597 | 572 | lun = cmd->device->lun; |
5a25ba16 JG |
573 | hba = (struct st_hba *) &host->hostdata[0]; |
574 | ||
575 | switch (cmd->cmnd[0]) { | |
576 | case MODE_SENSE_10: | |
577 | { | |
578 | static char ms10_caching_page[12] = | |
579 | { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 }; | |
580 | unsigned char page; | |
7cfe99a5 | 581 | |
5a25ba16 JG |
582 | page = cmd->cmnd[2] & 0x3f; |
583 | if (page == 0x8 || page == 0x3f) { | |
31fe47d4 FT |
584 | scsi_sg_copy_from_buffer(cmd, ms10_caching_page, |
585 | sizeof(ms10_caching_page)); | |
5a25ba16 JG |
586 | cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8; |
587 | done(cmd); | |
588 | } else | |
589 | stex_invalid_field(cmd, done); | |
590 | return 0; | |
591 | } | |
e0b2e597 EL |
592 | case REPORT_LUNS: |
593 | /* | |
594 | * The shasta firmware does not report actual luns in the | |
595 | * target, so fail the command to force sequential lun scan. | |
596 | * Also, the console device does not support this command. | |
597 | */ | |
598 | if (hba->cardtype == st_shasta || id == host->max_id - 1) { | |
599 | stex_invalid_field(cmd, done); | |
600 | return 0; | |
601 | } | |
602 | break; | |
d116a7bc EL |
603 | case TEST_UNIT_READY: |
604 | if (id == host->max_id - 1) { | |
605 | cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8; | |
606 | done(cmd); | |
607 | return 0; | |
608 | } | |
609 | break; | |
5a25ba16 | 610 | case INQUIRY: |
e0b2e597 | 611 | if (id != host->max_id - 1) |
5a25ba16 | 612 | break; |
0f3f6ee6 EL |
613 | if (!lun && !cmd->device->channel && |
614 | (cmd->cmnd[1] & INQUIRY_EVPD) == 0) { | |
31fe47d4 FT |
615 | scsi_sg_copy_from_buffer(cmd, (void *)console_inq_page, |
616 | sizeof(console_inq_page)); | |
5a25ba16 JG |
617 | cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8; |
618 | done(cmd); | |
619 | } else | |
620 | stex_invalid_field(cmd, done); | |
621 | return 0; | |
622 | case PASSTHRU_CMD: | |
623 | if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) { | |
624 | struct st_drvver ver; | |
26106e3c | 625 | size_t cp_len = sizeof(ver); |
7cfe99a5 | 626 | |
5a25ba16 JG |
627 | ver.major = ST_VER_MAJOR; |
628 | ver.minor = ST_VER_MINOR; | |
629 | ver.oem = ST_OEM; | |
630 | ver.build = ST_BUILD_VER; | |
631 | ver.signature[0] = PASSTHRU_SIGNATURE; | |
e0b2e597 | 632 | ver.console_id = host->max_id - 1; |
5a25ba16 | 633 | ver.host_no = hba->host->host_no; |
31fe47d4 | 634 | cp_len = scsi_sg_copy_from_buffer(cmd, &ver, cp_len); |
26106e3c | 635 | cmd->result = sizeof(ver) == cp_len ? |
5a25ba16 JG |
636 | DID_OK << 16 | COMMAND_COMPLETE << 8 : |
637 | DID_ERROR << 16 | COMMAND_COMPLETE << 8; | |
638 | done(cmd); | |
639 | return 0; | |
640 | } | |
641 | default: | |
642 | break; | |
643 | } | |
644 | ||
645 | cmd->scsi_done = done; | |
646 | ||
cf355883 EL |
647 | tag = cmd->request->tag; |
648 | ||
649 | if (unlikely(tag >= host->can_queue)) | |
5a25ba16 JG |
650 | return SCSI_MLQUEUE_HOST_BUSY; |
651 | ||
0f3f6ee6 | 652 | req = hba->alloc_rq(hba); |
fb4f66be | 653 | |
e0b2e597 EL |
654 | req->lun = lun; |
655 | req->target = id; | |
5a25ba16 JG |
656 | |
657 | /* cdb */ | |
658 | memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH); | |
659 | ||
7cfe99a5 ELP |
660 | if (cmd->sc_data_direction == DMA_FROM_DEVICE) |
661 | req->data_dir = MSG_DATA_DIR_IN; | |
662 | else if (cmd->sc_data_direction == DMA_TO_DEVICE) | |
663 | req->data_dir = MSG_DATA_DIR_OUT; | |
664 | else | |
665 | req->data_dir = MSG_DATA_DIR_ND; | |
666 | ||
5a25ba16 JG |
667 | hba->ccb[tag].cmd = cmd; |
668 | hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE; | |
669 | hba->ccb[tag].sense_buffer = cmd->sense_buffer; | |
5a25ba16 | 670 | |
0f3f6ee6 EL |
671 | if (!hba->map_sg(hba, req, &hba->ccb[tag])) { |
672 | hba->ccb[tag].sg_count = 0; | |
673 | memset(&req->variable[0], 0, 8); | |
674 | } | |
5a25ba16 | 675 | |
0f3f6ee6 | 676 | hba->send(hba, req, tag); |
5a25ba16 JG |
677 | return 0; |
678 | } | |
679 | ||
5a25ba16 JG |
680 | static void stex_scsi_done(struct st_ccb *ccb) |
681 | { | |
682 | struct scsi_cmnd *cmd = ccb->cmd; | |
683 | int result; | |
684 | ||
f1498161 | 685 | if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) { |
5a25ba16 JG |
686 | result = ccb->scsi_status; |
687 | switch (ccb->scsi_status) { | |
688 | case SAM_STAT_GOOD: | |
689 | result |= DID_OK << 16 | COMMAND_COMPLETE << 8; | |
690 | break; | |
691 | case SAM_STAT_CHECK_CONDITION: | |
692 | result |= DRIVER_SENSE << 24; | |
693 | break; | |
694 | case SAM_STAT_BUSY: | |
695 | result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8; | |
696 | break; | |
697 | default: | |
698 | result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8; | |
699 | break; | |
700 | } | |
701 | } | |
702 | else if (ccb->srb_status & SRB_SEE_SENSE) | |
703 | result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION; | |
704 | else switch (ccb->srb_status) { | |
705 | case SRB_STATUS_SELECTION_TIMEOUT: | |
706 | result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8; | |
707 | break; | |
708 | case SRB_STATUS_BUSY: | |
709 | result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8; | |
710 | break; | |
711 | case SRB_STATUS_INVALID_REQUEST: | |
712 | case SRB_STATUS_ERROR: | |
713 | default: | |
714 | result = DID_ERROR << 16 | COMMAND_COMPLETE << 8; | |
715 | break; | |
716 | } | |
717 | ||
718 | cmd->result = result; | |
719 | cmd->scsi_done(cmd); | |
720 | } | |
721 | ||
722 | static void stex_copy_data(struct st_ccb *ccb, | |
723 | struct status_msg *resp, unsigned int variable) | |
724 | { | |
5a25ba16 JG |
725 | if (resp->scsi_status != SAM_STAT_GOOD) { |
726 | if (ccb->sense_buffer != NULL) | |
727 | memcpy(ccb->sense_buffer, resp->variable, | |
728 | min(variable, ccb->sense_bufflen)); | |
729 | return; | |
730 | } | |
731 | ||
732 | if (ccb->cmd == NULL) | |
733 | return; | |
f1498161 | 734 | scsi_sg_copy_from_buffer(ccb->cmd, resp->variable, variable); |
fb4f66be EL |
735 | } |
736 | ||
f1498161 | 737 | static void stex_check_cmd(struct st_hba *hba, |
fb4f66be EL |
738 | struct st_ccb *ccb, struct status_msg *resp) |
739 | { | |
fb4f66be | 740 | if (ccb->cmd->cmnd[0] == MGT_CMD && |
f1498161 | 741 | resp->scsi_status != SAM_STAT_CHECK_CONDITION) |
968a5763 EL |
742 | scsi_set_resid(ccb->cmd, scsi_bufflen(ccb->cmd) - |
743 | le32_to_cpu(*(__le32 *)&resp->variable[0])); | |
5a25ba16 JG |
744 | } |
745 | ||
746 | static void stex_mu_intr(struct st_hba *hba, u32 doorbell) | |
747 | { | |
748 | void __iomem *base = hba->mmio_base; | |
749 | struct status_msg *resp; | |
750 | struct st_ccb *ccb; | |
751 | unsigned int size; | |
752 | u16 tag; | |
753 | ||
f1498161 | 754 | if (unlikely(!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED))) |
5a25ba16 JG |
755 | return; |
756 | ||
757 | /* status payloads */ | |
758 | hba->status_head = readl(base + OMR1); | |
591a3a5f | 759 | if (unlikely(hba->status_head > hba->sts_count)) { |
5a25ba16 JG |
760 | printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n", |
761 | pci_name(hba->pdev)); | |
762 | return; | |
763 | } | |
764 | ||
fb4f66be EL |
765 | /* |
766 | * it's not a valid status payload if: | |
767 | * 1. there are no pending requests(e.g. during init stage) | |
768 | * 2. there are some pending requests, but the controller is in | |
769 | * reset status, and its type is not st_yosemite | |
770 | * firmware of st_yosemite in reset status will return pending requests | |
771 | * to driver, so we allow it to pass | |
772 | */ | |
773 | if (unlikely(hba->out_req_cnt <= 0 || | |
774 | (hba->mu_status == MU_STATE_RESETTING && | |
775 | hba->cardtype != st_yosemite))) { | |
5a25ba16 JG |
776 | hba->status_tail = hba->status_head; |
777 | goto update_status; | |
778 | } | |
779 | ||
780 | while (hba->status_tail != hba->status_head) { | |
781 | resp = stex_get_status(hba); | |
782 | tag = le16_to_cpu(resp->tag); | |
cf355883 | 783 | if (unlikely(tag >= hba->host->can_queue)) { |
5a25ba16 JG |
784 | printk(KERN_WARNING DRV_NAME |
785 | "(%s): invalid tag\n", pci_name(hba->pdev)); | |
786 | continue; | |
787 | } | |
5a25ba16 | 788 | |
f1498161 | 789 | hba->out_req_cnt--; |
5a25ba16 | 790 | ccb = &hba->ccb[tag]; |
f1498161 | 791 | if (unlikely(hba->wait_ccb == ccb)) |
5a25ba16 JG |
792 | hba->wait_ccb = NULL; |
793 | if (unlikely(ccb->req == NULL)) { | |
794 | printk(KERN_WARNING DRV_NAME | |
795 | "(%s): lagging req\n", pci_name(hba->pdev)); | |
5a25ba16 JG |
796 | continue; |
797 | } | |
798 | ||
799 | size = resp->payload_sz * sizeof(u32); /* payload size */ | |
800 | if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN || | |
801 | size > sizeof(*resp))) { | |
802 | printk(KERN_WARNING DRV_NAME "(%s): bad status size\n", | |
803 | pci_name(hba->pdev)); | |
804 | } else { | |
805 | size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */ | |
806 | if (size) | |
807 | stex_copy_data(ccb, resp, size); | |
808 | } | |
809 | ||
dd48ebf7 | 810 | ccb->req = NULL; |
5a25ba16 JG |
811 | ccb->srb_status = resp->srb_status; |
812 | ccb->scsi_status = resp->scsi_status; | |
813 | ||
cf355883 | 814 | if (likely(ccb->cmd != NULL)) { |
fb4f66be | 815 | if (hba->cardtype == st_yosemite) |
f1498161 | 816 | stex_check_cmd(hba, ccb, resp); |
fb4f66be | 817 | |
cf355883 EL |
818 | if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD && |
819 | ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER)) | |
820 | stex_controller_info(hba, ccb); | |
fb4f66be | 821 | |
d5587d5d | 822 | scsi_dma_unmap(ccb->cmd); |
cf355883 | 823 | stex_scsi_done(ccb); |
f1498161 | 824 | } else |
5a25ba16 | 825 | ccb->req_type = 0; |
5a25ba16 JG |
826 | } |
827 | ||
828 | update_status: | |
829 | writel(hba->status_head, base + IMR1); | |
830 | readl(base + IMR1); /* flush */ | |
831 | } | |
832 | ||
7d12e780 | 833 | static irqreturn_t stex_intr(int irq, void *__hba) |
5a25ba16 JG |
834 | { |
835 | struct st_hba *hba = __hba; | |
836 | void __iomem *base = hba->mmio_base; | |
837 | u32 data; | |
838 | unsigned long flags; | |
839 | int handled = 0; | |
840 | ||
841 | spin_lock_irqsave(hba->host->host_lock, flags); | |
842 | ||
843 | data = readl(base + ODBL); | |
844 | ||
845 | if (data && data != 0xffffffff) { | |
846 | /* clear the interrupt */ | |
847 | writel(data, base + ODBL); | |
848 | readl(base + ODBL); /* flush */ | |
849 | stex_mu_intr(hba, data); | |
850 | handled = 1; | |
851 | } | |
852 | ||
853 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
854 | ||
855 | return IRQ_RETVAL(handled); | |
856 | } | |
857 | ||
0f3f6ee6 EL |
858 | static void stex_ss_mu_intr(struct st_hba *hba) |
859 | { | |
860 | struct status_msg *resp; | |
861 | struct st_ccb *ccb; | |
862 | __le32 *scratch; | |
863 | unsigned int size; | |
864 | int count = 0; | |
865 | u32 value; | |
866 | u16 tag; | |
867 | ||
868 | if (unlikely(hba->out_req_cnt <= 0 || | |
869 | hba->mu_status == MU_STATE_RESETTING)) | |
870 | return; | |
871 | ||
872 | while (count < hba->sts_count) { | |
873 | scratch = hba->scratch + hba->status_tail; | |
874 | value = le32_to_cpu(*scratch); | |
875 | if (unlikely(!(value & SS_STS_NORMAL))) | |
876 | return; | |
877 | ||
878 | resp = hba->status_buffer + hba->status_tail; | |
879 | *scratch = 0; | |
880 | ++count; | |
881 | ++hba->status_tail; | |
882 | hba->status_tail %= hba->sts_count+1; | |
883 | ||
884 | tag = (u16)value; | |
885 | if (unlikely(tag >= hba->host->can_queue)) { | |
886 | printk(KERN_WARNING DRV_NAME | |
887 | "(%s): invalid tag\n", pci_name(hba->pdev)); | |
888 | continue; | |
889 | } | |
890 | ||
891 | hba->out_req_cnt--; | |
892 | ccb = &hba->ccb[tag]; | |
893 | if (unlikely(hba->wait_ccb == ccb)) | |
894 | hba->wait_ccb = NULL; | |
895 | if (unlikely(ccb->req == NULL)) { | |
896 | printk(KERN_WARNING DRV_NAME | |
897 | "(%s): lagging req\n", pci_name(hba->pdev)); | |
898 | continue; | |
899 | } | |
900 | ||
901 | ccb->req = NULL; | |
902 | if (likely(value & SS_STS_DONE)) { /* normal case */ | |
903 | ccb->srb_status = SRB_STATUS_SUCCESS; | |
904 | ccb->scsi_status = SAM_STAT_GOOD; | |
905 | } else { | |
906 | ccb->srb_status = resp->srb_status; | |
907 | ccb->scsi_status = resp->scsi_status; | |
908 | size = resp->payload_sz * sizeof(u32); | |
909 | if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN || | |
910 | size > sizeof(*resp))) { | |
911 | printk(KERN_WARNING DRV_NAME | |
912 | "(%s): bad status size\n", | |
913 | pci_name(hba->pdev)); | |
914 | } else { | |
915 | size -= sizeof(*resp) - STATUS_VAR_LEN; | |
916 | if (size) | |
917 | stex_copy_data(ccb, resp, size); | |
918 | } | |
919 | if (likely(ccb->cmd != NULL)) | |
920 | stex_check_cmd(hba, ccb, resp); | |
921 | } | |
922 | ||
923 | if (likely(ccb->cmd != NULL)) { | |
924 | scsi_dma_unmap(ccb->cmd); | |
925 | stex_scsi_done(ccb); | |
926 | } else | |
927 | ccb->req_type = 0; | |
928 | } | |
929 | } | |
930 | ||
931 | static irqreturn_t stex_ss_intr(int irq, void *__hba) | |
932 | { | |
933 | struct st_hba *hba = __hba; | |
934 | void __iomem *base = hba->mmio_base; | |
935 | u32 data; | |
936 | unsigned long flags; | |
937 | int handled = 0; | |
938 | ||
939 | spin_lock_irqsave(hba->host->host_lock, flags); | |
940 | ||
941 | data = readl(base + YI2H_INT); | |
942 | if (data && data != 0xffffffff) { | |
943 | /* clear the interrupt */ | |
944 | writel(data, base + YI2H_INT_C); | |
945 | stex_ss_mu_intr(hba); | |
946 | handled = 1; | |
947 | } | |
948 | ||
949 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
950 | ||
951 | return IRQ_RETVAL(handled); | |
952 | } | |
953 | ||
954 | static int stex_common_handshake(struct st_hba *hba) | |
5a25ba16 JG |
955 | { |
956 | void __iomem *base = hba->mmio_base; | |
957 | struct handshake_frame *h; | |
958 | dma_addr_t status_phys; | |
529e7a62 | 959 | u32 data; |
76fbf96f | 960 | unsigned long before; |
5a25ba16 JG |
961 | |
962 | if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) { | |
963 | writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL); | |
964 | readl(base + IDBL); | |
76fbf96f EL |
965 | before = jiffies; |
966 | while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) { | |
967 | if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) { | |
968 | printk(KERN_ERR DRV_NAME | |
969 | "(%s): no handshake signature\n", | |
970 | pci_name(hba->pdev)); | |
971 | return -1; | |
972 | } | |
5a25ba16 JG |
973 | rmb(); |
974 | msleep(1); | |
975 | } | |
5a25ba16 JG |
976 | } |
977 | ||
978 | udelay(10); | |
979 | ||
529e7a62 EL |
980 | data = readl(base + OMR1); |
981 | if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) { | |
982 | data &= 0x0000ffff; | |
f1498161 | 983 | if (hba->host->can_queue > data) { |
529e7a62 | 984 | hba->host->can_queue = data; |
f1498161 EL |
985 | hba->host->cmd_per_lun = data; |
986 | } | |
529e7a62 EL |
987 | } |
988 | ||
f1498161 EL |
989 | h = (struct handshake_frame *)hba->status_buffer; |
990 | h->rb_phy = cpu_to_le64(hba->dma_handle); | |
591a3a5f EL |
991 | h->req_sz = cpu_to_le16(hba->rq_size); |
992 | h->req_cnt = cpu_to_le16(hba->rq_count+1); | |
5a25ba16 | 993 | h->status_sz = cpu_to_le16(sizeof(struct status_msg)); |
591a3a5f | 994 | h->status_cnt = cpu_to_le16(hba->sts_count+1); |
5a25ba16 JG |
995 | stex_gettime(&h->hosttime); |
996 | h->partner_type = HMU_PARTNER_TYPE; | |
591a3a5f EL |
997 | if (hba->extra_offset) { |
998 | h->extra_offset = cpu_to_le32(hba->extra_offset); | |
94e9108b EL |
999 | h->extra_size = cpu_to_le32(ST_ADDITIONAL_MEM); |
1000 | } else | |
1001 | h->extra_offset = h->extra_size = 0; | |
5a25ba16 | 1002 | |
591a3a5f | 1003 | status_phys = hba->dma_handle + (hba->rq_count+1) * hba->rq_size; |
5a25ba16 JG |
1004 | writel(status_phys, base + IMR0); |
1005 | readl(base + IMR0); | |
1006 | writel((status_phys >> 16) >> 16, base + IMR1); | |
1007 | readl(base + IMR1); | |
1008 | ||
1009 | writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */ | |
1010 | readl(base + OMR0); | |
1011 | writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL); | |
1012 | readl(base + IDBL); /* flush */ | |
1013 | ||
1014 | udelay(10); | |
76fbf96f EL |
1015 | before = jiffies; |
1016 | while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) { | |
1017 | if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) { | |
1018 | printk(KERN_ERR DRV_NAME | |
1019 | "(%s): no signature after handshake frame\n", | |
1020 | pci_name(hba->pdev)); | |
1021 | return -1; | |
1022 | } | |
5a25ba16 JG |
1023 | rmb(); |
1024 | msleep(1); | |
1025 | } | |
1026 | ||
5a25ba16 JG |
1027 | writel(0, base + IMR0); |
1028 | readl(base + IMR0); | |
1029 | writel(0, base + OMR0); | |
1030 | readl(base + OMR0); | |
1031 | writel(0, base + IMR1); | |
1032 | readl(base + IMR1); | |
1033 | writel(0, base + OMR1); | |
1034 | readl(base + OMR1); /* flush */ | |
5a25ba16 JG |
1035 | return 0; |
1036 | } | |
1037 | ||
0f3f6ee6 EL |
1038 | static int stex_ss_handshake(struct st_hba *hba) |
1039 | { | |
1040 | void __iomem *base = hba->mmio_base; | |
1041 | struct st_msg_header *msg_h; | |
1042 | struct handshake_frame *h; | |
1043 | __le32 *scratch = hba->scratch; | |
1044 | u32 data; | |
1045 | unsigned long before; | |
1046 | int ret = 0; | |
1047 | ||
1048 | h = (struct handshake_frame *)(hba->alloc_rq(hba)); | |
1049 | msg_h = (struct st_msg_header *)h - 1; | |
1050 | msg_h->handle = cpu_to_le64(hba->dma_handle); | |
1051 | msg_h->flag = SS_HEAD_HANDSHAKE; | |
1052 | ||
1053 | h->rb_phy = cpu_to_le64(hba->dma_handle); | |
1054 | h->req_sz = cpu_to_le16(hba->rq_size); | |
1055 | h->req_cnt = cpu_to_le16(hba->rq_count+1); | |
1056 | h->status_sz = cpu_to_le16(sizeof(struct status_msg)); | |
1057 | h->status_cnt = cpu_to_le16(hba->sts_count+1); | |
1058 | stex_gettime(&h->hosttime); | |
1059 | h->partner_type = HMU_PARTNER_TYPE; | |
1060 | h->extra_offset = h->extra_size = 0; | |
1061 | h->scratch_size = cpu_to_le32((hba->sts_count+1)*sizeof(u32)); | |
1062 | ||
1063 | data = readl(base + YINT_EN); | |
1064 | data &= ~4; | |
1065 | writel(data, base + YINT_EN); | |
1066 | writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI); | |
1067 | writel(hba->dma_handle, base + YH2I_REQ); | |
1068 | ||
1069 | scratch = hba->scratch; | |
1070 | before = jiffies; | |
1071 | while (!(le32_to_cpu(*scratch) & SS_STS_HANDSHAKE)) { | |
1072 | if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) { | |
1073 | printk(KERN_ERR DRV_NAME | |
1074 | "(%s): no signature after handshake frame\n", | |
1075 | pci_name(hba->pdev)); | |
1076 | ret = -1; | |
1077 | break; | |
1078 | } | |
1079 | rmb(); | |
1080 | msleep(1); | |
1081 | } | |
1082 | ||
1083 | *scratch = 0; | |
1084 | msg_h->flag = 0; | |
1085 | return ret; | |
1086 | } | |
1087 | ||
1088 | static int stex_handshake(struct st_hba *hba) | |
1089 | { | |
1090 | int err; | |
1091 | unsigned long flags; | |
1092 | ||
1093 | err = (hba->cardtype == st_yel) ? | |
1094 | stex_ss_handshake(hba) : stex_common_handshake(hba); | |
1095 | if (err == 0) { | |
1096 | spin_lock_irqsave(hba->host->host_lock, flags); | |
1097 | hba->req_head = 0; | |
1098 | hba->req_tail = 0; | |
1099 | hba->status_head = 0; | |
1100 | hba->status_tail = 0; | |
1101 | hba->out_req_cnt = 0; | |
1102 | hba->mu_status = MU_STATE_STARTED; | |
1103 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
1104 | } | |
1105 | return err; | |
1106 | } | |
1107 | ||
5a25ba16 JG |
1108 | static int stex_abort(struct scsi_cmnd *cmd) |
1109 | { | |
1110 | struct Scsi_Host *host = cmd->device->host; | |
1111 | struct st_hba *hba = (struct st_hba *)host->hostdata; | |
cf355883 | 1112 | u16 tag = cmd->request->tag; |
5a25ba16 JG |
1113 | void __iomem *base; |
1114 | u32 data; | |
1115 | int result = SUCCESS; | |
1116 | unsigned long flags; | |
c25da0af EL |
1117 | |
1118 | printk(KERN_INFO DRV_NAME | |
1119 | "(%s): aborting command\n", pci_name(hba->pdev)); | |
1120 | scsi_print_command(cmd); | |
1121 | ||
5a25ba16 JG |
1122 | base = hba->mmio_base; |
1123 | spin_lock_irqsave(host->host_lock, flags); | |
cf355883 EL |
1124 | if (tag < host->can_queue && hba->ccb[tag].cmd == cmd) |
1125 | hba->wait_ccb = &hba->ccb[tag]; | |
1126 | else { | |
1127 | for (tag = 0; tag < host->can_queue; tag++) | |
1128 | if (hba->ccb[tag].cmd == cmd) { | |
1129 | hba->wait_ccb = &hba->ccb[tag]; | |
1130 | break; | |
1131 | } | |
1132 | if (tag >= host->can_queue) | |
1133 | goto out; | |
1134 | } | |
5a25ba16 | 1135 | |
0f3f6ee6 EL |
1136 | if (hba->cardtype == st_yel) { |
1137 | data = readl(base + YI2H_INT); | |
1138 | if (data == 0 || data == 0xffffffff) | |
1139 | goto fail_out; | |
5a25ba16 | 1140 | |
0f3f6ee6 EL |
1141 | writel(data, base + YI2H_INT_C); |
1142 | stex_ss_mu_intr(hba); | |
1143 | } else { | |
1144 | data = readl(base + ODBL); | |
1145 | if (data == 0 || data == 0xffffffff) | |
1146 | goto fail_out; | |
5a25ba16 | 1147 | |
0f3f6ee6 EL |
1148 | writel(data, base + ODBL); |
1149 | readl(base + ODBL); /* flush */ | |
5a25ba16 | 1150 | |
0f3f6ee6 EL |
1151 | stex_mu_intr(hba, data); |
1152 | } | |
5a25ba16 JG |
1153 | if (hba->wait_ccb == NULL) { |
1154 | printk(KERN_WARNING DRV_NAME | |
1155 | "(%s): lost interrupt\n", pci_name(hba->pdev)); | |
1156 | goto out; | |
1157 | } | |
1158 | ||
1159 | fail_out: | |
d5587d5d | 1160 | scsi_dma_unmap(cmd); |
5a25ba16 JG |
1161 | hba->wait_ccb->req = NULL; /* nullify the req's future return */ |
1162 | hba->wait_ccb = NULL; | |
1163 | result = FAILED; | |
1164 | out: | |
1165 | spin_unlock_irqrestore(host->host_lock, flags); | |
1166 | return result; | |
1167 | } | |
1168 | ||
1169 | static void stex_hard_reset(struct st_hba *hba) | |
1170 | { | |
1171 | struct pci_bus *bus; | |
1172 | int i; | |
1173 | u16 pci_cmd; | |
1174 | u8 pci_bctl; | |
1175 | ||
1176 | for (i = 0; i < 16; i++) | |
1177 | pci_read_config_dword(hba->pdev, i * 4, | |
1178 | &hba->pdev->saved_config_space[i]); | |
1179 | ||
1180 | /* Reset secondary bus. Our controller(MU/ATU) is the only device on | |
1181 | secondary bus. Consult Intel 80331/3 developer's manual for detail */ | |
1182 | bus = hba->pdev->bus; | |
1183 | pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl); | |
1184 | pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET; | |
1185 | pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl); | |
69f4a513 EL |
1186 | |
1187 | /* | |
1188 | * 1 ms may be enough for 8-port controllers. But 16-port controllers | |
1189 | * require more time to finish bus reset. Use 100 ms here for safety | |
1190 | */ | |
1191 | msleep(100); | |
5a25ba16 JG |
1192 | pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET; |
1193 | pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl); | |
1194 | ||
76fbf96f | 1195 | for (i = 0; i < MU_HARD_RESET_WAIT; i++) { |
5a25ba16 | 1196 | pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd); |
47c4f997 | 1197 | if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER)) |
5a25ba16 JG |
1198 | break; |
1199 | msleep(1); | |
1200 | } | |
1201 | ||
1202 | ssleep(5); | |
1203 | for (i = 0; i < 16; i++) | |
1204 | pci_write_config_dword(hba->pdev, i * 4, | |
1205 | hba->pdev->saved_config_space[i]); | |
1206 | } | |
1207 | ||
1208 | static int stex_reset(struct scsi_cmnd *cmd) | |
1209 | { | |
1210 | struct st_hba *hba; | |
f1498161 EL |
1211 | void __iomem *base; |
1212 | unsigned long flags, before; | |
7cfe99a5 | 1213 | |
5a25ba16 JG |
1214 | hba = (struct st_hba *) &cmd->device->host->hostdata[0]; |
1215 | ||
c25da0af EL |
1216 | printk(KERN_INFO DRV_NAME |
1217 | "(%s): resetting host\n", pci_name(hba->pdev)); | |
1218 | scsi_print_command(cmd); | |
1219 | ||
5a25ba16 JG |
1220 | hba->mu_status = MU_STATE_RESETTING; |
1221 | ||
1222 | if (hba->cardtype == st_shasta) | |
1223 | stex_hard_reset(hba); | |
1224 | ||
fb4f66be EL |
1225 | if (hba->cardtype != st_yosemite) { |
1226 | if (stex_handshake(hba)) { | |
1227 | printk(KERN_WARNING DRV_NAME | |
1228 | "(%s): resetting: handshake failed\n", | |
1229 | pci_name(hba->pdev)); | |
1230 | return FAILED; | |
1231 | } | |
fb4f66be | 1232 | return SUCCESS; |
5a25ba16 | 1233 | } |
5a25ba16 | 1234 | |
fb4f66be EL |
1235 | /* st_yosemite */ |
1236 | writel(MU_INBOUND_DOORBELL_RESET, hba->mmio_base + IDBL); | |
1237 | readl(hba->mmio_base + IDBL); /* flush */ | |
1238 | before = jiffies; | |
1239 | while (hba->out_req_cnt > 0) { | |
1240 | if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) { | |
1241 | printk(KERN_WARNING DRV_NAME | |
1242 | "(%s): reset timeout\n", pci_name(hba->pdev)); | |
1243 | return FAILED; | |
1244 | } | |
1245 | msleep(1); | |
1246 | } | |
1247 | ||
f1498161 EL |
1248 | base = hba->mmio_base; |
1249 | writel(0, base + IMR0); | |
1250 | readl(base + IMR0); | |
1251 | writel(0, base + OMR0); | |
1252 | readl(base + OMR0); | |
1253 | writel(0, base + IMR1); | |
1254 | readl(base + IMR1); | |
1255 | writel(0, base + OMR1); | |
1256 | readl(base + OMR1); /* flush */ | |
1257 | spin_lock_irqsave(hba->host->host_lock, flags); | |
1258 | hba->req_head = 0; | |
1259 | hba->req_tail = 0; | |
1260 | hba->status_head = 0; | |
1261 | hba->status_tail = 0; | |
1262 | hba->out_req_cnt = 0; | |
fb4f66be | 1263 | hba->mu_status = MU_STATE_STARTED; |
f1498161 | 1264 | spin_unlock_irqrestore(hba->host->host_lock, flags); |
5a25ba16 JG |
1265 | return SUCCESS; |
1266 | } | |
1267 | ||
1268 | static int stex_biosparam(struct scsi_device *sdev, | |
1269 | struct block_device *bdev, sector_t capacity, int geom[]) | |
1270 | { | |
b4b8bed1 | 1271 | int heads = 255, sectors = 63; |
5a25ba16 JG |
1272 | |
1273 | if (capacity < 0x200000) { | |
1274 | heads = 64; | |
1275 | sectors = 32; | |
1276 | } | |
1277 | ||
b4b8bed1 | 1278 | sector_div(capacity, heads * sectors); |
5a25ba16 JG |
1279 | |
1280 | geom[0] = heads; | |
1281 | geom[1] = sectors; | |
b4b8bed1 | 1282 | geom[2] = capacity; |
5a25ba16 JG |
1283 | |
1284 | return 0; | |
1285 | } | |
1286 | ||
1287 | static struct scsi_host_template driver_template = { | |
1288 | .module = THIS_MODULE, | |
1289 | .name = DRV_NAME, | |
1290 | .proc_name = DRV_NAME, | |
1291 | .bios_param = stex_biosparam, | |
1292 | .queuecommand = stex_queuecommand, | |
cf355883 | 1293 | .slave_alloc = stex_slave_alloc, |
5a25ba16 JG |
1294 | .slave_configure = stex_slave_config, |
1295 | .slave_destroy = stex_slave_destroy, | |
1296 | .eh_abort_handler = stex_abort, | |
1297 | .eh_host_reset_handler = stex_reset, | |
5a25ba16 | 1298 | .this_id = -1, |
591a3a5f EL |
1299 | }; |
1300 | ||
1301 | static struct pci_device_id stex_pci_tbl[] = { | |
1302 | /* st_shasta */ | |
1303 | { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1304 | st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */ | |
1305 | { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1306 | st_shasta }, /* SuperTrak EX12350 */ | |
1307 | { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1308 | st_shasta }, /* SuperTrak EX4350 */ | |
1309 | { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1310 | st_shasta }, /* SuperTrak EX24350 */ | |
1311 | ||
1312 | /* st_vsc */ | |
1313 | { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc }, | |
1314 | ||
1315 | /* st_yosemite */ | |
0f3f6ee6 | 1316 | { 0x105a, 0x8650, 0x105a, PCI_ANY_ID, 0, 0, st_yosemite }, |
591a3a5f EL |
1317 | |
1318 | /* st_seq */ | |
1319 | { 0x105a, 0x3360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_seq }, | |
0f3f6ee6 EL |
1320 | |
1321 | /* st_yel */ | |
1322 | { 0x105a, 0x8650, 0x1033, PCI_ANY_ID, 0, 0, st_yel }, | |
1323 | { 0x105a, 0x8760, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_yel }, | |
591a3a5f EL |
1324 | { } /* terminate list */ |
1325 | }; | |
1326 | ||
1327 | static struct st_card_info stex_card_info[] = { | |
1328 | /* st_shasta */ | |
1329 | { | |
1330 | .max_id = 17, | |
1331 | .max_lun = 8, | |
1332 | .max_channel = 0, | |
1333 | .rq_count = 32, | |
1334 | .rq_size = 1048, | |
1335 | .sts_count = 32, | |
0f3f6ee6 EL |
1336 | .alloc_rq = stex_alloc_req, |
1337 | .map_sg = stex_map_sg, | |
1338 | .send = stex_send_cmd, | |
591a3a5f EL |
1339 | }, |
1340 | ||
1341 | /* st_vsc */ | |
1342 | { | |
1343 | .max_id = 129, | |
1344 | .max_lun = 1, | |
1345 | .max_channel = 0, | |
1346 | .rq_count = 32, | |
1347 | .rq_size = 1048, | |
1348 | .sts_count = 32, | |
0f3f6ee6 EL |
1349 | .alloc_rq = stex_alloc_req, |
1350 | .map_sg = stex_map_sg, | |
1351 | .send = stex_send_cmd, | |
591a3a5f EL |
1352 | }, |
1353 | ||
1354 | /* st_yosemite */ | |
1355 | { | |
1356 | .max_id = 2, | |
1357 | .max_lun = 256, | |
1358 | .max_channel = 0, | |
1359 | .rq_count = 256, | |
1360 | .rq_size = 1048, | |
1361 | .sts_count = 256, | |
0f3f6ee6 EL |
1362 | .alloc_rq = stex_alloc_req, |
1363 | .map_sg = stex_map_sg, | |
1364 | .send = stex_send_cmd, | |
591a3a5f EL |
1365 | }, |
1366 | ||
1367 | /* st_seq */ | |
1368 | { | |
1369 | .max_id = 129, | |
1370 | .max_lun = 1, | |
1371 | .max_channel = 0, | |
1372 | .rq_count = 32, | |
1373 | .rq_size = 1048, | |
1374 | .sts_count = 32, | |
0f3f6ee6 EL |
1375 | .alloc_rq = stex_alloc_req, |
1376 | .map_sg = stex_map_sg, | |
1377 | .send = stex_send_cmd, | |
1378 | }, | |
1379 | ||
1380 | /* st_yel */ | |
1381 | { | |
1382 | .max_id = 129, | |
1383 | .max_lun = 256, | |
1384 | .max_channel = 3, | |
1385 | .rq_count = 801, | |
1386 | .rq_size = 512, | |
1387 | .sts_count = 801, | |
1388 | .alloc_rq = stex_ss_alloc_req, | |
1389 | .map_sg = stex_ss_map_sg, | |
1390 | .send = stex_ss_send_cmd, | |
591a3a5f | 1391 | }, |
5a25ba16 JG |
1392 | }; |
1393 | ||
1394 | static int stex_set_dma_mask(struct pci_dev * pdev) | |
1395 | { | |
1396 | int ret; | |
7cfe99a5 | 1397 | |
6a35528a YH |
1398 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) |
1399 | && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) | |
5a25ba16 | 1400 | return 0; |
284901a9 | 1401 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
5a25ba16 | 1402 | if (!ret) |
284901a9 | 1403 | ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
5a25ba16 JG |
1404 | return ret; |
1405 | } | |
1406 | ||
99946f81 EL |
1407 | static int stex_request_irq(struct st_hba *hba) |
1408 | { | |
1409 | struct pci_dev *pdev = hba->pdev; | |
1410 | int status; | |
1411 | ||
1412 | if (msi) { | |
1413 | status = pci_enable_msi(pdev); | |
1414 | if (status != 0) | |
1415 | printk(KERN_ERR DRV_NAME | |
1416 | "(%s): error %d setting up MSI\n", | |
1417 | pci_name(pdev), status); | |
1418 | else | |
1419 | hba->msi_enabled = 1; | |
1420 | } else | |
1421 | hba->msi_enabled = 0; | |
1422 | ||
0f3f6ee6 EL |
1423 | status = request_irq(pdev->irq, hba->cardtype == st_yel ? |
1424 | stex_ss_intr : stex_intr, IRQF_SHARED, DRV_NAME, hba); | |
99946f81 EL |
1425 | |
1426 | if (status != 0) { | |
1427 | if (hba->msi_enabled) | |
1428 | pci_disable_msi(pdev); | |
1429 | } | |
1430 | return status; | |
1431 | } | |
1432 | ||
1433 | static void stex_free_irq(struct st_hba *hba) | |
1434 | { | |
1435 | struct pci_dev *pdev = hba->pdev; | |
1436 | ||
1437 | free_irq(pdev->irq, hba); | |
1438 | if (hba->msi_enabled) | |
1439 | pci_disable_msi(pdev); | |
1440 | } | |
1441 | ||
5a25ba16 JG |
1442 | static int __devinit |
1443 | stex_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |
1444 | { | |
1445 | struct st_hba *hba; | |
1446 | struct Scsi_Host *host; | |
591a3a5f | 1447 | const struct st_card_info *ci = NULL; |
0f3f6ee6 | 1448 | u32 sts_offset, cp_offset, scratch_offset; |
5a25ba16 JG |
1449 | int err; |
1450 | ||
1451 | err = pci_enable_device(pdev); | |
1452 | if (err) | |
1453 | return err; | |
1454 | ||
1455 | pci_set_master(pdev); | |
1456 | ||
1457 | host = scsi_host_alloc(&driver_template, sizeof(struct st_hba)); | |
1458 | ||
1459 | if (!host) { | |
1460 | printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n", | |
1461 | pci_name(pdev)); | |
1462 | err = -ENOMEM; | |
1463 | goto out_disable; | |
1464 | } | |
1465 | ||
1466 | hba = (struct st_hba *)host->hostdata; | |
1467 | memset(hba, 0, sizeof(struct st_hba)); | |
1468 | ||
1469 | err = pci_request_regions(pdev, DRV_NAME); | |
1470 | if (err < 0) { | |
1471 | printk(KERN_ERR DRV_NAME "(%s): request regions failed\n", | |
1472 | pci_name(pdev)); | |
1473 | goto out_scsi_host_put; | |
1474 | } | |
1475 | ||
25729a7f | 1476 | hba->mmio_base = pci_ioremap_bar(pdev, 0); |
5a25ba16 JG |
1477 | if ( !hba->mmio_base) { |
1478 | printk(KERN_ERR DRV_NAME "(%s): memory map failed\n", | |
1479 | pci_name(pdev)); | |
1480 | err = -ENOMEM; | |
1481 | goto out_release_regions; | |
1482 | } | |
1483 | ||
1484 | err = stex_set_dma_mask(pdev); | |
1485 | if (err) { | |
1486 | printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n", | |
1487 | pci_name(pdev)); | |
1488 | goto out_iounmap; | |
1489 | } | |
1490 | ||
94e9108b | 1491 | hba->cardtype = (unsigned int) id->driver_data; |
591a3a5f | 1492 | ci = &stex_card_info[hba->cardtype]; |
0f3f6ee6 EL |
1493 | sts_offset = scratch_offset = (ci->rq_count+1) * ci->rq_size; |
1494 | if (hba->cardtype == st_yel) | |
1495 | sts_offset += (ci->sts_count+1) * sizeof(u32); | |
591a3a5f EL |
1496 | cp_offset = sts_offset + (ci->sts_count+1) * sizeof(struct status_msg); |
1497 | hba->dma_size = cp_offset + sizeof(struct st_frame); | |
1498 | if (hba->cardtype == st_seq || | |
1499 | (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) { | |
1500 | hba->extra_offset = hba->dma_size; | |
1501 | hba->dma_size += ST_ADDITIONAL_MEM; | |
1502 | } | |
5a25ba16 | 1503 | hba->dma_mem = dma_alloc_coherent(&pdev->dev, |
94e9108b | 1504 | hba->dma_size, &hba->dma_handle, GFP_KERNEL); |
5a25ba16 JG |
1505 | if (!hba->dma_mem) { |
1506 | err = -ENOMEM; | |
1507 | printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n", | |
1508 | pci_name(pdev)); | |
1509 | goto out_iounmap; | |
1510 | } | |
1511 | ||
591a3a5f EL |
1512 | hba->ccb = kcalloc(ci->rq_count, sizeof(struct st_ccb), GFP_KERNEL); |
1513 | if (!hba->ccb) { | |
1514 | err = -ENOMEM; | |
1515 | printk(KERN_ERR DRV_NAME "(%s): ccb alloc failed\n", | |
1516 | pci_name(pdev)); | |
1517 | goto out_pci_free; | |
1518 | } | |
1519 | ||
0f3f6ee6 EL |
1520 | if (hba->cardtype == st_yel) |
1521 | hba->scratch = (__le32 *)(hba->dma_mem + scratch_offset); | |
591a3a5f EL |
1522 | hba->status_buffer = (struct status_msg *)(hba->dma_mem + sts_offset); |
1523 | hba->copy_buffer = hba->dma_mem + cp_offset; | |
1524 | hba->rq_count = ci->rq_count; | |
1525 | hba->rq_size = ci->rq_size; | |
1526 | hba->sts_count = ci->sts_count; | |
0f3f6ee6 EL |
1527 | hba->alloc_rq = ci->alloc_rq; |
1528 | hba->map_sg = ci->map_sg; | |
1529 | hba->send = ci->send; | |
5a25ba16 JG |
1530 | hba->mu_status = MU_STATE_STARTING; |
1531 | ||
0f3f6ee6 EL |
1532 | if (hba->cardtype == st_yel) |
1533 | host->sg_tablesize = 38; | |
1534 | else | |
1535 | host->sg_tablesize = 32; | |
591a3a5f EL |
1536 | host->can_queue = ci->rq_count; |
1537 | host->cmd_per_lun = ci->rq_count; | |
1538 | host->max_id = ci->max_id; | |
1539 | host->max_lun = ci->max_lun; | |
1540 | host->max_channel = ci->max_channel; | |
5a25ba16 JG |
1541 | host->unique_id = host->host_no; |
1542 | host->max_cmd_len = STEX_CDB_LENGTH; | |
1543 | ||
1544 | hba->host = host; | |
1545 | hba->pdev = pdev; | |
5a25ba16 | 1546 | |
99946f81 | 1547 | err = stex_request_irq(hba); |
5a25ba16 JG |
1548 | if (err) { |
1549 | printk(KERN_ERR DRV_NAME "(%s): request irq failed\n", | |
1550 | pci_name(pdev)); | |
591a3a5f | 1551 | goto out_ccb_free; |
5a25ba16 JG |
1552 | } |
1553 | ||
1554 | err = stex_handshake(hba); | |
1555 | if (err) | |
1556 | goto out_free_irq; | |
1557 | ||
529e7a62 | 1558 | err = scsi_init_shared_tag_map(host, host->can_queue); |
deb81d80 | 1559 | if (err) { |
cf355883 EL |
1560 | printk(KERN_ERR DRV_NAME "(%s): init shared queue failed\n", |
1561 | pci_name(pdev)); | |
1562 | goto out_free_irq; | |
1563 | } | |
1564 | ||
5a25ba16 JG |
1565 | pci_set_drvdata(pdev, hba); |
1566 | ||
1567 | err = scsi_add_host(host, &pdev->dev); | |
1568 | if (err) { | |
1569 | printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n", | |
1570 | pci_name(pdev)); | |
1571 | goto out_free_irq; | |
1572 | } | |
1573 | ||
1574 | scsi_scan_host(host); | |
1575 | ||
1576 | return 0; | |
1577 | ||
1578 | out_free_irq: | |
99946f81 | 1579 | stex_free_irq(hba); |
591a3a5f EL |
1580 | out_ccb_free: |
1581 | kfree(hba->ccb); | |
5a25ba16 | 1582 | out_pci_free: |
94e9108b | 1583 | dma_free_coherent(&pdev->dev, hba->dma_size, |
5a25ba16 JG |
1584 | hba->dma_mem, hba->dma_handle); |
1585 | out_iounmap: | |
1586 | iounmap(hba->mmio_base); | |
1587 | out_release_regions: | |
1588 | pci_release_regions(pdev); | |
1589 | out_scsi_host_put: | |
1590 | scsi_host_put(host); | |
1591 | out_disable: | |
1592 | pci_disable_device(pdev); | |
1593 | ||
1594 | return err; | |
1595 | } | |
1596 | ||
1597 | static void stex_hba_stop(struct st_hba *hba) | |
1598 | { | |
1599 | struct req_msg *req; | |
0f3f6ee6 | 1600 | struct st_msg_header *msg_h; |
5a25ba16 JG |
1601 | unsigned long flags; |
1602 | unsigned long before; | |
cf355883 | 1603 | u16 tag = 0; |
5a25ba16 JG |
1604 | |
1605 | spin_lock_irqsave(hba->host->host_lock, flags); | |
0f3f6ee6 EL |
1606 | req = hba->alloc_rq(hba); |
1607 | if (hba->cardtype == st_yel) { | |
1608 | msg_h = (struct st_msg_header *)req - 1; | |
1609 | memset(msg_h, 0, hba->rq_size); | |
1610 | } else | |
1611 | memset(req, 0, hba->rq_size); | |
5a25ba16 | 1612 | |
0f3f6ee6 | 1613 | if (hba->cardtype == st_yosemite || hba->cardtype == st_yel) { |
fb4f66be EL |
1614 | req->cdb[0] = MGT_CMD; |
1615 | req->cdb[1] = MGT_CMD_SIGNATURE; | |
1616 | req->cdb[2] = CTLR_CONFIG_CMD; | |
1617 | req->cdb[3] = CTLR_SHUTDOWN; | |
1618 | } else { | |
1619 | req->cdb[0] = CONTROLLER_CMD; | |
1620 | req->cdb[1] = CTLR_POWER_STATE_CHANGE; | |
1621 | req->cdb[2] = CTLR_POWER_SAVING; | |
1622 | } | |
5a25ba16 JG |
1623 | |
1624 | hba->ccb[tag].cmd = NULL; | |
1625 | hba->ccb[tag].sg_count = 0; | |
1626 | hba->ccb[tag].sense_bufflen = 0; | |
1627 | hba->ccb[tag].sense_buffer = NULL; | |
f1498161 | 1628 | hba->ccb[tag].req_type = PASSTHRU_REQ_TYPE; |
5a25ba16 | 1629 | |
0f3f6ee6 | 1630 | hba->send(hba, req, tag); |
5a25ba16 JG |
1631 | spin_unlock_irqrestore(hba->host->host_lock, flags); |
1632 | ||
cf355883 EL |
1633 | before = jiffies; |
1634 | while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) { | |
f1498161 EL |
1635 | if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) { |
1636 | hba->ccb[tag].req_type = 0; | |
cf355883 | 1637 | return; |
f1498161 EL |
1638 | } |
1639 | msleep(1); | |
cf355883 | 1640 | } |
5a25ba16 JG |
1641 | } |
1642 | ||
1643 | static void stex_hba_free(struct st_hba *hba) | |
1644 | { | |
99946f81 | 1645 | stex_free_irq(hba); |
5a25ba16 JG |
1646 | |
1647 | iounmap(hba->mmio_base); | |
1648 | ||
1649 | pci_release_regions(hba->pdev); | |
1650 | ||
591a3a5f EL |
1651 | kfree(hba->ccb); |
1652 | ||
94e9108b | 1653 | dma_free_coherent(&hba->pdev->dev, hba->dma_size, |
5a25ba16 JG |
1654 | hba->dma_mem, hba->dma_handle); |
1655 | } | |
1656 | ||
1657 | static void stex_remove(struct pci_dev *pdev) | |
1658 | { | |
1659 | struct st_hba *hba = pci_get_drvdata(pdev); | |
1660 | ||
1661 | scsi_remove_host(hba->host); | |
1662 | ||
1663 | pci_set_drvdata(pdev, NULL); | |
1664 | ||
1665 | stex_hba_stop(hba); | |
1666 | ||
1667 | stex_hba_free(hba); | |
1668 | ||
1669 | scsi_host_put(hba->host); | |
1670 | ||
1671 | pci_disable_device(pdev); | |
1672 | } | |
1673 | ||
1674 | static void stex_shutdown(struct pci_dev *pdev) | |
1675 | { | |
1676 | struct st_hba *hba = pci_get_drvdata(pdev); | |
1677 | ||
1678 | stex_hba_stop(hba); | |
1679 | } | |
1680 | ||
5a25ba16 JG |
1681 | MODULE_DEVICE_TABLE(pci, stex_pci_tbl); |
1682 | ||
1683 | static struct pci_driver stex_pci_driver = { | |
1684 | .name = DRV_NAME, | |
1685 | .id_table = stex_pci_tbl, | |
1686 | .probe = stex_probe, | |
1687 | .remove = __devexit_p(stex_remove), | |
1688 | .shutdown = stex_shutdown, | |
1689 | }; | |
1690 | ||
1691 | static int __init stex_init(void) | |
1692 | { | |
1693 | printk(KERN_INFO DRV_NAME | |
1694 | ": Promise SuperTrak EX Driver version: %s\n", | |
1695 | ST_DRIVER_VERSION); | |
1696 | ||
1697 | return pci_register_driver(&stex_pci_driver); | |
1698 | } | |
1699 | ||
1700 | static void __exit stex_exit(void) | |
1701 | { | |
1702 | pci_unregister_driver(&stex_pci_driver); | |
1703 | } | |
1704 | ||
1705 | module_init(stex_init); | |
1706 | module_exit(stex_exit); |