Commit | Line | Data |
---|---|---|
7a3e97b0 | 1 | /* |
e0eca63e | 2 | * Universal Flash Storage Host controller driver Core |
7a3e97b0 SY |
3 | * |
4 | * This code is based on drivers/scsi/ufs/ufshcd.c | |
3b1d0580 | 5 | * Copyright (C) 2011-2013 Samsung India Software Operations |
5c0c28a8 | 6 | * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. |
7a3e97b0 | 7 | * |
3b1d0580 VH |
8 | * Authors: |
9 | * Santosh Yaraganavi <santosh.sy@samsung.com> | |
10 | * Vinayak Holikatti <h.vinayak@samsung.com> | |
7a3e97b0 SY |
11 | * |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License | |
14 | * as published by the Free Software Foundation; either version 2 | |
15 | * of the License, or (at your option) any later version. | |
3b1d0580 VH |
16 | * See the COPYING file in the top-level directory or visit |
17 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
7a3e97b0 SY |
18 | * |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
3b1d0580 VH |
24 | * This program is provided "AS IS" and "WITH ALL FAULTS" and |
25 | * without warranty of any kind. You are solely responsible for | |
26 | * determining the appropriateness of using and distributing | |
27 | * the program and assume all risks associated with your exercise | |
28 | * of rights with respect to the program, including but not limited | |
29 | * to infringement of third party rights, the risks and costs of | |
30 | * program errors, damage to or loss of data, programs or equipment, | |
31 | * and unavailability or interruption of operations. Under no | |
32 | * circumstances will the contributor of this Program be liable for | |
33 | * any damages of any kind arising from your use or distribution of | |
34 | * this program. | |
5c0c28a8 SRT |
35 | * |
36 | * The Linux Foundation chooses to take subject only to the GPLv2 | |
37 | * license terms, and distributes only under these terms. | |
7a3e97b0 SY |
38 | */ |
39 | ||
6ccf44fe | 40 | #include <linux/async.h> |
856b3483 | 41 | #include <linux/devfreq.h> |
6ccf44fe | 42 | |
e0eca63e | 43 | #include "ufshcd.h" |
53b3d9c3 | 44 | #include "unipro.h" |
7a3e97b0 | 45 | |
2fbd009b SJ |
46 | #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\ |
47 | UTP_TASK_REQ_COMPL |\ | |
48 | UFSHCD_ERROR_MASK) | |
6ccf44fe SJ |
49 | /* UIC command timeout, unit: ms */ |
50 | #define UIC_CMD_TIMEOUT 500 | |
2fbd009b | 51 | |
5a0b0cb9 SRT |
52 | /* NOP OUT retries waiting for NOP IN response */ |
53 | #define NOP_OUT_RETRIES 10 | |
54 | /* Timeout after 30 msecs if NOP OUT hangs without response */ | |
55 | #define NOP_OUT_TIMEOUT 30 /* msecs */ | |
56 | ||
68078d5c DR |
57 | /* Query request retries */ |
58 | #define QUERY_REQ_RETRIES 10 | |
59 | /* Query request timeout */ | |
60 | #define QUERY_REQ_TIMEOUT 30 /* msec */ | |
61 | ||
e2933132 SRT |
62 | /* Task management command timeout */ |
63 | #define TM_CMD_TIMEOUT 100 /* msecs */ | |
64 | ||
1d337ec2 SRT |
65 | /* maximum number of link-startup retries */ |
66 | #define DME_LINKSTARTUP_RETRIES 3 | |
67 | ||
68 | /* maximum number of reset retries before giving up */ | |
69 | #define MAX_HOST_RESET_RETRIES 5 | |
70 | ||
68078d5c DR |
71 | /* Expose the flag value from utp_upiu_query.value */ |
72 | #define MASK_QUERY_UPIU_FLAG_LOC 0xFF | |
73 | ||
7d568652 SJ |
74 | /* Interrupt aggregation default timeout, unit: 40us */ |
75 | #define INT_AGGR_DEF_TO 0x02 | |
76 | ||
aa497613 SRT |
77 | #define ufshcd_toggle_vreg(_dev, _vreg, _on) \ |
78 | ({ \ | |
79 | int _ret; \ | |
80 | if (_on) \ | |
81 | _ret = ufshcd_enable_vreg(_dev, _vreg); \ | |
82 | else \ | |
83 | _ret = ufshcd_disable_vreg(_dev, _vreg); \ | |
84 | _ret; \ | |
85 | }) | |
86 | ||
da461cec SJ |
87 | static u32 ufs_query_desc_max_size[] = { |
88 | QUERY_DESC_DEVICE_MAX_SIZE, | |
89 | QUERY_DESC_CONFIGURAION_MAX_SIZE, | |
90 | QUERY_DESC_UNIT_MAX_SIZE, | |
91 | QUERY_DESC_RFU_MAX_SIZE, | |
92 | QUERY_DESC_INTERCONNECT_MAX_SIZE, | |
93 | QUERY_DESC_STRING_MAX_SIZE, | |
94 | QUERY_DESC_RFU_MAX_SIZE, | |
95 | QUERY_DESC_GEOMETRY_MAZ_SIZE, | |
96 | QUERY_DESC_POWER_MAX_SIZE, | |
97 | QUERY_DESC_RFU_MAX_SIZE, | |
98 | }; | |
99 | ||
7a3e97b0 SY |
100 | enum { |
101 | UFSHCD_MAX_CHANNEL = 0, | |
102 | UFSHCD_MAX_ID = 1, | |
7a3e97b0 SY |
103 | UFSHCD_CMD_PER_LUN = 32, |
104 | UFSHCD_CAN_QUEUE = 32, | |
105 | }; | |
106 | ||
107 | /* UFSHCD states */ | |
108 | enum { | |
7a3e97b0 SY |
109 | UFSHCD_STATE_RESET, |
110 | UFSHCD_STATE_ERROR, | |
3441da7d SRT |
111 | UFSHCD_STATE_OPERATIONAL, |
112 | }; | |
113 | ||
114 | /* UFSHCD error handling flags */ | |
115 | enum { | |
116 | UFSHCD_EH_IN_PROGRESS = (1 << 0), | |
7a3e97b0 SY |
117 | }; |
118 | ||
e8e7f271 SRT |
119 | /* UFSHCD UIC layer error flags */ |
120 | enum { | |
121 | UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */ | |
122 | UFSHCD_UIC_NL_ERROR = (1 << 1), /* Network layer error */ | |
123 | UFSHCD_UIC_TL_ERROR = (1 << 2), /* Transport Layer error */ | |
124 | UFSHCD_UIC_DME_ERROR = (1 << 3), /* DME error */ | |
125 | }; | |
126 | ||
7a3e97b0 SY |
127 | /* Interrupt configuration options */ |
128 | enum { | |
129 | UFSHCD_INT_DISABLE, | |
130 | UFSHCD_INT_ENABLE, | |
131 | UFSHCD_INT_CLEAR, | |
132 | }; | |
133 | ||
3441da7d SRT |
134 | #define ufshcd_set_eh_in_progress(h) \ |
135 | (h->eh_flags |= UFSHCD_EH_IN_PROGRESS) | |
136 | #define ufshcd_eh_in_progress(h) \ | |
137 | (h->eh_flags & UFSHCD_EH_IN_PROGRESS) | |
138 | #define ufshcd_clear_eh_in_progress(h) \ | |
139 | (h->eh_flags &= ~UFSHCD_EH_IN_PROGRESS) | |
140 | ||
57d104c1 SJ |
141 | #define ufshcd_set_ufs_dev_active(h) \ |
142 | ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE) | |
143 | #define ufshcd_set_ufs_dev_sleep(h) \ | |
144 | ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE) | |
145 | #define ufshcd_set_ufs_dev_poweroff(h) \ | |
146 | ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE) | |
147 | #define ufshcd_is_ufs_dev_active(h) \ | |
148 | ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE) | |
149 | #define ufshcd_is_ufs_dev_sleep(h) \ | |
150 | ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE) | |
151 | #define ufshcd_is_ufs_dev_poweroff(h) \ | |
152 | ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE) | |
153 | ||
154 | static struct ufs_pm_lvl_states ufs_pm_lvl_states[] = { | |
155 | {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE}, | |
156 | {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE}, | |
157 | {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE}, | |
158 | {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE}, | |
159 | {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE}, | |
160 | {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE}, | |
161 | }; | |
162 | ||
163 | static inline enum ufs_dev_pwr_mode | |
164 | ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl) | |
165 | { | |
166 | return ufs_pm_lvl_states[lvl].dev_state; | |
167 | } | |
168 | ||
169 | static inline enum uic_link_state | |
170 | ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl) | |
171 | { | |
172 | return ufs_pm_lvl_states[lvl].link_state; | |
173 | } | |
174 | ||
3441da7d SRT |
175 | static void ufshcd_tmc_handler(struct ufs_hba *hba); |
176 | static void ufshcd_async_scan(void *data, async_cookie_t cookie); | |
e8e7f271 SRT |
177 | static int ufshcd_reset_and_restore(struct ufs_hba *hba); |
178 | static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag); | |
1d337ec2 SRT |
179 | static void ufshcd_hba_exit(struct ufs_hba *hba); |
180 | static int ufshcd_probe_hba(struct ufs_hba *hba); | |
1ab27c9c ST |
181 | static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on, |
182 | bool skip_ref_clk); | |
183 | static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on); | |
184 | static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba); | |
185 | static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba); | |
cad2e03d | 186 | static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba); |
57d104c1 SJ |
187 | static int ufshcd_host_reset_and_restore(struct ufs_hba *hba); |
188 | static irqreturn_t ufshcd_intr(int irq, void *__hba); | |
7eb584db DR |
189 | static int ufshcd_config_pwr_mode(struct ufs_hba *hba, |
190 | struct ufs_pa_layer_attr *desired_pwr_mode); | |
874237f7 YG |
191 | static int ufshcd_change_power_mode(struct ufs_hba *hba, |
192 | struct ufs_pa_layer_attr *pwr_mode); | |
57d104c1 SJ |
193 | |
194 | static inline int ufshcd_enable_irq(struct ufs_hba *hba) | |
195 | { | |
196 | int ret = 0; | |
197 | ||
198 | if (!hba->is_irq_enabled) { | |
199 | ret = request_irq(hba->irq, ufshcd_intr, IRQF_SHARED, UFSHCD, | |
200 | hba); | |
201 | if (ret) | |
202 | dev_err(hba->dev, "%s: request_irq failed, ret=%d\n", | |
203 | __func__, ret); | |
204 | hba->is_irq_enabled = true; | |
205 | } | |
206 | ||
207 | return ret; | |
208 | } | |
209 | ||
210 | static inline void ufshcd_disable_irq(struct ufs_hba *hba) | |
211 | { | |
212 | if (hba->is_irq_enabled) { | |
213 | free_irq(hba->irq, hba); | |
214 | hba->is_irq_enabled = false; | |
215 | } | |
216 | } | |
3441da7d | 217 | |
5a0b0cb9 SRT |
218 | /* |
219 | * ufshcd_wait_for_register - wait for register value to change | |
220 | * @hba - per-adapter interface | |
221 | * @reg - mmio register offset | |
222 | * @mask - mask to apply to read register value | |
223 | * @val - wait condition | |
224 | * @interval_us - polling interval in microsecs | |
225 | * @timeout_ms - timeout in millisecs | |
226 | * | |
227 | * Returns -ETIMEDOUT on error, zero on success | |
228 | */ | |
229 | static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, | |
230 | u32 val, unsigned long interval_us, unsigned long timeout_ms) | |
231 | { | |
232 | int err = 0; | |
233 | unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); | |
234 | ||
235 | /* ignore bits that we don't intend to wait on */ | |
236 | val = val & mask; | |
237 | ||
238 | while ((ufshcd_readl(hba, reg) & mask) != val) { | |
239 | /* wakeup within 50us of expiry */ | |
240 | usleep_range(interval_us, interval_us + 50); | |
241 | ||
242 | if (time_after(jiffies, timeout)) { | |
243 | if ((ufshcd_readl(hba, reg) & mask) != val) | |
244 | err = -ETIMEDOUT; | |
245 | break; | |
246 | } | |
247 | } | |
248 | ||
249 | return err; | |
250 | } | |
251 | ||
2fbd009b SJ |
252 | /** |
253 | * ufshcd_get_intr_mask - Get the interrupt bit mask | |
254 | * @hba - Pointer to adapter instance | |
255 | * | |
256 | * Returns interrupt bit mask per version | |
257 | */ | |
258 | static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba) | |
259 | { | |
260 | if (hba->ufs_version == UFSHCI_VERSION_10) | |
261 | return INTERRUPT_MASK_ALL_VER_10; | |
262 | else | |
263 | return INTERRUPT_MASK_ALL_VER_11; | |
264 | } | |
265 | ||
7a3e97b0 SY |
266 | /** |
267 | * ufshcd_get_ufs_version - Get the UFS version supported by the HBA | |
268 | * @hba - Pointer to adapter instance | |
269 | * | |
270 | * Returns UFSHCI version supported by the controller | |
271 | */ | |
272 | static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba) | |
273 | { | |
9949e702 YG |
274 | if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION) { |
275 | if (hba->vops && hba->vops->get_ufs_hci_version) | |
276 | return hba->vops->get_ufs_hci_version(hba); | |
277 | } | |
278 | ||
b873a275 | 279 | return ufshcd_readl(hba, REG_UFS_VERSION); |
7a3e97b0 SY |
280 | } |
281 | ||
282 | /** | |
283 | * ufshcd_is_device_present - Check if any device connected to | |
284 | * the host controller | |
5c0c28a8 | 285 | * @hba: pointer to adapter instance |
7a3e97b0 | 286 | * |
73ec513a | 287 | * Returns 1 if device present, 0 if no device detected |
7a3e97b0 | 288 | */ |
5c0c28a8 | 289 | static inline int ufshcd_is_device_present(struct ufs_hba *hba) |
7a3e97b0 | 290 | { |
5c0c28a8 SRT |
291 | return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & |
292 | DEVICE_PRESENT) ? 1 : 0; | |
7a3e97b0 SY |
293 | } |
294 | ||
295 | /** | |
296 | * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status | |
297 | * @lrb: pointer to local command reference block | |
298 | * | |
299 | * This function is used to get the OCS field from UTRD | |
300 | * Returns the OCS field in the UTRD | |
301 | */ | |
302 | static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp) | |
303 | { | |
e8c8e82a | 304 | return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS; |
7a3e97b0 SY |
305 | } |
306 | ||
307 | /** | |
308 | * ufshcd_get_tmr_ocs - Get the UTMRD Overall Command Status | |
309 | * @task_req_descp: pointer to utp_task_req_desc structure | |
310 | * | |
311 | * This function is used to get the OCS field from UTMRD | |
312 | * Returns the OCS field in the UTMRD | |
313 | */ | |
314 | static inline int | |
315 | ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp) | |
316 | { | |
e8c8e82a | 317 | return le32_to_cpu(task_req_descp->header.dword_2) & MASK_OCS; |
7a3e97b0 SY |
318 | } |
319 | ||
320 | /** | |
321 | * ufshcd_get_tm_free_slot - get a free slot for task management request | |
322 | * @hba: per adapter instance | |
e2933132 | 323 | * @free_slot: pointer to variable with available slot value |
7a3e97b0 | 324 | * |
e2933132 SRT |
325 | * Get a free tag and lock it until ufshcd_put_tm_slot() is called. |
326 | * Returns 0 if free slot is not available, else return 1 with tag value | |
327 | * in @free_slot. | |
7a3e97b0 | 328 | */ |
e2933132 | 329 | static bool ufshcd_get_tm_free_slot(struct ufs_hba *hba, int *free_slot) |
7a3e97b0 | 330 | { |
e2933132 SRT |
331 | int tag; |
332 | bool ret = false; | |
333 | ||
334 | if (!free_slot) | |
335 | goto out; | |
336 | ||
337 | do { | |
338 | tag = find_first_zero_bit(&hba->tm_slots_in_use, hba->nutmrs); | |
339 | if (tag >= hba->nutmrs) | |
340 | goto out; | |
341 | } while (test_and_set_bit_lock(tag, &hba->tm_slots_in_use)); | |
342 | ||
343 | *free_slot = tag; | |
344 | ret = true; | |
345 | out: | |
346 | return ret; | |
347 | } | |
348 | ||
349 | static inline void ufshcd_put_tm_slot(struct ufs_hba *hba, int slot) | |
350 | { | |
351 | clear_bit_unlock(slot, &hba->tm_slots_in_use); | |
7a3e97b0 SY |
352 | } |
353 | ||
354 | /** | |
355 | * ufshcd_utrl_clear - Clear a bit in UTRLCLR register | |
356 | * @hba: per adapter instance | |
357 | * @pos: position of the bit to be cleared | |
358 | */ | |
359 | static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos) | |
360 | { | |
b873a275 | 361 | ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR); |
7a3e97b0 SY |
362 | } |
363 | ||
364 | /** | |
365 | * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY | |
366 | * @reg: Register value of host controller status | |
367 | * | |
368 | * Returns integer, 0 on Success and positive value if failed | |
369 | */ | |
370 | static inline int ufshcd_get_lists_status(u32 reg) | |
371 | { | |
372 | /* | |
373 | * The mask 0xFF is for the following HCS register bits | |
374 | * Bit Description | |
375 | * 0 Device Present | |
376 | * 1 UTRLRDY | |
377 | * 2 UTMRLRDY | |
378 | * 3 UCRDY | |
379 | * 4 HEI | |
380 | * 5 DEI | |
381 | * 6-7 reserved | |
382 | */ | |
383 | return (((reg) & (0xFF)) >> 1) ^ (0x07); | |
384 | } | |
385 | ||
386 | /** | |
387 | * ufshcd_get_uic_cmd_result - Get the UIC command result | |
388 | * @hba: Pointer to adapter instance | |
389 | * | |
390 | * This function gets the result of UIC command completion | |
391 | * Returns 0 on success, non zero value on error | |
392 | */ | |
393 | static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba) | |
394 | { | |
b873a275 | 395 | return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) & |
7a3e97b0 SY |
396 | MASK_UIC_COMMAND_RESULT; |
397 | } | |
398 | ||
12b4fdb4 SJ |
399 | /** |
400 | * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command | |
401 | * @hba: Pointer to adapter instance | |
402 | * | |
403 | * This function gets UIC command argument3 | |
404 | * Returns 0 on success, non zero value on error | |
405 | */ | |
406 | static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba) | |
407 | { | |
408 | return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3); | |
409 | } | |
410 | ||
7a3e97b0 | 411 | /** |
5a0b0cb9 | 412 | * ufshcd_get_req_rsp - returns the TR response transaction type |
7a3e97b0 | 413 | * @ucd_rsp_ptr: pointer to response UPIU |
7a3e97b0 SY |
414 | */ |
415 | static inline int | |
5a0b0cb9 | 416 | ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr) |
7a3e97b0 | 417 | { |
5a0b0cb9 | 418 | return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24; |
7a3e97b0 SY |
419 | } |
420 | ||
421 | /** | |
422 | * ufshcd_get_rsp_upiu_result - Get the result from response UPIU | |
423 | * @ucd_rsp_ptr: pointer to response UPIU | |
424 | * | |
425 | * This function gets the response status and scsi_status from response UPIU | |
426 | * Returns the response result code. | |
427 | */ | |
428 | static inline int | |
429 | ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr) | |
430 | { | |
431 | return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT; | |
432 | } | |
433 | ||
1c2623c5 SJ |
434 | /* |
435 | * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length | |
436 | * from response UPIU | |
437 | * @ucd_rsp_ptr: pointer to response UPIU | |
438 | * | |
439 | * Return the data segment length. | |
440 | */ | |
441 | static inline unsigned int | |
442 | ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr) | |
443 | { | |
444 | return be32_to_cpu(ucd_rsp_ptr->header.dword_2) & | |
445 | MASK_RSP_UPIU_DATA_SEG_LEN; | |
446 | } | |
447 | ||
66ec6d59 SRT |
448 | /** |
449 | * ufshcd_is_exception_event - Check if the device raised an exception event | |
450 | * @ucd_rsp_ptr: pointer to response UPIU | |
451 | * | |
452 | * The function checks if the device raised an exception event indicated in | |
453 | * the Device Information field of response UPIU. | |
454 | * | |
455 | * Returns true if exception is raised, false otherwise. | |
456 | */ | |
457 | static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr) | |
458 | { | |
459 | return be32_to_cpu(ucd_rsp_ptr->header.dword_2) & | |
460 | MASK_RSP_EXCEPTION_EVENT ? true : false; | |
461 | } | |
462 | ||
7a3e97b0 | 463 | /** |
7d568652 | 464 | * ufshcd_reset_intr_aggr - Reset interrupt aggregation values. |
7a3e97b0 | 465 | * @hba: per adapter instance |
7a3e97b0 SY |
466 | */ |
467 | static inline void | |
7d568652 | 468 | ufshcd_reset_intr_aggr(struct ufs_hba *hba) |
7a3e97b0 | 469 | { |
7d568652 SJ |
470 | ufshcd_writel(hba, INT_AGGR_ENABLE | |
471 | INT_AGGR_COUNTER_AND_TIMER_RESET, | |
472 | REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); | |
473 | } | |
474 | ||
475 | /** | |
476 | * ufshcd_config_intr_aggr - Configure interrupt aggregation values. | |
477 | * @hba: per adapter instance | |
478 | * @cnt: Interrupt aggregation counter threshold | |
479 | * @tmout: Interrupt aggregation timeout value | |
480 | */ | |
481 | static inline void | |
482 | ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout) | |
483 | { | |
484 | ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE | | |
485 | INT_AGGR_COUNTER_THLD_VAL(cnt) | | |
486 | INT_AGGR_TIMEOUT_VAL(tmout), | |
487 | REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); | |
7a3e97b0 SY |
488 | } |
489 | ||
b852190e YG |
490 | /** |
491 | * ufshcd_disable_intr_aggr - Disables interrupt aggregation. | |
492 | * @hba: per adapter instance | |
493 | */ | |
494 | static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba) | |
495 | { | |
496 | ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); | |
497 | } | |
498 | ||
7a3e97b0 SY |
499 | /** |
500 | * ufshcd_enable_run_stop_reg - Enable run-stop registers, | |
501 | * When run-stop registers are set to 1, it indicates the | |
502 | * host controller that it can process the requests | |
503 | * @hba: per adapter instance | |
504 | */ | |
505 | static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba) | |
506 | { | |
b873a275 SJ |
507 | ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT, |
508 | REG_UTP_TASK_REQ_LIST_RUN_STOP); | |
509 | ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT, | |
510 | REG_UTP_TRANSFER_REQ_LIST_RUN_STOP); | |
7a3e97b0 SY |
511 | } |
512 | ||
7a3e97b0 SY |
513 | /** |
514 | * ufshcd_hba_start - Start controller initialization sequence | |
515 | * @hba: per adapter instance | |
516 | */ | |
517 | static inline void ufshcd_hba_start(struct ufs_hba *hba) | |
518 | { | |
b873a275 | 519 | ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE); |
7a3e97b0 SY |
520 | } |
521 | ||
522 | /** | |
523 | * ufshcd_is_hba_active - Get controller state | |
524 | * @hba: per adapter instance | |
525 | * | |
526 | * Returns zero if controller is active, 1 otherwise | |
527 | */ | |
528 | static inline int ufshcd_is_hba_active(struct ufs_hba *hba) | |
529 | { | |
b873a275 | 530 | return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & 0x1) ? 0 : 1; |
7a3e97b0 SY |
531 | } |
532 | ||
1ab27c9c ST |
533 | static void ufshcd_ungate_work(struct work_struct *work) |
534 | { | |
535 | int ret; | |
536 | unsigned long flags; | |
537 | struct ufs_hba *hba = container_of(work, struct ufs_hba, | |
538 | clk_gating.ungate_work); | |
539 | ||
540 | cancel_delayed_work_sync(&hba->clk_gating.gate_work); | |
541 | ||
542 | spin_lock_irqsave(hba->host->host_lock, flags); | |
543 | if (hba->clk_gating.state == CLKS_ON) { | |
544 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
545 | goto unblock_reqs; | |
546 | } | |
547 | ||
548 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
549 | ufshcd_setup_clocks(hba, true); | |
550 | ||
551 | /* Exit from hibern8 */ | |
552 | if (ufshcd_can_hibern8_during_gating(hba)) { | |
553 | /* Prevent gating in this path */ | |
554 | hba->clk_gating.is_suspended = true; | |
555 | if (ufshcd_is_link_hibern8(hba)) { | |
556 | ret = ufshcd_uic_hibern8_exit(hba); | |
557 | if (ret) | |
558 | dev_err(hba->dev, "%s: hibern8 exit failed %d\n", | |
559 | __func__, ret); | |
560 | else | |
561 | ufshcd_set_link_active(hba); | |
562 | } | |
563 | hba->clk_gating.is_suspended = false; | |
564 | } | |
565 | unblock_reqs: | |
856b3483 ST |
566 | if (ufshcd_is_clkscaling_enabled(hba)) |
567 | devfreq_resume_device(hba->devfreq); | |
1ab27c9c ST |
568 | scsi_unblock_requests(hba->host); |
569 | } | |
570 | ||
571 | /** | |
572 | * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release. | |
573 | * Also, exit from hibern8 mode and set the link as active. | |
574 | * @hba: per adapter instance | |
575 | * @async: This indicates whether caller should ungate clocks asynchronously. | |
576 | */ | |
577 | int ufshcd_hold(struct ufs_hba *hba, bool async) | |
578 | { | |
579 | int rc = 0; | |
580 | unsigned long flags; | |
581 | ||
582 | if (!ufshcd_is_clkgating_allowed(hba)) | |
583 | goto out; | |
1ab27c9c ST |
584 | spin_lock_irqsave(hba->host->host_lock, flags); |
585 | hba->clk_gating.active_reqs++; | |
586 | ||
856b3483 | 587 | start: |
1ab27c9c ST |
588 | switch (hba->clk_gating.state) { |
589 | case CLKS_ON: | |
590 | break; | |
591 | case REQ_CLKS_OFF: | |
592 | if (cancel_delayed_work(&hba->clk_gating.gate_work)) { | |
593 | hba->clk_gating.state = CLKS_ON; | |
594 | break; | |
595 | } | |
596 | /* | |
597 | * If we here, it means gating work is either done or | |
598 | * currently running. Hence, fall through to cancel gating | |
599 | * work and to enable clocks. | |
600 | */ | |
601 | case CLKS_OFF: | |
602 | scsi_block_requests(hba->host); | |
603 | hba->clk_gating.state = REQ_CLKS_ON; | |
604 | schedule_work(&hba->clk_gating.ungate_work); | |
605 | /* | |
606 | * fall through to check if we should wait for this | |
607 | * work to be done or not. | |
608 | */ | |
609 | case REQ_CLKS_ON: | |
610 | if (async) { | |
611 | rc = -EAGAIN; | |
612 | hba->clk_gating.active_reqs--; | |
613 | break; | |
614 | } | |
615 | ||
616 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
617 | flush_work(&hba->clk_gating.ungate_work); | |
618 | /* Make sure state is CLKS_ON before returning */ | |
856b3483 | 619 | spin_lock_irqsave(hba->host->host_lock, flags); |
1ab27c9c ST |
620 | goto start; |
621 | default: | |
622 | dev_err(hba->dev, "%s: clk gating is in invalid state %d\n", | |
623 | __func__, hba->clk_gating.state); | |
624 | break; | |
625 | } | |
626 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
627 | out: | |
628 | return rc; | |
629 | } | |
630 | ||
631 | static void ufshcd_gate_work(struct work_struct *work) | |
632 | { | |
633 | struct ufs_hba *hba = container_of(work, struct ufs_hba, | |
634 | clk_gating.gate_work.work); | |
635 | unsigned long flags; | |
636 | ||
637 | spin_lock_irqsave(hba->host->host_lock, flags); | |
638 | if (hba->clk_gating.is_suspended) { | |
639 | hba->clk_gating.state = CLKS_ON; | |
640 | goto rel_lock; | |
641 | } | |
642 | ||
643 | if (hba->clk_gating.active_reqs | |
644 | || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL | |
645 | || hba->lrb_in_use || hba->outstanding_tasks | |
646 | || hba->active_uic_cmd || hba->uic_async_done) | |
647 | goto rel_lock; | |
648 | ||
649 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
650 | ||
651 | /* put the link into hibern8 mode before turning off clocks */ | |
652 | if (ufshcd_can_hibern8_during_gating(hba)) { | |
653 | if (ufshcd_uic_hibern8_enter(hba)) { | |
654 | hba->clk_gating.state = CLKS_ON; | |
655 | goto out; | |
656 | } | |
657 | ufshcd_set_link_hibern8(hba); | |
658 | } | |
659 | ||
856b3483 ST |
660 | if (ufshcd_is_clkscaling_enabled(hba)) { |
661 | devfreq_suspend_device(hba->devfreq); | |
662 | hba->clk_scaling.window_start_t = 0; | |
663 | } | |
664 | ||
1ab27c9c ST |
665 | if (!ufshcd_is_link_active(hba)) |
666 | ufshcd_setup_clocks(hba, false); | |
667 | else | |
668 | /* If link is active, device ref_clk can't be switched off */ | |
669 | __ufshcd_setup_clocks(hba, false, true); | |
670 | ||
671 | /* | |
672 | * In case you are here to cancel this work the gating state | |
673 | * would be marked as REQ_CLKS_ON. In this case keep the state | |
674 | * as REQ_CLKS_ON which would anyway imply that clocks are off | |
675 | * and a request to turn them on is pending. By doing this way, | |
676 | * we keep the state machine in tact and this would ultimately | |
677 | * prevent from doing cancel work multiple times when there are | |
678 | * new requests arriving before the current cancel work is done. | |
679 | */ | |
680 | spin_lock_irqsave(hba->host->host_lock, flags); | |
681 | if (hba->clk_gating.state == REQ_CLKS_OFF) | |
682 | hba->clk_gating.state = CLKS_OFF; | |
683 | ||
684 | rel_lock: | |
685 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
686 | out: | |
687 | return; | |
688 | } | |
689 | ||
690 | /* host lock must be held before calling this variant */ | |
691 | static void __ufshcd_release(struct ufs_hba *hba) | |
692 | { | |
693 | if (!ufshcd_is_clkgating_allowed(hba)) | |
694 | return; | |
695 | ||
696 | hba->clk_gating.active_reqs--; | |
697 | ||
698 | if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended | |
699 | || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL | |
700 | || hba->lrb_in_use || hba->outstanding_tasks | |
701 | || hba->active_uic_cmd || hba->uic_async_done) | |
702 | return; | |
703 | ||
704 | hba->clk_gating.state = REQ_CLKS_OFF; | |
705 | schedule_delayed_work(&hba->clk_gating.gate_work, | |
706 | msecs_to_jiffies(hba->clk_gating.delay_ms)); | |
707 | } | |
708 | ||
709 | void ufshcd_release(struct ufs_hba *hba) | |
710 | { | |
711 | unsigned long flags; | |
712 | ||
713 | spin_lock_irqsave(hba->host->host_lock, flags); | |
714 | __ufshcd_release(hba); | |
715 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
716 | } | |
717 | ||
718 | static ssize_t ufshcd_clkgate_delay_show(struct device *dev, | |
719 | struct device_attribute *attr, char *buf) | |
720 | { | |
721 | struct ufs_hba *hba = dev_get_drvdata(dev); | |
722 | ||
723 | return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms); | |
724 | } | |
725 | ||
726 | static ssize_t ufshcd_clkgate_delay_store(struct device *dev, | |
727 | struct device_attribute *attr, const char *buf, size_t count) | |
728 | { | |
729 | struct ufs_hba *hba = dev_get_drvdata(dev); | |
730 | unsigned long flags, value; | |
731 | ||
732 | if (kstrtoul(buf, 0, &value)) | |
733 | return -EINVAL; | |
734 | ||
735 | spin_lock_irqsave(hba->host->host_lock, flags); | |
736 | hba->clk_gating.delay_ms = value; | |
737 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
738 | return count; | |
739 | } | |
740 | ||
741 | static void ufshcd_init_clk_gating(struct ufs_hba *hba) | |
742 | { | |
743 | if (!ufshcd_is_clkgating_allowed(hba)) | |
744 | return; | |
745 | ||
746 | hba->clk_gating.delay_ms = 150; | |
747 | INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work); | |
748 | INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work); | |
749 | ||
750 | hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show; | |
751 | hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store; | |
752 | sysfs_attr_init(&hba->clk_gating.delay_attr.attr); | |
753 | hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms"; | |
754 | hba->clk_gating.delay_attr.attr.mode = S_IRUGO | S_IWUSR; | |
755 | if (device_create_file(hba->dev, &hba->clk_gating.delay_attr)) | |
756 | dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n"); | |
757 | } | |
758 | ||
759 | static void ufshcd_exit_clk_gating(struct ufs_hba *hba) | |
760 | { | |
761 | if (!ufshcd_is_clkgating_allowed(hba)) | |
762 | return; | |
763 | device_remove_file(hba->dev, &hba->clk_gating.delay_attr); | |
97cd6805 AM |
764 | cancel_work_sync(&hba->clk_gating.ungate_work); |
765 | cancel_delayed_work_sync(&hba->clk_gating.gate_work); | |
1ab27c9c ST |
766 | } |
767 | ||
856b3483 ST |
768 | /* Must be called with host lock acquired */ |
769 | static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba) | |
770 | { | |
771 | if (!ufshcd_is_clkscaling_enabled(hba)) | |
772 | return; | |
773 | ||
774 | if (!hba->clk_scaling.is_busy_started) { | |
775 | hba->clk_scaling.busy_start_t = ktime_get(); | |
776 | hba->clk_scaling.is_busy_started = true; | |
777 | } | |
778 | } | |
779 | ||
780 | static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba) | |
781 | { | |
782 | struct ufs_clk_scaling *scaling = &hba->clk_scaling; | |
783 | ||
784 | if (!ufshcd_is_clkscaling_enabled(hba)) | |
785 | return; | |
786 | ||
787 | if (!hba->outstanding_reqs && scaling->is_busy_started) { | |
788 | scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(), | |
789 | scaling->busy_start_t)); | |
790 | scaling->busy_start_t = ktime_set(0, 0); | |
791 | scaling->is_busy_started = false; | |
792 | } | |
793 | } | |
7a3e97b0 SY |
794 | /** |
795 | * ufshcd_send_command - Send SCSI or device management commands | |
796 | * @hba: per adapter instance | |
797 | * @task_tag: Task tag of the command | |
798 | */ | |
799 | static inline | |
800 | void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag) | |
801 | { | |
856b3483 | 802 | ufshcd_clk_scaling_start_busy(hba); |
7a3e97b0 | 803 | __set_bit(task_tag, &hba->outstanding_reqs); |
b873a275 | 804 | ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL); |
7a3e97b0 SY |
805 | } |
806 | ||
807 | /** | |
808 | * ufshcd_copy_sense_data - Copy sense data in case of check condition | |
809 | * @lrb - pointer to local reference block | |
810 | */ | |
811 | static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp) | |
812 | { | |
813 | int len; | |
1c2623c5 SJ |
814 | if (lrbp->sense_buffer && |
815 | ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) { | |
5a0b0cb9 | 816 | len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len); |
7a3e97b0 | 817 | memcpy(lrbp->sense_buffer, |
5a0b0cb9 | 818 | lrbp->ucd_rsp_ptr->sr.sense_data, |
7a3e97b0 SY |
819 | min_t(int, len, SCSI_SENSE_BUFFERSIZE)); |
820 | } | |
821 | } | |
822 | ||
68078d5c DR |
823 | /** |
824 | * ufshcd_copy_query_response() - Copy the Query Response and the data | |
825 | * descriptor | |
826 | * @hba: per adapter instance | |
827 | * @lrb - pointer to local reference block | |
828 | */ | |
829 | static | |
c6d4a831 | 830 | int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) |
68078d5c DR |
831 | { |
832 | struct ufs_query_res *query_res = &hba->dev_cmd.query.response; | |
833 | ||
68078d5c | 834 | memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE); |
68078d5c | 835 | |
68078d5c DR |
836 | /* Get the descriptor */ |
837 | if (lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) { | |
d44a5f98 | 838 | u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + |
68078d5c | 839 | GENERAL_UPIU_REQUEST_SIZE; |
c6d4a831 DR |
840 | u16 resp_len; |
841 | u16 buf_len; | |
68078d5c DR |
842 | |
843 | /* data segment length */ | |
c6d4a831 | 844 | resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) & |
68078d5c | 845 | MASK_QUERY_DATA_SEG_LEN; |
ea2aab24 SRT |
846 | buf_len = be16_to_cpu( |
847 | hba->dev_cmd.query.request.upiu_req.length); | |
c6d4a831 DR |
848 | if (likely(buf_len >= resp_len)) { |
849 | memcpy(hba->dev_cmd.query.descriptor, descp, resp_len); | |
850 | } else { | |
851 | dev_warn(hba->dev, | |
852 | "%s: Response size is bigger than buffer", | |
853 | __func__); | |
854 | return -EINVAL; | |
855 | } | |
68078d5c | 856 | } |
c6d4a831 DR |
857 | |
858 | return 0; | |
68078d5c DR |
859 | } |
860 | ||
7a3e97b0 SY |
861 | /** |
862 | * ufshcd_hba_capabilities - Read controller capabilities | |
863 | * @hba: per adapter instance | |
864 | */ | |
865 | static inline void ufshcd_hba_capabilities(struct ufs_hba *hba) | |
866 | { | |
b873a275 | 867 | hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES); |
7a3e97b0 SY |
868 | |
869 | /* nutrs and nutmrs are 0 based values */ | |
870 | hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1; | |
871 | hba->nutmrs = | |
872 | ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1; | |
873 | } | |
874 | ||
875 | /** | |
6ccf44fe SJ |
876 | * ufshcd_ready_for_uic_cmd - Check if controller is ready |
877 | * to accept UIC commands | |
7a3e97b0 | 878 | * @hba: per adapter instance |
6ccf44fe SJ |
879 | * Return true on success, else false |
880 | */ | |
881 | static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba) | |
882 | { | |
883 | if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY) | |
884 | return true; | |
885 | else | |
886 | return false; | |
887 | } | |
888 | ||
53b3d9c3 SJ |
889 | /** |
890 | * ufshcd_get_upmcrs - Get the power mode change request status | |
891 | * @hba: Pointer to adapter instance | |
892 | * | |
893 | * This function gets the UPMCRS field of HCS register | |
894 | * Returns value of UPMCRS field | |
895 | */ | |
896 | static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba) | |
897 | { | |
898 | return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7; | |
899 | } | |
900 | ||
6ccf44fe SJ |
901 | /** |
902 | * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers | |
903 | * @hba: per adapter instance | |
904 | * @uic_cmd: UIC command | |
905 | * | |
906 | * Mutex must be held. | |
7a3e97b0 SY |
907 | */ |
908 | static inline void | |
6ccf44fe | 909 | ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) |
7a3e97b0 | 910 | { |
6ccf44fe SJ |
911 | WARN_ON(hba->active_uic_cmd); |
912 | ||
913 | hba->active_uic_cmd = uic_cmd; | |
914 | ||
7a3e97b0 | 915 | /* Write Args */ |
6ccf44fe SJ |
916 | ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1); |
917 | ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2); | |
918 | ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3); | |
7a3e97b0 SY |
919 | |
920 | /* Write UIC Cmd */ | |
6ccf44fe | 921 | ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK, |
b873a275 | 922 | REG_UIC_COMMAND); |
7a3e97b0 SY |
923 | } |
924 | ||
6ccf44fe SJ |
925 | /** |
926 | * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command | |
927 | * @hba: per adapter instance | |
928 | * @uic_command: UIC command | |
929 | * | |
930 | * Must be called with mutex held. | |
931 | * Returns 0 only if success. | |
932 | */ | |
933 | static int | |
934 | ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) | |
935 | { | |
936 | int ret; | |
937 | unsigned long flags; | |
938 | ||
939 | if (wait_for_completion_timeout(&uic_cmd->done, | |
940 | msecs_to_jiffies(UIC_CMD_TIMEOUT))) | |
941 | ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT; | |
942 | else | |
943 | ret = -ETIMEDOUT; | |
944 | ||
945 | spin_lock_irqsave(hba->host->host_lock, flags); | |
946 | hba->active_uic_cmd = NULL; | |
947 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
948 | ||
949 | return ret; | |
950 | } | |
951 | ||
952 | /** | |
953 | * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result | |
954 | * @hba: per adapter instance | |
955 | * @uic_cmd: UIC command | |
956 | * | |
957 | * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called | |
57d104c1 | 958 | * with mutex held and host_lock locked. |
6ccf44fe SJ |
959 | * Returns 0 only if success. |
960 | */ | |
961 | static int | |
962 | __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) | |
963 | { | |
6ccf44fe SJ |
964 | if (!ufshcd_ready_for_uic_cmd(hba)) { |
965 | dev_err(hba->dev, | |
966 | "Controller not ready to accept UIC commands\n"); | |
967 | return -EIO; | |
968 | } | |
969 | ||
970 | init_completion(&uic_cmd->done); | |
971 | ||
6ccf44fe | 972 | ufshcd_dispatch_uic_cmd(hba, uic_cmd); |
6ccf44fe | 973 | |
57d104c1 | 974 | return 0; |
6ccf44fe SJ |
975 | } |
976 | ||
977 | /** | |
978 | * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result | |
979 | * @hba: per adapter instance | |
980 | * @uic_cmd: UIC command | |
981 | * | |
982 | * Returns 0 only if success. | |
983 | */ | |
984 | static int | |
985 | ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) | |
986 | { | |
987 | int ret; | |
57d104c1 | 988 | unsigned long flags; |
6ccf44fe | 989 | |
1ab27c9c | 990 | ufshcd_hold(hba, false); |
6ccf44fe | 991 | mutex_lock(&hba->uic_cmd_mutex); |
cad2e03d YG |
992 | ufshcd_add_delay_before_dme_cmd(hba); |
993 | ||
57d104c1 | 994 | spin_lock_irqsave(hba->host->host_lock, flags); |
6ccf44fe | 995 | ret = __ufshcd_send_uic_cmd(hba, uic_cmd); |
57d104c1 SJ |
996 | spin_unlock_irqrestore(hba->host->host_lock, flags); |
997 | if (!ret) | |
998 | ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd); | |
999 | ||
6ccf44fe SJ |
1000 | mutex_unlock(&hba->uic_cmd_mutex); |
1001 | ||
1ab27c9c | 1002 | ufshcd_release(hba); |
6ccf44fe SJ |
1003 | return ret; |
1004 | } | |
1005 | ||
7a3e97b0 SY |
1006 | /** |
1007 | * ufshcd_map_sg - Map scatter-gather list to prdt | |
1008 | * @lrbp - pointer to local reference block | |
1009 | * | |
1010 | * Returns 0 in case of success, non-zero value in case of failure | |
1011 | */ | |
1012 | static int ufshcd_map_sg(struct ufshcd_lrb *lrbp) | |
1013 | { | |
1014 | struct ufshcd_sg_entry *prd_table; | |
1015 | struct scatterlist *sg; | |
1016 | struct scsi_cmnd *cmd; | |
1017 | int sg_segments; | |
1018 | int i; | |
1019 | ||
1020 | cmd = lrbp->cmd; | |
1021 | sg_segments = scsi_dma_map(cmd); | |
1022 | if (sg_segments < 0) | |
1023 | return sg_segments; | |
1024 | ||
1025 | if (sg_segments) { | |
1026 | lrbp->utr_descriptor_ptr->prd_table_length = | |
1027 | cpu_to_le16((u16) (sg_segments)); | |
1028 | ||
1029 | prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr; | |
1030 | ||
1031 | scsi_for_each_sg(cmd, sg, sg_segments, i) { | |
1032 | prd_table[i].size = | |
1033 | cpu_to_le32(((u32) sg_dma_len(sg))-1); | |
1034 | prd_table[i].base_addr = | |
1035 | cpu_to_le32(lower_32_bits(sg->dma_address)); | |
1036 | prd_table[i].upper_addr = | |
1037 | cpu_to_le32(upper_32_bits(sg->dma_address)); | |
1038 | } | |
1039 | } else { | |
1040 | lrbp->utr_descriptor_ptr->prd_table_length = 0; | |
1041 | } | |
1042 | ||
1043 | return 0; | |
1044 | } | |
1045 | ||
1046 | /** | |
2fbd009b | 1047 | * ufshcd_enable_intr - enable interrupts |
7a3e97b0 | 1048 | * @hba: per adapter instance |
2fbd009b | 1049 | * @intrs: interrupt bits |
7a3e97b0 | 1050 | */ |
2fbd009b | 1051 | static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs) |
7a3e97b0 | 1052 | { |
2fbd009b SJ |
1053 | u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); |
1054 | ||
1055 | if (hba->ufs_version == UFSHCI_VERSION_10) { | |
1056 | u32 rw; | |
1057 | rw = set & INTERRUPT_MASK_RW_VER_10; | |
1058 | set = rw | ((set ^ intrs) & intrs); | |
1059 | } else { | |
1060 | set |= intrs; | |
1061 | } | |
1062 | ||
1063 | ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); | |
1064 | } | |
1065 | ||
1066 | /** | |
1067 | * ufshcd_disable_intr - disable interrupts | |
1068 | * @hba: per adapter instance | |
1069 | * @intrs: interrupt bits | |
1070 | */ | |
1071 | static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs) | |
1072 | { | |
1073 | u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); | |
1074 | ||
1075 | if (hba->ufs_version == UFSHCI_VERSION_10) { | |
1076 | u32 rw; | |
1077 | rw = (set & INTERRUPT_MASK_RW_VER_10) & | |
1078 | ~(intrs & INTERRUPT_MASK_RW_VER_10); | |
1079 | set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10); | |
1080 | ||
1081 | } else { | |
1082 | set &= ~intrs; | |
7a3e97b0 | 1083 | } |
2fbd009b SJ |
1084 | |
1085 | ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); | |
7a3e97b0 SY |
1086 | } |
1087 | ||
5a0b0cb9 SRT |
1088 | /** |
1089 | * ufshcd_prepare_req_desc_hdr() - Fills the requests header | |
1090 | * descriptor according to request | |
1091 | * @lrbp: pointer to local reference block | |
1092 | * @upiu_flags: flags required in the header | |
1093 | * @cmd_dir: requests data direction | |
1094 | */ | |
1095 | static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp, | |
1096 | u32 *upiu_flags, enum dma_data_direction cmd_dir) | |
1097 | { | |
1098 | struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr; | |
1099 | u32 data_direction; | |
1100 | u32 dword_0; | |
1101 | ||
1102 | if (cmd_dir == DMA_FROM_DEVICE) { | |
1103 | data_direction = UTP_DEVICE_TO_HOST; | |
1104 | *upiu_flags = UPIU_CMD_FLAGS_READ; | |
1105 | } else if (cmd_dir == DMA_TO_DEVICE) { | |
1106 | data_direction = UTP_HOST_TO_DEVICE; | |
1107 | *upiu_flags = UPIU_CMD_FLAGS_WRITE; | |
1108 | } else { | |
1109 | data_direction = UTP_NO_DATA_TRANSFER; | |
1110 | *upiu_flags = UPIU_CMD_FLAGS_NONE; | |
1111 | } | |
1112 | ||
1113 | dword_0 = data_direction | (lrbp->command_type | |
1114 | << UPIU_COMMAND_TYPE_OFFSET); | |
1115 | if (lrbp->intr_cmd) | |
1116 | dword_0 |= UTP_REQ_DESC_INT_CMD; | |
1117 | ||
1118 | /* Transfer request descriptor header fields */ | |
1119 | req_desc->header.dword_0 = cpu_to_le32(dword_0); | |
1120 | ||
1121 | /* | |
1122 | * assigning invalid value for command status. Controller | |
1123 | * updates OCS on command completion, with the command | |
1124 | * status | |
1125 | */ | |
1126 | req_desc->header.dword_2 = | |
1127 | cpu_to_le32(OCS_INVALID_COMMAND_STATUS); | |
1128 | } | |
1129 | ||
1130 | /** | |
1131 | * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc, | |
1132 | * for scsi commands | |
1133 | * @lrbp - local reference block pointer | |
1134 | * @upiu_flags - flags | |
1135 | */ | |
1136 | static | |
1137 | void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags) | |
1138 | { | |
1139 | struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; | |
1140 | ||
1141 | /* command descriptor fields */ | |
1142 | ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD( | |
1143 | UPIU_TRANSACTION_COMMAND, upiu_flags, | |
1144 | lrbp->lun, lrbp->task_tag); | |
1145 | ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD( | |
1146 | UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0); | |
1147 | ||
1148 | /* Total EHS length and Data segment length will be zero */ | |
1149 | ucd_req_ptr->header.dword_2 = 0; | |
1150 | ||
1151 | ucd_req_ptr->sc.exp_data_transfer_len = | |
1152 | cpu_to_be32(lrbp->cmd->sdb.length); | |
1153 | ||
1154 | memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd, | |
1155 | (min_t(unsigned short, lrbp->cmd->cmd_len, MAX_CDB_SIZE))); | |
1156 | } | |
1157 | ||
68078d5c DR |
1158 | /** |
1159 | * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc, | |
1160 | * for query requsts | |
1161 | * @hba: UFS hba | |
1162 | * @lrbp: local reference block pointer | |
1163 | * @upiu_flags: flags | |
1164 | */ | |
1165 | static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba, | |
1166 | struct ufshcd_lrb *lrbp, u32 upiu_flags) | |
1167 | { | |
1168 | struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; | |
1169 | struct ufs_query *query = &hba->dev_cmd.query; | |
e8c8e82a | 1170 | u16 len = be16_to_cpu(query->request.upiu_req.length); |
68078d5c DR |
1171 | u8 *descp = (u8 *)lrbp->ucd_req_ptr + GENERAL_UPIU_REQUEST_SIZE; |
1172 | ||
1173 | /* Query request header */ | |
1174 | ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD( | |
1175 | UPIU_TRANSACTION_QUERY_REQ, upiu_flags, | |
1176 | lrbp->lun, lrbp->task_tag); | |
1177 | ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD( | |
1178 | 0, query->request.query_func, 0, 0); | |
1179 | ||
1180 | /* Data segment length */ | |
1181 | ucd_req_ptr->header.dword_2 = UPIU_HEADER_DWORD( | |
1182 | 0, 0, len >> 8, (u8)len); | |
1183 | ||
1184 | /* Copy the Query Request buffer as is */ | |
1185 | memcpy(&ucd_req_ptr->qr, &query->request.upiu_req, | |
1186 | QUERY_OSF_SIZE); | |
68078d5c DR |
1187 | |
1188 | /* Copy the Descriptor */ | |
c6d4a831 DR |
1189 | if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) |
1190 | memcpy(descp, query->descriptor, len); | |
1191 | ||
68078d5c DR |
1192 | } |
1193 | ||
5a0b0cb9 SRT |
1194 | static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp) |
1195 | { | |
1196 | struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; | |
1197 | ||
1198 | memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req)); | |
1199 | ||
1200 | /* command descriptor fields */ | |
1201 | ucd_req_ptr->header.dword_0 = | |
1202 | UPIU_HEADER_DWORD( | |
1203 | UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag); | |
1204 | } | |
1205 | ||
7a3e97b0 SY |
1206 | /** |
1207 | * ufshcd_compose_upiu - form UFS Protocol Information Unit(UPIU) | |
5a0b0cb9 | 1208 | * @hba - per adapter instance |
7a3e97b0 SY |
1209 | * @lrb - pointer to local reference block |
1210 | */ | |
5a0b0cb9 | 1211 | static int ufshcd_compose_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) |
7a3e97b0 | 1212 | { |
7a3e97b0 | 1213 | u32 upiu_flags; |
5a0b0cb9 | 1214 | int ret = 0; |
7a3e97b0 SY |
1215 | |
1216 | switch (lrbp->command_type) { | |
1217 | case UTP_CMD_TYPE_SCSI: | |
5a0b0cb9 SRT |
1218 | if (likely(lrbp->cmd)) { |
1219 | ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, | |
1220 | lrbp->cmd->sc_data_direction); | |
1221 | ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags); | |
7a3e97b0 | 1222 | } else { |
5a0b0cb9 | 1223 | ret = -EINVAL; |
7a3e97b0 | 1224 | } |
7a3e97b0 SY |
1225 | break; |
1226 | case UTP_CMD_TYPE_DEV_MANAGE: | |
5a0b0cb9 | 1227 | ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE); |
68078d5c DR |
1228 | if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY) |
1229 | ufshcd_prepare_utp_query_req_upiu( | |
1230 | hba, lrbp, upiu_flags); | |
1231 | else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP) | |
5a0b0cb9 SRT |
1232 | ufshcd_prepare_utp_nop_upiu(lrbp); |
1233 | else | |
1234 | ret = -EINVAL; | |
7a3e97b0 SY |
1235 | break; |
1236 | case UTP_CMD_TYPE_UFS: | |
1237 | /* For UFS native command implementation */ | |
5a0b0cb9 SRT |
1238 | ret = -ENOTSUPP; |
1239 | dev_err(hba->dev, "%s: UFS native command are not supported\n", | |
1240 | __func__); | |
1241 | break; | |
1242 | default: | |
1243 | ret = -ENOTSUPP; | |
1244 | dev_err(hba->dev, "%s: unknown command type: 0x%x\n", | |
1245 | __func__, lrbp->command_type); | |
7a3e97b0 SY |
1246 | break; |
1247 | } /* end of switch */ | |
5a0b0cb9 SRT |
1248 | |
1249 | return ret; | |
7a3e97b0 SY |
1250 | } |
1251 | ||
0ce147d4 SJ |
1252 | /* |
1253 | * ufshcd_scsi_to_upiu_lun - maps scsi LUN to UPIU LUN | |
1254 | * @scsi_lun: scsi LUN id | |
1255 | * | |
1256 | * Returns UPIU LUN id | |
1257 | */ | |
1258 | static inline u8 ufshcd_scsi_to_upiu_lun(unsigned int scsi_lun) | |
1259 | { | |
1260 | if (scsi_is_wlun(scsi_lun)) | |
1261 | return (scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID) | |
1262 | | UFS_UPIU_WLUN_ID; | |
1263 | else | |
1264 | return scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID; | |
1265 | } | |
1266 | ||
2a8fa600 SJ |
1267 | /** |
1268 | * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID | |
1269 | * @scsi_lun: UPIU W-LUN id | |
1270 | * | |
1271 | * Returns SCSI W-LUN id | |
1272 | */ | |
1273 | static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id) | |
1274 | { | |
1275 | return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE; | |
1276 | } | |
1277 | ||
7a3e97b0 SY |
1278 | /** |
1279 | * ufshcd_queuecommand - main entry point for SCSI requests | |
1280 | * @cmd: command from SCSI Midlayer | |
1281 | * @done: call back function | |
1282 | * | |
1283 | * Returns 0 for success, non-zero in case of failure | |
1284 | */ | |
1285 | static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) | |
1286 | { | |
1287 | struct ufshcd_lrb *lrbp; | |
1288 | struct ufs_hba *hba; | |
1289 | unsigned long flags; | |
1290 | int tag; | |
1291 | int err = 0; | |
1292 | ||
1293 | hba = shost_priv(host); | |
1294 | ||
1295 | tag = cmd->request->tag; | |
1296 | ||
3441da7d SRT |
1297 | spin_lock_irqsave(hba->host->host_lock, flags); |
1298 | switch (hba->ufshcd_state) { | |
1299 | case UFSHCD_STATE_OPERATIONAL: | |
1300 | break; | |
1301 | case UFSHCD_STATE_RESET: | |
7a3e97b0 | 1302 | err = SCSI_MLQUEUE_HOST_BUSY; |
3441da7d SRT |
1303 | goto out_unlock; |
1304 | case UFSHCD_STATE_ERROR: | |
1305 | set_host_byte(cmd, DID_ERROR); | |
1306 | cmd->scsi_done(cmd); | |
1307 | goto out_unlock; | |
1308 | default: | |
1309 | dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n", | |
1310 | __func__, hba->ufshcd_state); | |
1311 | set_host_byte(cmd, DID_BAD_TARGET); | |
1312 | cmd->scsi_done(cmd); | |
1313 | goto out_unlock; | |
7a3e97b0 | 1314 | } |
3441da7d | 1315 | spin_unlock_irqrestore(hba->host->host_lock, flags); |
7a3e97b0 | 1316 | |
5a0b0cb9 SRT |
1317 | /* acquire the tag to make sure device cmds don't use it */ |
1318 | if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) { | |
1319 | /* | |
1320 | * Dev manage command in progress, requeue the command. | |
1321 | * Requeuing the command helps in cases where the request *may* | |
1322 | * find different tag instead of waiting for dev manage command | |
1323 | * completion. | |
1324 | */ | |
1325 | err = SCSI_MLQUEUE_HOST_BUSY; | |
1326 | goto out; | |
1327 | } | |
1328 | ||
1ab27c9c ST |
1329 | err = ufshcd_hold(hba, true); |
1330 | if (err) { | |
1331 | err = SCSI_MLQUEUE_HOST_BUSY; | |
1332 | clear_bit_unlock(tag, &hba->lrb_in_use); | |
1333 | goto out; | |
1334 | } | |
1335 | WARN_ON(hba->clk_gating.state != CLKS_ON); | |
1336 | ||
7a3e97b0 SY |
1337 | lrbp = &hba->lrb[tag]; |
1338 | ||
5a0b0cb9 | 1339 | WARN_ON(lrbp->cmd); |
7a3e97b0 SY |
1340 | lrbp->cmd = cmd; |
1341 | lrbp->sense_bufflen = SCSI_SENSE_BUFFERSIZE; | |
1342 | lrbp->sense_buffer = cmd->sense_buffer; | |
1343 | lrbp->task_tag = tag; | |
0ce147d4 | 1344 | lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun); |
b852190e | 1345 | lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false; |
7a3e97b0 SY |
1346 | lrbp->command_type = UTP_CMD_TYPE_SCSI; |
1347 | ||
1348 | /* form UPIU before issuing the command */ | |
5a0b0cb9 | 1349 | ufshcd_compose_upiu(hba, lrbp); |
7a3e97b0 | 1350 | err = ufshcd_map_sg(lrbp); |
5a0b0cb9 SRT |
1351 | if (err) { |
1352 | lrbp->cmd = NULL; | |
1353 | clear_bit_unlock(tag, &hba->lrb_in_use); | |
7a3e97b0 | 1354 | goto out; |
5a0b0cb9 | 1355 | } |
7a3e97b0 SY |
1356 | |
1357 | /* issue command to the controller */ | |
1358 | spin_lock_irqsave(hba->host->host_lock, flags); | |
1359 | ufshcd_send_command(hba, tag); | |
3441da7d | 1360 | out_unlock: |
7a3e97b0 SY |
1361 | spin_unlock_irqrestore(hba->host->host_lock, flags); |
1362 | out: | |
1363 | return err; | |
1364 | } | |
1365 | ||
5a0b0cb9 SRT |
1366 | static int ufshcd_compose_dev_cmd(struct ufs_hba *hba, |
1367 | struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag) | |
1368 | { | |
1369 | lrbp->cmd = NULL; | |
1370 | lrbp->sense_bufflen = 0; | |
1371 | lrbp->sense_buffer = NULL; | |
1372 | lrbp->task_tag = tag; | |
1373 | lrbp->lun = 0; /* device management cmd is not specific to any LUN */ | |
1374 | lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE; | |
1375 | lrbp->intr_cmd = true; /* No interrupt aggregation */ | |
1376 | hba->dev_cmd.type = cmd_type; | |
1377 | ||
1378 | return ufshcd_compose_upiu(hba, lrbp); | |
1379 | } | |
1380 | ||
1381 | static int | |
1382 | ufshcd_clear_cmd(struct ufs_hba *hba, int tag) | |
1383 | { | |
1384 | int err = 0; | |
1385 | unsigned long flags; | |
1386 | u32 mask = 1 << tag; | |
1387 | ||
1388 | /* clear outstanding transaction before retry */ | |
1389 | spin_lock_irqsave(hba->host->host_lock, flags); | |
1390 | ufshcd_utrl_clear(hba, tag); | |
1391 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
1392 | ||
1393 | /* | |
1394 | * wait for for h/w to clear corresponding bit in door-bell. | |
1395 | * max. wait is 1 sec. | |
1396 | */ | |
1397 | err = ufshcd_wait_for_register(hba, | |
1398 | REG_UTP_TRANSFER_REQ_DOOR_BELL, | |
1399 | mask, ~mask, 1000, 1000); | |
1400 | ||
1401 | return err; | |
1402 | } | |
1403 | ||
c6d4a831 DR |
1404 | static int |
1405 | ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) | |
1406 | { | |
1407 | struct ufs_query_res *query_res = &hba->dev_cmd.query.response; | |
1408 | ||
1409 | /* Get the UPIU response */ | |
1410 | query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >> | |
1411 | UPIU_RSP_CODE_OFFSET; | |
1412 | return query_res->response; | |
1413 | } | |
1414 | ||
5a0b0cb9 SRT |
1415 | /** |
1416 | * ufshcd_dev_cmd_completion() - handles device management command responses | |
1417 | * @hba: per adapter instance | |
1418 | * @lrbp: pointer to local reference block | |
1419 | */ | |
1420 | static int | |
1421 | ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) | |
1422 | { | |
1423 | int resp; | |
1424 | int err = 0; | |
1425 | ||
1426 | resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr); | |
1427 | ||
1428 | switch (resp) { | |
1429 | case UPIU_TRANSACTION_NOP_IN: | |
1430 | if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) { | |
1431 | err = -EINVAL; | |
1432 | dev_err(hba->dev, "%s: unexpected response %x\n", | |
1433 | __func__, resp); | |
1434 | } | |
1435 | break; | |
68078d5c | 1436 | case UPIU_TRANSACTION_QUERY_RSP: |
c6d4a831 DR |
1437 | err = ufshcd_check_query_response(hba, lrbp); |
1438 | if (!err) | |
1439 | err = ufshcd_copy_query_response(hba, lrbp); | |
68078d5c | 1440 | break; |
5a0b0cb9 SRT |
1441 | case UPIU_TRANSACTION_REJECT_UPIU: |
1442 | /* TODO: handle Reject UPIU Response */ | |
1443 | err = -EPERM; | |
1444 | dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n", | |
1445 | __func__); | |
1446 | break; | |
1447 | default: | |
1448 | err = -EINVAL; | |
1449 | dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n", | |
1450 | __func__, resp); | |
1451 | break; | |
1452 | } | |
1453 | ||
1454 | return err; | |
1455 | } | |
1456 | ||
1457 | static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba, | |
1458 | struct ufshcd_lrb *lrbp, int max_timeout) | |
1459 | { | |
1460 | int err = 0; | |
1461 | unsigned long time_left; | |
1462 | unsigned long flags; | |
1463 | ||
1464 | time_left = wait_for_completion_timeout(hba->dev_cmd.complete, | |
1465 | msecs_to_jiffies(max_timeout)); | |
1466 | ||
1467 | spin_lock_irqsave(hba->host->host_lock, flags); | |
1468 | hba->dev_cmd.complete = NULL; | |
1469 | if (likely(time_left)) { | |
1470 | err = ufshcd_get_tr_ocs(lrbp); | |
1471 | if (!err) | |
1472 | err = ufshcd_dev_cmd_completion(hba, lrbp); | |
1473 | } | |
1474 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
1475 | ||
1476 | if (!time_left) { | |
1477 | err = -ETIMEDOUT; | |
1478 | if (!ufshcd_clear_cmd(hba, lrbp->task_tag)) | |
1479 | /* sucessfully cleared the command, retry if needed */ | |
1480 | err = -EAGAIN; | |
1481 | } | |
1482 | ||
1483 | return err; | |
1484 | } | |
1485 | ||
1486 | /** | |
1487 | * ufshcd_get_dev_cmd_tag - Get device management command tag | |
1488 | * @hba: per-adapter instance | |
1489 | * @tag: pointer to variable with available slot value | |
1490 | * | |
1491 | * Get a free slot and lock it until device management command | |
1492 | * completes. | |
1493 | * | |
1494 | * Returns false if free slot is unavailable for locking, else | |
1495 | * return true with tag value in @tag. | |
1496 | */ | |
1497 | static bool ufshcd_get_dev_cmd_tag(struct ufs_hba *hba, int *tag_out) | |
1498 | { | |
1499 | int tag; | |
1500 | bool ret = false; | |
1501 | unsigned long tmp; | |
1502 | ||
1503 | if (!tag_out) | |
1504 | goto out; | |
1505 | ||
1506 | do { | |
1507 | tmp = ~hba->lrb_in_use; | |
1508 | tag = find_last_bit(&tmp, hba->nutrs); | |
1509 | if (tag >= hba->nutrs) | |
1510 | goto out; | |
1511 | } while (test_and_set_bit_lock(tag, &hba->lrb_in_use)); | |
1512 | ||
1513 | *tag_out = tag; | |
1514 | ret = true; | |
1515 | out: | |
1516 | return ret; | |
1517 | } | |
1518 | ||
1519 | static inline void ufshcd_put_dev_cmd_tag(struct ufs_hba *hba, int tag) | |
1520 | { | |
1521 | clear_bit_unlock(tag, &hba->lrb_in_use); | |
1522 | } | |
1523 | ||
1524 | /** | |
1525 | * ufshcd_exec_dev_cmd - API for sending device management requests | |
1526 | * @hba - UFS hba | |
1527 | * @cmd_type - specifies the type (NOP, Query...) | |
1528 | * @timeout - time in seconds | |
1529 | * | |
68078d5c DR |
1530 | * NOTE: Since there is only one available tag for device management commands, |
1531 | * it is expected you hold the hba->dev_cmd.lock mutex. | |
5a0b0cb9 SRT |
1532 | */ |
1533 | static int ufshcd_exec_dev_cmd(struct ufs_hba *hba, | |
1534 | enum dev_cmd_type cmd_type, int timeout) | |
1535 | { | |
1536 | struct ufshcd_lrb *lrbp; | |
1537 | int err; | |
1538 | int tag; | |
1539 | struct completion wait; | |
1540 | unsigned long flags; | |
1541 | ||
1542 | /* | |
1543 | * Get free slot, sleep if slots are unavailable. | |
1544 | * Even though we use wait_event() which sleeps indefinitely, | |
1545 | * the maximum wait time is bounded by SCSI request timeout. | |
1546 | */ | |
1547 | wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag)); | |
1548 | ||
1549 | init_completion(&wait); | |
1550 | lrbp = &hba->lrb[tag]; | |
1551 | WARN_ON(lrbp->cmd); | |
1552 | err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag); | |
1553 | if (unlikely(err)) | |
1554 | goto out_put_tag; | |
1555 | ||
1556 | hba->dev_cmd.complete = &wait; | |
1557 | ||
1558 | spin_lock_irqsave(hba->host->host_lock, flags); | |
1559 | ufshcd_send_command(hba, tag); | |
1560 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
1561 | ||
1562 | err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout); | |
1563 | ||
1564 | out_put_tag: | |
1565 | ufshcd_put_dev_cmd_tag(hba, tag); | |
1566 | wake_up(&hba->dev_cmd.tag_wq); | |
1567 | return err; | |
1568 | } | |
1569 | ||
d44a5f98 DR |
1570 | /** |
1571 | * ufshcd_init_query() - init the query response and request parameters | |
1572 | * @hba: per-adapter instance | |
1573 | * @request: address of the request pointer to be initialized | |
1574 | * @response: address of the response pointer to be initialized | |
1575 | * @opcode: operation to perform | |
1576 | * @idn: flag idn to access | |
1577 | * @index: LU number to access | |
1578 | * @selector: query/flag/descriptor further identification | |
1579 | */ | |
1580 | static inline void ufshcd_init_query(struct ufs_hba *hba, | |
1581 | struct ufs_query_req **request, struct ufs_query_res **response, | |
1582 | enum query_opcode opcode, u8 idn, u8 index, u8 selector) | |
1583 | { | |
1584 | *request = &hba->dev_cmd.query.request; | |
1585 | *response = &hba->dev_cmd.query.response; | |
1586 | memset(*request, 0, sizeof(struct ufs_query_req)); | |
1587 | memset(*response, 0, sizeof(struct ufs_query_res)); | |
1588 | (*request)->upiu_req.opcode = opcode; | |
1589 | (*request)->upiu_req.idn = idn; | |
1590 | (*request)->upiu_req.index = index; | |
1591 | (*request)->upiu_req.selector = selector; | |
1592 | } | |
1593 | ||
68078d5c DR |
1594 | /** |
1595 | * ufshcd_query_flag() - API function for sending flag query requests | |
1596 | * hba: per-adapter instance | |
1597 | * query_opcode: flag query to perform | |
1598 | * idn: flag idn to access | |
1599 | * flag_res: the flag value after the query request completes | |
1600 | * | |
1601 | * Returns 0 for success, non-zero in case of failure | |
1602 | */ | |
1603 | static int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, | |
1604 | enum flag_idn idn, bool *flag_res) | |
1605 | { | |
d44a5f98 DR |
1606 | struct ufs_query_req *request = NULL; |
1607 | struct ufs_query_res *response = NULL; | |
1608 | int err, index = 0, selector = 0; | |
68078d5c DR |
1609 | |
1610 | BUG_ON(!hba); | |
1611 | ||
1ab27c9c | 1612 | ufshcd_hold(hba, false); |
68078d5c | 1613 | mutex_lock(&hba->dev_cmd.lock); |
d44a5f98 DR |
1614 | ufshcd_init_query(hba, &request, &response, opcode, idn, index, |
1615 | selector); | |
68078d5c DR |
1616 | |
1617 | switch (opcode) { | |
1618 | case UPIU_QUERY_OPCODE_SET_FLAG: | |
1619 | case UPIU_QUERY_OPCODE_CLEAR_FLAG: | |
1620 | case UPIU_QUERY_OPCODE_TOGGLE_FLAG: | |
1621 | request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; | |
1622 | break; | |
1623 | case UPIU_QUERY_OPCODE_READ_FLAG: | |
1624 | request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; | |
1625 | if (!flag_res) { | |
1626 | /* No dummy reads */ | |
1627 | dev_err(hba->dev, "%s: Invalid argument for read request\n", | |
1628 | __func__); | |
1629 | err = -EINVAL; | |
1630 | goto out_unlock; | |
1631 | } | |
1632 | break; | |
1633 | default: | |
1634 | dev_err(hba->dev, | |
1635 | "%s: Expected query flag opcode but got = %d\n", | |
1636 | __func__, opcode); | |
1637 | err = -EINVAL; | |
1638 | goto out_unlock; | |
1639 | } | |
68078d5c | 1640 | |
d44a5f98 | 1641 | err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); |
68078d5c DR |
1642 | |
1643 | if (err) { | |
1644 | dev_err(hba->dev, | |
1645 | "%s: Sending flag query for idn %d failed, err = %d\n", | |
1646 | __func__, idn, err); | |
1647 | goto out_unlock; | |
1648 | } | |
1649 | ||
1650 | if (flag_res) | |
e8c8e82a | 1651 | *flag_res = (be32_to_cpu(response->upiu_res.value) & |
68078d5c DR |
1652 | MASK_QUERY_UPIU_FLAG_LOC) & 0x1; |
1653 | ||
1654 | out_unlock: | |
1655 | mutex_unlock(&hba->dev_cmd.lock); | |
1ab27c9c | 1656 | ufshcd_release(hba); |
68078d5c DR |
1657 | return err; |
1658 | } | |
1659 | ||
66ec6d59 SRT |
1660 | /** |
1661 | * ufshcd_query_attr - API function for sending attribute requests | |
1662 | * hba: per-adapter instance | |
1663 | * opcode: attribute opcode | |
1664 | * idn: attribute idn to access | |
1665 | * index: index field | |
1666 | * selector: selector field | |
1667 | * attr_val: the attribute value after the query request completes | |
1668 | * | |
1669 | * Returns 0 for success, non-zero in case of failure | |
1670 | */ | |
bdbe5d2f | 1671 | static int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode, |
66ec6d59 SRT |
1672 | enum attr_idn idn, u8 index, u8 selector, u32 *attr_val) |
1673 | { | |
d44a5f98 DR |
1674 | struct ufs_query_req *request = NULL; |
1675 | struct ufs_query_res *response = NULL; | |
66ec6d59 SRT |
1676 | int err; |
1677 | ||
1678 | BUG_ON(!hba); | |
1679 | ||
1ab27c9c | 1680 | ufshcd_hold(hba, false); |
66ec6d59 SRT |
1681 | if (!attr_val) { |
1682 | dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n", | |
1683 | __func__, opcode); | |
1684 | err = -EINVAL; | |
1685 | goto out; | |
1686 | } | |
1687 | ||
1688 | mutex_lock(&hba->dev_cmd.lock); | |
d44a5f98 DR |
1689 | ufshcd_init_query(hba, &request, &response, opcode, idn, index, |
1690 | selector); | |
66ec6d59 SRT |
1691 | |
1692 | switch (opcode) { | |
1693 | case UPIU_QUERY_OPCODE_WRITE_ATTR: | |
1694 | request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; | |
e8c8e82a | 1695 | request->upiu_req.value = cpu_to_be32(*attr_val); |
66ec6d59 SRT |
1696 | break; |
1697 | case UPIU_QUERY_OPCODE_READ_ATTR: | |
1698 | request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; | |
1699 | break; | |
1700 | default: | |
1701 | dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n", | |
1702 | __func__, opcode); | |
1703 | err = -EINVAL; | |
1704 | goto out_unlock; | |
1705 | } | |
1706 | ||
d44a5f98 | 1707 | err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); |
66ec6d59 SRT |
1708 | |
1709 | if (err) { | |
1710 | dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, err = %d\n", | |
1711 | __func__, opcode, idn, err); | |
1712 | goto out_unlock; | |
1713 | } | |
1714 | ||
e8c8e82a | 1715 | *attr_val = be32_to_cpu(response->upiu_res.value); |
66ec6d59 SRT |
1716 | |
1717 | out_unlock: | |
1718 | mutex_unlock(&hba->dev_cmd.lock); | |
1719 | out: | |
1ab27c9c | 1720 | ufshcd_release(hba); |
66ec6d59 SRT |
1721 | return err; |
1722 | } | |
1723 | ||
d44a5f98 DR |
1724 | /** |
1725 | * ufshcd_query_descriptor - API function for sending descriptor requests | |
1726 | * hba: per-adapter instance | |
1727 | * opcode: attribute opcode | |
1728 | * idn: attribute idn to access | |
1729 | * index: index field | |
1730 | * selector: selector field | |
1731 | * desc_buf: the buffer that contains the descriptor | |
1732 | * buf_len: length parameter passed to the device | |
1733 | * | |
1734 | * Returns 0 for success, non-zero in case of failure. | |
1735 | * The buf_len parameter will contain, on return, the length parameter | |
1736 | * received on the response. | |
1737 | */ | |
7289f983 | 1738 | static int ufshcd_query_descriptor(struct ufs_hba *hba, |
d44a5f98 DR |
1739 | enum query_opcode opcode, enum desc_idn idn, u8 index, |
1740 | u8 selector, u8 *desc_buf, int *buf_len) | |
1741 | { | |
1742 | struct ufs_query_req *request = NULL; | |
1743 | struct ufs_query_res *response = NULL; | |
1744 | int err; | |
1745 | ||
1746 | BUG_ON(!hba); | |
1747 | ||
1ab27c9c | 1748 | ufshcd_hold(hba, false); |
d44a5f98 DR |
1749 | if (!desc_buf) { |
1750 | dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n", | |
1751 | __func__, opcode); | |
1752 | err = -EINVAL; | |
1753 | goto out; | |
1754 | } | |
1755 | ||
1756 | if (*buf_len <= QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) { | |
1757 | dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n", | |
1758 | __func__, *buf_len); | |
1759 | err = -EINVAL; | |
1760 | goto out; | |
1761 | } | |
1762 | ||
1763 | mutex_lock(&hba->dev_cmd.lock); | |
1764 | ufshcd_init_query(hba, &request, &response, opcode, idn, index, | |
1765 | selector); | |
1766 | hba->dev_cmd.query.descriptor = desc_buf; | |
ea2aab24 | 1767 | request->upiu_req.length = cpu_to_be16(*buf_len); |
d44a5f98 DR |
1768 | |
1769 | switch (opcode) { | |
1770 | case UPIU_QUERY_OPCODE_WRITE_DESC: | |
1771 | request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; | |
1772 | break; | |
1773 | case UPIU_QUERY_OPCODE_READ_DESC: | |
1774 | request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; | |
1775 | break; | |
1776 | default: | |
1777 | dev_err(hba->dev, | |
1778 | "%s: Expected query descriptor opcode but got = 0x%.2x\n", | |
1779 | __func__, opcode); | |
1780 | err = -EINVAL; | |
1781 | goto out_unlock; | |
1782 | } | |
1783 | ||
1784 | err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); | |
1785 | ||
1786 | if (err) { | |
1787 | dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, err = %d\n", | |
1788 | __func__, opcode, idn, err); | |
1789 | goto out_unlock; | |
1790 | } | |
1791 | ||
1792 | hba->dev_cmd.query.descriptor = NULL; | |
ea2aab24 | 1793 | *buf_len = be16_to_cpu(response->upiu_res.length); |
d44a5f98 DR |
1794 | |
1795 | out_unlock: | |
1796 | mutex_unlock(&hba->dev_cmd.lock); | |
1797 | out: | |
1ab27c9c | 1798 | ufshcd_release(hba); |
d44a5f98 DR |
1799 | return err; |
1800 | } | |
1801 | ||
da461cec SJ |
1802 | /** |
1803 | * ufshcd_read_desc_param - read the specified descriptor parameter | |
1804 | * @hba: Pointer to adapter instance | |
1805 | * @desc_id: descriptor idn value | |
1806 | * @desc_index: descriptor index | |
1807 | * @param_offset: offset of the parameter to read | |
1808 | * @param_read_buf: pointer to buffer where parameter would be read | |
1809 | * @param_size: sizeof(param_read_buf) | |
1810 | * | |
1811 | * Return 0 in case of success, non-zero otherwise | |
1812 | */ | |
1813 | static int ufshcd_read_desc_param(struct ufs_hba *hba, | |
1814 | enum desc_idn desc_id, | |
1815 | int desc_index, | |
1816 | u32 param_offset, | |
1817 | u8 *param_read_buf, | |
1818 | u32 param_size) | |
1819 | { | |
1820 | int ret; | |
1821 | u8 *desc_buf; | |
1822 | u32 buff_len; | |
1823 | bool is_kmalloc = true; | |
1824 | ||
1825 | /* safety checks */ | |
1826 | if (desc_id >= QUERY_DESC_IDN_MAX) | |
1827 | return -EINVAL; | |
1828 | ||
1829 | buff_len = ufs_query_desc_max_size[desc_id]; | |
1830 | if ((param_offset + param_size) > buff_len) | |
1831 | return -EINVAL; | |
1832 | ||
1833 | if (!param_offset && (param_size == buff_len)) { | |
1834 | /* memory space already available to hold full descriptor */ | |
1835 | desc_buf = param_read_buf; | |
1836 | is_kmalloc = false; | |
1837 | } else { | |
1838 | /* allocate memory to hold full descriptor */ | |
1839 | desc_buf = kmalloc(buff_len, GFP_KERNEL); | |
1840 | if (!desc_buf) | |
1841 | return -ENOMEM; | |
1842 | } | |
1843 | ||
1844 | ret = ufshcd_query_descriptor(hba, UPIU_QUERY_OPCODE_READ_DESC, | |
1845 | desc_id, desc_index, 0, desc_buf, | |
1846 | &buff_len); | |
1847 | ||
1848 | if (ret || (buff_len < ufs_query_desc_max_size[desc_id]) || | |
1849 | (desc_buf[QUERY_DESC_LENGTH_OFFSET] != | |
1850 | ufs_query_desc_max_size[desc_id]) | |
1851 | || (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id)) { | |
1852 | dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d param_offset %d buff_len %d ret %d", | |
1853 | __func__, desc_id, param_offset, buff_len, ret); | |
1854 | if (!ret) | |
1855 | ret = -EINVAL; | |
1856 | ||
1857 | goto out; | |
1858 | } | |
1859 | ||
1860 | if (is_kmalloc) | |
1861 | memcpy(param_read_buf, &desc_buf[param_offset], param_size); | |
1862 | out: | |
1863 | if (is_kmalloc) | |
1864 | kfree(desc_buf); | |
1865 | return ret; | |
1866 | } | |
1867 | ||
1868 | static inline int ufshcd_read_desc(struct ufs_hba *hba, | |
1869 | enum desc_idn desc_id, | |
1870 | int desc_index, | |
1871 | u8 *buf, | |
1872 | u32 size) | |
1873 | { | |
1874 | return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size); | |
1875 | } | |
1876 | ||
1877 | static inline int ufshcd_read_power_desc(struct ufs_hba *hba, | |
1878 | u8 *buf, | |
1879 | u32 size) | |
1880 | { | |
1881 | return ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0, buf, size); | |
1882 | } | |
1883 | ||
1884 | /** | |
1885 | * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter | |
1886 | * @hba: Pointer to adapter instance | |
1887 | * @lun: lun id | |
1888 | * @param_offset: offset of the parameter to read | |
1889 | * @param_read_buf: pointer to buffer where parameter would be read | |
1890 | * @param_size: sizeof(param_read_buf) | |
1891 | * | |
1892 | * Return 0 in case of success, non-zero otherwise | |
1893 | */ | |
1894 | static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba, | |
1895 | int lun, | |
1896 | enum unit_desc_param param_offset, | |
1897 | u8 *param_read_buf, | |
1898 | u32 param_size) | |
1899 | { | |
1900 | /* | |
1901 | * Unit descriptors are only available for general purpose LUs (LUN id | |
1902 | * from 0 to 7) and RPMB Well known LU. | |
1903 | */ | |
0ce147d4 | 1904 | if (lun != UFS_UPIU_RPMB_WLUN && (lun >= UFS_UPIU_MAX_GENERAL_LUN)) |
da461cec SJ |
1905 | return -EOPNOTSUPP; |
1906 | ||
1907 | return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun, | |
1908 | param_offset, param_read_buf, param_size); | |
1909 | } | |
1910 | ||
7a3e97b0 SY |
1911 | /** |
1912 | * ufshcd_memory_alloc - allocate memory for host memory space data structures | |
1913 | * @hba: per adapter instance | |
1914 | * | |
1915 | * 1. Allocate DMA memory for Command Descriptor array | |
1916 | * Each command descriptor consist of Command UPIU, Response UPIU and PRDT | |
1917 | * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL). | |
1918 | * 3. Allocate DMA memory for UTP Task Management Request Descriptor List | |
1919 | * (UTMRDL) | |
1920 | * 4. Allocate memory for local reference block(lrb). | |
1921 | * | |
1922 | * Returns 0 for success, non-zero in case of failure | |
1923 | */ | |
1924 | static int ufshcd_memory_alloc(struct ufs_hba *hba) | |
1925 | { | |
1926 | size_t utmrdl_size, utrdl_size, ucdl_size; | |
1927 | ||
1928 | /* Allocate memory for UTP command descriptors */ | |
1929 | ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs); | |
2953f850 SJ |
1930 | hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev, |
1931 | ucdl_size, | |
1932 | &hba->ucdl_dma_addr, | |
1933 | GFP_KERNEL); | |
7a3e97b0 SY |
1934 | |
1935 | /* | |
1936 | * UFSHCI requires UTP command descriptor to be 128 byte aligned. | |
1937 | * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE | |
1938 | * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will | |
1939 | * be aligned to 128 bytes as well | |
1940 | */ | |
1941 | if (!hba->ucdl_base_addr || | |
1942 | WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) { | |
3b1d0580 | 1943 | dev_err(hba->dev, |
7a3e97b0 SY |
1944 | "Command Descriptor Memory allocation failed\n"); |
1945 | goto out; | |
1946 | } | |
1947 | ||
1948 | /* | |
1949 | * Allocate memory for UTP Transfer descriptors | |
1950 | * UFSHCI requires 1024 byte alignment of UTRD | |
1951 | */ | |
1952 | utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs); | |
2953f850 SJ |
1953 | hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev, |
1954 | utrdl_size, | |
1955 | &hba->utrdl_dma_addr, | |
1956 | GFP_KERNEL); | |
7a3e97b0 SY |
1957 | if (!hba->utrdl_base_addr || |
1958 | WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) { | |
3b1d0580 | 1959 | dev_err(hba->dev, |
7a3e97b0 SY |
1960 | "Transfer Descriptor Memory allocation failed\n"); |
1961 | goto out; | |
1962 | } | |
1963 | ||
1964 | /* | |
1965 | * Allocate memory for UTP Task Management descriptors | |
1966 | * UFSHCI requires 1024 byte alignment of UTMRD | |
1967 | */ | |
1968 | utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs; | |
2953f850 SJ |
1969 | hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev, |
1970 | utmrdl_size, | |
1971 | &hba->utmrdl_dma_addr, | |
1972 | GFP_KERNEL); | |
7a3e97b0 SY |
1973 | if (!hba->utmrdl_base_addr || |
1974 | WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) { | |
3b1d0580 | 1975 | dev_err(hba->dev, |
7a3e97b0 SY |
1976 | "Task Management Descriptor Memory allocation failed\n"); |
1977 | goto out; | |
1978 | } | |
1979 | ||
1980 | /* Allocate memory for local reference block */ | |
2953f850 SJ |
1981 | hba->lrb = devm_kzalloc(hba->dev, |
1982 | hba->nutrs * sizeof(struct ufshcd_lrb), | |
1983 | GFP_KERNEL); | |
7a3e97b0 | 1984 | if (!hba->lrb) { |
3b1d0580 | 1985 | dev_err(hba->dev, "LRB Memory allocation failed\n"); |
7a3e97b0 SY |
1986 | goto out; |
1987 | } | |
1988 | return 0; | |
1989 | out: | |
7a3e97b0 SY |
1990 | return -ENOMEM; |
1991 | } | |
1992 | ||
1993 | /** | |
1994 | * ufshcd_host_memory_configure - configure local reference block with | |
1995 | * memory offsets | |
1996 | * @hba: per adapter instance | |
1997 | * | |
1998 | * Configure Host memory space | |
1999 | * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA | |
2000 | * address. | |
2001 | * 2. Update each UTRD with Response UPIU offset, Response UPIU length | |
2002 | * and PRDT offset. | |
2003 | * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT | |
2004 | * into local reference block. | |
2005 | */ | |
2006 | static void ufshcd_host_memory_configure(struct ufs_hba *hba) | |
2007 | { | |
2008 | struct utp_transfer_cmd_desc *cmd_descp; | |
2009 | struct utp_transfer_req_desc *utrdlp; | |
2010 | dma_addr_t cmd_desc_dma_addr; | |
2011 | dma_addr_t cmd_desc_element_addr; | |
2012 | u16 response_offset; | |
2013 | u16 prdt_offset; | |
2014 | int cmd_desc_size; | |
2015 | int i; | |
2016 | ||
2017 | utrdlp = hba->utrdl_base_addr; | |
2018 | cmd_descp = hba->ucdl_base_addr; | |
2019 | ||
2020 | response_offset = | |
2021 | offsetof(struct utp_transfer_cmd_desc, response_upiu); | |
2022 | prdt_offset = | |
2023 | offsetof(struct utp_transfer_cmd_desc, prd_table); | |
2024 | ||
2025 | cmd_desc_size = sizeof(struct utp_transfer_cmd_desc); | |
2026 | cmd_desc_dma_addr = hba->ucdl_dma_addr; | |
2027 | ||
2028 | for (i = 0; i < hba->nutrs; i++) { | |
2029 | /* Configure UTRD with command descriptor base address */ | |
2030 | cmd_desc_element_addr = | |
2031 | (cmd_desc_dma_addr + (cmd_desc_size * i)); | |
2032 | utrdlp[i].command_desc_base_addr_lo = | |
2033 | cpu_to_le32(lower_32_bits(cmd_desc_element_addr)); | |
2034 | utrdlp[i].command_desc_base_addr_hi = | |
2035 | cpu_to_le32(upper_32_bits(cmd_desc_element_addr)); | |
2036 | ||
2037 | /* Response upiu and prdt offset should be in double words */ | |
2038 | utrdlp[i].response_upiu_offset = | |
2039 | cpu_to_le16((response_offset >> 2)); | |
2040 | utrdlp[i].prd_table_offset = | |
2041 | cpu_to_le16((prdt_offset >> 2)); | |
2042 | utrdlp[i].response_upiu_length = | |
3ca316c5 | 2043 | cpu_to_le16(ALIGNED_UPIU_SIZE >> 2); |
7a3e97b0 SY |
2044 | |
2045 | hba->lrb[i].utr_descriptor_ptr = (utrdlp + i); | |
5a0b0cb9 SRT |
2046 | hba->lrb[i].ucd_req_ptr = |
2047 | (struct utp_upiu_req *)(cmd_descp + i); | |
7a3e97b0 SY |
2048 | hba->lrb[i].ucd_rsp_ptr = |
2049 | (struct utp_upiu_rsp *)cmd_descp[i].response_upiu; | |
2050 | hba->lrb[i].ucd_prdt_ptr = | |
2051 | (struct ufshcd_sg_entry *)cmd_descp[i].prd_table; | |
2052 | } | |
2053 | } | |
2054 | ||
2055 | /** | |
2056 | * ufshcd_dme_link_startup - Notify Unipro to perform link startup | |
2057 | * @hba: per adapter instance | |
2058 | * | |
2059 | * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer, | |
2060 | * in order to initialize the Unipro link startup procedure. | |
2061 | * Once the Unipro links are up, the device connected to the controller | |
2062 | * is detected. | |
2063 | * | |
2064 | * Returns 0 on success, non-zero value on failure | |
2065 | */ | |
2066 | static int ufshcd_dme_link_startup(struct ufs_hba *hba) | |
2067 | { | |
6ccf44fe SJ |
2068 | struct uic_command uic_cmd = {0}; |
2069 | int ret; | |
7a3e97b0 | 2070 | |
6ccf44fe | 2071 | uic_cmd.command = UIC_CMD_DME_LINK_STARTUP; |
7a3e97b0 | 2072 | |
6ccf44fe SJ |
2073 | ret = ufshcd_send_uic_cmd(hba, &uic_cmd); |
2074 | if (ret) | |
2075 | dev_err(hba->dev, | |
2076 | "dme-link-startup: error code %d\n", ret); | |
2077 | return ret; | |
7a3e97b0 SY |
2078 | } |
2079 | ||
cad2e03d YG |
2080 | static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba) |
2081 | { | |
2082 | #define MIN_DELAY_BEFORE_DME_CMDS_US 1000 | |
2083 | unsigned long min_sleep_time_us; | |
2084 | ||
2085 | if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS)) | |
2086 | return; | |
2087 | ||
2088 | /* | |
2089 | * last_dme_cmd_tstamp will be 0 only for 1st call to | |
2090 | * this function | |
2091 | */ | |
2092 | if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) { | |
2093 | min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US; | |
2094 | } else { | |
2095 | unsigned long delta = | |
2096 | (unsigned long) ktime_to_us( | |
2097 | ktime_sub(ktime_get(), | |
2098 | hba->last_dme_cmd_tstamp)); | |
2099 | ||
2100 | if (delta < MIN_DELAY_BEFORE_DME_CMDS_US) | |
2101 | min_sleep_time_us = | |
2102 | MIN_DELAY_BEFORE_DME_CMDS_US - delta; | |
2103 | else | |
2104 | return; /* no more delay required */ | |
2105 | } | |
2106 | ||
2107 | /* allow sleep for extra 50us if needed */ | |
2108 | usleep_range(min_sleep_time_us, min_sleep_time_us + 50); | |
2109 | } | |
2110 | ||
12b4fdb4 SJ |
2111 | /** |
2112 | * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET | |
2113 | * @hba: per adapter instance | |
2114 | * @attr_sel: uic command argument1 | |
2115 | * @attr_set: attribute set type as uic command argument2 | |
2116 | * @mib_val: setting value as uic command argument3 | |
2117 | * @peer: indicate whether peer or local | |
2118 | * | |
2119 | * Returns 0 on success, non-zero value on failure | |
2120 | */ | |
2121 | int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, | |
2122 | u8 attr_set, u32 mib_val, u8 peer) | |
2123 | { | |
2124 | struct uic_command uic_cmd = {0}; | |
2125 | static const char *const action[] = { | |
2126 | "dme-set", | |
2127 | "dme-peer-set" | |
2128 | }; | |
2129 | const char *set = action[!!peer]; | |
2130 | int ret; | |
2131 | ||
2132 | uic_cmd.command = peer ? | |
2133 | UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET; | |
2134 | uic_cmd.argument1 = attr_sel; | |
2135 | uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set); | |
2136 | uic_cmd.argument3 = mib_val; | |
2137 | ||
2138 | ret = ufshcd_send_uic_cmd(hba, &uic_cmd); | |
2139 | if (ret) | |
2140 | dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n", | |
2141 | set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret); | |
2142 | ||
2143 | return ret; | |
2144 | } | |
2145 | EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr); | |
2146 | ||
2147 | /** | |
2148 | * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET | |
2149 | * @hba: per adapter instance | |
2150 | * @attr_sel: uic command argument1 | |
2151 | * @mib_val: the value of the attribute as returned by the UIC command | |
2152 | * @peer: indicate whether peer or local | |
2153 | * | |
2154 | * Returns 0 on success, non-zero value on failure | |
2155 | */ | |
2156 | int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, | |
2157 | u32 *mib_val, u8 peer) | |
2158 | { | |
2159 | struct uic_command uic_cmd = {0}; | |
2160 | static const char *const action[] = { | |
2161 | "dme-get", | |
2162 | "dme-peer-get" | |
2163 | }; | |
2164 | const char *get = action[!!peer]; | |
2165 | int ret; | |
874237f7 YG |
2166 | struct ufs_pa_layer_attr orig_pwr_info; |
2167 | struct ufs_pa_layer_attr temp_pwr_info; | |
2168 | bool pwr_mode_change = false; | |
2169 | ||
2170 | if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) { | |
2171 | orig_pwr_info = hba->pwr_info; | |
2172 | temp_pwr_info = orig_pwr_info; | |
2173 | ||
2174 | if (orig_pwr_info.pwr_tx == FAST_MODE || | |
2175 | orig_pwr_info.pwr_rx == FAST_MODE) { | |
2176 | temp_pwr_info.pwr_tx = FASTAUTO_MODE; | |
2177 | temp_pwr_info.pwr_rx = FASTAUTO_MODE; | |
2178 | pwr_mode_change = true; | |
2179 | } else if (orig_pwr_info.pwr_tx == SLOW_MODE || | |
2180 | orig_pwr_info.pwr_rx == SLOW_MODE) { | |
2181 | temp_pwr_info.pwr_tx = SLOWAUTO_MODE; | |
2182 | temp_pwr_info.pwr_rx = SLOWAUTO_MODE; | |
2183 | pwr_mode_change = true; | |
2184 | } | |
2185 | if (pwr_mode_change) { | |
2186 | ret = ufshcd_change_power_mode(hba, &temp_pwr_info); | |
2187 | if (ret) | |
2188 | goto out; | |
2189 | } | |
2190 | } | |
12b4fdb4 SJ |
2191 | |
2192 | uic_cmd.command = peer ? | |
2193 | UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET; | |
2194 | uic_cmd.argument1 = attr_sel; | |
2195 | ||
2196 | ret = ufshcd_send_uic_cmd(hba, &uic_cmd); | |
2197 | if (ret) { | |
2198 | dev_err(hba->dev, "%s: attr-id 0x%x error code %d\n", | |
2199 | get, UIC_GET_ATTR_ID(attr_sel), ret); | |
2200 | goto out; | |
2201 | } | |
2202 | ||
2203 | if (mib_val) | |
2204 | *mib_val = uic_cmd.argument3; | |
874237f7 YG |
2205 | |
2206 | if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE) | |
2207 | && pwr_mode_change) | |
2208 | ufshcd_change_power_mode(hba, &orig_pwr_info); | |
12b4fdb4 SJ |
2209 | out: |
2210 | return ret; | |
2211 | } | |
2212 | EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr); | |
2213 | ||
53b3d9c3 | 2214 | /** |
57d104c1 SJ |
2215 | * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power |
2216 | * state) and waits for it to take effect. | |
2217 | * | |
53b3d9c3 | 2218 | * @hba: per adapter instance |
57d104c1 SJ |
2219 | * @cmd: UIC command to execute |
2220 | * | |
2221 | * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER & | |
2222 | * DME_HIBERNATE_EXIT commands take some time to take its effect on both host | |
2223 | * and device UniPro link and hence it's final completion would be indicated by | |
2224 | * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in | |
2225 | * addition to normal UIC command completion Status (UCCS). This function only | |
2226 | * returns after the relevant status bits indicate the completion. | |
53b3d9c3 SJ |
2227 | * |
2228 | * Returns 0 on success, non-zero value on failure | |
2229 | */ | |
57d104c1 | 2230 | static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd) |
53b3d9c3 | 2231 | { |
57d104c1 | 2232 | struct completion uic_async_done; |
53b3d9c3 SJ |
2233 | unsigned long flags; |
2234 | u8 status; | |
2235 | int ret; | |
2236 | ||
53b3d9c3 | 2237 | mutex_lock(&hba->uic_cmd_mutex); |
57d104c1 | 2238 | init_completion(&uic_async_done); |
cad2e03d | 2239 | ufshcd_add_delay_before_dme_cmd(hba); |
53b3d9c3 SJ |
2240 | |
2241 | spin_lock_irqsave(hba->host->host_lock, flags); | |
57d104c1 SJ |
2242 | hba->uic_async_done = &uic_async_done; |
2243 | ret = __ufshcd_send_uic_cmd(hba, cmd); | |
53b3d9c3 | 2244 | spin_unlock_irqrestore(hba->host->host_lock, flags); |
53b3d9c3 SJ |
2245 | if (ret) { |
2246 | dev_err(hba->dev, | |
57d104c1 SJ |
2247 | "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n", |
2248 | cmd->command, cmd->argument3, ret); | |
2249 | goto out; | |
2250 | } | |
2251 | ret = ufshcd_wait_for_uic_cmd(hba, cmd); | |
2252 | if (ret) { | |
2253 | dev_err(hba->dev, | |
2254 | "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n", | |
2255 | cmd->command, cmd->argument3, ret); | |
53b3d9c3 SJ |
2256 | goto out; |
2257 | } | |
2258 | ||
57d104c1 | 2259 | if (!wait_for_completion_timeout(hba->uic_async_done, |
53b3d9c3 SJ |
2260 | msecs_to_jiffies(UIC_CMD_TIMEOUT))) { |
2261 | dev_err(hba->dev, | |
57d104c1 SJ |
2262 | "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n", |
2263 | cmd->command, cmd->argument3); | |
53b3d9c3 SJ |
2264 | ret = -ETIMEDOUT; |
2265 | goto out; | |
2266 | } | |
2267 | ||
2268 | status = ufshcd_get_upmcrs(hba); | |
2269 | if (status != PWR_LOCAL) { | |
2270 | dev_err(hba->dev, | |
57d104c1 SJ |
2271 | "pwr ctrl cmd 0x%0x failed, host umpcrs:0x%x\n", |
2272 | cmd->command, status); | |
53b3d9c3 SJ |
2273 | ret = (status != PWR_OK) ? status : -1; |
2274 | } | |
2275 | out: | |
2276 | spin_lock_irqsave(hba->host->host_lock, flags); | |
57d104c1 | 2277 | hba->uic_async_done = NULL; |
53b3d9c3 SJ |
2278 | spin_unlock_irqrestore(hba->host->host_lock, flags); |
2279 | mutex_unlock(&hba->uic_cmd_mutex); | |
1ab27c9c | 2280 | |
53b3d9c3 SJ |
2281 | return ret; |
2282 | } | |
2283 | ||
57d104c1 SJ |
2284 | /** |
2285 | * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage | |
2286 | * using DME_SET primitives. | |
2287 | * @hba: per adapter instance | |
2288 | * @mode: powr mode value | |
2289 | * | |
2290 | * Returns 0 on success, non-zero value on failure | |
2291 | */ | |
2292 | static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode) | |
2293 | { | |
2294 | struct uic_command uic_cmd = {0}; | |
1ab27c9c | 2295 | int ret; |
57d104c1 | 2296 | |
c3a2f9ee YG |
2297 | if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) { |
2298 | ret = ufshcd_dme_set(hba, | |
2299 | UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1); | |
2300 | if (ret) { | |
2301 | dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n", | |
2302 | __func__, ret); | |
2303 | goto out; | |
2304 | } | |
2305 | } | |
2306 | ||
57d104c1 SJ |
2307 | uic_cmd.command = UIC_CMD_DME_SET; |
2308 | uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE); | |
2309 | uic_cmd.argument3 = mode; | |
1ab27c9c ST |
2310 | ufshcd_hold(hba, false); |
2311 | ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); | |
2312 | ufshcd_release(hba); | |
57d104c1 | 2313 | |
c3a2f9ee | 2314 | out: |
1ab27c9c | 2315 | return ret; |
57d104c1 SJ |
2316 | } |
2317 | ||
2318 | static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba) | |
2319 | { | |
2320 | struct uic_command uic_cmd = {0}; | |
2321 | ||
2322 | uic_cmd.command = UIC_CMD_DME_HIBER_ENTER; | |
2323 | ||
2324 | return ufshcd_uic_pwr_ctrl(hba, &uic_cmd); | |
2325 | } | |
2326 | ||
2327 | static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba) | |
2328 | { | |
2329 | struct uic_command uic_cmd = {0}; | |
2330 | int ret; | |
2331 | ||
2332 | uic_cmd.command = UIC_CMD_DME_HIBER_EXIT; | |
2333 | ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); | |
2334 | if (ret) { | |
2335 | ufshcd_set_link_off(hba); | |
2336 | ret = ufshcd_host_reset_and_restore(hba); | |
2337 | } | |
2338 | ||
2339 | return ret; | |
2340 | } | |
2341 | ||
5064636c YG |
2342 | /** |
2343 | * ufshcd_init_pwr_info - setting the POR (power on reset) | |
2344 | * values in hba power info | |
2345 | * @hba: per-adapter instance | |
2346 | */ | |
2347 | static void ufshcd_init_pwr_info(struct ufs_hba *hba) | |
2348 | { | |
2349 | hba->pwr_info.gear_rx = UFS_PWM_G1; | |
2350 | hba->pwr_info.gear_tx = UFS_PWM_G1; | |
2351 | hba->pwr_info.lane_rx = 1; | |
2352 | hba->pwr_info.lane_tx = 1; | |
2353 | hba->pwr_info.pwr_rx = SLOWAUTO_MODE; | |
2354 | hba->pwr_info.pwr_tx = SLOWAUTO_MODE; | |
2355 | hba->pwr_info.hs_rate = 0; | |
2356 | } | |
2357 | ||
d3e89bac | 2358 | /** |
7eb584db DR |
2359 | * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device |
2360 | * @hba: per-adapter instance | |
d3e89bac | 2361 | */ |
7eb584db | 2362 | static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba) |
d3e89bac | 2363 | { |
7eb584db DR |
2364 | struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; |
2365 | ||
2366 | if (hba->max_pwr_info.is_valid) | |
2367 | return 0; | |
2368 | ||
2369 | pwr_info->pwr_tx = FASTAUTO_MODE; | |
2370 | pwr_info->pwr_rx = FASTAUTO_MODE; | |
2371 | pwr_info->hs_rate = PA_HS_MODE_B; | |
d3e89bac SJ |
2372 | |
2373 | /* Get the connected lane count */ | |
7eb584db DR |
2374 | ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES), |
2375 | &pwr_info->lane_rx); | |
2376 | ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), | |
2377 | &pwr_info->lane_tx); | |
2378 | ||
2379 | if (!pwr_info->lane_rx || !pwr_info->lane_tx) { | |
2380 | dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n", | |
2381 | __func__, | |
2382 | pwr_info->lane_rx, | |
2383 | pwr_info->lane_tx); | |
2384 | return -EINVAL; | |
2385 | } | |
d3e89bac SJ |
2386 | |
2387 | /* | |
2388 | * First, get the maximum gears of HS speed. | |
2389 | * If a zero value, it means there is no HSGEAR capability. | |
2390 | * Then, get the maximum gears of PWM speed. | |
2391 | */ | |
7eb584db DR |
2392 | ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx); |
2393 | if (!pwr_info->gear_rx) { | |
2394 | ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), | |
2395 | &pwr_info->gear_rx); | |
2396 | if (!pwr_info->gear_rx) { | |
2397 | dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n", | |
2398 | __func__, pwr_info->gear_rx); | |
2399 | return -EINVAL; | |
2400 | } | |
2401 | pwr_info->pwr_rx = SLOWAUTO_MODE; | |
d3e89bac SJ |
2402 | } |
2403 | ||
7eb584db DR |
2404 | ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), |
2405 | &pwr_info->gear_tx); | |
2406 | if (!pwr_info->gear_tx) { | |
d3e89bac | 2407 | ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), |
7eb584db DR |
2408 | &pwr_info->gear_tx); |
2409 | if (!pwr_info->gear_tx) { | |
2410 | dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n", | |
2411 | __func__, pwr_info->gear_tx); | |
2412 | return -EINVAL; | |
2413 | } | |
2414 | pwr_info->pwr_tx = SLOWAUTO_MODE; | |
2415 | } | |
2416 | ||
2417 | hba->max_pwr_info.is_valid = true; | |
2418 | return 0; | |
2419 | } | |
2420 | ||
2421 | static int ufshcd_change_power_mode(struct ufs_hba *hba, | |
2422 | struct ufs_pa_layer_attr *pwr_mode) | |
2423 | { | |
2424 | int ret; | |
2425 | ||
2426 | /* if already configured to the requested pwr_mode */ | |
2427 | if (pwr_mode->gear_rx == hba->pwr_info.gear_rx && | |
2428 | pwr_mode->gear_tx == hba->pwr_info.gear_tx && | |
2429 | pwr_mode->lane_rx == hba->pwr_info.lane_rx && | |
2430 | pwr_mode->lane_tx == hba->pwr_info.lane_tx && | |
2431 | pwr_mode->pwr_rx == hba->pwr_info.pwr_rx && | |
2432 | pwr_mode->pwr_tx == hba->pwr_info.pwr_tx && | |
2433 | pwr_mode->hs_rate == hba->pwr_info.hs_rate) { | |
2434 | dev_dbg(hba->dev, "%s: power already configured\n", __func__); | |
2435 | return 0; | |
d3e89bac SJ |
2436 | } |
2437 | ||
2438 | /* | |
2439 | * Configure attributes for power mode change with below. | |
2440 | * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION, | |
2441 | * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION, | |
2442 | * - PA_HSSERIES | |
2443 | */ | |
7eb584db DR |
2444 | ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx); |
2445 | ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES), | |
2446 | pwr_mode->lane_rx); | |
2447 | if (pwr_mode->pwr_rx == FASTAUTO_MODE || | |
2448 | pwr_mode->pwr_rx == FAST_MODE) | |
d3e89bac | 2449 | ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE); |
7eb584db DR |
2450 | else |
2451 | ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE); | |
d3e89bac | 2452 | |
7eb584db DR |
2453 | ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx); |
2454 | ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES), | |
2455 | pwr_mode->lane_tx); | |
2456 | if (pwr_mode->pwr_tx == FASTAUTO_MODE || | |
2457 | pwr_mode->pwr_tx == FAST_MODE) | |
d3e89bac | 2458 | ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE); |
7eb584db DR |
2459 | else |
2460 | ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE); | |
d3e89bac | 2461 | |
7eb584db DR |
2462 | if (pwr_mode->pwr_rx == FASTAUTO_MODE || |
2463 | pwr_mode->pwr_tx == FASTAUTO_MODE || | |
2464 | pwr_mode->pwr_rx == FAST_MODE || | |
2465 | pwr_mode->pwr_tx == FAST_MODE) | |
2466 | ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES), | |
2467 | pwr_mode->hs_rate); | |
d3e89bac | 2468 | |
7eb584db DR |
2469 | ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4 |
2470 | | pwr_mode->pwr_tx); | |
2471 | ||
2472 | if (ret) { | |
d3e89bac | 2473 | dev_err(hba->dev, |
7eb584db DR |
2474 | "%s: power mode change failed %d\n", __func__, ret); |
2475 | } else { | |
2476 | if (hba->vops && hba->vops->pwr_change_notify) | |
2477 | hba->vops->pwr_change_notify(hba, | |
2478 | POST_CHANGE, NULL, pwr_mode); | |
2479 | ||
2480 | memcpy(&hba->pwr_info, pwr_mode, | |
2481 | sizeof(struct ufs_pa_layer_attr)); | |
2482 | } | |
2483 | ||
2484 | return ret; | |
2485 | } | |
2486 | ||
2487 | /** | |
2488 | * ufshcd_config_pwr_mode - configure a new power mode | |
2489 | * @hba: per-adapter instance | |
2490 | * @desired_pwr_mode: desired power configuration | |
2491 | */ | |
2492 | static int ufshcd_config_pwr_mode(struct ufs_hba *hba, | |
2493 | struct ufs_pa_layer_attr *desired_pwr_mode) | |
2494 | { | |
2495 | struct ufs_pa_layer_attr final_params = { 0 }; | |
2496 | int ret; | |
2497 | ||
2498 | if (hba->vops && hba->vops->pwr_change_notify) | |
2499 | hba->vops->pwr_change_notify(hba, | |
2500 | PRE_CHANGE, desired_pwr_mode, &final_params); | |
2501 | else | |
2502 | memcpy(&final_params, desired_pwr_mode, sizeof(final_params)); | |
2503 | ||
2504 | ret = ufshcd_change_power_mode(hba, &final_params); | |
d3e89bac SJ |
2505 | |
2506 | return ret; | |
2507 | } | |
2508 | ||
68078d5c DR |
2509 | /** |
2510 | * ufshcd_complete_dev_init() - checks device readiness | |
2511 | * hba: per-adapter instance | |
2512 | * | |
2513 | * Set fDeviceInit flag and poll until device toggles it. | |
2514 | */ | |
2515 | static int ufshcd_complete_dev_init(struct ufs_hba *hba) | |
2516 | { | |
2517 | int i, retries, err = 0; | |
2518 | bool flag_res = 1; | |
2519 | ||
2520 | for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { | |
2521 | /* Set the fDeviceInit flag */ | |
2522 | err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_SET_FLAG, | |
2523 | QUERY_FLAG_IDN_FDEVICEINIT, NULL); | |
2524 | if (!err || err == -ETIMEDOUT) | |
2525 | break; | |
2526 | dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err); | |
2527 | } | |
2528 | if (err) { | |
2529 | dev_err(hba->dev, | |
2530 | "%s setting fDeviceInit flag failed with error %d\n", | |
2531 | __func__, err); | |
2532 | goto out; | |
2533 | } | |
2534 | ||
2535 | /* poll for max. 100 iterations for fDeviceInit flag to clear */ | |
2536 | for (i = 0; i < 100 && !err && flag_res; i++) { | |
2537 | for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { | |
2538 | err = ufshcd_query_flag(hba, | |
2539 | UPIU_QUERY_OPCODE_READ_FLAG, | |
2540 | QUERY_FLAG_IDN_FDEVICEINIT, &flag_res); | |
2541 | if (!err || err == -ETIMEDOUT) | |
2542 | break; | |
2543 | dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, | |
2544 | err); | |
2545 | } | |
2546 | } | |
2547 | if (err) | |
2548 | dev_err(hba->dev, | |
2549 | "%s reading fDeviceInit flag failed with error %d\n", | |
2550 | __func__, err); | |
2551 | else if (flag_res) | |
2552 | dev_err(hba->dev, | |
2553 | "%s fDeviceInit was not cleared by the device\n", | |
2554 | __func__); | |
2555 | ||
2556 | out: | |
2557 | return err; | |
2558 | } | |
2559 | ||
7a3e97b0 SY |
2560 | /** |
2561 | * ufshcd_make_hba_operational - Make UFS controller operational | |
2562 | * @hba: per adapter instance | |
2563 | * | |
2564 | * To bring UFS host controller to operational state, | |
5c0c28a8 SRT |
2565 | * 1. Enable required interrupts |
2566 | * 2. Configure interrupt aggregation | |
2567 | * 3. Program UTRL and UTMRL base addres | |
2568 | * 4. Configure run-stop-registers | |
7a3e97b0 SY |
2569 | * |
2570 | * Returns 0 on success, non-zero value on failure | |
2571 | */ | |
2572 | static int ufshcd_make_hba_operational(struct ufs_hba *hba) | |
2573 | { | |
2574 | int err = 0; | |
2575 | u32 reg; | |
2576 | ||
6ccf44fe SJ |
2577 | /* Enable required interrupts */ |
2578 | ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS); | |
2579 | ||
2580 | /* Configure interrupt aggregation */ | |
b852190e YG |
2581 | if (ufshcd_is_intr_aggr_allowed(hba)) |
2582 | ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO); | |
2583 | else | |
2584 | ufshcd_disable_intr_aggr(hba); | |
6ccf44fe SJ |
2585 | |
2586 | /* Configure UTRL and UTMRL base address registers */ | |
2587 | ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr), | |
2588 | REG_UTP_TRANSFER_REQ_LIST_BASE_L); | |
2589 | ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr), | |
2590 | REG_UTP_TRANSFER_REQ_LIST_BASE_H); | |
2591 | ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr), | |
2592 | REG_UTP_TASK_REQ_LIST_BASE_L); | |
2593 | ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr), | |
2594 | REG_UTP_TASK_REQ_LIST_BASE_H); | |
2595 | ||
7a3e97b0 SY |
2596 | /* |
2597 | * UCRDY, UTMRLDY and UTRLRDY bits must be 1 | |
2598 | * DEI, HEI bits must be 0 | |
2599 | */ | |
5c0c28a8 | 2600 | reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS); |
7a3e97b0 SY |
2601 | if (!(ufshcd_get_lists_status(reg))) { |
2602 | ufshcd_enable_run_stop_reg(hba); | |
2603 | } else { | |
3b1d0580 | 2604 | dev_err(hba->dev, |
7a3e97b0 SY |
2605 | "Host controller not ready to process requests"); |
2606 | err = -EIO; | |
2607 | goto out; | |
2608 | } | |
2609 | ||
7a3e97b0 SY |
2610 | out: |
2611 | return err; | |
2612 | } | |
2613 | ||
2614 | /** | |
2615 | * ufshcd_hba_enable - initialize the controller | |
2616 | * @hba: per adapter instance | |
2617 | * | |
2618 | * The controller resets itself and controller firmware initialization | |
2619 | * sequence kicks off. When controller is ready it will set | |
2620 | * the Host Controller Enable bit to 1. | |
2621 | * | |
2622 | * Returns 0 on success, non-zero value on failure | |
2623 | */ | |
2624 | static int ufshcd_hba_enable(struct ufs_hba *hba) | |
2625 | { | |
2626 | int retry; | |
2627 | ||
2628 | /* | |
2629 | * msleep of 1 and 5 used in this function might result in msleep(20), | |
2630 | * but it was necessary to send the UFS FPGA to reset mode during | |
2631 | * development and testing of this driver. msleep can be changed to | |
2632 | * mdelay and retry count can be reduced based on the controller. | |
2633 | */ | |
2634 | if (!ufshcd_is_hba_active(hba)) { | |
2635 | ||
2636 | /* change controller state to "reset state" */ | |
2637 | ufshcd_hba_stop(hba); | |
2638 | ||
2639 | /* | |
2640 | * This delay is based on the testing done with UFS host | |
2641 | * controller FPGA. The delay can be changed based on the | |
2642 | * host controller used. | |
2643 | */ | |
2644 | msleep(5); | |
2645 | } | |
2646 | ||
57d104c1 SJ |
2647 | /* UniPro link is disabled at this point */ |
2648 | ufshcd_set_link_off(hba); | |
2649 | ||
5c0c28a8 SRT |
2650 | if (hba->vops && hba->vops->hce_enable_notify) |
2651 | hba->vops->hce_enable_notify(hba, PRE_CHANGE); | |
2652 | ||
7a3e97b0 SY |
2653 | /* start controller initialization sequence */ |
2654 | ufshcd_hba_start(hba); | |
2655 | ||
2656 | /* | |
2657 | * To initialize a UFS host controller HCE bit must be set to 1. | |
2658 | * During initialization the HCE bit value changes from 1->0->1. | |
2659 | * When the host controller completes initialization sequence | |
2660 | * it sets the value of HCE bit to 1. The same HCE bit is read back | |
2661 | * to check if the controller has completed initialization sequence. | |
2662 | * So without this delay the value HCE = 1, set in the previous | |
2663 | * instruction might be read back. | |
2664 | * This delay can be changed based on the controller. | |
2665 | */ | |
2666 | msleep(1); | |
2667 | ||
2668 | /* wait for the host controller to complete initialization */ | |
2669 | retry = 10; | |
2670 | while (ufshcd_is_hba_active(hba)) { | |
2671 | if (retry) { | |
2672 | retry--; | |
2673 | } else { | |
3b1d0580 | 2674 | dev_err(hba->dev, |
7a3e97b0 SY |
2675 | "Controller enable failed\n"); |
2676 | return -EIO; | |
2677 | } | |
2678 | msleep(5); | |
2679 | } | |
5c0c28a8 | 2680 | |
1d337ec2 | 2681 | /* enable UIC related interrupts */ |
57d104c1 | 2682 | ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); |
1d337ec2 | 2683 | |
5c0c28a8 SRT |
2684 | if (hba->vops && hba->vops->hce_enable_notify) |
2685 | hba->vops->hce_enable_notify(hba, POST_CHANGE); | |
2686 | ||
7a3e97b0 SY |
2687 | return 0; |
2688 | } | |
2689 | ||
7ca38cf3 YG |
2690 | static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer) |
2691 | { | |
2692 | int tx_lanes, i, err = 0; | |
2693 | ||
2694 | if (!peer) | |
2695 | ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), | |
2696 | &tx_lanes); | |
2697 | else | |
2698 | ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), | |
2699 | &tx_lanes); | |
2700 | for (i = 0; i < tx_lanes; i++) { | |
2701 | if (!peer) | |
2702 | err = ufshcd_dme_set(hba, | |
2703 | UIC_ARG_MIB_SEL(TX_LCC_ENABLE, | |
2704 | UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), | |
2705 | 0); | |
2706 | else | |
2707 | err = ufshcd_dme_peer_set(hba, | |
2708 | UIC_ARG_MIB_SEL(TX_LCC_ENABLE, | |
2709 | UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), | |
2710 | 0); | |
2711 | if (err) { | |
2712 | dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d", | |
2713 | __func__, peer, i, err); | |
2714 | break; | |
2715 | } | |
2716 | } | |
2717 | ||
2718 | return err; | |
2719 | } | |
2720 | ||
2721 | static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba) | |
2722 | { | |
2723 | return ufshcd_disable_tx_lcc(hba, true); | |
2724 | } | |
2725 | ||
7a3e97b0 | 2726 | /** |
6ccf44fe | 2727 | * ufshcd_link_startup - Initialize unipro link startup |
7a3e97b0 SY |
2728 | * @hba: per adapter instance |
2729 | * | |
6ccf44fe | 2730 | * Returns 0 for success, non-zero in case of failure |
7a3e97b0 | 2731 | */ |
6ccf44fe | 2732 | static int ufshcd_link_startup(struct ufs_hba *hba) |
7a3e97b0 | 2733 | { |
6ccf44fe | 2734 | int ret; |
1d337ec2 | 2735 | int retries = DME_LINKSTARTUP_RETRIES; |
7a3e97b0 | 2736 | |
1d337ec2 SRT |
2737 | do { |
2738 | if (hba->vops && hba->vops->link_startup_notify) | |
2739 | hba->vops->link_startup_notify(hba, PRE_CHANGE); | |
6ccf44fe | 2740 | |
1d337ec2 | 2741 | ret = ufshcd_dme_link_startup(hba); |
5c0c28a8 | 2742 | |
1d337ec2 SRT |
2743 | /* check if device is detected by inter-connect layer */ |
2744 | if (!ret && !ufshcd_is_device_present(hba)) { | |
2745 | dev_err(hba->dev, "%s: Device not present\n", __func__); | |
2746 | ret = -ENXIO; | |
2747 | goto out; | |
2748 | } | |
6ccf44fe | 2749 | |
1d337ec2 SRT |
2750 | /* |
2751 | * DME link lost indication is only received when link is up, | |
2752 | * but we can't be sure if the link is up until link startup | |
2753 | * succeeds. So reset the local Uni-Pro and try again. | |
2754 | */ | |
2755 | if (ret && ufshcd_hba_enable(hba)) | |
2756 | goto out; | |
2757 | } while (ret && retries--); | |
2758 | ||
2759 | if (ret) | |
2760 | /* failed to get the link up... retire */ | |
5c0c28a8 | 2761 | goto out; |
5c0c28a8 | 2762 | |
7ca38cf3 YG |
2763 | if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) { |
2764 | ret = ufshcd_disable_device_tx_lcc(hba); | |
2765 | if (ret) | |
2766 | goto out; | |
2767 | } | |
2768 | ||
5c0c28a8 SRT |
2769 | /* Include any host controller configuration via UIC commands */ |
2770 | if (hba->vops && hba->vops->link_startup_notify) { | |
2771 | ret = hba->vops->link_startup_notify(hba, POST_CHANGE); | |
2772 | if (ret) | |
2773 | goto out; | |
2774 | } | |
7a3e97b0 | 2775 | |
5c0c28a8 | 2776 | ret = ufshcd_make_hba_operational(hba); |
6ccf44fe SJ |
2777 | out: |
2778 | if (ret) | |
2779 | dev_err(hba->dev, "link startup failed %d\n", ret); | |
2780 | return ret; | |
7a3e97b0 SY |
2781 | } |
2782 | ||
5a0b0cb9 SRT |
2783 | /** |
2784 | * ufshcd_verify_dev_init() - Verify device initialization | |
2785 | * @hba: per-adapter instance | |
2786 | * | |
2787 | * Send NOP OUT UPIU and wait for NOP IN response to check whether the | |
2788 | * device Transport Protocol (UTP) layer is ready after a reset. | |
2789 | * If the UTP layer at the device side is not initialized, it may | |
2790 | * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT | |
2791 | * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations. | |
2792 | */ | |
2793 | static int ufshcd_verify_dev_init(struct ufs_hba *hba) | |
2794 | { | |
2795 | int err = 0; | |
2796 | int retries; | |
2797 | ||
1ab27c9c | 2798 | ufshcd_hold(hba, false); |
5a0b0cb9 SRT |
2799 | mutex_lock(&hba->dev_cmd.lock); |
2800 | for (retries = NOP_OUT_RETRIES; retries > 0; retries--) { | |
2801 | err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP, | |
2802 | NOP_OUT_TIMEOUT); | |
2803 | ||
2804 | if (!err || err == -ETIMEDOUT) | |
2805 | break; | |
2806 | ||
2807 | dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err); | |
2808 | } | |
2809 | mutex_unlock(&hba->dev_cmd.lock); | |
1ab27c9c | 2810 | ufshcd_release(hba); |
5a0b0cb9 SRT |
2811 | |
2812 | if (err) | |
2813 | dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err); | |
2814 | return err; | |
2815 | } | |
2816 | ||
0ce147d4 SJ |
2817 | /** |
2818 | * ufshcd_set_queue_depth - set lun queue depth | |
2819 | * @sdev: pointer to SCSI device | |
2820 | * | |
2821 | * Read bLUQueueDepth value and activate scsi tagged command | |
2822 | * queueing. For WLUN, queue depth is set to 1. For best-effort | |
2823 | * cases (bLUQueueDepth = 0) the queue depth is set to a maximum | |
2824 | * value that host can queue. | |
2825 | */ | |
2826 | static void ufshcd_set_queue_depth(struct scsi_device *sdev) | |
2827 | { | |
2828 | int ret = 0; | |
2829 | u8 lun_qdepth; | |
2830 | struct ufs_hba *hba; | |
2831 | ||
2832 | hba = shost_priv(sdev->host); | |
2833 | ||
2834 | lun_qdepth = hba->nutrs; | |
2835 | ret = ufshcd_read_unit_desc_param(hba, | |
2836 | ufshcd_scsi_to_upiu_lun(sdev->lun), | |
2837 | UNIT_DESC_PARAM_LU_Q_DEPTH, | |
2838 | &lun_qdepth, | |
2839 | sizeof(lun_qdepth)); | |
2840 | ||
2841 | /* Some WLUN doesn't support unit descriptor */ | |
2842 | if (ret == -EOPNOTSUPP) | |
2843 | lun_qdepth = 1; | |
2844 | else if (!lun_qdepth) | |
2845 | /* eventually, we can figure out the real queue depth */ | |
2846 | lun_qdepth = hba->nutrs; | |
2847 | else | |
2848 | lun_qdepth = min_t(int, lun_qdepth, hba->nutrs); | |
2849 | ||
2850 | dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n", | |
2851 | __func__, lun_qdepth); | |
db5ed4df | 2852 | scsi_change_queue_depth(sdev, lun_qdepth); |
0ce147d4 SJ |
2853 | } |
2854 | ||
57d104c1 SJ |
2855 | /* |
2856 | * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR | |
2857 | * @hba: per-adapter instance | |
2858 | * @lun: UFS device lun id | |
2859 | * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info | |
2860 | * | |
2861 | * Returns 0 in case of success and b_lu_write_protect status would be returned | |
2862 | * @b_lu_write_protect parameter. | |
2863 | * Returns -ENOTSUPP if reading b_lu_write_protect is not supported. | |
2864 | * Returns -EINVAL in case of invalid parameters passed to this function. | |
2865 | */ | |
2866 | static int ufshcd_get_lu_wp(struct ufs_hba *hba, | |
2867 | u8 lun, | |
2868 | u8 *b_lu_write_protect) | |
2869 | { | |
2870 | int ret; | |
2871 | ||
2872 | if (!b_lu_write_protect) | |
2873 | ret = -EINVAL; | |
2874 | /* | |
2875 | * According to UFS device spec, RPMB LU can't be write | |
2876 | * protected so skip reading bLUWriteProtect parameter for | |
2877 | * it. For other W-LUs, UNIT DESCRIPTOR is not available. | |
2878 | */ | |
2879 | else if (lun >= UFS_UPIU_MAX_GENERAL_LUN) | |
2880 | ret = -ENOTSUPP; | |
2881 | else | |
2882 | ret = ufshcd_read_unit_desc_param(hba, | |
2883 | lun, | |
2884 | UNIT_DESC_PARAM_LU_WR_PROTECT, | |
2885 | b_lu_write_protect, | |
2886 | sizeof(*b_lu_write_protect)); | |
2887 | return ret; | |
2888 | } | |
2889 | ||
2890 | /** | |
2891 | * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect | |
2892 | * status | |
2893 | * @hba: per-adapter instance | |
2894 | * @sdev: pointer to SCSI device | |
2895 | * | |
2896 | */ | |
2897 | static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba, | |
2898 | struct scsi_device *sdev) | |
2899 | { | |
2900 | if (hba->dev_info.f_power_on_wp_en && | |
2901 | !hba->dev_info.is_lu_power_on_wp) { | |
2902 | u8 b_lu_write_protect; | |
2903 | ||
2904 | if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun), | |
2905 | &b_lu_write_protect) && | |
2906 | (b_lu_write_protect == UFS_LU_POWER_ON_WP)) | |
2907 | hba->dev_info.is_lu_power_on_wp = true; | |
2908 | } | |
2909 | } | |
2910 | ||
7a3e97b0 SY |
2911 | /** |
2912 | * ufshcd_slave_alloc - handle initial SCSI device configurations | |
2913 | * @sdev: pointer to SCSI device | |
2914 | * | |
2915 | * Returns success | |
2916 | */ | |
2917 | static int ufshcd_slave_alloc(struct scsi_device *sdev) | |
2918 | { | |
2919 | struct ufs_hba *hba; | |
2920 | ||
2921 | hba = shost_priv(sdev->host); | |
7a3e97b0 SY |
2922 | |
2923 | /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */ | |
2924 | sdev->use_10_for_ms = 1; | |
7a3e97b0 | 2925 | |
e8e7f271 SRT |
2926 | /* allow SCSI layer to restart the device in case of errors */ |
2927 | sdev->allow_restart = 1; | |
4264fd61 | 2928 | |
b2a6c522 SRT |
2929 | /* REPORT SUPPORTED OPERATION CODES is not supported */ |
2930 | sdev->no_report_opcodes = 1; | |
2931 | ||
e8e7f271 | 2932 | |
0ce147d4 | 2933 | ufshcd_set_queue_depth(sdev); |
4264fd61 | 2934 | |
57d104c1 SJ |
2935 | ufshcd_get_lu_power_on_wp_status(hba, sdev); |
2936 | ||
7a3e97b0 SY |
2937 | return 0; |
2938 | } | |
2939 | ||
4264fd61 SRT |
2940 | /** |
2941 | * ufshcd_change_queue_depth - change queue depth | |
2942 | * @sdev: pointer to SCSI device | |
2943 | * @depth: required depth to set | |
4264fd61 | 2944 | * |
db5ed4df | 2945 | * Change queue depth and make sure the max. limits are not crossed. |
4264fd61 | 2946 | */ |
db5ed4df | 2947 | static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth) |
4264fd61 SRT |
2948 | { |
2949 | struct ufs_hba *hba = shost_priv(sdev->host); | |
2950 | ||
2951 | if (depth > hba->nutrs) | |
2952 | depth = hba->nutrs; | |
db5ed4df | 2953 | return scsi_change_queue_depth(sdev, depth); |
4264fd61 SRT |
2954 | } |
2955 | ||
eeda4749 AM |
2956 | /** |
2957 | * ufshcd_slave_configure - adjust SCSI device configurations | |
2958 | * @sdev: pointer to SCSI device | |
2959 | */ | |
2960 | static int ufshcd_slave_configure(struct scsi_device *sdev) | |
2961 | { | |
2962 | struct request_queue *q = sdev->request_queue; | |
2963 | ||
2964 | blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1); | |
2965 | blk_queue_max_segment_size(q, PRDT_DATA_BYTE_COUNT_MAX); | |
2966 | ||
2967 | return 0; | |
2968 | } | |
2969 | ||
7a3e97b0 SY |
2970 | /** |
2971 | * ufshcd_slave_destroy - remove SCSI device configurations | |
2972 | * @sdev: pointer to SCSI device | |
2973 | */ | |
2974 | static void ufshcd_slave_destroy(struct scsi_device *sdev) | |
2975 | { | |
2976 | struct ufs_hba *hba; | |
2977 | ||
2978 | hba = shost_priv(sdev->host); | |
0ce147d4 | 2979 | /* Drop the reference as it won't be needed anymore */ |
7c48bfd0 AM |
2980 | if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) { |
2981 | unsigned long flags; | |
2982 | ||
2983 | spin_lock_irqsave(hba->host->host_lock, flags); | |
0ce147d4 | 2984 | hba->sdev_ufs_device = NULL; |
7c48bfd0 AM |
2985 | spin_unlock_irqrestore(hba->host->host_lock, flags); |
2986 | } | |
7a3e97b0 SY |
2987 | } |
2988 | ||
2989 | /** | |
2990 | * ufshcd_task_req_compl - handle task management request completion | |
2991 | * @hba: per adapter instance | |
2992 | * @index: index of the completed request | |
e2933132 | 2993 | * @resp: task management service response |
7a3e97b0 | 2994 | * |
e2933132 | 2995 | * Returns non-zero value on error, zero on success |
7a3e97b0 | 2996 | */ |
e2933132 | 2997 | static int ufshcd_task_req_compl(struct ufs_hba *hba, u32 index, u8 *resp) |
7a3e97b0 SY |
2998 | { |
2999 | struct utp_task_req_desc *task_req_descp; | |
3000 | struct utp_upiu_task_rsp *task_rsp_upiup; | |
3001 | unsigned long flags; | |
3002 | int ocs_value; | |
3003 | int task_result; | |
3004 | ||
3005 | spin_lock_irqsave(hba->host->host_lock, flags); | |
3006 | ||
3007 | /* Clear completed tasks from outstanding_tasks */ | |
3008 | __clear_bit(index, &hba->outstanding_tasks); | |
3009 | ||
3010 | task_req_descp = hba->utmrdl_base_addr; | |
3011 | ocs_value = ufshcd_get_tmr_ocs(&task_req_descp[index]); | |
3012 | ||
3013 | if (ocs_value == OCS_SUCCESS) { | |
3014 | task_rsp_upiup = (struct utp_upiu_task_rsp *) | |
3015 | task_req_descp[index].task_rsp_upiu; | |
3016 | task_result = be32_to_cpu(task_rsp_upiup->header.dword_1); | |
3017 | task_result = ((task_result & MASK_TASK_RESPONSE) >> 8); | |
e2933132 SRT |
3018 | if (resp) |
3019 | *resp = (u8)task_result; | |
7a3e97b0 | 3020 | } else { |
e2933132 SRT |
3021 | dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", |
3022 | __func__, ocs_value); | |
7a3e97b0 SY |
3023 | } |
3024 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
e2933132 SRT |
3025 | |
3026 | return ocs_value; | |
7a3e97b0 SY |
3027 | } |
3028 | ||
7a3e97b0 SY |
3029 | /** |
3030 | * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status | |
3031 | * @lrb: pointer to local reference block of completed command | |
3032 | * @scsi_status: SCSI command status | |
3033 | * | |
3034 | * Returns value base on SCSI command status | |
3035 | */ | |
3036 | static inline int | |
3037 | ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status) | |
3038 | { | |
3039 | int result = 0; | |
3040 | ||
3041 | switch (scsi_status) { | |
7a3e97b0 | 3042 | case SAM_STAT_CHECK_CONDITION: |
1c2623c5 SJ |
3043 | ufshcd_copy_sense_data(lrbp); |
3044 | case SAM_STAT_GOOD: | |
7a3e97b0 SY |
3045 | result |= DID_OK << 16 | |
3046 | COMMAND_COMPLETE << 8 | | |
1c2623c5 | 3047 | scsi_status; |
7a3e97b0 SY |
3048 | break; |
3049 | case SAM_STAT_TASK_SET_FULL: | |
1c2623c5 | 3050 | case SAM_STAT_BUSY: |
7a3e97b0 | 3051 | case SAM_STAT_TASK_ABORTED: |
1c2623c5 SJ |
3052 | ufshcd_copy_sense_data(lrbp); |
3053 | result |= scsi_status; | |
7a3e97b0 SY |
3054 | break; |
3055 | default: | |
3056 | result |= DID_ERROR << 16; | |
3057 | break; | |
3058 | } /* end of switch */ | |
3059 | ||
3060 | return result; | |
3061 | } | |
3062 | ||
3063 | /** | |
3064 | * ufshcd_transfer_rsp_status - Get overall status of the response | |
3065 | * @hba: per adapter instance | |
3066 | * @lrb: pointer to local reference block of completed command | |
3067 | * | |
3068 | * Returns result of the command to notify SCSI midlayer | |
3069 | */ | |
3070 | static inline int | |
3071 | ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) | |
3072 | { | |
3073 | int result = 0; | |
3074 | int scsi_status; | |
3075 | int ocs; | |
3076 | ||
3077 | /* overall command status of utrd */ | |
3078 | ocs = ufshcd_get_tr_ocs(lrbp); | |
3079 | ||
3080 | switch (ocs) { | |
3081 | case OCS_SUCCESS: | |
5a0b0cb9 | 3082 | result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr); |
7a3e97b0 | 3083 | |
5a0b0cb9 SRT |
3084 | switch (result) { |
3085 | case UPIU_TRANSACTION_RESPONSE: | |
3086 | /* | |
3087 | * get the response UPIU result to extract | |
3088 | * the SCSI command status | |
3089 | */ | |
3090 | result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr); | |
3091 | ||
3092 | /* | |
3093 | * get the result based on SCSI status response | |
3094 | * to notify the SCSI midlayer of the command status | |
3095 | */ | |
3096 | scsi_status = result & MASK_SCSI_STATUS; | |
3097 | result = ufshcd_scsi_cmd_status(lrbp, scsi_status); | |
66ec6d59 SRT |
3098 | |
3099 | if (ufshcd_is_exception_event(lrbp->ucd_rsp_ptr)) | |
3100 | schedule_work(&hba->eeh_work); | |
5a0b0cb9 SRT |
3101 | break; |
3102 | case UPIU_TRANSACTION_REJECT_UPIU: | |
3103 | /* TODO: handle Reject UPIU Response */ | |
3104 | result = DID_ERROR << 16; | |
3b1d0580 | 3105 | dev_err(hba->dev, |
5a0b0cb9 SRT |
3106 | "Reject UPIU not fully implemented\n"); |
3107 | break; | |
3108 | default: | |
3109 | result = DID_ERROR << 16; | |
3110 | dev_err(hba->dev, | |
3111 | "Unexpected request response code = %x\n", | |
3112 | result); | |
7a3e97b0 SY |
3113 | break; |
3114 | } | |
7a3e97b0 SY |
3115 | break; |
3116 | case OCS_ABORTED: | |
3117 | result |= DID_ABORT << 16; | |
3118 | break; | |
e8e7f271 SRT |
3119 | case OCS_INVALID_COMMAND_STATUS: |
3120 | result |= DID_REQUEUE << 16; | |
3121 | break; | |
7a3e97b0 SY |
3122 | case OCS_INVALID_CMD_TABLE_ATTR: |
3123 | case OCS_INVALID_PRDT_ATTR: | |
3124 | case OCS_MISMATCH_DATA_BUF_SIZE: | |
3125 | case OCS_MISMATCH_RESP_UPIU_SIZE: | |
3126 | case OCS_PEER_COMM_FAILURE: | |
3127 | case OCS_FATAL_ERROR: | |
3128 | default: | |
3129 | result |= DID_ERROR << 16; | |
3b1d0580 | 3130 | dev_err(hba->dev, |
7a3e97b0 SY |
3131 | "OCS error from controller = %x\n", ocs); |
3132 | break; | |
3133 | } /* end of switch */ | |
3134 | ||
3135 | return result; | |
3136 | } | |
3137 | ||
6ccf44fe SJ |
3138 | /** |
3139 | * ufshcd_uic_cmd_compl - handle completion of uic command | |
3140 | * @hba: per adapter instance | |
53b3d9c3 | 3141 | * @intr_status: interrupt status generated by the controller |
6ccf44fe | 3142 | */ |
53b3d9c3 | 3143 | static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status) |
6ccf44fe | 3144 | { |
53b3d9c3 | 3145 | if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) { |
6ccf44fe SJ |
3146 | hba->active_uic_cmd->argument2 |= |
3147 | ufshcd_get_uic_cmd_result(hba); | |
12b4fdb4 SJ |
3148 | hba->active_uic_cmd->argument3 = |
3149 | ufshcd_get_dme_attr_val(hba); | |
6ccf44fe SJ |
3150 | complete(&hba->active_uic_cmd->done); |
3151 | } | |
53b3d9c3 | 3152 | |
57d104c1 SJ |
3153 | if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) |
3154 | complete(hba->uic_async_done); | |
6ccf44fe SJ |
3155 | } |
3156 | ||
7a3e97b0 SY |
3157 | /** |
3158 | * ufshcd_transfer_req_compl - handle SCSI and query command completion | |
3159 | * @hba: per adapter instance | |
3160 | */ | |
3161 | static void ufshcd_transfer_req_compl(struct ufs_hba *hba) | |
3162 | { | |
5a0b0cb9 SRT |
3163 | struct ufshcd_lrb *lrbp; |
3164 | struct scsi_cmnd *cmd; | |
7a3e97b0 SY |
3165 | unsigned long completed_reqs; |
3166 | u32 tr_doorbell; | |
3167 | int result; | |
3168 | int index; | |
e9d501b1 DR |
3169 | |
3170 | /* Resetting interrupt aggregation counters first and reading the | |
3171 | * DOOR_BELL afterward allows us to handle all the completed requests. | |
3172 | * In order to prevent other interrupts starvation the DB is read once | |
3173 | * after reset. The down side of this solution is the possibility of | |
3174 | * false interrupt if device completes another request after resetting | |
3175 | * aggregation and before reading the DB. | |
3176 | */ | |
b852190e YG |
3177 | if (ufshcd_is_intr_aggr_allowed(hba)) |
3178 | ufshcd_reset_intr_aggr(hba); | |
7a3e97b0 | 3179 | |
b873a275 | 3180 | tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); |
7a3e97b0 SY |
3181 | completed_reqs = tr_doorbell ^ hba->outstanding_reqs; |
3182 | ||
e9d501b1 DR |
3183 | for_each_set_bit(index, &completed_reqs, hba->nutrs) { |
3184 | lrbp = &hba->lrb[index]; | |
3185 | cmd = lrbp->cmd; | |
3186 | if (cmd) { | |
3187 | result = ufshcd_transfer_rsp_status(hba, lrbp); | |
3188 | scsi_dma_unmap(cmd); | |
3189 | cmd->result = result; | |
3190 | /* Mark completed command as NULL in LRB */ | |
3191 | lrbp->cmd = NULL; | |
3192 | clear_bit_unlock(index, &hba->lrb_in_use); | |
3193 | /* Do not touch lrbp after scsi done */ | |
3194 | cmd->scsi_done(cmd); | |
1ab27c9c | 3195 | __ufshcd_release(hba); |
e9d501b1 DR |
3196 | } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE) { |
3197 | if (hba->dev_cmd.complete) | |
3198 | complete(hba->dev_cmd.complete); | |
3199 | } | |
3200 | } | |
7a3e97b0 SY |
3201 | |
3202 | /* clear corresponding bits of completed commands */ | |
3203 | hba->outstanding_reqs ^= completed_reqs; | |
3204 | ||
856b3483 ST |
3205 | ufshcd_clk_scaling_update_busy(hba); |
3206 | ||
5a0b0cb9 SRT |
3207 | /* we might have free'd some tags above */ |
3208 | wake_up(&hba->dev_cmd.tag_wq); | |
7a3e97b0 SY |
3209 | } |
3210 | ||
66ec6d59 SRT |
3211 | /** |
3212 | * ufshcd_disable_ee - disable exception event | |
3213 | * @hba: per-adapter instance | |
3214 | * @mask: exception event to disable | |
3215 | * | |
3216 | * Disables exception event in the device so that the EVENT_ALERT | |
3217 | * bit is not set. | |
3218 | * | |
3219 | * Returns zero on success, non-zero error value on failure. | |
3220 | */ | |
3221 | static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask) | |
3222 | { | |
3223 | int err = 0; | |
3224 | u32 val; | |
3225 | ||
3226 | if (!(hba->ee_ctrl_mask & mask)) | |
3227 | goto out; | |
3228 | ||
3229 | val = hba->ee_ctrl_mask & ~mask; | |
3230 | val &= 0xFFFF; /* 2 bytes */ | |
3231 | err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, | |
3232 | QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val); | |
3233 | if (!err) | |
3234 | hba->ee_ctrl_mask &= ~mask; | |
3235 | out: | |
3236 | return err; | |
3237 | } | |
3238 | ||
3239 | /** | |
3240 | * ufshcd_enable_ee - enable exception event | |
3241 | * @hba: per-adapter instance | |
3242 | * @mask: exception event to enable | |
3243 | * | |
3244 | * Enable corresponding exception event in the device to allow | |
3245 | * device to alert host in critical scenarios. | |
3246 | * | |
3247 | * Returns zero on success, non-zero error value on failure. | |
3248 | */ | |
3249 | static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask) | |
3250 | { | |
3251 | int err = 0; | |
3252 | u32 val; | |
3253 | ||
3254 | if (hba->ee_ctrl_mask & mask) | |
3255 | goto out; | |
3256 | ||
3257 | val = hba->ee_ctrl_mask | mask; | |
3258 | val &= 0xFFFF; /* 2 bytes */ | |
3259 | err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, | |
3260 | QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val); | |
3261 | if (!err) | |
3262 | hba->ee_ctrl_mask |= mask; | |
3263 | out: | |
3264 | return err; | |
3265 | } | |
3266 | ||
3267 | /** | |
3268 | * ufshcd_enable_auto_bkops - Allow device managed BKOPS | |
3269 | * @hba: per-adapter instance | |
3270 | * | |
3271 | * Allow device to manage background operations on its own. Enabling | |
3272 | * this might lead to inconsistent latencies during normal data transfers | |
3273 | * as the device is allowed to manage its own way of handling background | |
3274 | * operations. | |
3275 | * | |
3276 | * Returns zero on success, non-zero on failure. | |
3277 | */ | |
3278 | static int ufshcd_enable_auto_bkops(struct ufs_hba *hba) | |
3279 | { | |
3280 | int err = 0; | |
3281 | ||
3282 | if (hba->auto_bkops_enabled) | |
3283 | goto out; | |
3284 | ||
3285 | err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_SET_FLAG, | |
3286 | QUERY_FLAG_IDN_BKOPS_EN, NULL); | |
3287 | if (err) { | |
3288 | dev_err(hba->dev, "%s: failed to enable bkops %d\n", | |
3289 | __func__, err); | |
3290 | goto out; | |
3291 | } | |
3292 | ||
3293 | hba->auto_bkops_enabled = true; | |
3294 | ||
3295 | /* No need of URGENT_BKOPS exception from the device */ | |
3296 | err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS); | |
3297 | if (err) | |
3298 | dev_err(hba->dev, "%s: failed to disable exception event %d\n", | |
3299 | __func__, err); | |
3300 | out: | |
3301 | return err; | |
3302 | } | |
3303 | ||
3304 | /** | |
3305 | * ufshcd_disable_auto_bkops - block device in doing background operations | |
3306 | * @hba: per-adapter instance | |
3307 | * | |
3308 | * Disabling background operations improves command response latency but | |
3309 | * has drawback of device moving into critical state where the device is | |
3310 | * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the | |
3311 | * host is idle so that BKOPS are managed effectively without any negative | |
3312 | * impacts. | |
3313 | * | |
3314 | * Returns zero on success, non-zero on failure. | |
3315 | */ | |
3316 | static int ufshcd_disable_auto_bkops(struct ufs_hba *hba) | |
3317 | { | |
3318 | int err = 0; | |
3319 | ||
3320 | if (!hba->auto_bkops_enabled) | |
3321 | goto out; | |
3322 | ||
3323 | /* | |
3324 | * If host assisted BKOPs is to be enabled, make sure | |
3325 | * urgent bkops exception is allowed. | |
3326 | */ | |
3327 | err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS); | |
3328 | if (err) { | |
3329 | dev_err(hba->dev, "%s: failed to enable exception event %d\n", | |
3330 | __func__, err); | |
3331 | goto out; | |
3332 | } | |
3333 | ||
3334 | err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG, | |
3335 | QUERY_FLAG_IDN_BKOPS_EN, NULL); | |
3336 | if (err) { | |
3337 | dev_err(hba->dev, "%s: failed to disable bkops %d\n", | |
3338 | __func__, err); | |
3339 | ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS); | |
3340 | goto out; | |
3341 | } | |
3342 | ||
3343 | hba->auto_bkops_enabled = false; | |
3344 | out: | |
3345 | return err; | |
3346 | } | |
3347 | ||
3348 | /** | |
3349 | * ufshcd_force_reset_auto_bkops - force enable of auto bkops | |
3350 | * @hba: per adapter instance | |
3351 | * | |
3352 | * After a device reset the device may toggle the BKOPS_EN flag | |
3353 | * to default value. The s/w tracking variables should be updated | |
3354 | * as well. Do this by forcing enable of auto bkops. | |
3355 | */ | |
3356 | static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba) | |
3357 | { | |
3358 | hba->auto_bkops_enabled = false; | |
3359 | hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS; | |
3360 | ufshcd_enable_auto_bkops(hba); | |
3361 | } | |
3362 | ||
3363 | static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status) | |
3364 | { | |
3365 | return ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR, | |
3366 | QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status); | |
3367 | } | |
3368 | ||
3369 | /** | |
57d104c1 | 3370 | * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status |
66ec6d59 | 3371 | * @hba: per-adapter instance |
57d104c1 | 3372 | * @status: bkops_status value |
66ec6d59 | 3373 | * |
57d104c1 SJ |
3374 | * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn |
3375 | * flag in the device to permit background operations if the device | |
3376 | * bkops_status is greater than or equal to "status" argument passed to | |
3377 | * this function, disable otherwise. | |
3378 | * | |
3379 | * Returns 0 for success, non-zero in case of failure. | |
3380 | * | |
3381 | * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag | |
3382 | * to know whether auto bkops is enabled or disabled after this function | |
3383 | * returns control to it. | |
66ec6d59 | 3384 | */ |
57d104c1 SJ |
3385 | static int ufshcd_bkops_ctrl(struct ufs_hba *hba, |
3386 | enum bkops_status status) | |
66ec6d59 SRT |
3387 | { |
3388 | int err; | |
57d104c1 | 3389 | u32 curr_status = 0; |
66ec6d59 | 3390 | |
57d104c1 | 3391 | err = ufshcd_get_bkops_status(hba, &curr_status); |
66ec6d59 SRT |
3392 | if (err) { |
3393 | dev_err(hba->dev, "%s: failed to get BKOPS status %d\n", | |
3394 | __func__, err); | |
3395 | goto out; | |
57d104c1 SJ |
3396 | } else if (curr_status > BKOPS_STATUS_MAX) { |
3397 | dev_err(hba->dev, "%s: invalid BKOPS status %d\n", | |
3398 | __func__, curr_status); | |
3399 | err = -EINVAL; | |
3400 | goto out; | |
66ec6d59 SRT |
3401 | } |
3402 | ||
57d104c1 | 3403 | if (curr_status >= status) |
66ec6d59 | 3404 | err = ufshcd_enable_auto_bkops(hba); |
57d104c1 SJ |
3405 | else |
3406 | err = ufshcd_disable_auto_bkops(hba); | |
66ec6d59 SRT |
3407 | out: |
3408 | return err; | |
3409 | } | |
3410 | ||
57d104c1 SJ |
3411 | /** |
3412 | * ufshcd_urgent_bkops - handle urgent bkops exception event | |
3413 | * @hba: per-adapter instance | |
3414 | * | |
3415 | * Enable fBackgroundOpsEn flag in the device to permit background | |
3416 | * operations. | |
3417 | * | |
3418 | * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled | |
3419 | * and negative error value for any other failure. | |
3420 | */ | |
3421 | static int ufshcd_urgent_bkops(struct ufs_hba *hba) | |
3422 | { | |
3423 | return ufshcd_bkops_ctrl(hba, BKOPS_STATUS_PERF_IMPACT); | |
3424 | } | |
3425 | ||
66ec6d59 SRT |
3426 | static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status) |
3427 | { | |
3428 | return ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR, | |
3429 | QUERY_ATTR_IDN_EE_STATUS, 0, 0, status); | |
3430 | } | |
3431 | ||
3432 | /** | |
3433 | * ufshcd_exception_event_handler - handle exceptions raised by device | |
3434 | * @work: pointer to work data | |
3435 | * | |
3436 | * Read bExceptionEventStatus attribute from the device and handle the | |
3437 | * exception event accordingly. | |
3438 | */ | |
3439 | static void ufshcd_exception_event_handler(struct work_struct *work) | |
3440 | { | |
3441 | struct ufs_hba *hba; | |
3442 | int err; | |
3443 | u32 status = 0; | |
3444 | hba = container_of(work, struct ufs_hba, eeh_work); | |
3445 | ||
62694735 | 3446 | pm_runtime_get_sync(hba->dev); |
66ec6d59 SRT |
3447 | err = ufshcd_get_ee_status(hba, &status); |
3448 | if (err) { | |
3449 | dev_err(hba->dev, "%s: failed to get exception status %d\n", | |
3450 | __func__, err); | |
3451 | goto out; | |
3452 | } | |
3453 | ||
3454 | status &= hba->ee_ctrl_mask; | |
3455 | if (status & MASK_EE_URGENT_BKOPS) { | |
3456 | err = ufshcd_urgent_bkops(hba); | |
57d104c1 | 3457 | if (err < 0) |
66ec6d59 SRT |
3458 | dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n", |
3459 | __func__, err); | |
3460 | } | |
3461 | out: | |
62694735 | 3462 | pm_runtime_put_sync(hba->dev); |
66ec6d59 SRT |
3463 | return; |
3464 | } | |
3465 | ||
7a3e97b0 | 3466 | /** |
e8e7f271 SRT |
3467 | * ufshcd_err_handler - handle UFS errors that require s/w attention |
3468 | * @work: pointer to work structure | |
7a3e97b0 | 3469 | */ |
e8e7f271 | 3470 | static void ufshcd_err_handler(struct work_struct *work) |
7a3e97b0 SY |
3471 | { |
3472 | struct ufs_hba *hba; | |
e8e7f271 SRT |
3473 | unsigned long flags; |
3474 | u32 err_xfer = 0; | |
3475 | u32 err_tm = 0; | |
3476 | int err = 0; | |
3477 | int tag; | |
3478 | ||
3479 | hba = container_of(work, struct ufs_hba, eh_work); | |
7a3e97b0 | 3480 | |
62694735 | 3481 | pm_runtime_get_sync(hba->dev); |
1ab27c9c | 3482 | ufshcd_hold(hba, false); |
e8e7f271 SRT |
3483 | |
3484 | spin_lock_irqsave(hba->host->host_lock, flags); | |
3485 | if (hba->ufshcd_state == UFSHCD_STATE_RESET) { | |
3486 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
3487 | goto out; | |
3488 | } | |
3489 | ||
3490 | hba->ufshcd_state = UFSHCD_STATE_RESET; | |
3491 | ufshcd_set_eh_in_progress(hba); | |
3492 | ||
3493 | /* Complete requests that have door-bell cleared by h/w */ | |
3494 | ufshcd_transfer_req_compl(hba); | |
3495 | ufshcd_tmc_handler(hba); | |
3496 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
3497 | ||
3498 | /* Clear pending transfer requests */ | |
3499 | for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) | |
3500 | if (ufshcd_clear_cmd(hba, tag)) | |
3501 | err_xfer |= 1 << tag; | |
3502 | ||
3503 | /* Clear pending task management requests */ | |
3504 | for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) | |
3505 | if (ufshcd_clear_tm_cmd(hba, tag)) | |
3506 | err_tm |= 1 << tag; | |
3507 | ||
3508 | /* Complete the requests that are cleared by s/w */ | |
3509 | spin_lock_irqsave(hba->host->host_lock, flags); | |
3510 | ufshcd_transfer_req_compl(hba); | |
3511 | ufshcd_tmc_handler(hba); | |
3512 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
3513 | ||
3514 | /* Fatal errors need reset */ | |
3515 | if (err_xfer || err_tm || (hba->saved_err & INT_FATAL_ERRORS) || | |
3516 | ((hba->saved_err & UIC_ERROR) && | |
3517 | (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR))) { | |
3518 | err = ufshcd_reset_and_restore(hba); | |
3519 | if (err) { | |
3520 | dev_err(hba->dev, "%s: reset and restore failed\n", | |
3521 | __func__); | |
3522 | hba->ufshcd_state = UFSHCD_STATE_ERROR; | |
3523 | } | |
3524 | /* | |
3525 | * Inform scsi mid-layer that we did reset and allow to handle | |
3526 | * Unit Attention properly. | |
3527 | */ | |
3528 | scsi_report_bus_reset(hba->host, 0); | |
3529 | hba->saved_err = 0; | |
3530 | hba->saved_uic_err = 0; | |
3531 | } | |
3532 | ufshcd_clear_eh_in_progress(hba); | |
3533 | ||
3534 | out: | |
3535 | scsi_unblock_requests(hba->host); | |
1ab27c9c | 3536 | ufshcd_release(hba); |
62694735 | 3537 | pm_runtime_put_sync(hba->dev); |
7a3e97b0 SY |
3538 | } |
3539 | ||
3540 | /** | |
e8e7f271 SRT |
3541 | * ufshcd_update_uic_error - check and set fatal UIC error flags. |
3542 | * @hba: per-adapter instance | |
7a3e97b0 | 3543 | */ |
e8e7f271 | 3544 | static void ufshcd_update_uic_error(struct ufs_hba *hba) |
7a3e97b0 SY |
3545 | { |
3546 | u32 reg; | |
3547 | ||
e8e7f271 SRT |
3548 | /* PA_INIT_ERROR is fatal and needs UIC reset */ |
3549 | reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER); | |
3550 | if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT) | |
3551 | hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR; | |
3552 | ||
3553 | /* UIC NL/TL/DME errors needs software retry */ | |
3554 | reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER); | |
3555 | if (reg) | |
3556 | hba->uic_error |= UFSHCD_UIC_NL_ERROR; | |
3557 | ||
3558 | reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER); | |
3559 | if (reg) | |
3560 | hba->uic_error |= UFSHCD_UIC_TL_ERROR; | |
3561 | ||
3562 | reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME); | |
3563 | if (reg) | |
3564 | hba->uic_error |= UFSHCD_UIC_DME_ERROR; | |
3565 | ||
3566 | dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n", | |
3567 | __func__, hba->uic_error); | |
3568 | } | |
3569 | ||
3570 | /** | |
3571 | * ufshcd_check_errors - Check for errors that need s/w attention | |
3572 | * @hba: per-adapter instance | |
3573 | */ | |
3574 | static void ufshcd_check_errors(struct ufs_hba *hba) | |
3575 | { | |
3576 | bool queue_eh_work = false; | |
3577 | ||
7a3e97b0 | 3578 | if (hba->errors & INT_FATAL_ERRORS) |
e8e7f271 | 3579 | queue_eh_work = true; |
7a3e97b0 SY |
3580 | |
3581 | if (hba->errors & UIC_ERROR) { | |
e8e7f271 SRT |
3582 | hba->uic_error = 0; |
3583 | ufshcd_update_uic_error(hba); | |
3584 | if (hba->uic_error) | |
3585 | queue_eh_work = true; | |
7a3e97b0 | 3586 | } |
e8e7f271 SRT |
3587 | |
3588 | if (queue_eh_work) { | |
3589 | /* handle fatal errors only when link is functional */ | |
3590 | if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) { | |
3591 | /* block commands from scsi mid-layer */ | |
3592 | scsi_block_requests(hba->host); | |
3593 | ||
3594 | /* transfer error masks to sticky bits */ | |
3595 | hba->saved_err |= hba->errors; | |
3596 | hba->saved_uic_err |= hba->uic_error; | |
3597 | ||
3598 | hba->ufshcd_state = UFSHCD_STATE_ERROR; | |
3599 | schedule_work(&hba->eh_work); | |
3600 | } | |
3441da7d | 3601 | } |
e8e7f271 SRT |
3602 | /* |
3603 | * if (!queue_eh_work) - | |
3604 | * Other errors are either non-fatal where host recovers | |
3605 | * itself without s/w intervention or errors that will be | |
3606 | * handled by the SCSI core layer. | |
3607 | */ | |
7a3e97b0 SY |
3608 | } |
3609 | ||
3610 | /** | |
3611 | * ufshcd_tmc_handler - handle task management function completion | |
3612 | * @hba: per adapter instance | |
3613 | */ | |
3614 | static void ufshcd_tmc_handler(struct ufs_hba *hba) | |
3615 | { | |
3616 | u32 tm_doorbell; | |
3617 | ||
b873a275 | 3618 | tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL); |
7a3e97b0 | 3619 | hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks; |
e2933132 | 3620 | wake_up(&hba->tm_wq); |
7a3e97b0 SY |
3621 | } |
3622 | ||
3623 | /** | |
3624 | * ufshcd_sl_intr - Interrupt service routine | |
3625 | * @hba: per adapter instance | |
3626 | * @intr_status: contains interrupts generated by the controller | |
3627 | */ | |
3628 | static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status) | |
3629 | { | |
3630 | hba->errors = UFSHCD_ERROR_MASK & intr_status; | |
3631 | if (hba->errors) | |
e8e7f271 | 3632 | ufshcd_check_errors(hba); |
7a3e97b0 | 3633 | |
53b3d9c3 SJ |
3634 | if (intr_status & UFSHCD_UIC_MASK) |
3635 | ufshcd_uic_cmd_compl(hba, intr_status); | |
7a3e97b0 SY |
3636 | |
3637 | if (intr_status & UTP_TASK_REQ_COMPL) | |
3638 | ufshcd_tmc_handler(hba); | |
3639 | ||
3640 | if (intr_status & UTP_TRANSFER_REQ_COMPL) | |
3641 | ufshcd_transfer_req_compl(hba); | |
3642 | } | |
3643 | ||
3644 | /** | |
3645 | * ufshcd_intr - Main interrupt service routine | |
3646 | * @irq: irq number | |
3647 | * @__hba: pointer to adapter instance | |
3648 | * | |
3649 | * Returns IRQ_HANDLED - If interrupt is valid | |
3650 | * IRQ_NONE - If invalid interrupt | |
3651 | */ | |
3652 | static irqreturn_t ufshcd_intr(int irq, void *__hba) | |
3653 | { | |
3654 | u32 intr_status; | |
3655 | irqreturn_t retval = IRQ_NONE; | |
3656 | struct ufs_hba *hba = __hba; | |
3657 | ||
3658 | spin_lock(hba->host->host_lock); | |
b873a275 | 3659 | intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); |
7a3e97b0 SY |
3660 | |
3661 | if (intr_status) { | |
261ea452 | 3662 | ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS); |
7a3e97b0 | 3663 | ufshcd_sl_intr(hba, intr_status); |
7a3e97b0 SY |
3664 | retval = IRQ_HANDLED; |
3665 | } | |
3666 | spin_unlock(hba->host->host_lock); | |
3667 | return retval; | |
3668 | } | |
3669 | ||
e2933132 SRT |
3670 | static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag) |
3671 | { | |
3672 | int err = 0; | |
3673 | u32 mask = 1 << tag; | |
3674 | unsigned long flags; | |
3675 | ||
3676 | if (!test_bit(tag, &hba->outstanding_tasks)) | |
3677 | goto out; | |
3678 | ||
3679 | spin_lock_irqsave(hba->host->host_lock, flags); | |
3680 | ufshcd_writel(hba, ~(1 << tag), REG_UTP_TASK_REQ_LIST_CLEAR); | |
3681 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
3682 | ||
3683 | /* poll for max. 1 sec to clear door bell register by h/w */ | |
3684 | err = ufshcd_wait_for_register(hba, | |
3685 | REG_UTP_TASK_REQ_DOOR_BELL, | |
3686 | mask, 0, 1000, 1000); | |
3687 | out: | |
3688 | return err; | |
3689 | } | |
3690 | ||
7a3e97b0 SY |
3691 | /** |
3692 | * ufshcd_issue_tm_cmd - issues task management commands to controller | |
3693 | * @hba: per adapter instance | |
e2933132 SRT |
3694 | * @lun_id: LUN ID to which TM command is sent |
3695 | * @task_id: task ID to which the TM command is applicable | |
3696 | * @tm_function: task management function opcode | |
3697 | * @tm_response: task management service response return value | |
7a3e97b0 | 3698 | * |
e2933132 | 3699 | * Returns non-zero value on error, zero on success. |
7a3e97b0 | 3700 | */ |
e2933132 SRT |
3701 | static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id, |
3702 | u8 tm_function, u8 *tm_response) | |
7a3e97b0 SY |
3703 | { |
3704 | struct utp_task_req_desc *task_req_descp; | |
3705 | struct utp_upiu_task_req *task_req_upiup; | |
3706 | struct Scsi_Host *host; | |
3707 | unsigned long flags; | |
e2933132 | 3708 | int free_slot; |
7a3e97b0 | 3709 | int err; |
e2933132 | 3710 | int task_tag; |
7a3e97b0 SY |
3711 | |
3712 | host = hba->host; | |
3713 | ||
e2933132 SRT |
3714 | /* |
3715 | * Get free slot, sleep if slots are unavailable. | |
3716 | * Even though we use wait_event() which sleeps indefinitely, | |
3717 | * the maximum wait time is bounded by %TM_CMD_TIMEOUT. | |
3718 | */ | |
3719 | wait_event(hba->tm_tag_wq, ufshcd_get_tm_free_slot(hba, &free_slot)); | |
1ab27c9c | 3720 | ufshcd_hold(hba, false); |
7a3e97b0 | 3721 | |
e2933132 | 3722 | spin_lock_irqsave(host->host_lock, flags); |
7a3e97b0 SY |
3723 | task_req_descp = hba->utmrdl_base_addr; |
3724 | task_req_descp += free_slot; | |
3725 | ||
3726 | /* Configure task request descriptor */ | |
3727 | task_req_descp->header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD); | |
3728 | task_req_descp->header.dword_2 = | |
3729 | cpu_to_le32(OCS_INVALID_COMMAND_STATUS); | |
3730 | ||
3731 | /* Configure task request UPIU */ | |
3732 | task_req_upiup = | |
3733 | (struct utp_upiu_task_req *) task_req_descp->task_req_upiu; | |
e2933132 | 3734 | task_tag = hba->nutrs + free_slot; |
7a3e97b0 | 3735 | task_req_upiup->header.dword_0 = |
5a0b0cb9 | 3736 | UPIU_HEADER_DWORD(UPIU_TRANSACTION_TASK_REQ, 0, |
e2933132 | 3737 | lun_id, task_tag); |
7a3e97b0 | 3738 | task_req_upiup->header.dword_1 = |
5a0b0cb9 | 3739 | UPIU_HEADER_DWORD(0, tm_function, 0, 0); |
0ce147d4 SJ |
3740 | /* |
3741 | * The host shall provide the same value for LUN field in the basic | |
3742 | * header and for Input Parameter. | |
3743 | */ | |
e2933132 SRT |
3744 | task_req_upiup->input_param1 = cpu_to_be32(lun_id); |
3745 | task_req_upiup->input_param2 = cpu_to_be32(task_id); | |
7a3e97b0 SY |
3746 | |
3747 | /* send command to the controller */ | |
3748 | __set_bit(free_slot, &hba->outstanding_tasks); | |
b873a275 | 3749 | ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL); |
7a3e97b0 SY |
3750 | |
3751 | spin_unlock_irqrestore(host->host_lock, flags); | |
3752 | ||
3753 | /* wait until the task management command is completed */ | |
e2933132 SRT |
3754 | err = wait_event_timeout(hba->tm_wq, |
3755 | test_bit(free_slot, &hba->tm_condition), | |
3756 | msecs_to_jiffies(TM_CMD_TIMEOUT)); | |
7a3e97b0 | 3757 | if (!err) { |
e2933132 SRT |
3758 | dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n", |
3759 | __func__, tm_function); | |
3760 | if (ufshcd_clear_tm_cmd(hba, free_slot)) | |
3761 | dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n", | |
3762 | __func__, free_slot); | |
3763 | err = -ETIMEDOUT; | |
3764 | } else { | |
3765 | err = ufshcd_task_req_compl(hba, free_slot, tm_response); | |
7a3e97b0 | 3766 | } |
e2933132 | 3767 | |
7a3e97b0 | 3768 | clear_bit(free_slot, &hba->tm_condition); |
e2933132 SRT |
3769 | ufshcd_put_tm_slot(hba, free_slot); |
3770 | wake_up(&hba->tm_tag_wq); | |
3771 | ||
1ab27c9c | 3772 | ufshcd_release(hba); |
7a3e97b0 SY |
3773 | return err; |
3774 | } | |
3775 | ||
3776 | /** | |
3441da7d SRT |
3777 | * ufshcd_eh_device_reset_handler - device reset handler registered to |
3778 | * scsi layer. | |
7a3e97b0 SY |
3779 | * @cmd: SCSI command pointer |
3780 | * | |
3781 | * Returns SUCCESS/FAILED | |
3782 | */ | |
3441da7d | 3783 | static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd) |
7a3e97b0 SY |
3784 | { |
3785 | struct Scsi_Host *host; | |
3786 | struct ufs_hba *hba; | |
3787 | unsigned int tag; | |
3788 | u32 pos; | |
3789 | int err; | |
e2933132 SRT |
3790 | u8 resp = 0xF; |
3791 | struct ufshcd_lrb *lrbp; | |
3441da7d | 3792 | unsigned long flags; |
7a3e97b0 SY |
3793 | |
3794 | host = cmd->device->host; | |
3795 | hba = shost_priv(host); | |
3796 | tag = cmd->request->tag; | |
3797 | ||
e2933132 SRT |
3798 | lrbp = &hba->lrb[tag]; |
3799 | err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp); | |
3800 | if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) { | |
3441da7d SRT |
3801 | if (!err) |
3802 | err = resp; | |
7a3e97b0 | 3803 | goto out; |
e2933132 | 3804 | } |
7a3e97b0 | 3805 | |
3441da7d SRT |
3806 | /* clear the commands that were pending for corresponding LUN */ |
3807 | for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) { | |
3808 | if (hba->lrb[pos].lun == lrbp->lun) { | |
3809 | err = ufshcd_clear_cmd(hba, pos); | |
3810 | if (err) | |
3811 | break; | |
7a3e97b0 | 3812 | } |
3441da7d SRT |
3813 | } |
3814 | spin_lock_irqsave(host->host_lock, flags); | |
3815 | ufshcd_transfer_req_compl(hba); | |
3816 | spin_unlock_irqrestore(host->host_lock, flags); | |
7a3e97b0 | 3817 | out: |
3441da7d SRT |
3818 | if (!err) { |
3819 | err = SUCCESS; | |
3820 | } else { | |
3821 | dev_err(hba->dev, "%s: failed with err %d\n", __func__, err); | |
3822 | err = FAILED; | |
3823 | } | |
7a3e97b0 SY |
3824 | return err; |
3825 | } | |
3826 | ||
7a3e97b0 SY |
3827 | /** |
3828 | * ufshcd_abort - abort a specific command | |
3829 | * @cmd: SCSI command pointer | |
3830 | * | |
f20810d8 SRT |
3831 | * Abort the pending command in device by sending UFS_ABORT_TASK task management |
3832 | * command, and in host controller by clearing the door-bell register. There can | |
3833 | * be race between controller sending the command to the device while abort is | |
3834 | * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is | |
3835 | * really issued and then try to abort it. | |
3836 | * | |
7a3e97b0 SY |
3837 | * Returns SUCCESS/FAILED |
3838 | */ | |
3839 | static int ufshcd_abort(struct scsi_cmnd *cmd) | |
3840 | { | |
3841 | struct Scsi_Host *host; | |
3842 | struct ufs_hba *hba; | |
3843 | unsigned long flags; | |
3844 | unsigned int tag; | |
f20810d8 SRT |
3845 | int err = 0; |
3846 | int poll_cnt; | |
e2933132 SRT |
3847 | u8 resp = 0xF; |
3848 | struct ufshcd_lrb *lrbp; | |
e9d501b1 | 3849 | u32 reg; |
7a3e97b0 SY |
3850 | |
3851 | host = cmd->device->host; | |
3852 | hba = shost_priv(host); | |
3853 | tag = cmd->request->tag; | |
3854 | ||
1ab27c9c | 3855 | ufshcd_hold(hba, false); |
f20810d8 SRT |
3856 | /* If command is already aborted/completed, return SUCCESS */ |
3857 | if (!(test_bit(tag, &hba->outstanding_reqs))) | |
3858 | goto out; | |
7a3e97b0 | 3859 | |
e9d501b1 DR |
3860 | reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); |
3861 | if (!(reg & (1 << tag))) { | |
3862 | dev_err(hba->dev, | |
3863 | "%s: cmd was completed, but without a notifying intr, tag = %d", | |
3864 | __func__, tag); | |
3865 | } | |
3866 | ||
f20810d8 SRT |
3867 | lrbp = &hba->lrb[tag]; |
3868 | for (poll_cnt = 100; poll_cnt; poll_cnt--) { | |
3869 | err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag, | |
3870 | UFS_QUERY_TASK, &resp); | |
3871 | if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) { | |
3872 | /* cmd pending in the device */ | |
3873 | break; | |
3874 | } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) { | |
f20810d8 SRT |
3875 | /* |
3876 | * cmd not pending in the device, check if it is | |
3877 | * in transition. | |
3878 | */ | |
3879 | reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); | |
3880 | if (reg & (1 << tag)) { | |
3881 | /* sleep for max. 200us to stabilize */ | |
3882 | usleep_range(100, 200); | |
3883 | continue; | |
3884 | } | |
3885 | /* command completed already */ | |
3886 | goto out; | |
3887 | } else { | |
3888 | if (!err) | |
3889 | err = resp; /* service response error */ | |
3890 | goto out; | |
3891 | } | |
3892 | } | |
3893 | ||
3894 | if (!poll_cnt) { | |
3895 | err = -EBUSY; | |
7a3e97b0 SY |
3896 | goto out; |
3897 | } | |
7a3e97b0 | 3898 | |
e2933132 SRT |
3899 | err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag, |
3900 | UFS_ABORT_TASK, &resp); | |
3901 | if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) { | |
f20810d8 SRT |
3902 | if (!err) |
3903 | err = resp; /* service response error */ | |
7a3e97b0 | 3904 | goto out; |
e2933132 | 3905 | } |
7a3e97b0 | 3906 | |
f20810d8 SRT |
3907 | err = ufshcd_clear_cmd(hba, tag); |
3908 | if (err) | |
3909 | goto out; | |
3910 | ||
7a3e97b0 SY |
3911 | scsi_dma_unmap(cmd); |
3912 | ||
3913 | spin_lock_irqsave(host->host_lock, flags); | |
7a3e97b0 SY |
3914 | __clear_bit(tag, &hba->outstanding_reqs); |
3915 | hba->lrb[tag].cmd = NULL; | |
3916 | spin_unlock_irqrestore(host->host_lock, flags); | |
5a0b0cb9 SRT |
3917 | |
3918 | clear_bit_unlock(tag, &hba->lrb_in_use); | |
3919 | wake_up(&hba->dev_cmd.tag_wq); | |
1ab27c9c | 3920 | |
7a3e97b0 | 3921 | out: |
f20810d8 SRT |
3922 | if (!err) { |
3923 | err = SUCCESS; | |
3924 | } else { | |
3925 | dev_err(hba->dev, "%s: failed with err %d\n", __func__, err); | |
3926 | err = FAILED; | |
3927 | } | |
3928 | ||
1ab27c9c ST |
3929 | /* |
3930 | * This ufshcd_release() corresponds to the original scsi cmd that got | |
3931 | * aborted here (as we won't get any IRQ for it). | |
3932 | */ | |
3933 | ufshcd_release(hba); | |
7a3e97b0 SY |
3934 | return err; |
3935 | } | |
3936 | ||
3441da7d SRT |
3937 | /** |
3938 | * ufshcd_host_reset_and_restore - reset and restore host controller | |
3939 | * @hba: per-adapter instance | |
3940 | * | |
3941 | * Note that host controller reset may issue DME_RESET to | |
3942 | * local and remote (device) Uni-Pro stack and the attributes | |
3943 | * are reset to default state. | |
3944 | * | |
3945 | * Returns zero on success, non-zero on failure | |
3946 | */ | |
3947 | static int ufshcd_host_reset_and_restore(struct ufs_hba *hba) | |
3948 | { | |
3949 | int err; | |
3441da7d SRT |
3950 | unsigned long flags; |
3951 | ||
3952 | /* Reset the host controller */ | |
3953 | spin_lock_irqsave(hba->host->host_lock, flags); | |
3954 | ufshcd_hba_stop(hba); | |
3955 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
3956 | ||
3957 | err = ufshcd_hba_enable(hba); | |
3958 | if (err) | |
3959 | goto out; | |
3960 | ||
3961 | /* Establish the link again and restore the device */ | |
1d337ec2 SRT |
3962 | err = ufshcd_probe_hba(hba); |
3963 | ||
3964 | if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL)) | |
3441da7d SRT |
3965 | err = -EIO; |
3966 | out: | |
3967 | if (err) | |
3968 | dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err); | |
3969 | ||
3970 | return err; | |
3971 | } | |
3972 | ||
3973 | /** | |
3974 | * ufshcd_reset_and_restore - reset and re-initialize host/device | |
3975 | * @hba: per-adapter instance | |
3976 | * | |
3977 | * Reset and recover device, host and re-establish link. This | |
3978 | * is helpful to recover the communication in fatal error conditions. | |
3979 | * | |
3980 | * Returns zero on success, non-zero on failure | |
3981 | */ | |
3982 | static int ufshcd_reset_and_restore(struct ufs_hba *hba) | |
3983 | { | |
3984 | int err = 0; | |
3985 | unsigned long flags; | |
1d337ec2 | 3986 | int retries = MAX_HOST_RESET_RETRIES; |
3441da7d | 3987 | |
1d337ec2 SRT |
3988 | do { |
3989 | err = ufshcd_host_reset_and_restore(hba); | |
3990 | } while (err && --retries); | |
3441da7d SRT |
3991 | |
3992 | /* | |
3993 | * After reset the door-bell might be cleared, complete | |
3994 | * outstanding requests in s/w here. | |
3995 | */ | |
3996 | spin_lock_irqsave(hba->host->host_lock, flags); | |
3997 | ufshcd_transfer_req_compl(hba); | |
3998 | ufshcd_tmc_handler(hba); | |
3999 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
4000 | ||
4001 | return err; | |
4002 | } | |
4003 | ||
4004 | /** | |
4005 | * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer | |
4006 | * @cmd - SCSI command pointer | |
4007 | * | |
4008 | * Returns SUCCESS/FAILED | |
4009 | */ | |
4010 | static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd) | |
4011 | { | |
4012 | int err; | |
4013 | unsigned long flags; | |
4014 | struct ufs_hba *hba; | |
4015 | ||
4016 | hba = shost_priv(cmd->device->host); | |
4017 | ||
1ab27c9c | 4018 | ufshcd_hold(hba, false); |
3441da7d SRT |
4019 | /* |
4020 | * Check if there is any race with fatal error handling. | |
4021 | * If so, wait for it to complete. Even though fatal error | |
4022 | * handling does reset and restore in some cases, don't assume | |
4023 | * anything out of it. We are just avoiding race here. | |
4024 | */ | |
4025 | do { | |
4026 | spin_lock_irqsave(hba->host->host_lock, flags); | |
e8e7f271 | 4027 | if (!(work_pending(&hba->eh_work) || |
3441da7d SRT |
4028 | hba->ufshcd_state == UFSHCD_STATE_RESET)) |
4029 | break; | |
4030 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
4031 | dev_dbg(hba->dev, "%s: reset in progress\n", __func__); | |
e8e7f271 | 4032 | flush_work(&hba->eh_work); |
3441da7d SRT |
4033 | } while (1); |
4034 | ||
4035 | hba->ufshcd_state = UFSHCD_STATE_RESET; | |
4036 | ufshcd_set_eh_in_progress(hba); | |
4037 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
4038 | ||
4039 | err = ufshcd_reset_and_restore(hba); | |
4040 | ||
4041 | spin_lock_irqsave(hba->host->host_lock, flags); | |
4042 | if (!err) { | |
4043 | err = SUCCESS; | |
4044 | hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; | |
4045 | } else { | |
4046 | err = FAILED; | |
4047 | hba->ufshcd_state = UFSHCD_STATE_ERROR; | |
4048 | } | |
4049 | ufshcd_clear_eh_in_progress(hba); | |
4050 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
4051 | ||
1ab27c9c | 4052 | ufshcd_release(hba); |
3441da7d SRT |
4053 | return err; |
4054 | } | |
4055 | ||
3a4bf06d YG |
4056 | /** |
4057 | * ufshcd_get_max_icc_level - calculate the ICC level | |
4058 | * @sup_curr_uA: max. current supported by the regulator | |
4059 | * @start_scan: row at the desc table to start scan from | |
4060 | * @buff: power descriptor buffer | |
4061 | * | |
4062 | * Returns calculated max ICC level for specific regulator | |
4063 | */ | |
4064 | static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff) | |
4065 | { | |
4066 | int i; | |
4067 | int curr_uA; | |
4068 | u16 data; | |
4069 | u16 unit; | |
4070 | ||
4071 | for (i = start_scan; i >= 0; i--) { | |
4072 | data = be16_to_cpu(*((u16 *)(buff + 2*i))); | |
4073 | unit = (data & ATTR_ICC_LVL_UNIT_MASK) >> | |
4074 | ATTR_ICC_LVL_UNIT_OFFSET; | |
4075 | curr_uA = data & ATTR_ICC_LVL_VALUE_MASK; | |
4076 | switch (unit) { | |
4077 | case UFSHCD_NANO_AMP: | |
4078 | curr_uA = curr_uA / 1000; | |
4079 | break; | |
4080 | case UFSHCD_MILI_AMP: | |
4081 | curr_uA = curr_uA * 1000; | |
4082 | break; | |
4083 | case UFSHCD_AMP: | |
4084 | curr_uA = curr_uA * 1000 * 1000; | |
4085 | break; | |
4086 | case UFSHCD_MICRO_AMP: | |
4087 | default: | |
4088 | break; | |
4089 | } | |
4090 | if (sup_curr_uA >= curr_uA) | |
4091 | break; | |
4092 | } | |
4093 | if (i < 0) { | |
4094 | i = 0; | |
4095 | pr_err("%s: Couldn't find valid icc_level = %d", __func__, i); | |
4096 | } | |
4097 | ||
4098 | return (u32)i; | |
4099 | } | |
4100 | ||
4101 | /** | |
4102 | * ufshcd_calc_icc_level - calculate the max ICC level | |
4103 | * In case regulators are not initialized we'll return 0 | |
4104 | * @hba: per-adapter instance | |
4105 | * @desc_buf: power descriptor buffer to extract ICC levels from. | |
4106 | * @len: length of desc_buff | |
4107 | * | |
4108 | * Returns calculated ICC level | |
4109 | */ | |
4110 | static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba, | |
4111 | u8 *desc_buf, int len) | |
4112 | { | |
4113 | u32 icc_level = 0; | |
4114 | ||
4115 | if (!hba->vreg_info.vcc || !hba->vreg_info.vccq || | |
4116 | !hba->vreg_info.vccq2) { | |
4117 | dev_err(hba->dev, | |
4118 | "%s: Regulator capability was not set, actvIccLevel=%d", | |
4119 | __func__, icc_level); | |
4120 | goto out; | |
4121 | } | |
4122 | ||
4123 | if (hba->vreg_info.vcc) | |
4124 | icc_level = ufshcd_get_max_icc_level( | |
4125 | hba->vreg_info.vcc->max_uA, | |
4126 | POWER_DESC_MAX_ACTV_ICC_LVLS - 1, | |
4127 | &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]); | |
4128 | ||
4129 | if (hba->vreg_info.vccq) | |
4130 | icc_level = ufshcd_get_max_icc_level( | |
4131 | hba->vreg_info.vccq->max_uA, | |
4132 | icc_level, | |
4133 | &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]); | |
4134 | ||
4135 | if (hba->vreg_info.vccq2) | |
4136 | icc_level = ufshcd_get_max_icc_level( | |
4137 | hba->vreg_info.vccq2->max_uA, | |
4138 | icc_level, | |
4139 | &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]); | |
4140 | out: | |
4141 | return icc_level; | |
4142 | } | |
4143 | ||
4144 | static void ufshcd_init_icc_levels(struct ufs_hba *hba) | |
4145 | { | |
4146 | int ret; | |
4147 | int buff_len = QUERY_DESC_POWER_MAX_SIZE; | |
4148 | u8 desc_buf[QUERY_DESC_POWER_MAX_SIZE]; | |
4149 | ||
4150 | ret = ufshcd_read_power_desc(hba, desc_buf, buff_len); | |
4151 | if (ret) { | |
4152 | dev_err(hba->dev, | |
4153 | "%s: Failed reading power descriptor.len = %d ret = %d", | |
4154 | __func__, buff_len, ret); | |
4155 | return; | |
4156 | } | |
4157 | ||
4158 | hba->init_prefetch_data.icc_level = | |
4159 | ufshcd_find_max_sup_active_icc_level(hba, | |
4160 | desc_buf, buff_len); | |
4161 | dev_dbg(hba->dev, "%s: setting icc_level 0x%x", | |
4162 | __func__, hba->init_prefetch_data.icc_level); | |
4163 | ||
4164 | ret = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, | |
4165 | QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, | |
4166 | &hba->init_prefetch_data.icc_level); | |
4167 | ||
4168 | if (ret) | |
4169 | dev_err(hba->dev, | |
4170 | "%s: Failed configuring bActiveICCLevel = %d ret = %d", | |
4171 | __func__, hba->init_prefetch_data.icc_level , ret); | |
4172 | ||
4173 | } | |
4174 | ||
2a8fa600 SJ |
4175 | /** |
4176 | * ufshcd_scsi_add_wlus - Adds required W-LUs | |
4177 | * @hba: per-adapter instance | |
4178 | * | |
4179 | * UFS device specification requires the UFS devices to support 4 well known | |
4180 | * logical units: | |
4181 | * "REPORT_LUNS" (address: 01h) | |
4182 | * "UFS Device" (address: 50h) | |
4183 | * "RPMB" (address: 44h) | |
4184 | * "BOOT" (address: 30h) | |
4185 | * UFS device's power management needs to be controlled by "POWER CONDITION" | |
4186 | * field of SSU (START STOP UNIT) command. But this "power condition" field | |
4187 | * will take effect only when its sent to "UFS device" well known logical unit | |
4188 | * hence we require the scsi_device instance to represent this logical unit in | |
4189 | * order for the UFS host driver to send the SSU command for power management. | |
4190 | ||
4191 | * We also require the scsi_device instance for "RPMB" (Replay Protected Memory | |
4192 | * Block) LU so user space process can control this LU. User space may also | |
4193 | * want to have access to BOOT LU. | |
4194 | ||
4195 | * This function adds scsi device instances for each of all well known LUs | |
4196 | * (except "REPORT LUNS" LU). | |
4197 | * | |
4198 | * Returns zero on success (all required W-LUs are added successfully), | |
4199 | * non-zero error value on failure (if failed to add any of the required W-LU). | |
4200 | */ | |
4201 | static int ufshcd_scsi_add_wlus(struct ufs_hba *hba) | |
4202 | { | |
4203 | int ret = 0; | |
7c48bfd0 AM |
4204 | struct scsi_device *sdev_rpmb; |
4205 | struct scsi_device *sdev_boot; | |
2a8fa600 SJ |
4206 | |
4207 | hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0, | |
4208 | ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL); | |
4209 | if (IS_ERR(hba->sdev_ufs_device)) { | |
4210 | ret = PTR_ERR(hba->sdev_ufs_device); | |
4211 | hba->sdev_ufs_device = NULL; | |
4212 | goto out; | |
4213 | } | |
7c48bfd0 | 4214 | scsi_device_put(hba->sdev_ufs_device); |
2a8fa600 | 4215 | |
7c48bfd0 | 4216 | sdev_boot = __scsi_add_device(hba->host, 0, 0, |
2a8fa600 | 4217 | ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL); |
7c48bfd0 AM |
4218 | if (IS_ERR(sdev_boot)) { |
4219 | ret = PTR_ERR(sdev_boot); | |
2a8fa600 SJ |
4220 | goto remove_sdev_ufs_device; |
4221 | } | |
7c48bfd0 | 4222 | scsi_device_put(sdev_boot); |
2a8fa600 | 4223 | |
7c48bfd0 | 4224 | sdev_rpmb = __scsi_add_device(hba->host, 0, 0, |
2a8fa600 | 4225 | ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL); |
7c48bfd0 AM |
4226 | if (IS_ERR(sdev_rpmb)) { |
4227 | ret = PTR_ERR(sdev_rpmb); | |
2a8fa600 SJ |
4228 | goto remove_sdev_boot; |
4229 | } | |
7c48bfd0 | 4230 | scsi_device_put(sdev_rpmb); |
2a8fa600 SJ |
4231 | goto out; |
4232 | ||
4233 | remove_sdev_boot: | |
7c48bfd0 | 4234 | scsi_remove_device(sdev_boot); |
2a8fa600 SJ |
4235 | remove_sdev_ufs_device: |
4236 | scsi_remove_device(hba->sdev_ufs_device); | |
4237 | out: | |
4238 | return ret; | |
4239 | } | |
4240 | ||
6ccf44fe | 4241 | /** |
1d337ec2 SRT |
4242 | * ufshcd_probe_hba - probe hba to detect device and initialize |
4243 | * @hba: per-adapter instance | |
4244 | * | |
4245 | * Execute link-startup and verify device initialization | |
6ccf44fe | 4246 | */ |
1d337ec2 | 4247 | static int ufshcd_probe_hba(struct ufs_hba *hba) |
6ccf44fe | 4248 | { |
6ccf44fe SJ |
4249 | int ret; |
4250 | ||
4251 | ret = ufshcd_link_startup(hba); | |
5a0b0cb9 SRT |
4252 | if (ret) |
4253 | goto out; | |
4254 | ||
5064636c YG |
4255 | ufshcd_init_pwr_info(hba); |
4256 | ||
57d104c1 SJ |
4257 | /* UniPro link is active now */ |
4258 | ufshcd_set_link_active(hba); | |
d3e89bac | 4259 | |
5a0b0cb9 SRT |
4260 | ret = ufshcd_verify_dev_init(hba); |
4261 | if (ret) | |
4262 | goto out; | |
68078d5c DR |
4263 | |
4264 | ret = ufshcd_complete_dev_init(hba); | |
4265 | if (ret) | |
4266 | goto out; | |
5a0b0cb9 | 4267 | |
57d104c1 SJ |
4268 | /* UFS device is also active now */ |
4269 | ufshcd_set_ufs_dev_active(hba); | |
66ec6d59 | 4270 | ufshcd_force_reset_auto_bkops(hba); |
3441da7d | 4271 | hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; |
57d104c1 SJ |
4272 | hba->wlun_dev_clr_ua = true; |
4273 | ||
7eb584db DR |
4274 | if (ufshcd_get_max_pwr_mode(hba)) { |
4275 | dev_err(hba->dev, | |
4276 | "%s: Failed getting max supported power mode\n", | |
4277 | __func__); | |
4278 | } else { | |
4279 | ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info); | |
4280 | if (ret) | |
4281 | dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n", | |
4282 | __func__, ret); | |
4283 | } | |
57d104c1 SJ |
4284 | |
4285 | /* | |
4286 | * If we are in error handling context or in power management callbacks | |
4287 | * context, no need to scan the host | |
4288 | */ | |
4289 | if (!ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) { | |
4290 | bool flag; | |
4291 | ||
4292 | /* clear any previous UFS device information */ | |
4293 | memset(&hba->dev_info, 0, sizeof(hba->dev_info)); | |
4294 | if (!ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG, | |
4295 | QUERY_FLAG_IDN_PWR_ON_WPE, &flag)) | |
4296 | hba->dev_info.f_power_on_wp_en = flag; | |
3441da7d | 4297 | |
3a4bf06d YG |
4298 | if (!hba->is_init_prefetch) |
4299 | ufshcd_init_icc_levels(hba); | |
4300 | ||
2a8fa600 SJ |
4301 | /* Add required well known logical units to scsi mid layer */ |
4302 | if (ufshcd_scsi_add_wlus(hba)) | |
4303 | goto out; | |
4304 | ||
3441da7d SRT |
4305 | scsi_scan_host(hba->host); |
4306 | pm_runtime_put_sync(hba->dev); | |
4307 | } | |
3a4bf06d YG |
4308 | |
4309 | if (!hba->is_init_prefetch) | |
4310 | hba->is_init_prefetch = true; | |
4311 | ||
856b3483 ST |
4312 | /* Resume devfreq after UFS device is detected */ |
4313 | if (ufshcd_is_clkscaling_enabled(hba)) | |
4314 | devfreq_resume_device(hba->devfreq); | |
4315 | ||
5a0b0cb9 | 4316 | out: |
1d337ec2 SRT |
4317 | /* |
4318 | * If we failed to initialize the device or the device is not | |
4319 | * present, turn off the power/clocks etc. | |
4320 | */ | |
57d104c1 SJ |
4321 | if (ret && !ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) { |
4322 | pm_runtime_put_sync(hba->dev); | |
1d337ec2 | 4323 | ufshcd_hba_exit(hba); |
57d104c1 | 4324 | } |
1d337ec2 SRT |
4325 | |
4326 | return ret; | |
4327 | } | |
4328 | ||
4329 | /** | |
4330 | * ufshcd_async_scan - asynchronous execution for probing hba | |
4331 | * @data: data pointer to pass to this function | |
4332 | * @cookie: cookie data | |
4333 | */ | |
4334 | static void ufshcd_async_scan(void *data, async_cookie_t cookie) | |
4335 | { | |
4336 | struct ufs_hba *hba = (struct ufs_hba *)data; | |
4337 | ||
4338 | ufshcd_probe_hba(hba); | |
6ccf44fe SJ |
4339 | } |
4340 | ||
7a3e97b0 SY |
4341 | static struct scsi_host_template ufshcd_driver_template = { |
4342 | .module = THIS_MODULE, | |
4343 | .name = UFSHCD, | |
4344 | .proc_name = UFSHCD, | |
4345 | .queuecommand = ufshcd_queuecommand, | |
4346 | .slave_alloc = ufshcd_slave_alloc, | |
eeda4749 | 4347 | .slave_configure = ufshcd_slave_configure, |
7a3e97b0 | 4348 | .slave_destroy = ufshcd_slave_destroy, |
4264fd61 | 4349 | .change_queue_depth = ufshcd_change_queue_depth, |
7a3e97b0 | 4350 | .eh_abort_handler = ufshcd_abort, |
3441da7d SRT |
4351 | .eh_device_reset_handler = ufshcd_eh_device_reset_handler, |
4352 | .eh_host_reset_handler = ufshcd_eh_host_reset_handler, | |
7a3e97b0 SY |
4353 | .this_id = -1, |
4354 | .sg_tablesize = SG_ALL, | |
4355 | .cmd_per_lun = UFSHCD_CMD_PER_LUN, | |
4356 | .can_queue = UFSHCD_CAN_QUEUE, | |
1ab27c9c | 4357 | .max_host_blocked = 1, |
2ecb204d | 4358 | .use_blk_tags = 1, |
c40ecc12 | 4359 | .track_queue_depth = 1, |
7a3e97b0 SY |
4360 | }; |
4361 | ||
57d104c1 SJ |
4362 | static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg, |
4363 | int ua) | |
4364 | { | |
7b16a07c | 4365 | int ret; |
57d104c1 | 4366 | |
7b16a07c BA |
4367 | if (!vreg) |
4368 | return 0; | |
57d104c1 | 4369 | |
7b16a07c BA |
4370 | ret = regulator_set_load(vreg->reg, ua); |
4371 | if (ret < 0) { | |
4372 | dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n", | |
4373 | __func__, vreg->name, ua, ret); | |
57d104c1 SJ |
4374 | } |
4375 | ||
4376 | return ret; | |
4377 | } | |
4378 | ||
4379 | static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba, | |
4380 | struct ufs_vreg *vreg) | |
4381 | { | |
4382 | return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA); | |
4383 | } | |
4384 | ||
4385 | static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba, | |
4386 | struct ufs_vreg *vreg) | |
4387 | { | |
4388 | return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA); | |
4389 | } | |
4390 | ||
aa497613 SRT |
4391 | static int ufshcd_config_vreg(struct device *dev, |
4392 | struct ufs_vreg *vreg, bool on) | |
4393 | { | |
4394 | int ret = 0; | |
4395 | struct regulator *reg = vreg->reg; | |
4396 | const char *name = vreg->name; | |
4397 | int min_uV, uA_load; | |
4398 | ||
4399 | BUG_ON(!vreg); | |
4400 | ||
4401 | if (regulator_count_voltages(reg) > 0) { | |
4402 | min_uV = on ? vreg->min_uV : 0; | |
4403 | ret = regulator_set_voltage(reg, min_uV, vreg->max_uV); | |
4404 | if (ret) { | |
4405 | dev_err(dev, "%s: %s set voltage failed, err=%d\n", | |
4406 | __func__, name, ret); | |
4407 | goto out; | |
4408 | } | |
4409 | ||
4410 | uA_load = on ? vreg->max_uA : 0; | |
57d104c1 SJ |
4411 | ret = ufshcd_config_vreg_load(dev, vreg, uA_load); |
4412 | if (ret) | |
aa497613 | 4413 | goto out; |
aa497613 SRT |
4414 | } |
4415 | out: | |
4416 | return ret; | |
4417 | } | |
4418 | ||
4419 | static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg) | |
4420 | { | |
4421 | int ret = 0; | |
4422 | ||
4423 | if (!vreg || vreg->enabled) | |
4424 | goto out; | |
4425 | ||
4426 | ret = ufshcd_config_vreg(dev, vreg, true); | |
4427 | if (!ret) | |
4428 | ret = regulator_enable(vreg->reg); | |
4429 | ||
4430 | if (!ret) | |
4431 | vreg->enabled = true; | |
4432 | else | |
4433 | dev_err(dev, "%s: %s enable failed, err=%d\n", | |
4434 | __func__, vreg->name, ret); | |
4435 | out: | |
4436 | return ret; | |
4437 | } | |
4438 | ||
4439 | static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg) | |
4440 | { | |
4441 | int ret = 0; | |
4442 | ||
4443 | if (!vreg || !vreg->enabled) | |
4444 | goto out; | |
4445 | ||
4446 | ret = regulator_disable(vreg->reg); | |
4447 | ||
4448 | if (!ret) { | |
4449 | /* ignore errors on applying disable config */ | |
4450 | ufshcd_config_vreg(dev, vreg, false); | |
4451 | vreg->enabled = false; | |
4452 | } else { | |
4453 | dev_err(dev, "%s: %s disable failed, err=%d\n", | |
4454 | __func__, vreg->name, ret); | |
4455 | } | |
4456 | out: | |
4457 | return ret; | |
4458 | } | |
4459 | ||
4460 | static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on) | |
4461 | { | |
4462 | int ret = 0; | |
4463 | struct device *dev = hba->dev; | |
4464 | struct ufs_vreg_info *info = &hba->vreg_info; | |
4465 | ||
4466 | if (!info) | |
4467 | goto out; | |
4468 | ||
4469 | ret = ufshcd_toggle_vreg(dev, info->vcc, on); | |
4470 | if (ret) | |
4471 | goto out; | |
4472 | ||
4473 | ret = ufshcd_toggle_vreg(dev, info->vccq, on); | |
4474 | if (ret) | |
4475 | goto out; | |
4476 | ||
4477 | ret = ufshcd_toggle_vreg(dev, info->vccq2, on); | |
4478 | if (ret) | |
4479 | goto out; | |
4480 | ||
4481 | out: | |
4482 | if (ret) { | |
4483 | ufshcd_toggle_vreg(dev, info->vccq2, false); | |
4484 | ufshcd_toggle_vreg(dev, info->vccq, false); | |
4485 | ufshcd_toggle_vreg(dev, info->vcc, false); | |
4486 | } | |
4487 | return ret; | |
4488 | } | |
4489 | ||
6a771a65 RS |
4490 | static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on) |
4491 | { | |
4492 | struct ufs_vreg_info *info = &hba->vreg_info; | |
4493 | ||
4494 | if (info) | |
4495 | return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on); | |
4496 | ||
4497 | return 0; | |
4498 | } | |
4499 | ||
aa497613 SRT |
4500 | static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg) |
4501 | { | |
4502 | int ret = 0; | |
4503 | ||
4504 | if (!vreg) | |
4505 | goto out; | |
4506 | ||
4507 | vreg->reg = devm_regulator_get(dev, vreg->name); | |
4508 | if (IS_ERR(vreg->reg)) { | |
4509 | ret = PTR_ERR(vreg->reg); | |
4510 | dev_err(dev, "%s: %s get failed, err=%d\n", | |
4511 | __func__, vreg->name, ret); | |
4512 | } | |
4513 | out: | |
4514 | return ret; | |
4515 | } | |
4516 | ||
4517 | static int ufshcd_init_vreg(struct ufs_hba *hba) | |
4518 | { | |
4519 | int ret = 0; | |
4520 | struct device *dev = hba->dev; | |
4521 | struct ufs_vreg_info *info = &hba->vreg_info; | |
4522 | ||
4523 | if (!info) | |
4524 | goto out; | |
4525 | ||
4526 | ret = ufshcd_get_vreg(dev, info->vcc); | |
4527 | if (ret) | |
4528 | goto out; | |
4529 | ||
4530 | ret = ufshcd_get_vreg(dev, info->vccq); | |
4531 | if (ret) | |
4532 | goto out; | |
4533 | ||
4534 | ret = ufshcd_get_vreg(dev, info->vccq2); | |
4535 | out: | |
4536 | return ret; | |
4537 | } | |
4538 | ||
6a771a65 RS |
4539 | static int ufshcd_init_hba_vreg(struct ufs_hba *hba) |
4540 | { | |
4541 | struct ufs_vreg_info *info = &hba->vreg_info; | |
4542 | ||
4543 | if (info) | |
4544 | return ufshcd_get_vreg(hba->dev, info->vdd_hba); | |
4545 | ||
4546 | return 0; | |
4547 | } | |
4548 | ||
57d104c1 SJ |
4549 | static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on, |
4550 | bool skip_ref_clk) | |
c6e79dac SRT |
4551 | { |
4552 | int ret = 0; | |
4553 | struct ufs_clk_info *clki; | |
4554 | struct list_head *head = &hba->clk_list_head; | |
1ab27c9c | 4555 | unsigned long flags; |
c6e79dac SRT |
4556 | |
4557 | if (!head || list_empty(head)) | |
4558 | goto out; | |
4559 | ||
4560 | list_for_each_entry(clki, head, list) { | |
4561 | if (!IS_ERR_OR_NULL(clki->clk)) { | |
57d104c1 SJ |
4562 | if (skip_ref_clk && !strcmp(clki->name, "ref_clk")) |
4563 | continue; | |
4564 | ||
c6e79dac SRT |
4565 | if (on && !clki->enabled) { |
4566 | ret = clk_prepare_enable(clki->clk); | |
4567 | if (ret) { | |
4568 | dev_err(hba->dev, "%s: %s prepare enable failed, %d\n", | |
4569 | __func__, clki->name, ret); | |
4570 | goto out; | |
4571 | } | |
4572 | } else if (!on && clki->enabled) { | |
4573 | clk_disable_unprepare(clki->clk); | |
4574 | } | |
4575 | clki->enabled = on; | |
4576 | dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__, | |
4577 | clki->name, on ? "en" : "dis"); | |
4578 | } | |
4579 | } | |
1ab27c9c ST |
4580 | |
4581 | if (hba->vops && hba->vops->setup_clocks) | |
4582 | ret = hba->vops->setup_clocks(hba, on); | |
c6e79dac SRT |
4583 | out: |
4584 | if (ret) { | |
4585 | list_for_each_entry(clki, head, list) { | |
4586 | if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled) | |
4587 | clk_disable_unprepare(clki->clk); | |
4588 | } | |
eda910e4 | 4589 | } else if (on) { |
1ab27c9c ST |
4590 | spin_lock_irqsave(hba->host->host_lock, flags); |
4591 | hba->clk_gating.state = CLKS_ON; | |
4592 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
c6e79dac SRT |
4593 | } |
4594 | return ret; | |
4595 | } | |
4596 | ||
57d104c1 SJ |
4597 | static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on) |
4598 | { | |
4599 | return __ufshcd_setup_clocks(hba, on, false); | |
4600 | } | |
4601 | ||
c6e79dac SRT |
4602 | static int ufshcd_init_clocks(struct ufs_hba *hba) |
4603 | { | |
4604 | int ret = 0; | |
4605 | struct ufs_clk_info *clki; | |
4606 | struct device *dev = hba->dev; | |
4607 | struct list_head *head = &hba->clk_list_head; | |
4608 | ||
4609 | if (!head || list_empty(head)) | |
4610 | goto out; | |
4611 | ||
4612 | list_for_each_entry(clki, head, list) { | |
4613 | if (!clki->name) | |
4614 | continue; | |
4615 | ||
4616 | clki->clk = devm_clk_get(dev, clki->name); | |
4617 | if (IS_ERR(clki->clk)) { | |
4618 | ret = PTR_ERR(clki->clk); | |
4619 | dev_err(dev, "%s: %s clk get failed, %d\n", | |
4620 | __func__, clki->name, ret); | |
4621 | goto out; | |
4622 | } | |
4623 | ||
4624 | if (clki->max_freq) { | |
4625 | ret = clk_set_rate(clki->clk, clki->max_freq); | |
4626 | if (ret) { | |
4627 | dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", | |
4628 | __func__, clki->name, | |
4629 | clki->max_freq, ret); | |
4630 | goto out; | |
4631 | } | |
856b3483 | 4632 | clki->curr_freq = clki->max_freq; |
c6e79dac SRT |
4633 | } |
4634 | dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__, | |
4635 | clki->name, clk_get_rate(clki->clk)); | |
4636 | } | |
4637 | out: | |
4638 | return ret; | |
4639 | } | |
4640 | ||
5c0c28a8 SRT |
4641 | static int ufshcd_variant_hba_init(struct ufs_hba *hba) |
4642 | { | |
4643 | int err = 0; | |
4644 | ||
4645 | if (!hba->vops) | |
4646 | goto out; | |
4647 | ||
4648 | if (hba->vops->init) { | |
4649 | err = hba->vops->init(hba); | |
4650 | if (err) | |
4651 | goto out; | |
4652 | } | |
4653 | ||
5c0c28a8 SRT |
4654 | if (hba->vops->setup_regulators) { |
4655 | err = hba->vops->setup_regulators(hba, true); | |
4656 | if (err) | |
1ab27c9c | 4657 | goto out_exit; |
5c0c28a8 SRT |
4658 | } |
4659 | ||
4660 | goto out; | |
4661 | ||
5c0c28a8 SRT |
4662 | out_exit: |
4663 | if (hba->vops->exit) | |
4664 | hba->vops->exit(hba); | |
4665 | out: | |
4666 | if (err) | |
4667 | dev_err(hba->dev, "%s: variant %s init failed err %d\n", | |
4668 | __func__, hba->vops ? hba->vops->name : "", err); | |
4669 | return err; | |
4670 | } | |
4671 | ||
4672 | static void ufshcd_variant_hba_exit(struct ufs_hba *hba) | |
4673 | { | |
4674 | if (!hba->vops) | |
4675 | return; | |
4676 | ||
4677 | if (hba->vops->setup_clocks) | |
4678 | hba->vops->setup_clocks(hba, false); | |
4679 | ||
4680 | if (hba->vops->setup_regulators) | |
4681 | hba->vops->setup_regulators(hba, false); | |
4682 | ||
4683 | if (hba->vops->exit) | |
4684 | hba->vops->exit(hba); | |
4685 | } | |
4686 | ||
aa497613 SRT |
4687 | static int ufshcd_hba_init(struct ufs_hba *hba) |
4688 | { | |
4689 | int err; | |
4690 | ||
6a771a65 RS |
4691 | /* |
4692 | * Handle host controller power separately from the UFS device power | |
4693 | * rails as it will help controlling the UFS host controller power | |
4694 | * collapse easily which is different than UFS device power collapse. | |
4695 | * Also, enable the host controller power before we go ahead with rest | |
4696 | * of the initialization here. | |
4697 | */ | |
4698 | err = ufshcd_init_hba_vreg(hba); | |
aa497613 SRT |
4699 | if (err) |
4700 | goto out; | |
4701 | ||
6a771a65 | 4702 | err = ufshcd_setup_hba_vreg(hba, true); |
aa497613 SRT |
4703 | if (err) |
4704 | goto out; | |
4705 | ||
6a771a65 RS |
4706 | err = ufshcd_init_clocks(hba); |
4707 | if (err) | |
4708 | goto out_disable_hba_vreg; | |
4709 | ||
4710 | err = ufshcd_setup_clocks(hba, true); | |
4711 | if (err) | |
4712 | goto out_disable_hba_vreg; | |
4713 | ||
c6e79dac SRT |
4714 | err = ufshcd_init_vreg(hba); |
4715 | if (err) | |
4716 | goto out_disable_clks; | |
4717 | ||
4718 | err = ufshcd_setup_vreg(hba, true); | |
4719 | if (err) | |
4720 | goto out_disable_clks; | |
4721 | ||
aa497613 SRT |
4722 | err = ufshcd_variant_hba_init(hba); |
4723 | if (err) | |
4724 | goto out_disable_vreg; | |
4725 | ||
1d337ec2 | 4726 | hba->is_powered = true; |
aa497613 SRT |
4727 | goto out; |
4728 | ||
4729 | out_disable_vreg: | |
4730 | ufshcd_setup_vreg(hba, false); | |
c6e79dac SRT |
4731 | out_disable_clks: |
4732 | ufshcd_setup_clocks(hba, false); | |
6a771a65 RS |
4733 | out_disable_hba_vreg: |
4734 | ufshcd_setup_hba_vreg(hba, false); | |
aa497613 SRT |
4735 | out: |
4736 | return err; | |
4737 | } | |
4738 | ||
4739 | static void ufshcd_hba_exit(struct ufs_hba *hba) | |
4740 | { | |
1d337ec2 SRT |
4741 | if (hba->is_powered) { |
4742 | ufshcd_variant_hba_exit(hba); | |
4743 | ufshcd_setup_vreg(hba, false); | |
4744 | ufshcd_setup_clocks(hba, false); | |
4745 | ufshcd_setup_hba_vreg(hba, false); | |
4746 | hba->is_powered = false; | |
4747 | } | |
aa497613 SRT |
4748 | } |
4749 | ||
57d104c1 SJ |
4750 | static int |
4751 | ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp) | |
4752 | { | |
4753 | unsigned char cmd[6] = {REQUEST_SENSE, | |
4754 | 0, | |
4755 | 0, | |
4756 | 0, | |
4757 | SCSI_SENSE_BUFFERSIZE, | |
4758 | 0}; | |
4759 | char *buffer; | |
4760 | int ret; | |
4761 | ||
4762 | buffer = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL); | |
4763 | if (!buffer) { | |
4764 | ret = -ENOMEM; | |
4765 | goto out; | |
4766 | } | |
4767 | ||
4768 | ret = scsi_execute_req_flags(sdp, cmd, DMA_FROM_DEVICE, buffer, | |
4769 | SCSI_SENSE_BUFFERSIZE, NULL, | |
4770 | msecs_to_jiffies(1000), 3, NULL, REQ_PM); | |
4771 | if (ret) | |
4772 | pr_err("%s: failed with err %d\n", __func__, ret); | |
4773 | ||
4774 | kfree(buffer); | |
4775 | out: | |
4776 | return ret; | |
4777 | } | |
4778 | ||
4779 | /** | |
4780 | * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device | |
4781 | * power mode | |
4782 | * @hba: per adapter instance | |
4783 | * @pwr_mode: device power mode to set | |
4784 | * | |
4785 | * Returns 0 if requested power mode is set successfully | |
4786 | * Returns non-zero if failed to set the requested power mode | |
4787 | */ | |
4788 | static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba, | |
4789 | enum ufs_dev_pwr_mode pwr_mode) | |
4790 | { | |
4791 | unsigned char cmd[6] = { START_STOP }; | |
4792 | struct scsi_sense_hdr sshdr; | |
7c48bfd0 AM |
4793 | struct scsi_device *sdp; |
4794 | unsigned long flags; | |
57d104c1 SJ |
4795 | int ret; |
4796 | ||
7c48bfd0 AM |
4797 | spin_lock_irqsave(hba->host->host_lock, flags); |
4798 | sdp = hba->sdev_ufs_device; | |
4799 | if (sdp) { | |
4800 | ret = scsi_device_get(sdp); | |
4801 | if (!ret && !scsi_device_online(sdp)) { | |
4802 | ret = -ENODEV; | |
4803 | scsi_device_put(sdp); | |
4804 | } | |
4805 | } else { | |
4806 | ret = -ENODEV; | |
4807 | } | |
4808 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
4809 | ||
4810 | if (ret) | |
4811 | return ret; | |
57d104c1 SJ |
4812 | |
4813 | /* | |
4814 | * If scsi commands fail, the scsi mid-layer schedules scsi error- | |
4815 | * handling, which would wait for host to be resumed. Since we know | |
4816 | * we are functional while we are here, skip host resume in error | |
4817 | * handling context. | |
4818 | */ | |
4819 | hba->host->eh_noresume = 1; | |
4820 | if (hba->wlun_dev_clr_ua) { | |
4821 | ret = ufshcd_send_request_sense(hba, sdp); | |
4822 | if (ret) | |
4823 | goto out; | |
4824 | /* Unit attention condition is cleared now */ | |
4825 | hba->wlun_dev_clr_ua = false; | |
4826 | } | |
4827 | ||
4828 | cmd[4] = pwr_mode << 4; | |
4829 | ||
4830 | /* | |
4831 | * Current function would be generally called from the power management | |
4832 | * callbacks hence set the REQ_PM flag so that it doesn't resume the | |
4833 | * already suspended childs. | |
4834 | */ | |
4835 | ret = scsi_execute_req_flags(sdp, cmd, DMA_NONE, NULL, 0, &sshdr, | |
4836 | START_STOP_TIMEOUT, 0, NULL, REQ_PM); | |
4837 | if (ret) { | |
4838 | sdev_printk(KERN_WARNING, sdp, | |
ef61329d HR |
4839 | "START_STOP failed for power mode: %d, result %x\n", |
4840 | pwr_mode, ret); | |
21045519 HR |
4841 | if (driver_byte(ret) & DRIVER_SENSE) |
4842 | scsi_print_sense_hdr(sdp, NULL, &sshdr); | |
57d104c1 SJ |
4843 | } |
4844 | ||
4845 | if (!ret) | |
4846 | hba->curr_dev_pwr_mode = pwr_mode; | |
4847 | out: | |
7c48bfd0 | 4848 | scsi_device_put(sdp); |
57d104c1 SJ |
4849 | hba->host->eh_noresume = 0; |
4850 | return ret; | |
4851 | } | |
4852 | ||
4853 | static int ufshcd_link_state_transition(struct ufs_hba *hba, | |
4854 | enum uic_link_state req_link_state, | |
4855 | int check_for_bkops) | |
4856 | { | |
4857 | int ret = 0; | |
4858 | ||
4859 | if (req_link_state == hba->uic_link_state) | |
4860 | return 0; | |
4861 | ||
4862 | if (req_link_state == UIC_LINK_HIBERN8_STATE) { | |
4863 | ret = ufshcd_uic_hibern8_enter(hba); | |
4864 | if (!ret) | |
4865 | ufshcd_set_link_hibern8(hba); | |
4866 | else | |
4867 | goto out; | |
4868 | } | |
4869 | /* | |
4870 | * If autobkops is enabled, link can't be turned off because | |
4871 | * turning off the link would also turn off the device. | |
4872 | */ | |
4873 | else if ((req_link_state == UIC_LINK_OFF_STATE) && | |
4874 | (!check_for_bkops || (check_for_bkops && | |
4875 | !hba->auto_bkops_enabled))) { | |
4876 | /* | |
4877 | * Change controller state to "reset state" which | |
4878 | * should also put the link in off/reset state | |
4879 | */ | |
4880 | ufshcd_hba_stop(hba); | |
4881 | /* | |
4882 | * TODO: Check if we need any delay to make sure that | |
4883 | * controller is reset | |
4884 | */ | |
4885 | ufshcd_set_link_off(hba); | |
4886 | } | |
4887 | ||
4888 | out: | |
4889 | return ret; | |
4890 | } | |
4891 | ||
4892 | static void ufshcd_vreg_set_lpm(struct ufs_hba *hba) | |
4893 | { | |
4894 | /* | |
4895 | * If UFS device is either in UFS_Sleep turn off VCC rail to save some | |
4896 | * power. | |
4897 | * | |
4898 | * If UFS device and link is in OFF state, all power supplies (VCC, | |
4899 | * VCCQ, VCCQ2) can be turned off if power on write protect is not | |
4900 | * required. If UFS link is inactive (Hibern8 or OFF state) and device | |
4901 | * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode. | |
4902 | * | |
4903 | * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway | |
4904 | * in low power state which would save some power. | |
4905 | */ | |
4906 | if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) && | |
4907 | !hba->dev_info.is_lu_power_on_wp) { | |
4908 | ufshcd_setup_vreg(hba, false); | |
4909 | } else if (!ufshcd_is_ufs_dev_active(hba)) { | |
4910 | ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false); | |
4911 | if (!ufshcd_is_link_active(hba)) { | |
4912 | ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq); | |
4913 | ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2); | |
4914 | } | |
4915 | } | |
4916 | } | |
4917 | ||
4918 | static int ufshcd_vreg_set_hpm(struct ufs_hba *hba) | |
4919 | { | |
4920 | int ret = 0; | |
4921 | ||
4922 | if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) && | |
4923 | !hba->dev_info.is_lu_power_on_wp) { | |
4924 | ret = ufshcd_setup_vreg(hba, true); | |
4925 | } else if (!ufshcd_is_ufs_dev_active(hba)) { | |
4926 | ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true); | |
4927 | if (!ret && !ufshcd_is_link_active(hba)) { | |
4928 | ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq); | |
4929 | if (ret) | |
4930 | goto vcc_disable; | |
4931 | ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2); | |
4932 | if (ret) | |
4933 | goto vccq_lpm; | |
4934 | } | |
4935 | } | |
4936 | goto out; | |
4937 | ||
4938 | vccq_lpm: | |
4939 | ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq); | |
4940 | vcc_disable: | |
4941 | ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false); | |
4942 | out: | |
4943 | return ret; | |
4944 | } | |
4945 | ||
4946 | static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba) | |
4947 | { | |
4948 | if (ufshcd_is_link_off(hba)) | |
4949 | ufshcd_setup_hba_vreg(hba, false); | |
4950 | } | |
4951 | ||
4952 | static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba) | |
4953 | { | |
4954 | if (ufshcd_is_link_off(hba)) | |
4955 | ufshcd_setup_hba_vreg(hba, true); | |
4956 | } | |
4957 | ||
7a3e97b0 | 4958 | /** |
57d104c1 | 4959 | * ufshcd_suspend - helper function for suspend operations |
3b1d0580 | 4960 | * @hba: per adapter instance |
57d104c1 SJ |
4961 | * @pm_op: desired low power operation type |
4962 | * | |
4963 | * This function will try to put the UFS device and link into low power | |
4964 | * mode based on the "rpm_lvl" (Runtime PM level) or "spm_lvl" | |
4965 | * (System PM level). | |
4966 | * | |
4967 | * If this function is called during shutdown, it will make sure that | |
4968 | * both UFS device and UFS link is powered off. | |
7a3e97b0 | 4969 | * |
57d104c1 SJ |
4970 | * NOTE: UFS device & link must be active before we enter in this function. |
4971 | * | |
4972 | * Returns 0 for success and non-zero for failure | |
7a3e97b0 | 4973 | */ |
57d104c1 | 4974 | static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) |
7a3e97b0 | 4975 | { |
57d104c1 SJ |
4976 | int ret = 0; |
4977 | enum ufs_pm_level pm_lvl; | |
4978 | enum ufs_dev_pwr_mode req_dev_pwr_mode; | |
4979 | enum uic_link_state req_link_state; | |
4980 | ||
4981 | hba->pm_op_in_progress = 1; | |
4982 | if (!ufshcd_is_shutdown_pm(pm_op)) { | |
4983 | pm_lvl = ufshcd_is_runtime_pm(pm_op) ? | |
4984 | hba->rpm_lvl : hba->spm_lvl; | |
4985 | req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl); | |
4986 | req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl); | |
4987 | } else { | |
4988 | req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE; | |
4989 | req_link_state = UIC_LINK_OFF_STATE; | |
4990 | } | |
4991 | ||
7a3e97b0 | 4992 | /* |
57d104c1 SJ |
4993 | * If we can't transition into any of the low power modes |
4994 | * just gate the clocks. | |
7a3e97b0 | 4995 | */ |
1ab27c9c ST |
4996 | ufshcd_hold(hba, false); |
4997 | hba->clk_gating.is_suspended = true; | |
4998 | ||
57d104c1 SJ |
4999 | if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE && |
5000 | req_link_state == UIC_LINK_ACTIVE_STATE) { | |
5001 | goto disable_clks; | |
5002 | } | |
7a3e97b0 | 5003 | |
57d104c1 SJ |
5004 | if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) && |
5005 | (req_link_state == hba->uic_link_state)) | |
5006 | goto out; | |
5007 | ||
5008 | /* UFS device & link must be active before we enter in this function */ | |
5009 | if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) { | |
5010 | ret = -EINVAL; | |
5011 | goto out; | |
5012 | } | |
5013 | ||
5014 | if (ufshcd_is_runtime_pm(pm_op)) { | |
374a246e SJ |
5015 | if (ufshcd_can_autobkops_during_suspend(hba)) { |
5016 | /* | |
5017 | * The device is idle with no requests in the queue, | |
5018 | * allow background operations if bkops status shows | |
5019 | * that performance might be impacted. | |
5020 | */ | |
5021 | ret = ufshcd_urgent_bkops(hba); | |
5022 | if (ret) | |
5023 | goto enable_gating; | |
5024 | } else { | |
5025 | /* make sure that auto bkops is disabled */ | |
5026 | ufshcd_disable_auto_bkops(hba); | |
5027 | } | |
57d104c1 SJ |
5028 | } |
5029 | ||
5030 | if ((req_dev_pwr_mode != hba->curr_dev_pwr_mode) && | |
5031 | ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) || | |
5032 | !ufshcd_is_runtime_pm(pm_op))) { | |
5033 | /* ensure that bkops is disabled */ | |
5034 | ufshcd_disable_auto_bkops(hba); | |
5035 | ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode); | |
5036 | if (ret) | |
1ab27c9c | 5037 | goto enable_gating; |
57d104c1 SJ |
5038 | } |
5039 | ||
5040 | ret = ufshcd_link_state_transition(hba, req_link_state, 1); | |
5041 | if (ret) | |
5042 | goto set_dev_active; | |
5043 | ||
5044 | ufshcd_vreg_set_lpm(hba); | |
5045 | ||
5046 | disable_clks: | |
856b3483 ST |
5047 | /* |
5048 | * The clock scaling needs access to controller registers. Hence, Wait | |
5049 | * for pending clock scaling work to be done before clocks are | |
5050 | * turned off. | |
5051 | */ | |
5052 | if (ufshcd_is_clkscaling_enabled(hba)) { | |
5053 | devfreq_suspend_device(hba->devfreq); | |
5054 | hba->clk_scaling.window_start_t = 0; | |
5055 | } | |
57d104c1 SJ |
5056 | /* |
5057 | * Call vendor specific suspend callback. As these callbacks may access | |
5058 | * vendor specific host controller register space call them before the | |
5059 | * host clocks are ON. | |
5060 | */ | |
5061 | if (hba->vops && hba->vops->suspend) { | |
5062 | ret = hba->vops->suspend(hba, pm_op); | |
5063 | if (ret) | |
5064 | goto set_link_active; | |
5065 | } | |
5066 | ||
5067 | if (hba->vops && hba->vops->setup_clocks) { | |
5068 | ret = hba->vops->setup_clocks(hba, false); | |
5069 | if (ret) | |
5070 | goto vops_resume; | |
5071 | } | |
5072 | ||
5073 | if (!ufshcd_is_link_active(hba)) | |
5074 | ufshcd_setup_clocks(hba, false); | |
5075 | else | |
5076 | /* If link is active, device ref_clk can't be switched off */ | |
5077 | __ufshcd_setup_clocks(hba, false, true); | |
5078 | ||
1ab27c9c | 5079 | hba->clk_gating.state = CLKS_OFF; |
57d104c1 SJ |
5080 | /* |
5081 | * Disable the host irq as host controller as there won't be any | |
5082 | * host controller trasanction expected till resume. | |
5083 | */ | |
5084 | ufshcd_disable_irq(hba); | |
5085 | /* Put the host controller in low power mode if possible */ | |
5086 | ufshcd_hba_vreg_set_lpm(hba); | |
5087 | goto out; | |
5088 | ||
5089 | vops_resume: | |
5090 | if (hba->vops && hba->vops->resume) | |
5091 | hba->vops->resume(hba, pm_op); | |
5092 | set_link_active: | |
5093 | ufshcd_vreg_set_hpm(hba); | |
5094 | if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba)) | |
5095 | ufshcd_set_link_active(hba); | |
5096 | else if (ufshcd_is_link_off(hba)) | |
5097 | ufshcd_host_reset_and_restore(hba); | |
5098 | set_dev_active: | |
5099 | if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE)) | |
5100 | ufshcd_disable_auto_bkops(hba); | |
1ab27c9c ST |
5101 | enable_gating: |
5102 | hba->clk_gating.is_suspended = false; | |
5103 | ufshcd_release(hba); | |
57d104c1 SJ |
5104 | out: |
5105 | hba->pm_op_in_progress = 0; | |
5106 | return ret; | |
7a3e97b0 SY |
5107 | } |
5108 | ||
5109 | /** | |
57d104c1 | 5110 | * ufshcd_resume - helper function for resume operations |
3b1d0580 | 5111 | * @hba: per adapter instance |
57d104c1 | 5112 | * @pm_op: runtime PM or system PM |
7a3e97b0 | 5113 | * |
57d104c1 SJ |
5114 | * This function basically brings the UFS device, UniPro link and controller |
5115 | * to active state. | |
5116 | * | |
5117 | * Returns 0 for success and non-zero for failure | |
7a3e97b0 | 5118 | */ |
57d104c1 | 5119 | static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) |
7a3e97b0 | 5120 | { |
57d104c1 SJ |
5121 | int ret; |
5122 | enum uic_link_state old_link_state; | |
5123 | ||
5124 | hba->pm_op_in_progress = 1; | |
5125 | old_link_state = hba->uic_link_state; | |
5126 | ||
5127 | ufshcd_hba_vreg_set_hpm(hba); | |
5128 | /* Make sure clocks are enabled before accessing controller */ | |
5129 | ret = ufshcd_setup_clocks(hba, true); | |
5130 | if (ret) | |
5131 | goto out; | |
5132 | ||
57d104c1 SJ |
5133 | /* enable the host irq as host controller would be active soon */ |
5134 | ret = ufshcd_enable_irq(hba); | |
5135 | if (ret) | |
5136 | goto disable_irq_and_vops_clks; | |
5137 | ||
5138 | ret = ufshcd_vreg_set_hpm(hba); | |
5139 | if (ret) | |
5140 | goto disable_irq_and_vops_clks; | |
5141 | ||
7a3e97b0 | 5142 | /* |
57d104c1 SJ |
5143 | * Call vendor specific resume callback. As these callbacks may access |
5144 | * vendor specific host controller register space call them when the | |
5145 | * host clocks are ON. | |
7a3e97b0 | 5146 | */ |
57d104c1 SJ |
5147 | if (hba->vops && hba->vops->resume) { |
5148 | ret = hba->vops->resume(hba, pm_op); | |
5149 | if (ret) | |
5150 | goto disable_vreg; | |
5151 | } | |
5152 | ||
5153 | if (ufshcd_is_link_hibern8(hba)) { | |
5154 | ret = ufshcd_uic_hibern8_exit(hba); | |
5155 | if (!ret) | |
5156 | ufshcd_set_link_active(hba); | |
5157 | else | |
5158 | goto vendor_suspend; | |
5159 | } else if (ufshcd_is_link_off(hba)) { | |
5160 | ret = ufshcd_host_reset_and_restore(hba); | |
5161 | /* | |
5162 | * ufshcd_host_reset_and_restore() should have already | |
5163 | * set the link state as active | |
5164 | */ | |
5165 | if (ret || !ufshcd_is_link_active(hba)) | |
5166 | goto vendor_suspend; | |
5167 | } | |
5168 | ||
5169 | if (!ufshcd_is_ufs_dev_active(hba)) { | |
5170 | ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE); | |
5171 | if (ret) | |
5172 | goto set_old_link_state; | |
5173 | } | |
5174 | ||
374a246e SJ |
5175 | /* |
5176 | * If BKOPs operations are urgently needed at this moment then | |
5177 | * keep auto-bkops enabled or else disable it. | |
5178 | */ | |
5179 | ufshcd_urgent_bkops(hba); | |
1ab27c9c ST |
5180 | hba->clk_gating.is_suspended = false; |
5181 | ||
856b3483 ST |
5182 | if (ufshcd_is_clkscaling_enabled(hba)) |
5183 | devfreq_resume_device(hba->devfreq); | |
5184 | ||
1ab27c9c ST |
5185 | /* Schedule clock gating in case of no access to UFS device yet */ |
5186 | ufshcd_release(hba); | |
57d104c1 SJ |
5187 | goto out; |
5188 | ||
5189 | set_old_link_state: | |
5190 | ufshcd_link_state_transition(hba, old_link_state, 0); | |
5191 | vendor_suspend: | |
5192 | if (hba->vops && hba->vops->suspend) | |
5193 | hba->vops->suspend(hba, pm_op); | |
5194 | disable_vreg: | |
5195 | ufshcd_vreg_set_lpm(hba); | |
5196 | disable_irq_and_vops_clks: | |
5197 | ufshcd_disable_irq(hba); | |
57d104c1 SJ |
5198 | ufshcd_setup_clocks(hba, false); |
5199 | out: | |
5200 | hba->pm_op_in_progress = 0; | |
5201 | return ret; | |
5202 | } | |
5203 | ||
5204 | /** | |
5205 | * ufshcd_system_suspend - system suspend routine | |
5206 | * @hba: per adapter instance | |
5207 | * @pm_op: runtime PM or system PM | |
5208 | * | |
5209 | * Check the description of ufshcd_suspend() function for more details. | |
5210 | * | |
5211 | * Returns 0 for success and non-zero for failure | |
5212 | */ | |
5213 | int ufshcd_system_suspend(struct ufs_hba *hba) | |
5214 | { | |
5215 | int ret = 0; | |
5216 | ||
5217 | if (!hba || !hba->is_powered) | |
233b594b | 5218 | return 0; |
57d104c1 SJ |
5219 | |
5220 | if (pm_runtime_suspended(hba->dev)) { | |
5221 | if (hba->rpm_lvl == hba->spm_lvl) | |
5222 | /* | |
5223 | * There is possibility that device may still be in | |
5224 | * active state during the runtime suspend. | |
5225 | */ | |
5226 | if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) == | |
5227 | hba->curr_dev_pwr_mode) && !hba->auto_bkops_enabled) | |
5228 | goto out; | |
5229 | ||
5230 | /* | |
5231 | * UFS device and/or UFS link low power states during runtime | |
5232 | * suspend seems to be different than what is expected during | |
5233 | * system suspend. Hence runtime resume the devic & link and | |
5234 | * let the system suspend low power states to take effect. | |
5235 | * TODO: If resume takes longer time, we might have optimize | |
5236 | * it in future by not resuming everything if possible. | |
5237 | */ | |
5238 | ret = ufshcd_runtime_resume(hba); | |
5239 | if (ret) | |
5240 | goto out; | |
5241 | } | |
5242 | ||
5243 | ret = ufshcd_suspend(hba, UFS_SYSTEM_PM); | |
5244 | out: | |
e785060e DR |
5245 | if (!ret) |
5246 | hba->is_sys_suspended = true; | |
57d104c1 SJ |
5247 | return ret; |
5248 | } | |
5249 | EXPORT_SYMBOL(ufshcd_system_suspend); | |
5250 | ||
5251 | /** | |
5252 | * ufshcd_system_resume - system resume routine | |
5253 | * @hba: per adapter instance | |
5254 | * | |
5255 | * Returns 0 for success and non-zero for failure | |
5256 | */ | |
7a3e97b0 | 5257 | |
57d104c1 SJ |
5258 | int ufshcd_system_resume(struct ufs_hba *hba) |
5259 | { | |
5260 | if (!hba || !hba->is_powered || pm_runtime_suspended(hba->dev)) | |
5261 | /* | |
5262 | * Let the runtime resume take care of resuming | |
5263 | * if runtime suspended. | |
5264 | */ | |
5265 | return 0; | |
5266 | ||
5267 | return ufshcd_resume(hba, UFS_SYSTEM_PM); | |
7a3e97b0 | 5268 | } |
57d104c1 | 5269 | EXPORT_SYMBOL(ufshcd_system_resume); |
3b1d0580 | 5270 | |
57d104c1 SJ |
5271 | /** |
5272 | * ufshcd_runtime_suspend - runtime suspend routine | |
5273 | * @hba: per adapter instance | |
5274 | * | |
5275 | * Check the description of ufshcd_suspend() function for more details. | |
5276 | * | |
5277 | * Returns 0 for success and non-zero for failure | |
5278 | */ | |
66ec6d59 SRT |
5279 | int ufshcd_runtime_suspend(struct ufs_hba *hba) |
5280 | { | |
57d104c1 | 5281 | if (!hba || !hba->is_powered) |
66ec6d59 SRT |
5282 | return 0; |
5283 | ||
57d104c1 | 5284 | return ufshcd_suspend(hba, UFS_RUNTIME_PM); |
66ec6d59 SRT |
5285 | } |
5286 | EXPORT_SYMBOL(ufshcd_runtime_suspend); | |
5287 | ||
57d104c1 SJ |
5288 | /** |
5289 | * ufshcd_runtime_resume - runtime resume routine | |
5290 | * @hba: per adapter instance | |
5291 | * | |
5292 | * This function basically brings the UFS device, UniPro link and controller | |
5293 | * to active state. Following operations are done in this function: | |
5294 | * | |
5295 | * 1. Turn on all the controller related clocks | |
5296 | * 2. Bring the UniPro link out of Hibernate state | |
5297 | * 3. If UFS device is in sleep state, turn ON VCC rail and bring the UFS device | |
5298 | * to active state. | |
5299 | * 4. If auto-bkops is enabled on the device, disable it. | |
5300 | * | |
5301 | * So following would be the possible power state after this function return | |
5302 | * successfully: | |
5303 | * S1: UFS device in Active state with VCC rail ON | |
5304 | * UniPro link in Active state | |
5305 | * All the UFS/UniPro controller clocks are ON | |
5306 | * | |
5307 | * Returns 0 for success and non-zero for failure | |
5308 | */ | |
66ec6d59 SRT |
5309 | int ufshcd_runtime_resume(struct ufs_hba *hba) |
5310 | { | |
57d104c1 | 5311 | if (!hba || !hba->is_powered) |
66ec6d59 | 5312 | return 0; |
57d104c1 SJ |
5313 | else |
5314 | return ufshcd_resume(hba, UFS_RUNTIME_PM); | |
66ec6d59 SRT |
5315 | } |
5316 | EXPORT_SYMBOL(ufshcd_runtime_resume); | |
5317 | ||
5318 | int ufshcd_runtime_idle(struct ufs_hba *hba) | |
5319 | { | |
5320 | return 0; | |
5321 | } | |
5322 | EXPORT_SYMBOL(ufshcd_runtime_idle); | |
5323 | ||
57d104c1 SJ |
5324 | /** |
5325 | * ufshcd_shutdown - shutdown routine | |
5326 | * @hba: per adapter instance | |
5327 | * | |
5328 | * This function would power off both UFS device and UFS link. | |
5329 | * | |
5330 | * Returns 0 always to allow force shutdown even in case of errors. | |
5331 | */ | |
5332 | int ufshcd_shutdown(struct ufs_hba *hba) | |
5333 | { | |
5334 | int ret = 0; | |
5335 | ||
5336 | if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba)) | |
5337 | goto out; | |
5338 | ||
5339 | if (pm_runtime_suspended(hba->dev)) { | |
5340 | ret = ufshcd_runtime_resume(hba); | |
5341 | if (ret) | |
5342 | goto out; | |
5343 | } | |
5344 | ||
5345 | ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM); | |
5346 | out: | |
5347 | if (ret) | |
5348 | dev_err(hba->dev, "%s failed, err %d\n", __func__, ret); | |
5349 | /* allow force shutdown even in case of errors */ | |
5350 | return 0; | |
5351 | } | |
5352 | EXPORT_SYMBOL(ufshcd_shutdown); | |
5353 | ||
7a3e97b0 | 5354 | /** |
3b1d0580 | 5355 | * ufshcd_remove - de-allocate SCSI host and host memory space |
7a3e97b0 | 5356 | * data structure memory |
3b1d0580 | 5357 | * @hba - per adapter instance |
7a3e97b0 | 5358 | */ |
3b1d0580 | 5359 | void ufshcd_remove(struct ufs_hba *hba) |
7a3e97b0 | 5360 | { |
cfdf9c91 | 5361 | scsi_remove_host(hba->host); |
7a3e97b0 | 5362 | /* disable interrupts */ |
2fbd009b | 5363 | ufshcd_disable_intr(hba, hba->intr_mask); |
7a3e97b0 | 5364 | ufshcd_hba_stop(hba); |
7a3e97b0 | 5365 | |
7a3e97b0 | 5366 | scsi_host_put(hba->host); |
5c0c28a8 | 5367 | |
1ab27c9c | 5368 | ufshcd_exit_clk_gating(hba); |
856b3483 ST |
5369 | if (ufshcd_is_clkscaling_enabled(hba)) |
5370 | devfreq_remove_device(hba->devfreq); | |
aa497613 | 5371 | ufshcd_hba_exit(hba); |
3b1d0580 VH |
5372 | } |
5373 | EXPORT_SYMBOL_GPL(ufshcd_remove); | |
5374 | ||
ca3d7bf9 AM |
5375 | /** |
5376 | * ufshcd_set_dma_mask - Set dma mask based on the controller | |
5377 | * addressing capability | |
5378 | * @hba: per adapter instance | |
5379 | * | |
5380 | * Returns 0 for success, non-zero for failure | |
5381 | */ | |
5382 | static int ufshcd_set_dma_mask(struct ufs_hba *hba) | |
5383 | { | |
5384 | if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) { | |
5385 | if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64))) | |
5386 | return 0; | |
5387 | } | |
5388 | return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32)); | |
5389 | } | |
5390 | ||
7a3e97b0 | 5391 | /** |
5c0c28a8 | 5392 | * ufshcd_alloc_host - allocate Host Bus Adapter (HBA) |
3b1d0580 VH |
5393 | * @dev: pointer to device handle |
5394 | * @hba_handle: driver private handle | |
7a3e97b0 SY |
5395 | * Returns 0 on success, non-zero value on failure |
5396 | */ | |
5c0c28a8 | 5397 | int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle) |
7a3e97b0 SY |
5398 | { |
5399 | struct Scsi_Host *host; | |
5400 | struct ufs_hba *hba; | |
5c0c28a8 | 5401 | int err = 0; |
7a3e97b0 | 5402 | |
3b1d0580 VH |
5403 | if (!dev) { |
5404 | dev_err(dev, | |
5405 | "Invalid memory reference for dev is NULL\n"); | |
5406 | err = -ENODEV; | |
7a3e97b0 SY |
5407 | goto out_error; |
5408 | } | |
5409 | ||
7a3e97b0 SY |
5410 | host = scsi_host_alloc(&ufshcd_driver_template, |
5411 | sizeof(struct ufs_hba)); | |
5412 | if (!host) { | |
3b1d0580 | 5413 | dev_err(dev, "scsi_host_alloc failed\n"); |
7a3e97b0 | 5414 | err = -ENOMEM; |
3b1d0580 | 5415 | goto out_error; |
7a3e97b0 SY |
5416 | } |
5417 | hba = shost_priv(host); | |
7a3e97b0 | 5418 | hba->host = host; |
3b1d0580 | 5419 | hba->dev = dev; |
5c0c28a8 SRT |
5420 | *hba_handle = hba; |
5421 | ||
5422 | out_error: | |
5423 | return err; | |
5424 | } | |
5425 | EXPORT_SYMBOL(ufshcd_alloc_host); | |
5426 | ||
856b3483 ST |
5427 | static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up) |
5428 | { | |
5429 | int ret = 0; | |
5430 | struct ufs_clk_info *clki; | |
5431 | struct list_head *head = &hba->clk_list_head; | |
5432 | ||
5433 | if (!head || list_empty(head)) | |
5434 | goto out; | |
5435 | ||
5436 | list_for_each_entry(clki, head, list) { | |
5437 | if (!IS_ERR_OR_NULL(clki->clk)) { | |
5438 | if (scale_up && clki->max_freq) { | |
5439 | if (clki->curr_freq == clki->max_freq) | |
5440 | continue; | |
5441 | ret = clk_set_rate(clki->clk, clki->max_freq); | |
5442 | if (ret) { | |
5443 | dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", | |
5444 | __func__, clki->name, | |
5445 | clki->max_freq, ret); | |
5446 | break; | |
5447 | } | |
5448 | clki->curr_freq = clki->max_freq; | |
5449 | ||
5450 | } else if (!scale_up && clki->min_freq) { | |
5451 | if (clki->curr_freq == clki->min_freq) | |
5452 | continue; | |
5453 | ret = clk_set_rate(clki->clk, clki->min_freq); | |
5454 | if (ret) { | |
5455 | dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", | |
5456 | __func__, clki->name, | |
5457 | clki->min_freq, ret); | |
5458 | break; | |
5459 | } | |
5460 | clki->curr_freq = clki->min_freq; | |
5461 | } | |
5462 | } | |
5463 | dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__, | |
5464 | clki->name, clk_get_rate(clki->clk)); | |
5465 | } | |
5466 | if (hba->vops->clk_scale_notify) | |
5467 | hba->vops->clk_scale_notify(hba); | |
5468 | out: | |
5469 | return ret; | |
5470 | } | |
5471 | ||
5472 | static int ufshcd_devfreq_target(struct device *dev, | |
5473 | unsigned long *freq, u32 flags) | |
5474 | { | |
5475 | int err = 0; | |
5476 | struct ufs_hba *hba = dev_get_drvdata(dev); | |
5477 | ||
5478 | if (!ufshcd_is_clkscaling_enabled(hba)) | |
5479 | return -EINVAL; | |
5480 | ||
5481 | if (*freq == UINT_MAX) | |
5482 | err = ufshcd_scale_clks(hba, true); | |
5483 | else if (*freq == 0) | |
5484 | err = ufshcd_scale_clks(hba, false); | |
5485 | ||
5486 | return err; | |
5487 | } | |
5488 | ||
5489 | static int ufshcd_devfreq_get_dev_status(struct device *dev, | |
5490 | struct devfreq_dev_status *stat) | |
5491 | { | |
5492 | struct ufs_hba *hba = dev_get_drvdata(dev); | |
5493 | struct ufs_clk_scaling *scaling = &hba->clk_scaling; | |
5494 | unsigned long flags; | |
5495 | ||
5496 | if (!ufshcd_is_clkscaling_enabled(hba)) | |
5497 | return -EINVAL; | |
5498 | ||
5499 | memset(stat, 0, sizeof(*stat)); | |
5500 | ||
5501 | spin_lock_irqsave(hba->host->host_lock, flags); | |
5502 | if (!scaling->window_start_t) | |
5503 | goto start_window; | |
5504 | ||
5505 | if (scaling->is_busy_started) | |
5506 | scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(), | |
5507 | scaling->busy_start_t)); | |
5508 | ||
5509 | stat->total_time = jiffies_to_usecs((long)jiffies - | |
5510 | (long)scaling->window_start_t); | |
5511 | stat->busy_time = scaling->tot_busy_t; | |
5512 | start_window: | |
5513 | scaling->window_start_t = jiffies; | |
5514 | scaling->tot_busy_t = 0; | |
5515 | ||
5516 | if (hba->outstanding_reqs) { | |
5517 | scaling->busy_start_t = ktime_get(); | |
5518 | scaling->is_busy_started = true; | |
5519 | } else { | |
5520 | scaling->busy_start_t = ktime_set(0, 0); | |
5521 | scaling->is_busy_started = false; | |
5522 | } | |
5523 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
5524 | return 0; | |
5525 | } | |
5526 | ||
5527 | static struct devfreq_dev_profile ufs_devfreq_profile = { | |
5528 | .polling_ms = 100, | |
5529 | .target = ufshcd_devfreq_target, | |
5530 | .get_dev_status = ufshcd_devfreq_get_dev_status, | |
5531 | }; | |
5532 | ||
5c0c28a8 SRT |
5533 | /** |
5534 | * ufshcd_init - Driver initialization routine | |
5535 | * @hba: per-adapter instance | |
5536 | * @mmio_base: base register address | |
5537 | * @irq: Interrupt line of device | |
5538 | * Returns 0 on success, non-zero value on failure | |
5539 | */ | |
5540 | int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq) | |
5541 | { | |
5542 | int err; | |
5543 | struct Scsi_Host *host = hba->host; | |
5544 | struct device *dev = hba->dev; | |
5545 | ||
5546 | if (!mmio_base) { | |
5547 | dev_err(hba->dev, | |
5548 | "Invalid memory reference for mmio_base is NULL\n"); | |
5549 | err = -ENODEV; | |
5550 | goto out_error; | |
5551 | } | |
5552 | ||
3b1d0580 VH |
5553 | hba->mmio_base = mmio_base; |
5554 | hba->irq = irq; | |
7a3e97b0 | 5555 | |
aa497613 | 5556 | err = ufshcd_hba_init(hba); |
5c0c28a8 SRT |
5557 | if (err) |
5558 | goto out_error; | |
5559 | ||
7a3e97b0 SY |
5560 | /* Read capabilities registers */ |
5561 | ufshcd_hba_capabilities(hba); | |
5562 | ||
5563 | /* Get UFS version supported by the controller */ | |
5564 | hba->ufs_version = ufshcd_get_ufs_version(hba); | |
5565 | ||
2fbd009b SJ |
5566 | /* Get Interrupt bit mask per version */ |
5567 | hba->intr_mask = ufshcd_get_intr_mask(hba); | |
5568 | ||
ca3d7bf9 AM |
5569 | err = ufshcd_set_dma_mask(hba); |
5570 | if (err) { | |
5571 | dev_err(hba->dev, "set dma mask failed\n"); | |
5572 | goto out_disable; | |
5573 | } | |
5574 | ||
7a3e97b0 SY |
5575 | /* Allocate memory for host memory space */ |
5576 | err = ufshcd_memory_alloc(hba); | |
5577 | if (err) { | |
3b1d0580 VH |
5578 | dev_err(hba->dev, "Memory allocation failed\n"); |
5579 | goto out_disable; | |
7a3e97b0 SY |
5580 | } |
5581 | ||
5582 | /* Configure LRB */ | |
5583 | ufshcd_host_memory_configure(hba); | |
5584 | ||
5585 | host->can_queue = hba->nutrs; | |
5586 | host->cmd_per_lun = hba->nutrs; | |
5587 | host->max_id = UFSHCD_MAX_ID; | |
0ce147d4 | 5588 | host->max_lun = UFS_MAX_LUNS; |
7a3e97b0 SY |
5589 | host->max_channel = UFSHCD_MAX_CHANNEL; |
5590 | host->unique_id = host->host_no; | |
5591 | host->max_cmd_len = MAX_CDB_SIZE; | |
5592 | ||
7eb584db DR |
5593 | hba->max_pwr_info.is_valid = false; |
5594 | ||
7a3e97b0 | 5595 | /* Initailize wait queue for task management */ |
e2933132 SRT |
5596 | init_waitqueue_head(&hba->tm_wq); |
5597 | init_waitqueue_head(&hba->tm_tag_wq); | |
7a3e97b0 SY |
5598 | |
5599 | /* Initialize work queues */ | |
e8e7f271 | 5600 | INIT_WORK(&hba->eh_work, ufshcd_err_handler); |
66ec6d59 | 5601 | INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler); |
7a3e97b0 | 5602 | |
6ccf44fe SJ |
5603 | /* Initialize UIC command mutex */ |
5604 | mutex_init(&hba->uic_cmd_mutex); | |
5605 | ||
5a0b0cb9 SRT |
5606 | /* Initialize mutex for device management commands */ |
5607 | mutex_init(&hba->dev_cmd.lock); | |
5608 | ||
5609 | /* Initialize device management tag acquire wait queue */ | |
5610 | init_waitqueue_head(&hba->dev_cmd.tag_wq); | |
5611 | ||
1ab27c9c | 5612 | ufshcd_init_clk_gating(hba); |
7a3e97b0 | 5613 | /* IRQ registration */ |
2953f850 | 5614 | err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba); |
7a3e97b0 | 5615 | if (err) { |
3b1d0580 | 5616 | dev_err(hba->dev, "request irq failed\n"); |
1ab27c9c | 5617 | goto exit_gating; |
57d104c1 SJ |
5618 | } else { |
5619 | hba->is_irq_enabled = true; | |
7a3e97b0 SY |
5620 | } |
5621 | ||
5622 | /* Enable SCSI tag mapping */ | |
5623 | err = scsi_init_shared_tag_map(host, host->can_queue); | |
5624 | if (err) { | |
3b1d0580 | 5625 | dev_err(hba->dev, "init shared queue failed\n"); |
1ab27c9c | 5626 | goto exit_gating; |
7a3e97b0 SY |
5627 | } |
5628 | ||
3b1d0580 | 5629 | err = scsi_add_host(host, hba->dev); |
7a3e97b0 | 5630 | if (err) { |
3b1d0580 | 5631 | dev_err(hba->dev, "scsi_add_host failed\n"); |
1ab27c9c | 5632 | goto exit_gating; |
7a3e97b0 SY |
5633 | } |
5634 | ||
6ccf44fe SJ |
5635 | /* Host controller enable */ |
5636 | err = ufshcd_hba_enable(hba); | |
7a3e97b0 | 5637 | if (err) { |
6ccf44fe | 5638 | dev_err(hba->dev, "Host controller enable failed\n"); |
3b1d0580 | 5639 | goto out_remove_scsi_host; |
7a3e97b0 | 5640 | } |
6ccf44fe | 5641 | |
856b3483 ST |
5642 | if (ufshcd_is_clkscaling_enabled(hba)) { |
5643 | hba->devfreq = devfreq_add_device(dev, &ufs_devfreq_profile, | |
5644 | "simple_ondemand", NULL); | |
5645 | if (IS_ERR(hba->devfreq)) { | |
5646 | dev_err(hba->dev, "Unable to register with devfreq %ld\n", | |
5647 | PTR_ERR(hba->devfreq)); | |
5648 | goto out_remove_scsi_host; | |
5649 | } | |
5650 | /* Suspend devfreq until the UFS device is detected */ | |
5651 | devfreq_suspend_device(hba->devfreq); | |
5652 | hba->clk_scaling.window_start_t = 0; | |
5653 | } | |
5654 | ||
62694735 SRT |
5655 | /* Hold auto suspend until async scan completes */ |
5656 | pm_runtime_get_sync(dev); | |
5657 | ||
57d104c1 SJ |
5658 | /* |
5659 | * The device-initialize-sequence hasn't been invoked yet. | |
5660 | * Set the device to power-off state | |
5661 | */ | |
5662 | ufshcd_set_ufs_dev_poweroff(hba); | |
5663 | ||
6ccf44fe SJ |
5664 | async_schedule(ufshcd_async_scan, hba); |
5665 | ||
7a3e97b0 SY |
5666 | return 0; |
5667 | ||
3b1d0580 VH |
5668 | out_remove_scsi_host: |
5669 | scsi_remove_host(hba->host); | |
1ab27c9c ST |
5670 | exit_gating: |
5671 | ufshcd_exit_clk_gating(hba); | |
3b1d0580 | 5672 | out_disable: |
57d104c1 | 5673 | hba->is_irq_enabled = false; |
3b1d0580 | 5674 | scsi_host_put(host); |
aa497613 | 5675 | ufshcd_hba_exit(hba); |
3b1d0580 VH |
5676 | out_error: |
5677 | return err; | |
5678 | } | |
5679 | EXPORT_SYMBOL_GPL(ufshcd_init); | |
5680 | ||
3b1d0580 VH |
5681 | MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>"); |
5682 | MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>"); | |
e0eca63e | 5683 | MODULE_DESCRIPTION("Generic UFS host controller driver Core"); |
7a3e97b0 SY |
5684 | MODULE_LICENSE("GPL"); |
5685 | MODULE_VERSION(UFSHCD_DRIVER_VERSION); |