Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/drivers/char/8250.c | |
3 | * | |
4 | * Driver for 8250/16550-type serial ports | |
5 | * | |
6 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
7 | * | |
8 | * Copyright (C) 2001 Russell King. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * $Id: 8250.c,v 1.90 2002/07/28 10:03:27 rmk Exp $ | |
16 | * | |
17 | * A note about mapbase / membase | |
18 | * | |
19 | * mapbase is the physical address of the IO port. | |
20 | * membase is an 'ioremapped' cookie. | |
21 | */ | |
1da177e4 LT |
22 | |
23 | #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
24 | #define SUPPORT_SYSRQ | |
25 | #endif | |
26 | ||
27 | #include <linux/module.h> | |
28 | #include <linux/moduleparam.h> | |
29 | #include <linux/ioport.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/console.h> | |
32 | #include <linux/sysrq.h> | |
1da177e4 | 33 | #include <linux/delay.h> |
d052d1be | 34 | #include <linux/platform_device.h> |
1da177e4 LT |
35 | #include <linux/tty.h> |
36 | #include <linux/tty_flip.h> | |
37 | #include <linux/serial_reg.h> | |
38 | #include <linux/serial_core.h> | |
39 | #include <linux/serial.h> | |
40 | #include <linux/serial_8250.h> | |
78512ece | 41 | #include <linux/nmi.h> |
f392ecfa | 42 | #include <linux/mutex.h> |
1da177e4 LT |
43 | |
44 | #include <asm/io.h> | |
45 | #include <asm/irq.h> | |
46 | ||
47 | #include "8250.h" | |
48 | ||
49 | /* | |
50 | * Configuration: | |
40663cc7 | 51 | * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option |
1da177e4 LT |
52 | * is unsafe when used on edge-triggered interrupts. |
53 | */ | |
408b664a | 54 | static unsigned int share_irqs = SERIAL8250_SHARE_IRQS; |
1da177e4 | 55 | |
a61c2d78 DJ |
56 | static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS; |
57 | ||
1da177e4 LT |
58 | /* |
59 | * Debugging. | |
60 | */ | |
61 | #if 0 | |
62 | #define DEBUG_AUTOCONF(fmt...) printk(fmt) | |
63 | #else | |
64 | #define DEBUG_AUTOCONF(fmt...) do { } while (0) | |
65 | #endif | |
66 | ||
67 | #if 0 | |
68 | #define DEBUG_INTR(fmt...) printk(fmt) | |
69 | #else | |
70 | #define DEBUG_INTR(fmt...) do { } while (0) | |
71 | #endif | |
72 | ||
73 | #define PASS_LIMIT 256 | |
74 | ||
75 | /* | |
76 | * We default to IRQ0 for the "no irq" hack. Some | |
77 | * machine types want others as well - they're free | |
78 | * to redefine this in their header file. | |
79 | */ | |
80 | #define is_real_interrupt(irq) ((irq) != 0) | |
81 | ||
1da177e4 LT |
82 | #ifdef CONFIG_SERIAL_8250_DETECT_IRQ |
83 | #define CONFIG_SERIAL_DETECT_IRQ 1 | |
84 | #endif | |
1da177e4 LT |
85 | #ifdef CONFIG_SERIAL_8250_MANY_PORTS |
86 | #define CONFIG_SERIAL_MANY_PORTS 1 | |
87 | #endif | |
88 | ||
89 | /* | |
90 | * HUB6 is always on. This will be removed once the header | |
91 | * files have been cleaned. | |
92 | */ | |
93 | #define CONFIG_HUB6 1 | |
94 | ||
95 | #include <asm/serial.h> | |
96 | ||
97 | /* | |
98 | * SERIAL_PORT_DFNS tells us about built-in ports that have no | |
99 | * standard enumeration mechanism. Platforms that can find all | |
100 | * serial ports via mechanisms like ACPI or PCI need not supply it. | |
101 | */ | |
102 | #ifndef SERIAL_PORT_DFNS | |
103 | #define SERIAL_PORT_DFNS | |
104 | #endif | |
105 | ||
cb3592be | 106 | static const struct old_serial_port old_serial_port[] = { |
1da177e4 LT |
107 | SERIAL_PORT_DFNS /* defined in asm/serial.h */ |
108 | }; | |
109 | ||
026d02a2 | 110 | #define UART_NR CONFIG_SERIAL_8250_NR_UARTS |
1da177e4 LT |
111 | |
112 | #ifdef CONFIG_SERIAL_8250_RSA | |
113 | ||
114 | #define PORT_RSA_MAX 4 | |
115 | static unsigned long probe_rsa[PORT_RSA_MAX]; | |
116 | static unsigned int probe_rsa_count; | |
117 | #endif /* CONFIG_SERIAL_8250_RSA */ | |
118 | ||
119 | struct uart_8250_port { | |
120 | struct uart_port port; | |
121 | struct timer_list timer; /* "no irq" timer */ | |
122 | struct list_head list; /* ports on this IRQ */ | |
4ba5e35d RK |
123 | unsigned short capabilities; /* port capabilities */ |
124 | unsigned short bugs; /* port bugs */ | |
1da177e4 | 125 | unsigned int tx_loadsz; /* transmit fifo load size */ |
1da177e4 LT |
126 | unsigned char acr; |
127 | unsigned char ier; | |
128 | unsigned char lcr; | |
129 | unsigned char mcr; | |
130 | unsigned char mcr_mask; /* mask of user bits */ | |
131 | unsigned char mcr_force; /* mask of forced bits */ | |
ad4c2aa6 CM |
132 | |
133 | /* | |
134 | * Some bits in registers are cleared on a read, so they must | |
135 | * be saved whenever the register is read but the bits will not | |
136 | * be immediately processed. | |
137 | */ | |
138 | #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS | |
139 | unsigned char lsr_saved_flags; | |
140 | #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA | |
141 | unsigned char msr_saved_flags; | |
1da177e4 LT |
142 | |
143 | /* | |
144 | * We provide a per-port pm hook. | |
145 | */ | |
146 | void (*pm)(struct uart_port *port, | |
147 | unsigned int state, unsigned int old); | |
148 | }; | |
149 | ||
150 | struct irq_info { | |
151 | spinlock_t lock; | |
152 | struct list_head *head; | |
153 | }; | |
154 | ||
155 | static struct irq_info irq_lists[NR_IRQS]; | |
156 | ||
157 | /* | |
158 | * Here we define the default xmit fifo size used for each type of UART. | |
159 | */ | |
160 | static const struct serial8250_config uart_config[] = { | |
161 | [PORT_UNKNOWN] = { | |
162 | .name = "unknown", | |
163 | .fifo_size = 1, | |
164 | .tx_loadsz = 1, | |
165 | }, | |
166 | [PORT_8250] = { | |
167 | .name = "8250", | |
168 | .fifo_size = 1, | |
169 | .tx_loadsz = 1, | |
170 | }, | |
171 | [PORT_16450] = { | |
172 | .name = "16450", | |
173 | .fifo_size = 1, | |
174 | .tx_loadsz = 1, | |
175 | }, | |
176 | [PORT_16550] = { | |
177 | .name = "16550", | |
178 | .fifo_size = 1, | |
179 | .tx_loadsz = 1, | |
180 | }, | |
181 | [PORT_16550A] = { | |
182 | .name = "16550A", | |
183 | .fifo_size = 16, | |
184 | .tx_loadsz = 16, | |
185 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
186 | .flags = UART_CAP_FIFO, | |
187 | }, | |
188 | [PORT_CIRRUS] = { | |
189 | .name = "Cirrus", | |
190 | .fifo_size = 1, | |
191 | .tx_loadsz = 1, | |
192 | }, | |
193 | [PORT_16650] = { | |
194 | .name = "ST16650", | |
195 | .fifo_size = 1, | |
196 | .tx_loadsz = 1, | |
197 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, | |
198 | }, | |
199 | [PORT_16650V2] = { | |
200 | .name = "ST16650V2", | |
201 | .fifo_size = 32, | |
202 | .tx_loadsz = 16, | |
203 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | | |
204 | UART_FCR_T_TRIG_00, | |
205 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, | |
206 | }, | |
207 | [PORT_16750] = { | |
208 | .name = "TI16750", | |
209 | .fifo_size = 64, | |
210 | .tx_loadsz = 64, | |
211 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | | |
212 | UART_FCR7_64BYTE, | |
213 | .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE, | |
214 | }, | |
215 | [PORT_STARTECH] = { | |
216 | .name = "Startech", | |
217 | .fifo_size = 1, | |
218 | .tx_loadsz = 1, | |
219 | }, | |
220 | [PORT_16C950] = { | |
221 | .name = "16C950/954", | |
222 | .fifo_size = 128, | |
223 | .tx_loadsz = 128, | |
224 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
225 | .flags = UART_CAP_FIFO, | |
226 | }, | |
227 | [PORT_16654] = { | |
228 | .name = "ST16654", | |
229 | .fifo_size = 64, | |
230 | .tx_loadsz = 32, | |
231 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | | |
232 | UART_FCR_T_TRIG_10, | |
233 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, | |
234 | }, | |
235 | [PORT_16850] = { | |
236 | .name = "XR16850", | |
237 | .fifo_size = 128, | |
238 | .tx_loadsz = 128, | |
239 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
240 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, | |
241 | }, | |
242 | [PORT_RSA] = { | |
243 | .name = "RSA", | |
244 | .fifo_size = 2048, | |
245 | .tx_loadsz = 2048, | |
246 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11, | |
247 | .flags = UART_CAP_FIFO, | |
248 | }, | |
249 | [PORT_NS16550A] = { | |
250 | .name = "NS16550A", | |
251 | .fifo_size = 16, | |
252 | .tx_loadsz = 16, | |
253 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
254 | .flags = UART_CAP_FIFO | UART_NATSEMI, | |
255 | }, | |
256 | [PORT_XSCALE] = { | |
257 | .name = "XScale", | |
258 | .fifo_size = 32, | |
259 | .tx_loadsz = 32, | |
260 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
261 | .flags = UART_CAP_FIFO | UART_CAP_UUE, | |
262 | }, | |
bd71c182 TK |
263 | [PORT_RM9000] = { |
264 | .name = "RM9000", | |
265 | .fifo_size = 16, | |
266 | .tx_loadsz = 16, | |
267 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
268 | .flags = UART_CAP_FIFO, | |
269 | }, | |
1da177e4 LT |
270 | }; |
271 | ||
bd71c182 | 272 | #if defined (CONFIG_SERIAL_8250_AU1X00) |
21c614a7 PA |
273 | |
274 | /* Au1x00 UART hardware has a weird register layout */ | |
275 | static const u8 au_io_in_map[] = { | |
276 | [UART_RX] = 0, | |
277 | [UART_IER] = 2, | |
278 | [UART_IIR] = 3, | |
279 | [UART_LCR] = 5, | |
280 | [UART_MCR] = 6, | |
281 | [UART_LSR] = 7, | |
282 | [UART_MSR] = 8, | |
283 | }; | |
284 | ||
285 | static const u8 au_io_out_map[] = { | |
286 | [UART_TX] = 1, | |
287 | [UART_IER] = 2, | |
288 | [UART_FCR] = 4, | |
289 | [UART_LCR] = 5, | |
290 | [UART_MCR] = 6, | |
291 | }; | |
292 | ||
293 | /* sane hardware needs no mapping */ | |
294 | static inline int map_8250_in_reg(struct uart_8250_port *up, int offset) | |
295 | { | |
296 | if (up->port.iotype != UPIO_AU) | |
297 | return offset; | |
298 | return au_io_in_map[offset]; | |
299 | } | |
300 | ||
301 | static inline int map_8250_out_reg(struct uart_8250_port *up, int offset) | |
302 | { | |
303 | if (up->port.iotype != UPIO_AU) | |
304 | return offset; | |
305 | return au_io_out_map[offset]; | |
306 | } | |
307 | ||
6f803cd0 | 308 | #elif defined(CONFIG_SERIAL_8250_RM9K) |
bd71c182 TK |
309 | |
310 | static const u8 | |
311 | regmap_in[8] = { | |
312 | [UART_RX] = 0x00, | |
313 | [UART_IER] = 0x0c, | |
314 | [UART_IIR] = 0x14, | |
315 | [UART_LCR] = 0x1c, | |
316 | [UART_MCR] = 0x20, | |
317 | [UART_LSR] = 0x24, | |
318 | [UART_MSR] = 0x28, | |
319 | [UART_SCR] = 0x2c | |
320 | }, | |
321 | regmap_out[8] = { | |
322 | [UART_TX] = 0x04, | |
323 | [UART_IER] = 0x0c, | |
324 | [UART_FCR] = 0x18, | |
325 | [UART_LCR] = 0x1c, | |
326 | [UART_MCR] = 0x20, | |
327 | [UART_LSR] = 0x24, | |
328 | [UART_MSR] = 0x28, | |
329 | [UART_SCR] = 0x2c | |
330 | }; | |
331 | ||
332 | static inline int map_8250_in_reg(struct uart_8250_port *up, int offset) | |
333 | { | |
334 | if (up->port.iotype != UPIO_RM9000) | |
335 | return offset; | |
336 | return regmap_in[offset]; | |
337 | } | |
338 | ||
339 | static inline int map_8250_out_reg(struct uart_8250_port *up, int offset) | |
340 | { | |
341 | if (up->port.iotype != UPIO_RM9000) | |
342 | return offset; | |
343 | return regmap_out[offset]; | |
344 | } | |
345 | ||
21c614a7 PA |
346 | #else |
347 | ||
348 | /* sane hardware needs no mapping */ | |
349 | #define map_8250_in_reg(up, offset) (offset) | |
350 | #define map_8250_out_reg(up, offset) (offset) | |
351 | ||
352 | #endif | |
353 | ||
ea8874dc | 354 | static unsigned int serial_in(struct uart_8250_port *up, int offset) |
1da177e4 | 355 | { |
3be91ec7 | 356 | unsigned int tmp; |
21c614a7 | 357 | offset = map_8250_in_reg(up, offset) << up->port.regshift; |
1da177e4 LT |
358 | |
359 | switch (up->port.iotype) { | |
360 | case UPIO_HUB6: | |
361 | outb(up->port.hub6 - 1 + offset, up->port.iobase); | |
362 | return inb(up->port.iobase + 1); | |
363 | ||
364 | case UPIO_MEM: | |
beab697a | 365 | case UPIO_DWAPB: |
1da177e4 LT |
366 | return readb(up->port.membase + offset); |
367 | ||
bd71c182 | 368 | case UPIO_RM9000: |
1da177e4 LT |
369 | case UPIO_MEM32: |
370 | return readl(up->port.membase + offset); | |
371 | ||
21c614a7 PA |
372 | #ifdef CONFIG_SERIAL_8250_AU1X00 |
373 | case UPIO_AU: | |
374 | return __raw_readl(up->port.membase + offset); | |
375 | #endif | |
376 | ||
3be91ec7 ZR |
377 | case UPIO_TSI: |
378 | if (offset == UART_IIR) { | |
9e84b60e AV |
379 | tmp = readl(up->port.membase + (UART_IIR & ~3)); |
380 | return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */ | |
3be91ec7 ZR |
381 | } else |
382 | return readb(up->port.membase + offset); | |
383 | ||
1da177e4 LT |
384 | default: |
385 | return inb(up->port.iobase + offset); | |
386 | } | |
387 | } | |
388 | ||
ea8874dc | 389 | static void |
1da177e4 LT |
390 | serial_out(struct uart_8250_port *up, int offset, int value) |
391 | { | |
beab697a MSJ |
392 | /* Save the offset before it's remapped */ |
393 | int save_offset = offset; | |
21c614a7 | 394 | offset = map_8250_out_reg(up, offset) << up->port.regshift; |
1da177e4 LT |
395 | |
396 | switch (up->port.iotype) { | |
397 | case UPIO_HUB6: | |
398 | outb(up->port.hub6 - 1 + offset, up->port.iobase); | |
399 | outb(value, up->port.iobase + 1); | |
400 | break; | |
401 | ||
402 | case UPIO_MEM: | |
403 | writeb(value, up->port.membase + offset); | |
404 | break; | |
405 | ||
bd71c182 | 406 | case UPIO_RM9000: |
1da177e4 LT |
407 | case UPIO_MEM32: |
408 | writel(value, up->port.membase + offset); | |
409 | break; | |
410 | ||
21c614a7 PA |
411 | #ifdef CONFIG_SERIAL_8250_AU1X00 |
412 | case UPIO_AU: | |
413 | __raw_writel(value, up->port.membase + offset); | |
414 | break; | |
415 | #endif | |
3be91ec7 ZR |
416 | case UPIO_TSI: |
417 | if (!((offset == UART_IER) && (value & UART_IER_UUE))) | |
418 | writeb(value, up->port.membase + offset); | |
419 | break; | |
21c614a7 | 420 | |
beab697a MSJ |
421 | case UPIO_DWAPB: |
422 | /* Save the LCR value so it can be re-written when a | |
423 | * Busy Detect interrupt occurs. */ | |
424 | if (save_offset == UART_LCR) | |
425 | up->lcr = value; | |
426 | writeb(value, up->port.membase + offset); | |
427 | /* Read the IER to ensure any interrupt is cleared before | |
428 | * returning from ISR. */ | |
429 | if (save_offset == UART_TX || save_offset == UART_IER) | |
430 | value = serial_in(up, UART_IER); | |
431 | break; | |
432 | ||
1da177e4 LT |
433 | default: |
434 | outb(value, up->port.iobase + offset); | |
435 | } | |
436 | } | |
437 | ||
40b36daa AW |
438 | static void |
439 | serial_out_sync(struct uart_8250_port *up, int offset, int value) | |
440 | { | |
441 | switch (up->port.iotype) { | |
442 | case UPIO_MEM: | |
443 | case UPIO_MEM32: | |
444 | #ifdef CONFIG_SERIAL_8250_AU1X00 | |
445 | case UPIO_AU: | |
446 | #endif | |
beab697a | 447 | case UPIO_DWAPB: |
40b36daa AW |
448 | serial_out(up, offset, value); |
449 | serial_in(up, UART_LCR); /* safe, no side-effects */ | |
450 | break; | |
451 | default: | |
452 | serial_out(up, offset, value); | |
453 | } | |
454 | } | |
455 | ||
1da177e4 LT |
456 | /* |
457 | * We used to support using pause I/O for certain machines. We | |
458 | * haven't supported this for a while, but just in case it's badly | |
459 | * needed for certain old 386 machines, I've left these #define's | |
460 | * in.... | |
461 | */ | |
462 | #define serial_inp(up, offset) serial_in(up, offset) | |
463 | #define serial_outp(up, offset, value) serial_out(up, offset, value) | |
464 | ||
b32b19b8 JAH |
465 | /* Uart divisor latch read */ |
466 | static inline int _serial_dl_read(struct uart_8250_port *up) | |
467 | { | |
468 | return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8; | |
469 | } | |
470 | ||
471 | /* Uart divisor latch write */ | |
472 | static inline void _serial_dl_write(struct uart_8250_port *up, int value) | |
473 | { | |
474 | serial_outp(up, UART_DLL, value & 0xff); | |
475 | serial_outp(up, UART_DLM, value >> 8 & 0xff); | |
476 | } | |
477 | ||
6f803cd0 | 478 | #if defined(CONFIG_SERIAL_8250_AU1X00) |
b32b19b8 JAH |
479 | /* Au1x00 haven't got a standard divisor latch */ |
480 | static int serial_dl_read(struct uart_8250_port *up) | |
481 | { | |
482 | if (up->port.iotype == UPIO_AU) | |
483 | return __raw_readl(up->port.membase + 0x28); | |
484 | else | |
485 | return _serial_dl_read(up); | |
486 | } | |
487 | ||
488 | static void serial_dl_write(struct uart_8250_port *up, int value) | |
489 | { | |
490 | if (up->port.iotype == UPIO_AU) | |
491 | __raw_writel(value, up->port.membase + 0x28); | |
492 | else | |
493 | _serial_dl_write(up, value); | |
494 | } | |
6f803cd0 | 495 | #elif defined(CONFIG_SERIAL_8250_RM9K) |
bd71c182 TK |
496 | static int serial_dl_read(struct uart_8250_port *up) |
497 | { | |
498 | return (up->port.iotype == UPIO_RM9000) ? | |
499 | (((__raw_readl(up->port.membase + 0x10) << 8) | | |
500 | (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) : | |
501 | _serial_dl_read(up); | |
502 | } | |
503 | ||
504 | static void serial_dl_write(struct uart_8250_port *up, int value) | |
505 | { | |
506 | if (up->port.iotype == UPIO_RM9000) { | |
507 | __raw_writel(value, up->port.membase + 0x08); | |
508 | __raw_writel(value >> 8, up->port.membase + 0x10); | |
509 | } else { | |
510 | _serial_dl_write(up, value); | |
511 | } | |
512 | } | |
b32b19b8 JAH |
513 | #else |
514 | #define serial_dl_read(up) _serial_dl_read(up) | |
515 | #define serial_dl_write(up, value) _serial_dl_write(up, value) | |
516 | #endif | |
1da177e4 LT |
517 | |
518 | /* | |
519 | * For the 16C950 | |
520 | */ | |
521 | static void serial_icr_write(struct uart_8250_port *up, int offset, int value) | |
522 | { | |
523 | serial_out(up, UART_SCR, offset); | |
524 | serial_out(up, UART_ICR, value); | |
525 | } | |
526 | ||
527 | static unsigned int serial_icr_read(struct uart_8250_port *up, int offset) | |
528 | { | |
529 | unsigned int value; | |
530 | ||
531 | serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD); | |
532 | serial_out(up, UART_SCR, offset); | |
533 | value = serial_in(up, UART_ICR); | |
534 | serial_icr_write(up, UART_ACR, up->acr); | |
535 | ||
536 | return value; | |
537 | } | |
538 | ||
539 | /* | |
540 | * FIFO support. | |
541 | */ | |
542 | static inline void serial8250_clear_fifos(struct uart_8250_port *p) | |
543 | { | |
544 | if (p->capabilities & UART_CAP_FIFO) { | |
545 | serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO); | |
546 | serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO | | |
547 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); | |
548 | serial_outp(p, UART_FCR, 0); | |
549 | } | |
550 | } | |
551 | ||
552 | /* | |
553 | * IER sleep support. UARTs which have EFRs need the "extended | |
554 | * capability" bit enabled. Note that on XR16C850s, we need to | |
555 | * reset LCR to write to IER. | |
556 | */ | |
557 | static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep) | |
558 | { | |
559 | if (p->capabilities & UART_CAP_SLEEP) { | |
560 | if (p->capabilities & UART_CAP_EFR) { | |
561 | serial_outp(p, UART_LCR, 0xBF); | |
562 | serial_outp(p, UART_EFR, UART_EFR_ECB); | |
563 | serial_outp(p, UART_LCR, 0); | |
564 | } | |
565 | serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0); | |
566 | if (p->capabilities & UART_CAP_EFR) { | |
567 | serial_outp(p, UART_LCR, 0xBF); | |
568 | serial_outp(p, UART_EFR, 0); | |
569 | serial_outp(p, UART_LCR, 0); | |
570 | } | |
571 | } | |
572 | } | |
573 | ||
574 | #ifdef CONFIG_SERIAL_8250_RSA | |
575 | /* | |
576 | * Attempts to turn on the RSA FIFO. Returns zero on failure. | |
577 | * We set the port uart clock rate if we succeed. | |
578 | */ | |
579 | static int __enable_rsa(struct uart_8250_port *up) | |
580 | { | |
581 | unsigned char mode; | |
582 | int result; | |
583 | ||
584 | mode = serial_inp(up, UART_RSA_MSR); | |
585 | result = mode & UART_RSA_MSR_FIFO; | |
586 | ||
587 | if (!result) { | |
588 | serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO); | |
589 | mode = serial_inp(up, UART_RSA_MSR); | |
590 | result = mode & UART_RSA_MSR_FIFO; | |
591 | } | |
592 | ||
593 | if (result) | |
594 | up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16; | |
595 | ||
596 | return result; | |
597 | } | |
598 | ||
599 | static void enable_rsa(struct uart_8250_port *up) | |
600 | { | |
601 | if (up->port.type == PORT_RSA) { | |
602 | if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) { | |
603 | spin_lock_irq(&up->port.lock); | |
604 | __enable_rsa(up); | |
605 | spin_unlock_irq(&up->port.lock); | |
606 | } | |
607 | if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) | |
608 | serial_outp(up, UART_RSA_FRR, 0); | |
609 | } | |
610 | } | |
611 | ||
612 | /* | |
613 | * Attempts to turn off the RSA FIFO. Returns zero on failure. | |
614 | * It is unknown why interrupts were disabled in here. However, | |
615 | * the caller is expected to preserve this behaviour by grabbing | |
616 | * the spinlock before calling this function. | |
617 | */ | |
618 | static void disable_rsa(struct uart_8250_port *up) | |
619 | { | |
620 | unsigned char mode; | |
621 | int result; | |
622 | ||
623 | if (up->port.type == PORT_RSA && | |
624 | up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) { | |
625 | spin_lock_irq(&up->port.lock); | |
626 | ||
627 | mode = serial_inp(up, UART_RSA_MSR); | |
628 | result = !(mode & UART_RSA_MSR_FIFO); | |
629 | ||
630 | if (!result) { | |
631 | serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO); | |
632 | mode = serial_inp(up, UART_RSA_MSR); | |
633 | result = !(mode & UART_RSA_MSR_FIFO); | |
634 | } | |
635 | ||
636 | if (result) | |
637 | up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16; | |
638 | spin_unlock_irq(&up->port.lock); | |
639 | } | |
640 | } | |
641 | #endif /* CONFIG_SERIAL_8250_RSA */ | |
642 | ||
643 | /* | |
644 | * This is a quickie test to see how big the FIFO is. | |
645 | * It doesn't work at all the time, more's the pity. | |
646 | */ | |
647 | static int size_fifo(struct uart_8250_port *up) | |
648 | { | |
b32b19b8 JAH |
649 | unsigned char old_fcr, old_mcr, old_lcr; |
650 | unsigned short old_dl; | |
1da177e4 LT |
651 | int count; |
652 | ||
653 | old_lcr = serial_inp(up, UART_LCR); | |
654 | serial_outp(up, UART_LCR, 0); | |
655 | old_fcr = serial_inp(up, UART_FCR); | |
656 | old_mcr = serial_inp(up, UART_MCR); | |
657 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | | |
658 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); | |
659 | serial_outp(up, UART_MCR, UART_MCR_LOOP); | |
660 | serial_outp(up, UART_LCR, UART_LCR_DLAB); | |
b32b19b8 JAH |
661 | old_dl = serial_dl_read(up); |
662 | serial_dl_write(up, 0x0001); | |
1da177e4 LT |
663 | serial_outp(up, UART_LCR, 0x03); |
664 | for (count = 0; count < 256; count++) | |
665 | serial_outp(up, UART_TX, count); | |
666 | mdelay(20);/* FIXME - schedule_timeout */ | |
667 | for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) && | |
668 | (count < 256); count++) | |
669 | serial_inp(up, UART_RX); | |
670 | serial_outp(up, UART_FCR, old_fcr); | |
671 | serial_outp(up, UART_MCR, old_mcr); | |
672 | serial_outp(up, UART_LCR, UART_LCR_DLAB); | |
b32b19b8 | 673 | serial_dl_write(up, old_dl); |
1da177e4 LT |
674 | serial_outp(up, UART_LCR, old_lcr); |
675 | ||
676 | return count; | |
677 | } | |
678 | ||
679 | /* | |
680 | * Read UART ID using the divisor method - set DLL and DLM to zero | |
681 | * and the revision will be in DLL and device type in DLM. We | |
682 | * preserve the device state across this. | |
683 | */ | |
684 | static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p) | |
685 | { | |
686 | unsigned char old_dll, old_dlm, old_lcr; | |
687 | unsigned int id; | |
688 | ||
689 | old_lcr = serial_inp(p, UART_LCR); | |
690 | serial_outp(p, UART_LCR, UART_LCR_DLAB); | |
691 | ||
692 | old_dll = serial_inp(p, UART_DLL); | |
693 | old_dlm = serial_inp(p, UART_DLM); | |
694 | ||
695 | serial_outp(p, UART_DLL, 0); | |
696 | serial_outp(p, UART_DLM, 0); | |
697 | ||
698 | id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8; | |
699 | ||
700 | serial_outp(p, UART_DLL, old_dll); | |
701 | serial_outp(p, UART_DLM, old_dlm); | |
702 | serial_outp(p, UART_LCR, old_lcr); | |
703 | ||
704 | return id; | |
705 | } | |
706 | ||
707 | /* | |
708 | * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's. | |
709 | * When this function is called we know it is at least a StarTech | |
710 | * 16650 V2, but it might be one of several StarTech UARTs, or one of | |
711 | * its clones. (We treat the broken original StarTech 16650 V1 as a | |
712 | * 16550, and why not? Startech doesn't seem to even acknowledge its | |
713 | * existence.) | |
bd71c182 | 714 | * |
1da177e4 LT |
715 | * What evil have men's minds wrought... |
716 | */ | |
717 | static void autoconfig_has_efr(struct uart_8250_port *up) | |
718 | { | |
719 | unsigned int id1, id2, id3, rev; | |
720 | ||
721 | /* | |
722 | * Everything with an EFR has SLEEP | |
723 | */ | |
724 | up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; | |
725 | ||
726 | /* | |
727 | * First we check to see if it's an Oxford Semiconductor UART. | |
728 | * | |
729 | * If we have to do this here because some non-National | |
730 | * Semiconductor clone chips lock up if you try writing to the | |
731 | * LSR register (which serial_icr_read does) | |
732 | */ | |
733 | ||
734 | /* | |
735 | * Check for Oxford Semiconductor 16C950. | |
736 | * | |
737 | * EFR [4] must be set else this test fails. | |
738 | * | |
739 | * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca) | |
740 | * claims that it's needed for 952 dual UART's (which are not | |
741 | * recommended for new designs). | |
742 | */ | |
743 | up->acr = 0; | |
744 | serial_out(up, UART_LCR, 0xBF); | |
745 | serial_out(up, UART_EFR, UART_EFR_ECB); | |
746 | serial_out(up, UART_LCR, 0x00); | |
747 | id1 = serial_icr_read(up, UART_ID1); | |
748 | id2 = serial_icr_read(up, UART_ID2); | |
749 | id3 = serial_icr_read(up, UART_ID3); | |
750 | rev = serial_icr_read(up, UART_REV); | |
751 | ||
752 | DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev); | |
753 | ||
754 | if (id1 == 0x16 && id2 == 0xC9 && | |
755 | (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) { | |
756 | up->port.type = PORT_16C950; | |
4ba5e35d RK |
757 | |
758 | /* | |
759 | * Enable work around for the Oxford Semiconductor 952 rev B | |
760 | * chip which causes it to seriously miscalculate baud rates | |
761 | * when DLL is 0. | |
762 | */ | |
763 | if (id3 == 0x52 && rev == 0x01) | |
764 | up->bugs |= UART_BUG_QUOT; | |
1da177e4 LT |
765 | return; |
766 | } | |
bd71c182 | 767 | |
1da177e4 LT |
768 | /* |
769 | * We check for a XR16C850 by setting DLL and DLM to 0, and then | |
770 | * reading back DLL and DLM. The chip type depends on the DLM | |
771 | * value read back: | |
772 | * 0x10 - XR16C850 and the DLL contains the chip revision. | |
773 | * 0x12 - XR16C2850. | |
774 | * 0x14 - XR16C854. | |
775 | */ | |
776 | id1 = autoconfig_read_divisor_id(up); | |
777 | DEBUG_AUTOCONF("850id=%04x ", id1); | |
778 | ||
779 | id2 = id1 >> 8; | |
780 | if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) { | |
1da177e4 LT |
781 | up->port.type = PORT_16850; |
782 | return; | |
783 | } | |
784 | ||
785 | /* | |
786 | * It wasn't an XR16C850. | |
787 | * | |
788 | * We distinguish between the '654 and the '650 by counting | |
789 | * how many bytes are in the FIFO. I'm using this for now, | |
790 | * since that's the technique that was sent to me in the | |
791 | * serial driver update, but I'm not convinced this works. | |
792 | * I've had problems doing this in the past. -TYT | |
793 | */ | |
794 | if (size_fifo(up) == 64) | |
795 | up->port.type = PORT_16654; | |
796 | else | |
797 | up->port.type = PORT_16650V2; | |
798 | } | |
799 | ||
800 | /* | |
801 | * We detected a chip without a FIFO. Only two fall into | |
802 | * this category - the original 8250 and the 16450. The | |
803 | * 16450 has a scratch register (accessible with LCR=0) | |
804 | */ | |
805 | static void autoconfig_8250(struct uart_8250_port *up) | |
806 | { | |
807 | unsigned char scratch, status1, status2; | |
808 | ||
809 | up->port.type = PORT_8250; | |
810 | ||
811 | scratch = serial_in(up, UART_SCR); | |
812 | serial_outp(up, UART_SCR, 0xa5); | |
813 | status1 = serial_in(up, UART_SCR); | |
814 | serial_outp(up, UART_SCR, 0x5a); | |
815 | status2 = serial_in(up, UART_SCR); | |
816 | serial_outp(up, UART_SCR, scratch); | |
817 | ||
818 | if (status1 == 0xa5 && status2 == 0x5a) | |
819 | up->port.type = PORT_16450; | |
820 | } | |
821 | ||
822 | static int broken_efr(struct uart_8250_port *up) | |
823 | { | |
824 | /* | |
825 | * Exar ST16C2550 "A2" devices incorrectly detect as | |
826 | * having an EFR, and report an ID of 0x0201. See | |
827 | * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf | |
828 | */ | |
829 | if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16) | |
830 | return 1; | |
831 | ||
832 | return 0; | |
833 | } | |
834 | ||
835 | /* | |
836 | * We know that the chip has FIFOs. Does it have an EFR? The | |
837 | * EFR is located in the same register position as the IIR and | |
838 | * we know the top two bits of the IIR are currently set. The | |
839 | * EFR should contain zero. Try to read the EFR. | |
840 | */ | |
841 | static void autoconfig_16550a(struct uart_8250_port *up) | |
842 | { | |
843 | unsigned char status1, status2; | |
844 | unsigned int iersave; | |
845 | ||
846 | up->port.type = PORT_16550A; | |
847 | up->capabilities |= UART_CAP_FIFO; | |
848 | ||
849 | /* | |
850 | * Check for presence of the EFR when DLAB is set. | |
851 | * Only ST16C650V1 UARTs pass this test. | |
852 | */ | |
853 | serial_outp(up, UART_LCR, UART_LCR_DLAB); | |
854 | if (serial_in(up, UART_EFR) == 0) { | |
855 | serial_outp(up, UART_EFR, 0xA8); | |
856 | if (serial_in(up, UART_EFR) != 0) { | |
857 | DEBUG_AUTOCONF("EFRv1 "); | |
858 | up->port.type = PORT_16650; | |
859 | up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; | |
860 | } else { | |
861 | DEBUG_AUTOCONF("Motorola 8xxx DUART "); | |
862 | } | |
863 | serial_outp(up, UART_EFR, 0); | |
864 | return; | |
865 | } | |
866 | ||
867 | /* | |
868 | * Maybe it requires 0xbf to be written to the LCR. | |
869 | * (other ST16C650V2 UARTs, TI16C752A, etc) | |
870 | */ | |
871 | serial_outp(up, UART_LCR, 0xBF); | |
872 | if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) { | |
873 | DEBUG_AUTOCONF("EFRv2 "); | |
874 | autoconfig_has_efr(up); | |
875 | return; | |
876 | } | |
877 | ||
878 | /* | |
879 | * Check for a National Semiconductor SuperIO chip. | |
880 | * Attempt to switch to bank 2, read the value of the LOOP bit | |
881 | * from EXCR1. Switch back to bank 0, change it in MCR. Then | |
882 | * switch back to bank 2, read it from EXCR1 again and check | |
883 | * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2 | |
1da177e4 LT |
884 | */ |
885 | serial_outp(up, UART_LCR, 0); | |
886 | status1 = serial_in(up, UART_MCR); | |
887 | serial_outp(up, UART_LCR, 0xE0); | |
888 | status2 = serial_in(up, 0x02); /* EXCR1 */ | |
889 | ||
890 | if (!((status2 ^ status1) & UART_MCR_LOOP)) { | |
891 | serial_outp(up, UART_LCR, 0); | |
892 | serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP); | |
893 | serial_outp(up, UART_LCR, 0xE0); | |
894 | status2 = serial_in(up, 0x02); /* EXCR1 */ | |
895 | serial_outp(up, UART_LCR, 0); | |
896 | serial_outp(up, UART_MCR, status1); | |
897 | ||
898 | if ((status2 ^ status1) & UART_MCR_LOOP) { | |
857dde2e DW |
899 | unsigned short quot; |
900 | ||
1da177e4 | 901 | serial_outp(up, UART_LCR, 0xE0); |
857dde2e | 902 | |
b32b19b8 | 903 | quot = serial_dl_read(up); |
857dde2e DW |
904 | quot <<= 3; |
905 | ||
b5b82df6 | 906 | status1 = serial_in(up, 0x04); /* EXCR2 */ |
1da177e4 LT |
907 | status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */ |
908 | status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */ | |
909 | serial_outp(up, 0x04, status1); | |
bd71c182 | 910 | |
b32b19b8 | 911 | serial_dl_write(up, quot); |
857dde2e | 912 | |
1da177e4 | 913 | serial_outp(up, UART_LCR, 0); |
1da177e4 | 914 | |
857dde2e | 915 | up->port.uartclk = 921600*16; |
1da177e4 LT |
916 | up->port.type = PORT_NS16550A; |
917 | up->capabilities |= UART_NATSEMI; | |
918 | return; | |
919 | } | |
920 | } | |
921 | ||
922 | /* | |
923 | * No EFR. Try to detect a TI16750, which only sets bit 5 of | |
924 | * the IIR when 64 byte FIFO mode is enabled when DLAB is set. | |
925 | * Try setting it with and without DLAB set. Cheap clones | |
926 | * set bit 5 without DLAB set. | |
927 | */ | |
928 | serial_outp(up, UART_LCR, 0); | |
929 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); | |
930 | status1 = serial_in(up, UART_IIR) >> 5; | |
931 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
932 | serial_outp(up, UART_LCR, UART_LCR_DLAB); | |
933 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); | |
934 | status2 = serial_in(up, UART_IIR) >> 5; | |
935 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
936 | serial_outp(up, UART_LCR, 0); | |
937 | ||
938 | DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2); | |
939 | ||
940 | if (status1 == 6 && status2 == 7) { | |
941 | up->port.type = PORT_16750; | |
942 | up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP; | |
943 | return; | |
944 | } | |
945 | ||
946 | /* | |
947 | * Try writing and reading the UART_IER_UUE bit (b6). | |
948 | * If it works, this is probably one of the Xscale platform's | |
949 | * internal UARTs. | |
950 | * We're going to explicitly set the UUE bit to 0 before | |
951 | * trying to write and read a 1 just to make sure it's not | |
952 | * already a 1 and maybe locked there before we even start start. | |
953 | */ | |
954 | iersave = serial_in(up, UART_IER); | |
955 | serial_outp(up, UART_IER, iersave & ~UART_IER_UUE); | |
956 | if (!(serial_in(up, UART_IER) & UART_IER_UUE)) { | |
957 | /* | |
958 | * OK it's in a known zero state, try writing and reading | |
959 | * without disturbing the current state of the other bits. | |
960 | */ | |
961 | serial_outp(up, UART_IER, iersave | UART_IER_UUE); | |
962 | if (serial_in(up, UART_IER) & UART_IER_UUE) { | |
963 | /* | |
964 | * It's an Xscale. | |
965 | * We'll leave the UART_IER_UUE bit set to 1 (enabled). | |
966 | */ | |
967 | DEBUG_AUTOCONF("Xscale "); | |
968 | up->port.type = PORT_XSCALE; | |
969 | up->capabilities |= UART_CAP_UUE; | |
970 | return; | |
971 | } | |
972 | } else { | |
973 | /* | |
974 | * If we got here we couldn't force the IER_UUE bit to 0. | |
975 | * Log it and continue. | |
976 | */ | |
977 | DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 "); | |
978 | } | |
979 | serial_outp(up, UART_IER, iersave); | |
980 | } | |
981 | ||
982 | /* | |
983 | * This routine is called by rs_init() to initialize a specific serial | |
984 | * port. It determines what type of UART chip this serial port is | |
985 | * using: 8250, 16450, 16550, 16550A. The important question is | |
986 | * whether or not this UART is a 16550A or not, since this will | |
987 | * determine whether or not we can use its FIFO features or not. | |
988 | */ | |
989 | static void autoconfig(struct uart_8250_port *up, unsigned int probeflags) | |
990 | { | |
991 | unsigned char status1, scratch, scratch2, scratch3; | |
992 | unsigned char save_lcr, save_mcr; | |
993 | unsigned long flags; | |
994 | ||
995 | if (!up->port.iobase && !up->port.mapbase && !up->port.membase) | |
996 | return; | |
997 | ||
998 | DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ", | |
999 | up->port.line, up->port.iobase, up->port.membase); | |
1000 | ||
1001 | /* | |
1002 | * We really do need global IRQs disabled here - we're going to | |
1003 | * be frobbing the chips IRQ enable register to see if it exists. | |
1004 | */ | |
1005 | spin_lock_irqsave(&up->port.lock, flags); | |
1da177e4 LT |
1006 | |
1007 | up->capabilities = 0; | |
4ba5e35d | 1008 | up->bugs = 0; |
1da177e4 LT |
1009 | |
1010 | if (!(up->port.flags & UPF_BUGGY_UART)) { | |
1011 | /* | |
1012 | * Do a simple existence test first; if we fail this, | |
1013 | * there's no point trying anything else. | |
bd71c182 | 1014 | * |
1da177e4 LT |
1015 | * 0x80 is used as a nonsense port to prevent against |
1016 | * false positives due to ISA bus float. The | |
1017 | * assumption is that 0x80 is a non-existent port; | |
1018 | * which should be safe since include/asm/io.h also | |
1019 | * makes this assumption. | |
1020 | * | |
1021 | * Note: this is safe as long as MCR bit 4 is clear | |
1022 | * and the device is in "PC" mode. | |
1023 | */ | |
1024 | scratch = serial_inp(up, UART_IER); | |
1025 | serial_outp(up, UART_IER, 0); | |
1026 | #ifdef __i386__ | |
1027 | outb(0xff, 0x080); | |
1028 | #endif | |
48212008 TH |
1029 | /* |
1030 | * Mask out IER[7:4] bits for test as some UARTs (e.g. TL | |
1031 | * 16C754B) allow only to modify them if an EFR bit is set. | |
1032 | */ | |
1033 | scratch2 = serial_inp(up, UART_IER) & 0x0f; | |
1da177e4 LT |
1034 | serial_outp(up, UART_IER, 0x0F); |
1035 | #ifdef __i386__ | |
1036 | outb(0, 0x080); | |
1037 | #endif | |
48212008 | 1038 | scratch3 = serial_inp(up, UART_IER) & 0x0f; |
1da177e4 LT |
1039 | serial_outp(up, UART_IER, scratch); |
1040 | if (scratch2 != 0 || scratch3 != 0x0F) { | |
1041 | /* | |
1042 | * We failed; there's nothing here | |
1043 | */ | |
1044 | DEBUG_AUTOCONF("IER test failed (%02x, %02x) ", | |
1045 | scratch2, scratch3); | |
1046 | goto out; | |
1047 | } | |
1048 | } | |
1049 | ||
1050 | save_mcr = serial_in(up, UART_MCR); | |
1051 | save_lcr = serial_in(up, UART_LCR); | |
1052 | ||
bd71c182 | 1053 | /* |
1da177e4 LT |
1054 | * Check to see if a UART is really there. Certain broken |
1055 | * internal modems based on the Rockwell chipset fail this | |
1056 | * test, because they apparently don't implement the loopback | |
1057 | * test mode. So this test is skipped on the COM 1 through | |
1058 | * COM 4 ports. This *should* be safe, since no board | |
1059 | * manufacturer would be stupid enough to design a board | |
1060 | * that conflicts with COM 1-4 --- we hope! | |
1061 | */ | |
1062 | if (!(up->port.flags & UPF_SKIP_TEST)) { | |
1063 | serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A); | |
1064 | status1 = serial_inp(up, UART_MSR) & 0xF0; | |
1065 | serial_outp(up, UART_MCR, save_mcr); | |
1066 | if (status1 != 0x90) { | |
1067 | DEBUG_AUTOCONF("LOOP test failed (%02x) ", | |
1068 | status1); | |
1069 | goto out; | |
1070 | } | |
1071 | } | |
1072 | ||
1073 | /* | |
1074 | * We're pretty sure there's a port here. Lets find out what | |
1075 | * type of port it is. The IIR top two bits allows us to find | |
6f0d618f | 1076 | * out if it's 8250 or 16450, 16550, 16550A or later. This |
1da177e4 LT |
1077 | * determines what we test for next. |
1078 | * | |
1079 | * We also initialise the EFR (if any) to zero for later. The | |
1080 | * EFR occupies the same register location as the FCR and IIR. | |
1081 | */ | |
1082 | serial_outp(up, UART_LCR, 0xBF); | |
1083 | serial_outp(up, UART_EFR, 0); | |
1084 | serial_outp(up, UART_LCR, 0); | |
1085 | ||
1086 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
1087 | scratch = serial_in(up, UART_IIR) >> 6; | |
1088 | ||
1089 | DEBUG_AUTOCONF("iir=%d ", scratch); | |
1090 | ||
1091 | switch (scratch) { | |
1092 | case 0: | |
1093 | autoconfig_8250(up); | |
1094 | break; | |
1095 | case 1: | |
1096 | up->port.type = PORT_UNKNOWN; | |
1097 | break; | |
1098 | case 2: | |
1099 | up->port.type = PORT_16550; | |
1100 | break; | |
1101 | case 3: | |
1102 | autoconfig_16550a(up); | |
1103 | break; | |
1104 | } | |
1105 | ||
1106 | #ifdef CONFIG_SERIAL_8250_RSA | |
1107 | /* | |
1108 | * Only probe for RSA ports if we got the region. | |
1109 | */ | |
1110 | if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) { | |
1111 | int i; | |
1112 | ||
1113 | for (i = 0 ; i < probe_rsa_count; ++i) { | |
1114 | if (probe_rsa[i] == up->port.iobase && | |
1115 | __enable_rsa(up)) { | |
1116 | up->port.type = PORT_RSA; | |
1117 | break; | |
1118 | } | |
1119 | } | |
1120 | } | |
1121 | #endif | |
21c614a7 PA |
1122 | |
1123 | #ifdef CONFIG_SERIAL_8250_AU1X00 | |
1124 | /* if access method is AU, it is a 16550 with a quirk */ | |
1125 | if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU) | |
1126 | up->bugs |= UART_BUG_NOMSR; | |
1127 | #endif | |
1128 | ||
1da177e4 LT |
1129 | serial_outp(up, UART_LCR, save_lcr); |
1130 | ||
1131 | if (up->capabilities != uart_config[up->port.type].flags) { | |
1132 | printk(KERN_WARNING | |
1133 | "ttyS%d: detected caps %08x should be %08x\n", | |
1134 | up->port.line, up->capabilities, | |
1135 | uart_config[up->port.type].flags); | |
1136 | } | |
1137 | ||
1138 | up->port.fifosize = uart_config[up->port.type].fifo_size; | |
1139 | up->capabilities = uart_config[up->port.type].flags; | |
1140 | up->tx_loadsz = uart_config[up->port.type].tx_loadsz; | |
1141 | ||
1142 | if (up->port.type == PORT_UNKNOWN) | |
1143 | goto out; | |
1144 | ||
1145 | /* | |
1146 | * Reset the UART. | |
1147 | */ | |
1148 | #ifdef CONFIG_SERIAL_8250_RSA | |
1149 | if (up->port.type == PORT_RSA) | |
1150 | serial_outp(up, UART_RSA_FRR, 0); | |
1151 | #endif | |
1152 | serial_outp(up, UART_MCR, save_mcr); | |
1153 | serial8250_clear_fifos(up); | |
40b36daa | 1154 | serial_in(up, UART_RX); |
5c8c755c LB |
1155 | if (up->capabilities & UART_CAP_UUE) |
1156 | serial_outp(up, UART_IER, UART_IER_UUE); | |
1157 | else | |
1158 | serial_outp(up, UART_IER, 0); | |
1da177e4 | 1159 | |
bd71c182 | 1160 | out: |
1da177e4 | 1161 | spin_unlock_irqrestore(&up->port.lock, flags); |
1da177e4 LT |
1162 | DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name); |
1163 | } | |
1164 | ||
1165 | static void autoconfig_irq(struct uart_8250_port *up) | |
1166 | { | |
1167 | unsigned char save_mcr, save_ier; | |
1168 | unsigned char save_ICP = 0; | |
1169 | unsigned int ICP = 0; | |
1170 | unsigned long irqs; | |
1171 | int irq; | |
1172 | ||
1173 | if (up->port.flags & UPF_FOURPORT) { | |
1174 | ICP = (up->port.iobase & 0xfe0) | 0x1f; | |
1175 | save_ICP = inb_p(ICP); | |
1176 | outb_p(0x80, ICP); | |
1177 | (void) inb_p(ICP); | |
1178 | } | |
1179 | ||
1180 | /* forget possible initially masked and pending IRQ */ | |
1181 | probe_irq_off(probe_irq_on()); | |
1182 | save_mcr = serial_inp(up, UART_MCR); | |
1183 | save_ier = serial_inp(up, UART_IER); | |
1184 | serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2); | |
bd71c182 | 1185 | |
1da177e4 LT |
1186 | irqs = probe_irq_on(); |
1187 | serial_outp(up, UART_MCR, 0); | |
6f803cd0 AC |
1188 | udelay(10); |
1189 | if (up->port.flags & UPF_FOURPORT) { | |
1da177e4 LT |
1190 | serial_outp(up, UART_MCR, |
1191 | UART_MCR_DTR | UART_MCR_RTS); | |
1192 | } else { | |
1193 | serial_outp(up, UART_MCR, | |
1194 | UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2); | |
1195 | } | |
1196 | serial_outp(up, UART_IER, 0x0f); /* enable all intrs */ | |
1197 | (void)serial_inp(up, UART_LSR); | |
1198 | (void)serial_inp(up, UART_RX); | |
1199 | (void)serial_inp(up, UART_IIR); | |
1200 | (void)serial_inp(up, UART_MSR); | |
1201 | serial_outp(up, UART_TX, 0xFF); | |
6f803cd0 | 1202 | udelay(20); |
1da177e4 LT |
1203 | irq = probe_irq_off(irqs); |
1204 | ||
1205 | serial_outp(up, UART_MCR, save_mcr); | |
1206 | serial_outp(up, UART_IER, save_ier); | |
1207 | ||
1208 | if (up->port.flags & UPF_FOURPORT) | |
1209 | outb_p(save_ICP, ICP); | |
1210 | ||
1211 | up->port.irq = (irq > 0) ? irq : 0; | |
1212 | } | |
1213 | ||
e763b90c RK |
1214 | static inline void __stop_tx(struct uart_8250_port *p) |
1215 | { | |
1216 | if (p->ier & UART_IER_THRI) { | |
1217 | p->ier &= ~UART_IER_THRI; | |
1218 | serial_out(p, UART_IER, p->ier); | |
1219 | } | |
1220 | } | |
1221 | ||
b129a8cc | 1222 | static void serial8250_stop_tx(struct uart_port *port) |
1da177e4 LT |
1223 | { |
1224 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1225 | ||
e763b90c | 1226 | __stop_tx(up); |
1da177e4 LT |
1227 | |
1228 | /* | |
e763b90c | 1229 | * We really want to stop the transmitter from sending. |
1da177e4 | 1230 | */ |
e763b90c | 1231 | if (up->port.type == PORT_16C950) { |
1da177e4 LT |
1232 | up->acr |= UART_ACR_TXDIS; |
1233 | serial_icr_write(up, UART_ACR, up->acr); | |
1234 | } | |
1235 | } | |
1236 | ||
55d3b282 RK |
1237 | static void transmit_chars(struct uart_8250_port *up); |
1238 | ||
b129a8cc | 1239 | static void serial8250_start_tx(struct uart_port *port) |
1da177e4 LT |
1240 | { |
1241 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1242 | ||
1243 | if (!(up->ier & UART_IER_THRI)) { | |
1244 | up->ier |= UART_IER_THRI; | |
1245 | serial_out(up, UART_IER, up->ier); | |
55d3b282 | 1246 | |
67f7654e | 1247 | if (up->bugs & UART_BUG_TXEN) { |
55d3b282 RK |
1248 | unsigned char lsr, iir; |
1249 | lsr = serial_in(up, UART_LSR); | |
ad4c2aa6 | 1250 | up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; |
bd71c182 TK |
1251 | iir = serial_in(up, UART_IIR) & 0x0f; |
1252 | if ((up->port.type == PORT_RM9000) ? | |
1253 | (lsr & UART_LSR_THRE && | |
1254 | (iir == UART_IIR_NO_INT || iir == UART_IIR_THRI)) : | |
1255 | (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT)) | |
55d3b282 RK |
1256 | transmit_chars(up); |
1257 | } | |
1da177e4 | 1258 | } |
e763b90c | 1259 | |
1da177e4 | 1260 | /* |
e763b90c | 1261 | * Re-enable the transmitter if we disabled it. |
1da177e4 | 1262 | */ |
e763b90c | 1263 | if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) { |
1da177e4 LT |
1264 | up->acr &= ~UART_ACR_TXDIS; |
1265 | serial_icr_write(up, UART_ACR, up->acr); | |
1266 | } | |
1267 | } | |
1268 | ||
1269 | static void serial8250_stop_rx(struct uart_port *port) | |
1270 | { | |
1271 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1272 | ||
1273 | up->ier &= ~UART_IER_RLSI; | |
1274 | up->port.read_status_mask &= ~UART_LSR_DR; | |
1275 | serial_out(up, UART_IER, up->ier); | |
1276 | } | |
1277 | ||
1278 | static void serial8250_enable_ms(struct uart_port *port) | |
1279 | { | |
1280 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1281 | ||
21c614a7 PA |
1282 | /* no MSR capabilities */ |
1283 | if (up->bugs & UART_BUG_NOMSR) | |
1284 | return; | |
1285 | ||
1da177e4 LT |
1286 | up->ier |= UART_IER_MSI; |
1287 | serial_out(up, UART_IER, up->ier); | |
1288 | } | |
1289 | ||
ea8874dc | 1290 | static void |
cc79aa9d | 1291 | receive_chars(struct uart_8250_port *up, unsigned int *status) |
1da177e4 LT |
1292 | { |
1293 | struct tty_struct *tty = up->port.info->tty; | |
1294 | unsigned char ch, lsr = *status; | |
1295 | int max_count = 256; | |
1296 | char flag; | |
1297 | ||
1298 | do { | |
1da177e4 LT |
1299 | ch = serial_inp(up, UART_RX); |
1300 | flag = TTY_NORMAL; | |
1301 | up->port.icount.rx++; | |
1302 | ||
ad4c2aa6 CM |
1303 | lsr |= up->lsr_saved_flags; |
1304 | up->lsr_saved_flags = 0; | |
1da177e4 | 1305 | |
ad4c2aa6 | 1306 | if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) { |
1da177e4 LT |
1307 | /* |
1308 | * For statistics only | |
1309 | */ | |
1310 | if (lsr & UART_LSR_BI) { | |
1311 | lsr &= ~(UART_LSR_FE | UART_LSR_PE); | |
1312 | up->port.icount.brk++; | |
1313 | /* | |
1314 | * We do the SysRQ and SAK checking | |
1315 | * here because otherwise the break | |
1316 | * may get masked by ignore_status_mask | |
1317 | * or read_status_mask. | |
1318 | */ | |
1319 | if (uart_handle_break(&up->port)) | |
1320 | goto ignore_char; | |
1321 | } else if (lsr & UART_LSR_PE) | |
1322 | up->port.icount.parity++; | |
1323 | else if (lsr & UART_LSR_FE) | |
1324 | up->port.icount.frame++; | |
1325 | if (lsr & UART_LSR_OE) | |
1326 | up->port.icount.overrun++; | |
1327 | ||
1328 | /* | |
23907eb8 | 1329 | * Mask off conditions which should be ignored. |
1da177e4 LT |
1330 | */ |
1331 | lsr &= up->port.read_status_mask; | |
1332 | ||
1333 | if (lsr & UART_LSR_BI) { | |
1334 | DEBUG_INTR("handling break...."); | |
1335 | flag = TTY_BREAK; | |
1336 | } else if (lsr & UART_LSR_PE) | |
1337 | flag = TTY_PARITY; | |
1338 | else if (lsr & UART_LSR_FE) | |
1339 | flag = TTY_FRAME; | |
1340 | } | |
7d12e780 | 1341 | if (uart_handle_sysrq_char(&up->port, ch)) |
1da177e4 | 1342 | goto ignore_char; |
05ab3014 RK |
1343 | |
1344 | uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag); | |
1345 | ||
6f803cd0 | 1346 | ignore_char: |
1da177e4 LT |
1347 | lsr = serial_inp(up, UART_LSR); |
1348 | } while ((lsr & UART_LSR_DR) && (max_count-- > 0)); | |
1349 | spin_unlock(&up->port.lock); | |
1350 | tty_flip_buffer_push(tty); | |
1351 | spin_lock(&up->port.lock); | |
1352 | *status = lsr; | |
1353 | } | |
1354 | ||
ea8874dc | 1355 | static void transmit_chars(struct uart_8250_port *up) |
1da177e4 LT |
1356 | { |
1357 | struct circ_buf *xmit = &up->port.info->xmit; | |
1358 | int count; | |
1359 | ||
1360 | if (up->port.x_char) { | |
1361 | serial_outp(up, UART_TX, up->port.x_char); | |
1362 | up->port.icount.tx++; | |
1363 | up->port.x_char = 0; | |
1364 | return; | |
1365 | } | |
b129a8cc RK |
1366 | if (uart_tx_stopped(&up->port)) { |
1367 | serial8250_stop_tx(&up->port); | |
1368 | return; | |
1369 | } | |
1370 | if (uart_circ_empty(xmit)) { | |
e763b90c | 1371 | __stop_tx(up); |
1da177e4 LT |
1372 | return; |
1373 | } | |
1374 | ||
1375 | count = up->tx_loadsz; | |
1376 | do { | |
1377 | serial_out(up, UART_TX, xmit->buf[xmit->tail]); | |
1378 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
1379 | up->port.icount.tx++; | |
1380 | if (uart_circ_empty(xmit)) | |
1381 | break; | |
1382 | } while (--count > 0); | |
1383 | ||
1384 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
1385 | uart_write_wakeup(&up->port); | |
1386 | ||
1387 | DEBUG_INTR("THRE..."); | |
1388 | ||
1389 | if (uart_circ_empty(xmit)) | |
e763b90c | 1390 | __stop_tx(up); |
1da177e4 LT |
1391 | } |
1392 | ||
2af7cd68 | 1393 | static unsigned int check_modem_status(struct uart_8250_port *up) |
1da177e4 | 1394 | { |
2af7cd68 RK |
1395 | unsigned int status = serial_in(up, UART_MSR); |
1396 | ||
ad4c2aa6 CM |
1397 | status |= up->msr_saved_flags; |
1398 | up->msr_saved_flags = 0; | |
fdc30b3d TI |
1399 | if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && |
1400 | up->port.info != NULL) { | |
2af7cd68 RK |
1401 | if (status & UART_MSR_TERI) |
1402 | up->port.icount.rng++; | |
1403 | if (status & UART_MSR_DDSR) | |
1404 | up->port.icount.dsr++; | |
1405 | if (status & UART_MSR_DDCD) | |
1406 | uart_handle_dcd_change(&up->port, status & UART_MSR_DCD); | |
1407 | if (status & UART_MSR_DCTS) | |
1408 | uart_handle_cts_change(&up->port, status & UART_MSR_CTS); | |
1409 | ||
1410 | wake_up_interruptible(&up->port.info->delta_msr_wait); | |
1411 | } | |
1da177e4 | 1412 | |
2af7cd68 | 1413 | return status; |
1da177e4 LT |
1414 | } |
1415 | ||
1416 | /* | |
1417 | * This handles the interrupt from one port. | |
1418 | */ | |
1419 | static inline void | |
7d12e780 | 1420 | serial8250_handle_port(struct uart_8250_port *up) |
1da177e4 | 1421 | { |
45e24601 | 1422 | unsigned int status; |
4bf3631c | 1423 | unsigned long flags; |
45e24601 | 1424 | |
4bf3631c | 1425 | spin_lock_irqsave(&up->port.lock, flags); |
45e24601 RK |
1426 | |
1427 | status = serial_inp(up, UART_LSR); | |
1da177e4 LT |
1428 | |
1429 | DEBUG_INTR("status = %x...", status); | |
1430 | ||
1431 | if (status & UART_LSR_DR) | |
7d12e780 | 1432 | receive_chars(up, &status); |
1da177e4 LT |
1433 | check_modem_status(up); |
1434 | if (status & UART_LSR_THRE) | |
1435 | transmit_chars(up); | |
45e24601 | 1436 | |
4bf3631c | 1437 | spin_unlock_irqrestore(&up->port.lock, flags); |
1da177e4 LT |
1438 | } |
1439 | ||
1440 | /* | |
1441 | * This is the serial driver's interrupt routine. | |
1442 | * | |
1443 | * Arjan thinks the old way was overly complex, so it got simplified. | |
1444 | * Alan disagrees, saying that need the complexity to handle the weird | |
1445 | * nature of ISA shared interrupts. (This is a special exception.) | |
1446 | * | |
1447 | * In order to handle ISA shared interrupts properly, we need to check | |
1448 | * that all ports have been serviced, and therefore the ISA interrupt | |
1449 | * line has been de-asserted. | |
1450 | * | |
1451 | * This means we need to loop through all ports. checking that they | |
1452 | * don't have an interrupt pending. | |
1453 | */ | |
7d12e780 | 1454 | static irqreturn_t serial8250_interrupt(int irq, void *dev_id) |
1da177e4 LT |
1455 | { |
1456 | struct irq_info *i = dev_id; | |
1457 | struct list_head *l, *end = NULL; | |
1458 | int pass_counter = 0, handled = 0; | |
1459 | ||
1460 | DEBUG_INTR("serial8250_interrupt(%d)...", irq); | |
1461 | ||
1462 | spin_lock(&i->lock); | |
1463 | ||
1464 | l = i->head; | |
1465 | do { | |
1466 | struct uart_8250_port *up; | |
1467 | unsigned int iir; | |
1468 | ||
1469 | up = list_entry(l, struct uart_8250_port, list); | |
1470 | ||
1471 | iir = serial_in(up, UART_IIR); | |
1472 | if (!(iir & UART_IIR_NO_INT)) { | |
7d12e780 | 1473 | serial8250_handle_port(up); |
1da177e4 LT |
1474 | |
1475 | handled = 1; | |
1476 | ||
beab697a MSJ |
1477 | end = NULL; |
1478 | } else if (up->port.iotype == UPIO_DWAPB && | |
1479 | (iir & UART_IIR_BUSY) == UART_IIR_BUSY) { | |
1480 | /* The DesignWare APB UART has an Busy Detect (0x07) | |
1481 | * interrupt meaning an LCR write attempt occured while the | |
1482 | * UART was busy. The interrupt must be cleared by reading | |
1483 | * the UART status register (USR) and the LCR re-written. */ | |
1484 | unsigned int status; | |
1485 | status = *(volatile u32 *)up->port.private_data; | |
1486 | serial_out(up, UART_LCR, up->lcr); | |
1487 | ||
1488 | handled = 1; | |
1489 | ||
1da177e4 LT |
1490 | end = NULL; |
1491 | } else if (end == NULL) | |
1492 | end = l; | |
1493 | ||
1494 | l = l->next; | |
1495 | ||
1496 | if (l == i->head && pass_counter++ > PASS_LIMIT) { | |
1497 | /* If we hit this, we're dead. */ | |
1498 | printk(KERN_ERR "serial8250: too much work for " | |
1499 | "irq%d\n", irq); | |
1500 | break; | |
1501 | } | |
1502 | } while (l != end); | |
1503 | ||
1504 | spin_unlock(&i->lock); | |
1505 | ||
1506 | DEBUG_INTR("end.\n"); | |
1507 | ||
1508 | return IRQ_RETVAL(handled); | |
1509 | } | |
1510 | ||
1511 | /* | |
1512 | * To support ISA shared interrupts, we need to have one interrupt | |
1513 | * handler that ensures that the IRQ line has been deasserted | |
1514 | * before returning. Failing to do this will result in the IRQ | |
1515 | * line being stuck active, and, since ISA irqs are edge triggered, | |
1516 | * no more IRQs will be seen. | |
1517 | */ | |
1518 | static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up) | |
1519 | { | |
1520 | spin_lock_irq(&i->lock); | |
1521 | ||
1522 | if (!list_empty(i->head)) { | |
1523 | if (i->head == &up->list) | |
1524 | i->head = i->head->next; | |
1525 | list_del(&up->list); | |
1526 | } else { | |
1527 | BUG_ON(i->head != &up->list); | |
1528 | i->head = NULL; | |
1529 | } | |
1530 | ||
1531 | spin_unlock_irq(&i->lock); | |
1532 | } | |
1533 | ||
1534 | static int serial_link_irq_chain(struct uart_8250_port *up) | |
1535 | { | |
1536 | struct irq_info *i = irq_lists + up->port.irq; | |
40663cc7 | 1537 | int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0; |
1da177e4 LT |
1538 | |
1539 | spin_lock_irq(&i->lock); | |
1540 | ||
1541 | if (i->head) { | |
1542 | list_add(&up->list, i->head); | |
1543 | spin_unlock_irq(&i->lock); | |
1544 | ||
1545 | ret = 0; | |
1546 | } else { | |
1547 | INIT_LIST_HEAD(&up->list); | |
1548 | i->head = &up->list; | |
1549 | spin_unlock_irq(&i->lock); | |
1550 | ||
1551 | ret = request_irq(up->port.irq, serial8250_interrupt, | |
1552 | irq_flags, "serial", i); | |
1553 | if (ret < 0) | |
1554 | serial_do_unlink(i, up); | |
1555 | } | |
1556 | ||
1557 | return ret; | |
1558 | } | |
1559 | ||
1560 | static void serial_unlink_irq_chain(struct uart_8250_port *up) | |
1561 | { | |
1562 | struct irq_info *i = irq_lists + up->port.irq; | |
1563 | ||
1564 | BUG_ON(i->head == NULL); | |
1565 | ||
1566 | if (list_empty(i->head)) | |
1567 | free_irq(up->port.irq, i); | |
1568 | ||
1569 | serial_do_unlink(i, up); | |
1570 | } | |
1571 | ||
40b36daa AW |
1572 | /* Base timer interval for polling */ |
1573 | static inline int poll_timeout(int timeout) | |
1574 | { | |
1575 | return timeout > 6 ? (timeout / 2 - 2) : 1; | |
1576 | } | |
1577 | ||
1da177e4 LT |
1578 | /* |
1579 | * This function is used to handle ports that do not have an | |
1580 | * interrupt. This doesn't work very well for 16450's, but gives | |
1581 | * barely passable results for a 16550A. (Although at the expense | |
1582 | * of much CPU overhead). | |
1583 | */ | |
1584 | static void serial8250_timeout(unsigned long data) | |
1585 | { | |
1586 | struct uart_8250_port *up = (struct uart_8250_port *)data; | |
1da177e4 LT |
1587 | unsigned int iir; |
1588 | ||
1589 | iir = serial_in(up, UART_IIR); | |
45e24601 | 1590 | if (!(iir & UART_IIR_NO_INT)) |
7d12e780 | 1591 | serial8250_handle_port(up); |
40b36daa AW |
1592 | mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout)); |
1593 | } | |
1594 | ||
1595 | static void serial8250_backup_timeout(unsigned long data) | |
1596 | { | |
1597 | struct uart_8250_port *up = (struct uart_8250_port *)data; | |
ad4c2aa6 CM |
1598 | unsigned int iir, ier = 0, lsr; |
1599 | unsigned long flags; | |
40b36daa AW |
1600 | |
1601 | /* | |
1602 | * Must disable interrupts or else we risk racing with the interrupt | |
1603 | * based handler. | |
1604 | */ | |
1605 | if (is_real_interrupt(up->port.irq)) { | |
1606 | ier = serial_in(up, UART_IER); | |
1607 | serial_out(up, UART_IER, 0); | |
1608 | } | |
1da177e4 | 1609 | |
40b36daa AW |
1610 | iir = serial_in(up, UART_IIR); |
1611 | ||
1612 | /* | |
1613 | * This should be a safe test for anyone who doesn't trust the | |
1614 | * IIR bits on their UART, but it's specifically designed for | |
1615 | * the "Diva" UART used on the management processor on many HP | |
1616 | * ia64 and parisc boxes. | |
1617 | */ | |
ad4c2aa6 CM |
1618 | spin_lock_irqsave(&up->port.lock, flags); |
1619 | lsr = serial_in(up, UART_LSR); | |
1620 | up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; | |
1621 | spin_unlock_irqrestore(&up->port.lock, flags); | |
40b36daa AW |
1622 | if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) && |
1623 | (!uart_circ_empty(&up->port.info->xmit) || up->port.x_char) && | |
ad4c2aa6 | 1624 | (lsr & UART_LSR_THRE)) { |
40b36daa AW |
1625 | iir &= ~(UART_IIR_ID | UART_IIR_NO_INT); |
1626 | iir |= UART_IIR_THRI; | |
1627 | } | |
1628 | ||
1629 | if (!(iir & UART_IIR_NO_INT)) | |
1630 | serial8250_handle_port(up); | |
1631 | ||
1632 | if (is_real_interrupt(up->port.irq)) | |
1633 | serial_out(up, UART_IER, ier); | |
1634 | ||
1635 | /* Standard timer interval plus 0.2s to keep the port running */ | |
6f803cd0 AC |
1636 | mod_timer(&up->timer, |
1637 | jiffies + poll_timeout(up->port.timeout) + HZ / 5); | |
1da177e4 LT |
1638 | } |
1639 | ||
1640 | static unsigned int serial8250_tx_empty(struct uart_port *port) | |
1641 | { | |
1642 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1643 | unsigned long flags; | |
ad4c2aa6 | 1644 | unsigned int lsr; |
1da177e4 LT |
1645 | |
1646 | spin_lock_irqsave(&up->port.lock, flags); | |
ad4c2aa6 CM |
1647 | lsr = serial_in(up, UART_LSR); |
1648 | up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; | |
1da177e4 LT |
1649 | spin_unlock_irqrestore(&up->port.lock, flags); |
1650 | ||
ad4c2aa6 | 1651 | return lsr & UART_LSR_TEMT ? TIOCSER_TEMT : 0; |
1da177e4 LT |
1652 | } |
1653 | ||
1654 | static unsigned int serial8250_get_mctrl(struct uart_port *port) | |
1655 | { | |
1656 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
2af7cd68 | 1657 | unsigned int status; |
1da177e4 LT |
1658 | unsigned int ret; |
1659 | ||
2af7cd68 | 1660 | status = check_modem_status(up); |
1da177e4 LT |
1661 | |
1662 | ret = 0; | |
1663 | if (status & UART_MSR_DCD) | |
1664 | ret |= TIOCM_CAR; | |
1665 | if (status & UART_MSR_RI) | |
1666 | ret |= TIOCM_RNG; | |
1667 | if (status & UART_MSR_DSR) | |
1668 | ret |= TIOCM_DSR; | |
1669 | if (status & UART_MSR_CTS) | |
1670 | ret |= TIOCM_CTS; | |
1671 | return ret; | |
1672 | } | |
1673 | ||
1674 | static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
1675 | { | |
1676 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1677 | unsigned char mcr = 0; | |
1678 | ||
1679 | if (mctrl & TIOCM_RTS) | |
1680 | mcr |= UART_MCR_RTS; | |
1681 | if (mctrl & TIOCM_DTR) | |
1682 | mcr |= UART_MCR_DTR; | |
1683 | if (mctrl & TIOCM_OUT1) | |
1684 | mcr |= UART_MCR_OUT1; | |
1685 | if (mctrl & TIOCM_OUT2) | |
1686 | mcr |= UART_MCR_OUT2; | |
1687 | if (mctrl & TIOCM_LOOP) | |
1688 | mcr |= UART_MCR_LOOP; | |
1689 | ||
1690 | mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr; | |
1691 | ||
1692 | serial_out(up, UART_MCR, mcr); | |
1693 | } | |
1694 | ||
1695 | static void serial8250_break_ctl(struct uart_port *port, int break_state) | |
1696 | { | |
1697 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1698 | unsigned long flags; | |
1699 | ||
1700 | spin_lock_irqsave(&up->port.lock, flags); | |
1701 | if (break_state == -1) | |
1702 | up->lcr |= UART_LCR_SBC; | |
1703 | else | |
1704 | up->lcr &= ~UART_LCR_SBC; | |
1705 | serial_out(up, UART_LCR, up->lcr); | |
1706 | spin_unlock_irqrestore(&up->port.lock, flags); | |
1707 | } | |
1708 | ||
40b36daa AW |
1709 | #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) |
1710 | ||
1711 | /* | |
1712 | * Wait for transmitter & holding register to empty | |
1713 | */ | |
1714 | static inline void wait_for_xmitr(struct uart_8250_port *up, int bits) | |
1715 | { | |
1716 | unsigned int status, tmout = 10000; | |
1717 | ||
1718 | /* Wait up to 10ms for the character(s) to be sent. */ | |
1719 | do { | |
1720 | status = serial_in(up, UART_LSR); | |
1721 | ||
ad4c2aa6 | 1722 | up->lsr_saved_flags |= status & LSR_SAVE_FLAGS; |
40b36daa AW |
1723 | |
1724 | if (--tmout == 0) | |
1725 | break; | |
1726 | udelay(1); | |
1727 | } while ((status & bits) != bits); | |
1728 | ||
1729 | /* Wait up to 1s for flow control if necessary */ | |
1730 | if (up->port.flags & UPF_CONS_FLOW) { | |
ad4c2aa6 CM |
1731 | unsigned int tmout; |
1732 | for (tmout = 1000000; tmout; tmout--) { | |
1733 | unsigned int msr = serial_in(up, UART_MSR); | |
1734 | up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; | |
1735 | if (msr & UART_MSR_CTS) | |
1736 | break; | |
40b36daa AW |
1737 | udelay(1); |
1738 | touch_nmi_watchdog(); | |
1739 | } | |
1740 | } | |
1741 | } | |
1742 | ||
f2d937f3 JW |
1743 | #ifdef CONFIG_CONSOLE_POLL |
1744 | /* | |
1745 | * Console polling routines for writing and reading from the uart while | |
1746 | * in an interrupt or debug context. | |
1747 | */ | |
1748 | ||
1749 | static int serial8250_get_poll_char(struct uart_port *port) | |
1750 | { | |
1751 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1752 | unsigned char lsr = serial_inp(up, UART_LSR); | |
1753 | ||
1754 | while (!(lsr & UART_LSR_DR)) | |
1755 | lsr = serial_inp(up, UART_LSR); | |
1756 | ||
1757 | return serial_inp(up, UART_RX); | |
1758 | } | |
1759 | ||
1760 | ||
1761 | static void serial8250_put_poll_char(struct uart_port *port, | |
1762 | unsigned char c) | |
1763 | { | |
1764 | unsigned int ier; | |
1765 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1766 | ||
1767 | /* | |
1768 | * First save the IER then disable the interrupts | |
1769 | */ | |
1770 | ier = serial_in(up, UART_IER); | |
1771 | if (up->capabilities & UART_CAP_UUE) | |
1772 | serial_out(up, UART_IER, UART_IER_UUE); | |
1773 | else | |
1774 | serial_out(up, UART_IER, 0); | |
1775 | ||
1776 | wait_for_xmitr(up, BOTH_EMPTY); | |
1777 | /* | |
1778 | * Send the character out. | |
1779 | * If a LF, also do CR... | |
1780 | */ | |
1781 | serial_out(up, UART_TX, c); | |
1782 | if (c == 10) { | |
1783 | wait_for_xmitr(up, BOTH_EMPTY); | |
1784 | serial_out(up, UART_TX, 13); | |
1785 | } | |
1786 | ||
1787 | /* | |
1788 | * Finally, wait for transmitter to become empty | |
1789 | * and restore the IER | |
1790 | */ | |
1791 | wait_for_xmitr(up, BOTH_EMPTY); | |
1792 | serial_out(up, UART_IER, ier); | |
1793 | } | |
1794 | ||
1795 | #endif /* CONFIG_CONSOLE_POLL */ | |
1796 | ||
1da177e4 LT |
1797 | static int serial8250_startup(struct uart_port *port) |
1798 | { | |
1799 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1800 | unsigned long flags; | |
55d3b282 | 1801 | unsigned char lsr, iir; |
1da177e4 LT |
1802 | int retval; |
1803 | ||
1804 | up->capabilities = uart_config[up->port.type].flags; | |
1805 | up->mcr = 0; | |
1806 | ||
1807 | if (up->port.type == PORT_16C950) { | |
1808 | /* Wake up and initialize UART */ | |
1809 | up->acr = 0; | |
1810 | serial_outp(up, UART_LCR, 0xBF); | |
1811 | serial_outp(up, UART_EFR, UART_EFR_ECB); | |
1812 | serial_outp(up, UART_IER, 0); | |
1813 | serial_outp(up, UART_LCR, 0); | |
1814 | serial_icr_write(up, UART_CSR, 0); /* Reset the UART */ | |
1815 | serial_outp(up, UART_LCR, 0xBF); | |
1816 | serial_outp(up, UART_EFR, UART_EFR_ECB); | |
1817 | serial_outp(up, UART_LCR, 0); | |
1818 | } | |
1819 | ||
1820 | #ifdef CONFIG_SERIAL_8250_RSA | |
1821 | /* | |
1822 | * If this is an RSA port, see if we can kick it up to the | |
1823 | * higher speed clock. | |
1824 | */ | |
1825 | enable_rsa(up); | |
1826 | #endif | |
1827 | ||
1828 | /* | |
1829 | * Clear the FIFO buffers and disable them. | |
7f927fcc | 1830 | * (they will be reenabled in set_termios()) |
1da177e4 LT |
1831 | */ |
1832 | serial8250_clear_fifos(up); | |
1833 | ||
1834 | /* | |
1835 | * Clear the interrupt registers. | |
1836 | */ | |
1837 | (void) serial_inp(up, UART_LSR); | |
1838 | (void) serial_inp(up, UART_RX); | |
1839 | (void) serial_inp(up, UART_IIR); | |
1840 | (void) serial_inp(up, UART_MSR); | |
1841 | ||
1842 | /* | |
1843 | * At this point, there's no way the LSR could still be 0xff; | |
1844 | * if it is, then bail out, because there's likely no UART | |
1845 | * here. | |
1846 | */ | |
1847 | if (!(up->port.flags & UPF_BUGGY_UART) && | |
1848 | (serial_inp(up, UART_LSR) == 0xff)) { | |
1849 | printk("ttyS%d: LSR safety check engaged!\n", up->port.line); | |
1850 | return -ENODEV; | |
1851 | } | |
1852 | ||
1853 | /* | |
1854 | * For a XR16C850, we need to set the trigger levels | |
1855 | */ | |
1856 | if (up->port.type == PORT_16850) { | |
1857 | unsigned char fctr; | |
1858 | ||
1859 | serial_outp(up, UART_LCR, 0xbf); | |
1860 | ||
1861 | fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX); | |
1862 | serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX); | |
1863 | serial_outp(up, UART_TRG, UART_TRG_96); | |
1864 | serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX); | |
1865 | serial_outp(up, UART_TRG, UART_TRG_96); | |
1866 | ||
1867 | serial_outp(up, UART_LCR, 0); | |
1868 | } | |
1869 | ||
40b36daa AW |
1870 | if (is_real_interrupt(up->port.irq)) { |
1871 | /* | |
1872 | * Test for UARTs that do not reassert THRE when the | |
1873 | * transmitter is idle and the interrupt has already | |
1874 | * been cleared. Real 16550s should always reassert | |
1875 | * this interrupt whenever the transmitter is idle and | |
1876 | * the interrupt is enabled. Delays are necessary to | |
1877 | * allow register changes to become visible. | |
1878 | */ | |
1879 | spin_lock_irqsave(&up->port.lock, flags); | |
1880 | ||
1881 | wait_for_xmitr(up, UART_LSR_THRE); | |
1882 | serial_out_sync(up, UART_IER, UART_IER_THRI); | |
1883 | udelay(1); /* allow THRE to set */ | |
1884 | serial_in(up, UART_IIR); | |
1885 | serial_out(up, UART_IER, 0); | |
1886 | serial_out_sync(up, UART_IER, UART_IER_THRI); | |
1887 | udelay(1); /* allow a working UART time to re-assert THRE */ | |
1888 | iir = serial_in(up, UART_IIR); | |
1889 | serial_out(up, UART_IER, 0); | |
1890 | ||
1891 | spin_unlock_irqrestore(&up->port.lock, flags); | |
1892 | ||
1893 | /* | |
1894 | * If the interrupt is not reasserted, setup a timer to | |
1895 | * kick the UART on a regular basis. | |
1896 | */ | |
1897 | if (iir & UART_IIR_NO_INT) { | |
1898 | pr_debug("ttyS%d - using backup timer\n", port->line); | |
1899 | up->timer.function = serial8250_backup_timeout; | |
1900 | up->timer.data = (unsigned long)up; | |
1901 | mod_timer(&up->timer, jiffies + | |
6f803cd0 | 1902 | poll_timeout(up->port.timeout) + HZ / 5); |
40b36daa AW |
1903 | } |
1904 | } | |
1905 | ||
1da177e4 LT |
1906 | /* |
1907 | * If the "interrupt" for this port doesn't correspond with any | |
1908 | * hardware interrupt, we use a timer-based system. The original | |
1909 | * driver used to do this with IRQ0. | |
1910 | */ | |
1911 | if (!is_real_interrupt(up->port.irq)) { | |
1da177e4 | 1912 | up->timer.data = (unsigned long)up; |
40b36daa | 1913 | mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout)); |
1da177e4 LT |
1914 | } else { |
1915 | retval = serial_link_irq_chain(up); | |
1916 | if (retval) | |
1917 | return retval; | |
1918 | } | |
1919 | ||
1920 | /* | |
1921 | * Now, initialize the UART | |
1922 | */ | |
1923 | serial_outp(up, UART_LCR, UART_LCR_WLEN8); | |
1924 | ||
1925 | spin_lock_irqsave(&up->port.lock, flags); | |
1926 | if (up->port.flags & UPF_FOURPORT) { | |
1927 | if (!is_real_interrupt(up->port.irq)) | |
1928 | up->port.mctrl |= TIOCM_OUT1; | |
1929 | } else | |
1930 | /* | |
1931 | * Most PC uarts need OUT2 raised to enable interrupts. | |
1932 | */ | |
1933 | if (is_real_interrupt(up->port.irq)) | |
1934 | up->port.mctrl |= TIOCM_OUT2; | |
1935 | ||
1936 | serial8250_set_mctrl(&up->port, up->port.mctrl); | |
55d3b282 RK |
1937 | |
1938 | /* | |
1939 | * Do a quick test to see if we receive an | |
1940 | * interrupt when we enable the TX irq. | |
1941 | */ | |
1942 | serial_outp(up, UART_IER, UART_IER_THRI); | |
1943 | lsr = serial_in(up, UART_LSR); | |
1944 | iir = serial_in(up, UART_IIR); | |
1945 | serial_outp(up, UART_IER, 0); | |
1946 | ||
1947 | if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) { | |
67f7654e RK |
1948 | if (!(up->bugs & UART_BUG_TXEN)) { |
1949 | up->bugs |= UART_BUG_TXEN; | |
55d3b282 RK |
1950 | pr_debug("ttyS%d - enabling bad tx status workarounds\n", |
1951 | port->line); | |
1952 | } | |
1953 | } else { | |
67f7654e | 1954 | up->bugs &= ~UART_BUG_TXEN; |
55d3b282 RK |
1955 | } |
1956 | ||
1da177e4 LT |
1957 | spin_unlock_irqrestore(&up->port.lock, flags); |
1958 | ||
ad4c2aa6 CM |
1959 | /* |
1960 | * Clear the interrupt registers again for luck, and clear the | |
1961 | * saved flags to avoid getting false values from polling | |
1962 | * routines or the previous session. | |
1963 | */ | |
1964 | serial_inp(up, UART_LSR); | |
1965 | serial_inp(up, UART_RX); | |
1966 | serial_inp(up, UART_IIR); | |
1967 | serial_inp(up, UART_MSR); | |
1968 | up->lsr_saved_flags = 0; | |
1969 | up->msr_saved_flags = 0; | |
1970 | ||
1da177e4 LT |
1971 | /* |
1972 | * Finally, enable interrupts. Note: Modem status interrupts | |
1973 | * are set via set_termios(), which will be occurring imminently | |
1974 | * anyway, so we don't enable them here. | |
1975 | */ | |
1976 | up->ier = UART_IER_RLSI | UART_IER_RDI; | |
1977 | serial_outp(up, UART_IER, up->ier); | |
1978 | ||
1979 | if (up->port.flags & UPF_FOURPORT) { | |
1980 | unsigned int icp; | |
1981 | /* | |
1982 | * Enable interrupts on the AST Fourport board | |
1983 | */ | |
1984 | icp = (up->port.iobase & 0xfe0) | 0x01f; | |
1985 | outb_p(0x80, icp); | |
1986 | (void) inb_p(icp); | |
1987 | } | |
1988 | ||
1da177e4 LT |
1989 | return 0; |
1990 | } | |
1991 | ||
1992 | static void serial8250_shutdown(struct uart_port *port) | |
1993 | { | |
1994 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
1995 | unsigned long flags; | |
1996 | ||
1997 | /* | |
1998 | * Disable interrupts from this port | |
1999 | */ | |
2000 | up->ier = 0; | |
2001 | serial_outp(up, UART_IER, 0); | |
2002 | ||
2003 | spin_lock_irqsave(&up->port.lock, flags); | |
2004 | if (up->port.flags & UPF_FOURPORT) { | |
2005 | /* reset interrupts on the AST Fourport board */ | |
2006 | inb((up->port.iobase & 0xfe0) | 0x1f); | |
2007 | up->port.mctrl |= TIOCM_OUT1; | |
2008 | } else | |
2009 | up->port.mctrl &= ~TIOCM_OUT2; | |
2010 | ||
2011 | serial8250_set_mctrl(&up->port, up->port.mctrl); | |
2012 | spin_unlock_irqrestore(&up->port.lock, flags); | |
2013 | ||
2014 | /* | |
2015 | * Disable break condition and FIFOs | |
2016 | */ | |
2017 | serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC); | |
2018 | serial8250_clear_fifos(up); | |
2019 | ||
2020 | #ifdef CONFIG_SERIAL_8250_RSA | |
2021 | /* | |
2022 | * Reset the RSA board back to 115kbps compat mode. | |
2023 | */ | |
2024 | disable_rsa(up); | |
2025 | #endif | |
2026 | ||
2027 | /* | |
2028 | * Read data port to reset things, and then unlink from | |
2029 | * the IRQ chain. | |
2030 | */ | |
2031 | (void) serial_in(up, UART_RX); | |
2032 | ||
40b36daa AW |
2033 | del_timer_sync(&up->timer); |
2034 | up->timer.function = serial8250_timeout; | |
2035 | if (is_real_interrupt(up->port.irq)) | |
1da177e4 LT |
2036 | serial_unlink_irq_chain(up); |
2037 | } | |
2038 | ||
2039 | static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud) | |
2040 | { | |
2041 | unsigned int quot; | |
2042 | ||
2043 | /* | |
2044 | * Handle magic divisors for baud rates above baud_base on | |
2045 | * SMSC SuperIO chips. | |
2046 | */ | |
2047 | if ((port->flags & UPF_MAGIC_MULTIPLIER) && | |
2048 | baud == (port->uartclk/4)) | |
2049 | quot = 0x8001; | |
2050 | else if ((port->flags & UPF_MAGIC_MULTIPLIER) && | |
2051 | baud == (port->uartclk/8)) | |
2052 | quot = 0x8002; | |
2053 | else | |
2054 | quot = uart_get_divisor(port, baud); | |
2055 | ||
2056 | return quot; | |
2057 | } | |
2058 | ||
2059 | static void | |
606d099c AC |
2060 | serial8250_set_termios(struct uart_port *port, struct ktermios *termios, |
2061 | struct ktermios *old) | |
1da177e4 LT |
2062 | { |
2063 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
2064 | unsigned char cval, fcr = 0; | |
2065 | unsigned long flags; | |
2066 | unsigned int baud, quot; | |
2067 | ||
2068 | switch (termios->c_cflag & CSIZE) { | |
2069 | case CS5: | |
0a8b80c5 | 2070 | cval = UART_LCR_WLEN5; |
1da177e4 LT |
2071 | break; |
2072 | case CS6: | |
0a8b80c5 | 2073 | cval = UART_LCR_WLEN6; |
1da177e4 LT |
2074 | break; |
2075 | case CS7: | |
0a8b80c5 | 2076 | cval = UART_LCR_WLEN7; |
1da177e4 LT |
2077 | break; |
2078 | default: | |
2079 | case CS8: | |
0a8b80c5 | 2080 | cval = UART_LCR_WLEN8; |
1da177e4 LT |
2081 | break; |
2082 | } | |
2083 | ||
2084 | if (termios->c_cflag & CSTOPB) | |
0a8b80c5 | 2085 | cval |= UART_LCR_STOP; |
1da177e4 LT |
2086 | if (termios->c_cflag & PARENB) |
2087 | cval |= UART_LCR_PARITY; | |
2088 | if (!(termios->c_cflag & PARODD)) | |
2089 | cval |= UART_LCR_EPAR; | |
2090 | #ifdef CMSPAR | |
2091 | if (termios->c_cflag & CMSPAR) | |
2092 | cval |= UART_LCR_SPAR; | |
2093 | #endif | |
2094 | ||
2095 | /* | |
2096 | * Ask the core to calculate the divisor for us. | |
2097 | */ | |
bd71c182 | 2098 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); |
1da177e4 LT |
2099 | quot = serial8250_get_divisor(port, baud); |
2100 | ||
2101 | /* | |
4ba5e35d | 2102 | * Oxford Semi 952 rev B workaround |
1da177e4 | 2103 | */ |
4ba5e35d | 2104 | if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0) |
3e8d4e20 | 2105 | quot++; |
1da177e4 LT |
2106 | |
2107 | if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) { | |
2108 | if (baud < 2400) | |
2109 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1; | |
2110 | else | |
2111 | fcr = uart_config[up->port.type].fcr; | |
2112 | } | |
2113 | ||
2114 | /* | |
2115 | * MCR-based auto flow control. When AFE is enabled, RTS will be | |
2116 | * deasserted when the receive FIFO contains more characters than | |
2117 | * the trigger, or the MCR RTS bit is cleared. In the case where | |
2118 | * the remote UART is not using CTS auto flow control, we must | |
2119 | * have sufficient FIFO entries for the latency of the remote | |
2120 | * UART to respond. IOW, at least 32 bytes of FIFO. | |
2121 | */ | |
2122 | if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) { | |
2123 | up->mcr &= ~UART_MCR_AFE; | |
2124 | if (termios->c_cflag & CRTSCTS) | |
2125 | up->mcr |= UART_MCR_AFE; | |
2126 | } | |
2127 | ||
2128 | /* | |
2129 | * Ok, we're now changing the port state. Do it with | |
2130 | * interrupts disabled. | |
2131 | */ | |
2132 | spin_lock_irqsave(&up->port.lock, flags); | |
2133 | ||
2134 | /* | |
2135 | * Update the per-port timeout. | |
2136 | */ | |
2137 | uart_update_timeout(port, termios->c_cflag, baud); | |
2138 | ||
2139 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; | |
2140 | if (termios->c_iflag & INPCK) | |
2141 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; | |
2142 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
2143 | up->port.read_status_mask |= UART_LSR_BI; | |
2144 | ||
2145 | /* | |
2146 | * Characteres to ignore | |
2147 | */ | |
2148 | up->port.ignore_status_mask = 0; | |
2149 | if (termios->c_iflag & IGNPAR) | |
2150 | up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; | |
2151 | if (termios->c_iflag & IGNBRK) { | |
2152 | up->port.ignore_status_mask |= UART_LSR_BI; | |
2153 | /* | |
2154 | * If we're ignoring parity and break indicators, | |
2155 | * ignore overruns too (for real raw support). | |
2156 | */ | |
2157 | if (termios->c_iflag & IGNPAR) | |
2158 | up->port.ignore_status_mask |= UART_LSR_OE; | |
2159 | } | |
2160 | ||
2161 | /* | |
2162 | * ignore all characters if CREAD is not set | |
2163 | */ | |
2164 | if ((termios->c_cflag & CREAD) == 0) | |
2165 | up->port.ignore_status_mask |= UART_LSR_DR; | |
2166 | ||
2167 | /* | |
2168 | * CTS flow control flag and modem status interrupts | |
2169 | */ | |
2170 | up->ier &= ~UART_IER_MSI; | |
21c614a7 PA |
2171 | if (!(up->bugs & UART_BUG_NOMSR) && |
2172 | UART_ENABLE_MS(&up->port, termios->c_cflag)) | |
1da177e4 LT |
2173 | up->ier |= UART_IER_MSI; |
2174 | if (up->capabilities & UART_CAP_UUE) | |
2175 | up->ier |= UART_IER_UUE | UART_IER_RTOIE; | |
2176 | ||
2177 | serial_out(up, UART_IER, up->ier); | |
2178 | ||
2179 | if (up->capabilities & UART_CAP_EFR) { | |
2180 | unsigned char efr = 0; | |
2181 | /* | |
2182 | * TI16C752/Startech hardware flow control. FIXME: | |
2183 | * - TI16C752 requires control thresholds to be set. | |
2184 | * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled. | |
2185 | */ | |
2186 | if (termios->c_cflag & CRTSCTS) | |
2187 | efr |= UART_EFR_CTS; | |
2188 | ||
2189 | serial_outp(up, UART_LCR, 0xBF); | |
2190 | serial_outp(up, UART_EFR, efr); | |
2191 | } | |
2192 | ||
255341c6 JM |
2193 | #ifdef CONFIG_ARCH_OMAP15XX |
2194 | /* Workaround to enable 115200 baud on OMAP1510 internal ports */ | |
2195 | if (cpu_is_omap1510() && is_omap_port((unsigned int)up->port.membase)) { | |
2196 | if (baud == 115200) { | |
2197 | quot = 1; | |
2198 | serial_out(up, UART_OMAP_OSC_12M_SEL, 1); | |
2199 | } else | |
2200 | serial_out(up, UART_OMAP_OSC_12M_SEL, 0); | |
2201 | } | |
2202 | #endif | |
2203 | ||
1da177e4 LT |
2204 | if (up->capabilities & UART_NATSEMI) { |
2205 | /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */ | |
2206 | serial_outp(up, UART_LCR, 0xe0); | |
2207 | } else { | |
2208 | serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */ | |
2209 | } | |
2210 | ||
b32b19b8 | 2211 | serial_dl_write(up, quot); |
1da177e4 LT |
2212 | |
2213 | /* | |
2214 | * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR | |
2215 | * is written without DLAB set, this mode will be disabled. | |
2216 | */ | |
2217 | if (up->port.type == PORT_16750) | |
2218 | serial_outp(up, UART_FCR, fcr); | |
2219 | ||
2220 | serial_outp(up, UART_LCR, cval); /* reset DLAB */ | |
2221 | up->lcr = cval; /* Save LCR */ | |
2222 | if (up->port.type != PORT_16750) { | |
2223 | if (fcr & UART_FCR_ENABLE_FIFO) { | |
2224 | /* emulated UARTs (Lucent Venus 167x) need two steps */ | |
2225 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
2226 | } | |
2227 | serial_outp(up, UART_FCR, fcr); /* set fcr */ | |
2228 | } | |
2229 | serial8250_set_mctrl(&up->port, up->port.mctrl); | |
2230 | spin_unlock_irqrestore(&up->port.lock, flags); | |
b4c502a7 | 2231 | tty_termios_encode_baud_rate(termios, baud, baud); |
1da177e4 LT |
2232 | } |
2233 | ||
2234 | static void | |
2235 | serial8250_pm(struct uart_port *port, unsigned int state, | |
2236 | unsigned int oldstate) | |
2237 | { | |
2238 | struct uart_8250_port *p = (struct uart_8250_port *)port; | |
2239 | ||
2240 | serial8250_set_sleep(p, state != 0); | |
2241 | ||
2242 | if (p->pm) | |
2243 | p->pm(port, state, oldstate); | |
2244 | } | |
2245 | ||
2246 | /* | |
2247 | * Resource handling. | |
2248 | */ | |
2249 | static int serial8250_request_std_resource(struct uart_8250_port *up) | |
2250 | { | |
2251 | unsigned int size = 8 << up->port.regshift; | |
2252 | int ret = 0; | |
2253 | ||
2254 | switch (up->port.iotype) { | |
85835f44 SS |
2255 | case UPIO_AU: |
2256 | size = 0x100000; | |
2257 | /* fall thru */ | |
0b30d668 SS |
2258 | case UPIO_TSI: |
2259 | case UPIO_MEM32: | |
1da177e4 | 2260 | case UPIO_MEM: |
beab697a | 2261 | case UPIO_DWAPB: |
1da177e4 LT |
2262 | if (!up->port.mapbase) |
2263 | break; | |
2264 | ||
2265 | if (!request_mem_region(up->port.mapbase, size, "serial")) { | |
2266 | ret = -EBUSY; | |
2267 | break; | |
2268 | } | |
2269 | ||
2270 | if (up->port.flags & UPF_IOREMAP) { | |
2271 | up->port.membase = ioremap(up->port.mapbase, size); | |
2272 | if (!up->port.membase) { | |
2273 | release_mem_region(up->port.mapbase, size); | |
2274 | ret = -ENOMEM; | |
2275 | } | |
2276 | } | |
2277 | break; | |
2278 | ||
2279 | case UPIO_HUB6: | |
2280 | case UPIO_PORT: | |
2281 | if (!request_region(up->port.iobase, size, "serial")) | |
2282 | ret = -EBUSY; | |
2283 | break; | |
2284 | } | |
2285 | return ret; | |
2286 | } | |
2287 | ||
2288 | static void serial8250_release_std_resource(struct uart_8250_port *up) | |
2289 | { | |
2290 | unsigned int size = 8 << up->port.regshift; | |
2291 | ||
2292 | switch (up->port.iotype) { | |
85835f44 SS |
2293 | case UPIO_AU: |
2294 | size = 0x100000; | |
2295 | /* fall thru */ | |
0b30d668 SS |
2296 | case UPIO_TSI: |
2297 | case UPIO_MEM32: | |
1da177e4 | 2298 | case UPIO_MEM: |
beab697a | 2299 | case UPIO_DWAPB: |
1da177e4 LT |
2300 | if (!up->port.mapbase) |
2301 | break; | |
2302 | ||
2303 | if (up->port.flags & UPF_IOREMAP) { | |
2304 | iounmap(up->port.membase); | |
2305 | up->port.membase = NULL; | |
2306 | } | |
2307 | ||
2308 | release_mem_region(up->port.mapbase, size); | |
2309 | break; | |
2310 | ||
2311 | case UPIO_HUB6: | |
2312 | case UPIO_PORT: | |
2313 | release_region(up->port.iobase, size); | |
2314 | break; | |
2315 | } | |
2316 | } | |
2317 | ||
2318 | static int serial8250_request_rsa_resource(struct uart_8250_port *up) | |
2319 | { | |
2320 | unsigned long start = UART_RSA_BASE << up->port.regshift; | |
2321 | unsigned int size = 8 << up->port.regshift; | |
0b30d668 | 2322 | int ret = -EINVAL; |
1da177e4 LT |
2323 | |
2324 | switch (up->port.iotype) { | |
1da177e4 LT |
2325 | case UPIO_HUB6: |
2326 | case UPIO_PORT: | |
2327 | start += up->port.iobase; | |
0b30d668 SS |
2328 | if (request_region(start, size, "serial-rsa")) |
2329 | ret = 0; | |
2330 | else | |
1da177e4 LT |
2331 | ret = -EBUSY; |
2332 | break; | |
2333 | } | |
2334 | ||
2335 | return ret; | |
2336 | } | |
2337 | ||
2338 | static void serial8250_release_rsa_resource(struct uart_8250_port *up) | |
2339 | { | |
2340 | unsigned long offset = UART_RSA_BASE << up->port.regshift; | |
2341 | unsigned int size = 8 << up->port.regshift; | |
2342 | ||
2343 | switch (up->port.iotype) { | |
1da177e4 LT |
2344 | case UPIO_HUB6: |
2345 | case UPIO_PORT: | |
2346 | release_region(up->port.iobase + offset, size); | |
2347 | break; | |
2348 | } | |
2349 | } | |
2350 | ||
2351 | static void serial8250_release_port(struct uart_port *port) | |
2352 | { | |
2353 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
2354 | ||
2355 | serial8250_release_std_resource(up); | |
2356 | if (up->port.type == PORT_RSA) | |
2357 | serial8250_release_rsa_resource(up); | |
2358 | } | |
2359 | ||
2360 | static int serial8250_request_port(struct uart_port *port) | |
2361 | { | |
2362 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
2363 | int ret = 0; | |
2364 | ||
2365 | ret = serial8250_request_std_resource(up); | |
2366 | if (ret == 0 && up->port.type == PORT_RSA) { | |
2367 | ret = serial8250_request_rsa_resource(up); | |
2368 | if (ret < 0) | |
2369 | serial8250_release_std_resource(up); | |
2370 | } | |
2371 | ||
2372 | return ret; | |
2373 | } | |
2374 | ||
2375 | static void serial8250_config_port(struct uart_port *port, int flags) | |
2376 | { | |
2377 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
2378 | int probeflags = PROBE_ANY; | |
2379 | int ret; | |
2380 | ||
1da177e4 LT |
2381 | /* |
2382 | * Find the region that we can probe for. This in turn | |
2383 | * tells us whether we can probe for the type of port. | |
2384 | */ | |
2385 | ret = serial8250_request_std_resource(up); | |
2386 | if (ret < 0) | |
2387 | return; | |
2388 | ||
2389 | ret = serial8250_request_rsa_resource(up); | |
2390 | if (ret < 0) | |
2391 | probeflags &= ~PROBE_RSA; | |
2392 | ||
2393 | if (flags & UART_CONFIG_TYPE) | |
2394 | autoconfig(up, probeflags); | |
2395 | if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ) | |
2396 | autoconfig_irq(up); | |
2397 | ||
2398 | if (up->port.type != PORT_RSA && probeflags & PROBE_RSA) | |
2399 | serial8250_release_rsa_resource(up); | |
2400 | if (up->port.type == PORT_UNKNOWN) | |
2401 | serial8250_release_std_resource(up); | |
2402 | } | |
2403 | ||
2404 | static int | |
2405 | serial8250_verify_port(struct uart_port *port, struct serial_struct *ser) | |
2406 | { | |
2407 | if (ser->irq >= NR_IRQS || ser->irq < 0 || | |
2408 | ser->baud_base < 9600 || ser->type < PORT_UNKNOWN || | |
2409 | ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS || | |
2410 | ser->type == PORT_STARTECH) | |
2411 | return -EINVAL; | |
2412 | return 0; | |
2413 | } | |
2414 | ||
2415 | static const char * | |
2416 | serial8250_type(struct uart_port *port) | |
2417 | { | |
2418 | int type = port->type; | |
2419 | ||
2420 | if (type >= ARRAY_SIZE(uart_config)) | |
2421 | type = 0; | |
2422 | return uart_config[type].name; | |
2423 | } | |
2424 | ||
2425 | static struct uart_ops serial8250_pops = { | |
2426 | .tx_empty = serial8250_tx_empty, | |
2427 | .set_mctrl = serial8250_set_mctrl, | |
2428 | .get_mctrl = serial8250_get_mctrl, | |
2429 | .stop_tx = serial8250_stop_tx, | |
2430 | .start_tx = serial8250_start_tx, | |
2431 | .stop_rx = serial8250_stop_rx, | |
2432 | .enable_ms = serial8250_enable_ms, | |
2433 | .break_ctl = serial8250_break_ctl, | |
2434 | .startup = serial8250_startup, | |
2435 | .shutdown = serial8250_shutdown, | |
2436 | .set_termios = serial8250_set_termios, | |
2437 | .pm = serial8250_pm, | |
2438 | .type = serial8250_type, | |
2439 | .release_port = serial8250_release_port, | |
2440 | .request_port = serial8250_request_port, | |
2441 | .config_port = serial8250_config_port, | |
2442 | .verify_port = serial8250_verify_port, | |
f2d937f3 JW |
2443 | #ifdef CONFIG_CONSOLE_POLL |
2444 | .poll_get_char = serial8250_get_poll_char, | |
2445 | .poll_put_char = serial8250_put_poll_char, | |
2446 | #endif | |
1da177e4 LT |
2447 | }; |
2448 | ||
2449 | static struct uart_8250_port serial8250_ports[UART_NR]; | |
2450 | ||
2451 | static void __init serial8250_isa_init_ports(void) | |
2452 | { | |
2453 | struct uart_8250_port *up; | |
2454 | static int first = 1; | |
2455 | int i; | |
2456 | ||
2457 | if (!first) | |
2458 | return; | |
2459 | first = 0; | |
2460 | ||
a61c2d78 | 2461 | for (i = 0; i < nr_uarts; i++) { |
1da177e4 LT |
2462 | struct uart_8250_port *up = &serial8250_ports[i]; |
2463 | ||
2464 | up->port.line = i; | |
2465 | spin_lock_init(&up->port.lock); | |
2466 | ||
2467 | init_timer(&up->timer); | |
2468 | up->timer.function = serial8250_timeout; | |
2469 | ||
2470 | /* | |
2471 | * ALPHA_KLUDGE_MCR needs to be killed. | |
2472 | */ | |
2473 | up->mcr_mask = ~ALPHA_KLUDGE_MCR; | |
2474 | up->mcr_force = ALPHA_KLUDGE_MCR; | |
2475 | ||
2476 | up->port.ops = &serial8250_pops; | |
2477 | } | |
2478 | ||
44454bcd | 2479 | for (i = 0, up = serial8250_ports; |
a61c2d78 | 2480 | i < ARRAY_SIZE(old_serial_port) && i < nr_uarts; |
1da177e4 LT |
2481 | i++, up++) { |
2482 | up->port.iobase = old_serial_port[i].port; | |
2483 | up->port.irq = irq_canonicalize(old_serial_port[i].irq); | |
2484 | up->port.uartclk = old_serial_port[i].baud_base * 16; | |
2485 | up->port.flags = old_serial_port[i].flags; | |
2486 | up->port.hub6 = old_serial_port[i].hub6; | |
2487 | up->port.membase = old_serial_port[i].iomem_base; | |
2488 | up->port.iotype = old_serial_port[i].io_type; | |
2489 | up->port.regshift = old_serial_port[i].iomem_reg_shift; | |
2490 | if (share_irqs) | |
2491 | up->port.flags |= UPF_SHARE_IRQ; | |
2492 | } | |
2493 | } | |
2494 | ||
2495 | static void __init | |
2496 | serial8250_register_ports(struct uart_driver *drv, struct device *dev) | |
2497 | { | |
2498 | int i; | |
2499 | ||
2500 | serial8250_isa_init_ports(); | |
2501 | ||
a61c2d78 | 2502 | for (i = 0; i < nr_uarts; i++) { |
1da177e4 LT |
2503 | struct uart_8250_port *up = &serial8250_ports[i]; |
2504 | ||
2505 | up->port.dev = dev; | |
2506 | uart_add_one_port(drv, &up->port); | |
2507 | } | |
2508 | } | |
2509 | ||
2510 | #ifdef CONFIG_SERIAL_8250_CONSOLE | |
2511 | ||
d358788f RK |
2512 | static void serial8250_console_putchar(struct uart_port *port, int ch) |
2513 | { | |
2514 | struct uart_8250_port *up = (struct uart_8250_port *)port; | |
2515 | ||
2516 | wait_for_xmitr(up, UART_LSR_THRE); | |
2517 | serial_out(up, UART_TX, ch); | |
2518 | } | |
2519 | ||
1da177e4 LT |
2520 | /* |
2521 | * Print a string to the serial port trying not to disturb | |
2522 | * any possible real use of the port... | |
2523 | * | |
2524 | * The console_lock must be held when we get here. | |
2525 | */ | |
2526 | static void | |
2527 | serial8250_console_write(struct console *co, const char *s, unsigned int count) | |
2528 | { | |
2529 | struct uart_8250_port *up = &serial8250_ports[co->index]; | |
d8a5a8d7 | 2530 | unsigned long flags; |
1da177e4 | 2531 | unsigned int ier; |
d8a5a8d7 | 2532 | int locked = 1; |
1da177e4 | 2533 | |
78512ece AM |
2534 | touch_nmi_watchdog(); |
2535 | ||
68aa2c0d AM |
2536 | local_irq_save(flags); |
2537 | if (up->port.sysrq) { | |
2538 | /* serial8250_handle_port() already took the lock */ | |
2539 | locked = 0; | |
2540 | } else if (oops_in_progress) { | |
2541 | locked = spin_trylock(&up->port.lock); | |
d8a5a8d7 | 2542 | } else |
68aa2c0d | 2543 | spin_lock(&up->port.lock); |
d8a5a8d7 | 2544 | |
1da177e4 | 2545 | /* |
dc7bf130 | 2546 | * First save the IER then disable the interrupts |
1da177e4 LT |
2547 | */ |
2548 | ier = serial_in(up, UART_IER); | |
2549 | ||
2550 | if (up->capabilities & UART_CAP_UUE) | |
2551 | serial_out(up, UART_IER, UART_IER_UUE); | |
2552 | else | |
2553 | serial_out(up, UART_IER, 0); | |
2554 | ||
d358788f | 2555 | uart_console_write(&up->port, s, count, serial8250_console_putchar); |
1da177e4 LT |
2556 | |
2557 | /* | |
2558 | * Finally, wait for transmitter to become empty | |
2559 | * and restore the IER | |
2560 | */ | |
f91a3715 | 2561 | wait_for_xmitr(up, BOTH_EMPTY); |
a88d75b2 | 2562 | serial_out(up, UART_IER, ier); |
d8a5a8d7 | 2563 | |
ad4c2aa6 CM |
2564 | /* |
2565 | * The receive handling will happen properly because the | |
2566 | * receive ready bit will still be set; it is not cleared | |
2567 | * on read. However, modem control will not, we must | |
2568 | * call it if we have saved something in the saved flags | |
2569 | * while processing with interrupts off. | |
2570 | */ | |
2571 | if (up->msr_saved_flags) | |
2572 | check_modem_status(up); | |
2573 | ||
d8a5a8d7 | 2574 | if (locked) |
68aa2c0d AM |
2575 | spin_unlock(&up->port.lock); |
2576 | local_irq_restore(flags); | |
1da177e4 LT |
2577 | } |
2578 | ||
118c0ace | 2579 | static int __init serial8250_console_setup(struct console *co, char *options) |
1da177e4 LT |
2580 | { |
2581 | struct uart_port *port; | |
2582 | int baud = 9600; | |
2583 | int bits = 8; | |
2584 | int parity = 'n'; | |
2585 | int flow = 'n'; | |
2586 | ||
2587 | /* | |
2588 | * Check whether an invalid uart number has been specified, and | |
2589 | * if so, search for the first available port that does have | |
2590 | * console support. | |
2591 | */ | |
a61c2d78 | 2592 | if (co->index >= nr_uarts) |
1da177e4 LT |
2593 | co->index = 0; |
2594 | port = &serial8250_ports[co->index].port; | |
2595 | if (!port->iobase && !port->membase) | |
2596 | return -ENODEV; | |
2597 | ||
2598 | if (options) | |
2599 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
2600 | ||
2601 | return uart_set_options(port, co, baud, parity, bits, flow); | |
2602 | } | |
2603 | ||
b6b1d877 | 2604 | static int serial8250_console_early_setup(void) |
18a8bd94 YL |
2605 | { |
2606 | return serial8250_find_port_for_earlycon(); | |
2607 | } | |
2608 | ||
1da177e4 LT |
2609 | static struct uart_driver serial8250_reg; |
2610 | static struct console serial8250_console = { | |
2611 | .name = "ttyS", | |
2612 | .write = serial8250_console_write, | |
2613 | .device = uart_console_device, | |
2614 | .setup = serial8250_console_setup, | |
18a8bd94 | 2615 | .early_setup = serial8250_console_early_setup, |
1da177e4 LT |
2616 | .flags = CON_PRINTBUFFER, |
2617 | .index = -1, | |
2618 | .data = &serial8250_reg, | |
2619 | }; | |
2620 | ||
2621 | static int __init serial8250_console_init(void) | |
2622 | { | |
2623 | serial8250_isa_init_ports(); | |
2624 | register_console(&serial8250_console); | |
2625 | return 0; | |
2626 | } | |
2627 | console_initcall(serial8250_console_init); | |
2628 | ||
18a8bd94 | 2629 | int serial8250_find_port(struct uart_port *p) |
1da177e4 LT |
2630 | { |
2631 | int line; | |
2632 | struct uart_port *port; | |
2633 | ||
a61c2d78 | 2634 | for (line = 0; line < nr_uarts; line++) { |
1da177e4 | 2635 | port = &serial8250_ports[line].port; |
50aec3b5 | 2636 | if (uart_match_port(p, port)) |
1da177e4 LT |
2637 | return line; |
2638 | } | |
2639 | return -ENODEV; | |
2640 | } | |
2641 | ||
1da177e4 LT |
2642 | #define SERIAL8250_CONSOLE &serial8250_console |
2643 | #else | |
2644 | #define SERIAL8250_CONSOLE NULL | |
2645 | #endif | |
2646 | ||
2647 | static struct uart_driver serial8250_reg = { | |
2648 | .owner = THIS_MODULE, | |
2649 | .driver_name = "serial", | |
1da177e4 LT |
2650 | .dev_name = "ttyS", |
2651 | .major = TTY_MAJOR, | |
2652 | .minor = 64, | |
2653 | .nr = UART_NR, | |
2654 | .cons = SERIAL8250_CONSOLE, | |
2655 | }; | |
2656 | ||
d856c666 RK |
2657 | /* |
2658 | * early_serial_setup - early registration for 8250 ports | |
2659 | * | |
2660 | * Setup an 8250 port structure prior to console initialisation. Use | |
2661 | * after console initialisation will cause undefined behaviour. | |
2662 | */ | |
1da177e4 LT |
2663 | int __init early_serial_setup(struct uart_port *port) |
2664 | { | |
2665 | if (port->line >= ARRAY_SIZE(serial8250_ports)) | |
2666 | return -ENODEV; | |
2667 | ||
2668 | serial8250_isa_init_ports(); | |
2669 | serial8250_ports[port->line].port = *port; | |
2670 | serial8250_ports[port->line].port.ops = &serial8250_pops; | |
2671 | return 0; | |
2672 | } | |
2673 | ||
2674 | /** | |
2675 | * serial8250_suspend_port - suspend one serial port | |
2676 | * @line: serial line number | |
1da177e4 LT |
2677 | * |
2678 | * Suspend one serial port. | |
2679 | */ | |
2680 | void serial8250_suspend_port(int line) | |
2681 | { | |
2682 | uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port); | |
2683 | } | |
2684 | ||
2685 | /** | |
2686 | * serial8250_resume_port - resume one serial port | |
2687 | * @line: serial line number | |
1da177e4 LT |
2688 | * |
2689 | * Resume one serial port. | |
2690 | */ | |
2691 | void serial8250_resume_port(int line) | |
2692 | { | |
b5b82df6 DW |
2693 | struct uart_8250_port *up = &serial8250_ports[line]; |
2694 | ||
2695 | if (up->capabilities & UART_NATSEMI) { | |
2696 | unsigned char tmp; | |
2697 | ||
2698 | /* Ensure it's still in high speed mode */ | |
2699 | serial_outp(up, UART_LCR, 0xE0); | |
2700 | ||
2701 | tmp = serial_in(up, 0x04); /* EXCR2 */ | |
2702 | tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */ | |
2703 | tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */ | |
2704 | serial_outp(up, 0x04, tmp); | |
2705 | ||
2706 | serial_outp(up, UART_LCR, 0); | |
2707 | } | |
2708 | uart_resume_port(&serial8250_reg, &up->port); | |
1da177e4 LT |
2709 | } |
2710 | ||
2711 | /* | |
2712 | * Register a set of serial devices attached to a platform device. The | |
2713 | * list is terminated with a zero flags entry, which means we expect | |
2714 | * all entries to have at least UPF_BOOT_AUTOCONF set. | |
2715 | */ | |
3ae5eaec | 2716 | static int __devinit serial8250_probe(struct platform_device *dev) |
1da177e4 | 2717 | { |
3ae5eaec | 2718 | struct plat_serial8250_port *p = dev->dev.platform_data; |
1da177e4 | 2719 | struct uart_port port; |
ec9f47cd | 2720 | int ret, i; |
1da177e4 LT |
2721 | |
2722 | memset(&port, 0, sizeof(struct uart_port)); | |
2723 | ||
ec9f47cd | 2724 | for (i = 0; p && p->flags != 0; p++, i++) { |
74a19741 WN |
2725 | port.iobase = p->iobase; |
2726 | port.membase = p->membase; | |
2727 | port.irq = p->irq; | |
2728 | port.uartclk = p->uartclk; | |
2729 | port.regshift = p->regshift; | |
2730 | port.iotype = p->iotype; | |
2731 | port.flags = p->flags; | |
2732 | port.mapbase = p->mapbase; | |
2733 | port.hub6 = p->hub6; | |
2734 | port.private_data = p->private_data; | |
2735 | port.dev = &dev->dev; | |
1da177e4 LT |
2736 | if (share_irqs) |
2737 | port.flags |= UPF_SHARE_IRQ; | |
ec9f47cd RK |
2738 | ret = serial8250_register_port(&port); |
2739 | if (ret < 0) { | |
3ae5eaec | 2740 | dev_err(&dev->dev, "unable to register port at index %d " |
4f640efb JB |
2741 | "(IO%lx MEM%llx IRQ%d): %d\n", i, |
2742 | p->iobase, (unsigned long long)p->mapbase, | |
2743 | p->irq, ret); | |
ec9f47cd | 2744 | } |
1da177e4 LT |
2745 | } |
2746 | return 0; | |
2747 | } | |
2748 | ||
2749 | /* | |
2750 | * Remove serial ports registered against a platform device. | |
2751 | */ | |
3ae5eaec | 2752 | static int __devexit serial8250_remove(struct platform_device *dev) |
1da177e4 LT |
2753 | { |
2754 | int i; | |
2755 | ||
a61c2d78 | 2756 | for (i = 0; i < nr_uarts; i++) { |
1da177e4 LT |
2757 | struct uart_8250_port *up = &serial8250_ports[i]; |
2758 | ||
3ae5eaec | 2759 | if (up->port.dev == &dev->dev) |
1da177e4 LT |
2760 | serial8250_unregister_port(i); |
2761 | } | |
2762 | return 0; | |
2763 | } | |
2764 | ||
3ae5eaec | 2765 | static int serial8250_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 LT |
2766 | { |
2767 | int i; | |
2768 | ||
1da177e4 LT |
2769 | for (i = 0; i < UART_NR; i++) { |
2770 | struct uart_8250_port *up = &serial8250_ports[i]; | |
2771 | ||
3ae5eaec | 2772 | if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev) |
1da177e4 LT |
2773 | uart_suspend_port(&serial8250_reg, &up->port); |
2774 | } | |
2775 | ||
2776 | return 0; | |
2777 | } | |
2778 | ||
3ae5eaec | 2779 | static int serial8250_resume(struct platform_device *dev) |
1da177e4 LT |
2780 | { |
2781 | int i; | |
2782 | ||
1da177e4 LT |
2783 | for (i = 0; i < UART_NR; i++) { |
2784 | struct uart_8250_port *up = &serial8250_ports[i]; | |
2785 | ||
3ae5eaec | 2786 | if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev) |
b5b82df6 | 2787 | serial8250_resume_port(i); |
1da177e4 LT |
2788 | } |
2789 | ||
2790 | return 0; | |
2791 | } | |
2792 | ||
3ae5eaec | 2793 | static struct platform_driver serial8250_isa_driver = { |
1da177e4 LT |
2794 | .probe = serial8250_probe, |
2795 | .remove = __devexit_p(serial8250_remove), | |
2796 | .suspend = serial8250_suspend, | |
2797 | .resume = serial8250_resume, | |
3ae5eaec RK |
2798 | .driver = { |
2799 | .name = "serial8250", | |
7493a314 | 2800 | .owner = THIS_MODULE, |
3ae5eaec | 2801 | }, |
1da177e4 LT |
2802 | }; |
2803 | ||
2804 | /* | |
2805 | * This "device" covers _all_ ISA 8250-compatible serial devices listed | |
2806 | * in the table in include/asm/serial.h | |
2807 | */ | |
2808 | static struct platform_device *serial8250_isa_devs; | |
2809 | ||
2810 | /* | |
2811 | * serial8250_register_port and serial8250_unregister_port allows for | |
2812 | * 16x50 serial ports to be configured at run-time, to support PCMCIA | |
2813 | * modems and PCI multiport cards. | |
2814 | */ | |
f392ecfa | 2815 | static DEFINE_MUTEX(serial_mutex); |
1da177e4 LT |
2816 | |
2817 | static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port) | |
2818 | { | |
2819 | int i; | |
2820 | ||
2821 | /* | |
2822 | * First, find a port entry which matches. | |
2823 | */ | |
a61c2d78 | 2824 | for (i = 0; i < nr_uarts; i++) |
1da177e4 LT |
2825 | if (uart_match_port(&serial8250_ports[i].port, port)) |
2826 | return &serial8250_ports[i]; | |
2827 | ||
2828 | /* | |
2829 | * We didn't find a matching entry, so look for the first | |
2830 | * free entry. We look for one which hasn't been previously | |
2831 | * used (indicated by zero iobase). | |
2832 | */ | |
a61c2d78 | 2833 | for (i = 0; i < nr_uarts; i++) |
1da177e4 LT |
2834 | if (serial8250_ports[i].port.type == PORT_UNKNOWN && |
2835 | serial8250_ports[i].port.iobase == 0) | |
2836 | return &serial8250_ports[i]; | |
2837 | ||
2838 | /* | |
2839 | * That also failed. Last resort is to find any entry which | |
2840 | * doesn't have a real port associated with it. | |
2841 | */ | |
a61c2d78 | 2842 | for (i = 0; i < nr_uarts; i++) |
1da177e4 LT |
2843 | if (serial8250_ports[i].port.type == PORT_UNKNOWN) |
2844 | return &serial8250_ports[i]; | |
2845 | ||
2846 | return NULL; | |
2847 | } | |
2848 | ||
2849 | /** | |
2850 | * serial8250_register_port - register a serial port | |
2851 | * @port: serial port template | |
2852 | * | |
2853 | * Configure the serial port specified by the request. If the | |
2854 | * port exists and is in use, it is hung up and unregistered | |
2855 | * first. | |
2856 | * | |
2857 | * The port is then probed and if necessary the IRQ is autodetected | |
2858 | * If this fails an error is returned. | |
2859 | * | |
2860 | * On success the port is ready to use and the line number is returned. | |
2861 | */ | |
2862 | int serial8250_register_port(struct uart_port *port) | |
2863 | { | |
2864 | struct uart_8250_port *uart; | |
2865 | int ret = -ENOSPC; | |
2866 | ||
2867 | if (port->uartclk == 0) | |
2868 | return -EINVAL; | |
2869 | ||
f392ecfa | 2870 | mutex_lock(&serial_mutex); |
1da177e4 LT |
2871 | |
2872 | uart = serial8250_find_match_or_unused(port); | |
2873 | if (uart) { | |
2874 | uart_remove_one_port(&serial8250_reg, &uart->port); | |
2875 | ||
74a19741 WN |
2876 | uart->port.iobase = port->iobase; |
2877 | uart->port.membase = port->membase; | |
2878 | uart->port.irq = port->irq; | |
2879 | uart->port.uartclk = port->uartclk; | |
2880 | uart->port.fifosize = port->fifosize; | |
2881 | uart->port.regshift = port->regshift; | |
2882 | uart->port.iotype = port->iotype; | |
2883 | uart->port.flags = port->flags | UPF_BOOT_AUTOCONF; | |
2884 | uart->port.mapbase = port->mapbase; | |
2885 | uart->port.private_data = port->private_data; | |
1da177e4 LT |
2886 | if (port->dev) |
2887 | uart->port.dev = port->dev; | |
2888 | ||
2889 | ret = uart_add_one_port(&serial8250_reg, &uart->port); | |
2890 | if (ret == 0) | |
2891 | ret = uart->port.line; | |
2892 | } | |
f392ecfa | 2893 | mutex_unlock(&serial_mutex); |
1da177e4 LT |
2894 | |
2895 | return ret; | |
2896 | } | |
2897 | EXPORT_SYMBOL(serial8250_register_port); | |
2898 | ||
2899 | /** | |
2900 | * serial8250_unregister_port - remove a 16x50 serial port at runtime | |
2901 | * @line: serial line number | |
2902 | * | |
2903 | * Remove one serial port. This may not be called from interrupt | |
2904 | * context. We hand the port back to the our control. | |
2905 | */ | |
2906 | void serial8250_unregister_port(int line) | |
2907 | { | |
2908 | struct uart_8250_port *uart = &serial8250_ports[line]; | |
2909 | ||
f392ecfa | 2910 | mutex_lock(&serial_mutex); |
1da177e4 LT |
2911 | uart_remove_one_port(&serial8250_reg, &uart->port); |
2912 | if (serial8250_isa_devs) { | |
2913 | uart->port.flags &= ~UPF_BOOT_AUTOCONF; | |
2914 | uart->port.type = PORT_UNKNOWN; | |
2915 | uart->port.dev = &serial8250_isa_devs->dev; | |
2916 | uart_add_one_port(&serial8250_reg, &uart->port); | |
2917 | } else { | |
2918 | uart->port.dev = NULL; | |
2919 | } | |
f392ecfa | 2920 | mutex_unlock(&serial_mutex); |
1da177e4 LT |
2921 | } |
2922 | EXPORT_SYMBOL(serial8250_unregister_port); | |
2923 | ||
2924 | static int __init serial8250_init(void) | |
2925 | { | |
2926 | int ret, i; | |
2927 | ||
a61c2d78 DJ |
2928 | if (nr_uarts > UART_NR) |
2929 | nr_uarts = UART_NR; | |
2930 | ||
1da177e4 | 2931 | printk(KERN_INFO "Serial: 8250/16550 driver $Revision: 1.90 $ " |
a61c2d78 | 2932 | "%d ports, IRQ sharing %sabled\n", nr_uarts, |
1da177e4 LT |
2933 | share_irqs ? "en" : "dis"); |
2934 | ||
2935 | for (i = 0; i < NR_IRQS; i++) | |
2936 | spin_lock_init(&irq_lists[i].lock); | |
2937 | ||
2938 | ret = uart_register_driver(&serial8250_reg); | |
2939 | if (ret) | |
2940 | goto out; | |
2941 | ||
7493a314 DT |
2942 | serial8250_isa_devs = platform_device_alloc("serial8250", |
2943 | PLAT8250_DEV_LEGACY); | |
2944 | if (!serial8250_isa_devs) { | |
2945 | ret = -ENOMEM; | |
bc965a7f | 2946 | goto unreg_uart_drv; |
1da177e4 LT |
2947 | } |
2948 | ||
7493a314 DT |
2949 | ret = platform_device_add(serial8250_isa_devs); |
2950 | if (ret) | |
2951 | goto put_dev; | |
2952 | ||
1da177e4 LT |
2953 | serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev); |
2954 | ||
bc965a7f RK |
2955 | ret = platform_driver_register(&serial8250_isa_driver); |
2956 | if (ret == 0) | |
2957 | goto out; | |
1da177e4 | 2958 | |
bc965a7f | 2959 | platform_device_del(serial8250_isa_devs); |
7493a314 DT |
2960 | put_dev: |
2961 | platform_device_put(serial8250_isa_devs); | |
7493a314 | 2962 | unreg_uart_drv: |
1da177e4 LT |
2963 | uart_unregister_driver(&serial8250_reg); |
2964 | out: | |
2965 | return ret; | |
2966 | } | |
2967 | ||
2968 | static void __exit serial8250_exit(void) | |
2969 | { | |
2970 | struct platform_device *isa_dev = serial8250_isa_devs; | |
2971 | ||
2972 | /* | |
2973 | * This tells serial8250_unregister_port() not to re-register | |
2974 | * the ports (thereby making serial8250_isa_driver permanently | |
2975 | * in use.) | |
2976 | */ | |
2977 | serial8250_isa_devs = NULL; | |
2978 | ||
3ae5eaec | 2979 | platform_driver_unregister(&serial8250_isa_driver); |
1da177e4 LT |
2980 | platform_device_unregister(isa_dev); |
2981 | ||
2982 | uart_unregister_driver(&serial8250_reg); | |
2983 | } | |
2984 | ||
2985 | module_init(serial8250_init); | |
2986 | module_exit(serial8250_exit); | |
2987 | ||
2988 | EXPORT_SYMBOL(serial8250_suspend_port); | |
2989 | EXPORT_SYMBOL(serial8250_resume_port); | |
2990 | ||
2991 | MODULE_LICENSE("GPL"); | |
2992 | MODULE_DESCRIPTION("Generic 8250/16x50 serial driver $Revision: 1.90 $"); | |
2993 | ||
2994 | module_param(share_irqs, uint, 0644); | |
2995 | MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices" | |
2996 | " (unsafe)"); | |
2997 | ||
a61c2d78 DJ |
2998 | module_param(nr_uarts, uint, 0644); |
2999 | MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")"); | |
3000 | ||
1da177e4 LT |
3001 | #ifdef CONFIG_SERIAL_8250_RSA |
3002 | module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444); | |
3003 | MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA"); | |
3004 | #endif | |
3005 | MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR); |