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[SERIAL] Support Au1x00 8250 UARTs using the generic 8250 driver.
[deliverable/linux.git] / drivers / serial / 8250.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * $Id: 8250.c,v 1.90 2002/07/28 10:03:27 rmk Exp $
16 *
17 * A note about mapbase / membase
18 *
19 * mapbase is the physical address of the IO port.
20 * membase is an 'ioremapped' cookie.
21 */
22#include <linux/config.h>
23
24#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
25#define SUPPORT_SYSRQ
26#endif
27
28#include <linux/module.h>
29#include <linux/moduleparam.h>
30#include <linux/ioport.h>
31#include <linux/init.h>
32#include <linux/console.h>
33#include <linux/sysrq.h>
34#include <linux/mca.h>
35#include <linux/delay.h>
d052d1be 36#include <linux/platform_device.h>
1da177e4
LT		 37#include <linux/tty.h>
38#include <linux/tty_flip.h>
39#include <linux/serial_reg.h>
40#include <linux/serial_core.h>
41#include <linux/serial.h>
42#include <linux/serial_8250.h>
43
44#include <asm/io.h>
45#include <asm/irq.h>
46
47#include "8250.h"
48
49/*
50 * Configuration:
51 * share_irqs - whether we pass SA_SHIRQ to request_irq(). This option
52 * is unsafe when used on edge-triggered interrupts.
53 */
408b664a 54static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4
LT		 55
56/*
57 * Debugging.
58 */
59#if 0
60#define DEBUG_AUTOCONF(fmt...) printk(fmt)
61#else
62#define DEBUG_AUTOCONF(fmt...) do { } while (0)
63#endif
64
65#if 0
66#define DEBUG_INTR(fmt...) printk(fmt)
67#else
68#define DEBUG_INTR(fmt...) do { } while (0)
69#endif
70
71#define PASS_LIMIT 256
72
73/*
74 * We default to IRQ0 for the "no irq" hack. Some
75 * machine types want others as well - they're free
76 * to redefine this in their header file.
77 */
78#define is_real_interrupt(irq) ((irq) != 0)
79
1da177e4
LT		 80#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
81#define CONFIG_SERIAL_DETECT_IRQ 1
82#endif
1da177e4
LT		 83#ifdef CONFIG_SERIAL_8250_MANY_PORTS
84#define CONFIG_SERIAL_MANY_PORTS 1
85#endif
86
87/*
88 * HUB6 is always on. This will be removed once the header
89 * files have been cleaned.
90 */
91#define CONFIG_HUB6 1
92
93#include <asm/serial.h>
94
95/*
96 * SERIAL_PORT_DFNS tells us about built-in ports that have no
97 * standard enumeration mechanism. Platforms that can find all
98 * serial ports via mechanisms like ACPI or PCI need not supply it.
99 */
100#ifndef SERIAL_PORT_DFNS
101#define SERIAL_PORT_DFNS
102#endif
103
104static struct old_serial_port old_serial_port[] = {
105 SERIAL_PORT_DFNS /* defined in asm/serial.h */
106};
107
026d02a2 108#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 109
110#ifdef CONFIG_SERIAL_8250_RSA
111
112#define PORT_RSA_MAX 4
113static unsigned long probe_rsa[PORT_RSA_MAX];
114static unsigned int probe_rsa_count;
115#endif /* CONFIG_SERIAL_8250_RSA */
116
117struct uart_8250_port {
118 struct uart_port port;
119 struct timer_list timer; /* "no irq" timer */
120 struct list_head list; /* ports on this IRQ */
4ba5e35d
RK		 121 unsigned short capabilities; /* port capabilities */
122 unsigned short bugs; /* port bugs */
1da177e4 123 unsigned int tx_loadsz; /* transmit fifo load size */
1da177e4
LT		 124 unsigned char acr;
125 unsigned char ier;
126 unsigned char lcr;
127 unsigned char mcr;
128 unsigned char mcr_mask; /* mask of user bits */
129 unsigned char mcr_force; /* mask of forced bits */
130 unsigned char lsr_break_flag;
131
132 /*
133 * We provide a per-port pm hook.
134 */
135 void (*pm)(struct uart_port *port,
136 unsigned int state, unsigned int old);
137};
138
139struct irq_info {
140 spinlock_t lock;
141 struct list_head *head;
142};
143
144static struct irq_info irq_lists[NR_IRQS];
145
146/*
147 * Here we define the default xmit fifo size used for each type of UART.
148 */
149static const struct serial8250_config uart_config[] = {
150 [PORT_UNKNOWN] = {
151 .name = "unknown",
152 .fifo_size = 1,
153 .tx_loadsz = 1,
154 },
155 [PORT_8250] = {
156 .name = "8250",
157 .fifo_size = 1,
158 .tx_loadsz = 1,
159 },
160 [PORT_16450] = {
161 .name = "16450",
162 .fifo_size = 1,
163 .tx_loadsz = 1,
164 },
165 [PORT_16550] = {
166 .name = "16550",
167 .fifo_size = 1,
168 .tx_loadsz = 1,
169 },
170 [PORT_16550A] = {
171 .name = "16550A",
172 .fifo_size = 16,
173 .tx_loadsz = 16,
174 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
175 .flags = UART_CAP_FIFO,
176 },
177 [PORT_CIRRUS] = {
178 .name = "Cirrus",
179 .fifo_size = 1,
180 .tx_loadsz = 1,
181 },
182 [PORT_16650] = {
183 .name = "ST16650",
184 .fifo_size = 1,
185 .tx_loadsz = 1,
186 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
187 },
188 [PORT_16650V2] = {
189 .name = "ST16650V2",
190 .fifo_size = 32,
191 .tx_loadsz = 16,
192 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
193 UART_FCR_T_TRIG_00,
194 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
195 },
196 [PORT_16750] = {
197 .name = "TI16750",
198 .fifo_size = 64,
199 .tx_loadsz = 64,
200 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
201 UART_FCR7_64BYTE,
202 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
203 },
204 [PORT_STARTECH] = {
205 .name = "Startech",
206 .fifo_size = 1,
207 .tx_loadsz = 1,
208 },
209 [PORT_16C950] = {
210 .name = "16C950/954",
211 .fifo_size = 128,
212 .tx_loadsz = 128,
213 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
214 .flags = UART_CAP_FIFO,
215 },
216 [PORT_16654] = {
217 .name = "ST16654",
218 .fifo_size = 64,
219 .tx_loadsz = 32,
220 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
221 UART_FCR_T_TRIG_10,
222 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
223 },
224 [PORT_16850] = {
225 .name = "XR16850",
226 .fifo_size = 128,
227 .tx_loadsz = 128,
228 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
229 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
230 },
231 [PORT_RSA] = {
232 .name = "RSA",
233 .fifo_size = 2048,
234 .tx_loadsz = 2048,
235 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
236 .flags = UART_CAP_FIFO,
237 },
238 [PORT_NS16550A] = {
239 .name = "NS16550A",
240 .fifo_size = 16,
241 .tx_loadsz = 16,
242 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
243 .flags = UART_CAP_FIFO | UART_NATSEMI,
244 },
245 [PORT_XSCALE] = {
246 .name = "XScale",
247 .fifo_size = 32,
248 .tx_loadsz = 32,
249 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
250 .flags = UART_CAP_FIFO | UART_CAP_UUE,
251 },
252};
253
21c614a7
PA		 254#ifdef CONFIG_SERIAL_8250_AU1X00
255
256/* Au1x00 UART hardware has a weird register layout */
257static const u8 au_io_in_map[] = {
258 [UART_RX] = 0,
259 [UART_IER] = 2,
260 [UART_IIR] = 3,
261 [UART_LCR] = 5,
262 [UART_MCR] = 6,
263 [UART_LSR] = 7,
264 [UART_MSR] = 8,
265};
266
267static const u8 au_io_out_map[] = {
268 [UART_TX] = 1,
269 [UART_IER] = 2,
270 [UART_FCR] = 4,
271 [UART_LCR] = 5,
272 [UART_MCR] = 6,
273};
274
275/* sane hardware needs no mapping */
276static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
277{
278 if (up->port.iotype != UPIO_AU)
279 return offset;
280 return au_io_in_map[offset];
281}
282
283static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
284{
285 if (up->port.iotype != UPIO_AU)
286 return offset;
287 return au_io_out_map[offset];
288}
289
290#else
291
292/* sane hardware needs no mapping */
293#define map_8250_in_reg(up, offset) (offset)
294#define map_8250_out_reg(up, offset) (offset)
295
296#endif
297
1da177e4
LT		 298static _INLINE_ unsigned int serial_in(struct uart_8250_port *up, int offset)
299{
21c614a7 300 offset = map_8250_in_reg(up, offset) << up->port.regshift;
1da177e4
LT		 301
302 switch (up->port.iotype) {
303 case UPIO_HUB6:
304 outb(up->port.hub6 - 1 + offset, up->port.iobase);
305 return inb(up->port.iobase + 1);
306
307 case UPIO_MEM:
308 return readb(up->port.membase + offset);
309
310 case UPIO_MEM32:
311 return readl(up->port.membase + offset);
312
21c614a7
PA		 313#ifdef CONFIG_SERIAL_8250_AU1X00
314 case UPIO_AU:
315 return __raw_readl(up->port.membase + offset);
316#endif
317
1da177e4
LT		 318 default:
319 return inb(up->port.iobase + offset);
320 }
321}
322
323static _INLINE_ void
324serial_out(struct uart_8250_port *up, int offset, int value)
325{
21c614a7 326 offset = map_8250_out_reg(up, offset) << up->port.regshift;
1da177e4
LT		 327
328 switch (up->port.iotype) {
329 case UPIO_HUB6:
330 outb(up->port.hub6 - 1 + offset, up->port.iobase);
331 outb(value, up->port.iobase + 1);
332 break;
333
334 case UPIO_MEM:
335 writeb(value, up->port.membase + offset);
336 break;
337
338 case UPIO_MEM32:
339 writel(value, up->port.membase + offset);
340 break;
341
21c614a7
PA		 342#ifdef CONFIG_SERIAL_8250_AU1X00
343 case UPIO_AU:
344 __raw_writel(value, up->port.membase + offset);
345 break;
346#endif
347
1da177e4
LT		 348 default:
349 outb(value, up->port.iobase + offset);
350 }
351}
352
353/*
354 * We used to support using pause I/O for certain machines. We
355 * haven't supported this for a while, but just in case it's badly
356 * needed for certain old 386 machines, I've left these #define's
357 * in....
358 */
359#define serial_inp(up, offset) serial_in(up, offset)
360#define serial_outp(up, offset, value) serial_out(up, offset, value)
361
362
363/*
364 * For the 16C950
365 */
366static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
367{
368 serial_out(up, UART_SCR, offset);
369 serial_out(up, UART_ICR, value);
370}
371
372static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
373{
374 unsigned int value;
375
376 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
377 serial_out(up, UART_SCR, offset);
378 value = serial_in(up, UART_ICR);
379 serial_icr_write(up, UART_ACR, up->acr);
380
381 return value;
382}
383
384/*
385 * FIFO support.
386 */
387static inline void serial8250_clear_fifos(struct uart_8250_port *p)
388{
389 if (p->capabilities & UART_CAP_FIFO) {
390 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
391 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
392 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
393 serial_outp(p, UART_FCR, 0);
394 }
395}
396
397/*
398 * IER sleep support. UARTs which have EFRs need the "extended
399 * capability" bit enabled. Note that on XR16C850s, we need to
400 * reset LCR to write to IER.
401 */
402static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
403{
404 if (p->capabilities & UART_CAP_SLEEP) {
405 if (p->capabilities & UART_CAP_EFR) {
406 serial_outp(p, UART_LCR, 0xBF);
407 serial_outp(p, UART_EFR, UART_EFR_ECB);
408 serial_outp(p, UART_LCR, 0);
409 }
410 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
411 if (p->capabilities & UART_CAP_EFR) {
412 serial_outp(p, UART_LCR, 0xBF);
413 serial_outp(p, UART_EFR, 0);
414 serial_outp(p, UART_LCR, 0);
415 }
416 }
417}
418
419#ifdef CONFIG_SERIAL_8250_RSA
420/*
421 * Attempts to turn on the RSA FIFO. Returns zero on failure.
422 * We set the port uart clock rate if we succeed.
423 */
424static int __enable_rsa(struct uart_8250_port *up)
425{
426 unsigned char mode;
427 int result;
428
429 mode = serial_inp(up, UART_RSA_MSR);
430 result = mode & UART_RSA_MSR_FIFO;
431
432 if (!result) {
433 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
434 mode = serial_inp(up, UART_RSA_MSR);
435 result = mode & UART_RSA_MSR_FIFO;
436 }
437
438 if (result)
439 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
440
441 return result;
442}
443
444static void enable_rsa(struct uart_8250_port *up)
445{
446 if (up->port.type == PORT_RSA) {
447 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
448 spin_lock_irq(&up->port.lock);
449 __enable_rsa(up);
450 spin_unlock_irq(&up->port.lock);
451 }
452 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
453 serial_outp(up, UART_RSA_FRR, 0);
454 }
455}
456
457/*
458 * Attempts to turn off the RSA FIFO. Returns zero on failure.
459 * It is unknown why interrupts were disabled in here. However,
460 * the caller is expected to preserve this behaviour by grabbing
461 * the spinlock before calling this function.
462 */
463static void disable_rsa(struct uart_8250_port *up)
464{
465 unsigned char mode;
466 int result;
467
468 if (up->port.type == PORT_RSA &&
469 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
470 spin_lock_irq(&up->port.lock);
471
472 mode = serial_inp(up, UART_RSA_MSR);
473 result = !(mode & UART_RSA_MSR_FIFO);
474
475 if (!result) {
476 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
477 mode = serial_inp(up, UART_RSA_MSR);
478 result = !(mode & UART_RSA_MSR_FIFO);
479 }
480
481 if (result)
482 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
483 spin_unlock_irq(&up->port.lock);
484 }
485}
486#endif /* CONFIG_SERIAL_8250_RSA */
487
488/*
489 * This is a quickie test to see how big the FIFO is.
490 * It doesn't work at all the time, more's the pity.
491 */
492static int size_fifo(struct uart_8250_port *up)
493{
494 unsigned char old_fcr, old_mcr, old_dll, old_dlm, old_lcr;
495 int count;
496
497 old_lcr = serial_inp(up, UART_LCR);
498 serial_outp(up, UART_LCR, 0);
499 old_fcr = serial_inp(up, UART_FCR);
500 old_mcr = serial_inp(up, UART_MCR);
501 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
502 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
503 serial_outp(up, UART_MCR, UART_MCR_LOOP);
504 serial_outp(up, UART_LCR, UART_LCR_DLAB);
505 old_dll = serial_inp(up, UART_DLL);
506 old_dlm = serial_inp(up, UART_DLM);
507 serial_outp(up, UART_DLL, 0x01);
508 serial_outp(up, UART_DLM, 0x00);
509 serial_outp(up, UART_LCR, 0x03);
510 for (count = 0; count < 256; count++)
511 serial_outp(up, UART_TX, count);
512 mdelay(20);/* FIXME - schedule_timeout */
513 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
514 (count < 256); count++)
515 serial_inp(up, UART_RX);
516 serial_outp(up, UART_FCR, old_fcr);
517 serial_outp(up, UART_MCR, old_mcr);
518 serial_outp(up, UART_LCR, UART_LCR_DLAB);
519 serial_outp(up, UART_DLL, old_dll);
520 serial_outp(up, UART_DLM, old_dlm);
521 serial_outp(up, UART_LCR, old_lcr);
522
523 return count;
524}
525
526/*
527 * Read UART ID using the divisor method - set DLL and DLM to zero
528 * and the revision will be in DLL and device type in DLM. We
529 * preserve the device state across this.
530 */
531static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
532{
533 unsigned char old_dll, old_dlm, old_lcr;
534 unsigned int id;
535
536 old_lcr = serial_inp(p, UART_LCR);
537 serial_outp(p, UART_LCR, UART_LCR_DLAB);
538
539 old_dll = serial_inp(p, UART_DLL);
540 old_dlm = serial_inp(p, UART_DLM);
541
542 serial_outp(p, UART_DLL, 0);
543 serial_outp(p, UART_DLM, 0);
544
545 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
546
547 serial_outp(p, UART_DLL, old_dll);
548 serial_outp(p, UART_DLM, old_dlm);
549 serial_outp(p, UART_LCR, old_lcr);
550
551 return id;
552}
553
554/*
555 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
556 * When this function is called we know it is at least a StarTech
557 * 16650 V2, but it might be one of several StarTech UARTs, or one of
558 * its clones. (We treat the broken original StarTech 16650 V1 as a
559 * 16550, and why not? Startech doesn't seem to even acknowledge its
560 * existence.)
561 *
562 * What evil have men's minds wrought...
563 */
564static void autoconfig_has_efr(struct uart_8250_port *up)
565{
566 unsigned int id1, id2, id3, rev;
567
568 /*
569 * Everything with an EFR has SLEEP
570 */
571 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
572
573 /*
574 * First we check to see if it's an Oxford Semiconductor UART.
575 *
576 * If we have to do this here because some non-National
577 * Semiconductor clone chips lock up if you try writing to the
578 * LSR register (which serial_icr_read does)
579 */
580
581 /*
582 * Check for Oxford Semiconductor 16C950.
583 *
584 * EFR [4] must be set else this test fails.
585 *
586 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
587 * claims that it's needed for 952 dual UART's (which are not
588 * recommended for new designs).
589 */
590 up->acr = 0;
591 serial_out(up, UART_LCR, 0xBF);
592 serial_out(up, UART_EFR, UART_EFR_ECB);
593 serial_out(up, UART_LCR, 0x00);
594 id1 = serial_icr_read(up, UART_ID1);
595 id2 = serial_icr_read(up, UART_ID2);
596 id3 = serial_icr_read(up, UART_ID3);
597 rev = serial_icr_read(up, UART_REV);
598
599 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
600
601 if (id1 == 0x16 && id2 == 0xC9 &&
602 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
603 up->port.type = PORT_16C950;
4ba5e35d
RK		 604
605 /*
606 * Enable work around for the Oxford Semiconductor 952 rev B
607 * chip which causes it to seriously miscalculate baud rates
608 * when DLL is 0.
609 */
610 if (id3 == 0x52 && rev == 0x01)
611 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 612 return;
613 }
614
615 /*
616 * We check for a XR16C850 by setting DLL and DLM to 0, and then
617 * reading back DLL and DLM. The chip type depends on the DLM
618 * value read back:
619 * 0x10 - XR16C850 and the DLL contains the chip revision.
620 * 0x12 - XR16C2850.
621 * 0x14 - XR16C854.
622 */
623 id1 = autoconfig_read_divisor_id(up);
624 DEBUG_AUTOCONF("850id=%04x ", id1);
625
626 id2 = id1 >> 8;
627 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 628 up->port.type = PORT_16850;
629 return;
630 }
631
632 /*
633 * It wasn't an XR16C850.
634 *
635 * We distinguish between the '654 and the '650 by counting
636 * how many bytes are in the FIFO. I'm using this for now,
637 * since that's the technique that was sent to me in the
638 * serial driver update, but I'm not convinced this works.
639 * I've had problems doing this in the past. -TYT
640 */
641 if (size_fifo(up) == 64)
642 up->port.type = PORT_16654;
643 else
644 up->port.type = PORT_16650V2;
645}
646
647/*
648 * We detected a chip without a FIFO. Only two fall into
649 * this category - the original 8250 and the 16450. The
650 * 16450 has a scratch register (accessible with LCR=0)
651 */
652static void autoconfig_8250(struct uart_8250_port *up)
653{
654 unsigned char scratch, status1, status2;
655
656 up->port.type = PORT_8250;
657
658 scratch = serial_in(up, UART_SCR);
659 serial_outp(up, UART_SCR, 0xa5);
660 status1 = serial_in(up, UART_SCR);
661 serial_outp(up, UART_SCR, 0x5a);
662 status2 = serial_in(up, UART_SCR);
663 serial_outp(up, UART_SCR, scratch);
664
665 if (status1 == 0xa5 && status2 == 0x5a)
666 up->port.type = PORT_16450;
667}
668
669static int broken_efr(struct uart_8250_port *up)
670{
671 /*
672 * Exar ST16C2550 "A2" devices incorrectly detect as
673 * having an EFR, and report an ID of 0x0201. See
674 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
675 */
676 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
677 return 1;
678
679 return 0;
680}
681
682/*
683 * We know that the chip has FIFOs. Does it have an EFR? The
684 * EFR is located in the same register position as the IIR and
685 * we know the top two bits of the IIR are currently set. The
686 * EFR should contain zero. Try to read the EFR.
687 */
688static void autoconfig_16550a(struct uart_8250_port *up)
689{
690 unsigned char status1, status2;
691 unsigned int iersave;
692
693 up->port.type = PORT_16550A;
694 up->capabilities |= UART_CAP_FIFO;
695
696 /*
697 * Check for presence of the EFR when DLAB is set.
698 * Only ST16C650V1 UARTs pass this test.
699 */
700 serial_outp(up, UART_LCR, UART_LCR_DLAB);
701 if (serial_in(up, UART_EFR) == 0) {
702 serial_outp(up, UART_EFR, 0xA8);
703 if (serial_in(up, UART_EFR) != 0) {
704 DEBUG_AUTOCONF("EFRv1 ");
705 up->port.type = PORT_16650;
706 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
707 } else {
708 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
709 }
710 serial_outp(up, UART_EFR, 0);
711 return;
712 }
713
714 /*
715 * Maybe it requires 0xbf to be written to the LCR.
716 * (other ST16C650V2 UARTs, TI16C752A, etc)
717 */
718 serial_outp(up, UART_LCR, 0xBF);
719 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
720 DEBUG_AUTOCONF("EFRv2 ");
721 autoconfig_has_efr(up);
722 return;
723 }
724
725 /*
726 * Check for a National Semiconductor SuperIO chip.
727 * Attempt to switch to bank 2, read the value of the LOOP bit
728 * from EXCR1. Switch back to bank 0, change it in MCR. Then
729 * switch back to bank 2, read it from EXCR1 again and check
730 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4
LT		 731 */
732 serial_outp(up, UART_LCR, 0);
733 status1 = serial_in(up, UART_MCR);
734 serial_outp(up, UART_LCR, 0xE0);
735 status2 = serial_in(up, 0x02); /* EXCR1 */
736
737 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
738 serial_outp(up, UART_LCR, 0);
739 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
740 serial_outp(up, UART_LCR, 0xE0);
741 status2 = serial_in(up, 0x02); /* EXCR1 */
742 serial_outp(up, UART_LCR, 0);
743 serial_outp(up, UART_MCR, status1);
744
745 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 746 unsigned short quot;
747
1da177e4 748 serial_outp(up, UART_LCR, 0xE0);
857dde2e
DW		 749
750 quot = serial_inp(up, UART_DLM) << 8;
751 quot += serial_inp(up, UART_DLL);
752 quot <<= 3;
753
1da177e4
LT		 754 status1 = serial_in(up, 0x04); /* EXCR1 */
755 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
756 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
757 serial_outp(up, 0x04, status1);
857dde2e
DW		 758
759 serial_outp(up, UART_DLL, quot & 0xff);
760 serial_outp(up, UART_DLM, quot >> 8);
761
1da177e4 762 serial_outp(up, UART_LCR, 0);
1da177e4 763
857dde2e 764 up->port.uartclk = 921600*16;
1da177e4
LT		 765 up->port.type = PORT_NS16550A;
766 up->capabilities |= UART_NATSEMI;
767 return;
768 }
769 }
770
771 /*
772 * No EFR. Try to detect a TI16750, which only sets bit 5 of
773 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
774 * Try setting it with and without DLAB set. Cheap clones
775 * set bit 5 without DLAB set.
776 */
777 serial_outp(up, UART_LCR, 0);
778 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
779 status1 = serial_in(up, UART_IIR) >> 5;
780 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
781 serial_outp(up, UART_LCR, UART_LCR_DLAB);
782 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
783 status2 = serial_in(up, UART_IIR) >> 5;
784 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
785 serial_outp(up, UART_LCR, 0);
786
787 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
788
789 if (status1 == 6 && status2 == 7) {
790 up->port.type = PORT_16750;
791 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
792 return;
793 }
794
795 /*
796 * Try writing and reading the UART_IER_UUE bit (b6).
797 * If it works, this is probably one of the Xscale platform's
798 * internal UARTs.
799 * We're going to explicitly set the UUE bit to 0 before
800 * trying to write and read a 1 just to make sure it's not
801 * already a 1 and maybe locked there before we even start start.
802 */
803 iersave = serial_in(up, UART_IER);
804 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
805 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
806 /*
807 * OK it's in a known zero state, try writing and reading
808 * without disturbing the current state of the other bits.
809 */
810 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
811 if (serial_in(up, UART_IER) & UART_IER_UUE) {
812 /*
813 * It's an Xscale.
814 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
815 */
816 DEBUG_AUTOCONF("Xscale ");
817 up->port.type = PORT_XSCALE;
818 up->capabilities |= UART_CAP_UUE;
819 return;
820 }
821 } else {
822 /*
823 * If we got here we couldn't force the IER_UUE bit to 0.
824 * Log it and continue.
825 */
826 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
827 }
828 serial_outp(up, UART_IER, iersave);
829}
830
831/*
832 * This routine is called by rs_init() to initialize a specific serial
833 * port. It determines what type of UART chip this serial port is
834 * using: 8250, 16450, 16550, 16550A. The important question is
835 * whether or not this UART is a 16550A or not, since this will
836 * determine whether or not we can use its FIFO features or not.
837 */
838static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
839{
840 unsigned char status1, scratch, scratch2, scratch3;
841 unsigned char save_lcr, save_mcr;
842 unsigned long flags;
843
844 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
845 return;
846
847 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
848 up->port.line, up->port.iobase, up->port.membase);
849
850 /*
851 * We really do need global IRQs disabled here - we're going to
852 * be frobbing the chips IRQ enable register to see if it exists.
853 */
854 spin_lock_irqsave(&up->port.lock, flags);
855// save_flags(flags); cli();
856
857 up->capabilities = 0;
4ba5e35d 858 up->bugs = 0;
1da177e4
LT		 859
860 if (!(up->port.flags & UPF_BUGGY_UART)) {
861 /*
862 * Do a simple existence test first; if we fail this,
863 * there's no point trying anything else.
864 *
865 * 0x80 is used as a nonsense port to prevent against
866 * false positives due to ISA bus float. The
867 * assumption is that 0x80 is a non-existent port;
868 * which should be safe since include/asm/io.h also
869 * makes this assumption.
870 *
871 * Note: this is safe as long as MCR bit 4 is clear
872 * and the device is in "PC" mode.
873 */
874 scratch = serial_inp(up, UART_IER);
875 serial_outp(up, UART_IER, 0);
876#ifdef __i386__
877 outb(0xff, 0x080);
878#endif
879 scratch2 = serial_inp(up, UART_IER);
880 serial_outp(up, UART_IER, 0x0F);
881#ifdef __i386__
882 outb(0, 0x080);
883#endif
884 scratch3 = serial_inp(up, UART_IER);
885 serial_outp(up, UART_IER, scratch);
886 if (scratch2 != 0 || scratch3 != 0x0F) {
887 /*
888 * We failed; there's nothing here
889 */
890 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
891 scratch2, scratch3);
892 goto out;
893 }
894 }
895
896 save_mcr = serial_in(up, UART_MCR);
897 save_lcr = serial_in(up, UART_LCR);
898
899 /*
900 * Check to see if a UART is really there. Certain broken
901 * internal modems based on the Rockwell chipset fail this
902 * test, because they apparently don't implement the loopback
903 * test mode. So this test is skipped on the COM 1 through
904 * COM 4 ports. This *should* be safe, since no board
905 * manufacturer would be stupid enough to design a board
906 * that conflicts with COM 1-4 --- we hope!
907 */
908 if (!(up->port.flags & UPF_SKIP_TEST)) {
909 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
910 status1 = serial_inp(up, UART_MSR) & 0xF0;
911 serial_outp(up, UART_MCR, save_mcr);
912 if (status1 != 0x90) {
913 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
914 status1);
915 goto out;
916 }
917 }
918
919 /*
920 * We're pretty sure there's a port here. Lets find out what
921 * type of port it is. The IIR top two bits allows us to find
6f0d618f 922 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 923 * determines what we test for next.
924 *
925 * We also initialise the EFR (if any) to zero for later. The
926 * EFR occupies the same register location as the FCR and IIR.
927 */
928 serial_outp(up, UART_LCR, 0xBF);
929 serial_outp(up, UART_EFR, 0);
930 serial_outp(up, UART_LCR, 0);
931
932 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
933 scratch = serial_in(up, UART_IIR) >> 6;
934
935 DEBUG_AUTOCONF("iir=%d ", scratch);
936
937 switch (scratch) {
938 case 0:
939 autoconfig_8250(up);
940 break;
941 case 1:
942 up->port.type = PORT_UNKNOWN;
943 break;
944 case 2:
945 up->port.type = PORT_16550;
946 break;
947 case 3:
948 autoconfig_16550a(up);
949 break;
950 }
951
952#ifdef CONFIG_SERIAL_8250_RSA
953 /*
954 * Only probe for RSA ports if we got the region.
955 */
956 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
957 int i;
958
959 for (i = 0 ; i < probe_rsa_count; ++i) {
960 if (probe_rsa[i] == up->port.iobase &&
961 __enable_rsa(up)) {
962 up->port.type = PORT_RSA;
963 break;
964 }
965 }
966 }
967#endif
21c614a7
PA		 968
969#ifdef CONFIG_SERIAL_8250_AU1X00
970 /* if access method is AU, it is a 16550 with a quirk */
971 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
972 up->bugs |= UART_BUG_NOMSR;
973#endif
974
1da177e4
LT		 975 serial_outp(up, UART_LCR, save_lcr);
976
977 if (up->capabilities != uart_config[up->port.type].flags) {
978 printk(KERN_WARNING
979 "ttyS%d: detected caps %08x should be %08x\n",
980 up->port.line, up->capabilities,
981 uart_config[up->port.type].flags);
982 }
983
984 up->port.fifosize = uart_config[up->port.type].fifo_size;
985 up->capabilities = uart_config[up->port.type].flags;
986 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
987
988 if (up->port.type == PORT_UNKNOWN)
989 goto out;
990
991 /*
992 * Reset the UART.
993 */
994#ifdef CONFIG_SERIAL_8250_RSA
995 if (up->port.type == PORT_RSA)
996 serial_outp(up, UART_RSA_FRR, 0);
997#endif
998 serial_outp(up, UART_MCR, save_mcr);
999 serial8250_clear_fifos(up);
1000 (void)serial_in(up, UART_RX);
1001 serial_outp(up, UART_IER, 0);
1002
1003 out:
1004 spin_unlock_irqrestore(&up->port.lock, flags);
1005// restore_flags(flags);
1006 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1007}
1008
1009static void autoconfig_irq(struct uart_8250_port *up)
1010{
1011 unsigned char save_mcr, save_ier;
1012 unsigned char save_ICP = 0;
1013 unsigned int ICP = 0;
1014 unsigned long irqs;
1015 int irq;
1016
1017 if (up->port.flags & UPF_FOURPORT) {
1018 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1019 save_ICP = inb_p(ICP);
1020 outb_p(0x80, ICP);
1021 (void) inb_p(ICP);
1022 }
1023
1024 /* forget possible initially masked and pending IRQ */
1025 probe_irq_off(probe_irq_on());
1026 save_mcr = serial_inp(up, UART_MCR);
1027 save_ier = serial_inp(up, UART_IER);
1028 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1029
1030 irqs = probe_irq_on();
1031 serial_outp(up, UART_MCR, 0);
1032 udelay (10);
1033 if (up->port.flags & UPF_FOURPORT) {
1034 serial_outp(up, UART_MCR,
1035 UART_MCR_DTR | UART_MCR_RTS);
1036 } else {
1037 serial_outp(up, UART_MCR,
1038 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1039 }
1040 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1041 (void)serial_inp(up, UART_LSR);
1042 (void)serial_inp(up, UART_RX);
1043 (void)serial_inp(up, UART_IIR);
1044 (void)serial_inp(up, UART_MSR);
1045 serial_outp(up, UART_TX, 0xFF);
1046 udelay (20);
1047 irq = probe_irq_off(irqs);
1048
1049 serial_outp(up, UART_MCR, save_mcr);
1050 serial_outp(up, UART_IER, save_ier);
1051
1052 if (up->port.flags & UPF_FOURPORT)
1053 outb_p(save_ICP, ICP);
1054
1055 up->port.irq = (irq > 0) ? irq : 0;
1056}
1057
e763b90c
RK		 1058static inline void __stop_tx(struct uart_8250_port *p)
1059{
1060 if (p->ier & UART_IER_THRI) {
1061 p->ier &= ~UART_IER_THRI;
1062 serial_out(p, UART_IER, p->ier);
1063 }
1064}
1065
b129a8cc 1066static void serial8250_stop_tx(struct uart_port *port)
1da177e4
LT		 1067{
1068 struct uart_8250_port *up = (struct uart_8250_port *)port;
1069
e763b90c 1070 __stop_tx(up);
1da177e4
LT		 1071
1072 /*
e763b90c 1073 * We really want to stop the transmitter from sending.
1da177e4 1074 */
e763b90c 1075 if (up->port.type == PORT_16C950) {
1da177e4
LT		 1076 up->acr |= UART_ACR_TXDIS;
1077 serial_icr_write(up, UART_ACR, up->acr);
1078 }
1079}
1080
55d3b282
RK		 1081static void transmit_chars(struct uart_8250_port *up);
1082
b129a8cc 1083static void serial8250_start_tx(struct uart_port *port)
1da177e4
LT		 1084{
1085 struct uart_8250_port *up = (struct uart_8250_port *)port;
1086
1087 if (!(up->ier & UART_IER_THRI)) {
1088 up->ier |= UART_IER_THRI;
1089 serial_out(up, UART_IER, up->ier);
55d3b282 1090
67f7654e 1091 if (up->bugs & UART_BUG_TXEN) {
55d3b282
RK		 1092 unsigned char lsr, iir;
1093 lsr = serial_in(up, UART_LSR);
1094 iir = serial_in(up, UART_IIR);
1095 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT)
1096 transmit_chars(up);
1097 }
1da177e4 1098 }
e763b90c 1099
1da177e4 1100 /*
e763b90c 1101 * Re-enable the transmitter if we disabled it.
1da177e4 1102 */
e763b90c 1103 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1104 up->acr &= ~UART_ACR_TXDIS;
1105 serial_icr_write(up, UART_ACR, up->acr);
1106 }
1107}
1108
1109static void serial8250_stop_rx(struct uart_port *port)
1110{
1111 struct uart_8250_port *up = (struct uart_8250_port *)port;
1112
1113 up->ier &= ~UART_IER_RLSI;
1114 up->port.read_status_mask &= ~UART_LSR_DR;
1115 serial_out(up, UART_IER, up->ier);
1116}
1117
1118static void serial8250_enable_ms(struct uart_port *port)
1119{
1120 struct uart_8250_port *up = (struct uart_8250_port *)port;
1121
21c614a7
PA		 1122 /* no MSR capabilities */
1123 if (up->bugs & UART_BUG_NOMSR)
1124 return;
1125
1da177e4
LT		 1126 up->ier |= UART_IER_MSI;
1127 serial_out(up, UART_IER, up->ier);
1128}
1129
1130static _INLINE_ void
1131receive_chars(struct uart_8250_port *up, int *status, struct pt_regs *regs)
1132{
1133 struct tty_struct *tty = up->port.info->tty;
1134 unsigned char ch, lsr = *status;
1135 int max_count = 256;
1136 char flag;
1137
1138 do {
1139 /* The following is not allowed by the tty layer and
1140 unsafe. It should be fixed ASAP */
1141 if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) {
1142 if (tty->low_latency) {
1143 spin_unlock(&up->port.lock);
1144 tty_flip_buffer_push(tty);
1145 spin_lock(&up->port.lock);
1146 }
23907eb8
RK		 1147 /*
1148 * If this failed then we will throw away the
1149 * bytes but must do so to clear interrupts
1150 */
1da177e4
LT		 1151 }
1152 ch = serial_inp(up, UART_RX);
1153 flag = TTY_NORMAL;
1154 up->port.icount.rx++;
1155
1156#ifdef CONFIG_SERIAL_8250_CONSOLE
1157 /*
1158 * Recover the break flag from console xmit
1159 */
1160 if (up->port.line == up->port.cons->index) {
1161 lsr |= up->lsr_break_flag;
1162 up->lsr_break_flag = 0;
1163 }
1164#endif
1165
1166 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
1167 UART_LSR_FE | UART_LSR_OE))) {
1168 /*
1169 * For statistics only
1170 */
1171 if (lsr & UART_LSR_BI) {
1172 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1173 up->port.icount.brk++;
1174 /*
1175 * We do the SysRQ and SAK checking
1176 * here because otherwise the break
1177 * may get masked by ignore_status_mask
1178 * or read_status_mask.
1179 */
1180 if (uart_handle_break(&up->port))
1181 goto ignore_char;
1182 } else if (lsr & UART_LSR_PE)
1183 up->port.icount.parity++;
1184 else if (lsr & UART_LSR_FE)
1185 up->port.icount.frame++;
1186 if (lsr & UART_LSR_OE)
1187 up->port.icount.overrun++;
1188
1189 /*
23907eb8 1190 * Mask off conditions which should be ignored.
1da177e4
LT		 1191 */
1192 lsr &= up->port.read_status_mask;
1193
1194 if (lsr & UART_LSR_BI) {
1195 DEBUG_INTR("handling break....");
1196 flag = TTY_BREAK;
1197 } else if (lsr & UART_LSR_PE)
1198 flag = TTY_PARITY;
1199 else if (lsr & UART_LSR_FE)
1200 flag = TTY_FRAME;
1201 }
1202 if (uart_handle_sysrq_char(&up->port, ch, regs))
1203 goto ignore_char;
05ab3014
RK		 1204
1205 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1206
1da177e4
LT		 1207 ignore_char:
1208 lsr = serial_inp(up, UART_LSR);
1209 } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
1210 spin_unlock(&up->port.lock);
1211 tty_flip_buffer_push(tty);
1212 spin_lock(&up->port.lock);
1213 *status = lsr;
1214}
1215
1216static _INLINE_ void transmit_chars(struct uart_8250_port *up)
1217{
1218 struct circ_buf *xmit = &up->port.info->xmit;
1219 int count;
1220
1221 if (up->port.x_char) {
1222 serial_outp(up, UART_TX, up->port.x_char);
1223 up->port.icount.tx++;
1224 up->port.x_char = 0;
1225 return;
1226 }
b129a8cc
RK		 1227 if (uart_tx_stopped(&up->port)) {
1228 serial8250_stop_tx(&up->port);
1229 return;
1230 }
1231 if (uart_circ_empty(xmit)) {
e763b90c 1232 __stop_tx(up);
1da177e4
LT		 1233 return;
1234 }
1235
1236 count = up->tx_loadsz;
1237 do {
1238 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1239 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1240 up->port.icount.tx++;
1241 if (uart_circ_empty(xmit))
1242 break;
1243 } while (--count > 0);
1244
1245 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1246 uart_write_wakeup(&up->port);
1247
1248 DEBUG_INTR("THRE...");
1249
1250 if (uart_circ_empty(xmit))
e763b90c 1251 __stop_tx(up);
1da177e4
LT		 1252}
1253
1254static _INLINE_ void check_modem_status(struct uart_8250_port *up)
1255{
1256 int status;
1257
1258 status = serial_in(up, UART_MSR);
1259
1260 if ((status & UART_MSR_ANY_DELTA) == 0)
1261 return;
1262
1263 if (status & UART_MSR_TERI)
1264 up->port.icount.rng++;
1265 if (status & UART_MSR_DDSR)
1266 up->port.icount.dsr++;
1267 if (status & UART_MSR_DDCD)
1268 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1269 if (status & UART_MSR_DCTS)
1270 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1271
1272 wake_up_interruptible(&up->port.info->delta_msr_wait);
1273}
1274
1275/*
1276 * This handles the interrupt from one port.
1277 */
1278static inline void
1279serial8250_handle_port(struct uart_8250_port *up, struct pt_regs *regs)
1280{
1281 unsigned int status = serial_inp(up, UART_LSR);
1282
1283 DEBUG_INTR("status = %x...", status);
1284
1285 if (status & UART_LSR_DR)
1286 receive_chars(up, &status, regs);
1287 check_modem_status(up);
1288 if (status & UART_LSR_THRE)
1289 transmit_chars(up);
1290}
1291
1292/*
1293 * This is the serial driver's interrupt routine.
1294 *
1295 * Arjan thinks the old way was overly complex, so it got simplified.
1296 * Alan disagrees, saying that need the complexity to handle the weird
1297 * nature of ISA shared interrupts. (This is a special exception.)
1298 *
1299 * In order to handle ISA shared interrupts properly, we need to check
1300 * that all ports have been serviced, and therefore the ISA interrupt
1301 * line has been de-asserted.
1302 *
1303 * This means we need to loop through all ports. checking that they
1304 * don't have an interrupt pending.
1305 */
1306static irqreturn_t serial8250_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1307{
1308 struct irq_info *i = dev_id;
1309 struct list_head *l, *end = NULL;
1310 int pass_counter = 0, handled = 0;
1311
1312 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1313
1314 spin_lock(&i->lock);
1315
1316 l = i->head;
1317 do {
1318 struct uart_8250_port *up;
1319 unsigned int iir;
1320
1321 up = list_entry(l, struct uart_8250_port, list);
1322
1323 iir = serial_in(up, UART_IIR);
1324 if (!(iir & UART_IIR_NO_INT)) {
1325 spin_lock(&up->port.lock);
1326 serial8250_handle_port(up, regs);
1327 spin_unlock(&up->port.lock);
1328
1329 handled = 1;
1330
1331 end = NULL;
1332 } else if (end == NULL)
1333 end = l;
1334
1335 l = l->next;
1336
1337 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1338 /* If we hit this, we're dead. */
1339 printk(KERN_ERR "serial8250: too much work for "
1340 "irq%d\n", irq);
1341 break;
1342 }
1343 } while (l != end);
1344
1345 spin_unlock(&i->lock);
1346
1347 DEBUG_INTR("end.\n");
1348
1349 return IRQ_RETVAL(handled);
1350}
1351
1352/*
1353 * To support ISA shared interrupts, we need to have one interrupt
1354 * handler that ensures that the IRQ line has been deasserted
1355 * before returning. Failing to do this will result in the IRQ
1356 * line being stuck active, and, since ISA irqs are edge triggered,
1357 * no more IRQs will be seen.
1358 */
1359static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1360{
1361 spin_lock_irq(&i->lock);
1362
1363 if (!list_empty(i->head)) {
1364 if (i->head == &up->list)
1365 i->head = i->head->next;
1366 list_del(&up->list);
1367 } else {
1368 BUG_ON(i->head != &up->list);
1369 i->head = NULL;
1370 }
1371
1372 spin_unlock_irq(&i->lock);
1373}
1374
1375static int serial_link_irq_chain(struct uart_8250_port *up)
1376{
1377 struct irq_info *i = irq_lists + up->port.irq;
1378 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? SA_SHIRQ : 0;
1379
1380 spin_lock_irq(&i->lock);
1381
1382 if (i->head) {
1383 list_add(&up->list, i->head);
1384 spin_unlock_irq(&i->lock);
1385
1386 ret = 0;
1387 } else {
1388 INIT_LIST_HEAD(&up->list);
1389 i->head = &up->list;
1390 spin_unlock_irq(&i->lock);
1391
1392 ret = request_irq(up->port.irq, serial8250_interrupt,
1393 irq_flags, "serial", i);
1394 if (ret < 0)
1395 serial_do_unlink(i, up);
1396 }
1397
1398 return ret;
1399}
1400
1401static void serial_unlink_irq_chain(struct uart_8250_port *up)
1402{
1403 struct irq_info *i = irq_lists + up->port.irq;
1404
1405 BUG_ON(i->head == NULL);
1406
1407 if (list_empty(i->head))
1408 free_irq(up->port.irq, i);
1409
1410 serial_do_unlink(i, up);
1411}
1412
1413/*
1414 * This function is used to handle ports that do not have an
1415 * interrupt. This doesn't work very well for 16450's, but gives
1416 * barely passable results for a 16550A. (Although at the expense
1417 * of much CPU overhead).
1418 */
1419static void serial8250_timeout(unsigned long data)
1420{
1421 struct uart_8250_port *up = (struct uart_8250_port *)data;
1422 unsigned int timeout;
1423 unsigned int iir;
1424
1425 iir = serial_in(up, UART_IIR);
1426 if (!(iir & UART_IIR_NO_INT)) {
1427 spin_lock(&up->port.lock);
1428 serial8250_handle_port(up, NULL);
1429 spin_unlock(&up->port.lock);
1430 }
1431
1432 timeout = up->port.timeout;
1433 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1434 mod_timer(&up->timer, jiffies + timeout);
1435}
1436
1437static unsigned int serial8250_tx_empty(struct uart_port *port)
1438{
1439 struct uart_8250_port *up = (struct uart_8250_port *)port;
1440 unsigned long flags;
1441 unsigned int ret;
1442
1443 spin_lock_irqsave(&up->port.lock, flags);
1444 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1445 spin_unlock_irqrestore(&up->port.lock, flags);
1446
1447 return ret;
1448}
1449
1450static unsigned int serial8250_get_mctrl(struct uart_port *port)
1451{
1452 struct uart_8250_port *up = (struct uart_8250_port *)port;
1da177e4
LT		 1453 unsigned char status;
1454 unsigned int ret;
1455
1da177e4 1456 status = serial_in(up, UART_MSR);
1da177e4
LT		 1457
1458 ret = 0;
1459 if (status & UART_MSR_DCD)
1460 ret |= TIOCM_CAR;
1461 if (status & UART_MSR_RI)
1462 ret |= TIOCM_RNG;
1463 if (status & UART_MSR_DSR)
1464 ret |= TIOCM_DSR;
1465 if (status & UART_MSR_CTS)
1466 ret |= TIOCM_CTS;
1467 return ret;
1468}
1469
1470static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1471{
1472 struct uart_8250_port *up = (struct uart_8250_port *)port;
1473 unsigned char mcr = 0;
1474
1475 if (mctrl & TIOCM_RTS)
1476 mcr |= UART_MCR_RTS;
1477 if (mctrl & TIOCM_DTR)
1478 mcr |= UART_MCR_DTR;
1479 if (mctrl & TIOCM_OUT1)
1480 mcr |= UART_MCR_OUT1;
1481 if (mctrl & TIOCM_OUT2)
1482 mcr |= UART_MCR_OUT2;
1483 if (mctrl & TIOCM_LOOP)
1484 mcr |= UART_MCR_LOOP;
1485
1486 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1487
1488 serial_out(up, UART_MCR, mcr);
1489}
1490
1491static void serial8250_break_ctl(struct uart_port *port, int break_state)
1492{
1493 struct uart_8250_port *up = (struct uart_8250_port *)port;
1494 unsigned long flags;
1495
1496 spin_lock_irqsave(&up->port.lock, flags);
1497 if (break_state == -1)
1498 up->lcr |= UART_LCR_SBC;
1499 else
1500 up->lcr &= ~UART_LCR_SBC;
1501 serial_out(up, UART_LCR, up->lcr);
1502 spin_unlock_irqrestore(&up->port.lock, flags);
1503}
1504
1505static int serial8250_startup(struct uart_port *port)
1506{
1507 struct uart_8250_port *up = (struct uart_8250_port *)port;
1508 unsigned long flags;
55d3b282 1509 unsigned char lsr, iir;
1da177e4
LT		 1510 int retval;
1511
1512 up->capabilities = uart_config[up->port.type].flags;
1513 up->mcr = 0;
1514
1515 if (up->port.type == PORT_16C950) {
1516 /* Wake up and initialize UART */
1517 up->acr = 0;
1518 serial_outp(up, UART_LCR, 0xBF);
1519 serial_outp(up, UART_EFR, UART_EFR_ECB);
1520 serial_outp(up, UART_IER, 0);
1521 serial_outp(up, UART_LCR, 0);
1522 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1523 serial_outp(up, UART_LCR, 0xBF);
1524 serial_outp(up, UART_EFR, UART_EFR_ECB);
1525 serial_outp(up, UART_LCR, 0);
1526 }
1527
1528#ifdef CONFIG_SERIAL_8250_RSA
1529 /*
1530 * If this is an RSA port, see if we can kick it up to the
1531 * higher speed clock.
1532 */
1533 enable_rsa(up);
1534#endif
1535
1536 /*
1537 * Clear the FIFO buffers and disable them.
1538 * (they will be reeanbled in set_termios())
1539 */
1540 serial8250_clear_fifos(up);
1541
1542 /*
1543 * Clear the interrupt registers.
1544 */
1545 (void) serial_inp(up, UART_LSR);
1546 (void) serial_inp(up, UART_RX);
1547 (void) serial_inp(up, UART_IIR);
1548 (void) serial_inp(up, UART_MSR);
1549
1550 /*
1551 * At this point, there's no way the LSR could still be 0xff;
1552 * if it is, then bail out, because there's likely no UART
1553 * here.
1554 */
1555 if (!(up->port.flags & UPF_BUGGY_UART) &&
1556 (serial_inp(up, UART_LSR) == 0xff)) {
1557 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
1558 return -ENODEV;
1559 }
1560
1561 /*
1562 * For a XR16C850, we need to set the trigger levels
1563 */
1564 if (up->port.type == PORT_16850) {
1565 unsigned char fctr;
1566
1567 serial_outp(up, UART_LCR, 0xbf);
1568
1569 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1570 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1571 serial_outp(up, UART_TRG, UART_TRG_96);
1572 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1573 serial_outp(up, UART_TRG, UART_TRG_96);
1574
1575 serial_outp(up, UART_LCR, 0);
1576 }
1577
1578 /*
1579 * If the "interrupt" for this port doesn't correspond with any
1580 * hardware interrupt, we use a timer-based system. The original
1581 * driver used to do this with IRQ0.
1582 */
1583 if (!is_real_interrupt(up->port.irq)) {
1584 unsigned int timeout = up->port.timeout;
1585
1586 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1587
1588 up->timer.data = (unsigned long)up;
1589 mod_timer(&up->timer, jiffies + timeout);
1590 } else {
1591 retval = serial_link_irq_chain(up);
1592 if (retval)
1593 return retval;
1594 }
1595
1596 /*
1597 * Now, initialize the UART
1598 */
1599 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
1600
1601 spin_lock_irqsave(&up->port.lock, flags);
1602 if (up->port.flags & UPF_FOURPORT) {
1603 if (!is_real_interrupt(up->port.irq))
1604 up->port.mctrl |= TIOCM_OUT1;
1605 } else
1606 /*
1607 * Most PC uarts need OUT2 raised to enable interrupts.
1608 */
1609 if (is_real_interrupt(up->port.irq))
1610 up->port.mctrl |= TIOCM_OUT2;
1611
1612 serial8250_set_mctrl(&up->port, up->port.mctrl);
55d3b282
RK		 1613
1614 /*
1615 * Do a quick test to see if we receive an
1616 * interrupt when we enable the TX irq.
1617 */
1618 serial_outp(up, UART_IER, UART_IER_THRI);
1619 lsr = serial_in(up, UART_LSR);
1620 iir = serial_in(up, UART_IIR);
1621 serial_outp(up, UART_IER, 0);
1622
1623 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 1624 if (!(up->bugs & UART_BUG_TXEN)) {
1625 up->bugs |= UART_BUG_TXEN;
55d3b282
RK		 1626 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
1627 port->line);
1628 }
1629 } else {
67f7654e 1630 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 1631 }
1632
1da177e4
LT		 1633 spin_unlock_irqrestore(&up->port.lock, flags);
1634
1635 /*
1636 * Finally, enable interrupts. Note: Modem status interrupts
1637 * are set via set_termios(), which will be occurring imminently
1638 * anyway, so we don't enable them here.
1639 */
1640 up->ier = UART_IER_RLSI | UART_IER_RDI;
1641 serial_outp(up, UART_IER, up->ier);
1642
1643 if (up->port.flags & UPF_FOURPORT) {
1644 unsigned int icp;
1645 /*
1646 * Enable interrupts on the AST Fourport board
1647 */
1648 icp = (up->port.iobase & 0xfe0) | 0x01f;
1649 outb_p(0x80, icp);
1650 (void) inb_p(icp);
1651 }
1652
1653 /*
1654 * And clear the interrupt registers again for luck.
1655 */
1656 (void) serial_inp(up, UART_LSR);
1657 (void) serial_inp(up, UART_RX);
1658 (void) serial_inp(up, UART_IIR);
1659 (void) serial_inp(up, UART_MSR);
1660
1661 return 0;
1662}
1663
1664static void serial8250_shutdown(struct uart_port *port)
1665{
1666 struct uart_8250_port *up = (struct uart_8250_port *)port;
1667 unsigned long flags;
1668
1669 /*
1670 * Disable interrupts from this port
1671 */
1672 up->ier = 0;
1673 serial_outp(up, UART_IER, 0);
1674
1675 spin_lock_irqsave(&up->port.lock, flags);
1676 if (up->port.flags & UPF_FOURPORT) {
1677 /* reset interrupts on the AST Fourport board */
1678 inb((up->port.iobase & 0xfe0) | 0x1f);
1679 up->port.mctrl |= TIOCM_OUT1;
1680 } else
1681 up->port.mctrl &= ~TIOCM_OUT2;
1682
1683 serial8250_set_mctrl(&up->port, up->port.mctrl);
1684 spin_unlock_irqrestore(&up->port.lock, flags);
1685
1686 /*
1687 * Disable break condition and FIFOs
1688 */
1689 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
1690 serial8250_clear_fifos(up);
1691
1692#ifdef CONFIG_SERIAL_8250_RSA
1693 /*
1694 * Reset the RSA board back to 115kbps compat mode.
1695 */
1696 disable_rsa(up);
1697#endif
1698
1699 /*
1700 * Read data port to reset things, and then unlink from
1701 * the IRQ chain.
1702 */
1703 (void) serial_in(up, UART_RX);
1704
1705 if (!is_real_interrupt(up->port.irq))
1706 del_timer_sync(&up->timer);
1707 else
1708 serial_unlink_irq_chain(up);
1709}
1710
1711static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
1712{
1713 unsigned int quot;
1714
1715 /*
1716 * Handle magic divisors for baud rates above baud_base on
1717 * SMSC SuperIO chips.
1718 */
1719 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1720 baud == (port->uartclk/4))
1721 quot = 0x8001;
1722 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1723 baud == (port->uartclk/8))
1724 quot = 0x8002;
1725 else
1726 quot = uart_get_divisor(port, baud);
1727
1728 return quot;
1729}
1730
1731static void
1732serial8250_set_termios(struct uart_port *port, struct termios *termios,
1733 struct termios *old)
1734{
1735 struct uart_8250_port *up = (struct uart_8250_port *)port;
1736 unsigned char cval, fcr = 0;
1737 unsigned long flags;
1738 unsigned int baud, quot;
1739
1740 switch (termios->c_cflag & CSIZE) {
1741 case CS5:
0a8b80c5 1742 cval = UART_LCR_WLEN5;
1da177e4
LT		 1743 break;
1744 case CS6:
0a8b80c5 1745 cval = UART_LCR_WLEN6;
1da177e4
LT		 1746 break;
1747 case CS7:
0a8b80c5 1748 cval = UART_LCR_WLEN7;
1da177e4
LT		 1749 break;
1750 default:
1751 case CS8:
0a8b80c5 1752 cval = UART_LCR_WLEN8;
1da177e4
LT		 1753 break;
1754 }
1755
1756 if (termios->c_cflag & CSTOPB)
0a8b80c5 1757 cval |= UART_LCR_STOP;
1da177e4
LT		 1758 if (termios->c_cflag & PARENB)
1759 cval |= UART_LCR_PARITY;
1760 if (!(termios->c_cflag & PARODD))
1761 cval |= UART_LCR_EPAR;
1762#ifdef CMSPAR
1763 if (termios->c_cflag & CMSPAR)
1764 cval |= UART_LCR_SPAR;
1765#endif
1766
1767 /*
1768 * Ask the core to calculate the divisor for us.
1769 */
1770 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
1771 quot = serial8250_get_divisor(port, baud);
1772
1773 /*
4ba5e35d 1774 * Oxford Semi 952 rev B workaround
1da177e4 1775 */
4ba5e35d 1776 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
1da177e4
LT		 1777 quot ++;
1778
1779 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
1780 if (baud < 2400)
1781 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
1782 else
1783 fcr = uart_config[up->port.type].fcr;
1784 }
1785
1786 /*
1787 * MCR-based auto flow control. When AFE is enabled, RTS will be
1788 * deasserted when the receive FIFO contains more characters than
1789 * the trigger, or the MCR RTS bit is cleared. In the case where
1790 * the remote UART is not using CTS auto flow control, we must
1791 * have sufficient FIFO entries for the latency of the remote
1792 * UART to respond. IOW, at least 32 bytes of FIFO.
1793 */
1794 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
1795 up->mcr &= ~UART_MCR_AFE;
1796 if (termios->c_cflag & CRTSCTS)
1797 up->mcr |= UART_MCR_AFE;
1798 }
1799
1800 /*
1801 * Ok, we're now changing the port state. Do it with
1802 * interrupts disabled.
1803 */
1804 spin_lock_irqsave(&up->port.lock, flags);
1805
1806 /*
1807 * Update the per-port timeout.
1808 */
1809 uart_update_timeout(port, termios->c_cflag, baud);
1810
1811 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
1812 if (termios->c_iflag & INPCK)
1813 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
1814 if (termios->c_iflag & (BRKINT | PARMRK))
1815 up->port.read_status_mask |= UART_LSR_BI;
1816
1817 /*
1818 * Characteres to ignore
1819 */
1820 up->port.ignore_status_mask = 0;
1821 if (termios->c_iflag & IGNPAR)
1822 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
1823 if (termios->c_iflag & IGNBRK) {
1824 up->port.ignore_status_mask |= UART_LSR_BI;
1825 /*
1826 * If we're ignoring parity and break indicators,
1827 * ignore overruns too (for real raw support).
1828 */
1829 if (termios->c_iflag & IGNPAR)
1830 up->port.ignore_status_mask |= UART_LSR_OE;
1831 }
1832
1833 /*
1834 * ignore all characters if CREAD is not set
1835 */
1836 if ((termios->c_cflag & CREAD) == 0)
1837 up->port.ignore_status_mask |= UART_LSR_DR;
1838
1839 /*
1840 * CTS flow control flag and modem status interrupts
1841 */
1842 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 1843 if (!(up->bugs & UART_BUG_NOMSR) &&
1844 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 1845 up->ier |= UART_IER_MSI;
1846 if (up->capabilities & UART_CAP_UUE)
1847 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
1848
1849 serial_out(up, UART_IER, up->ier);
1850
1851 if (up->capabilities & UART_CAP_EFR) {
1852 unsigned char efr = 0;
1853 /*
1854 * TI16C752/Startech hardware flow control. FIXME:
1855 * - TI16C752 requires control thresholds to be set.
1856 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
1857 */
1858 if (termios->c_cflag & CRTSCTS)
1859 efr |= UART_EFR_CTS;
1860
1861 serial_outp(up, UART_LCR, 0xBF);
1862 serial_outp(up, UART_EFR, efr);
1863 }
1864
1865 if (up->capabilities & UART_NATSEMI) {
1866 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
1867 serial_outp(up, UART_LCR, 0xe0);
1868 } else {
1869 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
1870 }
1871
1872 serial_outp(up, UART_DLL, quot & 0xff); /* LS of divisor */
1873 serial_outp(up, UART_DLM, quot >> 8); /* MS of divisor */
1874
1875 /*
1876 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
1877 * is written without DLAB set, this mode will be disabled.
1878 */
1879 if (up->port.type == PORT_16750)
1880 serial_outp(up, UART_FCR, fcr);
1881
1882 serial_outp(up, UART_LCR, cval); /* reset DLAB */
1883 up->lcr = cval; /* Save LCR */
1884 if (up->port.type != PORT_16750) {
1885 if (fcr & UART_FCR_ENABLE_FIFO) {
1886 /* emulated UARTs (Lucent Venus 167x) need two steps */
1887 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1888 }
1889 serial_outp(up, UART_FCR, fcr); /* set fcr */
1890 }
1891 serial8250_set_mctrl(&up->port, up->port.mctrl);
1892 spin_unlock_irqrestore(&up->port.lock, flags);
1893}
1894
1895static void
1896serial8250_pm(struct uart_port *port, unsigned int state,
1897 unsigned int oldstate)
1898{
1899 struct uart_8250_port *p = (struct uart_8250_port *)port;
1900
1901 serial8250_set_sleep(p, state != 0);
1902
1903 if (p->pm)
1904 p->pm(port, state, oldstate);
1905}
1906
1907/*
1908 * Resource handling.
1909 */
1910static int serial8250_request_std_resource(struct uart_8250_port *up)
1911{
1912 unsigned int size = 8 << up->port.regshift;
1913 int ret = 0;
1914
1915 switch (up->port.iotype) {
1916 case UPIO_MEM:
1917 if (!up->port.mapbase)
1918 break;
1919
1920 if (!request_mem_region(up->port.mapbase, size, "serial")) {
1921 ret = -EBUSY;
1922 break;
1923 }
1924
1925 if (up->port.flags & UPF_IOREMAP) {
1926 up->port.membase = ioremap(up->port.mapbase, size);
1927 if (!up->port.membase) {
1928 release_mem_region(up->port.mapbase, size);
1929 ret = -ENOMEM;
1930 }
1931 }
1932 break;
1933
1934 case UPIO_HUB6:
1935 case UPIO_PORT:
1936 if (!request_region(up->port.iobase, size, "serial"))
1937 ret = -EBUSY;
1938 break;
1939 }
1940 return ret;
1941}
1942
1943static void serial8250_release_std_resource(struct uart_8250_port *up)
1944{
1945 unsigned int size = 8 << up->port.regshift;
1946
1947 switch (up->port.iotype) {
1948 case UPIO_MEM:
1949 if (!up->port.mapbase)
1950 break;
1951
1952 if (up->port.flags & UPF_IOREMAP) {
1953 iounmap(up->port.membase);
1954 up->port.membase = NULL;
1955 }
1956
1957 release_mem_region(up->port.mapbase, size);
1958 break;
1959
1960 case UPIO_HUB6:
1961 case UPIO_PORT:
1962 release_region(up->port.iobase, size);
1963 break;
1964 }
1965}
1966
1967static int serial8250_request_rsa_resource(struct uart_8250_port *up)
1968{
1969 unsigned long start = UART_RSA_BASE << up->port.regshift;
1970 unsigned int size = 8 << up->port.regshift;
1971 int ret = 0;
1972
1973 switch (up->port.iotype) {
1974 case UPIO_MEM:
1975 ret = -EINVAL;
1976 break;
1977
1978 case UPIO_HUB6:
1979 case UPIO_PORT:
1980 start += up->port.iobase;
1981 if (!request_region(start, size, "serial-rsa"))
1982 ret = -EBUSY;
1983 break;
1984 }
1985
1986 return ret;
1987}
1988
1989static void serial8250_release_rsa_resource(struct uart_8250_port *up)
1990{
1991 unsigned long offset = UART_RSA_BASE << up->port.regshift;
1992 unsigned int size = 8 << up->port.regshift;
1993
1994 switch (up->port.iotype) {
1995 case UPIO_MEM:
1996 break;
1997
1998 case UPIO_HUB6:
1999 case UPIO_PORT:
2000 release_region(up->port.iobase + offset, size);
2001 break;
2002 }
2003}
2004
2005static void serial8250_release_port(struct uart_port *port)
2006{
2007 struct uart_8250_port *up = (struct uart_8250_port *)port;
2008
2009 serial8250_release_std_resource(up);
2010 if (up->port.type == PORT_RSA)
2011 serial8250_release_rsa_resource(up);
2012}
2013
2014static int serial8250_request_port(struct uart_port *port)
2015{
2016 struct uart_8250_port *up = (struct uart_8250_port *)port;
2017 int ret = 0;
2018
2019 ret = serial8250_request_std_resource(up);
2020 if (ret == 0 && up->port.type == PORT_RSA) {
2021 ret = serial8250_request_rsa_resource(up);
2022 if (ret < 0)
2023 serial8250_release_std_resource(up);
2024 }
2025
2026 return ret;
2027}
2028
2029static void serial8250_config_port(struct uart_port *port, int flags)
2030{
2031 struct uart_8250_port *up = (struct uart_8250_port *)port;
2032 int probeflags = PROBE_ANY;
2033 int ret;
2034
2035 /*
2036 * Don't probe for MCA ports on non-MCA machines.
2037 */
2038 if (up->port.flags & UPF_BOOT_ONLYMCA && !MCA_bus)
2039 return;
2040
2041 /*
2042 * Find the region that we can probe for. This in turn
2043 * tells us whether we can probe for the type of port.
2044 */
2045 ret = serial8250_request_std_resource(up);
2046 if (ret < 0)
2047 return;
2048
2049 ret = serial8250_request_rsa_resource(up);
2050 if (ret < 0)
2051 probeflags &= ~PROBE_RSA;
2052
2053 if (flags & UART_CONFIG_TYPE)
2054 autoconfig(up, probeflags);
2055 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2056 autoconfig_irq(up);
2057
2058 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2059 serial8250_release_rsa_resource(up);
2060 if (up->port.type == PORT_UNKNOWN)
2061 serial8250_release_std_resource(up);
2062}
2063
2064static int
2065serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2066{
2067 if (ser->irq >= NR_IRQS || ser->irq < 0 ||
2068 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2069 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2070 ser->type == PORT_STARTECH)
2071 return -EINVAL;
2072 return 0;
2073}
2074
2075static const char *
2076serial8250_type(struct uart_port *port)
2077{
2078 int type = port->type;
2079
2080 if (type >= ARRAY_SIZE(uart_config))
2081 type = 0;
2082 return uart_config[type].name;
2083}
2084
2085static struct uart_ops serial8250_pops = {
2086 .tx_empty = serial8250_tx_empty,
2087 .set_mctrl = serial8250_set_mctrl,
2088 .get_mctrl = serial8250_get_mctrl,
2089 .stop_tx = serial8250_stop_tx,
2090 .start_tx = serial8250_start_tx,
2091 .stop_rx = serial8250_stop_rx,
2092 .enable_ms = serial8250_enable_ms,
2093 .break_ctl = serial8250_break_ctl,
2094 .startup = serial8250_startup,
2095 .shutdown = serial8250_shutdown,
2096 .set_termios = serial8250_set_termios,
2097 .pm = serial8250_pm,
2098 .type = serial8250_type,
2099 .release_port = serial8250_release_port,
2100 .request_port = serial8250_request_port,
2101 .config_port = serial8250_config_port,
2102 .verify_port = serial8250_verify_port,
2103};
2104
2105static struct uart_8250_port serial8250_ports[UART_NR];
2106
2107static void __init serial8250_isa_init_ports(void)
2108{
2109 struct uart_8250_port *up;
2110 static int first = 1;
2111 int i;
2112
2113 if (!first)
2114 return;
2115 first = 0;
2116
2117 for (i = 0; i < UART_NR; i++) {
2118 struct uart_8250_port *up = &serial8250_ports[i];
2119
2120 up->port.line = i;
2121 spin_lock_init(&up->port.lock);
2122
2123 init_timer(&up->timer);
2124 up->timer.function = serial8250_timeout;
2125
2126 /*
2127 * ALPHA_KLUDGE_MCR needs to be killed.
2128 */
2129 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2130 up->mcr_force = ALPHA_KLUDGE_MCR;
2131
2132 up->port.ops = &serial8250_pops;
2133 }
2134
44454bcd
RK		 2135 for (i = 0, up = serial8250_ports;
2136 i < ARRAY_SIZE(old_serial_port) && i < UART_NR;
1da177e4
LT		 2137 i++, up++) {
2138 up->port.iobase = old_serial_port[i].port;
2139 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2140 up->port.uartclk = old_serial_port[i].baud_base * 16;
2141 up->port.flags = old_serial_port[i].flags;
2142 up->port.hub6 = old_serial_port[i].hub6;
2143 up->port.membase = old_serial_port[i].iomem_base;
2144 up->port.iotype = old_serial_port[i].io_type;
2145 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2146 if (share_irqs)
2147 up->port.flags |= UPF_SHARE_IRQ;
2148 }
2149}
2150
2151static void __init
2152serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2153{
2154 int i;
2155
2156 serial8250_isa_init_ports();
2157
2158 for (i = 0; i < UART_NR; i++) {
2159 struct uart_8250_port *up = &serial8250_ports[i];
2160
2161 up->port.dev = dev;
2162 uart_add_one_port(drv, &up->port);
2163 }
2164}
2165
2166#ifdef CONFIG_SERIAL_8250_CONSOLE
2167
2168#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
2169
2170/*
2171 * Wait for transmitter & holding register to empty
2172 */
2173static inline void wait_for_xmitr(struct uart_8250_port *up)
2174{
2175 unsigned int status, tmout = 10000;
2176
2177 /* Wait up to 10ms for the character(s) to be sent. */
2178 do {
2179 status = serial_in(up, UART_LSR);
2180
2181 if (status & UART_LSR_BI)
2182 up->lsr_break_flag = UART_LSR_BI;
2183
2184 if (--tmout == 0)
2185 break;
2186 udelay(1);
2187 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
2188
2189 /* Wait up to 1s for flow control if necessary */
2190 if (up->port.flags & UPF_CONS_FLOW) {
2191 tmout = 1000000;
2192 while (--tmout &&
2193 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
2194 udelay(1);
2195 }
2196}
2197
2198/*
2199 * Print a string to the serial port trying not to disturb
2200 * any possible real use of the port...
2201 *
2202 * The console_lock must be held when we get here.
2203 */
2204static void
2205serial8250_console_write(struct console *co, const char *s, unsigned int count)
2206{
2207 struct uart_8250_port *up = &serial8250_ports[co->index];
2208 unsigned int ier;
2209 int i;
2210
2211 /*
2212 * First save the UER then disable the interrupts
2213 */
2214 ier = serial_in(up, UART_IER);
2215
2216 if (up->capabilities & UART_CAP_UUE)
2217 serial_out(up, UART_IER, UART_IER_UUE);
2218 else
2219 serial_out(up, UART_IER, 0);
2220
2221 /*
2222 * Now, do each character
2223 */
2224 for (i = 0; i < count; i++, s++) {
2225 wait_for_xmitr(up);
2226
2227 /*
2228 * Send the character out.
2229 * If a LF, also do CR...
2230 */
2231 serial_out(up, UART_TX, *s);
2232 if (*s == 10) {
2233 wait_for_xmitr(up);
2234 serial_out(up, UART_TX, 13);
2235 }
2236 }
2237
2238 /*
2239 * Finally, wait for transmitter to become empty
2240 * and restore the IER
2241 */
2242 wait_for_xmitr(up);
2243 serial_out(up, UART_IER, ier);
2244}
2245
2246static int serial8250_console_setup(struct console *co, char *options)
2247{
2248 struct uart_port *port;
2249 int baud = 9600;
2250 int bits = 8;
2251 int parity = 'n';
2252 int flow = 'n';
2253
2254 /*
2255 * Check whether an invalid uart number has been specified, and
2256 * if so, search for the first available port that does have
2257 * console support.
2258 */
2259 if (co->index >= UART_NR)
2260 co->index = 0;
2261 port = &serial8250_ports[co->index].port;
2262 if (!port->iobase && !port->membase)
2263 return -ENODEV;
2264
2265 if (options)
2266 uart_parse_options(options, &baud, &parity, &bits, &flow);
2267
2268 return uart_set_options(port, co, baud, parity, bits, flow);
2269}
2270
2271static struct uart_driver serial8250_reg;
2272static struct console serial8250_console = {
2273 .name = "ttyS",
2274 .write = serial8250_console_write,
2275 .device = uart_console_device,
2276 .setup = serial8250_console_setup,
2277 .flags = CON_PRINTBUFFER,
2278 .index = -1,
2279 .data = &serial8250_reg,
2280};
2281
2282static int __init serial8250_console_init(void)
2283{
2284 serial8250_isa_init_ports();
2285 register_console(&serial8250_console);
2286 return 0;
2287}
2288console_initcall(serial8250_console_init);
2289
2290static int __init find_port(struct uart_port *p)
2291{
2292 int line;
2293 struct uart_port *port;
2294
2295 for (line = 0; line < UART_NR; line++) {
2296 port = &serial8250_ports[line].port;
2297 if (p->iotype == port->iotype &&
2298 p->iobase == port->iobase &&
2299 p->membase == port->membase)
2300 return line;
2301 }
2302 return -ENODEV;
2303}
2304
2305int __init serial8250_start_console(struct uart_port *port, char *options)
2306{
2307 int line;
2308
2309 line = find_port(port);
2310 if (line < 0)
2311 return -ENODEV;
2312
2313 add_preferred_console("ttyS", line, options);
2314 printk("Adding console on ttyS%d at %s 0x%lx (options '%s')\n",
2315 line, port->iotype == UPIO_MEM ? "MMIO" : "I/O port",
2316 port->iotype == UPIO_MEM ? (unsigned long) port->mapbase :
2317 (unsigned long) port->iobase, options);
2318 if (!(serial8250_console.flags & CON_ENABLED)) {
2319 serial8250_console.flags &= ~CON_PRINTBUFFER;
2320 register_console(&serial8250_console);
2321 }
2322 return line;
2323}
2324
2325#define SERIAL8250_CONSOLE &serial8250_console
2326#else
2327#define SERIAL8250_CONSOLE NULL
2328#endif
2329
2330static struct uart_driver serial8250_reg = {
2331 .owner = THIS_MODULE,
2332 .driver_name = "serial",
2333 .devfs_name = "tts/",
2334 .dev_name = "ttyS",
2335 .major = TTY_MAJOR,
2336 .minor = 64,
2337 .nr = UART_NR,
2338 .cons = SERIAL8250_CONSOLE,
2339};
2340
2341int __init early_serial_setup(struct uart_port *port)
2342{
2343 if (port->line >= ARRAY_SIZE(serial8250_ports))
2344 return -ENODEV;
2345
2346 serial8250_isa_init_ports();
2347 serial8250_ports[port->line].port = *port;
2348 serial8250_ports[port->line].port.ops = &serial8250_pops;
2349 return 0;
2350}
2351
2352/**
2353 * serial8250_suspend_port - suspend one serial port
2354 * @line: serial line number
2355 * @level: the level of port suspension, as per uart_suspend_port
2356 *
2357 * Suspend one serial port.
2358 */
2359void serial8250_suspend_port(int line)
2360{
2361 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2362}
2363
2364/**
2365 * serial8250_resume_port - resume one serial port
2366 * @line: serial line number
2367 * @level: the level of port resumption, as per uart_resume_port
2368 *
2369 * Resume one serial port.
2370 */
2371void serial8250_resume_port(int line)
2372{
2373 uart_resume_port(&serial8250_reg, &serial8250_ports[line].port);
2374}
2375
2376/*
2377 * Register a set of serial devices attached to a platform device. The
2378 * list is terminated with a zero flags entry, which means we expect
2379 * all entries to have at least UPF_BOOT_AUTOCONF set.
2380 */
2381static int __devinit serial8250_probe(struct device *dev)
2382{
2383 struct plat_serial8250_port *p = dev->platform_data;
2384 struct uart_port port;
ec9f47cd 2385 int ret, i;
1da177e4
LT		 2386
2387 memset(&port, 0, sizeof(struct uart_port));
2388
ec9f47cd 2389 for (i = 0; p && p->flags != 0; p++, i++) {
1da177e4
LT		 2390 port.iobase = p->iobase;
2391 port.membase = p->membase;
2392 port.irq = p->irq;
2393 port.uartclk = p->uartclk;
2394 port.regshift = p->regshift;
2395 port.iotype = p->iotype;
2396 port.flags = p->flags;
2397 port.mapbase = p->mapbase;
ec9f47cd 2398 port.hub6 = p->hub6;
1da177e4
LT		 2399 port.dev = dev;
2400 if (share_irqs)
2401 port.flags |= UPF_SHARE_IRQ;
ec9f47cd
RK		 2402 ret = serial8250_register_port(&port);
2403 if (ret < 0) {
2404 dev_err(dev, "unable to register port at index %d "
2405 "(IO%lx MEM%lx IRQ%d): %d\n", i,
2406 p->iobase, p->mapbase, p->irq, ret);
2407 }
1da177e4
LT		 2408 }
2409 return 0;
2410}
2411
2412/*
2413 * Remove serial ports registered against a platform device.
2414 */
2415static int __devexit serial8250_remove(struct device *dev)
2416{
2417 int i;
2418
2419 for (i = 0; i < UART_NR; i++) {
2420 struct uart_8250_port *up = &serial8250_ports[i];
2421
2422 if (up->port.dev == dev)
2423 serial8250_unregister_port(i);
2424 }
2425 return 0;
2426}
2427
9480e307 2428static int serial8250_suspend(struct device *dev, pm_message_t state)
1da177e4
LT		 2429{
2430 int i;
2431
1da177e4
LT		 2432 for (i = 0; i < UART_NR; i++) {
2433 struct uart_8250_port *up = &serial8250_ports[i];
2434
2435 if (up->port.type != PORT_UNKNOWN && up->port.dev == dev)
2436 uart_suspend_port(&serial8250_reg, &up->port);
2437 }
2438
2439 return 0;
2440}
2441
9480e307 2442static int serial8250_resume(struct device *dev)
1da177e4
LT		 2443{
2444 int i;
2445
1da177e4
LT		 2446 for (i = 0; i < UART_NR; i++) {
2447 struct uart_8250_port *up = &serial8250_ports[i];
2448
2449 if (up->port.type != PORT_UNKNOWN && up->port.dev == dev)
2450 uart_resume_port(&serial8250_reg, &up->port);
2451 }
2452
2453 return 0;
2454}
2455
2456static struct device_driver serial8250_isa_driver = {
2457 .name = "serial8250",
2458 .bus = &platform_bus_type,
2459 .probe = serial8250_probe,
2460 .remove = __devexit_p(serial8250_remove),
2461 .suspend = serial8250_suspend,
2462 .resume = serial8250_resume,
2463};
2464
2465/*
2466 * This "device" covers _all_ ISA 8250-compatible serial devices listed
2467 * in the table in include/asm/serial.h
2468 */
2469static struct platform_device *serial8250_isa_devs;
2470
2471/*
2472 * serial8250_register_port and serial8250_unregister_port allows for
2473 * 16x50 serial ports to be configured at run-time, to support PCMCIA
2474 * modems and PCI multiport cards.
2475 */
2476static DECLARE_MUTEX(serial_sem);
2477
2478static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
2479{
2480 int i;
2481
2482 /*
2483 * First, find a port entry which matches.
2484 */
2485 for (i = 0; i < UART_NR; i++)
2486 if (uart_match_port(&serial8250_ports[i].port, port))
2487 return &serial8250_ports[i];
2488
2489 /*
2490 * We didn't find a matching entry, so look for the first
2491 * free entry. We look for one which hasn't been previously
2492 * used (indicated by zero iobase).
2493 */
2494 for (i = 0; i < UART_NR; i++)
2495 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
2496 serial8250_ports[i].port.iobase == 0)
2497 return &serial8250_ports[i];
2498
2499 /*
2500 * That also failed. Last resort is to find any entry which
2501 * doesn't have a real port associated with it.
2502 */
2503 for (i = 0; i < UART_NR; i++)
2504 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
2505 return &serial8250_ports[i];
2506
2507 return NULL;
2508}
2509
2510/**
2511 * serial8250_register_port - register a serial port
2512 * @port: serial port template
2513 *
2514 * Configure the serial port specified by the request. If the
2515 * port exists and is in use, it is hung up and unregistered
2516 * first.
2517 *
2518 * The port is then probed and if necessary the IRQ is autodetected
2519 * If this fails an error is returned.
2520 *
2521 * On success the port is ready to use and the line number is returned.
2522 */
2523int serial8250_register_port(struct uart_port *port)
2524{
2525 struct uart_8250_port *uart;
2526 int ret = -ENOSPC;
2527
2528 if (port->uartclk == 0)
2529 return -EINVAL;
2530
2531 down(&serial_sem);
2532
2533 uart = serial8250_find_match_or_unused(port);
2534 if (uart) {
2535 uart_remove_one_port(&serial8250_reg, &uart->port);
2536
2537 uart->port.iobase = port->iobase;
2538 uart->port.membase = port->membase;
2539 uart->port.irq = port->irq;
2540 uart->port.uartclk = port->uartclk;
2541 uart->port.fifosize = port->fifosize;
2542 uart->port.regshift = port->regshift;
2543 uart->port.iotype = port->iotype;
2544 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
2545 uart->port.mapbase = port->mapbase;
2546 if (port->dev)
2547 uart->port.dev = port->dev;
2548
2549 ret = uart_add_one_port(&serial8250_reg, &uart->port);
2550 if (ret == 0)
2551 ret = uart->port.line;
2552 }
2553 up(&serial_sem);
2554
2555 return ret;
2556}
2557EXPORT_SYMBOL(serial8250_register_port);
2558
2559/**
2560 * serial8250_unregister_port - remove a 16x50 serial port at runtime
2561 * @line: serial line number
2562 *
2563 * Remove one serial port. This may not be called from interrupt
2564 * context. We hand the port back to the our control.
2565 */
2566void serial8250_unregister_port(int line)
2567{
2568 struct uart_8250_port *uart = &serial8250_ports[line];
2569
2570 down(&serial_sem);
2571 uart_remove_one_port(&serial8250_reg, &uart->port);
2572 if (serial8250_isa_devs) {
2573 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
2574 uart->port.type = PORT_UNKNOWN;
2575 uart->port.dev = &serial8250_isa_devs->dev;
2576 uart_add_one_port(&serial8250_reg, &uart->port);
2577 } else {
2578 uart->port.dev = NULL;
2579 }
2580 up(&serial_sem);
2581}
2582EXPORT_SYMBOL(serial8250_unregister_port);
2583
2584static int __init serial8250_init(void)
2585{
2586 int ret, i;
2587
2588 printk(KERN_INFO "Serial: 8250/16550 driver $Revision: 1.90 $ "
2589 "%d ports, IRQ sharing %sabled\n", (int) UART_NR,
2590 share_irqs ? "en" : "dis");
2591
2592 for (i = 0; i < NR_IRQS; i++)
2593 spin_lock_init(&irq_lists[i].lock);
2594
2595 ret = uart_register_driver(&serial8250_reg);
2596 if (ret)
2597 goto out;
2598
2599 serial8250_isa_devs = platform_device_register_simple("serial8250",
6df29deb 2600 PLAT8250_DEV_LEGACY, NULL, 0);
1da177e4
LT		 2601 if (IS_ERR(serial8250_isa_devs)) {
2602 ret = PTR_ERR(serial8250_isa_devs);
2603 goto unreg;
2604 }
2605
2606 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
2607
2608 ret = driver_register(&serial8250_isa_driver);
2609 if (ret == 0)
2610 goto out;
2611
2612 platform_device_unregister(serial8250_isa_devs);
2613 unreg:
2614 uart_unregister_driver(&serial8250_reg);
2615 out:
2616 return ret;
2617}
2618
2619static void __exit serial8250_exit(void)
2620{
2621 struct platform_device *isa_dev = serial8250_isa_devs;
2622
2623 /*
2624 * This tells serial8250_unregister_port() not to re-register
2625 * the ports (thereby making serial8250_isa_driver permanently
2626 * in use.)
2627 */
2628 serial8250_isa_devs = NULL;
2629
2630 driver_unregister(&serial8250_isa_driver);
2631 platform_device_unregister(isa_dev);
2632
2633 uart_unregister_driver(&serial8250_reg);
2634}
2635
2636module_init(serial8250_init);
2637module_exit(serial8250_exit);
2638
2639EXPORT_SYMBOL(serial8250_suspend_port);
2640EXPORT_SYMBOL(serial8250_resume_port);
2641
2642MODULE_LICENSE("GPL");
2643MODULE_DESCRIPTION("Generic 8250/16x50 serial driver $Revision: 1.90 $");
2644
2645module_param(share_irqs, uint, 0644);
2646MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
2647 " (unsafe)");
2648
2649#ifdef CONFIG_SERIAL_8250_RSA
2650module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
2651MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
2652#endif
2653MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
Linux kernel - Deliverables
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