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serial driver PMC MSP71xx
[deliverable/linux.git] / drivers / serial / 8250.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * $Id: 8250.c,v 1.90 2002/07/28 10:03:27 rmk Exp $
16 *
17 * A note about mapbase / membase
18 *
19 * mapbase is the physical address of the IO port.
20 * membase is an 'ioremapped' cookie.
21 */
1da177e4
LT		 22
23#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24#define SUPPORT_SYSRQ
25#endif
26
27#include <linux/module.h>
28#include <linux/moduleparam.h>
29#include <linux/ioport.h>
30#include <linux/init.h>
31#include <linux/console.h>
32#include <linux/sysrq.h>
1da177e4 33#include <linux/delay.h>
d052d1be 34#include <linux/platform_device.h>
1da177e4
LT		 35#include <linux/tty.h>
36#include <linux/tty_flip.h>
37#include <linux/serial_reg.h>
38#include <linux/serial_core.h>
39#include <linux/serial.h>
40#include <linux/serial_8250.h>
78512ece 41#include <linux/nmi.h>
f392ecfa 42#include <linux/mutex.h>
1da177e4
LT		 43
44#include <asm/io.h>
45#include <asm/irq.h>
46
47#include "8250.h"
48
49/*
50 * Configuration:
40663cc7 51 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
1da177e4
LT		 52 * is unsafe when used on edge-triggered interrupts.
53 */
408b664a 54static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4 55
a61c2d78
DJ		 56static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
57
1da177e4
LT		 58/*
59 * Debugging.
60 */
61#if 0
62#define DEBUG_AUTOCONF(fmt...) printk(fmt)
63#else
64#define DEBUG_AUTOCONF(fmt...) do { } while (0)
65#endif
66
67#if 0
68#define DEBUG_INTR(fmt...) printk(fmt)
69#else
70#define DEBUG_INTR(fmt...) do { } while (0)
71#endif
72
73#define PASS_LIMIT 256
74
75/*
76 * We default to IRQ0 for the "no irq" hack. Some
77 * machine types want others as well - they're free
78 * to redefine this in their header file.
79 */
80#define is_real_interrupt(irq) ((irq) != 0)
81
1da177e4
LT		 82#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
83#define CONFIG_SERIAL_DETECT_IRQ 1
84#endif
1da177e4
LT		 85#ifdef CONFIG_SERIAL_8250_MANY_PORTS
86#define CONFIG_SERIAL_MANY_PORTS 1
87#endif
88
89/*
90 * HUB6 is always on. This will be removed once the header
91 * files have been cleaned.
92 */
93#define CONFIG_HUB6 1
94
95#include <asm/serial.h>
96
97/*
98 * SERIAL_PORT_DFNS tells us about built-in ports that have no
99 * standard enumeration mechanism. Platforms that can find all
100 * serial ports via mechanisms like ACPI or PCI need not supply it.
101 */
102#ifndef SERIAL_PORT_DFNS
103#define SERIAL_PORT_DFNS
104#endif
105
cb3592be 106static const struct old_serial_port old_serial_port[] = {
1da177e4
LT		 107 SERIAL_PORT_DFNS /* defined in asm/serial.h */
108};
109
026d02a2 110#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 111
112#ifdef CONFIG_SERIAL_8250_RSA
113
114#define PORT_RSA_MAX 4
115static unsigned long probe_rsa[PORT_RSA_MAX];
116static unsigned int probe_rsa_count;
117#endif /* CONFIG_SERIAL_8250_RSA */
118
119struct uart_8250_port {
120 struct uart_port port;
121 struct timer_list timer; /* "no irq" timer */
122 struct list_head list; /* ports on this IRQ */
4ba5e35d
RK		 123 unsigned short capabilities; /* port capabilities */
124 unsigned short bugs; /* port bugs */
1da177e4 125 unsigned int tx_loadsz; /* transmit fifo load size */
1da177e4
LT		 126 unsigned char acr;
127 unsigned char ier;
128 unsigned char lcr;
129 unsigned char mcr;
130 unsigned char mcr_mask; /* mask of user bits */
131 unsigned char mcr_force; /* mask of forced bits */
132 unsigned char lsr_break_flag;
133
134 /*
135 * We provide a per-port pm hook.
136 */
137 void (*pm)(struct uart_port *port,
138 unsigned int state, unsigned int old);
139};
140
141struct irq_info {
142 spinlock_t lock;
143 struct list_head *head;
144};
145
146static struct irq_info irq_lists[NR_IRQS];
147
148/*
149 * Here we define the default xmit fifo size used for each type of UART.
150 */
151static const struct serial8250_config uart_config[] = {
152 [PORT_UNKNOWN] = {
153 .name = "unknown",
154 .fifo_size = 1,
155 .tx_loadsz = 1,
156 },
157 [PORT_8250] = {
158 .name = "8250",
159 .fifo_size = 1,
160 .tx_loadsz = 1,
161 },
162 [PORT_16450] = {
163 .name = "16450",
164 .fifo_size = 1,
165 .tx_loadsz = 1,
166 },
167 [PORT_16550] = {
168 .name = "16550",
169 .fifo_size = 1,
170 .tx_loadsz = 1,
171 },
172 [PORT_16550A] = {
173 .name = "16550A",
174 .fifo_size = 16,
175 .tx_loadsz = 16,
176 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
177 .flags = UART_CAP_FIFO,
178 },
179 [PORT_CIRRUS] = {
180 .name = "Cirrus",
181 .fifo_size = 1,
182 .tx_loadsz = 1,
183 },
184 [PORT_16650] = {
185 .name = "ST16650",
186 .fifo_size = 1,
187 .tx_loadsz = 1,
188 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
189 },
190 [PORT_16650V2] = {
191 .name = "ST16650V2",
192 .fifo_size = 32,
193 .tx_loadsz = 16,
194 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
195 UART_FCR_T_TRIG_00,
196 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
197 },
198 [PORT_16750] = {
199 .name = "TI16750",
200 .fifo_size = 64,
201 .tx_loadsz = 64,
202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
203 UART_FCR7_64BYTE,
204 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
205 },
206 [PORT_STARTECH] = {
207 .name = "Startech",
208 .fifo_size = 1,
209 .tx_loadsz = 1,
210 },
211 [PORT_16C950] = {
212 .name = "16C950/954",
213 .fifo_size = 128,
214 .tx_loadsz = 128,
215 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
216 .flags = UART_CAP_FIFO,
217 },
218 [PORT_16654] = {
219 .name = "ST16654",
220 .fifo_size = 64,
221 .tx_loadsz = 32,
222 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
223 UART_FCR_T_TRIG_10,
224 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
225 },
226 [PORT_16850] = {
227 .name = "XR16850",
228 .fifo_size = 128,
229 .tx_loadsz = 128,
230 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
231 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
232 },
233 [PORT_RSA] = {
234 .name = "RSA",
235 .fifo_size = 2048,
236 .tx_loadsz = 2048,
237 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
238 .flags = UART_CAP_FIFO,
239 },
240 [PORT_NS16550A] = {
241 .name = "NS16550A",
242 .fifo_size = 16,
243 .tx_loadsz = 16,
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
245 .flags = UART_CAP_FIFO | UART_NATSEMI,
246 },
247 [PORT_XSCALE] = {
248 .name = "XScale",
249 .fifo_size = 32,
250 .tx_loadsz = 32,
251 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
252 .flags = UART_CAP_FIFO | UART_CAP_UUE,
253 },
254};
255
21c614a7
PA		 256#ifdef CONFIG_SERIAL_8250_AU1X00
257
258/* Au1x00 UART hardware has a weird register layout */
259static const u8 au_io_in_map[] = {
260 [UART_RX] = 0,
261 [UART_IER] = 2,
262 [UART_IIR] = 3,
263 [UART_LCR] = 5,
264 [UART_MCR] = 6,
265 [UART_LSR] = 7,
266 [UART_MSR] = 8,
267};
268
269static const u8 au_io_out_map[] = {
270 [UART_TX] = 1,
271 [UART_IER] = 2,
272 [UART_FCR] = 4,
273 [UART_LCR] = 5,
274 [UART_MCR] = 6,
275};
276
277/* sane hardware needs no mapping */
278static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
279{
280 if (up->port.iotype != UPIO_AU)
281 return offset;
282 return au_io_in_map[offset];
283}
284
285static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
286{
287 if (up->port.iotype != UPIO_AU)
288 return offset;
289 return au_io_out_map[offset];
290}
291
292#else
293
294/* sane hardware needs no mapping */
295#define map_8250_in_reg(up, offset) (offset)
296#define map_8250_out_reg(up, offset) (offset)
297
298#endif
299
ea8874dc 300static unsigned int serial_in(struct uart_8250_port *up, int offset)
1da177e4 301{
3be91ec7 302 unsigned int tmp;
21c614a7 303 offset = map_8250_in_reg(up, offset) << up->port.regshift;
1da177e4
LT		 304
305 switch (up->port.iotype) {
306 case UPIO_HUB6:
307 outb(up->port.hub6 - 1 + offset, up->port.iobase);
308 return inb(up->port.iobase + 1);
309
310 case UPIO_MEM:
beab697a 311 case UPIO_DWAPB:
1da177e4
LT		 312 return readb(up->port.membase + offset);
313
314 case UPIO_MEM32:
315 return readl(up->port.membase + offset);
316
21c614a7
PA		 317#ifdef CONFIG_SERIAL_8250_AU1X00
318 case UPIO_AU:
319 return __raw_readl(up->port.membase + offset);
320#endif
321
3be91ec7
ZR		 322 case UPIO_TSI:
323 if (offset == UART_IIR) {
9e84b60e
AV		 324 tmp = readl(up->port.membase + (UART_IIR & ~3));
325 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
3be91ec7
ZR		 326 } else
327 return readb(up->port.membase + offset);
328
1da177e4
LT		 329 default:
330 return inb(up->port.iobase + offset);
331 }
332}
333
ea8874dc 334static void
1da177e4
LT		 335serial_out(struct uart_8250_port *up, int offset, int value)
336{
beab697a
MSJ		 337 /* Save the offset before it's remapped */
338 int save_offset = offset;
21c614a7 339 offset = map_8250_out_reg(up, offset) << up->port.regshift;
1da177e4
LT		 340
341 switch (up->port.iotype) {
342 case UPIO_HUB6:
343 outb(up->port.hub6 - 1 + offset, up->port.iobase);
344 outb(value, up->port.iobase + 1);
345 break;
346
347 case UPIO_MEM:
348 writeb(value, up->port.membase + offset);
349 break;
350
351 case UPIO_MEM32:
352 writel(value, up->port.membase + offset);
353 break;
354
21c614a7
PA		 355#ifdef CONFIG_SERIAL_8250_AU1X00
356 case UPIO_AU:
357 __raw_writel(value, up->port.membase + offset);
358 break;
359#endif
3be91ec7
ZR		 360 case UPIO_TSI:
361 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
362 writeb(value, up->port.membase + offset);
363 break;
21c614a7 364
beab697a
MSJ		 365 case UPIO_DWAPB:
366 /* Save the LCR value so it can be re-written when a
367 * Busy Detect interrupt occurs. */
368 if (save_offset == UART_LCR)
369 up->lcr = value;
370 writeb(value, up->port.membase + offset);
371 /* Read the IER to ensure any interrupt is cleared before
372 * returning from ISR. */
373 if (save_offset == UART_TX || save_offset == UART_IER)
374 value = serial_in(up, UART_IER);
375 break;
376
1da177e4
LT		 377 default:
378 outb(value, up->port.iobase + offset);
379 }
380}
381
40b36daa
AW		 382static void
383serial_out_sync(struct uart_8250_port *up, int offset, int value)
384{
385 switch (up->port.iotype) {
386 case UPIO_MEM:
387 case UPIO_MEM32:
388#ifdef CONFIG_SERIAL_8250_AU1X00
389 case UPIO_AU:
390#endif
beab697a 391 case UPIO_DWAPB:
40b36daa
AW		 392 serial_out(up, offset, value);
393 serial_in(up, UART_LCR); /* safe, no side-effects */
394 break;
395 default:
396 serial_out(up, offset, value);
397 }
398}
399
1da177e4
LT		 400/*
401 * We used to support using pause I/O for certain machines. We
402 * haven't supported this for a while, but just in case it's badly
403 * needed for certain old 386 machines, I've left these #define's
404 * in....
405 */
406#define serial_inp(up, offset) serial_in(up, offset)
407#define serial_outp(up, offset, value) serial_out(up, offset, value)
408
b32b19b8
JAH		 409/* Uart divisor latch read */
410static inline int _serial_dl_read(struct uart_8250_port *up)
411{
412 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
413}
414
415/* Uart divisor latch write */
416static inline void _serial_dl_write(struct uart_8250_port *up, int value)
417{
418 serial_outp(up, UART_DLL, value & 0xff);
419 serial_outp(up, UART_DLM, value >> 8 & 0xff);
420}
421
422#ifdef CONFIG_SERIAL_8250_AU1X00
423/* Au1x00 haven't got a standard divisor latch */
424static int serial_dl_read(struct uart_8250_port *up)
425{
426 if (up->port.iotype == UPIO_AU)
427 return __raw_readl(up->port.membase + 0x28);
428 else
429 return _serial_dl_read(up);
430}
431
432static void serial_dl_write(struct uart_8250_port *up, int value)
433{
434 if (up->port.iotype == UPIO_AU)
435 __raw_writel(value, up->port.membase + 0x28);
436 else
437 _serial_dl_write(up, value);
438}
439#else
440#define serial_dl_read(up) _serial_dl_read(up)
441#define serial_dl_write(up, value) _serial_dl_write(up, value)
442#endif
1da177e4
LT		 443
444/*
445 * For the 16C950
446 */
447static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
448{
449 serial_out(up, UART_SCR, offset);
450 serial_out(up, UART_ICR, value);
451}
452
453static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
454{
455 unsigned int value;
456
457 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
458 serial_out(up, UART_SCR, offset);
459 value = serial_in(up, UART_ICR);
460 serial_icr_write(up, UART_ACR, up->acr);
461
462 return value;
463}
464
465/*
466 * FIFO support.
467 */
468static inline void serial8250_clear_fifos(struct uart_8250_port *p)
469{
470 if (p->capabilities & UART_CAP_FIFO) {
471 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
472 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
473 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
474 serial_outp(p, UART_FCR, 0);
475 }
476}
477
478/*
479 * IER sleep support. UARTs which have EFRs need the "extended
480 * capability" bit enabled. Note that on XR16C850s, we need to
481 * reset LCR to write to IER.
482 */
483static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
484{
485 if (p->capabilities & UART_CAP_SLEEP) {
486 if (p->capabilities & UART_CAP_EFR) {
487 serial_outp(p, UART_LCR, 0xBF);
488 serial_outp(p, UART_EFR, UART_EFR_ECB);
489 serial_outp(p, UART_LCR, 0);
490 }
491 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
492 if (p->capabilities & UART_CAP_EFR) {
493 serial_outp(p, UART_LCR, 0xBF);
494 serial_outp(p, UART_EFR, 0);
495 serial_outp(p, UART_LCR, 0);
496 }
497 }
498}
499
500#ifdef CONFIG_SERIAL_8250_RSA
501/*
502 * Attempts to turn on the RSA FIFO. Returns zero on failure.
503 * We set the port uart clock rate if we succeed.
504 */
505static int __enable_rsa(struct uart_8250_port *up)
506{
507 unsigned char mode;
508 int result;
509
510 mode = serial_inp(up, UART_RSA_MSR);
511 result = mode & UART_RSA_MSR_FIFO;
512
513 if (!result) {
514 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
515 mode = serial_inp(up, UART_RSA_MSR);
516 result = mode & UART_RSA_MSR_FIFO;
517 }
518
519 if (result)
520 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
521
522 return result;
523}
524
525static void enable_rsa(struct uart_8250_port *up)
526{
527 if (up->port.type == PORT_RSA) {
528 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
529 spin_lock_irq(&up->port.lock);
530 __enable_rsa(up);
531 spin_unlock_irq(&up->port.lock);
532 }
533 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
534 serial_outp(up, UART_RSA_FRR, 0);
535 }
536}
537
538/*
539 * Attempts to turn off the RSA FIFO. Returns zero on failure.
540 * It is unknown why interrupts were disabled in here. However,
541 * the caller is expected to preserve this behaviour by grabbing
542 * the spinlock before calling this function.
543 */
544static void disable_rsa(struct uart_8250_port *up)
545{
546 unsigned char mode;
547 int result;
548
549 if (up->port.type == PORT_RSA &&
550 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
551 spin_lock_irq(&up->port.lock);
552
553 mode = serial_inp(up, UART_RSA_MSR);
554 result = !(mode & UART_RSA_MSR_FIFO);
555
556 if (!result) {
557 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
558 mode = serial_inp(up, UART_RSA_MSR);
559 result = !(mode & UART_RSA_MSR_FIFO);
560 }
561
562 if (result)
563 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
564 spin_unlock_irq(&up->port.lock);
565 }
566}
567#endif /* CONFIG_SERIAL_8250_RSA */
568
569/*
570 * This is a quickie test to see how big the FIFO is.
571 * It doesn't work at all the time, more's the pity.
572 */
573static int size_fifo(struct uart_8250_port *up)
574{
b32b19b8
JAH		 575 unsigned char old_fcr, old_mcr, old_lcr;
576 unsigned short old_dl;
1da177e4
LT		 577 int count;
578
579 old_lcr = serial_inp(up, UART_LCR);
580 serial_outp(up, UART_LCR, 0);
581 old_fcr = serial_inp(up, UART_FCR);
582 old_mcr = serial_inp(up, UART_MCR);
583 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
584 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
585 serial_outp(up, UART_MCR, UART_MCR_LOOP);
586 serial_outp(up, UART_LCR, UART_LCR_DLAB);
b32b19b8
JAH		 587 old_dl = serial_dl_read(up);
588 serial_dl_write(up, 0x0001);
1da177e4
LT		 589 serial_outp(up, UART_LCR, 0x03);
590 for (count = 0; count < 256; count++)
591 serial_outp(up, UART_TX, count);
592 mdelay(20);/* FIXME - schedule_timeout */
593 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
594 (count < 256); count++)
595 serial_inp(up, UART_RX);
596 serial_outp(up, UART_FCR, old_fcr);
597 serial_outp(up, UART_MCR, old_mcr);
598 serial_outp(up, UART_LCR, UART_LCR_DLAB);
b32b19b8 599 serial_dl_write(up, old_dl);
1da177e4
LT		 600 serial_outp(up, UART_LCR, old_lcr);
601
602 return count;
603}
604
605/*
606 * Read UART ID using the divisor method - set DLL and DLM to zero
607 * and the revision will be in DLL and device type in DLM. We
608 * preserve the device state across this.
609 */
610static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
611{
612 unsigned char old_dll, old_dlm, old_lcr;
613 unsigned int id;
614
615 old_lcr = serial_inp(p, UART_LCR);
616 serial_outp(p, UART_LCR, UART_LCR_DLAB);
617
618 old_dll = serial_inp(p, UART_DLL);
619 old_dlm = serial_inp(p, UART_DLM);
620
621 serial_outp(p, UART_DLL, 0);
622 serial_outp(p, UART_DLM, 0);
623
624 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
625
626 serial_outp(p, UART_DLL, old_dll);
627 serial_outp(p, UART_DLM, old_dlm);
628 serial_outp(p, UART_LCR, old_lcr);
629
630 return id;
631}
632
633/*
634 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
635 * When this function is called we know it is at least a StarTech
636 * 16650 V2, but it might be one of several StarTech UARTs, or one of
637 * its clones. (We treat the broken original StarTech 16650 V1 as a
638 * 16550, and why not? Startech doesn't seem to even acknowledge its
639 * existence.)
640 *
641 * What evil have men's minds wrought...
642 */
643static void autoconfig_has_efr(struct uart_8250_port *up)
644{
645 unsigned int id1, id2, id3, rev;
646
647 /*
648 * Everything with an EFR has SLEEP
649 */
650 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
651
652 /*
653 * First we check to see if it's an Oxford Semiconductor UART.
654 *
655 * If we have to do this here because some non-National
656 * Semiconductor clone chips lock up if you try writing to the
657 * LSR register (which serial_icr_read does)
658 */
659
660 /*
661 * Check for Oxford Semiconductor 16C950.
662 *
663 * EFR [4] must be set else this test fails.
664 *
665 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
666 * claims that it's needed for 952 dual UART's (which are not
667 * recommended for new designs).
668 */
669 up->acr = 0;
670 serial_out(up, UART_LCR, 0xBF);
671 serial_out(up, UART_EFR, UART_EFR_ECB);
672 serial_out(up, UART_LCR, 0x00);
673 id1 = serial_icr_read(up, UART_ID1);
674 id2 = serial_icr_read(up, UART_ID2);
675 id3 = serial_icr_read(up, UART_ID3);
676 rev = serial_icr_read(up, UART_REV);
677
678 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
679
680 if (id1 == 0x16 && id2 == 0xC9 &&
681 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
682 up->port.type = PORT_16C950;
4ba5e35d
RK		 683
684 /*
685 * Enable work around for the Oxford Semiconductor 952 rev B
686 * chip which causes it to seriously miscalculate baud rates
687 * when DLL is 0.
688 */
689 if (id3 == 0x52 && rev == 0x01)
690 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 691 return;
692 }
693
694 /*
695 * We check for a XR16C850 by setting DLL and DLM to 0, and then
696 * reading back DLL and DLM. The chip type depends on the DLM
697 * value read back:
698 * 0x10 - XR16C850 and the DLL contains the chip revision.
699 * 0x12 - XR16C2850.
700 * 0x14 - XR16C854.
701 */
702 id1 = autoconfig_read_divisor_id(up);
703 DEBUG_AUTOCONF("850id=%04x ", id1);
704
705 id2 = id1 >> 8;
706 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 707 up->port.type = PORT_16850;
708 return;
709 }
710
711 /*
712 * It wasn't an XR16C850.
713 *
714 * We distinguish between the '654 and the '650 by counting
715 * how many bytes are in the FIFO. I'm using this for now,
716 * since that's the technique that was sent to me in the
717 * serial driver update, but I'm not convinced this works.
718 * I've had problems doing this in the past. -TYT
719 */
720 if (size_fifo(up) == 64)
721 up->port.type = PORT_16654;
722 else
723 up->port.type = PORT_16650V2;
724}
725
726/*
727 * We detected a chip without a FIFO. Only two fall into
728 * this category - the original 8250 and the 16450. The
729 * 16450 has a scratch register (accessible with LCR=0)
730 */
731static void autoconfig_8250(struct uart_8250_port *up)
732{
733 unsigned char scratch, status1, status2;
734
735 up->port.type = PORT_8250;
736
737 scratch = serial_in(up, UART_SCR);
738 serial_outp(up, UART_SCR, 0xa5);
739 status1 = serial_in(up, UART_SCR);
740 serial_outp(up, UART_SCR, 0x5a);
741 status2 = serial_in(up, UART_SCR);
742 serial_outp(up, UART_SCR, scratch);
743
744 if (status1 == 0xa5 && status2 == 0x5a)
745 up->port.type = PORT_16450;
746}
747
748static int broken_efr(struct uart_8250_port *up)
749{
750 /*
751 * Exar ST16C2550 "A2" devices incorrectly detect as
752 * having an EFR, and report an ID of 0x0201. See
753 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
754 */
755 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
756 return 1;
757
758 return 0;
759}
760
761/*
762 * We know that the chip has FIFOs. Does it have an EFR? The
763 * EFR is located in the same register position as the IIR and
764 * we know the top two bits of the IIR are currently set. The
765 * EFR should contain zero. Try to read the EFR.
766 */
767static void autoconfig_16550a(struct uart_8250_port *up)
768{
769 unsigned char status1, status2;
770 unsigned int iersave;
771
772 up->port.type = PORT_16550A;
773 up->capabilities |= UART_CAP_FIFO;
774
775 /*
776 * Check for presence of the EFR when DLAB is set.
777 * Only ST16C650V1 UARTs pass this test.
778 */
779 serial_outp(up, UART_LCR, UART_LCR_DLAB);
780 if (serial_in(up, UART_EFR) == 0) {
781 serial_outp(up, UART_EFR, 0xA8);
782 if (serial_in(up, UART_EFR) != 0) {
783 DEBUG_AUTOCONF("EFRv1 ");
784 up->port.type = PORT_16650;
785 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
786 } else {
787 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
788 }
789 serial_outp(up, UART_EFR, 0);
790 return;
791 }
792
793 /*
794 * Maybe it requires 0xbf to be written to the LCR.
795 * (other ST16C650V2 UARTs, TI16C752A, etc)
796 */
797 serial_outp(up, UART_LCR, 0xBF);
798 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
799 DEBUG_AUTOCONF("EFRv2 ");
800 autoconfig_has_efr(up);
801 return;
802 }
803
804 /*
805 * Check for a National Semiconductor SuperIO chip.
806 * Attempt to switch to bank 2, read the value of the LOOP bit
807 * from EXCR1. Switch back to bank 0, change it in MCR. Then
808 * switch back to bank 2, read it from EXCR1 again and check
809 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4
LT		 810 */
811 serial_outp(up, UART_LCR, 0);
812 status1 = serial_in(up, UART_MCR);
813 serial_outp(up, UART_LCR, 0xE0);
814 status2 = serial_in(up, 0x02); /* EXCR1 */
815
816 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
817 serial_outp(up, UART_LCR, 0);
818 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
819 serial_outp(up, UART_LCR, 0xE0);
820 status2 = serial_in(up, 0x02); /* EXCR1 */
821 serial_outp(up, UART_LCR, 0);
822 serial_outp(up, UART_MCR, status1);
823
824 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 825 unsigned short quot;
826
1da177e4 827 serial_outp(up, UART_LCR, 0xE0);
857dde2e 828
b32b19b8 829 quot = serial_dl_read(up);
857dde2e
DW		 830 quot <<= 3;
831
1da177e4
LT		 832 status1 = serial_in(up, 0x04); /* EXCR1 */
833 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
834 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
835 serial_outp(up, 0x04, status1);
857dde2e 836
b32b19b8 837 serial_dl_write(up, quot);
857dde2e 838
1da177e4 839 serial_outp(up, UART_LCR, 0);
1da177e4 840
857dde2e 841 up->port.uartclk = 921600*16;
1da177e4
LT		 842 up->port.type = PORT_NS16550A;
843 up->capabilities |= UART_NATSEMI;
844 return;
845 }
846 }
847
848 /*
849 * No EFR. Try to detect a TI16750, which only sets bit 5 of
850 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
851 * Try setting it with and without DLAB set. Cheap clones
852 * set bit 5 without DLAB set.
853 */
854 serial_outp(up, UART_LCR, 0);
855 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
856 status1 = serial_in(up, UART_IIR) >> 5;
857 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
858 serial_outp(up, UART_LCR, UART_LCR_DLAB);
859 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
860 status2 = serial_in(up, UART_IIR) >> 5;
861 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
862 serial_outp(up, UART_LCR, 0);
863
864 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
865
866 if (status1 == 6 && status2 == 7) {
867 up->port.type = PORT_16750;
868 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
869 return;
870 }
871
872 /*
873 * Try writing and reading the UART_IER_UUE bit (b6).
874 * If it works, this is probably one of the Xscale platform's
875 * internal UARTs.
876 * We're going to explicitly set the UUE bit to 0 before
877 * trying to write and read a 1 just to make sure it's not
878 * already a 1 and maybe locked there before we even start start.
879 */
880 iersave = serial_in(up, UART_IER);
881 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
882 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
883 /*
884 * OK it's in a known zero state, try writing and reading
885 * without disturbing the current state of the other bits.
886 */
887 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
888 if (serial_in(up, UART_IER) & UART_IER_UUE) {
889 /*
890 * It's an Xscale.
891 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
892 */
893 DEBUG_AUTOCONF("Xscale ");
894 up->port.type = PORT_XSCALE;
895 up->capabilities |= UART_CAP_UUE;
896 return;
897 }
898 } else {
899 /*
900 * If we got here we couldn't force the IER_UUE bit to 0.
901 * Log it and continue.
902 */
903 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
904 }
905 serial_outp(up, UART_IER, iersave);
906}
907
908/*
909 * This routine is called by rs_init() to initialize a specific serial
910 * port. It determines what type of UART chip this serial port is
911 * using: 8250, 16450, 16550, 16550A. The important question is
912 * whether or not this UART is a 16550A or not, since this will
913 * determine whether or not we can use its FIFO features or not.
914 */
915static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
916{
917 unsigned char status1, scratch, scratch2, scratch3;
918 unsigned char save_lcr, save_mcr;
919 unsigned long flags;
920
921 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
922 return;
923
924 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
925 up->port.line, up->port.iobase, up->port.membase);
926
927 /*
928 * We really do need global IRQs disabled here - we're going to
929 * be frobbing the chips IRQ enable register to see if it exists.
930 */
931 spin_lock_irqsave(&up->port.lock, flags);
932// save_flags(flags); cli();
933
934 up->capabilities = 0;
4ba5e35d 935 up->bugs = 0;
1da177e4
LT		 936
937 if (!(up->port.flags & UPF_BUGGY_UART)) {
938 /*
939 * Do a simple existence test first; if we fail this,
940 * there's no point trying anything else.
941 *
942 * 0x80 is used as a nonsense port to prevent against
943 * false positives due to ISA bus float. The
944 * assumption is that 0x80 is a non-existent port;
945 * which should be safe since include/asm/io.h also
946 * makes this assumption.
947 *
948 * Note: this is safe as long as MCR bit 4 is clear
949 * and the device is in "PC" mode.
950 */
951 scratch = serial_inp(up, UART_IER);
952 serial_outp(up, UART_IER, 0);
953#ifdef __i386__
954 outb(0xff, 0x080);
955#endif
48212008
TH		 956 /*
957 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
958 * 16C754B) allow only to modify them if an EFR bit is set.
959 */
960 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 961 serial_outp(up, UART_IER, 0x0F);
962#ifdef __i386__
963 outb(0, 0x080);
964#endif
48212008 965 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 966 serial_outp(up, UART_IER, scratch);
967 if (scratch2 != 0 || scratch3 != 0x0F) {
968 /*
969 * We failed; there's nothing here
970 */
971 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
972 scratch2, scratch3);
973 goto out;
974 }
975 }
976
977 save_mcr = serial_in(up, UART_MCR);
978 save_lcr = serial_in(up, UART_LCR);
979
980 /*
981 * Check to see if a UART is really there. Certain broken
982 * internal modems based on the Rockwell chipset fail this
983 * test, because they apparently don't implement the loopback
984 * test mode. So this test is skipped on the COM 1 through
985 * COM 4 ports. This *should* be safe, since no board
986 * manufacturer would be stupid enough to design a board
987 * that conflicts with COM 1-4 --- we hope!
988 */
989 if (!(up->port.flags & UPF_SKIP_TEST)) {
990 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
991 status1 = serial_inp(up, UART_MSR) & 0xF0;
992 serial_outp(up, UART_MCR, save_mcr);
993 if (status1 != 0x90) {
994 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
995 status1);
996 goto out;
997 }
998 }
999
1000 /*
1001 * We're pretty sure there's a port here. Lets find out what
1002 * type of port it is. The IIR top two bits allows us to find
6f0d618f 1003 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 1004 * determines what we test for next.
1005 *
1006 * We also initialise the EFR (if any) to zero for later. The
1007 * EFR occupies the same register location as the FCR and IIR.
1008 */
1009 serial_outp(up, UART_LCR, 0xBF);
1010 serial_outp(up, UART_EFR, 0);
1011 serial_outp(up, UART_LCR, 0);
1012
1013 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1014 scratch = serial_in(up, UART_IIR) >> 6;
1015
1016 DEBUG_AUTOCONF("iir=%d ", scratch);
1017
1018 switch (scratch) {
1019 case 0:
1020 autoconfig_8250(up);
1021 break;
1022 case 1:
1023 up->port.type = PORT_UNKNOWN;
1024 break;
1025 case 2:
1026 up->port.type = PORT_16550;
1027 break;
1028 case 3:
1029 autoconfig_16550a(up);
1030 break;
1031 }
1032
1033#ifdef CONFIG_SERIAL_8250_RSA
1034 /*
1035 * Only probe for RSA ports if we got the region.
1036 */
1037 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1038 int i;
1039
1040 for (i = 0 ; i < probe_rsa_count; ++i) {
1041 if (probe_rsa[i] == up->port.iobase &&
1042 __enable_rsa(up)) {
1043 up->port.type = PORT_RSA;
1044 break;
1045 }
1046 }
1047 }
1048#endif
21c614a7
PA		 1049
1050#ifdef CONFIG_SERIAL_8250_AU1X00
1051 /* if access method is AU, it is a 16550 with a quirk */
1052 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
1053 up->bugs |= UART_BUG_NOMSR;
1054#endif
1055
1da177e4
LT		 1056 serial_outp(up, UART_LCR, save_lcr);
1057
1058 if (up->capabilities != uart_config[up->port.type].flags) {
1059 printk(KERN_WARNING
1060 "ttyS%d: detected caps %08x should be %08x\n",
1061 up->port.line, up->capabilities,
1062 uart_config[up->port.type].flags);
1063 }
1064
1065 up->port.fifosize = uart_config[up->port.type].fifo_size;
1066 up->capabilities = uart_config[up->port.type].flags;
1067 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1068
1069 if (up->port.type == PORT_UNKNOWN)
1070 goto out;
1071
1072 /*
1073 * Reset the UART.
1074 */
1075#ifdef CONFIG_SERIAL_8250_RSA
1076 if (up->port.type == PORT_RSA)
1077 serial_outp(up, UART_RSA_FRR, 0);
1078#endif
1079 serial_outp(up, UART_MCR, save_mcr);
1080 serial8250_clear_fifos(up);
40b36daa 1081 serial_in(up, UART_RX);
5c8c755c
LB		 1082 if (up->capabilities & UART_CAP_UUE)
1083 serial_outp(up, UART_IER, UART_IER_UUE);
1084 else
1085 serial_outp(up, UART_IER, 0);
1da177e4
LT		 1086
1087 out:
1088 spin_unlock_irqrestore(&up->port.lock, flags);
1089// restore_flags(flags);
1090 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1091}
1092
1093static void autoconfig_irq(struct uart_8250_port *up)
1094{
1095 unsigned char save_mcr, save_ier;
1096 unsigned char save_ICP = 0;
1097 unsigned int ICP = 0;
1098 unsigned long irqs;
1099 int irq;
1100
1101 if (up->port.flags & UPF_FOURPORT) {
1102 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1103 save_ICP = inb_p(ICP);
1104 outb_p(0x80, ICP);
1105 (void) inb_p(ICP);
1106 }
1107
1108 /* forget possible initially masked and pending IRQ */
1109 probe_irq_off(probe_irq_on());
1110 save_mcr = serial_inp(up, UART_MCR);
1111 save_ier = serial_inp(up, UART_IER);
1112 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1113
1114 irqs = probe_irq_on();
1115 serial_outp(up, UART_MCR, 0);
1116 udelay (10);
1117 if (up->port.flags & UPF_FOURPORT) {
1118 serial_outp(up, UART_MCR,
1119 UART_MCR_DTR | UART_MCR_RTS);
1120 } else {
1121 serial_outp(up, UART_MCR,
1122 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1123 }
1124 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1125 (void)serial_inp(up, UART_LSR);
1126 (void)serial_inp(up, UART_RX);
1127 (void)serial_inp(up, UART_IIR);
1128 (void)serial_inp(up, UART_MSR);
1129 serial_outp(up, UART_TX, 0xFF);
1130 udelay (20);
1131 irq = probe_irq_off(irqs);
1132
1133 serial_outp(up, UART_MCR, save_mcr);
1134 serial_outp(up, UART_IER, save_ier);
1135
1136 if (up->port.flags & UPF_FOURPORT)
1137 outb_p(save_ICP, ICP);
1138
1139 up->port.irq = (irq > 0) ? irq : 0;
1140}
1141
e763b90c
RK		 1142static inline void __stop_tx(struct uart_8250_port *p)
1143{
1144 if (p->ier & UART_IER_THRI) {
1145 p->ier &= ~UART_IER_THRI;
1146 serial_out(p, UART_IER, p->ier);
1147 }
1148}
1149
b129a8cc 1150static void serial8250_stop_tx(struct uart_port *port)
1da177e4
LT		 1151{
1152 struct uart_8250_port *up = (struct uart_8250_port *)port;
1153
e763b90c 1154 __stop_tx(up);
1da177e4
LT		 1155
1156 /*
e763b90c 1157 * We really want to stop the transmitter from sending.
1da177e4 1158 */
e763b90c 1159 if (up->port.type == PORT_16C950) {
1da177e4
LT		 1160 up->acr |= UART_ACR_TXDIS;
1161 serial_icr_write(up, UART_ACR, up->acr);
1162 }
1163}
1164
55d3b282
RK		 1165static void transmit_chars(struct uart_8250_port *up);
1166
b129a8cc 1167static void serial8250_start_tx(struct uart_port *port)
1da177e4
LT		 1168{
1169 struct uart_8250_port *up = (struct uart_8250_port *)port;
1170
1171 if (!(up->ier & UART_IER_THRI)) {
1172 up->ier |= UART_IER_THRI;
1173 serial_out(up, UART_IER, up->ier);
55d3b282 1174
67f7654e 1175 if (up->bugs & UART_BUG_TXEN) {
55d3b282
RK		 1176 unsigned char lsr, iir;
1177 lsr = serial_in(up, UART_LSR);
1178 iir = serial_in(up, UART_IIR);
1179 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT)
1180 transmit_chars(up);
1181 }
1da177e4 1182 }
e763b90c 1183
1da177e4 1184 /*
e763b90c 1185 * Re-enable the transmitter if we disabled it.
1da177e4 1186 */
e763b90c 1187 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1188 up->acr &= ~UART_ACR_TXDIS;
1189 serial_icr_write(up, UART_ACR, up->acr);
1190 }
1191}
1192
1193static void serial8250_stop_rx(struct uart_port *port)
1194{
1195 struct uart_8250_port *up = (struct uart_8250_port *)port;
1196
1197 up->ier &= ~UART_IER_RLSI;
1198 up->port.read_status_mask &= ~UART_LSR_DR;
1199 serial_out(up, UART_IER, up->ier);
1200}
1201
1202static void serial8250_enable_ms(struct uart_port *port)
1203{
1204 struct uart_8250_port *up = (struct uart_8250_port *)port;
1205
21c614a7
PA		 1206 /* no MSR capabilities */
1207 if (up->bugs & UART_BUG_NOMSR)
1208 return;
1209
1da177e4
LT		 1210 up->ier |= UART_IER_MSI;
1211 serial_out(up, UART_IER, up->ier);
1212}
1213
ea8874dc 1214static void
cc79aa9d 1215receive_chars(struct uart_8250_port *up, unsigned int *status)
1da177e4
LT		 1216{
1217 struct tty_struct *tty = up->port.info->tty;
1218 unsigned char ch, lsr = *status;
1219 int max_count = 256;
1220 char flag;
1221
1222 do {
1da177e4
LT		 1223 ch = serial_inp(up, UART_RX);
1224 flag = TTY_NORMAL;
1225 up->port.icount.rx++;
1226
1227#ifdef CONFIG_SERIAL_8250_CONSOLE
1228 /*
1229 * Recover the break flag from console xmit
1230 */
1231 if (up->port.line == up->port.cons->index) {
1232 lsr |= up->lsr_break_flag;
1233 up->lsr_break_flag = 0;
1234 }
1235#endif
1236
1237 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
1238 UART_LSR_FE | UART_LSR_OE))) {
1239 /*
1240 * For statistics only
1241 */
1242 if (lsr & UART_LSR_BI) {
1243 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1244 up->port.icount.brk++;
1245 /*
1246 * We do the SysRQ and SAK checking
1247 * here because otherwise the break
1248 * may get masked by ignore_status_mask
1249 * or read_status_mask.
1250 */
1251 if (uart_handle_break(&up->port))
1252 goto ignore_char;
1253 } else if (lsr & UART_LSR_PE)
1254 up->port.icount.parity++;
1255 else if (lsr & UART_LSR_FE)
1256 up->port.icount.frame++;
1257 if (lsr & UART_LSR_OE)
1258 up->port.icount.overrun++;
1259
1260 /*
23907eb8 1261 * Mask off conditions which should be ignored.
1da177e4
LT		 1262 */
1263 lsr &= up->port.read_status_mask;
1264
1265 if (lsr & UART_LSR_BI) {
1266 DEBUG_INTR("handling break....");
1267 flag = TTY_BREAK;
1268 } else if (lsr & UART_LSR_PE)
1269 flag = TTY_PARITY;
1270 else if (lsr & UART_LSR_FE)
1271 flag = TTY_FRAME;
1272 }
7d12e780 1273 if (uart_handle_sysrq_char(&up->port, ch))
1da177e4 1274 goto ignore_char;
05ab3014
RK		 1275
1276 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1277
1da177e4
LT		 1278 ignore_char:
1279 lsr = serial_inp(up, UART_LSR);
1280 } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
1281 spin_unlock(&up->port.lock);
1282 tty_flip_buffer_push(tty);
1283 spin_lock(&up->port.lock);
1284 *status = lsr;
1285}
1286
ea8874dc 1287static void transmit_chars(struct uart_8250_port *up)
1da177e4
LT		 1288{
1289 struct circ_buf *xmit = &up->port.info->xmit;
1290 int count;
1291
1292 if (up->port.x_char) {
1293 serial_outp(up, UART_TX, up->port.x_char);
1294 up->port.icount.tx++;
1295 up->port.x_char = 0;
1296 return;
1297 }
b129a8cc
RK		 1298 if (uart_tx_stopped(&up->port)) {
1299 serial8250_stop_tx(&up->port);
1300 return;
1301 }
1302 if (uart_circ_empty(xmit)) {
e763b90c 1303 __stop_tx(up);
1da177e4
LT		 1304 return;
1305 }
1306
1307 count = up->tx_loadsz;
1308 do {
1309 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1310 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1311 up->port.icount.tx++;
1312 if (uart_circ_empty(xmit))
1313 break;
1314 } while (--count > 0);
1315
1316 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1317 uart_write_wakeup(&up->port);
1318
1319 DEBUG_INTR("THRE...");
1320
1321 if (uart_circ_empty(xmit))
e763b90c 1322 __stop_tx(up);
1da177e4
LT		 1323}
1324
2af7cd68 1325static unsigned int check_modem_status(struct uart_8250_port *up)
1da177e4 1326{
2af7cd68
RK		 1327 unsigned int status = serial_in(up, UART_MSR);
1328
fdc30b3d
TI		 1329 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1330 up->port.info != NULL) {
2af7cd68
RK		 1331 if (status & UART_MSR_TERI)
1332 up->port.icount.rng++;
1333 if (status & UART_MSR_DDSR)
1334 up->port.icount.dsr++;
1335 if (status & UART_MSR_DDCD)
1336 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1337 if (status & UART_MSR_DCTS)
1338 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1339
1340 wake_up_interruptible(&up->port.info->delta_msr_wait);
1341 }
1da177e4 1342
2af7cd68 1343 return status;
1da177e4
LT		 1344}
1345
1346/*
1347 * This handles the interrupt from one port.
1348 */
1349static inline void
7d12e780 1350serial8250_handle_port(struct uart_8250_port *up)
1da177e4 1351{
45e24601 1352 unsigned int status;
4bf3631c 1353 unsigned long flags;
45e24601 1354
4bf3631c 1355 spin_lock_irqsave(&up->port.lock, flags);
45e24601
RK		 1356
1357 status = serial_inp(up, UART_LSR);
1da177e4
LT		 1358
1359 DEBUG_INTR("status = %x...", status);
1360
1361 if (status & UART_LSR_DR)
7d12e780 1362 receive_chars(up, &status);
1da177e4
LT		 1363 check_modem_status(up);
1364 if (status & UART_LSR_THRE)
1365 transmit_chars(up);
45e24601 1366
4bf3631c 1367 spin_unlock_irqrestore(&up->port.lock, flags);
1da177e4
LT		 1368}
1369
1370/*
1371 * This is the serial driver's interrupt routine.
1372 *
1373 * Arjan thinks the old way was overly complex, so it got simplified.
1374 * Alan disagrees, saying that need the complexity to handle the weird
1375 * nature of ISA shared interrupts. (This is a special exception.)
1376 *
1377 * In order to handle ISA shared interrupts properly, we need to check
1378 * that all ports have been serviced, and therefore the ISA interrupt
1379 * line has been de-asserted.
1380 *
1381 * This means we need to loop through all ports. checking that they
1382 * don't have an interrupt pending.
1383 */
7d12e780 1384static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1da177e4
LT		 1385{
1386 struct irq_info *i = dev_id;
1387 struct list_head *l, *end = NULL;
1388 int pass_counter = 0, handled = 0;
1389
1390 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1391
1392 spin_lock(&i->lock);
1393
1394 l = i->head;
1395 do {
1396 struct uart_8250_port *up;
1397 unsigned int iir;
1398
1399 up = list_entry(l, struct uart_8250_port, list);
1400
1401 iir = serial_in(up, UART_IIR);
1402 if (!(iir & UART_IIR_NO_INT)) {
7d12e780 1403 serial8250_handle_port(up);
1da177e4
LT		 1404
1405 handled = 1;
1406
beab697a
MSJ		 1407 end = NULL;
1408 } else if (up->port.iotype == UPIO_DWAPB &&
1409 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1410 /* The DesignWare APB UART has an Busy Detect (0x07)
1411 * interrupt meaning an LCR write attempt occured while the
1412 * UART was busy. The interrupt must be cleared by reading
1413 * the UART status register (USR) and the LCR re-written. */
1414 unsigned int status;
1415 status = *(volatile u32 *)up->port.private_data;
1416 serial_out(up, UART_LCR, up->lcr);
1417
1418 handled = 1;
1419
1da177e4
LT		 1420 end = NULL;
1421 } else if (end == NULL)
1422 end = l;
1423
1424 l = l->next;
1425
1426 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1427 /* If we hit this, we're dead. */
1428 printk(KERN_ERR "serial8250: too much work for "
1429 "irq%d\n", irq);
1430 break;
1431 }
1432 } while (l != end);
1433
1434 spin_unlock(&i->lock);
1435
1436 DEBUG_INTR("end.\n");
1437
1438 return IRQ_RETVAL(handled);
1439}
1440
1441/*
1442 * To support ISA shared interrupts, we need to have one interrupt
1443 * handler that ensures that the IRQ line has been deasserted
1444 * before returning. Failing to do this will result in the IRQ
1445 * line being stuck active, and, since ISA irqs are edge triggered,
1446 * no more IRQs will be seen.
1447 */
1448static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1449{
1450 spin_lock_irq(&i->lock);
1451
1452 if (!list_empty(i->head)) {
1453 if (i->head == &up->list)
1454 i->head = i->head->next;
1455 list_del(&up->list);
1456 } else {
1457 BUG_ON(i->head != &up->list);
1458 i->head = NULL;
1459 }
1460
1461 spin_unlock_irq(&i->lock);
1462}
1463
1464static int serial_link_irq_chain(struct uart_8250_port *up)
1465{
1466 struct irq_info *i = irq_lists + up->port.irq;
40663cc7 1467 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1da177e4
LT		 1468
1469 spin_lock_irq(&i->lock);
1470
1471 if (i->head) {
1472 list_add(&up->list, i->head);
1473 spin_unlock_irq(&i->lock);
1474
1475 ret = 0;
1476 } else {
1477 INIT_LIST_HEAD(&up->list);
1478 i->head = &up->list;
1479 spin_unlock_irq(&i->lock);
1480
1481 ret = request_irq(up->port.irq, serial8250_interrupt,
1482 irq_flags, "serial", i);
1483 if (ret < 0)
1484 serial_do_unlink(i, up);
1485 }
1486
1487 return ret;
1488}
1489
1490static void serial_unlink_irq_chain(struct uart_8250_port *up)
1491{
1492 struct irq_info *i = irq_lists + up->port.irq;
1493
1494 BUG_ON(i->head == NULL);
1495
1496 if (list_empty(i->head))
1497 free_irq(up->port.irq, i);
1498
1499 serial_do_unlink(i, up);
1500}
1501
40b36daa
AW		 1502/* Base timer interval for polling */
1503static inline int poll_timeout(int timeout)
1504{
1505 return timeout > 6 ? (timeout / 2 - 2) : 1;
1506}
1507
1da177e4
LT		 1508/*
1509 * This function is used to handle ports that do not have an
1510 * interrupt. This doesn't work very well for 16450's, but gives
1511 * barely passable results for a 16550A. (Although at the expense
1512 * of much CPU overhead).
1513 */
1514static void serial8250_timeout(unsigned long data)
1515{
1516 struct uart_8250_port *up = (struct uart_8250_port *)data;
1da177e4
LT		 1517 unsigned int iir;
1518
1519 iir = serial_in(up, UART_IIR);
45e24601 1520 if (!(iir & UART_IIR_NO_INT))
7d12e780 1521 serial8250_handle_port(up);
40b36daa
AW		 1522 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1523}
1524
1525static void serial8250_backup_timeout(unsigned long data)
1526{
1527 struct uart_8250_port *up = (struct uart_8250_port *)data;
1528 unsigned int iir, ier = 0;
1529
1530 /*
1531 * Must disable interrupts or else we risk racing with the interrupt
1532 * based handler.
1533 */
1534 if (is_real_interrupt(up->port.irq)) {
1535 ier = serial_in(up, UART_IER);
1536 serial_out(up, UART_IER, 0);
1537 }
1da177e4 1538
40b36daa
AW		 1539 iir = serial_in(up, UART_IIR);
1540
1541 /*
1542 * This should be a safe test for anyone who doesn't trust the
1543 * IIR bits on their UART, but it's specifically designed for
1544 * the "Diva" UART used on the management processor on many HP
1545 * ia64 and parisc boxes.
1546 */
1547 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1548 (!uart_circ_empty(&up->port.info->xmit) || up->port.x_char) &&
1549 (serial_in(up, UART_LSR) & UART_LSR_THRE)) {
1550 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1551 iir |= UART_IIR_THRI;
1552 }
1553
1554 if (!(iir & UART_IIR_NO_INT))
1555 serial8250_handle_port(up);
1556
1557 if (is_real_interrupt(up->port.irq))
1558 serial_out(up, UART_IER, ier);
1559
1560 /* Standard timer interval plus 0.2s to keep the port running */
1561 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout) + HZ/5);
1da177e4
LT		 1562}
1563
1564static unsigned int serial8250_tx_empty(struct uart_port *port)
1565{
1566 struct uart_8250_port *up = (struct uart_8250_port *)port;
1567 unsigned long flags;
1568 unsigned int ret;
1569
1570 spin_lock_irqsave(&up->port.lock, flags);
1571 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1572 spin_unlock_irqrestore(&up->port.lock, flags);
1573
1574 return ret;
1575}
1576
1577static unsigned int serial8250_get_mctrl(struct uart_port *port)
1578{
1579 struct uart_8250_port *up = (struct uart_8250_port *)port;
2af7cd68 1580 unsigned int status;
1da177e4
LT		 1581 unsigned int ret;
1582
2af7cd68 1583 status = check_modem_status(up);
1da177e4
LT		 1584
1585 ret = 0;
1586 if (status & UART_MSR_DCD)
1587 ret |= TIOCM_CAR;
1588 if (status & UART_MSR_RI)
1589 ret |= TIOCM_RNG;
1590 if (status & UART_MSR_DSR)
1591 ret |= TIOCM_DSR;
1592 if (status & UART_MSR_CTS)
1593 ret |= TIOCM_CTS;
1594 return ret;
1595}
1596
1597static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1598{
1599 struct uart_8250_port *up = (struct uart_8250_port *)port;
1600 unsigned char mcr = 0;
1601
1602 if (mctrl & TIOCM_RTS)
1603 mcr |= UART_MCR_RTS;
1604 if (mctrl & TIOCM_DTR)
1605 mcr |= UART_MCR_DTR;
1606 if (mctrl & TIOCM_OUT1)
1607 mcr |= UART_MCR_OUT1;
1608 if (mctrl & TIOCM_OUT2)
1609 mcr |= UART_MCR_OUT2;
1610 if (mctrl & TIOCM_LOOP)
1611 mcr |= UART_MCR_LOOP;
1612
1613 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1614
1615 serial_out(up, UART_MCR, mcr);
1616}
1617
1618static void serial8250_break_ctl(struct uart_port *port, int break_state)
1619{
1620 struct uart_8250_port *up = (struct uart_8250_port *)port;
1621 unsigned long flags;
1622
1623 spin_lock_irqsave(&up->port.lock, flags);
1624 if (break_state == -1)
1625 up->lcr |= UART_LCR_SBC;
1626 else
1627 up->lcr &= ~UART_LCR_SBC;
1628 serial_out(up, UART_LCR, up->lcr);
1629 spin_unlock_irqrestore(&up->port.lock, flags);
1630}
1631
40b36daa
AW		 1632#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1633
1634/*
1635 * Wait for transmitter & holding register to empty
1636 */
1637static inline void wait_for_xmitr(struct uart_8250_port *up, int bits)
1638{
1639 unsigned int status, tmout = 10000;
1640
1641 /* Wait up to 10ms for the character(s) to be sent. */
1642 do {
1643 status = serial_in(up, UART_LSR);
1644
1645 if (status & UART_LSR_BI)
1646 up->lsr_break_flag = UART_LSR_BI;
1647
1648 if (--tmout == 0)
1649 break;
1650 udelay(1);
1651 } while ((status & bits) != bits);
1652
1653 /* Wait up to 1s for flow control if necessary */
1654 if (up->port.flags & UPF_CONS_FLOW) {
1655 tmout = 1000000;
1656 while (!(serial_in(up, UART_MSR) & UART_MSR_CTS) && --tmout) {
1657 udelay(1);
1658 touch_nmi_watchdog();
1659 }
1660 }
1661}
1662
1da177e4
LT		 1663static int serial8250_startup(struct uart_port *port)
1664{
1665 struct uart_8250_port *up = (struct uart_8250_port *)port;
1666 unsigned long flags;
55d3b282 1667 unsigned char lsr, iir;
1da177e4
LT		 1668 int retval;
1669
1670 up->capabilities = uart_config[up->port.type].flags;
1671 up->mcr = 0;
1672
1673 if (up->port.type == PORT_16C950) {
1674 /* Wake up and initialize UART */
1675 up->acr = 0;
1676 serial_outp(up, UART_LCR, 0xBF);
1677 serial_outp(up, UART_EFR, UART_EFR_ECB);
1678 serial_outp(up, UART_IER, 0);
1679 serial_outp(up, UART_LCR, 0);
1680 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1681 serial_outp(up, UART_LCR, 0xBF);
1682 serial_outp(up, UART_EFR, UART_EFR_ECB);
1683 serial_outp(up, UART_LCR, 0);
1684 }
1685
1686#ifdef CONFIG_SERIAL_8250_RSA
1687 /*
1688 * If this is an RSA port, see if we can kick it up to the
1689 * higher speed clock.
1690 */
1691 enable_rsa(up);
1692#endif
1693
1694 /*
1695 * Clear the FIFO buffers and disable them.
7f927fcc 1696 * (they will be reenabled in set_termios())
1da177e4
LT		 1697 */
1698 serial8250_clear_fifos(up);
1699
1700 /*
1701 * Clear the interrupt registers.
1702 */
1703 (void) serial_inp(up, UART_LSR);
1704 (void) serial_inp(up, UART_RX);
1705 (void) serial_inp(up, UART_IIR);
1706 (void) serial_inp(up, UART_MSR);
1707
1708 /*
1709 * At this point, there's no way the LSR could still be 0xff;
1710 * if it is, then bail out, because there's likely no UART
1711 * here.
1712 */
1713 if (!(up->port.flags & UPF_BUGGY_UART) &&
1714 (serial_inp(up, UART_LSR) == 0xff)) {
1715 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
1716 return -ENODEV;
1717 }
1718
1719 /*
1720 * For a XR16C850, we need to set the trigger levels
1721 */
1722 if (up->port.type == PORT_16850) {
1723 unsigned char fctr;
1724
1725 serial_outp(up, UART_LCR, 0xbf);
1726
1727 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1728 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1729 serial_outp(up, UART_TRG, UART_TRG_96);
1730 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1731 serial_outp(up, UART_TRG, UART_TRG_96);
1732
1733 serial_outp(up, UART_LCR, 0);
1734 }
1735
40b36daa
AW		 1736 if (is_real_interrupt(up->port.irq)) {
1737 /*
1738 * Test for UARTs that do not reassert THRE when the
1739 * transmitter is idle and the interrupt has already
1740 * been cleared. Real 16550s should always reassert
1741 * this interrupt whenever the transmitter is idle and
1742 * the interrupt is enabled. Delays are necessary to
1743 * allow register changes to become visible.
1744 */
1745 spin_lock_irqsave(&up->port.lock, flags);
1746
1747 wait_for_xmitr(up, UART_LSR_THRE);
1748 serial_out_sync(up, UART_IER, UART_IER_THRI);
1749 udelay(1); /* allow THRE to set */
1750 serial_in(up, UART_IIR);
1751 serial_out(up, UART_IER, 0);
1752 serial_out_sync(up, UART_IER, UART_IER_THRI);
1753 udelay(1); /* allow a working UART time to re-assert THRE */
1754 iir = serial_in(up, UART_IIR);
1755 serial_out(up, UART_IER, 0);
1756
1757 spin_unlock_irqrestore(&up->port.lock, flags);
1758
1759 /*
1760 * If the interrupt is not reasserted, setup a timer to
1761 * kick the UART on a regular basis.
1762 */
1763 if (iir & UART_IIR_NO_INT) {
1764 pr_debug("ttyS%d - using backup timer\n", port->line);
1765 up->timer.function = serial8250_backup_timeout;
1766 up->timer.data = (unsigned long)up;
1767 mod_timer(&up->timer, jiffies +
1768 poll_timeout(up->port.timeout) + HZ/5);
1769 }
1770 }
1771
1da177e4
LT		 1772 /*
1773 * If the "interrupt" for this port doesn't correspond with any
1774 * hardware interrupt, we use a timer-based system. The original
1775 * driver used to do this with IRQ0.
1776 */
1777 if (!is_real_interrupt(up->port.irq)) {
1da177e4 1778 up->timer.data = (unsigned long)up;
40b36daa 1779 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1da177e4
LT		 1780 } else {
1781 retval = serial_link_irq_chain(up);
1782 if (retval)
1783 return retval;
1784 }
1785
1786 /*
1787 * Now, initialize the UART
1788 */
1789 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
1790
1791 spin_lock_irqsave(&up->port.lock, flags);
1792 if (up->port.flags & UPF_FOURPORT) {
1793 if (!is_real_interrupt(up->port.irq))
1794 up->port.mctrl |= TIOCM_OUT1;
1795 } else
1796 /*
1797 * Most PC uarts need OUT2 raised to enable interrupts.
1798 */
1799 if (is_real_interrupt(up->port.irq))
1800 up->port.mctrl |= TIOCM_OUT2;
1801
1802 serial8250_set_mctrl(&up->port, up->port.mctrl);
55d3b282
RK		 1803
1804 /*
1805 * Do a quick test to see if we receive an
1806 * interrupt when we enable the TX irq.
1807 */
1808 serial_outp(up, UART_IER, UART_IER_THRI);
1809 lsr = serial_in(up, UART_LSR);
1810 iir = serial_in(up, UART_IIR);
1811 serial_outp(up, UART_IER, 0);
1812
1813 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 1814 if (!(up->bugs & UART_BUG_TXEN)) {
1815 up->bugs |= UART_BUG_TXEN;
55d3b282
RK		 1816 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
1817 port->line);
1818 }
1819 } else {
67f7654e 1820 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 1821 }
1822
1da177e4
LT		 1823 spin_unlock_irqrestore(&up->port.lock, flags);
1824
1825 /*
1826 * Finally, enable interrupts. Note: Modem status interrupts
1827 * are set via set_termios(), which will be occurring imminently
1828 * anyway, so we don't enable them here.
1829 */
1830 up->ier = UART_IER_RLSI | UART_IER_RDI;
1831 serial_outp(up, UART_IER, up->ier);
1832
1833 if (up->port.flags & UPF_FOURPORT) {
1834 unsigned int icp;
1835 /*
1836 * Enable interrupts on the AST Fourport board
1837 */
1838 icp = (up->port.iobase & 0xfe0) | 0x01f;
1839 outb_p(0x80, icp);
1840 (void) inb_p(icp);
1841 }
1842
1843 /*
1844 * And clear the interrupt registers again for luck.
1845 */
1846 (void) serial_inp(up, UART_LSR);
1847 (void) serial_inp(up, UART_RX);
1848 (void) serial_inp(up, UART_IIR);
1849 (void) serial_inp(up, UART_MSR);
1850
1851 return 0;
1852}
1853
1854static void serial8250_shutdown(struct uart_port *port)
1855{
1856 struct uart_8250_port *up = (struct uart_8250_port *)port;
1857 unsigned long flags;
1858
1859 /*
1860 * Disable interrupts from this port
1861 */
1862 up->ier = 0;
1863 serial_outp(up, UART_IER, 0);
1864
1865 spin_lock_irqsave(&up->port.lock, flags);
1866 if (up->port.flags & UPF_FOURPORT) {
1867 /* reset interrupts on the AST Fourport board */
1868 inb((up->port.iobase & 0xfe0) | 0x1f);
1869 up->port.mctrl |= TIOCM_OUT1;
1870 } else
1871 up->port.mctrl &= ~TIOCM_OUT2;
1872
1873 serial8250_set_mctrl(&up->port, up->port.mctrl);
1874 spin_unlock_irqrestore(&up->port.lock, flags);
1875
1876 /*
1877 * Disable break condition and FIFOs
1878 */
1879 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
1880 serial8250_clear_fifos(up);
1881
1882#ifdef CONFIG_SERIAL_8250_RSA
1883 /*
1884 * Reset the RSA board back to 115kbps compat mode.
1885 */
1886 disable_rsa(up);
1887#endif
1888
1889 /*
1890 * Read data port to reset things, and then unlink from
1891 * the IRQ chain.
1892 */
1893 (void) serial_in(up, UART_RX);
1894
40b36daa
AW		 1895 del_timer_sync(&up->timer);
1896 up->timer.function = serial8250_timeout;
1897 if (is_real_interrupt(up->port.irq))
1da177e4
LT		 1898 serial_unlink_irq_chain(up);
1899}
1900
1901static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
1902{
1903 unsigned int quot;
1904
1905 /*
1906 * Handle magic divisors for baud rates above baud_base on
1907 * SMSC SuperIO chips.
1908 */
1909 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1910 baud == (port->uartclk/4))
1911 quot = 0x8001;
1912 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1913 baud == (port->uartclk/8))
1914 quot = 0x8002;
1915 else
1916 quot = uart_get_divisor(port, baud);
1917
1918 return quot;
1919}
1920
1921static void
606d099c
AC		 1922serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
1923 struct ktermios *old)
1da177e4
LT		 1924{
1925 struct uart_8250_port *up = (struct uart_8250_port *)port;
1926 unsigned char cval, fcr = 0;
1927 unsigned long flags;
1928 unsigned int baud, quot;
1929
1930 switch (termios->c_cflag & CSIZE) {
1931 case CS5:
0a8b80c5 1932 cval = UART_LCR_WLEN5;
1da177e4
LT		 1933 break;
1934 case CS6:
0a8b80c5 1935 cval = UART_LCR_WLEN6;
1da177e4
LT		 1936 break;
1937 case CS7:
0a8b80c5 1938 cval = UART_LCR_WLEN7;
1da177e4
LT		 1939 break;
1940 default:
1941 case CS8:
0a8b80c5 1942 cval = UART_LCR_WLEN8;
1da177e4
LT		 1943 break;
1944 }
1945
1946 if (termios->c_cflag & CSTOPB)
0a8b80c5 1947 cval |= UART_LCR_STOP;
1da177e4
LT		 1948 if (termios->c_cflag & PARENB)
1949 cval |= UART_LCR_PARITY;
1950 if (!(termios->c_cflag & PARODD))
1951 cval |= UART_LCR_EPAR;
1952#ifdef CMSPAR
1953 if (termios->c_cflag & CMSPAR)
1954 cval |= UART_LCR_SPAR;
1955#endif
1956
1957 /*
1958 * Ask the core to calculate the divisor for us.
1959 */
1960 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
1961 quot = serial8250_get_divisor(port, baud);
1962
1963 /*
4ba5e35d 1964 * Oxford Semi 952 rev B workaround
1da177e4 1965 */
4ba5e35d 1966 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
1da177e4
LT		 1967 quot ++;
1968
1969 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
1970 if (baud < 2400)
1971 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
1972 else
1973 fcr = uart_config[up->port.type].fcr;
1974 }
1975
1976 /*
1977 * MCR-based auto flow control. When AFE is enabled, RTS will be
1978 * deasserted when the receive FIFO contains more characters than
1979 * the trigger, or the MCR RTS bit is cleared. In the case where
1980 * the remote UART is not using CTS auto flow control, we must
1981 * have sufficient FIFO entries for the latency of the remote
1982 * UART to respond. IOW, at least 32 bytes of FIFO.
1983 */
1984 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
1985 up->mcr &= ~UART_MCR_AFE;
1986 if (termios->c_cflag & CRTSCTS)
1987 up->mcr |= UART_MCR_AFE;
1988 }
1989
1990 /*
1991 * Ok, we're now changing the port state. Do it with
1992 * interrupts disabled.
1993 */
1994 spin_lock_irqsave(&up->port.lock, flags);
1995
1996 /*
1997 * Update the per-port timeout.
1998 */
1999 uart_update_timeout(port, termios->c_cflag, baud);
2000
2001 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2002 if (termios->c_iflag & INPCK)
2003 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2004 if (termios->c_iflag & (BRKINT | PARMRK))
2005 up->port.read_status_mask |= UART_LSR_BI;
2006
2007 /*
2008 * Characteres to ignore
2009 */
2010 up->port.ignore_status_mask = 0;
2011 if (termios->c_iflag & IGNPAR)
2012 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2013 if (termios->c_iflag & IGNBRK) {
2014 up->port.ignore_status_mask |= UART_LSR_BI;
2015 /*
2016 * If we're ignoring parity and break indicators,
2017 * ignore overruns too (for real raw support).
2018 */
2019 if (termios->c_iflag & IGNPAR)
2020 up->port.ignore_status_mask |= UART_LSR_OE;
2021 }
2022
2023 /*
2024 * ignore all characters if CREAD is not set
2025 */
2026 if ((termios->c_cflag & CREAD) == 0)
2027 up->port.ignore_status_mask |= UART_LSR_DR;
2028
2029 /*
2030 * CTS flow control flag and modem status interrupts
2031 */
2032 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 2033 if (!(up->bugs & UART_BUG_NOMSR) &&
2034 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 2035 up->ier |= UART_IER_MSI;
2036 if (up->capabilities & UART_CAP_UUE)
2037 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
2038
2039 serial_out(up, UART_IER, up->ier);
2040
2041 if (up->capabilities & UART_CAP_EFR) {
2042 unsigned char efr = 0;
2043 /*
2044 * TI16C752/Startech hardware flow control. FIXME:
2045 * - TI16C752 requires control thresholds to be set.
2046 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2047 */
2048 if (termios->c_cflag & CRTSCTS)
2049 efr |= UART_EFR_CTS;
2050
2051 serial_outp(up, UART_LCR, 0xBF);
2052 serial_outp(up, UART_EFR, efr);
2053 }
2054
255341c6
JM		 2055#ifdef CONFIG_ARCH_OMAP15XX
2056 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2057 if (cpu_is_omap1510() && is_omap_port((unsigned int)up->port.membase)) {
2058 if (baud == 115200) {
2059 quot = 1;
2060 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2061 } else
2062 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2063 }
2064#endif
2065
1da177e4
LT		 2066 if (up->capabilities & UART_NATSEMI) {
2067 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2068 serial_outp(up, UART_LCR, 0xe0);
2069 } else {
2070 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2071 }
2072
b32b19b8 2073 serial_dl_write(up, quot);
1da177e4
LT		 2074
2075 /*
2076 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2077 * is written without DLAB set, this mode will be disabled.
2078 */
2079 if (up->port.type == PORT_16750)
2080 serial_outp(up, UART_FCR, fcr);
2081
2082 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2083 up->lcr = cval; /* Save LCR */
2084 if (up->port.type != PORT_16750) {
2085 if (fcr & UART_FCR_ENABLE_FIFO) {
2086 /* emulated UARTs (Lucent Venus 167x) need two steps */
2087 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2088 }
2089 serial_outp(up, UART_FCR, fcr); /* set fcr */
2090 }
2091 serial8250_set_mctrl(&up->port, up->port.mctrl);
2092 spin_unlock_irqrestore(&up->port.lock, flags);
2093}
2094
2095static void
2096serial8250_pm(struct uart_port *port, unsigned int state,
2097 unsigned int oldstate)
2098{
2099 struct uart_8250_port *p = (struct uart_8250_port *)port;
2100
2101 serial8250_set_sleep(p, state != 0);
2102
2103 if (p->pm)
2104 p->pm(port, state, oldstate);
2105}
2106
2107/*
2108 * Resource handling.
2109 */
2110static int serial8250_request_std_resource(struct uart_8250_port *up)
2111{
2112 unsigned int size = 8 << up->port.regshift;
2113 int ret = 0;
2114
2115 switch (up->port.iotype) {
85835f44
SS		 2116 case UPIO_AU:
2117 size = 0x100000;
2118 /* fall thru */
0b30d668
SS		 2119 case UPIO_TSI:
2120 case UPIO_MEM32:
1da177e4 2121 case UPIO_MEM:
beab697a 2122 case UPIO_DWAPB:
1da177e4
LT		 2123 if (!up->port.mapbase)
2124 break;
2125
2126 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2127 ret = -EBUSY;
2128 break;
2129 }
2130
2131 if (up->port.flags & UPF_IOREMAP) {
2132 up->port.membase = ioremap(up->port.mapbase, size);
2133 if (!up->port.membase) {
2134 release_mem_region(up->port.mapbase, size);
2135 ret = -ENOMEM;
2136 }
2137 }
2138 break;
2139
2140 case UPIO_HUB6:
2141 case UPIO_PORT:
2142 if (!request_region(up->port.iobase, size, "serial"))
2143 ret = -EBUSY;
2144 break;
2145 }
2146 return ret;
2147}
2148
2149static void serial8250_release_std_resource(struct uart_8250_port *up)
2150{
2151 unsigned int size = 8 << up->port.regshift;
2152
2153 switch (up->port.iotype) {
85835f44
SS		 2154 case UPIO_AU:
2155 size = 0x100000;
2156 /* fall thru */
0b30d668
SS		 2157 case UPIO_TSI:
2158 case UPIO_MEM32:
1da177e4 2159 case UPIO_MEM:
beab697a 2160 case UPIO_DWAPB:
1da177e4
LT		 2161 if (!up->port.mapbase)
2162 break;
2163
2164 if (up->port.flags & UPF_IOREMAP) {
2165 iounmap(up->port.membase);
2166 up->port.membase = NULL;
2167 }
2168
2169 release_mem_region(up->port.mapbase, size);
2170 break;
2171
2172 case UPIO_HUB6:
2173 case UPIO_PORT:
2174 release_region(up->port.iobase, size);
2175 break;
2176 }
2177}
2178
2179static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2180{
2181 unsigned long start = UART_RSA_BASE << up->port.regshift;
2182 unsigned int size = 8 << up->port.regshift;
0b30d668 2183 int ret = -EINVAL;
1da177e4
LT		 2184
2185 switch (up->port.iotype) {
1da177e4
LT		 2186 case UPIO_HUB6:
2187 case UPIO_PORT:
2188 start += up->port.iobase;
0b30d668
SS		 2189 if (request_region(start, size, "serial-rsa"))
2190 ret = 0;
2191 else
1da177e4
LT		 2192 ret = -EBUSY;
2193 break;
2194 }
2195
2196 return ret;
2197}
2198
2199static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2200{
2201 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2202 unsigned int size = 8 << up->port.regshift;
2203
2204 switch (up->port.iotype) {
1da177e4
LT		 2205 case UPIO_HUB6:
2206 case UPIO_PORT:
2207 release_region(up->port.iobase + offset, size);
2208 break;
2209 }
2210}
2211
2212static void serial8250_release_port(struct uart_port *port)
2213{
2214 struct uart_8250_port *up = (struct uart_8250_port *)port;
2215
2216 serial8250_release_std_resource(up);
2217 if (up->port.type == PORT_RSA)
2218 serial8250_release_rsa_resource(up);
2219}
2220
2221static int serial8250_request_port(struct uart_port *port)
2222{
2223 struct uart_8250_port *up = (struct uart_8250_port *)port;
2224 int ret = 0;
2225
2226 ret = serial8250_request_std_resource(up);
2227 if (ret == 0 && up->port.type == PORT_RSA) {
2228 ret = serial8250_request_rsa_resource(up);
2229 if (ret < 0)
2230 serial8250_release_std_resource(up);
2231 }
2232
2233 return ret;
2234}
2235
2236static void serial8250_config_port(struct uart_port *port, int flags)
2237{
2238 struct uart_8250_port *up = (struct uart_8250_port *)port;
2239 int probeflags = PROBE_ANY;
2240 int ret;
2241
1da177e4
LT		 2242 /*
2243 * Find the region that we can probe for. This in turn
2244 * tells us whether we can probe for the type of port.
2245 */
2246 ret = serial8250_request_std_resource(up);
2247 if (ret < 0)
2248 return;
2249
2250 ret = serial8250_request_rsa_resource(up);
2251 if (ret < 0)
2252 probeflags &= ~PROBE_RSA;
2253
2254 if (flags & UART_CONFIG_TYPE)
2255 autoconfig(up, probeflags);
2256 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2257 autoconfig_irq(up);
2258
2259 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2260 serial8250_release_rsa_resource(up);
2261 if (up->port.type == PORT_UNKNOWN)
2262 serial8250_release_std_resource(up);
2263}
2264
2265static int
2266serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2267{
2268 if (ser->irq >= NR_IRQS || ser->irq < 0 ||
2269 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2270 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2271 ser->type == PORT_STARTECH)
2272 return -EINVAL;
2273 return 0;
2274}
2275
2276static const char *
2277serial8250_type(struct uart_port *port)
2278{
2279 int type = port->type;
2280
2281 if (type >= ARRAY_SIZE(uart_config))
2282 type = 0;
2283 return uart_config[type].name;
2284}
2285
2286static struct uart_ops serial8250_pops = {
2287 .tx_empty = serial8250_tx_empty,
2288 .set_mctrl = serial8250_set_mctrl,
2289 .get_mctrl = serial8250_get_mctrl,
2290 .stop_tx = serial8250_stop_tx,
2291 .start_tx = serial8250_start_tx,
2292 .stop_rx = serial8250_stop_rx,
2293 .enable_ms = serial8250_enable_ms,
2294 .break_ctl = serial8250_break_ctl,
2295 .startup = serial8250_startup,
2296 .shutdown = serial8250_shutdown,
2297 .set_termios = serial8250_set_termios,
2298 .pm = serial8250_pm,
2299 .type = serial8250_type,
2300 .release_port = serial8250_release_port,
2301 .request_port = serial8250_request_port,
2302 .config_port = serial8250_config_port,
2303 .verify_port = serial8250_verify_port,
2304};
2305
2306static struct uart_8250_port serial8250_ports[UART_NR];
2307
2308static void __init serial8250_isa_init_ports(void)
2309{
2310 struct uart_8250_port *up;
2311 static int first = 1;
2312 int i;
2313
2314 if (!first)
2315 return;
2316 first = 0;
2317
a61c2d78 2318 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2319 struct uart_8250_port *up = &serial8250_ports[i];
2320
2321 up->port.line = i;
2322 spin_lock_init(&up->port.lock);
2323
2324 init_timer(&up->timer);
2325 up->timer.function = serial8250_timeout;
2326
2327 /*
2328 * ALPHA_KLUDGE_MCR needs to be killed.
2329 */
2330 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2331 up->mcr_force = ALPHA_KLUDGE_MCR;
2332
2333 up->port.ops = &serial8250_pops;
2334 }
2335
44454bcd 2336 for (i = 0, up = serial8250_ports;
a61c2d78 2337 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
1da177e4
LT		 2338 i++, up++) {
2339 up->port.iobase = old_serial_port[i].port;
2340 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2341 up->port.uartclk = old_serial_port[i].baud_base * 16;
2342 up->port.flags = old_serial_port[i].flags;
2343 up->port.hub6 = old_serial_port[i].hub6;
2344 up->port.membase = old_serial_port[i].iomem_base;
2345 up->port.iotype = old_serial_port[i].io_type;
2346 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2347 if (share_irqs)
2348 up->port.flags |= UPF_SHARE_IRQ;
2349 }
2350}
2351
2352static void __init
2353serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2354{
2355 int i;
2356
2357 serial8250_isa_init_ports();
2358
a61c2d78 2359 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2360 struct uart_8250_port *up = &serial8250_ports[i];
2361
2362 up->port.dev = dev;
2363 uart_add_one_port(drv, &up->port);
2364 }
2365}
2366
2367#ifdef CONFIG_SERIAL_8250_CONSOLE
2368
d358788f
RK		 2369static void serial8250_console_putchar(struct uart_port *port, int ch)
2370{
2371 struct uart_8250_port *up = (struct uart_8250_port *)port;
2372
2373 wait_for_xmitr(up, UART_LSR_THRE);
2374 serial_out(up, UART_TX, ch);
2375}
2376
1da177e4
LT		 2377/*
2378 * Print a string to the serial port trying not to disturb
2379 * any possible real use of the port...
2380 *
2381 * The console_lock must be held when we get here.
2382 */
2383static void
2384serial8250_console_write(struct console *co, const char *s, unsigned int count)
2385{
2386 struct uart_8250_port *up = &serial8250_ports[co->index];
d8a5a8d7 2387 unsigned long flags;
1da177e4 2388 unsigned int ier;
d8a5a8d7 2389 int locked = 1;
1da177e4 2390
78512ece
AM		 2391 touch_nmi_watchdog();
2392
68aa2c0d
AM		 2393 local_irq_save(flags);
2394 if (up->port.sysrq) {
2395 /* serial8250_handle_port() already took the lock */
2396 locked = 0;
2397 } else if (oops_in_progress) {
2398 locked = spin_trylock(&up->port.lock);
d8a5a8d7 2399 } else
68aa2c0d 2400 spin_lock(&up->port.lock);
d8a5a8d7 2401
1da177e4 2402 /*
dc7bf130 2403 * First save the IER then disable the interrupts
1da177e4
LT		 2404 */
2405 ier = serial_in(up, UART_IER);
2406
2407 if (up->capabilities & UART_CAP_UUE)
2408 serial_out(up, UART_IER, UART_IER_UUE);
2409 else
2410 serial_out(up, UART_IER, 0);
2411
d358788f 2412 uart_console_write(&up->port, s, count, serial8250_console_putchar);
1da177e4
LT		 2413
2414 /*
2415 * Finally, wait for transmitter to become empty
2416 * and restore the IER
2417 */
f91a3715 2418 wait_for_xmitr(up, BOTH_EMPTY);
a88d75b2 2419 serial_out(up, UART_IER, ier);
d8a5a8d7
RK		 2420
2421 if (locked)
68aa2c0d
AM		 2422 spin_unlock(&up->port.lock);
2423 local_irq_restore(flags);
1da177e4
LT		 2424}
2425
118c0ace 2426static int __init serial8250_console_setup(struct console *co, char *options)
1da177e4
LT		 2427{
2428 struct uart_port *port;
2429 int baud = 9600;
2430 int bits = 8;
2431 int parity = 'n';
2432 int flow = 'n';
2433
2434 /*
2435 * Check whether an invalid uart number has been specified, and
2436 * if so, search for the first available port that does have
2437 * console support.
2438 */
a61c2d78 2439 if (co->index >= nr_uarts)
1da177e4
LT		 2440 co->index = 0;
2441 port = &serial8250_ports[co->index].port;
2442 if (!port->iobase && !port->membase)
2443 return -ENODEV;
2444
2445 if (options)
2446 uart_parse_options(options, &baud, &parity, &bits, &flow);
2447
2448 return uart_set_options(port, co, baud, parity, bits, flow);
2449}
2450
2451static struct uart_driver serial8250_reg;
2452static struct console serial8250_console = {
2453 .name = "ttyS",
2454 .write = serial8250_console_write,
2455 .device = uart_console_device,
2456 .setup = serial8250_console_setup,
2457 .flags = CON_PRINTBUFFER,
2458 .index = -1,
2459 .data = &serial8250_reg,
2460};
2461
2462static int __init serial8250_console_init(void)
2463{
2464 serial8250_isa_init_ports();
2465 register_console(&serial8250_console);
2466 return 0;
2467}
2468console_initcall(serial8250_console_init);
2469
2470static int __init find_port(struct uart_port *p)
2471{
2472 int line;
2473 struct uart_port *port;
2474
a61c2d78 2475 for (line = 0; line < nr_uarts; line++) {
1da177e4 2476 port = &serial8250_ports[line].port;
50aec3b5 2477 if (uart_match_port(p, port))
1da177e4
LT		 2478 return line;
2479 }
2480 return -ENODEV;
2481}
2482
2483int __init serial8250_start_console(struct uart_port *port, char *options)
2484{
2485 int line;
2486
2487 line = find_port(port);
2488 if (line < 0)
2489 return -ENODEV;
2490
2491 add_preferred_console("ttyS", line, options);
2492 printk("Adding console on ttyS%d at %s 0x%lx (options '%s')\n",
2493 line, port->iotype == UPIO_MEM ? "MMIO" : "I/O port",
2494 port->iotype == UPIO_MEM ? (unsigned long) port->mapbase :
2495 (unsigned long) port->iobase, options);
2496 if (!(serial8250_console.flags & CON_ENABLED)) {
2497 serial8250_console.flags &= ~CON_PRINTBUFFER;
2498 register_console(&serial8250_console);
2499 }
2500 return line;
2501}
2502
2503#define SERIAL8250_CONSOLE &serial8250_console
2504#else
2505#define SERIAL8250_CONSOLE NULL
2506#endif
2507
2508static struct uart_driver serial8250_reg = {
2509 .owner = THIS_MODULE,
2510 .driver_name = "serial",
1da177e4
LT		 2511 .dev_name = "ttyS",
2512 .major = TTY_MAJOR,
2513 .minor = 64,
2514 .nr = UART_NR,
2515 .cons = SERIAL8250_CONSOLE,
2516};
2517
d856c666
RK		 2518/*
2519 * early_serial_setup - early registration for 8250 ports
2520 *
2521 * Setup an 8250 port structure prior to console initialisation. Use
2522 * after console initialisation will cause undefined behaviour.
2523 */
1da177e4
LT		 2524int __init early_serial_setup(struct uart_port *port)
2525{
2526 if (port->line >= ARRAY_SIZE(serial8250_ports))
2527 return -ENODEV;
2528
2529 serial8250_isa_init_ports();
2530 serial8250_ports[port->line].port = *port;
2531 serial8250_ports[port->line].port.ops = &serial8250_pops;
2532 return 0;
2533}
2534
2535/**
2536 * serial8250_suspend_port - suspend one serial port
2537 * @line: serial line number
1da177e4
LT		 2538 *
2539 * Suspend one serial port.
2540 */
2541void serial8250_suspend_port(int line)
2542{
2543 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2544}
2545
2546/**
2547 * serial8250_resume_port - resume one serial port
2548 * @line: serial line number
1da177e4
LT		 2549 *
2550 * Resume one serial port.
2551 */
2552void serial8250_resume_port(int line)
2553{
2554 uart_resume_port(&serial8250_reg, &serial8250_ports[line].port);
2555}
2556
2557/*
2558 * Register a set of serial devices attached to a platform device. The
2559 * list is terminated with a zero flags entry, which means we expect
2560 * all entries to have at least UPF_BOOT_AUTOCONF set.
2561 */
3ae5eaec 2562static int __devinit serial8250_probe(struct platform_device *dev)
1da177e4 2563{
3ae5eaec 2564 struct plat_serial8250_port *p = dev->dev.platform_data;
1da177e4 2565 struct uart_port port;
ec9f47cd 2566 int ret, i;
1da177e4
LT		 2567
2568 memset(&port, 0, sizeof(struct uart_port));
2569
ec9f47cd 2570 for (i = 0; p && p->flags != 0; p++, i++) {
1da177e4
LT		 2571 port.iobase = p->iobase;
2572 port.membase = p->membase;
2573 port.irq = p->irq;
2574 port.uartclk = p->uartclk;
2575 port.regshift = p->regshift;
2576 port.iotype = p->iotype;
2577 port.flags = p->flags;
2578 port.mapbase = p->mapbase;
ec9f47cd 2579 port.hub6 = p->hub6;
3ae5eaec 2580 port.dev = &dev->dev;
1da177e4
LT		 2581 if (share_irqs)
2582 port.flags |= UPF_SHARE_IRQ;
ec9f47cd
RK		 2583 ret = serial8250_register_port(&port);
2584 if (ret < 0) {
3ae5eaec 2585 dev_err(&dev->dev, "unable to register port at index %d "
ec9f47cd
RK		 2586 "(IO%lx MEM%lx IRQ%d): %d\n", i,
2587 p->iobase, p->mapbase, p->irq, ret);
2588 }
1da177e4
LT		 2589 }
2590 return 0;
2591}
2592
2593/*
2594 * Remove serial ports registered against a platform device.
2595 */
3ae5eaec 2596static int __devexit serial8250_remove(struct platform_device *dev)
1da177e4
LT		 2597{
2598 int i;
2599
a61c2d78 2600 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2601 struct uart_8250_port *up = &serial8250_ports[i];
2602
3ae5eaec 2603 if (up->port.dev == &dev->dev)
1da177e4
LT		 2604 serial8250_unregister_port(i);
2605 }
2606 return 0;
2607}
2608
3ae5eaec 2609static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
1da177e4
LT		 2610{
2611 int i;
2612
1da177e4
LT		 2613 for (i = 0; i < UART_NR; i++) {
2614 struct uart_8250_port *up = &serial8250_ports[i];
2615
3ae5eaec 2616 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 2617 uart_suspend_port(&serial8250_reg, &up->port);
2618 }
2619
2620 return 0;
2621}
2622
3ae5eaec 2623static int serial8250_resume(struct platform_device *dev)
1da177e4
LT		 2624{
2625 int i;
2626
1da177e4
LT		 2627 for (i = 0; i < UART_NR; i++) {
2628 struct uart_8250_port *up = &serial8250_ports[i];
2629
3ae5eaec 2630 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 2631 uart_resume_port(&serial8250_reg, &up->port);
2632 }
2633
2634 return 0;
2635}
2636
3ae5eaec 2637static struct platform_driver serial8250_isa_driver = {
1da177e4
LT		 2638 .probe = serial8250_probe,
2639 .remove = __devexit_p(serial8250_remove),
2640 .suspend = serial8250_suspend,
2641 .resume = serial8250_resume,
3ae5eaec
RK		 2642 .driver = {
2643 .name = "serial8250",
7493a314 2644 .owner = THIS_MODULE,
3ae5eaec 2645 },
1da177e4
LT		 2646};
2647
2648/*
2649 * This "device" covers _all_ ISA 8250-compatible serial devices listed
2650 * in the table in include/asm/serial.h
2651 */
2652static struct platform_device *serial8250_isa_devs;
2653
2654/*
2655 * serial8250_register_port and serial8250_unregister_port allows for
2656 * 16x50 serial ports to be configured at run-time, to support PCMCIA
2657 * modems and PCI multiport cards.
2658 */
f392ecfa 2659static DEFINE_MUTEX(serial_mutex);
1da177e4
LT		 2660
2661static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
2662{
2663 int i;
2664
2665 /*
2666 * First, find a port entry which matches.
2667 */
a61c2d78 2668 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 2669 if (uart_match_port(&serial8250_ports[i].port, port))
2670 return &serial8250_ports[i];
2671
2672 /*
2673 * We didn't find a matching entry, so look for the first
2674 * free entry. We look for one which hasn't been previously
2675 * used (indicated by zero iobase).
2676 */
a61c2d78 2677 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 2678 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
2679 serial8250_ports[i].port.iobase == 0)
2680 return &serial8250_ports[i];
2681
2682 /*
2683 * That also failed. Last resort is to find any entry which
2684 * doesn't have a real port associated with it.
2685 */
a61c2d78 2686 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 2687 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
2688 return &serial8250_ports[i];
2689
2690 return NULL;
2691}
2692
2693/**
2694 * serial8250_register_port - register a serial port
2695 * @port: serial port template
2696 *
2697 * Configure the serial port specified by the request. If the
2698 * port exists and is in use, it is hung up and unregistered
2699 * first.
2700 *
2701 * The port is then probed and if necessary the IRQ is autodetected
2702 * If this fails an error is returned.
2703 *
2704 * On success the port is ready to use and the line number is returned.
2705 */
2706int serial8250_register_port(struct uart_port *port)
2707{
2708 struct uart_8250_port *uart;
2709 int ret = -ENOSPC;
2710
2711 if (port->uartclk == 0)
2712 return -EINVAL;
2713
f392ecfa 2714 mutex_lock(&serial_mutex);
1da177e4
LT		 2715
2716 uart = serial8250_find_match_or_unused(port);
2717 if (uart) {
2718 uart_remove_one_port(&serial8250_reg, &uart->port);
2719
2720 uart->port.iobase = port->iobase;
2721 uart->port.membase = port->membase;
2722 uart->port.irq = port->irq;
2723 uart->port.uartclk = port->uartclk;
2724 uart->port.fifosize = port->fifosize;
2725 uart->port.regshift = port->regshift;
2726 uart->port.iotype = port->iotype;
2727 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
2728 uart->port.mapbase = port->mapbase;
2729 if (port->dev)
2730 uart->port.dev = port->dev;
2731
2732 ret = uart_add_one_port(&serial8250_reg, &uart->port);
2733 if (ret == 0)
2734 ret = uart->port.line;
2735 }
f392ecfa 2736 mutex_unlock(&serial_mutex);
1da177e4
LT		 2737
2738 return ret;
2739}
2740EXPORT_SYMBOL(serial8250_register_port);
2741
2742/**
2743 * serial8250_unregister_port - remove a 16x50 serial port at runtime
2744 * @line: serial line number
2745 *
2746 * Remove one serial port. This may not be called from interrupt
2747 * context. We hand the port back to the our control.
2748 */
2749void serial8250_unregister_port(int line)
2750{
2751 struct uart_8250_port *uart = &serial8250_ports[line];
2752
f392ecfa 2753 mutex_lock(&serial_mutex);
1da177e4
LT		 2754 uart_remove_one_port(&serial8250_reg, &uart->port);
2755 if (serial8250_isa_devs) {
2756 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
2757 uart->port.type = PORT_UNKNOWN;
2758 uart->port.dev = &serial8250_isa_devs->dev;
2759 uart_add_one_port(&serial8250_reg, &uart->port);
2760 } else {
2761 uart->port.dev = NULL;
2762 }
f392ecfa 2763 mutex_unlock(&serial_mutex);
1da177e4
LT		 2764}
2765EXPORT_SYMBOL(serial8250_unregister_port);
2766
2767static int __init serial8250_init(void)
2768{
2769 int ret, i;
2770
a61c2d78
DJ		 2771 if (nr_uarts > UART_NR)
2772 nr_uarts = UART_NR;
2773
1da177e4 2774 printk(KERN_INFO "Serial: 8250/16550 driver $Revision: 1.90 $ "
a61c2d78 2775 "%d ports, IRQ sharing %sabled\n", nr_uarts,
1da177e4
LT		 2776 share_irqs ? "en" : "dis");
2777
2778 for (i = 0; i < NR_IRQS; i++)
2779 spin_lock_init(&irq_lists[i].lock);
2780
2781 ret = uart_register_driver(&serial8250_reg);
2782 if (ret)
2783 goto out;
2784
7493a314
DT		 2785 serial8250_isa_devs = platform_device_alloc("serial8250",
2786 PLAT8250_DEV_LEGACY);
2787 if (!serial8250_isa_devs) {
2788 ret = -ENOMEM;
bc965a7f 2789 goto unreg_uart_drv;
1da177e4
LT		 2790 }
2791
7493a314
DT		 2792 ret = platform_device_add(serial8250_isa_devs);
2793 if (ret)
2794 goto put_dev;
2795
1da177e4
LT		 2796 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
2797
bc965a7f
RK		 2798 ret = platform_driver_register(&serial8250_isa_driver);
2799 if (ret == 0)
2800 goto out;
1da177e4 2801
bc965a7f 2802 platform_device_del(serial8250_isa_devs);
7493a314
DT		 2803 put_dev:
2804 platform_device_put(serial8250_isa_devs);
7493a314 2805 unreg_uart_drv:
1da177e4
LT		 2806 uart_unregister_driver(&serial8250_reg);
2807 out:
2808 return ret;
2809}
2810
2811static void __exit serial8250_exit(void)
2812{
2813 struct platform_device *isa_dev = serial8250_isa_devs;
2814
2815 /*
2816 * This tells serial8250_unregister_port() not to re-register
2817 * the ports (thereby making serial8250_isa_driver permanently
2818 * in use.)
2819 */
2820 serial8250_isa_devs = NULL;
2821
3ae5eaec 2822 platform_driver_unregister(&serial8250_isa_driver);
1da177e4
LT		 2823 platform_device_unregister(isa_dev);
2824
2825 uart_unregister_driver(&serial8250_reg);
2826}
2827
2828module_init(serial8250_init);
2829module_exit(serial8250_exit);
2830
2831EXPORT_SYMBOL(serial8250_suspend_port);
2832EXPORT_SYMBOL(serial8250_resume_port);
2833
2834MODULE_LICENSE("GPL");
2835MODULE_DESCRIPTION("Generic 8250/16x50 serial driver $Revision: 1.90 $");
2836
2837module_param(share_irqs, uint, 0644);
2838MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
2839 " (unsafe)");
2840
a61c2d78
DJ		 2841module_param(nr_uarts, uint, 0644);
2842MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
2843
1da177e4
LT		 2844#ifdef CONFIG_SERIAL_8250_RSA
2845module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
2846MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
2847#endif
2848MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
Linux kernel - Deliverables
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