[MTD] Avoid 64-bit division in mtdconcat
[deliverable/linux.git] / drivers / serial / 8250.h
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1da177e4
LT
1/*
2 * linux/drivers/char/8250.h
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * $Id: 8250.h,v 1.8 2002/07/21 21:32:30 rmk Exp $
16 */
17
18#include <linux/config.h>
bc49a661 19#include <linux/serial_8250.h>
1da177e4
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20
21struct old_serial_port {
22 unsigned int uart;
23 unsigned int baud_base;
24 unsigned int port;
25 unsigned int irq;
26 unsigned int flags;
27 unsigned char hub6;
28 unsigned char io_type;
29 unsigned char *iomem_base;
30 unsigned short iomem_reg_shift;
31};
32
33/*
34 * This replaces serial_uart_config in include/linux/serial.h
35 */
36struct serial8250_config {
37 const char *name;
38 unsigned short fifo_size;
39 unsigned short tx_loadsz;
40 unsigned char fcr;
41 unsigned int flags;
42};
43
44#define UART_CAP_FIFO (1 << 8) /* UART has FIFO */
45#define UART_CAP_EFR (1 << 9) /* UART has EFR */
46#define UART_CAP_SLEEP (1 << 10) /* UART has IER sleep */
47#define UART_CAP_AFE (1 << 11) /* MCR-based hw flow control */
48#define UART_CAP_UUE (1 << 12) /* UART needs IER bit 6 set (Xscale) */
49
4ba5e35d 50#define UART_BUG_QUOT (1 << 0) /* UART has buggy quot LSB */
55d3b282 51#define UART_BUG_TXEN (1 << 1) /* UART has buggy TX IIR status */
21c614a7 52#define UART_BUG_NOMSR (1 << 2) /* UART has buggy MSR status bits (Au1x00) */
4ba5e35d 53
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54#define PROBE_RSA (1 << 0)
55#define PROBE_ANY (~0)
56
57#define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8)
58
59#ifdef CONFIG_SERIAL_8250_SHARE_IRQ
60#define SERIAL8250_SHARE_IRQS 1
61#else
62#define SERIAL8250_SHARE_IRQS 0
63#endif
64
65#if defined(__alpha__) && !defined(CONFIG_PCI)
66/*
67 * Digital did something really horribly wrong with the OUT1 and OUT2
68 * lines on at least some ALPHA's. The failure mode is that if either
69 * is cleared, the machine locks up with endless interrupts.
70 */
71#define ALPHA_KLUDGE_MCR (UART_MCR_OUT2 | UART_MCR_OUT1)
72#elif defined(CONFIG_SBC8560)
73/*
74 * WindRiver did something similarly broken on their SBC8560 board. The
75 * UART tristates its IRQ output while OUT2 is clear, but they pulled
76 * the interrupt line _up_ instead of down, so if we register the IRQ
77 * while the UART is in that state, we die in an IRQ storm. */
78#define ALPHA_KLUDGE_MCR (UART_MCR_OUT2)
79#else
80#define ALPHA_KLUDGE_MCR 0
81#endif
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